[Pkg-clamav-commits] [SCM] Debian repository for ClamAV branch, debian/unstable, updated. debian/0.95+dfsg-1-6156-g094ec9b
Török Edvin
edwin at clamav.net
Sun Apr 4 01:16:46 UTC 2010
The following commit has been merged in the debian/unstable branch:
commit b1249c5eb3f860ce6fea5a5e0f6c01be63da826e
Author: Török Edvin <edwin at clamav.net>
Date: Tue Jan 26 15:33:56 2010 +0200
Update autogenerated files after LLVM import.
diff --git a/libclamav/c++/ARMGenAsmWriter.inc b/libclamav/c++/ARMGenAsmWriter.inc
index 063f82d..c301a40 100644
--- a/libclamav/c++/ARMGenAsmWriter.inc
+++ b/libclamav/c++/ARMGenAsmWriter.inc
@@ -21,1552 +21,1554 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
0U, // IMPLICIT_DEF
0U, // SUBREG_TO_REG
0U, // COPY_TO_REGCLASS
- 1U, // ADCSSri
- 7U, // ADCSSrr
- 7U, // ADCSSrs
- 135299085U, // ADCri
- 135331853U, // ADCrr
- 270532621U, // ADCrs
- 137461777U, // ADDSri
- 137461777U, // ADDSrr
- 271679505U, // ADDSrs
- 135299094U, // ADDri
- 135331862U, // ADDrr
- 270532630U, // ADDrs
- 4194330U, // ADJCALLSTACKDOWN
- 4194350U, // ADJCALLSTACKUP
- 135299136U, // ANDri
- 135331904U, // ANDrr
- 270532672U, // ANDrs
- 407896132U, // ATOMIC_CMP_SWAP_I16
- 408944708U, // ATOMIC_CMP_SWAP_I32
- 409993284U, // ATOMIC_CMP_SWAP_I8
- 411041860U, // ATOMIC_LOAD_ADD_I16
- 412090436U, // ATOMIC_LOAD_ADD_I32
- 413139012U, // ATOMIC_LOAD_ADD_I8
- 414187588U, // ATOMIC_LOAD_AND_I16
- 415236164U, // ATOMIC_LOAD_AND_I32
- 416284740U, // ATOMIC_LOAD_AND_I8
- 417333316U, // ATOMIC_LOAD_NAND_I16
- 418381892U, // ATOMIC_LOAD_NAND_I32
- 419430468U, // ATOMIC_LOAD_NAND_I8
- 420479044U, // ATOMIC_LOAD_OR_I16
- 421527620U, // ATOMIC_LOAD_OR_I32
- 422576196U, // ATOMIC_LOAD_OR_I8
- 423624772U, // ATOMIC_LOAD_SUB_I16
- 424673348U, // ATOMIC_LOAD_SUB_I32
- 425721924U, // ATOMIC_LOAD_SUB_I8
- 426770500U, // ATOMIC_LOAD_XOR_I16
- 427819076U, // ATOMIC_LOAD_XOR_I32
- 428867652U, // ATOMIC_LOAD_XOR_I8
- 429916228U, // ATOMIC_SWAP_I16
- 430964804U, // ATOMIC_SWAP_I32
- 432013380U, // ATOMIC_SWAP_I8
- 4194373U, // B
- 137461832U, // BFC
- 135299148U, // BICri
- 135331916U, // BICrr
- 270532684U, // BICrs
- 536870992U, // BL
- 4194388U, // BLX
- 4194388U, // BLXr9
- 674365529U, // BL_pred
- 536870992U, // BLr9
- 674365529U, // BLr9_pred
- 4194396U, // BRIND
- 96U, // BR_JTadd
- 805306473U, // BR_JTm
- 30408818U, // BR_JTr
- 4194427U, // BX
- 970981515U, // BX_RET
- 4194427U, // BXr9
- 674332814U, // Bcc
- 1076986000U, // CLZ
- 1076986004U, // CMNri
- 1076986004U, // CMNrr
- 1211203732U, // CMNrs
- 1076986004U, // CMNzri
- 1076986004U, // CMNzrr
- 1211203732U, // CMNzrs
- 1076986008U, // CMPri
- 1076986008U, // CMPrr
- 1211203736U, // CMPrs
- 1076986008U, // CMPzri
- 1076986008U, // CMPzrr
- 1211203736U, // CMPzrs
- 1342177348U, // CONSTPOOL_ENTRY
- 135299228U, // EORri
- 135331996U, // EORrr
- 270532764U, // EORrs
- 1106411680U, // FCONSTD
- 1107460256U, // FCONSTS
- 974127269U, // FMSTAT
- 35651754U, // Int_MemBarrierV6
- 1476395191U, // Int_MemBarrierV7
- 36700330U, // Int_SyncBarrierV6
- 1476395195U, // Int_SyncBarrierV7
- 37748927U, // Int_eh_sjlj_setjmp
- 1613955273U, // LDM
- 1613955273U, // LDM_RET
- 1211203789U, // LDR
- 1211203793U, // LDRB
- 271679697U, // LDRB_POST
- 271679697U, // LDRB_PRE
- 271679702U, // LDRD
- 1076986075U, // LDREX
- 1076986081U, // LDREXB
- 137461992U, // LDREXD
- 1076986095U, // LDREXH
- 1211203830U, // LDRH
- 271679734U, // LDRH_POST
- 271679734U, // LDRH_PRE
- 1211203835U, // LDRSB
- 271679739U, // LDRSB_POST
- 271679739U, // LDRSB_PRE
- 1211203841U, // LDRSH
- 271679745U, // LDRSH_POST
- 271679745U, // LDRSH_PRE
- 271679693U, // LDR_POST
- 271679693U, // LDR_PRE
- 1211203789U, // LDRcp
- 1783628039U, // LEApcrel
- 1784676615U, // LEApcrelJT
- 1248854285U, // MLA
- 1211203857U, // MLS
- 137462037U, // MOVCCi
- 137462037U, // MOVCCr
- 271679765U, // MOVCCs
- 137462041U, // MOVTi16
- 1115914517U, // MOVi
- 1076986142U, // MOVi16
- 1076986133U, // MOVi2pieces
- 1076986142U, // MOVi32imm
- 1115685141U, // MOVr
- 1115685141U, // MOVrx
- 1249116437U, // MOVs
- 1076986147U, // MOVsra_flag
- 1076986147U, // MOVsrl_flag
- 135332136U, // MUL
- 1115914540U, // MVNi
- 1115685164U, // MVNr
- 1249116460U, // MVNs
- 135299376U, // ORRri
- 135332144U, // ORRrr
- 270532912U, // ORRrs
- 1922040116U, // PICADD
- 2057306420U, // PICLDR
- 2058354996U, // PICLDRB
- 2059403572U, // PICLDRH
- 2060452148U, // PICLDRSB
- 2061500724U, // PICLDRSH
- 2062549300U, // PICSTR
- 2063597876U, // PICSTRB
- 2064646452U, // PICSTRH
- 1211203894U, // PKHBT
- 1211203900U, // PKHTB
- 1076986178U, // REV
- 1076986182U, // REV16
- 1076986188U, // REVSH
- 137462098U, // RSBSri
- 271679826U, // RSBSrs
- 135299415U, // RSBri
- 270532951U, // RSBrs
- 347U, // RSCSri
- 347U, // RSCSrs
- 135299425U, // RSCri
- 270532961U, // RSCrs
- 357U, // SBCSSri
- 357U, // SBCSSrr
- 357U, // SBCSSrs
- 135299435U, // SBCri
- 135332203U, // SBCrr
- 270532971U, // SBCrs
- 1211203951U, // SBFX
- 1211203956U, // SMLABB
- 1211203963U, // SMLABT
- 1248854402U, // SMLAL
- 1211203976U, // SMLATB
- 1211203983U, // SMLATT
- 1211203990U, // SMLAWB
- 1211203997U, // SMLAWT
- 1211204004U, // SMMLA
- 1211204010U, // SMMLS
- 137462192U, // SMMUL
- 137462198U, // SMULBB
- 137462205U, // SMULBT
- 1248854468U, // SMULL
- 137462218U, // SMULTB
- 137462225U, // SMULTT
- 137462232U, // SMULWB
- 137462239U, // SMULWT
- 1613955558U, // STM
- 1211204074U, // STR
- 1211204078U, // STRB
- 271581678U, // STRB_POST
- 271581678U, // STRB_PRE
- 271679987U, // STRD
- 137462264U, // STREX
- 137462270U, // STREXB
- 1211204101U, // STREXD
- 137462284U, // STREXH
- 1211204115U, // STRH
- 271581715U, // STRH_POST
- 271581715U, // STRH_PRE
- 271581674U, // STR_POST
- 271581674U, // STR_PRE
- 137462296U, // SUBSri
- 137462296U, // SUBSrr
- 271680024U, // SUBSrs
- 135299613U, // SUBri
- 135332381U, // SUBrr
- 270533149U, // SUBrs
- 137462305U, // SXTABrr
- 1211204129U, // SXTABrr_rot
- 137462311U, // SXTAHrr
- 1211204135U, // SXTAHrr_rot
- 1076986413U, // SXTBr
- 137462317U, // SXTBr_rot
- 1076986418U, // SXTHr
- 137462322U, // SXTHr_rot
- 1076986423U, // TEQri
- 1076986423U, // TEQrr
- 1211204151U, // TEQrs
- 1476395579U, // TPsoft
- 1076986446U, // TSTri
- 1076986446U, // TSTrr
- 1211204174U, // TSTrs
- 1211204178U, // UBFX
- 1211204183U, // UMAAL
- 1248854621U, // UMLAL
- 1248854627U, // UMULL
- 137462377U, // UXTABrr
- 1211204201U, // UXTABrr_rot
- 137462383U, // UXTAHrr
- 1211204207U, // UXTAHrr_rot
- 1076986485U, // UXTB16r
- 137462389U, // UXTB16r_rot
- 1076986492U, // UXTBr
- 137462396U, // UXTBr_rot
- 1076986497U, // UXTHr
- 137462401U, // UXTHr_rot
- 1260454534U, // VABALsv2i64
- 1261503110U, // VABALsv4i32
- 1262551686U, // VABALsv8i16
- 1263600262U, // VABALuv2i64
- 1264648838U, // VABALuv4i32
- 1265697414U, // VABALuv8i16
- 1262551692U, // VABAsv16i8
- 1260454540U, // VABAsv2i32
- 1261503116U, // VABAsv4i16
- 1260454540U, // VABAsv4i32
- 1261503116U, // VABAsv8i16
- 1262551692U, // VABAsv8i8
- 1265697420U, // VABAuv16i8
- 1263600268U, // VABAuv2i32
- 1264648844U, // VABAuv4i16
- 1263600268U, // VABAuv4i32
- 1264648844U, // VABAuv8i16
- 1265697420U, // VABAuv8i8
- 186647185U, // VABDLsv2i64
- 187695761U, // VABDLsv4i32
- 188744337U, // VABDLsv8i16
- 189792913U, // VABDLuv2i64
- 190841489U, // VABDLuv4i32
- 191890065U, // VABDLuv8i16
- 167936663U, // VABDfd
- 167936663U, // VABDfq
- 188744343U, // VABDsv16i8
- 186647191U, // VABDsv2i32
- 187695767U, // VABDsv4i16
- 186647191U, // VABDsv4i32
- 187695767U, // VABDsv8i16
- 188744343U, // VABDsv8i8
- 191890071U, // VABDuv16i8
- 189792919U, // VABDuv2i32
- 190841495U, // VABDuv4i16
- 189792919U, // VABDuv4i32
- 190841495U, // VABDuv8i16
- 191890071U, // VABDuv8i8
- 1106412188U, // VABSD
- 1107460764U, // VABSS
- 1107460764U, // VABSfd
- 1107460764U, // VABSfd_sfp
- 1107460764U, // VABSfq
- 1128268444U, // VABSv16i8
- 1126171292U, // VABSv2i32
- 1127219868U, // VABSv4i16
- 1126171292U, // VABSv4i32
- 1127219868U, // VABSv8i16
- 1128268444U, // VABSv8i8
- 167936673U, // VACGEd
- 167936673U, // VACGEq
- 167936679U, // VACGTd
- 167936679U, // VACGTq
- 166888109U, // VADDD
- 192938674U, // VADDHNv2i32
- 193987250U, // VADDHNv4i16
- 195035826U, // VADDHNv8i8
- 186647225U, // VADDLsv2i64
- 187695801U, // VADDLsv4i32
- 188744377U, // VADDLsv8i16
- 189792953U, // VADDLuv2i64
- 190841529U, // VADDLuv4i32
- 191890105U, // VADDLuv8i16
- 167936685U, // VADDS
- 186647231U, // VADDWsv2i64
- 187695807U, // VADDWsv4i32
- 188744383U, // VADDWsv8i16
- 189792959U, // VADDWuv2i64
- 190841535U, // VADDWuv4i32
- 191890111U, // VADDWuv8i16
- 167936685U, // VADDfd
- 167936685U, // VADDfd_sfp
- 167936685U, // VADDfq
- 196084397U, // VADDv16i8
- 192938669U, // VADDv1i64
- 193987245U, // VADDv2i32
- 192938669U, // VADDv2i64
- 195035821U, // VADDv4i16
- 193987245U, // VADDv4i32
- 195035821U, // VADDv8i16
- 196084397U, // VADDv8i8
- 137462469U, // VANDd
- 137462469U, // VANDq
- 137462474U, // VBICd
- 137462474U, // VBICq
- 1211204303U, // VBSLd
- 1211204303U, // VBSLq
- 167936724U, // VCEQfd
- 167936724U, // VCEQfq
- 196084436U, // VCEQv16i8
- 193987284U, // VCEQv2i32
- 195035860U, // VCEQv4i16
- 193987284U, // VCEQv4i32
- 195035860U, // VCEQv8i16
- 196084436U, // VCEQv8i8
- 167936729U, // VCGEfd
- 167936729U, // VCGEfq
- 188744409U, // VCGEsv16i8
- 186647257U, // VCGEsv2i32
- 187695833U, // VCGEsv4i16
- 186647257U, // VCGEsv4i32
- 187695833U, // VCGEsv8i16
- 188744409U, // VCGEsv8i8
- 191890137U, // VCGEuv16i8
- 189792985U, // VCGEuv2i32
- 190841561U, // VCGEuv4i16
- 189792985U, // VCGEuv4i32
- 190841561U, // VCGEuv8i16
- 191890137U, // VCGEuv8i8
- 167936734U, // VCGTfd
- 167936734U, // VCGTfq
- 188744414U, // VCGTsv16i8
- 186647262U, // VCGTsv2i32
- 187695838U, // VCGTsv4i16
- 186647262U, // VCGTsv4i32
- 187695838U, // VCGTsv8i16
- 188744414U, // VCGTsv8i8
- 191890142U, // VCGTuv16i8
- 189792990U, // VCGTuv2i32
- 190841566U, // VCGTuv4i16
- 189792990U, // VCGTuv4i32
- 190841566U, // VCGTuv8i16
- 191890142U, // VCGTuv8i8
- 1128268515U, // VCLSv16i8
- 1126171363U, // VCLSv2i32
- 1127219939U, // VCLSv4i16
- 1126171363U, // VCLSv4i32
- 1127219939U, // VCLSv8i16
- 1128268515U, // VCLSv8i8
- 1135608552U, // VCLZv16i8
- 1133511400U, // VCLZv2i32
- 1134559976U, // VCLZv4i16
- 1133511400U, // VCLZv4i32
- 1134559976U, // VCLZv8i16
- 1135608552U, // VCLZv8i8
- 1106412269U, // VCMPED
- 1107460845U, // VCMPES
- 703890157U, // VCMPEZD
- 704938733U, // VCMPEZS
- 1136755443U, // VCNTd
- 1136755443U, // VCNTq
- 1137705720U, // VCVTDS
- 1138754296U, // VCVTSD
- 1140130552U, // VCVTf2sd
- 1140130552U, // VCVTf2sd_sfp
- 1140130552U, // VCVTf2sq
- 1141179128U, // VCVTf2ud
- 1141179128U, // VCVTf2ud_sfp
- 1141179128U, // VCVTf2uq
- 200442616U, // VCVTf2xsd
- 200442616U, // VCVTf2xsq
- 201491192U, // VCVTf2xud
- 201491192U, // VCVTf2xuq
- 1142227704U, // VCVTs2fd
- 1142227704U, // VCVTs2fd_sfp
- 1142227704U, // VCVTs2fq
- 1143276280U, // VCVTu2fd
- 1143276280U, // VCVTu2fd_sfp
- 1143276280U, // VCVTu2fq
- 202539768U, // VCVTxs2fd
- 202539768U, // VCVTxs2fq
- 203588344U, // VCVTxu2fd
- 203588344U, // VCVTxu2fq
- 166888189U, // VDIVD
- 167936765U, // VDIVS
- 1144095490U, // VDUP16d
- 1144095490U, // VDUP16q
- 1145144066U, // VDUP32d
- 1145144066U, // VDUP32q
- 1136755458U, // VDUP8d
- 1136755458U, // VDUP8q
- 204571394U, // VDUPLN16d
- 204571394U, // VDUPLN16q
- 205619970U, // VDUPLN32d
- 205619970U, // VDUPLN32q
- 197231362U, // VDUPLN8d
- 197231362U, // VDUPLN8q
- 205619970U, // VDUPLNfd
- 205619970U, // VDUPLNfq
- 1145144066U, // VDUPfd
- 1145144066U, // VDUPfdf
- 1145144066U, // VDUPfq
- 1145144066U, // VDUPfqf
- 137462535U, // VEORd
- 137462535U, // VEORq
- 1278313228U, // VEXTd16
- 1279361804U, // VEXTd32
- 1270973196U, // VEXTd8
- 1279361804U, // VEXTdf
- 1278313228U, // VEXTq16
- 1279361804U, // VEXTq32
- 1270973196U, // VEXTq8
- 1279361804U, // VEXTqf
- 205619360U, // VGETLNi32
- 187695264U, // VGETLNs16
- 188743840U, // VGETLNs8
- 190840992U, // VGETLNu16
- 191889568U, // VGETLNu8
- 188744465U, // VHADDsv16i8
- 186647313U, // VHADDsv2i32
- 187695889U, // VHADDsv4i16
- 186647313U, // VHADDsv4i32
- 187695889U, // VHADDsv8i16
- 188744465U, // VHADDsv8i8
- 191890193U, // VHADDuv16i8
- 189793041U, // VHADDuv2i32
- 190841617U, // VHADDuv4i16
- 189793041U, // VHADDuv4i32
- 190841617U, // VHADDuv8i16
- 191890193U, // VHADDuv8i8
- 188744471U, // VHSUBsv16i8
- 186647319U, // VHSUBsv2i32
- 187695895U, // VHSUBsv4i16
- 186647319U, // VHSUBsv4i32
- 187695895U, // VHSUBsv8i16
- 188744471U, // VHSUBsv8i8
- 191890199U, // VHSUBuv16i8
- 189793047U, // VHSUBuv2i32
- 190841623U, // VHSUBuv4i16
- 189793047U, // VHSUBuv4i32
- 190841623U, // VHSUBuv8i16
- 191890199U, // VHSUBuv8i8
- 340886301U, // VLD1d16
- 341934877U, // VLD1d32
- 342983453U, // VLD1d64
- 344032029U, // VLD1d8
- 341934877U, // VLD1df
- 339051293U, // VLD1q16
- 340099869U, // VLD1q32
- 345342749U, // VLD1q64
- 331711261U, // VLD1q8
- 340099869U, // VLD1qf
- 2219934498U, // VLD2LNd16
- 2220983074U, // VLD2LNd32
- 2223080226U, // VLD2LNd8
- 2219934498U, // VLD2LNq16a
- 2219934498U, // VLD2LNq16b
- 2220983074U, // VLD2LNq32a
- 2220983074U, // VLD2LNq32b
- 2354152226U, // VLD2d16
- 2355200802U, // VLD2d32
- 2356249373U, // VLD2d64
- 2357297954U, // VLD2d8
- 2488369954U, // VLD2q16
- 2489418530U, // VLD2q32
- 2491515682U, // VLD2q8
- 2622587687U, // VLD3LNd16
- 2623636263U, // VLD3LNd32
- 2625733415U, // VLD3LNd8
- 2622587687U, // VLD3LNq16a
- 2622587687U, // VLD3LNq16b
- 2623636263U, // VLD3LNq32a
- 2623636263U, // VLD3LNq32b
- 2756805415U, // VLD3d16
- 2757853991U, // VLD3d32
- 2758902557U, // VLD3d64
- 2759951143U, // VLD3d8
- 2488369959U, // VLD3q16a
- 2488369959U, // VLD3q16b
- 2489418535U, // VLD3q32a
- 2489418535U, // VLD3q32b
- 2491515687U, // VLD3q8a
- 2491515687U, // VLD3q8b
- 2891023148U, // VLD4LNd16
- 2892071724U, // VLD4LNd32
- 2894168876U, // VLD4LNd8
- 2891023148U, // VLD4LNq16a
- 2891023148U, // VLD4LNq16b
- 2892071724U, // VLD4LNq32a
- 2892071724U, // VLD4LNq32b
- 2488369964U, // VLD4d16
- 2489418540U, // VLD4d32
- 2490467101U, // VLD4d64
- 2491515692U, // VLD4d8
- 2219934508U, // VLD4q16a
- 2219934508U, // VLD4q16b
- 2220983084U, // VLD4q32a
- 2220983084U, // VLD4q32b
- 2223080236U, // VLD4q8a
- 2223080236U, // VLD4q8b
- 2952790833U, // VLDMD
- 2952790833U, // VLDMS
- 210862902U, // VLDRD
- 137757499U, // VLDRQ
- 205620022U, // VLDRS
- 167936834U, // VMAXfd
- 167936834U, // VMAXfq
- 188744514U, // VMAXsv16i8
- 186647362U, // VMAXsv2i32
- 187695938U, // VMAXsv4i16
- 186647362U, // VMAXsv4i32
- 187695938U, // VMAXsv8i16
- 188744514U, // VMAXsv8i8
- 191890242U, // VMAXuv16i8
- 189793090U, // VMAXuv2i32
- 190841666U, // VMAXuv4i16
- 189793090U, // VMAXuv4i32
- 190841666U, // VMAXuv8i16
- 191890242U, // VMAXuv8i8
- 167936839U, // VMINfd
- 167936839U, // VMINfq
- 188744519U, // VMINsv16i8
- 186647367U, // VMINsv2i32
- 187695943U, // VMINsv4i16
- 186647367U, // VMINsv4i32
- 187695943U, // VMINsv8i16
- 188744519U, // VMINsv8i8
- 191890247U, // VMINuv16i8
- 189793095U, // VMINuv2i32
- 190841671U, // VMINuv4i16
- 189793095U, // VMINuv4i32
- 190841671U, // VMINuv8i16
- 191890247U, // VMINuv8i8
- 1240630092U, // VMLAD
- 320930641U, // VMLALslsv2i32
- 321979217U, // VMLALslsv4i16
- 324076369U, // VMLALsluv2i32
- 325124945U, // VMLALsluv4i16
- 1260454737U, // VMLALsv2i64
- 1261503313U, // VMLALsv4i32
- 1262551889U, // VMLALsv8i16
- 1263600465U, // VMLALuv2i64
- 1264649041U, // VMLALuv4i32
- 1265697617U, // VMLALuv8i16
- 1241678668U, // VMLAS
- 1241678668U, // VMLAfd
- 1241678668U, // VMLAfq
- 302154572U, // VMLAslfd
- 302154572U, // VMLAslfq
- 328270668U, // VMLAslv2i32
- 329319244U, // VMLAslv4i16
- 328270668U, // VMLAslv4i32
- 329319244U, // VMLAslv8i16
- 1269891916U, // VMLAv16i8
- 1267794764U, // VMLAv2i32
- 1268843340U, // VMLAv4i16
- 1267794764U, // VMLAv4i32
- 1268843340U, // VMLAv8i16
- 1269891916U, // VMLAv8i8
- 1240630103U, // VMLSD
- 320930652U, // VMLSLslsv2i32
- 321979228U, // VMLSLslsv4i16
- 324076380U, // VMLSLsluv2i32
- 325124956U, // VMLSLsluv4i16
- 1260454748U, // VMLSLsv2i64
- 1261503324U, // VMLSLsv4i32
- 1262551900U, // VMLSLsv8i16
- 1263600476U, // VMLSLuv2i64
- 1264649052U, // VMLSLuv4i32
- 1265697628U, // VMLSLuv8i16
- 1241678679U, // VMLSS
- 1241678679U, // VMLSfd
- 1241678679U, // VMLSfq
- 302154583U, // VMLSslfd
- 302154583U, // VMLSslfq
- 328270679U, // VMLSslv2i32
- 329319255U, // VMLSslv4i16
- 328270679U, // VMLSslv4i32
- 329319255U, // VMLSslv8i16
- 1269891927U, // VMLSv16i8
- 1267794775U, // VMLSv2i32
- 1268843351U, // VMLSv4i16
- 1267794775U, // VMLSv4i32
- 1268843351U, // VMLSv8i16
- 1269891927U, // VMLSv8i8
- 1106411680U, // VMOVD
- 137461920U, // VMOVDRR
- 166887584U, // VMOVDcc
- 1076986016U, // VMOVDneon
- 1126171490U, // VMOVLsv2i64
- 1127220066U, // VMOVLsv4i32
- 1128268642U, // VMOVLsv8i16
- 1129317218U, // VMOVLuv2i64
- 1130365794U, // VMOVLuv4i32
- 1131414370U, // VMOVLuv8i16
- 1132462952U, // VMOVNv2i32
- 1133511528U, // VMOVNv4i16
- 1134560104U, // VMOVNv8i8
- 1076986016U, // VMOVQ
- 137461920U, // VMOVRRD
- 1076986016U, // VMOVRS
- 1107460256U, // VMOVS
- 1076986016U, // VMOVSR
- 167936160U, // VMOVScc
- 1136033952U, // VMOVv16i8
- 1132920992U, // VMOVv1i64
- 1134002336U, // VMOVv2i32
- 1132920992U, // VMOVv2i64
- 1135083680U, // VMOVv4i16
- 1134002336U, // VMOVv4i32
- 1135083680U, // VMOVv8i16
- 1136033952U, // VMOVv8i8
- 166888302U, // VMULD
- 211813235U, // VMULLp
- 1260389235U, // VMULLslsv2i32
- 1261437811U, // VMULLslsv4i16
- 1263534963U, // VMULLsluv2i32
- 1264583539U, // VMULLsluv4i16
- 186647411U, // VMULLsv2i64
- 187695987U, // VMULLsv4i32
- 188744563U, // VMULLsv8i16
- 189793139U, // VMULLuv2i64
- 190841715U, // VMULLuv4i32
- 191890291U, // VMULLuv8i16
- 167936878U, // VMULS
- 167936878U, // VMULfd
- 167936878U, // VMULfd_sfp
- 167936878U, // VMULfq
- 211813230U, // VMULpd
- 211813230U, // VMULpq
- 1241678702U, // VMULslfd
- 1241678702U, // VMULslfq
- 1267729262U, // VMULslv2i32
- 1268777838U, // VMULslv4i16
- 1267729262U, // VMULslv4i32
- 1268777838U, // VMULslv8i16
- 196084590U, // VMULv16i8
- 193987438U, // VMULv2i32
- 195036014U, // VMULv4i16
- 193987438U, // VMULv4i32
- 195036014U, // VMULv8i16
- 196084590U, // VMULv8i8
- 1076986745U, // VMVNd
- 1076986745U, // VMVNq
- 1106412414U, // VNEGD
- 166888318U, // VNEGDcc
- 1107460990U, // VNEGS
- 167936894U, // VNEGScc
- 1107460990U, // VNEGf32d
- 1107460990U, // VNEGf32d_sfp
- 1107460990U, // VNEGf32q
- 1127220094U, // VNEGs16d
- 1127220094U, // VNEGs16q
- 1126171518U, // VNEGs32d
- 1126171518U, // VNEGs32q
- 1128268670U, // VNEGs8d
- 1128268670U, // VNEGs8q
- 1240630147U, // VNMLAD
- 1241678723U, // VNMLAS
- 1240630153U, // VNMLSD
- 1241678729U, // VNMLSS
- 166888335U, // VNMULD
- 167936911U, // VNMULS
- 137462677U, // VORNd
- 137462677U, // VORNq
- 137462682U, // VORRd
- 137462682U, // VORRq
- 188810143U, // VPADALsv16i8
- 186712991U, // VPADALsv2i32
- 187761567U, // VPADALsv4i16
- 186712991U, // VPADALsv4i32
- 187761567U, // VPADALsv8i16
- 188810143U, // VPADALsv8i8
- 191955871U, // VPADALuv16i8
- 189858719U, // VPADALuv2i32
- 190907295U, // VPADALuv4i16
- 189858719U, // VPADALuv4i32
- 190907295U, // VPADALuv8i16
- 191955871U, // VPADALuv8i8
- 1128268710U, // VPADDLsv16i8
- 1126171558U, // VPADDLsv2i32
- 1127220134U, // VPADDLsv4i16
- 1126171558U, // VPADDLsv4i32
- 1127220134U, // VPADDLsv8i16
- 1128268710U, // VPADDLsv8i8
- 1131414438U, // VPADDLuv16i8
- 1129317286U, // VPADDLuv2i32
- 1130365862U, // VPADDLuv4i16
- 1129317286U, // VPADDLuv4i32
- 1130365862U, // VPADDLuv8i16
- 1131414438U, // VPADDLuv8i8
- 167936941U, // VPADDf
- 195036077U, // VPADDi16
- 193987501U, // VPADDi32
- 196084653U, // VPADDi8
- 167936947U, // VPMAXf
- 187696051U, // VPMAXs16
- 186647475U, // VPMAXs32
- 188744627U, // VPMAXs8
- 190841779U, // VPMAXu16
- 189793203U, // VPMAXu32
- 191890355U, // VPMAXu8
- 167936953U, // VPMINf
- 187696057U, // VPMINs16
- 186647481U, // VPMINs32
- 188744633U, // VPMINs8
- 190841785U, // VPMINu16
- 189793209U, // VPMINu32
- 191890361U, // VPMINu8
- 1128268735U, // VQABSv16i8
- 1126171583U, // VQABSv2i32
- 1127220159U, // VQABSv4i16
- 1126171583U, // VQABSv4i32
- 1127220159U, // VQABSv8i16
- 1128268735U, // VQABSv8i8
- 188744645U, // VQADDsv16i8
- 212861893U, // VQADDsv1i64
- 186647493U, // VQADDsv2i32
- 212861893U, // VQADDsv2i64
- 187696069U, // VQADDsv4i16
- 186647493U, // VQADDsv4i32
- 187696069U, // VQADDsv8i16
- 188744645U, // VQADDsv8i8
- 191890373U, // VQADDuv16i8
- 213910469U, // VQADDuv1i64
- 189793221U, // VQADDuv2i32
- 213910469U, // VQADDuv2i64
- 190841797U, // VQADDuv4i16
- 189793221U, // VQADDuv4i32
- 190841797U, // VQADDuv8i16
- 191890373U, // VQADDuv8i8
- 320930763U, // VQDMLALslv2i32
- 321979339U, // VQDMLALslv4i16
- 1260454859U, // VQDMLALv2i64
- 1261503435U, // VQDMLALv4i32
- 320930771U, // VQDMLSLslv2i32
- 321979347U, // VQDMLSLslv4i16
- 1260454867U, // VQDMLSLv2i64
- 1261503443U, // VQDMLSLv4i32
- 1260389339U, // VQDMULHslv2i32
- 1261437915U, // VQDMULHslv4i16
- 1260389339U, // VQDMULHslv4i32
- 1261437915U, // VQDMULHslv8i16
- 186647515U, // VQDMULHv2i32
- 187696091U, // VQDMULHv4i16
- 186647515U, // VQDMULHv4i32
- 187696091U, // VQDMULHv8i16
- 1260389347U, // VQDMULLslv2i32
- 1261437923U, // VQDMULLslv4i16
- 186647523U, // VQDMULLv2i64
- 187696099U, // VQDMULLv4i32
- 1152386027U, // VQMOVNsuv2i32
- 1126171627U, // VQMOVNsuv4i16
- 1127220203U, // VQMOVNsuv8i8
- 1152386035U, // VQMOVNsv2i32
- 1126171635U, // VQMOVNsv4i16
- 1127220211U, // VQMOVNsv8i8
- 1153434611U, // VQMOVNuv2i32
- 1129317363U, // VQMOVNuv4i16
- 1130365939U, // VQMOVNuv8i8
- 1128268794U, // VQNEGv16i8
- 1126171642U, // VQNEGv2i32
- 1127220218U, // VQNEGv4i16
- 1126171642U, // VQNEGv4i32
- 1127220218U, // VQNEGv8i16
- 1128268794U, // VQNEGv8i8
- 1260389376U, // VQRDMULHslv2i32
- 1261437952U, // VQRDMULHslv4i16
- 1260389376U, // VQRDMULHslv4i32
- 1261437952U, // VQRDMULHslv8i16
- 186647552U, // VQRDMULHv2i32
- 187696128U, // VQRDMULHv4i16
- 186647552U, // VQRDMULHv4i32
- 187696128U, // VQRDMULHv8i16
- 188744713U, // VQRSHLsv16i8
- 212861961U, // VQRSHLsv1i64
- 186647561U, // VQRSHLsv2i32
- 212861961U, // VQRSHLsv2i64
- 187696137U, // VQRSHLsv4i16
- 186647561U, // VQRSHLsv4i32
- 187696137U, // VQRSHLsv8i16
- 188744713U, // VQRSHLsv8i8
- 191890441U, // VQRSHLuv16i8
- 213910537U, // VQRSHLuv1i64
- 189793289U, // VQRSHLuv2i32
- 213910537U, // VQRSHLuv2i64
- 190841865U, // VQRSHLuv4i16
- 189793289U, // VQRSHLuv4i32
- 190841865U, // VQRSHLuv8i16
- 191890441U, // VQRSHLuv8i8
- 212861968U, // VQRSHRNsv2i32
- 186647568U, // VQRSHRNsv4i16
- 187696144U, // VQRSHRNsv8i8
- 213910544U, // VQRSHRNuv2i32
- 189793296U, // VQRSHRNuv4i16
- 190841872U, // VQRSHRNuv8i8
- 212861976U, // VQRSHRUNv2i32
- 186647576U, // VQRSHRUNv4i16
- 187696152U, // VQRSHRUNv8i8
- 188744737U, // VQSHLsiv16i8
- 212861985U, // VQSHLsiv1i64
- 186647585U, // VQSHLsiv2i32
- 212861985U, // VQSHLsiv2i64
- 187696161U, // VQSHLsiv4i16
- 186647585U, // VQSHLsiv4i32
- 187696161U, // VQSHLsiv8i16
- 188744737U, // VQSHLsiv8i8
- 188744743U, // VQSHLsuv16i8
- 212861991U, // VQSHLsuv1i64
- 186647591U, // VQSHLsuv2i32
- 212861991U, // VQSHLsuv2i64
- 187696167U, // VQSHLsuv4i16
- 186647591U, // VQSHLsuv4i32
- 187696167U, // VQSHLsuv8i16
- 188744743U, // VQSHLsuv8i8
- 188744737U, // VQSHLsv16i8
- 212861985U, // VQSHLsv1i64
- 186647585U, // VQSHLsv2i32
- 212861985U, // VQSHLsv2i64
- 187696161U, // VQSHLsv4i16
- 186647585U, // VQSHLsv4i32
- 187696161U, // VQSHLsv8i16
- 188744737U, // VQSHLsv8i8
- 191890465U, // VQSHLuiv16i8
- 213910561U, // VQSHLuiv1i64
- 189793313U, // VQSHLuiv2i32
- 213910561U, // VQSHLuiv2i64
- 190841889U, // VQSHLuiv4i16
- 189793313U, // VQSHLuiv4i32
- 190841889U, // VQSHLuiv8i16
- 191890465U, // VQSHLuiv8i8
- 191890465U, // VQSHLuv16i8
- 213910561U, // VQSHLuv1i64
- 189793313U, // VQSHLuv2i32
- 213910561U, // VQSHLuv2i64
- 190841889U, // VQSHLuv4i16
- 189793313U, // VQSHLuv4i32
- 190841889U, // VQSHLuv8i16
- 191890465U, // VQSHLuv8i8
- 212861998U, // VQSHRNsv2i32
- 186647598U, // VQSHRNsv4i16
- 187696174U, // VQSHRNsv8i8
- 213910574U, // VQSHRNuv2i32
- 189793326U, // VQSHRNuv4i16
- 190841902U, // VQSHRNuv8i8
- 212862005U, // VQSHRUNv2i32
- 186647605U, // VQSHRUNv4i16
- 187696181U, // VQSHRUNv8i8
- 188744765U, // VQSUBsv16i8
- 212862013U, // VQSUBsv1i64
- 186647613U, // VQSUBsv2i32
- 212862013U, // VQSUBsv2i64
- 187696189U, // VQSUBsv4i16
- 186647613U, // VQSUBsv4i32
- 187696189U, // VQSUBsv8i16
- 188744765U, // VQSUBsv8i8
- 191890493U, // VQSUBuv16i8
- 213910589U, // VQSUBuv1i64
- 189793341U, // VQSUBuv2i32
- 213910589U, // VQSUBuv2i64
- 190841917U, // VQSUBuv4i16
- 189793341U, // VQSUBuv4i32
- 190841917U, // VQSUBuv8i16
- 191890493U, // VQSUBuv8i8
- 192939075U, // VRADDHNv2i32
- 193987651U, // VRADDHNv4i16
- 195036227U, // VRADDHNv8i8
- 1129317451U, // VRECPEd
- 1107461195U, // VRECPEfd
- 1107461195U, // VRECPEfq
- 1129317451U, // VRECPEq
- 167937106U, // VRECPSfd
- 167937106U, // VRECPSfq
- 1136755801U, // VREV16d8
- 1136755801U, // VREV16q8
- 1144095840U, // VREV32d16
- 1136755808U, // VREV32d8
- 1144095840U, // VREV32q16
- 1136755808U, // VREV32q8
- 1144095847U, // VREV64d16
- 1145144423U, // VREV64d32
- 1136755815U, // VREV64d8
- 1145144423U, // VREV64df
- 1144095847U, // VREV64q16
- 1145144423U, // VREV64q32
- 1136755815U, // VREV64q8
- 1145144423U, // VREV64qf
- 188744814U, // VRHADDsv16i8
- 186647662U, // VRHADDsv2i32
- 187696238U, // VRHADDsv4i16
- 186647662U, // VRHADDsv4i32
- 187696238U, // VRHADDsv8i16
- 188744814U, // VRHADDsv8i8
- 191890542U, // VRHADDuv16i8
- 189793390U, // VRHADDuv2i32
- 190841966U, // VRHADDuv4i16
- 189793390U, // VRHADDuv4i32
- 190841966U, // VRHADDuv8i16
- 191890542U, // VRHADDuv8i8
- 188744821U, // VRSHLsv16i8
- 212862069U, // VRSHLsv1i64
- 186647669U, // VRSHLsv2i32
- 212862069U, // VRSHLsv2i64
- 187696245U, // VRSHLsv4i16
- 186647669U, // VRSHLsv4i32
- 187696245U, // VRSHLsv8i16
- 188744821U, // VRSHLsv8i8
- 191890549U, // VRSHLuv16i8
- 213910645U, // VRSHLuv1i64
- 189793397U, // VRSHLuv2i32
- 213910645U, // VRSHLuv2i64
- 190841973U, // VRSHLuv4i16
- 189793397U, // VRSHLuv4i32
- 190841973U, // VRSHLuv8i16
- 191890549U, // VRSHLuv8i8
- 192939131U, // VRSHRNv2i32
- 193987707U, // VRSHRNv4i16
- 195036283U, // VRSHRNv8i8
- 188744834U, // VRSHRsv16i8
- 212862082U, // VRSHRsv1i64
- 186647682U, // VRSHRsv2i32
- 212862082U, // VRSHRsv2i64
- 187696258U, // VRSHRsv4i16
- 186647682U, // VRSHRsv4i32
- 187696258U, // VRSHRsv8i16
- 188744834U, // VRSHRsv8i8
- 191890562U, // VRSHRuv16i8
- 213910658U, // VRSHRuv1i64
- 189793410U, // VRSHRuv2i32
- 213910658U, // VRSHRuv2i64
- 190841986U, // VRSHRuv4i16
- 189793410U, // VRSHRuv4i32
- 190841986U, // VRSHRuv8i16
- 191890562U, // VRSHRuv8i8
- 1129317512U, // VRSQRTEd
- 1107461256U, // VRSQRTEfd
- 1107461256U, // VRSQRTEfq
- 1129317512U, // VRSQRTEq
- 167937168U, // VRSQRTSfd
- 167937168U, // VRSQRTSfq
- 1262552216U, // VRSRAsv16i8
- 1286669464U, // VRSRAsv1i64
- 1260455064U, // VRSRAsv2i32
- 1286669464U, // VRSRAsv2i64
- 1261503640U, // VRSRAsv4i16
- 1260455064U, // VRSRAsv4i32
- 1261503640U, // VRSRAsv8i16
- 1262552216U, // VRSRAsv8i8
- 1265697944U, // VRSRAuv16i8
- 1287718040U, // VRSRAuv1i64
- 1263600792U, // VRSRAuv2i32
- 1287718040U, // VRSRAuv2i64
- 1264649368U, // VRSRAuv4i16
- 1263600792U, // VRSRAuv4i32
- 1264649368U, // VRSRAuv8i16
- 1265697944U, // VRSRAuv8i8
- 192939166U, // VRSUBHNv2i32
- 193987742U, // VRSUBHNv4i16
- 195036318U, // VRSUBHNv8i8
- 1278312608U, // VSETLNi16
- 1279361184U, // VSETLNi32
- 1270972576U, // VSETLNi8
- 195036326U, // VSHLLi16
- 193987750U, // VSHLLi32
- 196084902U, // VSHLLi8
- 186647718U, // VSHLLsv2i64
- 187696294U, // VSHLLsv4i32
- 188744870U, // VSHLLsv8i16
- 189793446U, // VSHLLuv2i64
- 190842022U, // VSHLLuv4i32
- 191890598U, // VSHLLuv8i16
- 196084908U, // VSHLiv16i8
- 192939180U, // VSHLiv1i64
- 193987756U, // VSHLiv2i32
- 192939180U, // VSHLiv2i64
- 195036332U, // VSHLiv4i16
- 193987756U, // VSHLiv4i32
- 195036332U, // VSHLiv8i16
- 196084908U, // VSHLiv8i8
- 188744876U, // VSHLsv16i8
- 212862124U, // VSHLsv1i64
- 186647724U, // VSHLsv2i32
- 212862124U, // VSHLsv2i64
- 187696300U, // VSHLsv4i16
- 186647724U, // VSHLsv4i32
- 187696300U, // VSHLsv8i16
- 188744876U, // VSHLsv8i8
- 191890604U, // VSHLuv16i8
- 213910700U, // VSHLuv1i64
- 189793452U, // VSHLuv2i32
- 213910700U, // VSHLuv2i64
- 190842028U, // VSHLuv4i16
- 189793452U, // VSHLuv4i32
- 190842028U, // VSHLuv8i16
- 191890604U, // VSHLuv8i8
- 192939185U, // VSHRNv2i32
- 193987761U, // VSHRNv4i16
- 195036337U, // VSHRNv8i8
- 188744887U, // VSHRsv16i8
- 212862135U, // VSHRsv1i64
- 186647735U, // VSHRsv2i32
- 212862135U, // VSHRsv2i64
- 187696311U, // VSHRsv4i16
- 186647735U, // VSHRsv4i32
- 187696311U, // VSHRsv8i16
- 188744887U, // VSHRsv8i8
- 191890615U, // VSHRuv16i8
- 213910711U, // VSHRuv1i64
- 189793463U, // VSHRuv2i32
- 213910711U, // VSHRuv2i64
- 190842039U, // VSHRuv4i16
- 189793463U, // VSHRuv4i32
- 190842039U, // VSHRuv8i16
- 191890615U, // VSHRuv8i8
- 1154482936U, // VSITOD
- 1142227704U, // VSITOS
- 1270973628U, // VSLIv16i8
- 1284605116U, // VSLIv1i64
- 1279362236U, // VSLIv2i32
- 1284605116U, // VSLIv2i64
- 1278313660U, // VSLIv4i16
- 1279362236U, // VSLIv4i32
- 1278313660U, // VSLIv8i16
- 1270973628U, // VSLIv8i8
- 1106412737U, // VSQRTD
- 1107461313U, // VSQRTS
- 1262552263U, // VSRAsv16i8
- 1286669511U, // VSRAsv1i64
- 1260455111U, // VSRAsv2i32
- 1286669511U, // VSRAsv2i64
- 1261503687U, // VSRAsv4i16
- 1260455111U, // VSRAsv4i32
- 1261503687U, // VSRAsv8i16
- 1262552263U, // VSRAsv8i8
- 1265697991U, // VSRAuv16i8
- 1287718087U, // VSRAuv1i64
- 1263600839U, // VSRAuv2i32
- 1287718087U, // VSRAuv2i64
- 1264649415U, // VSRAuv4i16
- 1263600839U, // VSRAuv4i32
- 1264649415U, // VSRAuv8i16
- 1265697991U, // VSRAuv8i8
- 1270973644U, // VSRIv16i8
- 1284605132U, // VSRIv1i64
- 1279362252U, // VSRIv2i32
- 1284605132U, // VSRIv2i64
- 1278313676U, // VSRIv4i16
- 1279362252U, // VSRIv4i32
- 1278313676U, // VSRIv8i16
- 1270973644U, // VSRIv8i8
- 341345489U, // VST1d16
- 342394065U, // VST1d32
- 343442641U, // VST1d64
- 344491217U, // VST1d8
- 342394065U, // VST1df
- 339281105U, // VST1q16
- 340329681U, // VST1q32
- 345572561U, // VST1q64
- 331941073U, // VST1q8
- 340329681U, // VST1qf
- 2757264598U, // VST2LNd16
- 2758313174U, // VST2LNd32
- 2760410326U, // VST2LNd8
- 2757264598U, // VST2LNq16a
- 2757264598U, // VST2LNq16b
- 2758313174U, // VST2LNq32a
- 2758313174U, // VST2LNq32b
- 2354611414U, // VST2d16
- 2355659990U, // VST2d32
- 2356708561U, // VST2d64
- 2357757142U, // VST2d8
- 2488829142U, // VST2q16
- 2489877718U, // VST2q32
- 2491974870U, // VST2q8
- 2488829147U, // VST3LNd16
- 2489877723U, // VST3LNd32
- 2491974875U, // VST3LNd8
- 2488829147U, // VST3LNq16a
- 2488829147U, // VST3LNq16b
- 2489877723U, // VST3LNq32a
- 2489877723U, // VST3LNq32b
- 2757264603U, // VST3d16
- 2758313179U, // VST3d32
- 2759361745U, // VST3d64
- 2760410331U, // VST3d8
- 2488894683U, // VST3q16a
- 2488894683U, // VST3q16b
- 2489943259U, // VST3q32a
- 2489943259U, // VST3q32b
- 2492040411U, // VST3q8a
- 2492040411U, // VST3q8b
- 2220393696U, // VST4LNd16
- 2221442272U, // VST4LNd32
- 2223539424U, // VST4LNd8
- 2220393696U, // VST4LNq16a
- 2220393696U, // VST4LNq16b
- 2221442272U, // VST4LNq32a
- 2221442272U, // VST4LNq32b
- 2488829152U, // VST4d16
- 2489877728U, // VST4d32
- 2490926289U, // VST4d64
- 2491974880U, // VST4d8
- 2220459232U, // VST4q16a
- 2220459232U, // VST4q16b
- 2221507808U, // VST4q32a
- 2221507808U, // VST4q32b
- 2223604960U, // VST4q8a
- 2223604960U, // VST4q8b
- 2952791269U, // VSTMD
- 2952791269U, // VSTMS
- 210863338U, // VSTRD
- 137757935U, // VSTRQ
- 205620458U, // VSTRS
- 166888694U, // VSUBD
- 192939259U, // VSUBHNv2i32
- 193987835U, // VSUBHNv4i16
- 195036411U, // VSUBHNv8i8
- 186647810U, // VSUBLsv2i64
- 187696386U, // VSUBLsv4i32
- 188744962U, // VSUBLsv8i16
- 189793538U, // VSUBLuv2i64
- 190842114U, // VSUBLuv4i32
- 191890690U, // VSUBLuv8i16
- 167937270U, // VSUBS
- 186647816U, // VSUBWsv2i64
- 187696392U, // VSUBWsv4i32
- 188744968U, // VSUBWsv8i16
- 189793544U, // VSUBWuv2i64
- 190842120U, // VSUBWuv4i32
- 191890696U, // VSUBWuv8i16
- 167937270U, // VSUBfd
- 167937270U, // VSUBfd_sfp
- 167937270U, // VSUBfq
- 196084982U, // VSUBv16i8
- 192939254U, // VSUBv1i64
- 193987830U, // VSUBv2i32
- 192939254U, // VSUBv2i64
- 195036406U, // VSUBv4i16
- 193987830U, // VSUBv4i32
- 195036406U, // VSUBv8i16
- 196084982U, // VSUBv8i8
- 197231886U, // VTBL1
- 1270973710U, // VTBL2
- 331449614U, // VTBL3
- 2344715534U, // VTBL4
- 1270973715U, // VTBX1
- 331449619U, // VTBX2
- 2344715539U, // VTBX3
- 2747368723U, // VTBX4
- 1155531512U, // VTOSIZD
- 1140130552U, // VTOSIZS
- 1156580088U, // VTOUIZD
- 1141179128U, // VTOUIZS
- 1278313752U, // VTRNd16
- 1279362328U, // VTRNd32
- 1270973720U, // VTRNd8
- 1278313752U, // VTRNq16
- 1279362328U, // VTRNq32
- 1270973720U, // VTRNq8
- 196085021U, // VTSTv16i8
- 193987869U, // VTSTv2i32
- 195036445U, // VTSTv4i16
- 193987869U, // VTSTv4i32
- 195036445U, // VTSTv8i16
- 196085021U, // VTSTv8i8
- 1157628664U, // VUITOD
- 1143276280U, // VUITOS
- 1278313762U, // VUZPd16
- 1279362338U, // VUZPd32
- 1270973730U, // VUZPd8
- 1278313762U, // VUZPq16
- 1279362338U, // VUZPq32
- 1270973730U, // VUZPq8
- 1278313767U, // VZIPd16
- 1279362343U, // VZIPd32
- 1270973735U, // VZIPd8
- 1278313767U, // VZIPq16
- 1279362343U, // VZIPq32
- 1270973735U, // VZIPq8
- 7U, // t2ADCSri
- 1324U, // t2ADCSrr
- 1324U, // t2ADCSrs
- 3090251789U, // t2ADCri
- 3172106253U, // t2ADCrr
- 3306323981U, // t2ADCrs
- 219316241U, // t2ADDSri
- 219316241U, // t2ADDSrr
- 1293058065U, // t2ADDSrs
- 3172106262U, // t2ADDrSPi
- 137463092U, // t2ADDrSPi12
- 3306323990U, // t2ADDrSPs
- 3172106262U, // t2ADDri
- 3090253108U, // t2ADDri12
- 3172106262U, // t2ADDrr
- 3306323990U, // t2ADDrs
- 3090251840U, // t2ANDri
- 3172106304U, // t2ANDrr
- 3306324032U, // t2ANDrs
- 3172107577U, // t2ASRri
- 3172107577U, // t2ASRrr
- 4195645U, // t2B
- 137461832U, // t2BFC
- 3090251852U, // t2BICri
- 3172106316U, // t2BICrr
- 3306324044U, // t2BICrs
- 85983346U, // t2BR_JT
- 756351118U, // t2Bcc
- 1076986000U, // t2CLZ
- 1158840468U, // t2CMNri
- 1158840468U, // t2CMNrr
- 219316372U, // t2CMNrs
- 1158840468U, // t2CMNzri
- 1158840468U, // t2CMNzrr
- 219316372U, // t2CMNzrs
- 1158840472U, // t2CMPri
- 1158840472U, // t2CMPrr
- 219316376U, // t2CMPrs
- 1158840472U, // t2CMPzri
- 1158840472U, // t2CMPzrr
- 219316376U, // t2CMPzrs
- 3090251932U, // t2EORri
- 3172106396U, // t2EORrr
- 3306324124U, // t2EORrs
- 3355444546U, // t2IT
- 1476395191U, // t2Int_MemBarrierV7
- 1476395195U, // t2Int_SyncBarrierV7
- 87033157U, // t2Int_eh_sjlj_setjmp
- 1698693321U, // t2LDM
- 1698693321U, // t2LDM_RET
- 1211203793U, // t2LDRB_POST
- 1211203793U, // t2LDRB_PRE
- 219316433U, // t2LDRBi12
- 137461969U, // t2LDRBi8
- 1158840529U, // t2LDRBpci
- 1293058257U, // t2LDRBs
- 1211203798U, // t2LDRDi8
- 137461974U, // t2LDRDpci
- 1076986075U, // t2LDREX
- 1076986081U, // t2LDREXB
- 137461992U, // t2LDREXD
- 1076986095U, // t2LDREXH
- 1211203830U, // t2LDRH_POST
- 1211203830U, // t2LDRH_PRE
- 219316470U, // t2LDRHi12
- 137462006U, // t2LDRHi8
- 1158840566U, // t2LDRHpci
- 1293058294U, // t2LDRHs
- 1211203835U, // t2LDRSB_POST
- 1211203835U, // t2LDRSB_PRE
- 219316475U, // t2LDRSBi12
- 137462011U, // t2LDRSBi8
- 1158840571U, // t2LDRSBpci
- 1293058299U, // t2LDRSBs
- 1211203841U, // t2LDRSH_POST
- 1211203841U, // t2LDRSH_PRE
- 219316481U, // t2LDRSHi12
- 137462017U, // t2LDRSHi8
- 1158840577U, // t2LDRSHpci
- 1293058305U, // t2LDRSHs
- 1211203789U, // t2LDR_POST
- 1211203789U, // t2LDR_PRE
- 219316429U, // t2LDRi12
- 137461965U, // t2LDRi8
- 1158840525U, // t2LDRpci
- 1361U, // t2LDRpci_pic
- 1293058253U, // t2LDRs
- 1159333210U, // t2LEApcrel
- 219809114U, // t2LEApcrelJT
- 3172107614U, // t2LSLri
- 3172107614U, // t2LSLrr
- 3172107618U, // t2LSRri
- 3172107618U, // t2LSRrr
- 1211203853U, // t2MLA
- 1211203857U, // t2MLS
- 1293059385U, // t2MOVCCasr
- 219316501U, // t2MOVCCi
- 1293059422U, // t2MOVCClsl
- 1293059426U, // t2MOVCClsr
- 219316501U, // t2MOVCCr
- 1293059430U, // t2MOVCCror
- 137462041U, // t2MOVTi16
- 3579478293U, // t2MOVi
- 1076986142U, // t2MOVi16
- 1076986142U, // t2MOVi32imm
- 3579478293U, // t2MOVr
- 3579512170U, // t2MOVrx
- 1390U, // t2MOVsra_flag
- 1398U, // t2MOVsrl_flag
- 137462056U, // t2MUL
- 3579511084U, // t2MVNi
- 1158840620U, // t2MVNr
- 219316524U, // t2MVNs
- 3090253182U, // t2ORNri
- 3090253182U, // t2ORNrr
- 3224470910U, // t2ORNrs
- 3090252080U, // t2ORRri
- 3172106544U, // t2ORRrr
- 3306324272U, // t2ORRrs
- 1211203894U, // t2PKHBT
- 1211203900U, // t2PKHTB
- 1158840642U, // t2REV
- 1158840646U, // t2REV16
- 1158840652U, // t2REVSH
- 3172107622U, // t2RORri
- 3172107622U, // t2RORrr
- 3623878999U, // t2RSBSri
- 3492905303U, // t2RSBSrs
- 219316567U, // t2RSBri
- 1211203927U, // t2RSBrs
- 357U, // t2SBCSri
- 1410U, // t2SBCSrr
- 1410U, // t2SBCSrs
- 3090252139U, // t2SBCri
- 3172106603U, // t2SBCrr
- 3306324331U, // t2SBCrs
- 1211203951U, // t2SBFX
- 1211203956U, // t2SMLABB
- 1211203963U, // t2SMLABT
- 1211203970U, // t2SMLAL
- 1211203976U, // t2SMLATB
- 1211203983U, // t2SMLATT
- 1211203990U, // t2SMLAWB
- 1211203997U, // t2SMLAWT
- 1211204004U, // t2SMMLA
- 1211204010U, // t2SMMLS
- 137462192U, // t2SMMUL
- 137462198U, // t2SMULBB
- 137462205U, // t2SMULBT
- 1211204036U, // t2SMULL
- 137462218U, // t2SMULTB
- 137462225U, // t2SMULTT
- 137462232U, // t2SMULWB
- 137462239U, // t2SMULWT
- 1698693606U, // t2STM
- 1211105774U, // t2STRB_POST
- 1211105774U, // t2STRB_PRE
- 219316718U, // t2STRBi12
- 137462254U, // t2STRBi8
- 1293058542U, // t2STRBs
- 1211204083U, // t2STRDi8
- 137462264U, // t2STREX
- 137462270U, // t2STREXB
- 1211204101U, // t2STREXD
- 137462284U, // t2STREXH
- 1211105811U, // t2STRH_POST
- 1211105811U, // t2STRH_PRE
- 219316755U, // t2STRHi12
- 137462291U, // t2STRHi8
- 1293058579U, // t2STRHs
- 1211105770U, // t2STR_POST
- 1211105770U, // t2STR_PRE
- 219316714U, // t2STRi12
- 137462250U, // t2STRi8
- 1293058538U, // t2STRs
- 219316760U, // t2SUBSri
- 219316760U, // t2SUBSrr
- 1293058584U, // t2SUBSrs
- 3172106781U, // t2SUBrSPi
- 137463178U, // t2SUBrSPi12
- 1423U, // t2SUBrSPi12_
- 1431U, // t2SUBrSPi_
- 3224470045U, // t2SUBrSPs
- 1440U, // t2SUBrSPs_
- 3172106781U, // t2SUBri
- 3090253194U, // t2SUBri12
- 3172106781U, // t2SUBrr
- 3306324509U, // t2SUBrs
- 137462305U, // t2SXTABrr
- 1211204129U, // t2SXTABrr_rot
- 137462311U, // t2SXTAHrr
- 1211204135U, // t2SXTAHrr_rot
- 1158840877U, // t2SXTBr
- 219316781U, // t2SXTBr_rot
- 1158840882U, // t2SXTHr
- 219316786U, // t2SXTHr_rot
- 3758097831U, // t2TBB
- 3758097836U, // t2TBH
- 1158840887U, // t2TEQri
- 1158840887U, // t2TEQrr
- 219316791U, // t2TEQrs
- 1476395579U, // t2TPsoft
- 1158840910U, // t2TSTri
- 1158840910U, // t2TSTrr
- 219316814U, // t2TSTrs
- 1211204178U, // t2UBFX
- 1211204183U, // t2UMAAL
- 1211204189U, // t2UMLAL
- 1211204195U, // t2UMULL
- 137462377U, // t2UXTABrr
- 1211204201U, // t2UXTABrr_rot
- 137462383U, // t2UXTAHrr
- 1211204207U, // t2UXTAHrr_rot
- 1158840949U, // t2UXTB16r
- 219316853U, // t2UXTB16r_rot
- 1158840956U, // t2UXTBr
- 219316860U, // t2UXTBr_rot
- 1158840961U, // t2UXTHr
- 219316865U, // t2UXTHr_rot
- 3983245325U, // tADC
- 137461782U, // tADDhirr
- 3982557206U, // tADDi3
- 3983245334U, // tADDi8
- 91227569U, // tADDrPCi
- 66993U, // tADDrSP
- 1457U, // tADDrSPi
- 3982557206U, // tADDrr
- 787889U, // tADDspi
- 66993U, // tADDspr
- 66998U, // tADDspr_
- 4195773U, // tADJCALLSTACKDOWN
- 4195794U, // tADJCALLSTACKUP
- 3983245376U, // tAND
- 67045U, // tANDsp
- 3982558521U, // tASRri
- 3983246649U, // tASRrr
- 4194373U, // tB
- 3983245388U, // tBIC
- 536870992U, // tBL
- 536870996U, // tBLXi
- 536870996U, // tBLXi_r9
- 4194388U, // tBLXr
- 4194388U, // tBLXr_r9
- 536870992U, // tBLr9
- 4194418U, // tBRIND
- 92274802U, // tBR_JTr
- 4194427U, // tBX
- 1476396524U, // tBX_RET
- 4194396U, // tBX_RET_vararg
- 4194427U, // tBXr9
- 674332814U, // tBcc
- 93323344U, // tBfar
- 1522U, // tCBNZ
- 1528U, // tCBZ
- 1076986004U, // tCMN
- 1076986004U, // tCMNz
- 1076986008U, // tCMPhir
- 1076986008U, // tCMPi8
- 1076986008U, // tCMPr
- 1076986008U, // tCMPzhir
- 1076986008U, // tCMPzi8
- 1076986008U, // tCMPzr
- 3983245468U, // tEOR
- 94373373U, // tInt_eh_sjlj_setjmp
- 1613955273U, // tLDM
- 1211203789U, // tLDR
- 1211203793U, // tLDRB
- 1211203830U, // tLDRH
- 137462011U, // tLDRSB
- 137462017U, // tLDRSH
- 1076986061U, // tLDRcp
- 1169162445U, // tLDRpci
- 1586U, // tLDRpci_pic
- 137461965U, // tLDRspi
- 1076987226U, // tLEApcrel
- 137463130U, // tLEApcrelJT
- 3982558558U, // tLSLri
- 3983246686U, // tLSLrr
- 3982558562U, // tLSRri
- 3983246690U, // tLSRrr
- 137462037U, // tMOVCCi
- 137462037U, // tMOVCCr
- 138413627U, // tMOVCCr_pseudo
- 1606U, // tMOVSr
- 1612U, // tMOVgpr2gpr
- 1612U, // tMOVgpr2tgpr
- 3989111061U, // tMOVi8
- 1612U, // tMOVr
- 1612U, // tMOVtgpr2gpr
- 3983245608U, // tMUL
- 3989111084U, // tMVN
- 3983245616U, // tORR
- 1976566068U, // tPICADD
- 943490641U, // tPOP
- 943490641U, // tPOP_RET
- 943490645U, // tPUSH
- 1076986178U, // tREV
- 1076986182U, // tREV16
- 1076986188U, // tREVSH
- 3983246694U, // tROR
- 3989078359U, // tRSB
- 137461965U, // tRestore
- 3983245675U, // tSBC
- 1613955558U, // tSTM
- 1211204074U, // tSTR
- 1211204078U, // tSTRB
- 1211204115U, // tSTRH
- 137462250U, // tSTRspi
- 3982557725U, // tSUBi3
- 3983245853U, // tSUBi8
- 3982557725U, // tSUBrr
- 788058U, // tSUBspi
- 787872U, // tSUBspi_
- 1076986413U, // tSXTB
- 1076986418U, // tSXTH
- 137462250U, // tSpill
- 1476395579U, // tTPsoft
- 1076986446U, // tTST
- 1076986492U, // tUXTB
- 1076986497U, // tUXTH
+ 1U, // DEBUG_VALUE
+ 134217741U, // ADCSSri
+ 134217741U, // ADCSSrr
+ 134217741U, // ADCSSrs
+ 269516819U, // ADCri
+ 269549587U, // ADCrr
+ 404750355U, // ADCrs
+ 271679511U, // ADDSri
+ 271679511U, // ADDSrr
+ 405897239U, // ADDSrs
+ 269516828U, // ADDri
+ 269549596U, // ADDrr
+ 404750364U, // ADDrs
+ 138412064U, // ADJCALLSTACKDOWN
+ 138412084U, // ADJCALLSTACKUP
+ 269516870U, // ANDri
+ 269549638U, // ANDrr
+ 404750406U, // ANDrs
+ 542113866U, // ATOMIC_CMP_SWAP_I16
+ 543162442U, // ATOMIC_CMP_SWAP_I32
+ 544211018U, // ATOMIC_CMP_SWAP_I8
+ 545259594U, // ATOMIC_LOAD_ADD_I16
+ 546308170U, // ATOMIC_LOAD_ADD_I32
+ 547356746U, // ATOMIC_LOAD_ADD_I8
+ 548405322U, // ATOMIC_LOAD_AND_I16
+ 549453898U, // ATOMIC_LOAD_AND_I32
+ 550502474U, // ATOMIC_LOAD_AND_I8
+ 551551050U, // ATOMIC_LOAD_NAND_I16
+ 552599626U, // ATOMIC_LOAD_NAND_I32
+ 553648202U, // ATOMIC_LOAD_NAND_I8
+ 554696778U, // ATOMIC_LOAD_OR_I16
+ 555745354U, // ATOMIC_LOAD_OR_I32
+ 556793930U, // ATOMIC_LOAD_OR_I8
+ 557842506U, // ATOMIC_LOAD_SUB_I16
+ 558891082U, // ATOMIC_LOAD_SUB_I32
+ 559939658U, // ATOMIC_LOAD_SUB_I8
+ 560988234U, // ATOMIC_LOAD_XOR_I16
+ 562036810U, // ATOMIC_LOAD_XOR_I32
+ 563085386U, // ATOMIC_LOAD_XOR_I8
+ 564133962U, // ATOMIC_SWAP_I16
+ 565182538U, // ATOMIC_SWAP_I32
+ 566231114U, // ATOMIC_SWAP_I8
+ 138412107U, // B
+ 271679566U, // BFC
+ 269516882U, // BICri
+ 269549650U, // BICrr
+ 404750418U, // BICrs
+ 671088726U, // BL
+ 138412122U, // BLX
+ 138412122U, // BLXr9
+ 808583263U, // BL_pred
+ 671088726U, // BLr9
+ 808583263U, // BLr9_pred
+ 138412130U, // BRIND
+ 134217830U, // BR_JTadd
+ 939524207U, // BR_JTm
+ 164626552U, // BR_JTr
+ 138412161U, // BX
+ 1105199249U, // BX_RET
+ 138412161U, // BXr9
+ 808550548U, // Bcc
+ 1211203734U, // CLZ
+ 1211203738U, // CMNzri
+ 1211203738U, // CMNzrr
+ 1345421466U, // CMNzrs
+ 1211203742U, // CMPri
+ 1211203742U, // CMPrr
+ 1345421470U, // CMPrs
+ 1211203742U, // CMPzri
+ 1211203742U, // CMPzrr
+ 1345421470U, // CMPzrs
+ 1476395082U, // CONSTPOOL_ENTRY
+ 269516962U, // EORri
+ 269549730U, // EORrr
+ 404750498U, // EORrs
+ 1240629414U, // FCONSTD
+ 1241677990U, // FCONSTS
+ 1108345003U, // FMSTAT
+ 169869488U, // Int_MemBarrierV6
+ 189U, // Int_MemBarrierV7
+ 170918064U, // Int_SyncBarrierV6
+ 193U, // Int_SyncBarrierV7
+ 171966661U, // Int_eh_sjlj_setjmp
+ 1613955279U, // LDM
+ 1613955279U, // LDM_RET
+ 1345421523U, // LDR
+ 1345421527U, // LDRB
+ 405897431U, // LDRB_POST
+ 405897431U, // LDRB_PRE
+ 405897436U, // LDRD
+ 1211203809U, // LDREX
+ 1211203815U, // LDREXB
+ 271679726U, // LDREXD
+ 1211203829U, // LDREXH
+ 1345421564U, // LDRH
+ 405897468U, // LDRH_POST
+ 405897468U, // LDRH_PRE
+ 1345421569U, // LDRSB
+ 405897473U, // LDRSB_POST
+ 405897473U, // LDRSB_PRE
+ 1345421575U, // LDRSH
+ 405897479U, // LDRSH_POST
+ 405897479U, // LDRSH_PRE
+ 405897427U, // LDR_POST
+ 405897427U, // LDR_PRE
+ 1345421523U, // LDRcp
+ 1783628045U, // LEApcrel
+ 1784676621U, // LEApcrelJT
+ 1383072019U, // MLA
+ 1345421591U, // MLS
+ 271679771U, // MOVCCi
+ 271679771U, // MOVCCr
+ 405897499U, // MOVCCs
+ 271679775U, // MOVTi16
+ 1250132251U, // MOVi
+ 1211203876U, // MOVi16
+ 1211203867U, // MOVi2pieces
+ 1211203876U, // MOVi32imm
+ 1249902875U, // MOVr
+ 1249902875U, // MOVrx
+ 1383334171U, // MOVs
+ 1211203881U, // MOVsra_flag
+ 1211203881U, // MOVsrl_flag
+ 269549870U, // MUL
+ 1250132274U, // MVNi
+ 1249902898U, // MVNr
+ 1383334194U, // MVNs
+ 269517110U, // ORRri
+ 269549878U, // ORRrr
+ 404750646U, // ORRrs
+ 1922040122U, // PICADD
+ 2057306426U, // PICLDR
+ 2058355002U, // PICLDRB
+ 2059403578U, // PICLDRH
+ 2060452154U, // PICLDRSB
+ 2061500730U, // PICLDRSH
+ 2062549306U, // PICSTR
+ 2063597882U, // PICSTRB
+ 2064646458U, // PICSTRH
+ 1345421628U, // PKHBT
+ 1345421634U, // PKHTB
+ 1211203912U, // RBIT
+ 1211203917U, // REV
+ 1211203921U, // REV16
+ 1211203927U, // REVSH
+ 271679837U, // RSBSri
+ 405897565U, // RSBSrs
+ 269517154U, // RSBri
+ 404750690U, // RSBrs
+ 134218086U, // RSCSri
+ 134218086U, // RSCSrs
+ 269517164U, // RSCri
+ 404750700U, // RSCrs
+ 134218096U, // SBCSSri
+ 134218096U, // SBCSSrr
+ 134218096U, // SBCSSrs
+ 269517174U, // SBCri
+ 269549942U, // SBCrr
+ 404750710U, // SBCrs
+ 1345421690U, // SBFX
+ 1345421695U, // SMLABB
+ 1345421702U, // SMLABT
+ 1383072141U, // SMLAL
+ 1345421715U, // SMLATB
+ 1345421722U, // SMLATT
+ 1345421729U, // SMLAWB
+ 1345421736U, // SMLAWT
+ 1345421743U, // SMMLA
+ 1345421749U, // SMMLS
+ 271679931U, // SMMUL
+ 271679937U, // SMULBB
+ 271679944U, // SMULBT
+ 1383072207U, // SMULL
+ 271679957U, // SMULTB
+ 271679964U, // SMULTT
+ 271679971U, // SMULWB
+ 271679978U, // SMULWT
+ 1613955569U, // STM
+ 1345421813U, // STR
+ 1345421817U, // STRB
+ 405799417U, // STRB_POST
+ 405799417U, // STRB_PRE
+ 405897726U, // STRD
+ 271680003U, // STREX
+ 271680009U, // STREXB
+ 1345421840U, // STREXD
+ 271680023U, // STREXH
+ 1345421854U, // STRH
+ 405799454U, // STRH_POST
+ 405799454U, // STRH_PRE
+ 405799413U, // STR_POST
+ 405799413U, // STR_PRE
+ 271680035U, // SUBSri
+ 271680035U, // SUBSrr
+ 405897763U, // SUBSrs
+ 269517352U, // SUBri
+ 269550120U, // SUBrr
+ 404750888U, // SUBrs
+ 271680044U, // SXTABrr
+ 1345421868U, // SXTABrr_rot
+ 271680050U, // SXTAHrr
+ 1345421874U, // SXTAHrr_rot
+ 1211204152U, // SXTBr
+ 271680056U, // SXTBr_rot
+ 1211204157U, // SXTHr
+ 271680061U, // SXTHr_rot
+ 1211204162U, // TEQri
+ 1211204162U, // TEQrr
+ 1345421890U, // TEQrs
+ 582U, // TPsoft
+ 1211204185U, // TSTri
+ 1211204185U, // TSTrr
+ 1345421913U, // TSTrs
+ 1345421917U, // UBFX
+ 1345421922U, // UMAAL
+ 1383072360U, // UMLAL
+ 1383072366U, // UMULL
+ 271680116U, // UXTABrr
+ 1345421940U, // UXTABrr_rot
+ 271680122U, // UXTAHrr
+ 1345421946U, // UXTAHrr_rot
+ 1211204224U, // UXTB16r
+ 271680128U, // UXTB16r_rot
+ 1211204231U, // UXTBr
+ 271680135U, // UXTBr_rot
+ 1211204236U, // UXTHr
+ 271680140U, // UXTHr_rot
+ 1394672273U, // VABALsv2i64
+ 1395720849U, // VABALsv4i32
+ 1396769425U, // VABALsv8i16
+ 1397818001U, // VABALuv2i64
+ 1398866577U, // VABALuv4i32
+ 1399915153U, // VABALuv8i16
+ 1396769431U, // VABAsv16i8
+ 1394672279U, // VABAsv2i32
+ 1395720855U, // VABAsv4i16
+ 1394672279U, // VABAsv4i32
+ 1395720855U, // VABAsv8i16
+ 1396769431U, // VABAsv8i8
+ 1399915159U, // VABAuv16i8
+ 1397818007U, // VABAuv2i32
+ 1398866583U, // VABAuv4i16
+ 1397818007U, // VABAuv4i32
+ 1398866583U, // VABAuv8i16
+ 1399915159U, // VABAuv8i8
+ 320864924U, // VABDLsv2i64
+ 321913500U, // VABDLsv4i32
+ 322962076U, // VABDLsv8i16
+ 324010652U, // VABDLuv2i64
+ 325059228U, // VABDLuv4i32
+ 326107804U, // VABDLuv8i16
+ 302154402U, // VABDfd
+ 302154402U, // VABDfq
+ 322962082U, // VABDsv16i8
+ 320864930U, // VABDsv2i32
+ 321913506U, // VABDsv4i16
+ 320864930U, // VABDsv4i32
+ 321913506U, // VABDsv8i16
+ 322962082U, // VABDsv8i8
+ 326107810U, // VABDuv16i8
+ 324010658U, // VABDuv2i32
+ 325059234U, // VABDuv4i16
+ 324010658U, // VABDuv4i32
+ 325059234U, // VABDuv8i16
+ 326107810U, // VABDuv8i8
+ 1240629927U, // VABSD
+ 1241678503U, // VABSS
+ 1241678503U, // VABSfd
+ 1241678503U, // VABSfd_sfp
+ 1241678503U, // VABSfq
+ 1262486183U, // VABSv16i8
+ 1260389031U, // VABSv2i32
+ 1261437607U, // VABSv4i16
+ 1260389031U, // VABSv4i32
+ 1261437607U, // VABSv8i16
+ 1262486183U, // VABSv8i8
+ 302154412U, // VACGEd
+ 302154412U, // VACGEq
+ 302154418U, // VACGTd
+ 302154418U, // VACGTq
+ 301105848U, // VADDD
+ 327156413U, // VADDHNv2i32
+ 328204989U, // VADDHNv4i16
+ 329253565U, // VADDHNv8i8
+ 320864964U, // VADDLsv2i64
+ 321913540U, // VADDLsv4i32
+ 322962116U, // VADDLsv8i16
+ 324010692U, // VADDLuv2i64
+ 325059268U, // VADDLuv4i32
+ 326107844U, // VADDLuv8i16
+ 302154424U, // VADDS
+ 320864970U, // VADDWsv2i64
+ 321913546U, // VADDWsv4i32
+ 322962122U, // VADDWsv8i16
+ 324010698U, // VADDWuv2i64
+ 325059274U, // VADDWuv4i32
+ 326107850U, // VADDWuv8i16
+ 302154424U, // VADDfd
+ 302154424U, // VADDfd_sfp
+ 302154424U, // VADDfq
+ 330302136U, // VADDv16i8
+ 327156408U, // VADDv1i64
+ 328204984U, // VADDv2i32
+ 327156408U, // VADDv2i64
+ 329253560U, // VADDv4i16
+ 328204984U, // VADDv4i32
+ 329253560U, // VADDv8i16
+ 330302136U, // VADDv8i8
+ 271680208U, // VANDd
+ 271680208U, // VANDq
+ 271680213U, // VBICd
+ 271680213U, // VBICq
+ 1345422042U, // VBSLd
+ 1345422042U, // VBSLq
+ 302154463U, // VCEQfd
+ 302154463U, // VCEQfq
+ 330302175U, // VCEQv16i8
+ 328205023U, // VCEQv2i32
+ 329253599U, // VCEQv4i16
+ 328205023U, // VCEQv4i32
+ 329253599U, // VCEQv8i16
+ 330302175U, // VCEQv8i8
+ 302154468U, // VCGEfd
+ 302154468U, // VCGEfq
+ 322962148U, // VCGEsv16i8
+ 320864996U, // VCGEsv2i32
+ 321913572U, // VCGEsv4i16
+ 320864996U, // VCGEsv4i32
+ 321913572U, // VCGEsv8i16
+ 322962148U, // VCGEsv8i8
+ 326107876U, // VCGEuv16i8
+ 324010724U, // VCGEuv2i32
+ 325059300U, // VCGEuv4i16
+ 324010724U, // VCGEuv4i32
+ 325059300U, // VCGEuv8i16
+ 326107876U, // VCGEuv8i8
+ 302154473U, // VCGTfd
+ 302154473U, // VCGTfq
+ 322962153U, // VCGTsv16i8
+ 320865001U, // VCGTsv2i32
+ 321913577U, // VCGTsv4i16
+ 320865001U, // VCGTsv4i32
+ 321913577U, // VCGTsv8i16
+ 322962153U, // VCGTsv8i8
+ 326107881U, // VCGTuv16i8
+ 324010729U, // VCGTuv2i32
+ 325059305U, // VCGTuv4i16
+ 324010729U, // VCGTuv4i32
+ 325059305U, // VCGTuv8i16
+ 326107881U, // VCGTuv8i8
+ 1262486254U, // VCLSv16i8
+ 1260389102U, // VCLSv2i32
+ 1261437678U, // VCLSv4i16
+ 1260389102U, // VCLSv4i32
+ 1261437678U, // VCLSv8i16
+ 1262486254U, // VCLSv8i8
+ 1269826291U, // VCLZv16i8
+ 1267729139U, // VCLZv2i32
+ 1268777715U, // VCLZv4i16
+ 1267729139U, // VCLZv4i32
+ 1268777715U, // VCLZv8i16
+ 1269826291U, // VCLZv8i8
+ 1240630008U, // VCMPED
+ 1241678584U, // VCMPES
+ 838107896U, // VCMPEZD
+ 839156472U, // VCMPEZS
+ 1270973182U, // VCNTd
+ 1270973182U, // VCNTq
+ 1271923459U, // VCVTDS
+ 1272972035U, // VCVTSD
+ 1274348291U, // VCVTf2sd
+ 1274348291U, // VCVTf2sd_sfp
+ 1274348291U, // VCVTf2sq
+ 1275396867U, // VCVTf2ud
+ 1275396867U, // VCVTf2ud_sfp
+ 1275396867U, // VCVTf2uq
+ 334660355U, // VCVTf2xsd
+ 334660355U, // VCVTf2xsq
+ 335708931U, // VCVTf2xud
+ 335708931U, // VCVTf2xuq
+ 1276445443U, // VCVTs2fd
+ 1276445443U, // VCVTs2fd_sfp
+ 1276445443U, // VCVTs2fq
+ 1277494019U, // VCVTu2fd
+ 1277494019U, // VCVTu2fd_sfp
+ 1277494019U, // VCVTu2fq
+ 336757507U, // VCVTxs2fd
+ 336757507U, // VCVTxs2fq
+ 337806083U, // VCVTxu2fd
+ 337806083U, // VCVTxu2fq
+ 301105928U, // VDIVD
+ 302154504U, // VDIVS
+ 1278313229U, // VDUP16d
+ 1278313229U, // VDUP16q
+ 1279361805U, // VDUP32d
+ 1279361805U, // VDUP32q
+ 1270973197U, // VDUP8d
+ 1270973197U, // VDUP8q
+ 338789133U, // VDUPLN16d
+ 338789133U, // VDUPLN16q
+ 339837709U, // VDUPLN32d
+ 339837709U, // VDUPLN32q
+ 331449101U, // VDUPLN8d
+ 331449101U, // VDUPLN8q
+ 339837709U, // VDUPLNfd
+ 339837709U, // VDUPLNfq
+ 1279361805U, // VDUPfd
+ 1279361805U, // VDUPfdf
+ 1279361805U, // VDUPfq
+ 1279361805U, // VDUPfqf
+ 271680274U, // VEORd
+ 271680274U, // VEORq
+ 1412530967U, // VEXTd16
+ 1413579543U, // VEXTd32
+ 1405190935U, // VEXTd8
+ 1413579543U, // VEXTdf
+ 1412530967U, // VEXTq16
+ 1413579543U, // VEXTq32
+ 1405190935U, // VEXTq8
+ 1413579543U, // VEXTqf
+ 339837094U, // VGETLNi32
+ 321912998U, // VGETLNs16
+ 322961574U, // VGETLNs8
+ 325058726U, // VGETLNu16
+ 326107302U, // VGETLNu8
+ 322962204U, // VHADDsv16i8
+ 320865052U, // VHADDsv2i32
+ 321913628U, // VHADDsv4i16
+ 320865052U, // VHADDsv4i32
+ 321913628U, // VHADDsv8i16
+ 322962204U, // VHADDsv8i8
+ 326107932U, // VHADDuv16i8
+ 324010780U, // VHADDuv2i32
+ 325059356U, // VHADDuv4i16
+ 324010780U, // VHADDuv4i32
+ 325059356U, // VHADDuv8i16
+ 326107932U, // VHADDuv8i8
+ 322962210U, // VHSUBsv16i8
+ 320865058U, // VHSUBsv2i32
+ 321913634U, // VHSUBsv4i16
+ 320865058U, // VHSUBsv4i32
+ 321913634U, // VHSUBsv8i16
+ 322962210U, // VHSUBsv8i8
+ 326107938U, // VHSUBuv16i8
+ 324010786U, // VHSUBuv2i32
+ 325059362U, // VHSUBuv4i16
+ 324010786U, // VHSUBuv4i32
+ 325059362U, // VHSUBuv8i16
+ 326107938U, // VHSUBuv8i8
+ 475104040U, // VLD1d16
+ 476152616U, // VLD1d32
+ 477201192U, // VLD1d64
+ 478249768U, // VLD1d8
+ 476152616U, // VLD1df
+ 473269032U, // VLD1q16
+ 474317608U, // VLD1q32
+ 479560488U, // VLD1q64
+ 465929000U, // VLD1q8
+ 474317608U, // VLD1qf
+ 2219934509U, // VLD2LNd16
+ 2220983085U, // VLD2LNd32
+ 2223080237U, // VLD2LNd8
+ 2219934509U, // VLD2LNq16a
+ 2219934509U, // VLD2LNq16b
+ 2220983085U, // VLD2LNq32a
+ 2220983085U, // VLD2LNq32b
+ 2354152237U, // VLD2d16
+ 2355200813U, // VLD2d32
+ 2356249384U, // VLD2d64
+ 2357297965U, // VLD2d8
+ 2488369965U, // VLD2q16
+ 2489418541U, // VLD2q32
+ 2491515693U, // VLD2q8
+ 2622587698U, // VLD3LNd16
+ 2623636274U, // VLD3LNd32
+ 2625733426U, // VLD3LNd8
+ 2622587698U, // VLD3LNq16a
+ 2622587698U, // VLD3LNq16b
+ 2623636274U, // VLD3LNq32a
+ 2623636274U, // VLD3LNq32b
+ 2756805426U, // VLD3d16
+ 2757854002U, // VLD3d32
+ 2758902568U, // VLD3d64
+ 2759951154U, // VLD3d8
+ 2488369970U, // VLD3q16a
+ 2488369970U, // VLD3q16b
+ 2489418546U, // VLD3q32a
+ 2489418546U, // VLD3q32b
+ 2491515698U, // VLD3q8a
+ 2491515698U, // VLD3q8b
+ 2891023159U, // VLD4LNd16
+ 2892071735U, // VLD4LNd32
+ 2894168887U, // VLD4LNd8
+ 2891023159U, // VLD4LNq16a
+ 2891023159U, // VLD4LNq16b
+ 2892071735U, // VLD4LNq32a
+ 2892071735U, // VLD4LNq32b
+ 2488369975U, // VLD4d16
+ 2489418551U, // VLD4d32
+ 2490467112U, // VLD4d64
+ 2491515703U, // VLD4d8
+ 2219934519U, // VLD4q16a
+ 2219934519U, // VLD4q16b
+ 2220983095U, // VLD4q32a
+ 2220983095U, // VLD4q32b
+ 2223080247U, // VLD4q8a
+ 2223080247U, // VLD4q8b
+ 2952790844U, // VLDMD
+ 2952790844U, // VLDMS
+ 345080641U, // VLDRD
+ 271975238U, // VLDRQ
+ 339837761U, // VLDRS
+ 302154573U, // VMAXfd
+ 302154573U, // VMAXfq
+ 322962253U, // VMAXsv16i8
+ 320865101U, // VMAXsv2i32
+ 321913677U, // VMAXsv4i16
+ 320865101U, // VMAXsv4i32
+ 321913677U, // VMAXsv8i16
+ 322962253U, // VMAXsv8i8
+ 326107981U, // VMAXuv16i8
+ 324010829U, // VMAXuv2i32
+ 325059405U, // VMAXuv4i16
+ 324010829U, // VMAXuv4i32
+ 325059405U, // VMAXuv8i16
+ 326107981U, // VMAXuv8i8
+ 302154578U, // VMINfd
+ 302154578U, // VMINfq
+ 322962258U, // VMINsv16i8
+ 320865106U, // VMINsv2i32
+ 321913682U, // VMINsv4i16
+ 320865106U, // VMINsv4i32
+ 321913682U, // VMINsv8i16
+ 322962258U, // VMINsv8i8
+ 326107986U, // VMINuv16i8
+ 324010834U, // VMINuv2i32
+ 325059410U, // VMINuv4i16
+ 324010834U, // VMINuv4i32
+ 325059410U, // VMINuv8i16
+ 326107986U, // VMINuv8i8
+ 1374847831U, // VMLAD
+ 455148380U, // VMLALslsv2i32
+ 456196956U, // VMLALslsv4i16
+ 458294108U, // VMLALsluv2i32
+ 459342684U, // VMLALsluv4i16
+ 1394672476U, // VMLALsv2i64
+ 1395721052U, // VMLALsv4i32
+ 1396769628U, // VMLALsv8i16
+ 1397818204U, // VMLALuv2i64
+ 1398866780U, // VMLALuv4i32
+ 1399915356U, // VMLALuv8i16
+ 1375896407U, // VMLAS
+ 1375896407U, // VMLAfd
+ 1375896407U, // VMLAfq
+ 436372311U, // VMLAslfd
+ 436372311U, // VMLAslfq
+ 462488407U, // VMLAslv2i32
+ 463536983U, // VMLAslv4i16
+ 462488407U, // VMLAslv4i32
+ 463536983U, // VMLAslv8i16
+ 1404109655U, // VMLAv16i8
+ 1402012503U, // VMLAv2i32
+ 1403061079U, // VMLAv4i16
+ 1402012503U, // VMLAv4i32
+ 1403061079U, // VMLAv8i16
+ 1404109655U, // VMLAv8i8
+ 1374847842U, // VMLSD
+ 455148391U, // VMLSLslsv2i32
+ 456196967U, // VMLSLslsv4i16
+ 458294119U, // VMLSLsluv2i32
+ 459342695U, // VMLSLsluv4i16
+ 1394672487U, // VMLSLsv2i64
+ 1395721063U, // VMLSLsv4i32
+ 1396769639U, // VMLSLsv8i16
+ 1397818215U, // VMLSLuv2i64
+ 1398866791U, // VMLSLuv4i32
+ 1399915367U, // VMLSLuv8i16
+ 1375896418U, // VMLSS
+ 1375896418U, // VMLSfd
+ 1375896418U, // VMLSfq
+ 436372322U, // VMLSslfd
+ 436372322U, // VMLSslfq
+ 462488418U, // VMLSslv2i32
+ 463536994U, // VMLSslv4i16
+ 462488418U, // VMLSslv4i32
+ 463536994U, // VMLSslv8i16
+ 1404109666U, // VMLSv16i8
+ 1402012514U, // VMLSv2i32
+ 1403061090U, // VMLSv4i16
+ 1402012514U, // VMLSv4i32
+ 1403061090U, // VMLSv8i16
+ 1404109666U, // VMLSv8i8
+ 1240629414U, // VMOVD
+ 271679654U, // VMOVDRR
+ 301105318U, // VMOVDcc
+ 1211203750U, // VMOVDneon
+ 1260389229U, // VMOVLsv2i64
+ 1261437805U, // VMOVLsv4i32
+ 1262486381U, // VMOVLsv8i16
+ 1263534957U, // VMOVLuv2i64
+ 1264583533U, // VMOVLuv4i32
+ 1265632109U, // VMOVLuv8i16
+ 1266680691U, // VMOVNv2i32
+ 1267729267U, // VMOVNv4i16
+ 1268777843U, // VMOVNv8i8
+ 1211203750U, // VMOVQ
+ 271679654U, // VMOVRRD
+ 1211203750U, // VMOVRS
+ 1241677990U, // VMOVS
+ 1211203750U, // VMOVSR
+ 302153894U, // VMOVScc
+ 1270251686U, // VMOVv16i8
+ 1267138726U, // VMOVv1i64
+ 1268220070U, // VMOVv2i32
+ 1267138726U, // VMOVv2i64
+ 1269301414U, // VMOVv4i16
+ 1268220070U, // VMOVv4i32
+ 1269301414U, // VMOVv8i16
+ 1270251686U, // VMOVv8i8
+ 301106041U, // VMULD
+ 346030974U, // VMULLp
+ 1394606974U, // VMULLslsv2i32
+ 1395655550U, // VMULLslsv4i16
+ 1397752702U, // VMULLsluv2i32
+ 1398801278U, // VMULLsluv4i16
+ 320865150U, // VMULLsv2i64
+ 321913726U, // VMULLsv4i32
+ 322962302U, // VMULLsv8i16
+ 324010878U, // VMULLuv2i64
+ 325059454U, // VMULLuv4i32
+ 326108030U, // VMULLuv8i16
+ 302154617U, // VMULS
+ 302154617U, // VMULfd
+ 302154617U, // VMULfd_sfp
+ 302154617U, // VMULfq
+ 346030969U, // VMULpd
+ 346030969U, // VMULpq
+ 1375896441U, // VMULslfd
+ 1375896441U, // VMULslfq
+ 1401947001U, // VMULslv2i32
+ 1402995577U, // VMULslv4i16
+ 1401947001U, // VMULslv4i32
+ 1402995577U, // VMULslv8i16
+ 330302329U, // VMULv16i8
+ 328205177U, // VMULv2i32
+ 329253753U, // VMULv4i16
+ 328205177U, // VMULv4i32
+ 329253753U, // VMULv8i16
+ 330302329U, // VMULv8i8
+ 1211204484U, // VMVNd
+ 1211204484U, // VMVNq
+ 1240630153U, // VNEGD
+ 301106057U, // VNEGDcc
+ 1241678729U, // VNEGS
+ 302154633U, // VNEGScc
+ 1241678729U, // VNEGf32d
+ 1241678729U, // VNEGf32d_sfp
+ 1241678729U, // VNEGf32q
+ 1261437833U, // VNEGs16d
+ 1261437833U, // VNEGs16q
+ 1260389257U, // VNEGs32d
+ 1260389257U, // VNEGs32q
+ 1262486409U, // VNEGs8d
+ 1262486409U, // VNEGs8q
+ 1374847886U, // VNMLAD
+ 1375896462U, // VNMLAS
+ 1374847892U, // VNMLSD
+ 1375896468U, // VNMLSS
+ 301106074U, // VNMULD
+ 302154650U, // VNMULS
+ 271680416U, // VORNd
+ 271680416U, // VORNq
+ 271680421U, // VORRd
+ 271680421U, // VORRq
+ 323027882U, // VPADALsv16i8
+ 320930730U, // VPADALsv2i32
+ 321979306U, // VPADALsv4i16
+ 320930730U, // VPADALsv4i32
+ 321979306U, // VPADALsv8i16
+ 323027882U, // VPADALsv8i8
+ 326173610U, // VPADALuv16i8
+ 324076458U, // VPADALuv2i32
+ 325125034U, // VPADALuv4i16
+ 324076458U, // VPADALuv4i32
+ 325125034U, // VPADALuv8i16
+ 326173610U, // VPADALuv8i8
+ 1262486449U, // VPADDLsv16i8
+ 1260389297U, // VPADDLsv2i32
+ 1261437873U, // VPADDLsv4i16
+ 1260389297U, // VPADDLsv4i32
+ 1261437873U, // VPADDLsv8i16
+ 1262486449U, // VPADDLsv8i8
+ 1265632177U, // VPADDLuv16i8
+ 1263535025U, // VPADDLuv2i32
+ 1264583601U, // VPADDLuv4i16
+ 1263535025U, // VPADDLuv4i32
+ 1264583601U, // VPADDLuv8i16
+ 1265632177U, // VPADDLuv8i8
+ 302154680U, // VPADDf
+ 329253816U, // VPADDi16
+ 328205240U, // VPADDi32
+ 330302392U, // VPADDi8
+ 302154686U, // VPMAXf
+ 321913790U, // VPMAXs16
+ 320865214U, // VPMAXs32
+ 322962366U, // VPMAXs8
+ 325059518U, // VPMAXu16
+ 324010942U, // VPMAXu32
+ 326108094U, // VPMAXu8
+ 302154692U, // VPMINf
+ 321913796U, // VPMINs16
+ 320865220U, // VPMINs32
+ 322962372U, // VPMINs8
+ 325059524U, // VPMINu16
+ 324010948U, // VPMINu32
+ 326108100U, // VPMINu8
+ 1262486474U, // VQABSv16i8
+ 1260389322U, // VQABSv2i32
+ 1261437898U, // VQABSv4i16
+ 1260389322U, // VQABSv4i32
+ 1261437898U, // VQABSv8i16
+ 1262486474U, // VQABSv8i8
+ 322962384U, // VQADDsv16i8
+ 347079632U, // VQADDsv1i64
+ 320865232U, // VQADDsv2i32
+ 347079632U, // VQADDsv2i64
+ 321913808U, // VQADDsv4i16
+ 320865232U, // VQADDsv4i32
+ 321913808U, // VQADDsv8i16
+ 322962384U, // VQADDsv8i8
+ 326108112U, // VQADDuv16i8
+ 348128208U, // VQADDuv1i64
+ 324010960U, // VQADDuv2i32
+ 348128208U, // VQADDuv2i64
+ 325059536U, // VQADDuv4i16
+ 324010960U, // VQADDuv4i32
+ 325059536U, // VQADDuv8i16
+ 326108112U, // VQADDuv8i8
+ 455148502U, // VQDMLALslv2i32
+ 456197078U, // VQDMLALslv4i16
+ 1394672598U, // VQDMLALv2i64
+ 1395721174U, // VQDMLALv4i32
+ 455148510U, // VQDMLSLslv2i32
+ 456197086U, // VQDMLSLslv4i16
+ 1394672606U, // VQDMLSLv2i64
+ 1395721182U, // VQDMLSLv4i32
+ 1394607078U, // VQDMULHslv2i32
+ 1395655654U, // VQDMULHslv4i16
+ 1394607078U, // VQDMULHslv4i32
+ 1395655654U, // VQDMULHslv8i16
+ 320865254U, // VQDMULHv2i32
+ 321913830U, // VQDMULHv4i16
+ 320865254U, // VQDMULHv4i32
+ 321913830U, // VQDMULHv8i16
+ 1394607086U, // VQDMULLslv2i32
+ 1395655662U, // VQDMULLslv4i16
+ 320865262U, // VQDMULLv2i64
+ 321913838U, // VQDMULLv4i32
+ 1286603766U, // VQMOVNsuv2i32
+ 1260389366U, // VQMOVNsuv4i16
+ 1261437942U, // VQMOVNsuv8i8
+ 1286603774U, // VQMOVNsv2i32
+ 1260389374U, // VQMOVNsv4i16
+ 1261437950U, // VQMOVNsv8i8
+ 1287652350U, // VQMOVNuv2i32
+ 1263535102U, // VQMOVNuv4i16
+ 1264583678U, // VQMOVNuv8i8
+ 1262486533U, // VQNEGv16i8
+ 1260389381U, // VQNEGv2i32
+ 1261437957U, // VQNEGv4i16
+ 1260389381U, // VQNEGv4i32
+ 1261437957U, // VQNEGv8i16
+ 1262486533U, // VQNEGv8i8
+ 1394607115U, // VQRDMULHslv2i32
+ 1395655691U, // VQRDMULHslv4i16
+ 1394607115U, // VQRDMULHslv4i32
+ 1395655691U, // VQRDMULHslv8i16
+ 320865291U, // VQRDMULHv2i32
+ 321913867U, // VQRDMULHv4i16
+ 320865291U, // VQRDMULHv4i32
+ 321913867U, // VQRDMULHv8i16
+ 322962452U, // VQRSHLsv16i8
+ 347079700U, // VQRSHLsv1i64
+ 320865300U, // VQRSHLsv2i32
+ 347079700U, // VQRSHLsv2i64
+ 321913876U, // VQRSHLsv4i16
+ 320865300U, // VQRSHLsv4i32
+ 321913876U, // VQRSHLsv8i16
+ 322962452U, // VQRSHLsv8i8
+ 326108180U, // VQRSHLuv16i8
+ 348128276U, // VQRSHLuv1i64
+ 324011028U, // VQRSHLuv2i32
+ 348128276U, // VQRSHLuv2i64
+ 325059604U, // VQRSHLuv4i16
+ 324011028U, // VQRSHLuv4i32
+ 325059604U, // VQRSHLuv8i16
+ 326108180U, // VQRSHLuv8i8
+ 347079707U, // VQRSHRNsv2i32
+ 320865307U, // VQRSHRNsv4i16
+ 321913883U, // VQRSHRNsv8i8
+ 348128283U, // VQRSHRNuv2i32
+ 324011035U, // VQRSHRNuv4i16
+ 325059611U, // VQRSHRNuv8i8
+ 347079715U, // VQRSHRUNv2i32
+ 320865315U, // VQRSHRUNv4i16
+ 321913891U, // VQRSHRUNv8i8
+ 322962476U, // VQSHLsiv16i8
+ 347079724U, // VQSHLsiv1i64
+ 320865324U, // VQSHLsiv2i32
+ 347079724U, // VQSHLsiv2i64
+ 321913900U, // VQSHLsiv4i16
+ 320865324U, // VQSHLsiv4i32
+ 321913900U, // VQSHLsiv8i16
+ 322962476U, // VQSHLsiv8i8
+ 322962482U, // VQSHLsuv16i8
+ 347079730U, // VQSHLsuv1i64
+ 320865330U, // VQSHLsuv2i32
+ 347079730U, // VQSHLsuv2i64
+ 321913906U, // VQSHLsuv4i16
+ 320865330U, // VQSHLsuv4i32
+ 321913906U, // VQSHLsuv8i16
+ 322962482U, // VQSHLsuv8i8
+ 322962476U, // VQSHLsv16i8
+ 347079724U, // VQSHLsv1i64
+ 320865324U, // VQSHLsv2i32
+ 347079724U, // VQSHLsv2i64
+ 321913900U, // VQSHLsv4i16
+ 320865324U, // VQSHLsv4i32
+ 321913900U, // VQSHLsv8i16
+ 322962476U, // VQSHLsv8i8
+ 326108204U, // VQSHLuiv16i8
+ 348128300U, // VQSHLuiv1i64
+ 324011052U, // VQSHLuiv2i32
+ 348128300U, // VQSHLuiv2i64
+ 325059628U, // VQSHLuiv4i16
+ 324011052U, // VQSHLuiv4i32
+ 325059628U, // VQSHLuiv8i16
+ 326108204U, // VQSHLuiv8i8
+ 326108204U, // VQSHLuv16i8
+ 348128300U, // VQSHLuv1i64
+ 324011052U, // VQSHLuv2i32
+ 348128300U, // VQSHLuv2i64
+ 325059628U, // VQSHLuv4i16
+ 324011052U, // VQSHLuv4i32
+ 325059628U, // VQSHLuv8i16
+ 326108204U, // VQSHLuv8i8
+ 347079737U, // VQSHRNsv2i32
+ 320865337U, // VQSHRNsv4i16
+ 321913913U, // VQSHRNsv8i8
+ 348128313U, // VQSHRNuv2i32
+ 324011065U, // VQSHRNuv4i16
+ 325059641U, // VQSHRNuv8i8
+ 347079744U, // VQSHRUNv2i32
+ 320865344U, // VQSHRUNv4i16
+ 321913920U, // VQSHRUNv8i8
+ 322962504U, // VQSUBsv16i8
+ 347079752U, // VQSUBsv1i64
+ 320865352U, // VQSUBsv2i32
+ 347079752U, // VQSUBsv2i64
+ 321913928U, // VQSUBsv4i16
+ 320865352U, // VQSUBsv4i32
+ 321913928U, // VQSUBsv8i16
+ 322962504U, // VQSUBsv8i8
+ 326108232U, // VQSUBuv16i8
+ 348128328U, // VQSUBuv1i64
+ 324011080U, // VQSUBuv2i32
+ 348128328U, // VQSUBuv2i64
+ 325059656U, // VQSUBuv4i16
+ 324011080U, // VQSUBuv4i32
+ 325059656U, // VQSUBuv8i16
+ 326108232U, // VQSUBuv8i8
+ 327156814U, // VRADDHNv2i32
+ 328205390U, // VRADDHNv4i16
+ 329253966U, // VRADDHNv8i8
+ 1263535190U, // VRECPEd
+ 1241678934U, // VRECPEfd
+ 1241678934U, // VRECPEfq
+ 1263535190U, // VRECPEq
+ 302154845U, // VRECPSfd
+ 302154845U, // VRECPSfq
+ 1270973540U, // VREV16d8
+ 1270973540U, // VREV16q8
+ 1278313579U, // VREV32d16
+ 1270973547U, // VREV32d8
+ 1278313579U, // VREV32q16
+ 1270973547U, // VREV32q8
+ 1278313586U, // VREV64d16
+ 1279362162U, // VREV64d32
+ 1270973554U, // VREV64d8
+ 1279362162U, // VREV64df
+ 1278313586U, // VREV64q16
+ 1279362162U, // VREV64q32
+ 1270973554U, // VREV64q8
+ 1279362162U, // VREV64qf
+ 322962553U, // VRHADDsv16i8
+ 320865401U, // VRHADDsv2i32
+ 321913977U, // VRHADDsv4i16
+ 320865401U, // VRHADDsv4i32
+ 321913977U, // VRHADDsv8i16
+ 322962553U, // VRHADDsv8i8
+ 326108281U, // VRHADDuv16i8
+ 324011129U, // VRHADDuv2i32
+ 325059705U, // VRHADDuv4i16
+ 324011129U, // VRHADDuv4i32
+ 325059705U, // VRHADDuv8i16
+ 326108281U, // VRHADDuv8i8
+ 322962560U, // VRSHLsv16i8
+ 347079808U, // VRSHLsv1i64
+ 320865408U, // VRSHLsv2i32
+ 347079808U, // VRSHLsv2i64
+ 321913984U, // VRSHLsv4i16
+ 320865408U, // VRSHLsv4i32
+ 321913984U, // VRSHLsv8i16
+ 322962560U, // VRSHLsv8i8
+ 326108288U, // VRSHLuv16i8
+ 348128384U, // VRSHLuv1i64
+ 324011136U, // VRSHLuv2i32
+ 348128384U, // VRSHLuv2i64
+ 325059712U, // VRSHLuv4i16
+ 324011136U, // VRSHLuv4i32
+ 325059712U, // VRSHLuv8i16
+ 326108288U, // VRSHLuv8i8
+ 327156870U, // VRSHRNv2i32
+ 328205446U, // VRSHRNv4i16
+ 329254022U, // VRSHRNv8i8
+ 322962573U, // VRSHRsv16i8
+ 347079821U, // VRSHRsv1i64
+ 320865421U, // VRSHRsv2i32
+ 347079821U, // VRSHRsv2i64
+ 321913997U, // VRSHRsv4i16
+ 320865421U, // VRSHRsv4i32
+ 321913997U, // VRSHRsv8i16
+ 322962573U, // VRSHRsv8i8
+ 326108301U, // VRSHRuv16i8
+ 348128397U, // VRSHRuv1i64
+ 324011149U, // VRSHRuv2i32
+ 348128397U, // VRSHRuv2i64
+ 325059725U, // VRSHRuv4i16
+ 324011149U, // VRSHRuv4i32
+ 325059725U, // VRSHRuv8i16
+ 326108301U, // VRSHRuv8i8
+ 1263535251U, // VRSQRTEd
+ 1241678995U, // VRSQRTEfd
+ 1241678995U, // VRSQRTEfq
+ 1263535251U, // VRSQRTEq
+ 302154907U, // VRSQRTSfd
+ 302154907U, // VRSQRTSfq
+ 1396769955U, // VRSRAsv16i8
+ 1420887203U, // VRSRAsv1i64
+ 1394672803U, // VRSRAsv2i32
+ 1420887203U, // VRSRAsv2i64
+ 1395721379U, // VRSRAsv4i16
+ 1394672803U, // VRSRAsv4i32
+ 1395721379U, // VRSRAsv8i16
+ 1396769955U, // VRSRAsv8i8
+ 1399915683U, // VRSRAuv16i8
+ 1421935779U, // VRSRAuv1i64
+ 1397818531U, // VRSRAuv2i32
+ 1421935779U, // VRSRAuv2i64
+ 1398867107U, // VRSRAuv4i16
+ 1397818531U, // VRSRAuv4i32
+ 1398867107U, // VRSRAuv8i16
+ 1399915683U, // VRSRAuv8i8
+ 327156905U, // VRSUBHNv2i32
+ 328205481U, // VRSUBHNv4i16
+ 329254057U, // VRSUBHNv8i8
+ 1412530342U, // VSETLNi16
+ 1413578918U, // VSETLNi32
+ 1405190310U, // VSETLNi8
+ 329254065U, // VSHLLi16
+ 328205489U, // VSHLLi32
+ 330302641U, // VSHLLi8
+ 320865457U, // VSHLLsv2i64
+ 321914033U, // VSHLLsv4i32
+ 322962609U, // VSHLLsv8i16
+ 324011185U, // VSHLLuv2i64
+ 325059761U, // VSHLLuv4i32
+ 326108337U, // VSHLLuv8i16
+ 330302647U, // VSHLiv16i8
+ 327156919U, // VSHLiv1i64
+ 328205495U, // VSHLiv2i32
+ 327156919U, // VSHLiv2i64
+ 329254071U, // VSHLiv4i16
+ 328205495U, // VSHLiv4i32
+ 329254071U, // VSHLiv8i16
+ 330302647U, // VSHLiv8i8
+ 322962615U, // VSHLsv16i8
+ 347079863U, // VSHLsv1i64
+ 320865463U, // VSHLsv2i32
+ 347079863U, // VSHLsv2i64
+ 321914039U, // VSHLsv4i16
+ 320865463U, // VSHLsv4i32
+ 321914039U, // VSHLsv8i16
+ 322962615U, // VSHLsv8i8
+ 326108343U, // VSHLuv16i8
+ 348128439U, // VSHLuv1i64
+ 324011191U, // VSHLuv2i32
+ 348128439U, // VSHLuv2i64
+ 325059767U, // VSHLuv4i16
+ 324011191U, // VSHLuv4i32
+ 325059767U, // VSHLuv8i16
+ 326108343U, // VSHLuv8i8
+ 327156924U, // VSHRNv2i32
+ 328205500U, // VSHRNv4i16
+ 329254076U, // VSHRNv8i8
+ 322962626U, // VSHRsv16i8
+ 347079874U, // VSHRsv1i64
+ 320865474U, // VSHRsv2i32
+ 347079874U, // VSHRsv2i64
+ 321914050U, // VSHRsv4i16
+ 320865474U, // VSHRsv4i32
+ 321914050U, // VSHRsv8i16
+ 322962626U, // VSHRsv8i8
+ 326108354U, // VSHRuv16i8
+ 348128450U, // VSHRuv1i64
+ 324011202U, // VSHRuv2i32
+ 348128450U, // VSHRuv2i64
+ 325059778U, // VSHRuv4i16
+ 324011202U, // VSHRuv4i32
+ 325059778U, // VSHRuv8i16
+ 326108354U, // VSHRuv8i8
+ 1288700675U, // VSITOD
+ 1276445443U, // VSITOS
+ 1405191367U, // VSLIv16i8
+ 1418822855U, // VSLIv1i64
+ 1413579975U, // VSLIv2i32
+ 1418822855U, // VSLIv2i64
+ 1412531399U, // VSLIv4i16
+ 1413579975U, // VSLIv4i32
+ 1412531399U, // VSLIv8i16
+ 1405191367U, // VSLIv8i8
+ 1240630476U, // VSQRTD
+ 1241679052U, // VSQRTS
+ 1396770002U, // VSRAsv16i8
+ 1420887250U, // VSRAsv1i64
+ 1394672850U, // VSRAsv2i32
+ 1420887250U, // VSRAsv2i64
+ 1395721426U, // VSRAsv4i16
+ 1394672850U, // VSRAsv4i32
+ 1395721426U, // VSRAsv8i16
+ 1396770002U, // VSRAsv8i8
+ 1399915730U, // VSRAuv16i8
+ 1421935826U, // VSRAuv1i64
+ 1397818578U, // VSRAuv2i32
+ 1421935826U, // VSRAuv2i64
+ 1398867154U, // VSRAuv4i16
+ 1397818578U, // VSRAuv4i32
+ 1398867154U, // VSRAuv8i16
+ 1399915730U, // VSRAuv8i8
+ 1405191383U, // VSRIv16i8
+ 1418822871U, // VSRIv1i64
+ 1413579991U, // VSRIv2i32
+ 1418822871U, // VSRIv2i64
+ 1412531415U, // VSRIv4i16
+ 1413579991U, // VSRIv4i32
+ 1412531415U, // VSRIv8i16
+ 1405191383U, // VSRIv8i8
+ 475563228U, // VST1d16
+ 476611804U, // VST1d32
+ 477660380U, // VST1d64
+ 478708956U, // VST1d8
+ 476611804U, // VST1df
+ 473498844U, // VST1q16
+ 474547420U, // VST1q32
+ 479790300U, // VST1q64
+ 466158812U, // VST1q8
+ 474547420U, // VST1qf
+ 2757264609U, // VST2LNd16
+ 2758313185U, // VST2LNd32
+ 2760410337U, // VST2LNd8
+ 2757264609U, // VST2LNq16a
+ 2757264609U, // VST2LNq16b
+ 2758313185U, // VST2LNq32a
+ 2758313185U, // VST2LNq32b
+ 2354611425U, // VST2d16
+ 2355660001U, // VST2d32
+ 2356708572U, // VST2d64
+ 2357757153U, // VST2d8
+ 2488829153U, // VST2q16
+ 2489877729U, // VST2q32
+ 2491974881U, // VST2q8
+ 2488829158U, // VST3LNd16
+ 2489877734U, // VST3LNd32
+ 2491974886U, // VST3LNd8
+ 2488829158U, // VST3LNq16a
+ 2488829158U, // VST3LNq16b
+ 2489877734U, // VST3LNq32a
+ 2489877734U, // VST3LNq32b
+ 2757264614U, // VST3d16
+ 2758313190U, // VST3d32
+ 2759361756U, // VST3d64
+ 2760410342U, // VST3d8
+ 2488894694U, // VST3q16a
+ 2488894694U, // VST3q16b
+ 2489943270U, // VST3q32a
+ 2489943270U, // VST3q32b
+ 2492040422U, // VST3q8a
+ 2492040422U, // VST3q8b
+ 2220393707U, // VST4LNd16
+ 2221442283U, // VST4LNd32
+ 2223539435U, // VST4LNd8
+ 2220393707U, // VST4LNq16a
+ 2220393707U, // VST4LNq16b
+ 2221442283U, // VST4LNq32a
+ 2221442283U, // VST4LNq32b
+ 2488829163U, // VST4d16
+ 2489877739U, // VST4d32
+ 2490926300U, // VST4d64
+ 2491974891U, // VST4d8
+ 2220459243U, // VST4q16a
+ 2220459243U, // VST4q16b
+ 2221507819U, // VST4q32a
+ 2221507819U, // VST4q32b
+ 2223604971U, // VST4q8a
+ 2223604971U, // VST4q8b
+ 2952791280U, // VSTMD
+ 2952791280U, // VSTMS
+ 345081077U, // VSTRD
+ 271975674U, // VSTRQ
+ 339838197U, // VSTRS
+ 301106433U, // VSUBD
+ 327156998U, // VSUBHNv2i32
+ 328205574U, // VSUBHNv4i16
+ 329254150U, // VSUBHNv8i8
+ 320865549U, // VSUBLsv2i64
+ 321914125U, // VSUBLsv4i32
+ 322962701U, // VSUBLsv8i16
+ 324011277U, // VSUBLuv2i64
+ 325059853U, // VSUBLuv4i32
+ 326108429U, // VSUBLuv8i16
+ 302155009U, // VSUBS
+ 320865555U, // VSUBWsv2i64
+ 321914131U, // VSUBWsv4i32
+ 322962707U, // VSUBWsv8i16
+ 324011283U, // VSUBWuv2i64
+ 325059859U, // VSUBWuv4i32
+ 326108435U, // VSUBWuv8i16
+ 302155009U, // VSUBfd
+ 302155009U, // VSUBfd_sfp
+ 302155009U, // VSUBfq
+ 330302721U, // VSUBv16i8
+ 327156993U, // VSUBv1i64
+ 328205569U, // VSUBv2i32
+ 327156993U, // VSUBv2i64
+ 329254145U, // VSUBv4i16
+ 328205569U, // VSUBv4i32
+ 329254145U, // VSUBv8i16
+ 330302721U, // VSUBv8i8
+ 331449625U, // VTBL1
+ 1405191449U, // VTBL2
+ 465667353U, // VTBL3
+ 2344715545U, // VTBL4
+ 1405191454U, // VTBX1
+ 465667358U, // VTBX2
+ 2344715550U, // VTBX3
+ 2747368734U, // VTBX4
+ 1289749251U, // VTOSIZD
+ 1274348291U, // VTOSIZS
+ 1290797827U, // VTOUIZD
+ 1275396867U, // VTOUIZS
+ 1412531491U, // VTRNd16
+ 1413580067U, // VTRNd32
+ 1405191459U, // VTRNd8
+ 1412531491U, // VTRNq16
+ 1413580067U, // VTRNq32
+ 1405191459U, // VTRNq8
+ 331449640U, // VTSTv16i8
+ 339838248U, // VTSTv2i32
+ 338789672U, // VTSTv4i16
+ 339838248U, // VTSTv4i32
+ 338789672U, // VTSTv8i16
+ 331449640U, // VTSTv8i8
+ 1291846403U, // VUITOD
+ 1277494019U, // VUITOS
+ 1412531501U, // VUZPd16
+ 1413580077U, // VUZPd32
+ 1405191469U, // VUZPd8
+ 1412531501U, // VUZPq16
+ 1413580077U, // VUZPq32
+ 1405191469U, // VUZPq8
+ 1412531506U, // VZIPd16
+ 1413580082U, // VZIPd32
+ 1405191474U, // VZIPd8
+ 1412531506U, // VZIPq16
+ 1413580082U, // VZIPq32
+ 1405191474U, // VZIPq8
+ 134217741U, // t2ADCSri
+ 134219063U, // t2ADCSrr
+ 134219063U, // t2ADCSrs
+ 3090251795U, // t2ADCri
+ 3172106259U, // t2ADCrr
+ 3306323987U, // t2ADCrs
+ 353533975U, // t2ADDSri
+ 353533975U, // t2ADDSrr
+ 1427275799U, // t2ADDSrs
+ 3172106268U, // t2ADDrSPi
+ 271680831U, // t2ADDrSPi12
+ 3306323996U, // t2ADDrSPs
+ 3172106268U, // t2ADDri
+ 3090253119U, // t2ADDri12
+ 3172106268U, // t2ADDrr
+ 3306323996U, // t2ADDrs
+ 3090251846U, // t2ANDri
+ 3172106310U, // t2ANDrr
+ 3306324038U, // t2ANDrs
+ 3172107588U, // t2ASRri
+ 3172107588U, // t2ASRrr
+ 138413384U, // t2B
+ 271679566U, // t2BFC
+ 3090251858U, // t2BICri
+ 3172106322U, // t2BICrr
+ 3306324050U, // t2BICrs
+ 220201080U, // t2BR_JT
+ 890568852U, // t2Bcc
+ 1211203734U, // t2CLZ
+ 1293058202U, // t2CMNzri
+ 1293058202U, // t2CMNzrr
+ 353534106U, // t2CMNzrs
+ 1293058206U, // t2CMPri
+ 1293058206U, // t2CMPrr
+ 353534110U, // t2CMPrs
+ 1293058206U, // t2CMPzri
+ 1293058206U, // t2CMPzrr
+ 353534110U, // t2CMPzrs
+ 3090251938U, // t2EORri
+ 3172106402U, // t2EORrr
+ 3306324130U, // t2EORrs
+ 3355444557U, // t2IT
+ 189U, // t2Int_MemBarrierV7
+ 193U, // t2Int_SyncBarrierV7
+ 221250896U, // t2Int_eh_sjlj_setjmp
+ 1698693327U, // t2LDM
+ 1698693327U, // t2LDM_RET
+ 1345421527U, // t2LDRB_POST
+ 1345421527U, // t2LDRB_PRE
+ 353534167U, // t2LDRBi12
+ 271679703U, // t2LDRBi8
+ 1293058263U, // t2LDRBpci
+ 1427275991U, // t2LDRBs
+ 1345421532U, // t2LDRDi8
+ 271679708U, // t2LDRDpci
+ 1211203809U, // t2LDREX
+ 1211203815U, // t2LDREXB
+ 271679726U, // t2LDREXD
+ 1211203829U, // t2LDREXH
+ 1345421564U, // t2LDRH_POST
+ 1345421564U, // t2LDRH_PRE
+ 353534204U, // t2LDRHi12
+ 271679740U, // t2LDRHi8
+ 1293058300U, // t2LDRHpci
+ 1427276028U, // t2LDRHs
+ 1345421569U, // t2LDRSB_POST
+ 1345421569U, // t2LDRSB_PRE
+ 353534209U, // t2LDRSBi12
+ 271679745U, // t2LDRSBi8
+ 1293058305U, // t2LDRSBpci
+ 1427276033U, // t2LDRSBs
+ 1345421575U, // t2LDRSH_POST
+ 1345421575U, // t2LDRSH_PRE
+ 353534215U, // t2LDRSHi12
+ 271679751U, // t2LDRSHi8
+ 1293058311U, // t2LDRSHpci
+ 1427276039U, // t2LDRSHs
+ 1345421523U, // t2LDR_POST
+ 1345421523U, // t2LDR_PRE
+ 353534163U, // t2LDRi12
+ 271679699U, // t2LDRi8
+ 1293058259U, // t2LDRpci
+ 134219100U, // t2LDRpci_pic
+ 1427275987U, // t2LDRs
+ 1293550949U, // t2LEApcrel
+ 354026853U, // t2LEApcrelJT
+ 3172107625U, // t2LSLri
+ 3172107625U, // t2LSLrr
+ 3172107629U, // t2LSRri
+ 3172107629U, // t2LSRrr
+ 1345421587U, // t2MLA
+ 1345421591U, // t2MLS
+ 1427277124U, // t2MOVCCasr
+ 353534235U, // t2MOVCCi
+ 1427277161U, // t2MOVCClsl
+ 1427277165U, // t2MOVCClsr
+ 353534235U, // t2MOVCCr
+ 1427277169U, // t2MOVCCror
+ 271679775U, // t2MOVTi16
+ 3579478299U, // t2MOVi
+ 1211203876U, // t2MOVi16
+ 1211203876U, // t2MOVi32imm
+ 3579478299U, // t2MOVr
+ 3579512181U, // t2MOVrx
+ 134219129U, // t2MOVsra_flag
+ 134219137U, // t2MOVsrl_flag
+ 271679790U, // t2MUL
+ 3579511090U, // t2MVNi
+ 1293058354U, // t2MVNr
+ 353534258U, // t2MVNs
+ 3090253193U, // t2ORNri
+ 3090253193U, // t2ORNrr
+ 3224470921U, // t2ORNrs
+ 3090252086U, // t2ORRri
+ 3172106550U, // t2ORRrr
+ 3306324278U, // t2ORRrs
+ 1345421628U, // t2PKHBT
+ 1345421634U, // t2PKHTB
+ 1211203912U, // t2RBIT
+ 1293058381U, // t2REV
+ 1293058385U, // t2REV16
+ 1293058391U, // t2REVSH
+ 3172107633U, // t2RORri
+ 3172107633U, // t2RORrr
+ 3623879010U, // t2RSBSri
+ 3492905314U, // t2RSBSrs
+ 353534306U, // t2RSBri
+ 1345421666U, // t2RSBrs
+ 134218096U, // t2SBCSri
+ 134219149U, // t2SBCSrr
+ 134219149U, // t2SBCSrs
+ 3090252150U, // t2SBCri
+ 3172106614U, // t2SBCrr
+ 3306324342U, // t2SBCrs
+ 1345421690U, // t2SBFX
+ 1345421695U, // t2SMLABB
+ 1345421702U, // t2SMLABT
+ 1345421709U, // t2SMLAL
+ 1345421715U, // t2SMLATB
+ 1345421722U, // t2SMLATT
+ 1345421729U, // t2SMLAWB
+ 1345421736U, // t2SMLAWT
+ 1345421743U, // t2SMMLA
+ 1345421749U, // t2SMMLS
+ 271679931U, // t2SMMUL
+ 271679937U, // t2SMULBB
+ 271679944U, // t2SMULBT
+ 1345421775U, // t2SMULL
+ 271679957U, // t2SMULTB
+ 271679964U, // t2SMULTT
+ 271679971U, // t2SMULWB
+ 271679978U, // t2SMULWT
+ 1698693617U, // t2STM
+ 1345323513U, // t2STRB_POST
+ 1345323513U, // t2STRB_PRE
+ 353534457U, // t2STRBi12
+ 271679993U, // t2STRBi8
+ 1427276281U, // t2STRBs
+ 1345421822U, // t2STRDi8
+ 271680003U, // t2STREX
+ 271680009U, // t2STREXB
+ 1345421840U, // t2STREXD
+ 271680023U, // t2STREXH
+ 1345323550U, // t2STRH_POST
+ 1345323550U, // t2STRH_PRE
+ 353534494U, // t2STRHi12
+ 271680030U, // t2STRHi8
+ 1427276318U, // t2STRHs
+ 1345323509U, // t2STR_POST
+ 1345323509U, // t2STR_PRE
+ 353534453U, // t2STRi12
+ 271679989U, // t2STRi8
+ 1427276277U, // t2STRs
+ 353534499U, // t2SUBSri
+ 353534499U, // t2SUBSrr
+ 1427276323U, // t2SUBSrs
+ 3172106792U, // t2SUBrSPi
+ 271680917U, // t2SUBrSPi12
+ 134219162U, // t2SUBrSPi12_
+ 134219170U, // t2SUBrSPi_
+ 3224470056U, // t2SUBrSPs
+ 134219179U, // t2SUBrSPs_
+ 3172106792U, // t2SUBri
+ 3090253205U, // t2SUBri12
+ 3172106792U, // t2SUBrr
+ 3306324520U, // t2SUBrs
+ 271680044U, // t2SXTABrr
+ 1345421868U, // t2SXTABrr_rot
+ 271680050U, // t2SXTAHrr
+ 1345421874U, // t2SXTAHrr_rot
+ 1293058616U, // t2SXTBr
+ 353534520U, // t2SXTBr_rot
+ 1293058621U, // t2SXTHr
+ 353534525U, // t2SXTHr_rot
+ 3758097842U, // t2TBB
+ 3758097847U, // t2TBH
+ 1293058626U, // t2TEQri
+ 1293058626U, // t2TEQrr
+ 353534530U, // t2TEQrs
+ 582U, // t2TPsoft
+ 1293058649U, // t2TSTri
+ 1293058649U, // t2TSTrr
+ 353534553U, // t2TSTrs
+ 1345421917U, // t2UBFX
+ 1345421922U, // t2UMAAL
+ 1345421928U, // t2UMLAL
+ 1345421934U, // t2UMULL
+ 271680116U, // t2UXTABrr
+ 1345421940U, // t2UXTABrr_rot
+ 271680122U, // t2UXTAHrr
+ 1345421946U, // t2UXTAHrr_rot
+ 1293058688U, // t2UXTB16r
+ 353534592U, // t2UXTB16r_rot
+ 1293058695U, // t2UXTBr
+ 353534599U, // t2UXTBr_rot
+ 1293058700U, // t2UXTHr
+ 353534604U, // t2UXTHr_rot
+ 3983245331U, // tADC
+ 271679516U, // tADDhirr
+ 3982557212U, // tADDi3
+ 3983245340U, // tADDi8
+ 225445308U, // tADDrPCi
+ 134284732U, // tADDrSP
+ 134219196U, // tADDrSPi
+ 3982557212U, // tADDrr
+ 135005628U, // tADDspi
+ 134284732U, // tADDspr
+ 134284737U, // tADDspr_
+ 138413512U, // tADJCALLSTACKDOWN
+ 138413533U, // tADJCALLSTACKUP
+ 3983245382U, // tAND
+ 134284784U, // tANDsp
+ 3982558532U, // tASRri
+ 3983246660U, // tASRrr
+ 138412107U, // tB
+ 3983245394U, // tBIC
+ 671088726U, // tBL
+ 671088730U, // tBLXi
+ 671088730U, // tBLXi_r9
+ 138412122U, // tBLXr
+ 138412122U, // tBLXr_r9
+ 671088726U, // tBLr9
+ 138412152U, // tBRIND
+ 226492536U, // tBR_JTr
+ 138412161U, // tBX
+ 1527U, // tBX_RET
+ 138412130U, // tBX_RET_vararg
+ 138412161U, // tBXr9
+ 808550548U, // tBcc
+ 227541078U, // tBfar
+ 134219261U, // tCBNZ
+ 134219267U, // tCBZ
+ 1211203738U, // tCMNz
+ 1211203742U, // tCMPhir
+ 1211203742U, // tCMPi8
+ 1211203742U, // tCMPr
+ 1211203742U, // tCMPzhir
+ 1211203742U, // tCMPzi8
+ 1211203742U, // tCMPzr
+ 3983245474U, // tEOR
+ 228591112U, // tInt_eh_sjlj_setjmp
+ 1613955279U, // tLDM
+ 1345421523U, // tLDR
+ 1345421527U, // tLDRB
+ 1345421527U, // tLDRBi
+ 1345421564U, // tLDRH
+ 1345421564U, // tLDRHi
+ 271679745U, // tLDRSB
+ 271679751U, // tLDRSH
+ 1211203795U, // tLDRcp
+ 1345421523U, // tLDRi
+ 1303380179U, // tLDRpci
+ 134219325U, // tLDRpci_pic
+ 271679699U, // tLDRspi
+ 1211204965U, // tLEApcrel
+ 271680869U, // tLEApcrelJT
+ 3982558569U, // tLSLri
+ 3983246697U, // tLSLrr
+ 3982558573U, // tLSRri
+ 3983246701U, // tLSRrr
+ 271679771U, // tMOVCCi
+ 271679771U, // tMOVCCr
+ 272631366U, // tMOVCCr_pseudo
+ 134219345U, // tMOVSr
+ 134219351U, // tMOVgpr2gpr
+ 134219351U, // tMOVgpr2tgpr
+ 3989111067U, // tMOVi8
+ 134219351U, // tMOVr
+ 134219351U, // tMOVtgpr2gpr
+ 3983245614U, // tMUL
+ 3989111090U, // tMVN
+ 3983245622U, // tORR
+ 1976566074U, // tPICADD
+ 1077708380U, // tPOP
+ 1077708380U, // tPOP_RET
+ 1077708384U, // tPUSH
+ 1211203917U, // tREV
+ 1211203921U, // tREV16
+ 1211203927U, // tREVSH
+ 3983246705U, // tROR
+ 3989078370U, // tRSB
+ 271679699U, // tRestore
+ 3983245686U, // tSBC
+ 1613955569U, // tSTM
+ 1345421813U, // tSTR
+ 1345421817U, // tSTRB
+ 1345421817U, // tSTRBi
+ 1345421854U, // tSTRH
+ 1345421854U, // tSTRHi
+ 1345421813U, // tSTRi
+ 271679989U, // tSTRspi
+ 3982557736U, // tSUBi3
+ 3983245864U, // tSUBi8
+ 3982557736U, // tSUBrr
+ 135005797U, // tSUBspi
+ 135005611U, // tSUBspi_
+ 1211204152U, // tSXTB
+ 1211204157U, // tSXTH
+ 271679989U, // tSpill
+ 582U, // tTPsoft
+ 1211204185U, // tTST
+ 1211204231U, // tUXTB
+ 1211204236U, // tUXTH
0U
};
const char *AsmStrs =
- "adcs\t\000adcs\t\000adc\000adds\000add\000@ ADJCALLSTACKDOWN \000@ ADJC"
- "ALLSTACKUP \000and\000\000b\t\000bfc\000bic\000bl\t\000blx\t\000bl\000b"
- "x\t\000add\tpc, \000ldr\tpc, \000mov\tpc, \000mov\tlr, pc\n\tbx\t\000bx"
- "\000b\000clz\000cmn\000cmp\000eor\000vmov\000vmrs\000mcr\tp15, 0, \000d"
- "mb\000dsb\000str\tsp, [\000ldm\000ldr\000ldrb\000ldrd\000ldrex\000ldrex"
- "b\000ldrexd\000ldrexh\000ldrh\000ldrsb\000ldrsh\000.set \000mla\000mls\000"
- "mov\000movt\000movw\000movs\000mul\000mvn\000orr\000\n\000pkhbt\000pkht"
- "b\000rev\000rev16\000revsh\000rsbs\000rsb\000rscs\t\000rsc\000sbcs\t\000"
- "sbc\000sbfx\000smlabb\000smlabt\000smlal\000smlatb\000smlatt\000smlawb\000"
- "smlawt\000smmla\000smmls\000smmul\000smulbb\000smulbt\000smull\000smult"
- "b\000smultt\000smulwb\000smulwt\000stm\000str\000strb\000strd\000strex\000"
- "strexb\000strexd\000strexh\000strh\000subs\000sub\000sxtab\000sxtah\000"
- "sxtb\000sxth\000teq\000bl\t__aeabi_read_tp\000tst\000ubfx\000umaal\000u"
- "mlal\000umull\000uxtab\000uxtah\000uxtb16\000uxtb\000uxth\000vabal\000v"
- "aba\000vabdl\000vabd\000vabs\000vacge\000vacgt\000vadd\000vaddhn\000vad"
- "dl\000vaddw\000vand\000vbic\000vbsl\000vceq\000vcge\000vcgt\000vcls\000"
- "vclz\000vcmpe\000vcnt\000vcvt\000vdiv\000vdup\000veor\000vext\000vhadd\000"
- "vhsub\000vld1\000vld2\000vld3\000vld4\000vldm\000vldr\000vldmia\000vmax"
- "\000vmin\000vmla\000vmlal\000vmls\000vmlsl\000vmovl\000vmovn\000vmul\000"
- "vmull\000vmvn\000vneg\000vnmla\000vnmls\000vnmul\000vorn\000vorr\000vpa"
- "dal\000vpaddl\000vpadd\000vpmax\000vpmin\000vqabs\000vqadd\000vqdmlal\000"
- "vqdmlsl\000vqdmulh\000vqdmull\000vqmovun\000vqmovn\000vqneg\000vqrdmulh"
- "\000vqrshl\000vqrshrn\000vqrshrun\000vqshl\000vqshlu\000vqshrn\000vqshr"
- "un\000vqsub\000vraddhn\000vrecpe\000vrecps\000vrev16\000vrev32\000vrev6"
- "4\000vrhadd\000vrshl\000vrshrn\000vrshr\000vrsqrte\000vrsqrts\000vrsra\000"
- "vrsubhn\000vshll\000vshl\000vshrn\000vshr\000vsli\000vsqrt\000vsra\000v"
- "sri\000vst1\000vst2\000vst3\000vst4\000vstm\000vstr\000vstmia\000vsub\000"
- "vsubhn\000vsubl\000vsubw\000vtbl\000vtbx\000vtrn\000vtst\000vuzp\000vzi"
- "p\000adcs.w\t\000addw\000asr\000b.w\t\000it\000str.w\tsp, [\000@ ldr.w\t"
- "\000adr\000lsl\000lsr\000ror\000rrx\000asrs.w\t\000lsrs.w\t\000orn\000s"
- "bcs.w\t\000subw\000@ subw\t\000@ sub.w\t\000@ sub\t\000tbb\t\000tbh\t\000"
- "add\t\000@ add\t\000@ tADJCALLSTACKDOWN \000@ tADJCALLSTACKUP \000@ and"
- "\t\000bx\tlr\000cbnz\t\000cbz\t\000mov\tr12, r1\t@ begin eh.setjmp\n\tm"
- "ov\tr1, sp\n\tstr\tr1, [\000@ ldr.n\t\000@ tMOVCCr \000movs\t\000mov\t\000"
- "pop\000push\000sub\t\000";
+ "DEBUG_VALUE\000adcs\t\000adc\000adds\000add\000@ ADJCALLSTACKDOWN \000@"
+ " ADJCALLSTACKUP \000and\000\000b\t\000bfc\000bic\000bl\t\000blx\t\000bl"
+ "\000bx\t\000add\tpc, \000ldr\tpc, \000mov\tpc, \000mov\tlr, pc\n\tbx\t\000"
+ "bx\000b\000clz\000cmn\000cmp\000eor\000vmov\000vmrs\000mcr\tp15, 0, \000"
+ "dmb\000dsb\000str\tsp, [\000ldm\000ldr\000ldrb\000ldrd\000ldrex\000ldre"
+ "xb\000ldrexd\000ldrexh\000ldrh\000ldrsb\000ldrsh\000.set \000mla\000mls"
+ "\000mov\000movt\000movw\000movs\000mul\000mvn\000orr\000\n\000pkhbt\000"
+ "pkhtb\000rbit\000rev\000rev16\000revsh\000rsbs\000rsb\000rscs\t\000rsc\000"
+ "sbcs\t\000sbc\000sbfx\000smlabb\000smlabt\000smlal\000smlatb\000smlatt\000"
+ "smlawb\000smlawt\000smmla\000smmls\000smmul\000smulbb\000smulbt\000smul"
+ "l\000smultb\000smultt\000smulwb\000smulwt\000stm\000str\000strb\000strd"
+ "\000strex\000strexb\000strexd\000strexh\000strh\000subs\000sub\000sxtab"
+ "\000sxtah\000sxtb\000sxth\000teq\000bl\t__aeabi_read_tp\000tst\000ubfx\000"
+ "umaal\000umlal\000umull\000uxtab\000uxtah\000uxtb16\000uxtb\000uxth\000"
+ "vabal\000vaba\000vabdl\000vabd\000vabs\000vacge\000vacgt\000vadd\000vad"
+ "dhn\000vaddl\000vaddw\000vand\000vbic\000vbsl\000vceq\000vcge\000vcgt\000"
+ "vcls\000vclz\000vcmpe\000vcnt\000vcvt\000vdiv\000vdup\000veor\000vext\000"
+ "vhadd\000vhsub\000vld1\000vld2\000vld3\000vld4\000vldm\000vldr\000vldmi"
+ "a\000vmax\000vmin\000vmla\000vmlal\000vmls\000vmlsl\000vmovl\000vmovn\000"
+ "vmul\000vmull\000vmvn\000vneg\000vnmla\000vnmls\000vnmul\000vorn\000vor"
+ "r\000vpadal\000vpaddl\000vpadd\000vpmax\000vpmin\000vqabs\000vqadd\000v"
+ "qdmlal\000vqdmlsl\000vqdmulh\000vqdmull\000vqmovun\000vqmovn\000vqneg\000"
+ "vqrdmulh\000vqrshl\000vqrshrn\000vqrshrun\000vqshl\000vqshlu\000vqshrn\000"
+ "vqshrun\000vqsub\000vraddhn\000vrecpe\000vrecps\000vrev16\000vrev32\000"
+ "vrev64\000vrhadd\000vrshl\000vrshrn\000vrshr\000vrsqrte\000vrsqrts\000v"
+ "rsra\000vrsubhn\000vshll\000vshl\000vshrn\000vshr\000vsli\000vsqrt\000v"
+ "sra\000vsri\000vst1\000vst2\000vst3\000vst4\000vstm\000vstr\000vstmia\000"
+ "vsub\000vsubhn\000vsubl\000vsubw\000vtbl\000vtbx\000vtrn\000vtst\000vuz"
+ "p\000vzip\000adcs.w\t\000addw\000asr\000b.w\t\000it\000str.w\tsp, [\000"
+ "@ ldr.w\t\000adr\000lsl\000lsr\000ror\000rrx\000asrs.w\t\000lsrs.w\t\000"
+ "orn\000sbcs.w\t\000subw\000@ subw\t\000@ sub.w\t\000@ sub\t\000tbb\t\000"
+ "tbh\t\000add\t\000@ add\t\000@ tADJCALLSTACKDOWN \000@ tADJCALLSTACKUP "
+ "\000@ and\t\000bx\tlr\000cbnz\t\000cbz\t\000mov\tr12, r1\t@ begin eh.se"
+ "tjmp\n\tmov\tr1, sp\n\tstr\tr1, [\000@ ldr.n\t\000@ tMOVCCr \000movs\t\000"
+ "mov\t\000pop\000push\000sub\t\000";
#ifndef NO_ASM_WRITER_BOILERPLATE
@@ -1598,60 +1600,60 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
switch ((Bits >> 27) & 31) {
default: // unreachable.
case 0:
+ // DEBUG_VALUE, Int_MemBarrierV7, Int_SyncBarrierV7, TPsoft, t2Int_MemBar...
+ return;
+ break;
+ case 1:
// ADCSSri, ADCSSrr, ADCSSrs, ADJCALLSTACKDOWN, ADJCALLSTACKUP, B, BLX, B...
printOperand(MI, 0);
break;
- case 1:
+ case 2:
// ADCri, ADCrr, ADDSri, ADDSrr, ADDri, ADDrr, ANDri, ANDrr, BFC, BICri, ...
printPredicateOperand(MI, 3);
break;
- case 2:
+ case 3:
// ADCrs, ADDSrs, ADDrs, ANDrs, BICrs, EORrs, LDRB_POST, LDRB_PRE, LDRD, ...
printPredicateOperand(MI, 5);
break;
- case 3:
+ case 4:
// ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32, ATOMIC_CMP_SWAP_I8, ATOMIC_L...
PrintSpecial(MI, "comment");
break;
- case 4:
+ case 5:
// BL, BLr9, tBL, tBLXi, tBLXi_r9, tBLr9
printOperand(MI, 0, "call");
return;
break;
- case 5:
+ case 6:
// BL_pred, BLr9_pred, Bcc, VCMPEZD, VCMPEZS, t2Bcc, tBcc
printPredicateOperand(MI, 1);
break;
- case 6:
+ case 7:
// BR_JTm
printAddrMode2Operand(MI, 0);
O << " \n";
printJTBlockOperand(MI, 3);
return;
break;
- case 7:
+ case 8:
// BX_RET, FMSTAT, tPOP, tPOP_RET, tPUSH
printPredicateOperand(MI, 0);
break;
- case 8:
- // CLZ, CMNri, CMNrr, CMNzri, CMNzrr, CMPri, CMPrr, CMPzri, CMPzrr, FCONS...
+ case 9:
+ // CLZ, CMNzri, CMNzrr, CMPri, CMPrr, CMPzri, CMPzrr, FCONSTD, FCONSTS, L...
printPredicateOperand(MI, 2);
break;
- case 9:
- // CMNrs, CMNzrs, CMPrs, CMPzrs, LDR, LDRB, LDRH, LDRSB, LDRSH, LDRcp, ML...
+ case 10:
+ // CMNzrs, CMPrs, CMPzrs, LDR, LDRB, LDRH, LDRSB, LDRSH, LDRcp, MLA, MLS,...
printPredicateOperand(MI, 4);
break;
- case 10:
+ case 11:
// CONSTPOOL_ENTRY
printCPInstOperand(MI, 0, "label");
O << ' ';
printCPInstOperand(MI, 1, "cpentry");
return;
break;
- case 11:
- // Int_MemBarrierV7, Int_SyncBarrierV7, TPsoft, t2Int_MemBarrierV7, t2Int...
- return;
- break;
case 12:
// LDM, LDM_RET, STM, t2LDM, t2LDM_RET, t2STM, tLDM, tSTM
printAddrMode4Operand(MI, 0, "submode");
@@ -1781,7 +1783,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 3:
- // ADDSri, ADDSrr, ADDSrs, BFC, BL_pred, BLr9_pred, Bcc, CLZ, CMNri, CMNr...
+ // ADDSri, ADDSrr, ADDSrs, BFC, BL_pred, BLr9_pred, Bcc, CLZ, CMNzri, CMN...
O << "\t";
break;
case 4:
@@ -2392,7 +2394,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
break;
case 3:
- // ADDSri, ADDSrr, ADDSrs, BFC, Bcc, CLZ, CMNri, CMNrr, CMNrs, CMNzri, CM...
+ // ADDSri, ADDSrr, ADDSrs, BFC, Bcc, CLZ, CMNzri, CMNzrr, CMNzrs, CMPri, ...
printOperand(MI, 0);
break;
case 4:
@@ -2478,9 +2480,9 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case 19:
// VST3q16a, VST3q16b, VST3q32a, VST3q32b, VST3q8a, VST3q8b, VST4q16a, VS...
printOperand(MI, 5);
- O << ',';
+ O << ", ";
printOperand(MI, 6);
- O << ',';
+ O << ", ";
printOperand(MI, 7);
break;
case 20:
@@ -2527,9 +2529,6 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::ADCSSrs:
case ARM::BFC:
case ARM::CLZ:
- case ARM::CMNri:
- case ARM::CMNrr:
- case ARM::CMNrs:
case ARM::CMNzri:
case ARM::CMNzrr:
case ARM::CMNzrs:
@@ -2552,6 +2551,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::MOVTi16:
case ARM::MOVi16:
case ARM::MOVi2pieces:
+ case ARM::RBIT:
case ARM::REV:
case ARM::REV16:
case ARM::REVSH:
@@ -3085,12 +3085,6 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VTRNq16:
case ARM::VTRNq32:
case ARM::VTRNq8:
- case ARM::VTSTv16i8:
- case ARM::VTSTv2i32:
- case ARM::VTSTv4i16:
- case ARM::VTSTv4i32:
- case ARM::VTSTv8i16:
- case ARM::VTSTv8i8:
case ARM::VUZPd16:
case ARM::VUZPd32:
case ARM::VUZPd8:
@@ -3117,6 +3111,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::t2LDRi8:
case ARM::t2MOVTi16:
case ARM::t2MOVi16:
+ case ARM::t2RBIT:
case ARM::t2SBCSri:
case ARM::t2SBCSrr:
case ARM::t2SBCSrs:
@@ -3132,7 +3127,6 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::tADDrSPi:
case ARM::tADDrr:
case ARM::tASRri:
- case ARM::tCMN:
case ARM::tCMNz:
case ARM::tCMPhir:
case ARM::tCMPi8:
@@ -3142,10 +3136,13 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::tCMPzr:
case ARM::tLDR:
case ARM::tLDRB:
+ case ARM::tLDRBi:
case ARM::tLDRH:
+ case ARM::tLDRHi:
case ARM::tLDRSB:
case ARM::tLDRSH:
case ARM::tLDRcp:
+ case ARM::tLDRi:
case ARM::tLDRspi:
case ARM::tLSLri:
case ARM::tLSRri:
@@ -3157,7 +3154,10 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::tRestore:
case ARM::tSTR:
case ARM::tSTRB:
+ case ARM::tSTRBi:
case ARM::tSTRH:
+ case ARM::tSTRHi:
+ case ARM::tSTRi:
case ARM::tSTRspi:
case ARM::tSUBi3:
case ARM::tSUBrr:
@@ -3567,12 +3567,6 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VSUBv4i32:
case ARM::VSUBv8i16:
case ARM::VSUBv8i8:
- case ARM::VTSTv16i8:
- case ARM::VTSTv2i32:
- case ARM::VTSTv4i16:
- case ARM::VTSTv4i32:
- case ARM::VTSTv8i16:
- case ARM::VTSTv8i8:
case ARM::t2ADCSri:
case ARM::t2ADCSrr:
case ARM::t2LDRDpci:
@@ -3591,11 +3585,11 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::BFC:
case ARM::t2BFC: printBitfieldInvMaskImmOperand(MI, 2); break;
case ARM::CLZ:
- case ARM::CMNrr:
case ARM::CMNzrr:
case ARM::CMPrr:
case ARM::CMPzrr:
case ARM::MOVi16:
+ case ARM::RBIT:
case ARM::REV:
case ARM::REV16:
case ARM::REVSH:
@@ -3656,7 +3650,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VZIPq8:
case ARM::t2CLZ:
case ARM::t2MOVi16:
- case ARM::tCMN:
+ case ARM::t2RBIT:
case ARM::tCMNz:
case ARM::tCMPhir:
case ARM::tCMPi8:
@@ -3673,13 +3667,11 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::tTST:
case ARM::tUXTB:
case ARM::tUXTH: printOperand(MI, 1); break;
- case ARM::CMNri:
case ARM::CMNzri:
case ARM::CMPri:
case ARM::CMPzri:
case ARM::TEQri:
case ARM::TSTri: printSOImmOperand(MI, 1); break;
- case ARM::CMNrs:
case ARM::CMNzrs:
case ARM::CMPrs:
case ARM::CMPzrs:
@@ -3803,11 +3795,17 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::t2STRDi8: printT2AddrModeImm8s4Operand(MI, 2); break;
case ARM::tADDrSPi: printThumbS4ImmOperand(MI, 2); break;
case ARM::tLDR:
- case ARM::tSTR: printThumbAddrModeS4Operand(MI, 1); break;
+ case ARM::tLDRi:
+ case ARM::tSTR:
+ case ARM::tSTRi: printThumbAddrModeS4Operand(MI, 1); break;
case ARM::tLDRB:
- case ARM::tSTRB: printThumbAddrModeS1Operand(MI, 1); break;
+ case ARM::tLDRBi:
+ case ARM::tSTRB:
+ case ARM::tSTRBi: printThumbAddrModeS1Operand(MI, 1); break;
case ARM::tLDRH:
- case ARM::tSTRH: printThumbAddrModeS2Operand(MI, 1); break;
+ case ARM::tLDRHi:
+ case ARM::tSTRH:
+ case ARM::tSTRHi: printThumbAddrModeS2Operand(MI, 1); break;
case ARM::tLDRSB:
case ARM::tLDRSH: printThumbAddrModeRROperand(MI, 1); break;
case ARM::tLDRspi:
@@ -3957,6 +3955,12 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VORNq:
case ARM::VORRd:
case ARM::VORRq:
+ case ARM::VTSTv16i8:
+ case ARM::VTSTv2i32:
+ case ARM::VTSTv4i16:
+ case ARM::VTSTv4i32:
+ case ARM::VTSTv8i16:
+ case ARM::VTSTv8i8:
case ARM::t2ADCri:
case ARM::t2ADDrSPi12:
case ARM::t2ADDri12:
@@ -4017,6 +4021,12 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VORNq:
case ARM::VORRd:
case ARM::VORRq:
+ case ARM::VTSTv16i8:
+ case ARM::VTSTv2i32:
+ case ARM::VTSTv4i16:
+ case ARM::VTSTv4i32:
+ case ARM::VTSTv8i16:
+ case ARM::VTSTv8i8:
case ARM::t2ADCri:
case ARM::t2ADDrSPi12:
case ARM::t2ADDri12:
@@ -4091,9 +4101,6 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VRSQRTEfq:
case ARM::VSQRTD:
case ARM::VSQRTS:
- case ARM::t2CMNri:
- case ARM::t2CMNrr:
- case ARM::t2CMNrs:
case ARM::t2CMNzri:
case ARM::t2CMNzrr:
case ARM::t2CMNzrs:
@@ -4168,8 +4175,6 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VRSQRTEfq:
case ARM::VSQRTD:
case ARM::VSQRTS:
- case ARM::t2CMNri:
- case ARM::t2CMNrr:
case ARM::t2CMNzri:
case ARM::t2CMNzrr:
case ARM::t2CMPri:
@@ -4208,7 +4213,6 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VNEGScc:
case ARM::t2MOVCCi:
case ARM::t2MOVCCr: printOperand(MI, 2); break;
- case ARM::t2CMNrs:
case ARM::t2CMNzrs:
case ARM::t2CMPrs:
case ARM::t2CMPzrs:
@@ -4760,7 +4764,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VLD2LNq32b:
O << '[';
printNoHashImmediate(MI, 8);
- O << "],";
+ O << "], ";
printOperand(MI, 1);
O << '[';
printNoHashImmediate(MI, 8);
@@ -4772,7 +4776,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VLD2d32:
case ARM::VLD2d64:
case ARM::VLD2d8:
- O << ',';
+ O << ", ";
printOperand(MI, 1);
O << "}, ";
printAddrMode6Operand(MI, 2);
@@ -4791,11 +4795,11 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VLD4q32b:
case ARM::VLD4q8a:
case ARM::VLD4q8b:
- O << ',';
+ O << ", ";
printOperand(MI, 1);
- O << ',';
+ O << ", ";
printOperand(MI, 2);
- O << ',';
+ O << ", ";
printOperand(MI, 3);
O << "}, ";
switch (MI->getOpcode()) {
@@ -4824,11 +4828,11 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VLD3LNq32b:
O << '[';
printNoHashImmediate(MI, 10);
- O << "],";
+ O << "], ";
printOperand(MI, 1);
O << '[';
printNoHashImmediate(MI, 10);
- O << "],";
+ O << "], ";
printOperand(MI, 2);
O << '[';
printNoHashImmediate(MI, 10);
@@ -4846,9 +4850,9 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VLD3q32b:
case ARM::VLD3q8a:
case ARM::VLD3q8b:
- O << ',';
+ O << ", ";
printOperand(MI, 1);
- O << ',';
+ O << ", ";
printOperand(MI, 2);
O << "}, ";
switch (MI->getOpcode()) {
@@ -4874,15 +4878,15 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VLD4LNq32b:
O << '[';
printNoHashImmediate(MI, 12);
- O << "],";
+ O << "], ";
printOperand(MI, 1);
O << '[';
printNoHashImmediate(MI, 12);
- O << "],";
+ O << "], ";
printOperand(MI, 2);
O << '[';
printNoHashImmediate(MI, 12);
- O << "],";
+ O << "], ";
printOperand(MI, 3);
O << '[';
printNoHashImmediate(MI, 12);
@@ -5003,7 +5007,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VST2LNq32b:
O << '[';
printNoHashImmediate(MI, 6);
- O << "],";
+ O << "], ";
printOperand(MI, 5);
O << '[';
printNoHashImmediate(MI, 6);
@@ -5015,7 +5019,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VST2d32:
case ARM::VST2d64:
case ARM::VST2d8:
- O << ',';
+ O << ", ";
printOperand(MI, 5);
O << "}, ";
printAddrMode6Operand(MI, 0);
@@ -5028,11 +5032,11 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VST4d32:
case ARM::VST4d64:
case ARM::VST4d8:
- O << ',';
+ O << ", ";
printOperand(MI, 5);
- O << ',';
+ O << ", ";
printOperand(MI, 6);
- O << ',';
+ O << ", ";
printOperand(MI, 7);
O << "}, ";
printAddrMode6Operand(MI, 0);
@@ -5047,11 +5051,11 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VST3LNq32b:
O << '[';
printNoHashImmediate(MI, 7);
- O << "],";
+ O << "], ";
printOperand(MI, 5);
O << '[';
printNoHashImmediate(MI, 7);
- O << "],";
+ O << "], ";
printOperand(MI, 6);
O << '[';
printNoHashImmediate(MI, 7);
@@ -5063,9 +5067,9 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VST3d32:
case ARM::VST3d64:
case ARM::VST3d8:
- O << ',';
+ O << ", ";
printOperand(MI, 5);
- O << ',';
+ O << ", ";
printOperand(MI, 6);
O << "}, ";
printAddrMode6Operand(MI, 0);
@@ -5080,15 +5084,15 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VST4LNq32b:
O << '[';
printNoHashImmediate(MI, 8);
- O << "],";
+ O << "], ";
printOperand(MI, 5);
O << '[';
printNoHashImmediate(MI, 8);
- O << "],";
+ O << "], ";
printOperand(MI, 6);
O << '[';
printNoHashImmediate(MI, 8);
- O << "],";
+ O << "], ";
printOperand(MI, 7);
O << '[';
printNoHashImmediate(MI, 8);
@@ -5102,7 +5106,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VST4q32b:
case ARM::VST4q8a:
case ARM::VST4q8b:
- O << ',';
+ O << ", ";
printOperand(MI, 8);
O << "}, ";
printAddrMode6Operand(MI, 1);
@@ -5118,7 +5122,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VTBL2:
O << ", {";
printOperand(MI, 1);
- O << ',';
+ O << ", ";
printOperand(MI, 2);
O << "}, ";
printOperand(MI, 3);
@@ -5127,9 +5131,9 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VTBL3:
O << ", {";
printOperand(MI, 1);
- O << ',';
+ O << ", ";
printOperand(MI, 2);
- O << ',';
+ O << ", ";
printOperand(MI, 3);
O << "}, ";
printOperand(MI, 4);
@@ -5138,11 +5142,11 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VTBL4:
O << ", {";
printOperand(MI, 1);
- O << ',';
+ O << ", ";
printOperand(MI, 2);
- O << ',';
+ O << ", ";
printOperand(MI, 3);
- O << ',';
+ O << ", ";
printOperand(MI, 4);
O << "}, ";
printOperand(MI, 5);
@@ -5158,7 +5162,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VTBX2:
O << ", {";
printOperand(MI, 2);
- O << ',';
+ O << ", ";
printOperand(MI, 3);
O << "}, ";
printOperand(MI, 4);
@@ -5167,9 +5171,9 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VTBX3:
O << ", {";
printOperand(MI, 2);
- O << ',';
+ O << ", ";
printOperand(MI, 3);
- O << ',';
+ O << ", ";
printOperand(MI, 4);
O << "}, ";
printOperand(MI, 5);
@@ -5178,11 +5182,11 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
case ARM::VTBX4:
O << ", {";
printOperand(MI, 2);
- O << ',';
+ O << ", ";
printOperand(MI, 3);
- O << ',';
+ O << ", ";
printOperand(MI, 4);
- O << ',';
+ O << ", ";
printOperand(MI, 5);
O << "}, ";
printOperand(MI, 6);
diff --git a/libclamav/c++/ARMGenCodeEmitter.inc b/libclamav/c++/ARMGenCodeEmitter.inc
index c593b9e..a10485a 100644
--- a/libclamav/c++/ARMGenCodeEmitter.inc
+++ b/libclamav/c++/ARMGenCodeEmitter.inc
@@ -19,6 +19,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
0U,
0U,
0U,
+ 0U,
45088768U, // ADCSSri
11534336U, // ADCSSrr
11534336U, // ADCSSrs
@@ -80,9 +81,6 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
19922704U, // BXr9
167772160U, // Bcc
24055568U, // CLZ
- 57671680U, // CMNri
- 24117248U, // CMNrr
- 24117248U, // CMNrs
57671680U, // CMNzri
24117248U, // CMNzrr
24117248U, // CMNzrs
@@ -162,6 +160,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
16777392U, // PICSTRH
109051920U, // PKHBT
109051984U, // PKHTB
+ 117378864U, // RBIT
113184560U, // REV
113184688U, // REV16
117378992U, // REVSH
@@ -1235,9 +1234,6 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
3931049728U, // t2BR_JT
4026564608U, // t2Bcc
4205899904U, // t2CLZ
- 4044361472U, // t2CMNri
- 3943698176U, // t2CMNrr
- 3943698176U, // t2CMNrs
4044361472U, // t2CMNzri
3943698176U, // t2CMNzrr
3943698176U, // t2CMNzrs
@@ -1327,6 +1323,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
3930062848U, // t2ORRrs
3938451456U, // t2PKHBT
3938451488U, // t2PKHTB
+ 4203802784U, // t2RBIT
4203802752U, // t2REV
4203802768U, // t2REV16
4203802800U, // t2REVSH
@@ -1460,7 +1457,6 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4026585088U, // tBfar
47360U, // tCBNZ
45312U, // tCBZ
- 17088U, // tCMN
17088U, // tCMNz
17664U, // tCMPhir
10240U, // tCMPi8
@@ -1473,10 +1469,13 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
51200U, // tLDM
22528U, // tLDR
23552U, // tLDRB
+ 30720U, // tLDRBi
23040U, // tLDRH
+ 34816U, // tLDRHi
22016U, // tLDRSB
24064U, // tLDRSH
38912U, // tLDRcp
+ 26624U, // tLDRi
18432U, // tLDRpci
0U, // tLDRpci_pic
38912U, // tLDRspi
@@ -1490,11 +1489,11 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
17920U, // tMOVCCr
0U, // tMOVCCr_pseudo
0U, // tMOVSr
- 18112U, // tMOVgpr2gpr
- 17984U, // tMOVgpr2tgpr
+ 17920U, // tMOVgpr2gpr
+ 17920U, // tMOVgpr2tgpr
8192U, // tMOVi8
17920U, // tMOVr
- 18048U, // tMOVtgpr2gpr
+ 17920U, // tMOVtgpr2gpr
17216U, // tMUL
17344U, // tMVN
17152U, // tORR
@@ -1512,7 +1511,10 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
49152U, // tSTM
20480U, // tSTR
21504U, // tSTRB
+ 28672U, // tSTRBi
20992U, // tSTRH
+ 32768U, // tSTRHi
+ 24576U, // tSTRi
36864U, // tSTRspi
7680U, // tSUBi3
14336U, // tSUBi8
@@ -1594,9 +1596,6 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::BXr9:
case ARM::Bcc:
case ARM::CLZ:
- case ARM::CMNri:
- case ARM::CMNrr:
- case ARM::CMNrs:
case ARM::CMNzri:
case ARM::CMNzrr:
case ARM::CMNzrs:
@@ -1676,6 +1675,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::PICSTRH:
case ARM::PKHBT:
case ARM::PKHTB:
+ case ARM::RBIT:
case ARM::REV:
case ARM::REV16:
case ARM::REVSH:
@@ -2749,9 +2749,6 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::t2BR_JT:
case ARM::t2Bcc:
case ARM::t2CLZ:
- case ARM::t2CMNri:
- case ARM::t2CMNrr:
- case ARM::t2CMNrs:
case ARM::t2CMNzri:
case ARM::t2CMNzrr:
case ARM::t2CMNzrs:
@@ -2841,6 +2838,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::t2ORRrs:
case ARM::t2PKHBT:
case ARM::t2PKHTB:
+ case ARM::t2RBIT:
case ARM::t2REV:
case ARM::t2REV16:
case ARM::t2REVSH:
@@ -2974,7 +2972,6 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::tBfar:
case ARM::tCBNZ:
case ARM::tCBZ:
- case ARM::tCMN:
case ARM::tCMNz:
case ARM::tCMPhir:
case ARM::tCMPi8:
@@ -2987,10 +2984,13 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::tLDM:
case ARM::tLDR:
case ARM::tLDRB:
+ case ARM::tLDRBi:
case ARM::tLDRH:
+ case ARM::tLDRHi:
case ARM::tLDRSB:
case ARM::tLDRSH:
case ARM::tLDRcp:
+ case ARM::tLDRi:
case ARM::tLDRpci:
case ARM::tLDRpci_pic:
case ARM::tLDRspi:
@@ -3026,7 +3026,10 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::tSTM:
case ARM::tSTR:
case ARM::tSTRB:
+ case ARM::tSTRBi:
case ARM::tSTRH:
+ case ARM::tSTRHi:
+ case ARM::tSTRi:
case ARM::tSTRspi:
case ARM::tSUBi3:
case ARM::tSUBi8:
diff --git a/libclamav/c++/ARMGenDAGISel.inc b/libclamav/c++/ARMGenDAGISel.inc
index c03b62e..d9ed02b 100644
--- a/libclamav/c++/ARMGenDAGISel.inc
+++ b/libclamav/c++/ARMGenDAGISel.inc
@@ -968,25 +968,25 @@ inline bool Predicate_zextloadi8(SDNode *N) {
}
-DISABLE_INLINE SDNode *Emit_0(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
+DISABLE_INLINE SDNode *Emit_0(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N4)->getZExtValue()), MVT::i32);
SDValue Ops0[] = { N1, N2, N3, Tmp3, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 5);
}
-SDNode *Select_ARMISD_BR2_JT(const SDValue &N) {
+SDNode *Select_ARMISD_BR2_JT(SDNode *N) {
if ((Subtarget->isThumb2())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::TargetJumpTable) {
- SDValue N4 = N.getOperand(4);
- if (N4.getOpcode() == ISD::Constant &&
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDValue N4 = N->getOperand(4);
+ if (N4.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_0(N, ARM::t2BR_JT);
return Result;
@@ -998,38 +998,38 @@ SDNode *Select_ARMISD_BR2_JT(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_1(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_1(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
SDValue Ops0[] = { N1, N2, Tmp2, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_2(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_2(SDNode *N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N1.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain1);
- Chain1 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain1 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, N2, Tmp2, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 6);
Chain1 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
const SDValue Froms[] = {
SDValue(N1.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -1038,41 +1038,41 @@ DISABLE_INLINE SDNode *Emit_2(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_3(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_3(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
SDValue Ops0[] = { N10, N11, N2, Tmp3, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 5);
}
-SDNode *Select_ARMISD_BR_JT(const SDValue &N) {
+SDNode *Select_ARMISD_BR_JT(SDNode *N) {
if ((!Subtarget->isThumb())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (ARMbrjt:isVoid (ld:i32 addrmode2:i32:$target)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (tjumptable:i32):$jt, (imm:i32):$id)
// Emits: (BR_JTm:isVoid addrmode2:i32:$target, (tjumptable:i32):$jt, (imm:i32):$id)
// Pattern complexity = 25 cost = 1 size = 0
- if (N1.getOpcode() == ISD::LOAD &&
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N) &&
(Chain.getNode() == N1.getNode() || IsChainCompatible(Chain.getNode(), N1.getNode()))) {
- SDValue Chain1 = N1.getOperand(0);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
if (SelectAddrMode2(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2)) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::TargetJumpTable) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant &&
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i32) {
SDNode *Result = Emit_2(N, ARM::BR_JTm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2);
@@ -1086,13 +1086,13 @@ SDNode *Select_ARMISD_BR_JT(const SDValue &N) {
// Pattern: (ARMbrjt:isVoid (add:i32 GPR:i32:$target, GPR:i32:$idx), (tjumptable:i32):$jt, (imm:i32):$id)
// Emits: (BR_JTadd:isVoid GPR:i32:$target, GPR:i32:$idx, (tjumptable:i32):$jt, (imm:i32):$id)
// Pattern complexity = 12 cost = 1 size = 0
- if (N1.getOpcode() == ISD::ADD) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::TargetJumpTable) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::ADD) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_3(N, ARM::BR_JTadd);
return Result;
@@ -1103,10 +1103,10 @@ SDNode *Select_ARMISD_BR_JT(const SDValue &N) {
// Pattern: (ARMbrjt:isVoid GPR:i32:$target, (tjumptable:i32):$jt, (imm:i32):$id)
// Emits: (BR_JTr:isVoid GPR:i32:$target, (tjumptable:i32):$jt, (imm:i32):$id)
// Pattern complexity = 9 cost = 1 size = 0
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::TargetJumpTable) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant &&
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_1(N, ARM::BR_JTr);
return Result;
@@ -1118,12 +1118,12 @@ SDNode *Select_ARMISD_BR_JT(const SDValue &N) {
// Emits: (tBR_JTr:isVoid tGPR:i32:$target, (tjumptable:i32):$jt, (imm:i32):$id)
// Pattern complexity = 9 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::TargetJumpTable) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant &&
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_1(N, ARM::tBR_JTr);
return Result;
@@ -1135,28 +1135,28 @@ SDNode *Select_ARMISD_BR_JT(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_4(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_4(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SmallVector<SDValue, 8> Ops0;
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
Ops0.push_back(N1);
- for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N.getOperand(i));
+ for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N->getOperand(i));
}
Ops0.push_back(Chain);
if (HasInFlag)
Ops0.push_back(InFlag);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -1165,15 +1165,15 @@ DISABLE_INLINE SDNode *Emit_4(const SDValue &N, unsigned Opc0, unsigned NumInput
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_ARMISD_CALL(const SDValue &N) {
+SDNode *Select_ARMISD_CALL(SDNode *N) {
// Pattern: (ARMcall:isVoid (tglobaladdr:iPTR):$func)
// Emits: (BL:isVoid (tglobaladdr:i32):$func)
// Pattern complexity = 6 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
SDNode *Result = Emit_4(N, ARM::BL, 1);
return Result;
}
@@ -1183,9 +1183,9 @@ SDNode *Select_ARMISD_CALL(const SDValue &N) {
// Emits: (BLr9:isVoid (tglobaladdr:i32):$func)
// Pattern complexity = 6 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
SDNode *Result = Emit_4(N, ARM::BLr9, 1);
return Result;
}
@@ -1195,9 +1195,9 @@ SDNode *Select_ARMISD_CALL(const SDValue &N) {
// Emits: (tBLXi:isVoid (tglobaladdr:i32):$func)
// Pattern complexity = 6 cost = 1 size = 0
if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
SDNode *Result = Emit_4(N, ARM::tBLXi, 1);
return Result;
}
@@ -1207,9 +1207,9 @@ SDNode *Select_ARMISD_CALL(const SDValue &N) {
// Emits: (tBLXi_r9:isVoid (tglobaladdr:i32):$func)
// Pattern complexity = 6 cost = 1 size = 0
if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
SDNode *Result = Emit_4(N, ARM::tBLXi_r9, 1);
return Result;
}
@@ -1219,9 +1219,9 @@ SDNode *Select_ARMISD_CALL(const SDValue &N) {
// Emits: (tBLXi:isVoid (texternalsym:i32):$func)
// Pattern complexity = 6 cost = 1 size = 0
if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetExternalSymbol) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
SDNode *Result = Emit_4(N, ARM::tBLXi, 1);
return Result;
}
@@ -1231,9 +1231,9 @@ SDNode *Select_ARMISD_CALL(const SDValue &N) {
// Emits: (tBLXi_r9:isVoid (texternalsym:i32):$func)
// Pattern complexity = 6 cost = 1 size = 0
if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetExternalSymbol) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
SDNode *Result = Emit_4(N, ARM::tBLXi_r9, 1);
return Result;
}
@@ -1243,9 +1243,9 @@ SDNode *Select_ARMISD_CALL(const SDValue &N) {
// Emits: (BL:isVoid (texternalsym:i32):$func)
// Pattern complexity = 6 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetExternalSymbol) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
SDNode *Result = Emit_4(N, ARM::BL, 1);
return Result;
}
@@ -1255,9 +1255,9 @@ SDNode *Select_ARMISD_CALL(const SDValue &N) {
// Emits: (BLr9:isVoid (texternalsym:i32):$func)
// Pattern complexity = 6 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetExternalSymbol) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
SDNode *Result = Emit_4(N, ARM::BLr9, 1);
return Result;
}
@@ -1267,8 +1267,8 @@ SDNode *Select_ARMISD_CALL(const SDValue &N) {
// Emits: (BLX:isVoid GPR:i32:$func)
// Pattern complexity = 3 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_4(N, ARM::BLX, 1);
return Result;
@@ -1279,8 +1279,8 @@ SDNode *Select_ARMISD_CALL(const SDValue &N) {
// Emits: (BLXr9:isVoid GPR:i32:$func)
// Pattern complexity = 3 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_4(N, ARM::BLXr9, 1);
return Result;
@@ -1291,8 +1291,8 @@ SDNode *Select_ARMISD_CALL(const SDValue &N) {
// Emits: (tBLXr:isVoid GPR:i32:$dst)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_4(N, ARM::tBLXr, 1);
return Result;
@@ -1303,8 +1303,8 @@ SDNode *Select_ARMISD_CALL(const SDValue &N) {
// Emits: (tBLXr_r9:isVoid GPR:i32:$dst)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_4(N, ARM::tBLXr_r9, 1);
return Result;
@@ -1315,14 +1315,14 @@ SDNode *Select_ARMISD_CALL(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_CALL_NOLINK(const SDValue &N) {
+SDNode *Select_ARMISD_CALL_NOLINK(SDNode *N) {
// Pattern: (ARMcall_nolink:isVoid GPR:i32:$func)
// Emits: (BX:isVoid GPR:i32:$func)
// Pattern complexity = 3 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_4(N, ARM::BX, 1);
return Result;
@@ -1333,8 +1333,8 @@ SDNode *Select_ARMISD_CALL_NOLINK(const SDValue &N) {
// Emits: (BXr9:isVoid GPR:i32:$func)
// Pattern complexity = 3 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_4(N, ARM::BXr9, 1);
return Result;
@@ -1345,8 +1345,8 @@ SDNode *Select_ARMISD_CALL_NOLINK(const SDValue &N) {
// Emits: (tBX:isVoid tGPR:i32:$func)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb1Only()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_4(N, ARM::tBX, 1);
return Result;
@@ -1357,8 +1357,8 @@ SDNode *Select_ARMISD_CALL_NOLINK(const SDValue &N) {
// Emits: (tBXr9:isVoid tGPR:i32:$func)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb1Only()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_4(N, ARM::tBXr9, 1);
return Result;
@@ -1369,32 +1369,32 @@ SDNode *Select_ARMISD_CALL_NOLINK(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_5(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_5(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SmallVector<SDValue, 8> Ops0;
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
Ops0.push_back(N1);
Ops0.push_back(Tmp1);
Ops0.push_back(Tmp2);
- for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N.getOperand(i));
+ for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N->getOperand(i));
}
Ops0.push_back(Chain);
if (HasInFlag)
Ops0.push_back(InFlag);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -1403,15 +1403,15 @@ DISABLE_INLINE SDNode *Emit_5(const SDValue &N, unsigned Opc0, unsigned NumInput
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_ARMISD_CALL_PRED(const SDValue &N) {
+SDNode *Select_ARMISD_CALL_PRED(SDNode *N) {
// Pattern: (ARMcall_pred:isVoid (tglobaladdr:iPTR):$func)
// Emits: (BL_pred:isVoid (tglobaladdr:i32):$func)
// Pattern complexity = 6 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
SDNode *Result = Emit_5(N, ARM::BL_pred, 1);
return Result;
}
@@ -1421,9 +1421,9 @@ SDNode *Select_ARMISD_CALL_PRED(const SDValue &N) {
// Emits: (BLr9_pred:isVoid (tglobaladdr:i32):$func)
// Pattern complexity = 6 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
SDNode *Result = Emit_5(N, ARM::BLr9_pred, 1);
return Result;
}
@@ -1433,329 +1433,91 @@ SDNode *Select_ARMISD_CALL_PRED(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_6(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_6(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 4);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 4);
SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ ReplaceUses(SDValue(N, 0), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_7(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_7(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, N1, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 4);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 4);
SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ ReplaceUses(SDValue(N, 0), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_8(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_8(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 6);
SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ ReplaceUses(SDValue(N, 0), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_9(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp3, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 4);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_10(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, N11, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 4);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_11(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 6);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_12(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_9(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 5);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_13(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 5);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 5);
SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ ReplaceUses(SDValue(N, 0), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_14(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_t2_so_imm_neg_XFORM(Tmp1.getNode());
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 4);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_15(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue Tmp2 = Transform_so_imm_neg_XFORM(Tmp1.getNode());
- SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
- SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 4);
- SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
- return ResNode;
-}
-SDNode *Select_ARMISD_CMP(const SDValue &N) {
+SDNode *Select_ARMISD_CMP(SDNode *N) {
- // Pattern: (ARMcmp:isVoid GPR:i32:$a, (sub:i32 0:i32, so_reg:i32:$b))
- // Emits: (CMNrs:isVoid GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 23 cost = 1 size = 0
+ // Pattern: (ARMcmp:isVoid GPR:i32:$a, so_reg:i32:$b)
+ // Emits: (CMPrs:isVoid GPR:i32:$a, so_reg:i32:$b)
+ // Pattern complexity = 15 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- if (SelectShifterOperandReg(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_11(N, ARM::CMNrs, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (ARMcmp:isVoid GPR:i32:$lhs, (sub:i32 0:i32, t2_so_reg:i32:$rhs))
- // Emits: (t2CMNrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 20 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- if (SelectT2ShifterOperandReg(N, N11, CPTmpN11_0, CPTmpN11_1) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_13(N, ARM::t2CMNrs, CPTmpN11_0, CPTmpN11_1);
- return Result;
- }
- }
- }
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue CPTmpN1_0;
+ SDValue CPTmpN1_1;
+ SDValue CPTmpN1_2;
+ if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
+ N0.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_8(N, ARM::CMPrs, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
+ return Result;
}
}
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
-
- // Pattern: (ARMcmp:isVoid GPR:i32:$a, so_reg:i32:$b)
- // Emits: (CMPrs:isVoid GPR:i32:$a, so_reg:i32:$b)
- // Pattern complexity = 15 cost = 1 size = 0
- {
- SDValue CPTmpN1_0;
- SDValue CPTmpN1_1;
- SDValue CPTmpN1_2;
- if (SelectShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_8(N, ARM::CMPrs, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2);
- return Result;
- }
- }
- // Pattern: (ARMcmp:isVoid GPR:i32:$a, (sub:i32 0:i32, (imm:i32)<<P:Predicate_so_imm>>:$b))
- // Emits: (CMNri:isVoid GPR:i32:$a, (imm:i32):$b)
- // Pattern complexity = 15 cost = 1 size = 0
- if (N1.getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
- Predicate_so_imm(N11.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_9(N, ARM::CMNri);
- return Result;
- }
- }
- }
- }
- }
+ // Pattern: (ARMcmp:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Emits: (t2CMPrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
+ // Pattern complexity = 12 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
-
- // Pattern: (ARMcmp:isVoid GPR:i32:$lhs, (sub:i32 0:i32, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs))
- // Emits: (t2CMNri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 15 cost = 1 size = 0
- if (N1.getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
- Predicate_t2_so_imm(N11.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_9(N, ARM::t2CMNri);
- return Result;
- }
- }
- }
- }
-
- // Pattern: (ARMcmp:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Emits: (t2CMPrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
- // Pattern complexity = 12 cost = 1 size = 0
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_12(N, ARM::t2CMPrs, CPTmpN1_0, CPTmpN1_1);
+ SDNode *Result = Emit_9(N, ARM::t2CMPrs, CPTmpN1_0, CPTmpN1_1);
return Result;
}
}
- // Pattern: (ARMcmp:isVoid GPR:i32:$a, (sub:i32 0:i32, GPR:i32:$b))
- // Emits: (CMNrr:isVoid GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 11 cost = 1 size = 0
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_10(N, ARM::CMNrr);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (ARMcmp:isVoid tGPR:i32:$lhs, (sub:i32 0:i32, tGPR:i32:$rhs))
- // Emits: (tCMN:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
- // Pattern complexity = 11 cost = 1 size = 0
- if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_10(N, ARM::tCMN);
- return Result;
- }
- }
- }
- }
- }
-
- // Pattern: (ARMcmp:isVoid GPR:i32:$lhs, (sub:i32 0:i32, GPR:i32:$rhs))
- // Emits: (t2CMNrr:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
- // Pattern complexity = 11 cost = 1 size = 0
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getOperand(1);
- if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_10(N, ARM::t2CMNrr);
- return Result;
- }
- }
- }
- }
- }
-
// Pattern: (ARMcmp:isVoid GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
// Emits: (CMPri:isVoid GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 7 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N1.getNode()) &&
N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_6(N, ARM::CMPri);
@@ -1767,56 +1529,36 @@ SDNode *Select_ARMISD_CMP(const SDValue &N) {
// Emits: (tCMPi8:isVoid tGPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 7 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_imm0_255(N1.getNode()) &&
N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_6(N, ARM::tCMPi8);
return Result;
}
}
- if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
-
- // Pattern: (ARMcmp:isVoid GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
- // Emits: (t2CMPri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_t2_so_imm(N1.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_6(N, ARM::t2CMPri);
- return Result;
- }
-
- // Pattern: (ARMcmp:isVoid GPR:i32:$src, (imm:i32)<<P:Predicate_t2_so_imm_neg>><<X:t2_so_imm_neg_XFORM>>:$imm)
- // Emits: (t2CMNri:isVoid GPR:i32:$src, (t2_so_imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_t2_so_imm_neg>>:$imm))
- // Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_t2_so_imm_neg(N1.getNode()) &&
- N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_14(N, ARM::t2CMNri);
- return Result;
- }
- }
- }
- if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- // Pattern: (ARMcmp:isVoid GPR:i32:$src, (imm:i32)<<P:Predicate_so_imm_neg>><<X:so_imm_neg_XFORM>>:$imm)
- // Emits: (CMNri:isVoid GPR:i32:$src, (so_imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_so_imm_neg>>:$imm))
- // Pattern complexity = 7 cost = 1 size = 0
- if (N1.getOpcode() == ISD::Constant &&
- Predicate_so_imm_neg(N1.getNode()) &&
+ // Pattern: (ARMcmp:isVoid GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
+ // Emits: (t2CMPri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
+ // Pattern complexity = 7 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
+ Predicate_t2_so_imm(N1.getNode()) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_15(N, ARM::CMNri);
+ SDNode *Result = Emit_6(N, ARM::t2CMPri);
return Result;
}
+ }
- // Pattern: (ARMcmp:isVoid GPR:i32:$a, GPR:i32:$b)
- // Emits: (CMPrr:isVoid GPR:i32:$a, GPR:i32:$b)
- // Pattern complexity = 3 cost = 1 size = 0
+ // Pattern: (ARMcmp:isVoid GPR:i32:$a, GPR:i32:$b)
+ // Emits: (CMPrr:isVoid GPR:i32:$a, GPR:i32:$b)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb())) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_7(N, ARM::CMPrr);
return Result;
@@ -1827,8 +1569,8 @@ SDNode *Select_ARMISD_CMP(const SDValue &N) {
// Emits: (tCMPr:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_7(N, ARM::tCMPr);
return Result;
@@ -1839,8 +1581,8 @@ SDNode *Select_ARMISD_CMP(const SDValue &N) {
// Emits: (t2CMPrr:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_7(N, ARM::t2CMPrr);
return Result;
@@ -1851,10 +1593,10 @@ SDNode *Select_ARMISD_CMP(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_CMPFP(const SDValue &N) {
+SDNode *Select_ARMISD_CMPFP(SDNode *N) {
if ((Subtarget->hasVFP2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (arm_cmpfp:isVoid DPR:f64:$a, DPR:f64:$b)
// Emits: (VCMPED:isVoid DPR:f64:$a, DPR:f64:$b)
@@ -1877,24 +1619,24 @@ SDNode *Select_ARMISD_CMPFP(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_16(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
+DISABLE_INLINE SDNode *Emit_10(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, N0, Tmp1, Tmp2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, N0, Tmp1, Tmp2);
SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ ReplaceUses(SDValue(N, 0), InFlag);
return ResNode;
}
-SDNode *Select_ARMISD_CMPFPw0(const SDValue &N) {
+SDNode *Select_ARMISD_CMPFPw0(SDNode *N) {
if ((Subtarget->hasVFP2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (arm_cmpfp0:isVoid DPR:f64:$a)
// Emits: (VCMPEZD:isVoid DPR:f64:$a)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_16(N, ARM::VCMPEZD);
+ SDNode *Result = Emit_10(N, ARM::VCMPEZD);
return Result;
}
@@ -1902,7 +1644,7 @@ SDNode *Select_ARMISD_CMPFPw0(const SDValue &N) {
// Emits: (VCMPEZS:isVoid SPR:f32:$a)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_16(N, ARM::VCMPEZS);
+ SDNode *Result = Emit_10(N, ARM::VCMPEZS);
return Result;
}
}
@@ -1911,181 +1653,260 @@ SDNode *Select_ARMISD_CMPFPw0(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_17(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_11(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, Tmp3, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 4);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 4);
SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ ReplaceUses(SDValue(N, 0), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_18(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_12(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N01, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 4);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 4);
SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ ReplaceUses(SDValue(N, 0), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_19(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_13(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 6);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N, 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_14(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp3, Tmp4, Tmp5 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 4);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N, 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_15(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, N11, Tmp4, Tmp5 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 4);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N, 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_16(SDNode *N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, Tmp4, Tmp5 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 6);
SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ ReplaceUses(SDValue(N, 0), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_20(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_17(SDNode *N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, Tmp4, Tmp5 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 5);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N, 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_18(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, CPTmpN01_0, CPTmpN01_1, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 5);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 5);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N, 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_19(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_t2_so_imm_neg_XFORM(Tmp1.getNode());
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 4);
SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ ReplaceUses(SDValue(N, 0), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_21(const SDValue &N, unsigned Opc0, SDValue &CPTmpN00_0, SDValue &CPTmpN00_1, SDValue &CPTmpN00_2) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_20(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp2 = Transform_so_imm_neg_XFORM(Tmp1.getNode());
+ SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
+ SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
+ SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 4);
+ SDValue InFlag(ResNode, 0);
+ ReplaceUses(SDValue(N, 0), InFlag);
+ return ResNode;
+}
+DISABLE_INLINE SDNode *Emit_21(SDNode *N, unsigned Opc0, SDValue &CPTmpN00_0, SDValue &CPTmpN00_1, SDValue &CPTmpN00_2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N01, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 6);
SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ ReplaceUses(SDValue(N, 0), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_22(const SDValue &N, unsigned Opc0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_22(SDNode *N, unsigned Opc0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 6);
SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ ReplaceUses(SDValue(N, 0), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_23(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_23(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, Tmp3, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 4);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 4);
SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ ReplaceUses(SDValue(N, 0), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_24(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_24(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, N01, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 4);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 4);
SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ ReplaceUses(SDValue(N, 0), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_25(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_25(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 6);
SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ ReplaceUses(SDValue(N, 0), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_26(const SDValue &N, unsigned Opc0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_26(SDNode *N, unsigned Opc0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 5);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 5);
SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ ReplaceUses(SDValue(N, 0), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_27(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_27(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 5);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 5);
SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ ReplaceUses(SDValue(N, 0), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_28(const SDValue &N, unsigned Opc0, SDValue &CPTmpN00_0, SDValue &CPTmpN00_1) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_28(SDNode *N, unsigned Opc0, SDValue &CPTmpN00_0, SDValue &CPTmpN00_1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N01, CPTmpN00_0, CPTmpN00_1, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Ops0, 5);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Ops0, 5);
SDValue InFlag(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ ReplaceUses(SDValue(N, 0), InFlag);
return ResNode;
}
-SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
+SDNode *Select_ARMISD_CMPZ(SDNode *N) {
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (ARMcmpZ:isVoid (and:i32 GPR:i32:$a, so_reg:i32:$b), 0:i32)
// Emits: (TSTrs:isVoid GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 23 cost = 1 size = 0
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
if (SelectShifterOperandReg(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2)) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_19(N, ARM::TSTrs, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2);
+ SDNode *Result = Emit_13(N, ARM::TSTrs, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2);
return Result;
}
}
@@ -2095,20 +1916,20 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Pattern: (ARMcmpZ:isVoid (xor:i32 GPR:i32:$a, so_reg:i32:$b), 0:i32)
// Emits: (TEQrs:isVoid GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 23 cost = 1 size = 0
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
if (SelectShifterOperandReg(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2)) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_19(N, ARM::TEQrs, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2);
+ SDNode *Result = Emit_13(N, ARM::TEQrs, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2);
return Result;
}
}
@@ -2119,20 +1940,20 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Emits: (CMNzrs:isVoid GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 23 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
if (SelectShifterOperandReg(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_11(N, ARM::CMNzrs, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2);
+ SDNode *Result = Emit_16(N, ARM::CMNzrs, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2);
return Result;
}
}
@@ -2143,15 +1964,15 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Pattern: (ARMcmpZ:isVoid (and:i32 so_reg:i32:$b, GPR:i32:$a), 0:i32)
// Emits: (TSTrs:isVoid GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 23 cost = 1 size = 0
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
SDValue CPTmpN00_0;
SDValue CPTmpN00_1;
SDValue CPTmpN00_2;
if (SelectShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2)) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
@@ -2166,15 +1987,15 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Pattern: (ARMcmpZ:isVoid (xor:i32 so_reg:i32:$b, GPR:i32:$a), 0:i32)
// Emits: (TEQrs:isVoid GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 23 cost = 1 size = 0
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
SDValue CPTmpN00_0;
SDValue CPTmpN00_1;
SDValue CPTmpN00_2;
if (SelectShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2)) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
@@ -2189,18 +2010,18 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Pattern: (ARMcmpZ:isVoid (sub:i32 0:i32, so_reg:i32:$b), GPR:i32:$a)
// Emits: (CMNzrs:isVoid GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 23 cost = 1 size = 0
- if (N0.getOpcode() == ISD::SUB) {
- SDValue N00 = N0.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ if (N0.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
if (SelectShifterOperandReg(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_25(N, ARM::CMNzrs, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2);
return Result;
@@ -2211,25 +2032,25 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (ARMcmpZ:isVoid GPR:i32:$lhs, (sub:i32 0:i32, t2_so_reg:i32:$rhs))
// Emits: (t2CMNzrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 20 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
if (SelectT2ShifterOperandReg(N, N11, CPTmpN11_0, CPTmpN11_1) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_13(N, ARM::t2CMNzrs, CPTmpN11_0, CPTmpN11_1);
+ SDNode *Result = Emit_17(N, ARM::t2CMNzrs, CPTmpN11_0, CPTmpN11_1);
return Result;
}
}
@@ -2240,19 +2061,19 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Pattern: (ARMcmpZ:isVoid (and:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs), 0:i32)
// Emits: (t2TSTrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 20 cost = 1 size = 0
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
if (SelectT2ShifterOperandReg(N, N01, CPTmpN01_0, CPTmpN01_1)) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_20(N, ARM::t2TSTrs, CPTmpN01_0, CPTmpN01_1);
+ SDNode *Result = Emit_18(N, ARM::t2TSTrs, CPTmpN01_0, CPTmpN01_1);
return Result;
}
}
@@ -2262,19 +2083,19 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Pattern: (ARMcmpZ:isVoid (xor:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs), 0:i32)
// Emits: (t2TEQrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 20 cost = 1 size = 0
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
if (SelectT2ShifterOperandReg(N, N01, CPTmpN01_0, CPTmpN01_1)) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_20(N, ARM::t2TEQrs, CPTmpN01_0, CPTmpN01_1);
+ SDNode *Result = Emit_18(N, ARM::t2TEQrs, CPTmpN01_0, CPTmpN01_1);
return Result;
}
}
@@ -2284,17 +2105,17 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Pattern: (ARMcmpZ:isVoid (sub:i32 0:i32, t2_so_reg:i32:$rhs), GPR:i32:$lhs)
// Emits: (t2CMNzrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 20 cost = 1 size = 0
- if (N0.getOpcode() == ISD::SUB) {
- SDValue N00 = N0.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ if (N0.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
if (SelectT2ShifterOperandReg(N, N01, CPTmpN01_0, CPTmpN01_1)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_27(N, ARM::t2CMNzrs, CPTmpN01_0, CPTmpN01_1);
return Result;
@@ -2307,14 +2128,14 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Pattern: (ARMcmpZ:isVoid (and:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs), 0:i32)
// Emits: (t2TSTrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 20 cost = 1 size = 0
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
SDValue CPTmpN00_0;
SDValue CPTmpN00_1;
if (SelectT2ShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1)) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
@@ -2329,14 +2150,14 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Pattern: (ARMcmpZ:isVoid (xor:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs), 0:i32)
// Emits: (t2TEQrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 20 cost = 1 size = 0
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
SDValue CPTmpN00_0;
SDValue CPTmpN00_1;
if (SelectT2ShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1)) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
@@ -2349,23 +2170,23 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
}
}
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (ARMcmpZ:isVoid (and:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b), 0:i32)
// Emits: (TSTri:isVoid GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 15 cost = 1 size = 0
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N01.getNode())) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_17(N, ARM::TSTri);
+ SDNode *Result = Emit_11(N, ARM::TSTri);
return Result;
}
}
@@ -2375,24 +2196,24 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Pattern: (ARMcmpZ:isVoid (xor:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b), 0:i32)
// Emits: (TEQri:isVoid GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 15 cost = 1 size = 0
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N01.getNode())) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_17(N, ARM::TEQri);
+ SDNode *Result = Emit_11(N, ARM::TEQri);
return Result;
}
}
}
}
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
// Pattern: (ARMcmpZ:isVoid GPR:i32:$a, so_reg:i32:$b)
// Emits: (CMPzrs:isVoid GPR:i32:$a, so_reg:i32:$b)
@@ -2411,17 +2232,17 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Pattern: (ARMcmpZ:isVoid GPR:i32:$a, (sub:i32 0:i32, (imm:i32)<<P:Predicate_so_imm>>:$b))
// Emits: (CMNzri:isVoid GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 15 cost = 1 size = 0
- if (N1.getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ if (N1.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N11.getNode()) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_9(N, ARM::CMNzri);
+ SDNode *Result = Emit_14(N, ARM::CMNzri);
return Result;
}
}
@@ -2429,24 +2250,24 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (ARMcmpZ:isVoid GPR:i32:$lhs, (sub:i32 0:i32, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs))
// Emits: (t2CMNzri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 15 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_t2_so_imm(N11.getNode()) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_9(N, ARM::t2CMNzri);
+ SDNode *Result = Emit_14(N, ARM::t2CMNzri);
return Result;
}
}
@@ -2457,18 +2278,18 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Pattern: (ARMcmpZ:isVoid (and:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs), 0:i32)
// Emits: (t2TSTri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 15 cost = 1 size = 0
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_t2_so_imm(N01.getNode())) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_17(N, ARM::t2TSTri);
+ SDNode *Result = Emit_11(N, ARM::t2TSTri);
return Result;
}
}
@@ -2478,18 +2299,18 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Pattern: (ARMcmpZ:isVoid (xor:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs), 0:i32)
// Emits: (t2TEQri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 15 cost = 1 size = 0
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_t2_so_imm(N01.getNode())) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_17(N, ARM::t2TEQri);
+ SDNode *Result = Emit_11(N, ARM::t2TEQri);
return Result;
}
}
@@ -2497,7 +2318,7 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
}
}
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (ARMcmpZ:isVoid so_reg:i32:$b, GPR:i32:$a)
// Emits: (CMPzrs:isVoid GPR:i32:$a, so_reg:i32:$b)
@@ -2507,7 +2328,7 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
SDValue CPTmpN0_1;
SDValue CPTmpN0_2;
if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_22(N, ARM::CMPzrs, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
return Result;
@@ -2518,16 +2339,16 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Pattern: (ARMcmpZ:isVoid (sub:i32 0:i32, (imm:i32)<<P:Predicate_so_imm>>:$b), GPR:i32:$a)
// Emits: (CMNzri:isVoid GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 15 cost = 1 size = 0
- if (N0.getOpcode() == ISD::SUB) {
- SDValue N00 = N0.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ if (N0.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N01.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_23(N, ARM::CMNzri);
return Result;
@@ -2538,21 +2359,21 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (ARMcmpZ:isVoid (sub:i32 0:i32, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs), GPR:i32:$lhs)
// Emits: (t2CMNzri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 15 cost = 1 size = 0
- if (N0.getOpcode() == ISD::SUB) {
- SDValue N00 = N0.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ if (N0.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_t2_so_imm(N01.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_23(N, ARM::t2CMNzri);
return Result;
@@ -2566,12 +2387,12 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Emits: (t2CMPzrs:isVoid GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_12(N, ARM::t2CMPzrs, CPTmpN1_0, CPTmpN1_1);
+ SDNode *Result = Emit_9(N, ARM::t2CMPzrs, CPTmpN1_0, CPTmpN1_1);
return Result;
}
}
@@ -2582,7 +2403,7 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
SDValue CPTmpN0_0;
SDValue CPTmpN0_1;
if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_26(N, ARM::t2CMPzrs, CPTmpN0_0, CPTmpN0_1);
return Result;
@@ -2590,21 +2411,21 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
}
}
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (ARMcmpZ:isVoid (and:i32 GPR:i32:$a, GPR:i32:$b), 0:i32)
// Emits: (TSTrr:isVoid GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_18(N, ARM::TSTrr);
+ SDNode *Result = Emit_12(N, ARM::TSTrr);
return Result;
}
}
@@ -2613,16 +2434,16 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Pattern: (ARMcmpZ:isVoid (xor:i32 GPR:i32:$a, GPR:i32:$b), 0:i32)
// Emits: (TEQrr:isVoid GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_18(N, ARM::TEQrr);
+ SDNode *Result = Emit_12(N, ARM::TEQrr);
return Result;
}
}
@@ -2631,16 +2452,16 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Pattern: (ARMcmpZ:isVoid GPR:i32:$a, (sub:i32 0:i32, GPR:i32:$b))
// Emits: (CMNzrr:isVoid GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 11 cost = 1 size = 0
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_10(N, ARM::CMNzrr);
+ SDNode *Result = Emit_15(N, ARM::CMNzrr);
return Result;
}
}
@@ -2648,22 +2469,22 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
}
}
if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (ARMcmpZ:isVoid tGPR:i32:$lhs, (sub:i32 0:i32, tGPR:i32:$rhs))
// Emits: (tCMNz:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
// Pattern complexity = 11 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_10(N, ARM::tCMNz);
+ SDNode *Result = Emit_15(N, ARM::tCMNz);
return Result;
}
}
@@ -2674,38 +2495,38 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Pattern: (ARMcmpZ:isVoid (and:i32 tGPR:i32:$lhs, tGPR:i32:$rhs), 0:i32)
// Emits: (tTST:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_18(N, ARM::tTST);
+ SDNode *Result = Emit_12(N, ARM::tTST);
return Result;
}
}
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (ARMcmpZ:isVoid GPR:i32:$lhs, (sub:i32 0:i32, GPR:i32:$rhs))
// Emits: (t2CMNzrr:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
// Pattern complexity = 11 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SUB) {
- SDValue N10 = N1.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_10(N, ARM::t2CMNzrr);
+ SDNode *Result = Emit_15(N, ARM::t2CMNzrr);
return Result;
}
}
@@ -2716,16 +2537,16 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Pattern: (ARMcmpZ:isVoid (and:i32 GPR:i32:$lhs, GPR:i32:$rhs), 0:i32)
// Emits: (t2TSTrr:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_18(N, ARM::t2TSTrr);
+ SDNode *Result = Emit_12(N, ARM::t2TSTrr);
return Result;
}
}
@@ -2734,16 +2555,16 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Pattern: (ARMcmpZ:isVoid (xor:i32 GPR:i32:$lhs, GPR:i32:$rhs), 0:i32)
// Emits: (t2TEQrr:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_18(N, ARM::t2TEQrr);
+ SDNode *Result = Emit_12(N, ARM::t2TEQrr);
return Result;
}
}
@@ -2754,15 +2575,15 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Emits: (CMNzrr:isVoid GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 11 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SUB) {
- SDValue N00 = N0.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_24(N, ARM::CMNzrr);
return Result;
@@ -2776,15 +2597,15 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Emits: (tCMNz:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
// Pattern complexity = 11 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SUB) {
- SDValue N00 = N0.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_24(N, ARM::tCMNz);
return Result;
@@ -2798,15 +2619,15 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Emits: (t2CMNzrr:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
// Pattern complexity = 11 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SUB) {
- SDValue N00 = N0.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_24(N, ARM::t2CMNzrr);
return Result;
@@ -2820,9 +2641,9 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Emits: (CMPzri:isVoid GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 7 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N1.getNode()) &&
N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_6(N, ARM::CMPzri);
@@ -2834,9 +2655,9 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Emits: (tCMPzi8:isVoid tGPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 7 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_imm0_255(N1.getNode()) &&
N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_6(N, ARM::tCMPzi8);
@@ -2844,9 +2665,9 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (ARMcmpZ:isVoid GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
// Emits: (t2CMPzri:isVoid GPR:i32:$lhs, (imm:i32):$rhs)
@@ -2858,26 +2679,26 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
}
// Pattern: (ARMcmpZ:isVoid GPR:i32:$src, (imm:i32)<<P:Predicate_t2_so_imm_neg>><<X:t2_so_imm_neg_XFORM>>:$imm)
- // Emits: (t2CMNri:isVoid GPR:i32:$src, (t2_so_imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_t2_so_imm_neg>>:$imm))
+ // Emits: (t2CMNzri:isVoid GPR:i32:$src, (t2_so_imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_t2_so_imm_neg>>:$imm))
// Pattern complexity = 7 cost = 1 size = 0
if (Predicate_t2_so_imm_neg(N1.getNode()) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_14(N, ARM::t2CMNri);
+ SDNode *Result = Emit_19(N, ARM::t2CMNzri);
return Result;
}
}
}
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (ARMcmpZ:isVoid GPR:i32:$src, (imm:i32)<<P:Predicate_so_imm_neg>><<X:so_imm_neg_XFORM>>:$imm)
- // Emits: (CMNri:isVoid GPR:i32:$src, (so_imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_so_imm_neg>>:$imm))
+ // Emits: (CMNzri:isVoid GPR:i32:$src, (so_imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_so_imm_neg>>:$imm))
// Pattern complexity = 7 cost = 1 size = 0
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm_neg(N1.getNode()) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_15(N, ARM::CMNri);
+ SDNode *Result = Emit_20(N, ARM::CMNzri);
return Result;
}
@@ -2894,8 +2715,8 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Emits: (tCMPzr:isVoid tGPR:i32:$lhs, tGPR:i32:$rhs)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_7(N, ARM::tCMPzr);
return Result;
@@ -2906,8 +2727,8 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
// Emits: (t2CMPzrr:isVoid GPR:i32:$lhs, GPR:i32:$rhs)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_7(N, ARM::t2CMPzrr);
return Result;
@@ -2918,17 +2739,17 @@ SDNode *Select_ARMISD_CMPZ(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_29(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N0);
+DISABLE_INLINE SDNode *Emit_29(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0);
}
-SDNode *Select_ARMISD_EH_SJLJ_SETJMP_i32(const SDValue &N) {
+SDNode *Select_ARMISD_EH_SJLJ_SETJMP_i32(SDNode *N) {
// Pattern: (ARMeh_sjlj_setjmp:i32 GPR:i32:$src)
// Emits: (Int_eh_sjlj_setjmp:isVoid GPR:i32:$src)
// Pattern complexity = 3 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_29(N, ARM::Int_eh_sjlj_setjmp);
return Result;
@@ -2939,7 +2760,7 @@ SDNode *Select_ARMISD_EH_SJLJ_SETJMP_i32(const SDValue &N) {
// Emits: (tInt_eh_sjlj_setjmp:isVoid GPR:i32:$src)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_29(N, ARM::tInt_eh_sjlj_setjmp);
return Result;
@@ -2950,7 +2771,7 @@ SDNode *Select_ARMISD_EH_SJLJ_SETJMP_i32(const SDValue &N) {
// Emits: (t2Int_eh_sjlj_setjmp:isVoid GPR:i32:$src)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_29(N, ARM::t2Int_eh_sjlj_setjmp);
return Result;
@@ -2961,16 +2782,16 @@ SDNode *Select_ARMISD_EH_SJLJ_SETJMP_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_30(const SDValue &N, unsigned Opc0) {
+DISABLE_INLINE SDNode *Emit_30(SDNode *N, unsigned Opc0) {
SDValue Tmp0 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp1 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag = N.getOperand(0);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Tmp0, Tmp1, InFlag);
+ SDValue InFlag = N->getOperand(0);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Tmp0, Tmp1, InFlag);
InFlag = SDValue(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ ReplaceUses(SDValue(N, 0), InFlag);
return ResNode;
}
-SDNode *Select_ARMISD_FMSTAT(const SDValue &N) {
+SDNode *Select_ARMISD_FMSTAT(SDNode *N) {
if ((Subtarget->hasVFP2())) {
SDNode *Result = Emit_30(N, ARM::FMSTAT);
return Result;
@@ -2980,30 +2801,30 @@ SDNode *Select_ARMISD_FMSTAT(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_31(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
+DISABLE_INLINE SDNode *Emit_31(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1, Tmp2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_32(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
- SDValue N0 = N.getOperand(0);
- SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
+DISABLE_INLINE SDNode *Emit_32(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Tmp0(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
SDValue Tmp2 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- SDValue Tmp3(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp0, N0, Tmp2), 0);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp0, N0, Tmp2), 0);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
- SDValue Tmp6(CurDAG->getMachineNode(Opc2, N.getDebugLoc(), VT2, Tmp3, Tmp4, Tmp5), 0);
+ SDValue Tmp6(CurDAG->getMachineNode(Opc2, N->getDebugLoc(), VT2, Tmp3, Tmp4, Tmp5), 0);
SDValue Tmp7 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc3, VT3, Tmp6, Tmp7);
+ return CurDAG->SelectNodeTo(N, Opc3, VT3, Tmp6, Tmp7);
}
-SDNode *Select_ARMISD_FTOSI_f32(const SDValue &N) {
+SDNode *Select_ARMISD_FTOSI_f32(SDNode *N) {
// Pattern: (arm_ftosi:f32 DPR:f64:$a)
// Emits: (VTOSIZD:f32 DPR:f64:$a)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->hasVFP2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f64) {
SDNode *Result = Emit_31(N, ARM::VTOSIZD, MVT::f32);
return Result;
@@ -3014,7 +2835,7 @@ SDNode *Select_ARMISD_FTOSI_f32(const SDValue &N) {
// Emits: (VTOSIZS:f32 SPR:f32:$a)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
SDNode *Result = Emit_31(N, ARM::VTOSIZS, MVT::f32);
return Result;
@@ -3025,7 +2846,7 @@ SDNode *Select_ARMISD_FTOSI_f32(const SDValue &N) {
// Emits: (EXTRACT_SUBREG:f32 (VCVTf2sd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32)), 1:i32)
// Pattern complexity = 3 cost = 4 size = 0
if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
SDNode *Result = Emit_32(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VCVTf2sd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
return Result;
@@ -3036,13 +2857,13 @@ SDNode *Select_ARMISD_FTOSI_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_FTOUI_f32(const SDValue &N) {
+SDNode *Select_ARMISD_FTOUI_f32(SDNode *N) {
// Pattern: (arm_ftoui:f32 DPR:f64:$a)
// Emits: (VTOUIZD:f32 DPR:f64:$a)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->hasVFP2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f64) {
SDNode *Result = Emit_31(N, ARM::VTOUIZD, MVT::f32);
return Result;
@@ -3053,7 +2874,7 @@ SDNode *Select_ARMISD_FTOUI_f32(const SDValue &N) {
// Emits: (VTOUIZS:f32 SPR:f32:$a)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
SDNode *Result = Emit_31(N, ARM::VTOUIZS, MVT::f32);
return Result;
@@ -3064,7 +2885,7 @@ SDNode *Select_ARMISD_FTOUI_f32(const SDValue &N) {
// Emits: (EXTRACT_SUBREG:f32 (VCVTf2ud_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32)), 1:i32)
// Pattern complexity = 3 cost = 4 size = 0
if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
SDNode *Result = Emit_32(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VCVTf2ud_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
return Result;
@@ -3075,16 +2896,16 @@ SDNode *Select_ARMISD_FTOUI_f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_33(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain);
+DISABLE_INLINE SDNode *Emit_33(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Chain);
}
-DISABLE_INLINE SDNode *Emit_34(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, N1, Chain);
+DISABLE_INLINE SDNode *Emit_34(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, N1, Chain);
}
-SDNode *Select_ARMISD_MEMBARRIER(const SDValue &N) {
+SDNode *Select_ARMISD_MEMBARRIER(SDNode *N) {
// Pattern: (ARMMemBarrierV7:isVoid)
// Emits: (Int_MemBarrierV7:isVoid)
@@ -3098,8 +2919,8 @@ SDNode *Select_ARMISD_MEMBARRIER(const SDValue &N) {
// Emits: (Int_MemBarrierV6:isVoid GPR:i32:$zero)
// Pattern complexity = 3 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_34(N, ARM::Int_MemBarrierV6);
return Result;
@@ -3118,55 +2939,55 @@ SDNode *Select_ARMISD_MEMBARRIER(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_35(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_35(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_36(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_36(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
-}
-DISABLE_INLINE SDNode *Emit_37(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1);
+}
+DISABLE_INLINE SDNode *Emit_37(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, N010, Tmp1, Chain0);
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, N010, Tmp1, Chain0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_ARMISD_PIC_ADD_i32(const SDValue &N) {
+SDNode *Select_ARMISD_PIC_ADD_i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
// Pattern: (ARMpic_add:i32 (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32):$cp)
// Emits: (tLDRpci_pic:i32 (tconstpool:i32):$addr, (imm:i32):$cp)
// Pattern complexity = 16 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ARMISD::Wrapper) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::TargetConstantPool) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ARMISD::Wrapper) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::TargetConstantPool) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_37(N, ARM::tLDRpci_pic, MVT::i32);
return Result;
}
@@ -3180,19 +3001,19 @@ SDNode *Select_ARMISD_PIC_ADD_i32(const SDValue &N) {
// Emits: (t2LDRpci_pic:i32 (tconstpool:i32):$addr, (imm:i32):$cp)
// Pattern complexity = 16 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ARMISD::Wrapper) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::TargetConstantPool) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ARMISD::Wrapper) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::TargetConstantPool) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_37(N, ARM::t2LDRpci_pic, MVT::i32);
return Result;
}
@@ -3207,9 +3028,9 @@ SDNode *Select_ARMISD_PIC_ADD_i32(const SDValue &N) {
// Emits: (PICADD:i32 GPR:i32:$a, (imm:i32):$cp)
// Pattern complexity = 6 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::PICADD, MVT::i32);
return Result;
}
@@ -3219,9 +3040,9 @@ SDNode *Select_ARMISD_PIC_ADD_i32(const SDValue &N) {
// Emits: (tPICADD:i32 GPR:i32:$lhs, (imm:i32):$cp)
// Pattern complexity = 6 cost = 1 size = 0
if ((Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_36(N, ARM::tPICADD, MVT::i32);
return Result;
}
@@ -3231,29 +3052,51 @@ SDNode *Select_ARMISD_PIC_ADD_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_38(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+SDNode *Select_ARMISD_RBIT_i32(SDNode *N) {
+
+ // Pattern: (ARMrbit:i32 GPR:i32:$src)
+ // Emits: (RBIT:i32 GPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops())) {
+ SDNode *Result = Emit_31(N, ARM::RBIT, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (ARMrbit:i32 GPR:i32:$src)
+ // Emits: (t2RBIT:i32 GPR:i32:$src)
+ // Pattern complexity = 3 cost = 1 size = 0
+ if ((Subtarget->isThumb2())) {
+ SDNode *Result = Emit_31(N, ARM::t2RBIT, MVT::i32);
+ return Result;
+ }
+
+ CannotYetSelect(N);
+ return NULL;
+}
+
+DISABLE_INLINE SDNode *Emit_38(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SDValue Tmp0 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp1 = CurDAG->getRegister(0, MVT::i32);
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
SDValue Ops0[] = { Tmp0, Tmp1, Chain, InFlag };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, HasInFlag ? 4 : 3);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, HasInFlag ? 4 : 3);
}
-DISABLE_INLINE SDNode *Emit_39(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_39(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
SDValue Ops0[] = { Chain, InFlag };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, HasInFlag ? 2 : 1);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, HasInFlag ? 2 : 1);
}
-SDNode *Select_ARMISD_RET_FLAG(const SDValue &N) {
+SDNode *Select_ARMISD_RET_FLAG(SDNode *N) {
// Pattern: (ARMretflag:isVoid)
// Emits: (BX_RET:isVoid)
@@ -3275,16 +3118,16 @@ SDNode *Select_ARMISD_RET_FLAG(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_40(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
+DISABLE_INLINE SDNode *Emit_40(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag = N.getOperand(1);
+ SDValue InFlag = N->getOperand(1);
SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3, InFlag };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-SDNode *Select_ARMISD_RRX_i32(const SDValue &N) {
+SDNode *Select_ARMISD_RRX_i32(SDNode *N) {
// Pattern: (ARMrrx:i32 GPR:i32:$src)
// Emits: (MOVrx:i32 GPR:i32:$src)
@@ -3306,7 +3149,7 @@ SDNode *Select_ARMISD_RRX_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_SITOF_f32(const SDValue &N) {
+SDNode *Select_ARMISD_SITOF_f32(SDNode *N) {
// Pattern: (arm_sitof:f32 SPR:f32:$a)
// Emits: (VSITOS:f32 SPR:f32:$a)
@@ -3328,7 +3171,7 @@ SDNode *Select_ARMISD_SITOF_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_SITOF_f64(const SDValue &N) {
+SDNode *Select_ARMISD_SITOF_f64(SDNode *N) {
if ((Subtarget->hasVFP2())) {
SDNode *Result = Emit_31(N, ARM::VSITOD, MVT::f64);
return Result;
@@ -3338,23 +3181,23 @@ SDNode *Select_ARMISD_SITOF_f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_41(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
+DISABLE_INLINE SDNode *Emit_41(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, Tmp1, Tmp2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, Tmp1, Tmp2);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_42(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0);
+DISABLE_INLINE SDNode *Emit_42(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-SDNode *Select_ARMISD_SRA_FLAG_i32(const SDValue &N) {
+SDNode *Select_ARMISD_SRA_FLAG_i32(SDNode *N) {
// Pattern: (ARMsra_flag:i32 GPR:i32:$src)
// Emits: (MOVsra_flag:i32 GPR:i32:$src)
@@ -3376,7 +3219,7 @@ SDNode *Select_ARMISD_SRA_FLAG_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_SRL_FLAG_i32(const SDValue &N) {
+SDNode *Select_ARMISD_SRL_FLAG_i32(SDNode *N) {
// Pattern: (ARMsrl_flag:i32 GPR:i32:$src)
// Emits: (MOVsrl_flag:i32 GPR:i32:$src)
@@ -3398,7 +3241,7 @@ SDNode *Select_ARMISD_SRL_FLAG_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_SYNCBARRIER(const SDValue &N) {
+SDNode *Select_ARMISD_SYNCBARRIER(SDNode *N) {
// Pattern: (ARMSyncBarrierV7:isVoid)
// Emits: (Int_SyncBarrierV7:isVoid)
@@ -3412,8 +3255,8 @@ SDNode *Select_ARMISD_SYNCBARRIER(const SDValue &N) {
// Emits: (Int_SyncBarrierV6:isVoid GPR:i32:$zero)
// Pattern complexity = 3 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_34(N, ARM::Int_SyncBarrierV6);
return Result;
@@ -3432,10 +3275,10 @@ SDNode *Select_ARMISD_SYNCBARRIER(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_43(const SDValue &N, unsigned Opc0) {
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32);
+DISABLE_INLINE SDNode *Emit_43(SDNode *N, unsigned Opc0) {
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::i32);
}
-SDNode *Select_ARMISD_THREAD_POINTER_i32(const SDValue &N) {
+SDNode *Select_ARMISD_THREAD_POINTER_i32(SDNode *N) {
// Pattern: (ARMthread_pointer:i32)
// Emits: (TPsoft:isVoid)
@@ -3465,7 +3308,7 @@ SDNode *Select_ARMISD_THREAD_POINTER_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_UITOF_f32(const SDValue &N) {
+SDNode *Select_ARMISD_UITOF_f32(SDNode *N) {
// Pattern: (arm_uitof:f32 SPR:f32:$a)
// Emits: (VUITOS:f32 SPR:f32:$a)
@@ -3487,7 +3330,7 @@ SDNode *Select_ARMISD_UITOF_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_UITOF_f64(const SDValue &N) {
+SDNode *Select_ARMISD_UITOF_f64(SDNode *N) {
if ((Subtarget->hasVFP2())) {
SDNode *Result = Emit_31(N, ARM::VUITOD, MVT::f64);
return Result;
@@ -3497,18 +3340,18 @@ SDNode *Select_ARMISD_UITOF_f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_44(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_44(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, N1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-SDNode *Select_ARMISD_VCEQ_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VCEQ_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_44(N, ARM::VCEQv8i8, MVT::v8i8);
return Result;
@@ -3519,10 +3362,10 @@ SDNode *Select_ARMISD_VCEQ_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCEQ_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VCEQ_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_44(N, ARM::VCEQv16i8, MVT::v16i8);
return Result;
@@ -3533,10 +3376,10 @@ SDNode *Select_ARMISD_VCEQ_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCEQ_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VCEQ_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_44(N, ARM::VCEQv4i16, MVT::v4i16);
return Result;
@@ -3547,10 +3390,10 @@ SDNode *Select_ARMISD_VCEQ_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCEQ_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VCEQ_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_44(N, ARM::VCEQv8i16, MVT::v8i16);
return Result;
@@ -3561,10 +3404,10 @@ SDNode *Select_ARMISD_VCEQ_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCEQ_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VCEQ_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (NEONvceq:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Emits: (VCEQv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
@@ -3587,10 +3430,10 @@ SDNode *Select_ARMISD_VCEQ_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCEQ_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VCEQ_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (NEONvceq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Emits: (VCEQv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
@@ -3613,10 +3456,10 @@ SDNode *Select_ARMISD_VCEQ_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGE_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VCGE_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_44(N, ARM::VCGEsv8i8, MVT::v8i8);
return Result;
@@ -3627,10 +3470,10 @@ SDNode *Select_ARMISD_VCGE_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGE_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VCGE_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_44(N, ARM::VCGEsv16i8, MVT::v16i8);
return Result;
@@ -3641,10 +3484,10 @@ SDNode *Select_ARMISD_VCGE_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGE_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VCGE_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_44(N, ARM::VCGEsv4i16, MVT::v4i16);
return Result;
@@ -3655,10 +3498,10 @@ SDNode *Select_ARMISD_VCGE_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGE_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VCGE_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_44(N, ARM::VCGEsv8i16, MVT::v8i16);
return Result;
@@ -3669,10 +3512,10 @@ SDNode *Select_ARMISD_VCGE_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGE_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VCGE_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (NEONvcge:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Emits: (VCGEsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
@@ -3695,10 +3538,10 @@ SDNode *Select_ARMISD_VCGE_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGE_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VCGE_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (NEONvcge:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Emits: (VCGEsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
@@ -3721,10 +3564,10 @@ SDNode *Select_ARMISD_VCGE_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGEU_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VCGEU_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_44(N, ARM::VCGEuv8i8, MVT::v8i8);
return Result;
@@ -3735,10 +3578,10 @@ SDNode *Select_ARMISD_VCGEU_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGEU_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VCGEU_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_44(N, ARM::VCGEuv16i8, MVT::v16i8);
return Result;
@@ -3749,10 +3592,10 @@ SDNode *Select_ARMISD_VCGEU_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGEU_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VCGEU_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_44(N, ARM::VCGEuv4i16, MVT::v4i16);
return Result;
@@ -3763,10 +3606,10 @@ SDNode *Select_ARMISD_VCGEU_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGEU_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VCGEU_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_44(N, ARM::VCGEuv8i16, MVT::v8i16);
return Result;
@@ -3777,10 +3620,10 @@ SDNode *Select_ARMISD_VCGEU_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGEU_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VCGEU_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_44(N, ARM::VCGEuv2i32, MVT::v2i32);
return Result;
@@ -3791,10 +3634,10 @@ SDNode *Select_ARMISD_VCGEU_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGEU_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VCGEU_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_44(N, ARM::VCGEuv4i32, MVT::v4i32);
return Result;
@@ -3805,10 +3648,10 @@ SDNode *Select_ARMISD_VCGEU_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGT_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VCGT_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_44(N, ARM::VCGTsv8i8, MVT::v8i8);
return Result;
@@ -3819,10 +3662,10 @@ SDNode *Select_ARMISD_VCGT_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGT_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VCGT_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_44(N, ARM::VCGTsv16i8, MVT::v16i8);
return Result;
@@ -3833,10 +3676,10 @@ SDNode *Select_ARMISD_VCGT_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGT_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VCGT_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_44(N, ARM::VCGTsv4i16, MVT::v4i16);
return Result;
@@ -3847,10 +3690,10 @@ SDNode *Select_ARMISD_VCGT_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGT_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VCGT_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_44(N, ARM::VCGTsv8i16, MVT::v8i16);
return Result;
@@ -3861,10 +3704,10 @@ SDNode *Select_ARMISD_VCGT_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGT_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VCGT_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (NEONvcgt:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Emits: (VCGTsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
@@ -3887,10 +3730,10 @@ SDNode *Select_ARMISD_VCGT_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGT_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VCGT_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (NEONvcgt:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Emits: (VCGTsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
@@ -3913,10 +3756,10 @@ SDNode *Select_ARMISD_VCGT_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGTU_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VCGTU_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_44(N, ARM::VCGTuv8i8, MVT::v8i8);
return Result;
@@ -3927,10 +3770,10 @@ SDNode *Select_ARMISD_VCGTU_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGTU_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VCGTU_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_44(N, ARM::VCGTuv16i8, MVT::v16i8);
return Result;
@@ -3941,10 +3784,10 @@ SDNode *Select_ARMISD_VCGTU_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGTU_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VCGTU_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_44(N, ARM::VCGTuv4i16, MVT::v4i16);
return Result;
@@ -3955,10 +3798,10 @@ SDNode *Select_ARMISD_VCGTU_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGTU_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VCGTU_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_44(N, ARM::VCGTuv8i16, MVT::v8i16);
return Result;
@@ -3969,10 +3812,10 @@ SDNode *Select_ARMISD_VCGTU_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGTU_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VCGTU_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_44(N, ARM::VCGTuv2i32, MVT::v2i32);
return Result;
@@ -3983,10 +3826,10 @@ SDNode *Select_ARMISD_VCGTU_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VCGTU_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VCGTU_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_44(N, ARM::VCGTuv4i32, MVT::v4i32);
return Result;
@@ -3997,9 +3840,9 @@ SDNode *Select_ARMISD_VCGTU_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VDUP_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VDUP_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_31(N, ARM::VDUP8d, MVT::v8i8);
return Result;
@@ -4010,9 +3853,9 @@ SDNode *Select_ARMISD_VDUP_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VDUP_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VDUP_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_31(N, ARM::VDUP8q, MVT::v16i8);
return Result;
@@ -4023,9 +3866,9 @@ SDNode *Select_ARMISD_VDUP_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VDUP_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VDUP_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_31(N, ARM::VDUP16d, MVT::v4i16);
return Result;
@@ -4036,9 +3879,9 @@ SDNode *Select_ARMISD_VDUP_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VDUP_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VDUP_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_31(N, ARM::VDUP16q, MVT::v8i16);
return Result;
@@ -4049,9 +3892,9 @@ SDNode *Select_ARMISD_VDUP_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VDUP_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VDUP_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_31(N, ARM::VDUP32d, MVT::v2i32);
return Result;
@@ -4062,9 +3905,9 @@ SDNode *Select_ARMISD_VDUP_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VDUP_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VDUP_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_31(N, ARM::VDUP32q, MVT::v4i32);
return Result;
@@ -4075,22 +3918,22 @@ SDNode *Select_ARMISD_VDUP_v4i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_45(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
+DISABLE_INLINE SDNode *Emit_45(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, Tmp1, Tmp2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, Tmp1, Tmp2);
}
-SDNode *Select_ARMISD_VDUP_v2f32(const SDValue &N) {
+SDNode *Select_ARMISD_VDUP_v2f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (NEONvdup:v2f32 (bitconvert:f32 GPR:i32:$src))
// Emits: (VDUPfd:v2f32 GPR:i32:$src)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
if (N0.getValueType() == MVT::f32 &&
N00.getValueType() == MVT::i32) {
SDNode *Result = Emit_45(N, ARM::VDUPfd, MVT::v2f32);
@@ -4111,15 +3954,15 @@ SDNode *Select_ARMISD_VDUP_v2f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VDUP_v4f32(const SDValue &N) {
+SDNode *Select_ARMISD_VDUP_v4f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (NEONvdup:v4f32 (bitconvert:f32 GPR:i32:$src))
// Emits: (VDUPfq:v4f32 GPR:i32:$src)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
if (N0.getValueType() == MVT::f32 &&
N00.getValueType() == MVT::i32) {
SDNode *Result = Emit_45(N, ARM::VDUPfq, MVT::v4f32);
@@ -4140,11 +3983,11 @@ SDNode *Select_ARMISD_VDUP_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VDUPLANE_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VDUPLANE_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_35(N, ARM::VDUPLN8d, MVT::v8i8);
return Result;
@@ -4155,27 +3998,27 @@ SDNode *Select_ARMISD_VDUPLANE_v8i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_46(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_46(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_DSubReg_i8_reg(Tmp1.getNode());
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp2), 0);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
SDValue Tmp4 = Transform_SubReg_i8_lane(Tmp1.getNode());
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { Tmp3, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 4);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 4);
}
-SDNode *Select_ARMISD_VDUPLANE_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VDUPLANE_v16i8(SDNode *N) {
// Pattern: (NEONvduplane:v16i8 DPR:v8i8:$src, (imm:i32):$lane)
// Emits: (VDUPLN8q:v16i8 DPR:v8i8:$src, (imm:i32):$lane)
// Pattern complexity = 6 cost = 1 size = 0
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_35(N, ARM::VDUPLN8q, MVT::v16i8);
return Result;
@@ -4185,9 +4028,9 @@ SDNode *Select_ARMISD_VDUPLANE_v16i8(const SDValue &N) {
// Pattern: (NEONvduplane:v16i8 QPR:v16i8:$src, (imm:i32):$lane)
// Emits: (VDUPLN8q:v16i8 (EXTRACT_SUBREG:v8i8 QPR:v16i8:$src, (DSubReg_i8_reg:i32 (imm:i32):$lane)), (SubReg_i8_lane:i32 (imm:i32):$lane))
// Pattern complexity = 6 cost = 2 size = 0
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_46(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VDUPLN8q, MVT::v8i8, MVT::v16i8);
return Result;
@@ -4197,11 +4040,11 @@ SDNode *Select_ARMISD_VDUPLANE_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VDUPLANE_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VDUPLANE_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_35(N, ARM::VDUPLN16d, MVT::v4i16);
return Result;
@@ -4212,27 +4055,27 @@ SDNode *Select_ARMISD_VDUPLANE_v4i16(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_47(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_47(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_DSubReg_i16_reg(Tmp1.getNode());
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp2), 0);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
SDValue Tmp4 = Transform_SubReg_i16_lane(Tmp1.getNode());
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { Tmp3, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 4);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 4);
}
-SDNode *Select_ARMISD_VDUPLANE_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VDUPLANE_v8i16(SDNode *N) {
// Pattern: (NEONvduplane:v8i16 DPR:v4i16:$src, (imm:i32):$lane)
// Emits: (VDUPLN16q:v8i16 DPR:v4i16:$src, (imm:i32):$lane)
// Pattern complexity = 6 cost = 1 size = 0
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_35(N, ARM::VDUPLN16q, MVT::v8i16);
return Result;
@@ -4242,9 +4085,9 @@ SDNode *Select_ARMISD_VDUPLANE_v8i16(const SDValue &N) {
// Pattern: (NEONvduplane:v8i16 QPR:v8i16:$src, (imm:i32):$lane)
// Emits: (VDUPLN16q:v8i16 (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
// Pattern complexity = 6 cost = 2 size = 0
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_47(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VDUPLN16q, MVT::v4i16, MVT::v8i16);
return Result;
@@ -4254,11 +4097,11 @@ SDNode *Select_ARMISD_VDUPLANE_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VDUPLANE_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VDUPLANE_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_35(N, ARM::VDUPLN32d, MVT::v2i32);
return Result;
@@ -4269,27 +4112,27 @@ SDNode *Select_ARMISD_VDUPLANE_v2i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_48(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_48(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_DSubReg_i32_reg(Tmp1.getNode());
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp2), 0);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
SDValue Tmp4 = Transform_SubReg_i32_lane(Tmp1.getNode());
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { Tmp3, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 4);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 4);
}
-SDNode *Select_ARMISD_VDUPLANE_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VDUPLANE_v4i32(SDNode *N) {
// Pattern: (NEONvduplane:v4i32 DPR:v2i32:$src, (imm:i32):$lane)
// Emits: (VDUPLN32q:v4i32 DPR:v2i32:$src, (imm:i32):$lane)
// Pattern complexity = 6 cost = 1 size = 0
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_35(N, ARM::VDUPLN32q, MVT::v4i32);
return Result;
@@ -4299,9 +4142,9 @@ SDNode *Select_ARMISD_VDUPLANE_v4i32(const SDValue &N) {
// Pattern: (NEONvduplane:v4i32 QPR:v4i32:$src, (imm:i32):$lane)
// Emits: (VDUPLN32q:v4i32 (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 6 cost = 2 size = 0
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_48(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VDUPLN32q, MVT::v2i32, MVT::v4i32);
return Result;
@@ -4311,19 +4154,19 @@ SDNode *Select_ARMISD_VDUPLANE_v4i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_49(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_49(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp3 = Transform_DSubReg_f64_reg(Tmp2.getNode());
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp3), 0);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp3), 0);
SDValue Tmp5 = Transform_DSubReg_f64_other_reg(Tmp2.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, N0, Tmp4, Tmp5);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, N0, Tmp4, Tmp5);
}
-SDNode *Select_ARMISD_VDUPLANE_v2i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+SDNode *Select_ARMISD_VDUPLANE_v2i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_49(N, TargetInstrInfo::EXTRACT_SUBREG, TargetInstrInfo::INSERT_SUBREG, MVT::i64, MVT::v2i64);
return Result;
@@ -4333,11 +4176,11 @@ SDNode *Select_ARMISD_VDUPLANE_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VDUPLANE_v2f32(const SDValue &N) {
+SDNode *Select_ARMISD_VDUPLANE_v2f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_35(N, ARM::VDUPLNfd, MVT::v2f32);
return Result;
@@ -4348,15 +4191,15 @@ SDNode *Select_ARMISD_VDUPLANE_v2f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VDUPLANE_v4f32(const SDValue &N) {
+SDNode *Select_ARMISD_VDUPLANE_v4f32(SDNode *N) {
// Pattern: (NEONvduplane:v4f32 DPR:v2f32:$src, (imm:i32):$lane)
// Emits: (VDUPLNfq:v4f32 DPR:v2f32:$src, (imm:i32):$lane)
// Pattern complexity = 6 cost = 1 size = 0
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_35(N, ARM::VDUPLNfq, MVT::v4f32);
return Result;
@@ -4366,9 +4209,9 @@ SDNode *Select_ARMISD_VDUPLANE_v4f32(const SDValue &N) {
// Pattern: (NEONvduplane:v4f32 QPR:v4f32:$src, (imm:i32):$lane)
// Emits: (VDUPLNfq:v4f32 (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 6 cost = 2 size = 0
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_48(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VDUPLNfq, MVT::v2f32, MVT::v4f32);
return Result;
@@ -4378,10 +4221,10 @@ SDNode *Select_ARMISD_VDUPLANE_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VDUPLANE_v2f64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+SDNode *Select_ARMISD_VDUPLANE_v2f64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2f64) {
SDNode *Result = Emit_49(N, TargetInstrInfo::EXTRACT_SUBREG, TargetInstrInfo::INSERT_SUBREG, MVT::f64, MVT::v2f64);
return Result;
@@ -4391,22 +4234,22 @@ SDNode *Select_ARMISD_VDUPLANE_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_50(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_50(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, N1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-SDNode *Select_ARMISD_VEXT_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VEXT_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VEXTd8, MVT::v8i8);
return Result;
}
@@ -4416,12 +4259,12 @@ SDNode *Select_ARMISD_VEXT_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VEXT_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VEXT_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VEXTq8, MVT::v16i8);
return Result;
}
@@ -4431,12 +4274,12 @@ SDNode *Select_ARMISD_VEXT_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VEXT_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VEXT_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VEXTd16, MVT::v4i16);
return Result;
}
@@ -4446,12 +4289,12 @@ SDNode *Select_ARMISD_VEXT_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VEXT_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VEXT_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VEXTq16, MVT::v8i16);
return Result;
}
@@ -4461,12 +4304,12 @@ SDNode *Select_ARMISD_VEXT_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VEXT_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VEXT_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VEXTd32, MVT::v2i32);
return Result;
}
@@ -4476,12 +4319,12 @@ SDNode *Select_ARMISD_VEXT_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VEXT_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VEXT_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VEXTq32, MVT::v4i32);
return Result;
}
@@ -4491,12 +4334,12 @@ SDNode *Select_ARMISD_VEXT_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VEXT_v2f32(const SDValue &N) {
+SDNode *Select_ARMISD_VEXT_v2f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VEXTdf, MVT::v2f32);
return Result;
}
@@ -4506,12 +4349,12 @@ SDNode *Select_ARMISD_VEXT_v2f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VEXT_v4f32(const SDValue &N) {
+SDNode *Select_ARMISD_VEXT_v4f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VEXTqf, MVT::v4f32);
return Result;
}
@@ -4521,11 +4364,11 @@ SDNode *Select_ARMISD_VEXT_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VGETLANEs_i32(const SDValue &N) {
+SDNode *Select_ARMISD_VGETLANEs_i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (NEONvgetlanes:i32 DPR:v8i8:$src, (imm:i32):$lane)
// Emits: (VGETLNs8:i32 DPR:v8i8:$src, (imm:i32):$lane)
@@ -4544,9 +4387,9 @@ SDNode *Select_ARMISD_VGETLANEs_i32(const SDValue &N) {
}
}
}
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (NEONvgetlanes:i32 QPR:v16i8:$src, (imm:i32):$lane)
// Emits: (VGETLNs8:i32 (EXTRACT_SUBREG:v8i8 QPR:v16i8:$src, (DSubReg_i8_reg:i32 (imm:i32):$lane)), (SubReg_i8_lane:i32 (imm:i32):$lane))
@@ -4569,11 +4412,11 @@ SDNode *Select_ARMISD_VGETLANEs_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VGETLANEu_i32(const SDValue &N) {
+SDNode *Select_ARMISD_VGETLANEu_i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (NEONvgetlaneu:i32 DPR:v8i8:$src, (imm:i32):$lane)
// Emits: (VGETLNu8:i32 DPR:v8i8:$src, (imm:i32):$lane)
@@ -4592,9 +4435,9 @@ SDNode *Select_ARMISD_VGETLANEu_i32(const SDValue &N) {
}
}
}
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (NEONvgetlaneu:i32 QPR:v16i8:$src, (imm:i32):$lane)
// Emits: (VGETLNu8:i32 (EXTRACT_SUBREG:v8i8 QPR:v16i8:$src, (DSubReg_i8_reg:i32 (imm:i32):$lane)), (SubReg_i8_lane:i32 (imm:i32):$lane))
@@ -4617,7 +4460,7 @@ SDNode *Select_ARMISD_VGETLANEu_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VMOVDRR_f64(const SDValue &N) {
+SDNode *Select_ARMISD_VMOVDRR_f64(SDNode *N) {
if ((Subtarget->hasVFP2())) {
SDNode *Result = Emit_44(N, ARM::VMOVDRR, MVT::f64);
return Result;
@@ -4627,11 +4470,11 @@ SDNode *Select_ARMISD_VMOVDRR_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQRSHRNs_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VQRSHRNs_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_35(N, ARM::VQRSHRNsv8i8, MVT::v8i8);
return Result;
@@ -4642,11 +4485,11 @@ SDNode *Select_ARMISD_VQRSHRNs_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQRSHRNs_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VQRSHRNs_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_35(N, ARM::VQRSHRNsv4i16, MVT::v4i16);
return Result;
@@ -4657,11 +4500,11 @@ SDNode *Select_ARMISD_VQRSHRNs_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQRSHRNs_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VQRSHRNs_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_35(N, ARM::VQRSHRNsv2i32, MVT::v2i32);
return Result;
@@ -4672,11 +4515,11 @@ SDNode *Select_ARMISD_VQRSHRNs_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQRSHRNsu_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VQRSHRNsu_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_35(N, ARM::VQRSHRUNv8i8, MVT::v8i8);
return Result;
@@ -4687,11 +4530,11 @@ SDNode *Select_ARMISD_VQRSHRNsu_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQRSHRNsu_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VQRSHRNsu_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_35(N, ARM::VQRSHRUNv4i16, MVT::v4i16);
return Result;
@@ -4702,11 +4545,11 @@ SDNode *Select_ARMISD_VQRSHRNsu_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQRSHRNsu_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VQRSHRNsu_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_35(N, ARM::VQRSHRUNv2i32, MVT::v2i32);
return Result;
@@ -4717,11 +4560,11 @@ SDNode *Select_ARMISD_VQRSHRNsu_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQRSHRNu_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VQRSHRNu_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_35(N, ARM::VQRSHRNuv8i8, MVT::v8i8);
return Result;
@@ -4732,11 +4575,11 @@ SDNode *Select_ARMISD_VQRSHRNu_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQRSHRNu_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VQRSHRNu_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_35(N, ARM::VQRSHRNuv4i16, MVT::v4i16);
return Result;
@@ -4747,11 +4590,11 @@ SDNode *Select_ARMISD_VQRSHRNu_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQRSHRNu_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VQRSHRNu_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_35(N, ARM::VQRSHRNuv2i32, MVT::v2i32);
return Result;
@@ -4762,11 +4605,11 @@ SDNode *Select_ARMISD_VQRSHRNu_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLs_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLs_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLsiv8i8, MVT::v8i8);
return Result;
}
@@ -4776,11 +4619,11 @@ SDNode *Select_ARMISD_VQSHLs_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLs_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLs_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLsiv16i8, MVT::v16i8);
return Result;
}
@@ -4790,11 +4633,11 @@ SDNode *Select_ARMISD_VQSHLs_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLs_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLs_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLsiv4i16, MVT::v4i16);
return Result;
}
@@ -4804,11 +4647,11 @@ SDNode *Select_ARMISD_VQSHLs_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLs_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLs_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLsiv8i16, MVT::v8i16);
return Result;
}
@@ -4818,11 +4661,11 @@ SDNode *Select_ARMISD_VQSHLs_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLs_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLs_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLsiv2i32, MVT::v2i32);
return Result;
}
@@ -4832,11 +4675,11 @@ SDNode *Select_ARMISD_VQSHLs_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLs_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLs_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLsiv4i32, MVT::v4i32);
return Result;
}
@@ -4846,11 +4689,11 @@ SDNode *Select_ARMISD_VQSHLs_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLs_v1i64(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLs_v1i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLsiv1i64, MVT::v1i64);
return Result;
}
@@ -4860,11 +4703,11 @@ SDNode *Select_ARMISD_VQSHLs_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLs_v2i64(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLs_v2i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLsiv2i64, MVT::v2i64);
return Result;
}
@@ -4874,11 +4717,11 @@ SDNode *Select_ARMISD_VQSHLs_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLsu_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLsu_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLsuv8i8, MVT::v8i8);
return Result;
}
@@ -4888,11 +4731,11 @@ SDNode *Select_ARMISD_VQSHLsu_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLsu_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLsu_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLsuv16i8, MVT::v16i8);
return Result;
}
@@ -4902,11 +4745,11 @@ SDNode *Select_ARMISD_VQSHLsu_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLsu_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLsu_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLsuv4i16, MVT::v4i16);
return Result;
}
@@ -4916,11 +4759,11 @@ SDNode *Select_ARMISD_VQSHLsu_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLsu_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLsu_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLsuv8i16, MVT::v8i16);
return Result;
}
@@ -4930,11 +4773,11 @@ SDNode *Select_ARMISD_VQSHLsu_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLsu_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLsu_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLsuv2i32, MVT::v2i32);
return Result;
}
@@ -4944,11 +4787,11 @@ SDNode *Select_ARMISD_VQSHLsu_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLsu_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLsu_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLsuv4i32, MVT::v4i32);
return Result;
}
@@ -4958,11 +4801,11 @@ SDNode *Select_ARMISD_VQSHLsu_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLsu_v1i64(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLsu_v1i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLsuv1i64, MVT::v1i64);
return Result;
}
@@ -4972,11 +4815,11 @@ SDNode *Select_ARMISD_VQSHLsu_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLsu_v2i64(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLsu_v2i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLsuv2i64, MVT::v2i64);
return Result;
}
@@ -4986,11 +4829,11 @@ SDNode *Select_ARMISD_VQSHLsu_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLu_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLu_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLuiv8i8, MVT::v8i8);
return Result;
}
@@ -5000,11 +4843,11 @@ SDNode *Select_ARMISD_VQSHLu_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLu_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLu_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLuiv16i8, MVT::v16i8);
return Result;
}
@@ -5014,11 +4857,11 @@ SDNode *Select_ARMISD_VQSHLu_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLu_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLu_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLuiv4i16, MVT::v4i16);
return Result;
}
@@ -5028,11 +4871,11 @@ SDNode *Select_ARMISD_VQSHLu_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLu_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLu_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLuiv8i16, MVT::v8i16);
return Result;
}
@@ -5042,11 +4885,11 @@ SDNode *Select_ARMISD_VQSHLu_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLu_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLu_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLuiv2i32, MVT::v2i32);
return Result;
}
@@ -5056,11 +4899,11 @@ SDNode *Select_ARMISD_VQSHLu_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLu_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLu_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLuiv4i32, MVT::v4i32);
return Result;
}
@@ -5070,11 +4913,11 @@ SDNode *Select_ARMISD_VQSHLu_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLu_v1i64(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLu_v1i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLuiv1i64, MVT::v1i64);
return Result;
}
@@ -5084,11 +4927,11 @@ SDNode *Select_ARMISD_VQSHLu_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHLu_v2i64(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHLu_v2i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VQSHLuiv2i64, MVT::v2i64);
return Result;
}
@@ -5098,11 +4941,11 @@ SDNode *Select_ARMISD_VQSHLu_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHRNs_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHRNs_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_35(N, ARM::VQSHRNsv8i8, MVT::v8i8);
return Result;
@@ -5113,11 +4956,11 @@ SDNode *Select_ARMISD_VQSHRNs_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHRNs_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHRNs_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_35(N, ARM::VQSHRNsv4i16, MVT::v4i16);
return Result;
@@ -5128,11 +4971,11 @@ SDNode *Select_ARMISD_VQSHRNs_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHRNs_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHRNs_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_35(N, ARM::VQSHRNsv2i32, MVT::v2i32);
return Result;
@@ -5143,11 +4986,11 @@ SDNode *Select_ARMISD_VQSHRNs_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHRNsu_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHRNsu_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_35(N, ARM::VQSHRUNv8i8, MVT::v8i8);
return Result;
@@ -5158,11 +5001,11 @@ SDNode *Select_ARMISD_VQSHRNsu_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHRNsu_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHRNsu_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_35(N, ARM::VQSHRUNv4i16, MVT::v4i16);
return Result;
@@ -5173,11 +5016,11 @@ SDNode *Select_ARMISD_VQSHRNsu_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHRNsu_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHRNsu_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_35(N, ARM::VQSHRUNv2i32, MVT::v2i32);
return Result;
@@ -5188,11 +5031,11 @@ SDNode *Select_ARMISD_VQSHRNsu_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHRNu_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHRNu_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_35(N, ARM::VQSHRNuv8i8, MVT::v8i8);
return Result;
@@ -5203,11 +5046,11 @@ SDNode *Select_ARMISD_VQSHRNu_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHRNu_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHRNu_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_35(N, ARM::VQSHRNuv4i16, MVT::v4i16);
return Result;
@@ -5218,11 +5061,11 @@ SDNode *Select_ARMISD_VQSHRNu_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VQSHRNu_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VQSHRNu_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_35(N, ARM::VQSHRNuv2i32, MVT::v2i32);
return Result;
@@ -5233,7 +5076,7 @@ SDNode *Select_ARMISD_VQSHRNu_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VREV16_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VREV16_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
SDNode *Result = Emit_31(N, ARM::VREV16d8, MVT::v8i8);
return Result;
@@ -5243,7 +5086,7 @@ SDNode *Select_ARMISD_VREV16_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VREV16_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VREV16_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
SDNode *Result = Emit_31(N, ARM::VREV16q8, MVT::v16i8);
return Result;
@@ -5253,7 +5096,7 @@ SDNode *Select_ARMISD_VREV16_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VREV32_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VREV32_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
SDNode *Result = Emit_31(N, ARM::VREV32d8, MVT::v8i8);
return Result;
@@ -5263,7 +5106,7 @@ SDNode *Select_ARMISD_VREV32_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VREV32_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VREV32_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
SDNode *Result = Emit_31(N, ARM::VREV32q8, MVT::v16i8);
return Result;
@@ -5273,7 +5116,7 @@ SDNode *Select_ARMISD_VREV32_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VREV32_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VREV32_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
SDNode *Result = Emit_31(N, ARM::VREV32d16, MVT::v4i16);
return Result;
@@ -5283,7 +5126,7 @@ SDNode *Select_ARMISD_VREV32_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VREV32_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VREV32_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
SDNode *Result = Emit_31(N, ARM::VREV32q16, MVT::v8i16);
return Result;
@@ -5293,7 +5136,7 @@ SDNode *Select_ARMISD_VREV32_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VREV64_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VREV64_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
SDNode *Result = Emit_31(N, ARM::VREV64d8, MVT::v8i8);
return Result;
@@ -5303,7 +5146,7 @@ SDNode *Select_ARMISD_VREV64_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VREV64_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VREV64_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
SDNode *Result = Emit_31(N, ARM::VREV64q8, MVT::v16i8);
return Result;
@@ -5313,7 +5156,7 @@ SDNode *Select_ARMISD_VREV64_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VREV64_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VREV64_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
SDNode *Result = Emit_31(N, ARM::VREV64d16, MVT::v4i16);
return Result;
@@ -5323,7 +5166,7 @@ SDNode *Select_ARMISD_VREV64_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VREV64_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VREV64_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
SDNode *Result = Emit_31(N, ARM::VREV64q16, MVT::v8i16);
return Result;
@@ -5333,7 +5176,7 @@ SDNode *Select_ARMISD_VREV64_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VREV64_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VREV64_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
SDNode *Result = Emit_31(N, ARM::VREV64d32, MVT::v2i32);
return Result;
@@ -5343,7 +5186,7 @@ SDNode *Select_ARMISD_VREV64_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VREV64_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VREV64_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
SDNode *Result = Emit_31(N, ARM::VREV64q32, MVT::v4i32);
return Result;
@@ -5353,7 +5196,7 @@ SDNode *Select_ARMISD_VREV64_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VREV64_v2f32(const SDValue &N) {
+SDNode *Select_ARMISD_VREV64_v2f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
SDNode *Result = Emit_31(N, ARM::VREV64df, MVT::v2f32);
return Result;
@@ -5363,7 +5206,7 @@ SDNode *Select_ARMISD_VREV64_v2f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VREV64_v4f32(const SDValue &N) {
+SDNode *Select_ARMISD_VREV64_v4f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
SDNode *Result = Emit_31(N, ARM::VREV64qf, MVT::v4f32);
return Result;
@@ -5373,11 +5216,11 @@ SDNode *Select_ARMISD_VREV64_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VRSHRN_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VRSHRN_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_35(N, ARM::VRSHRNv8i8, MVT::v8i8);
return Result;
@@ -5388,11 +5231,11 @@ SDNode *Select_ARMISD_VRSHRN_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VRSHRN_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VRSHRN_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_35(N, ARM::VRSHRNv4i16, MVT::v4i16);
return Result;
@@ -5403,11 +5246,11 @@ SDNode *Select_ARMISD_VRSHRN_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VRSHRN_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VRSHRN_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_35(N, ARM::VRSHRNv2i32, MVT::v2i32);
return Result;
@@ -5418,11 +5261,11 @@ SDNode *Select_ARMISD_VRSHRN_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VRSHRs_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VRSHRs_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VRSHRsv8i8, MVT::v8i8);
return Result;
}
@@ -5432,11 +5275,11 @@ SDNode *Select_ARMISD_VRSHRs_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VRSHRs_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VRSHRs_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VRSHRsv16i8, MVT::v16i8);
return Result;
}
@@ -5446,11 +5289,11 @@ SDNode *Select_ARMISD_VRSHRs_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VRSHRs_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VRSHRs_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VRSHRsv4i16, MVT::v4i16);
return Result;
}
@@ -5460,11 +5303,11 @@ SDNode *Select_ARMISD_VRSHRs_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VRSHRs_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VRSHRs_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VRSHRsv8i16, MVT::v8i16);
return Result;
}
@@ -5474,11 +5317,11 @@ SDNode *Select_ARMISD_VRSHRs_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VRSHRs_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VRSHRs_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VRSHRsv2i32, MVT::v2i32);
return Result;
}
@@ -5488,11 +5331,11 @@ SDNode *Select_ARMISD_VRSHRs_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VRSHRs_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VRSHRs_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VRSHRsv4i32, MVT::v4i32);
return Result;
}
@@ -5502,11 +5345,11 @@ SDNode *Select_ARMISD_VRSHRs_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VRSHRs_v1i64(const SDValue &N) {
+SDNode *Select_ARMISD_VRSHRs_v1i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VRSHRsv1i64, MVT::v1i64);
return Result;
}
@@ -5516,11 +5359,11 @@ SDNode *Select_ARMISD_VRSHRs_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VRSHRs_v2i64(const SDValue &N) {
+SDNode *Select_ARMISD_VRSHRs_v2i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VRSHRsv2i64, MVT::v2i64);
return Result;
}
@@ -5530,11 +5373,11 @@ SDNode *Select_ARMISD_VRSHRs_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VRSHRu_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VRSHRu_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VRSHRuv8i8, MVT::v8i8);
return Result;
}
@@ -5544,11 +5387,11 @@ SDNode *Select_ARMISD_VRSHRu_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VRSHRu_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VRSHRu_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VRSHRuv16i8, MVT::v16i8);
return Result;
}
@@ -5558,11 +5401,11 @@ SDNode *Select_ARMISD_VRSHRu_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VRSHRu_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VRSHRu_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VRSHRuv4i16, MVT::v4i16);
return Result;
}
@@ -5572,11 +5415,11 @@ SDNode *Select_ARMISD_VRSHRu_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VRSHRu_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VRSHRu_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VRSHRuv8i16, MVT::v8i16);
return Result;
}
@@ -5586,11 +5429,11 @@ SDNode *Select_ARMISD_VRSHRu_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VRSHRu_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VRSHRu_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VRSHRuv2i32, MVT::v2i32);
return Result;
}
@@ -5600,11 +5443,11 @@ SDNode *Select_ARMISD_VRSHRu_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VRSHRu_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VRSHRu_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VRSHRuv4i32, MVT::v4i32);
return Result;
}
@@ -5614,11 +5457,11 @@ SDNode *Select_ARMISD_VRSHRu_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VRSHRu_v1i64(const SDValue &N) {
+SDNode *Select_ARMISD_VRSHRu_v1i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VRSHRuv1i64, MVT::v1i64);
return Result;
}
@@ -5628,11 +5471,11 @@ SDNode *Select_ARMISD_VRSHRu_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VRSHRu_v2i64(const SDValue &N) {
+SDNode *Select_ARMISD_VRSHRu_v2i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VRSHRuv2i64, MVT::v2i64);
return Result;
}
@@ -5642,11 +5485,11 @@ SDNode *Select_ARMISD_VRSHRu_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHL_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VSHL_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHLiv8i8, MVT::v8i8);
return Result;
}
@@ -5656,11 +5499,11 @@ SDNode *Select_ARMISD_VSHL_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHL_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VSHL_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHLiv16i8, MVT::v16i8);
return Result;
}
@@ -5670,11 +5513,11 @@ SDNode *Select_ARMISD_VSHL_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHL_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VSHL_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHLiv4i16, MVT::v4i16);
return Result;
}
@@ -5684,11 +5527,11 @@ SDNode *Select_ARMISD_VSHL_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHL_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VSHL_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHLiv8i16, MVT::v8i16);
return Result;
}
@@ -5698,11 +5541,11 @@ SDNode *Select_ARMISD_VSHL_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHL_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VSHL_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHLiv2i32, MVT::v2i32);
return Result;
}
@@ -5712,11 +5555,11 @@ SDNode *Select_ARMISD_VSHL_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHL_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VSHL_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHLiv4i32, MVT::v4i32);
return Result;
}
@@ -5726,11 +5569,11 @@ SDNode *Select_ARMISD_VSHL_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHL_v1i64(const SDValue &N) {
+SDNode *Select_ARMISD_VSHL_v1i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHLiv1i64, MVT::v1i64);
return Result;
}
@@ -5740,11 +5583,11 @@ SDNode *Select_ARMISD_VSHL_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHL_v2i64(const SDValue &N) {
+SDNode *Select_ARMISD_VSHL_v2i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHLiv2i64, MVT::v2i64);
return Result;
}
@@ -5754,11 +5597,11 @@ SDNode *Select_ARMISD_VSHL_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHLLi_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VSHLLi_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_35(N, ARM::VSHLLi8, MVT::v8i16);
return Result;
@@ -5769,11 +5612,11 @@ SDNode *Select_ARMISD_VSHLLi_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHLLi_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VSHLLi_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_35(N, ARM::VSHLLi16, MVT::v4i32);
return Result;
@@ -5784,11 +5627,11 @@ SDNode *Select_ARMISD_VSHLLi_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHLLi_v2i64(const SDValue &N) {
+SDNode *Select_ARMISD_VSHLLi_v2i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_35(N, ARM::VSHLLi32, MVT::v2i64);
return Result;
@@ -5799,11 +5642,11 @@ SDNode *Select_ARMISD_VSHLLi_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHLLs_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VSHLLs_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_35(N, ARM::VSHLLsv8i16, MVT::v8i16);
return Result;
@@ -5814,11 +5657,11 @@ SDNode *Select_ARMISD_VSHLLs_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHLLs_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VSHLLs_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_35(N, ARM::VSHLLsv4i32, MVT::v4i32);
return Result;
@@ -5829,11 +5672,11 @@ SDNode *Select_ARMISD_VSHLLs_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHLLs_v2i64(const SDValue &N) {
+SDNode *Select_ARMISD_VSHLLs_v2i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_35(N, ARM::VSHLLsv2i64, MVT::v2i64);
return Result;
@@ -5844,11 +5687,11 @@ SDNode *Select_ARMISD_VSHLLs_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHLLu_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VSHLLu_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_35(N, ARM::VSHLLuv8i16, MVT::v8i16);
return Result;
@@ -5859,11 +5702,11 @@ SDNode *Select_ARMISD_VSHLLu_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHLLu_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VSHLLu_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_35(N, ARM::VSHLLuv4i32, MVT::v4i32);
return Result;
@@ -5874,11 +5717,11 @@ SDNode *Select_ARMISD_VSHLLu_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHLLu_v2i64(const SDValue &N) {
+SDNode *Select_ARMISD_VSHLLu_v2i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_35(N, ARM::VSHLLuv2i64, MVT::v2i64);
return Result;
@@ -5889,11 +5732,11 @@ SDNode *Select_ARMISD_VSHLLu_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHRN_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VSHRN_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_35(N, ARM::VSHRNv8i8, MVT::v8i8);
return Result;
@@ -5904,11 +5747,11 @@ SDNode *Select_ARMISD_VSHRN_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHRN_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VSHRN_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_35(N, ARM::VSHRNv4i16, MVT::v4i16);
return Result;
@@ -5919,11 +5762,11 @@ SDNode *Select_ARMISD_VSHRN_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHRN_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VSHRN_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_35(N, ARM::VSHRNv2i32, MVT::v2i32);
return Result;
@@ -5934,11 +5777,11 @@ SDNode *Select_ARMISD_VSHRN_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHRs_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VSHRs_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHRsv8i8, MVT::v8i8);
return Result;
}
@@ -5948,11 +5791,11 @@ SDNode *Select_ARMISD_VSHRs_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHRs_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VSHRs_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHRsv16i8, MVT::v16i8);
return Result;
}
@@ -5962,11 +5805,11 @@ SDNode *Select_ARMISD_VSHRs_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHRs_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VSHRs_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHRsv4i16, MVT::v4i16);
return Result;
}
@@ -5976,11 +5819,11 @@ SDNode *Select_ARMISD_VSHRs_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHRs_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VSHRs_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHRsv8i16, MVT::v8i16);
return Result;
}
@@ -5990,11 +5833,11 @@ SDNode *Select_ARMISD_VSHRs_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHRs_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VSHRs_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHRsv2i32, MVT::v2i32);
return Result;
}
@@ -6004,11 +5847,11 @@ SDNode *Select_ARMISD_VSHRs_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHRs_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VSHRs_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHRsv4i32, MVT::v4i32);
return Result;
}
@@ -6018,11 +5861,11 @@ SDNode *Select_ARMISD_VSHRs_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHRs_v1i64(const SDValue &N) {
+SDNode *Select_ARMISD_VSHRs_v1i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHRsv1i64, MVT::v1i64);
return Result;
}
@@ -6032,11 +5875,11 @@ SDNode *Select_ARMISD_VSHRs_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHRs_v2i64(const SDValue &N) {
+SDNode *Select_ARMISD_VSHRs_v2i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHRsv2i64, MVT::v2i64);
return Result;
}
@@ -6046,11 +5889,11 @@ SDNode *Select_ARMISD_VSHRs_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHRu_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VSHRu_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHRuv8i8, MVT::v8i8);
return Result;
}
@@ -6060,11 +5903,11 @@ SDNode *Select_ARMISD_VSHRu_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHRu_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VSHRu_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHRuv16i8, MVT::v16i8);
return Result;
}
@@ -6074,11 +5917,11 @@ SDNode *Select_ARMISD_VSHRu_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHRu_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VSHRu_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHRuv4i16, MVT::v4i16);
return Result;
}
@@ -6088,11 +5931,11 @@ SDNode *Select_ARMISD_VSHRu_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHRu_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VSHRu_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHRuv8i16, MVT::v8i16);
return Result;
}
@@ -6102,11 +5945,11 @@ SDNode *Select_ARMISD_VSHRu_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHRu_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VSHRu_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHRuv2i32, MVT::v2i32);
return Result;
}
@@ -6116,11 +5959,11 @@ SDNode *Select_ARMISD_VSHRu_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHRu_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VSHRu_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHRuv4i32, MVT::v4i32);
return Result;
}
@@ -6130,11 +5973,11 @@ SDNode *Select_ARMISD_VSHRu_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHRu_v1i64(const SDValue &N) {
+SDNode *Select_ARMISD_VSHRu_v1i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHRuv1i64, MVT::v1i64);
return Result;
}
@@ -6144,11 +5987,11 @@ SDNode *Select_ARMISD_VSHRu_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSHRu_v2i64(const SDValue &N) {
+SDNode *Select_ARMISD_VSHRu_v2i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::VSHRuv2i64, MVT::v2i64);
return Result;
}
@@ -6158,12 +6001,12 @@ SDNode *Select_ARMISD_VSHRu_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSLI_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VSLI_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VSLIv8i8, MVT::v8i8);
return Result;
}
@@ -6173,12 +6016,12 @@ SDNode *Select_ARMISD_VSLI_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSLI_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VSLI_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VSLIv16i8, MVT::v16i8);
return Result;
}
@@ -6188,12 +6031,12 @@ SDNode *Select_ARMISD_VSLI_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSLI_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VSLI_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VSLIv4i16, MVT::v4i16);
return Result;
}
@@ -6203,12 +6046,12 @@ SDNode *Select_ARMISD_VSLI_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSLI_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VSLI_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VSLIv8i16, MVT::v8i16);
return Result;
}
@@ -6218,12 +6061,12 @@ SDNode *Select_ARMISD_VSLI_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSLI_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VSLI_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VSLIv2i32, MVT::v2i32);
return Result;
}
@@ -6233,12 +6076,12 @@ SDNode *Select_ARMISD_VSLI_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSLI_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VSLI_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VSLIv4i32, MVT::v4i32);
return Result;
}
@@ -6248,12 +6091,12 @@ SDNode *Select_ARMISD_VSLI_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSLI_v1i64(const SDValue &N) {
+SDNode *Select_ARMISD_VSLI_v1i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VSLIv1i64, MVT::v1i64);
return Result;
}
@@ -6263,12 +6106,12 @@ SDNode *Select_ARMISD_VSLI_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSLI_v2i64(const SDValue &N) {
+SDNode *Select_ARMISD_VSLI_v2i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VSLIv2i64, MVT::v2i64);
return Result;
}
@@ -6278,12 +6121,12 @@ SDNode *Select_ARMISD_VSLI_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSRI_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VSRI_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VSRIv8i8, MVT::v8i8);
return Result;
}
@@ -6293,12 +6136,12 @@ SDNode *Select_ARMISD_VSRI_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSRI_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VSRI_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VSRIv16i8, MVT::v16i8);
return Result;
}
@@ -6308,12 +6151,12 @@ SDNode *Select_ARMISD_VSRI_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSRI_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VSRI_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VSRIv4i16, MVT::v4i16);
return Result;
}
@@ -6323,12 +6166,12 @@ SDNode *Select_ARMISD_VSRI_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSRI_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VSRI_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VSRIv8i16, MVT::v8i16);
return Result;
}
@@ -6338,12 +6181,12 @@ SDNode *Select_ARMISD_VSRI_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSRI_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VSRI_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VSRIv2i32, MVT::v2i32);
return Result;
}
@@ -6353,12 +6196,12 @@ SDNode *Select_ARMISD_VSRI_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSRI_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VSRI_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VSRIv4i32, MVT::v4i32);
return Result;
}
@@ -6368,12 +6211,12 @@ SDNode *Select_ARMISD_VSRI_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSRI_v1i64(const SDValue &N) {
+SDNode *Select_ARMISD_VSRI_v1i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VSRIv1i64, MVT::v1i64);
return Result;
}
@@ -6383,12 +6226,12 @@ SDNode *Select_ARMISD_VSRI_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VSRI_v2i64(const SDValue &N) {
+SDNode *Select_ARMISD_VSRI_v2i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VSRIv2i64, MVT::v2i64);
return Result;
}
@@ -6398,10 +6241,10 @@ SDNode *Select_ARMISD_VSRI_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VTST_v8i8(const SDValue &N) {
+SDNode *Select_ARMISD_VTST_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_44(N, ARM::VTSTv8i8, MVT::v8i8);
return Result;
@@ -6412,10 +6255,10 @@ SDNode *Select_ARMISD_VTST_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VTST_v16i8(const SDValue &N) {
+SDNode *Select_ARMISD_VTST_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_44(N, ARM::VTSTv16i8, MVT::v16i8);
return Result;
@@ -6426,10 +6269,10 @@ SDNode *Select_ARMISD_VTST_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VTST_v4i16(const SDValue &N) {
+SDNode *Select_ARMISD_VTST_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_44(N, ARM::VTSTv4i16, MVT::v4i16);
return Result;
@@ -6440,10 +6283,10 @@ SDNode *Select_ARMISD_VTST_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VTST_v8i16(const SDValue &N) {
+SDNode *Select_ARMISD_VTST_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_44(N, ARM::VTSTv8i16, MVT::v8i16);
return Result;
@@ -6454,10 +6297,10 @@ SDNode *Select_ARMISD_VTST_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VTST_v2i32(const SDValue &N) {
+SDNode *Select_ARMISD_VTST_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_44(N, ARM::VTSTv2i32, MVT::v2i32);
return Result;
@@ -6468,10 +6311,10 @@ SDNode *Select_ARMISD_VTST_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_VTST_v4i32(const SDValue &N) {
+SDNode *Select_ARMISD_VTST_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_44(N, ARM::VTSTv4i32, MVT::v4i32);
return Result;
@@ -6482,14 +6325,14 @@ SDNode *Select_ARMISD_VTST_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_Wrapper_i32(const SDValue &N) {
+SDNode *Select_ARMISD_Wrapper_i32(SDNode *N) {
// Pattern: (ARMWrapper:i32 (tglobaladdr:i32):$dst)
// Emits: (t2LEApcrel:i32 (tglobaladdr:i32):$dst)
// Pattern complexity = 6 cost = 1 size = 0
if ((Subtarget->isThumb2()) && (!Subtarget->useMovt())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
SDNode *Result = Emit_31(N, ARM::t2LEApcrel, MVT::i32);
return Result;
}
@@ -6499,8 +6342,8 @@ SDNode *Select_ARMISD_Wrapper_i32(const SDValue &N) {
// Emits: (t2LEApcrel:i32 (tconstpool:i32):$dst)
// Pattern complexity = 6 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::TargetConstantPool) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
SDNode *Result = Emit_31(N, ARM::t2LEApcrel, MVT::i32);
return Result;
}
@@ -6510,8 +6353,8 @@ SDNode *Select_ARMISD_Wrapper_i32(const SDValue &N) {
// Emits: (t2MOVi32imm:i32 (tglobaladdr:i32):$dst)
// Pattern complexity = 6 cost = 1 size = 0
if ((Subtarget->isThumb2()) && (Subtarget->useMovt())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
SDNode *Result = Emit_31(N, ARM::t2MOVi32imm, MVT::i32);
return Result;
}
@@ -6521,8 +6364,8 @@ SDNode *Select_ARMISD_Wrapper_i32(const SDValue &N) {
// Emits: (LEApcrel:i32 (tglobaladdr:i32):$dst)
// Pattern complexity = 6 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (!Subtarget->useMovt())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
SDNode *Result = Emit_31(N, ARM::LEApcrel, MVT::i32);
return Result;
}
@@ -6532,8 +6375,8 @@ SDNode *Select_ARMISD_Wrapper_i32(const SDValue &N) {
// Emits: (LEApcrel:i32 (tconstpool:i32):$dst)
// Pattern complexity = 6 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::TargetConstantPool) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
SDNode *Result = Emit_31(N, ARM::LEApcrel, MVT::i32);
return Result;
}
@@ -6543,19 +6386,19 @@ SDNode *Select_ARMISD_Wrapper_i32(const SDValue &N) {
// Emits: (MOVi32imm:i32 (tglobaladdr:i32):$dst)
// Pattern complexity = 6 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->useMovt())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
SDNode *Result = Emit_31(N, ARM::MOVi32imm, MVT::i32);
return Result;
}
}
if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (ARMWrapper:i32 (tglobaladdr:i32):$dst)
// Emits: (tLEApcrel:i32 (tglobaladdr:i32):$dst)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::TargetGlobalAddress) {
+ if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
SDNode *Result = Emit_31(N, ARM::tLEApcrel, MVT::i32);
return Result;
}
@@ -6563,7 +6406,7 @@ SDNode *Select_ARMISD_Wrapper_i32(const SDValue &N) {
// Pattern: (ARMWrapper:i32 (tconstpool:i32):$dst)
// Emits: (tLEApcrel:i32 (tconstpool:i32):$dst)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::TargetConstantPool) {
+ if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
SDNode *Result = Emit_31(N, ARM::tLEApcrel, MVT::i32);
return Result;
}
@@ -6573,16 +6416,16 @@ SDNode *Select_ARMISD_Wrapper_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_WrapperJT_i32(const SDValue &N) {
+SDNode *Select_ARMISD_WrapperJT_i32(SDNode *N) {
// Pattern: (ARMWrapperJT:i32 (tjumptable:i32):$dst, (imm:i32):$id)
// Emits: (t2LEApcrelJT:i32 (tjumptable:i32):$dst, (imm:i32):$id)
// Pattern complexity = 9 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::TargetJumpTable) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::t2LEApcrelJT, MVT::i32);
return Result;
}
@@ -6593,10 +6436,10 @@ SDNode *Select_ARMISD_WrapperJT_i32(const SDValue &N) {
// Emits: (LEApcrelJT:i32 (tjumptable:i32):$dst, (imm:i32):$id)
// Pattern complexity = 9 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::TargetJumpTable) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::LEApcrelJT, MVT::i32);
return Result;
}
@@ -6607,10 +6450,10 @@ SDNode *Select_ARMISD_WrapperJT_i32(const SDValue &N) {
// Emits: (tLEApcrelJT:i32 (tjumptable:i32):$dst, (imm:i32):$id)
// Pattern complexity = 9 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::TargetJumpTable) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_35(N, ARM::tLEApcrelJT, MVT::i32);
return Result;
}
@@ -6621,52 +6464,48 @@ SDNode *Select_ARMISD_WrapperJT_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ARMISD_tCALL(const SDValue &N) {
+SDNode *Select_ARMISD_tCALL(SDNode *N) {
// Pattern: (ARMtcall:isVoid (tglobaladdr:iPTR):$func)
// Emits: (tBL:isVoid (tglobaladdr:i32):$func)
// Pattern complexity = 6 cost = 1 size = 0
if ((Subtarget->isThumb()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
SDNode *Result = Emit_4(N, ARM::tBL, 1);
return Result;
}
}
-
- // Pattern: (ARMtcall:isVoid (tglobaladdr:iPTR):$func)
- // Emits: (tBLr9:isVoid (tglobaladdr:i32):$func)
- // Pattern complexity = 6 cost = 1 size = 0
if ((Subtarget->isThumb()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+
+ // Pattern: (ARMtcall:isVoid (tglobaladdr:iPTR):$func)
+ // Emits: (tBLr9:isVoid (tglobaladdr:i32):$func)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
SDNode *Result = Emit_4(N, ARM::tBLr9, 1);
return Result;
}
- }
- // Pattern: (ARMtcall:isVoid (texternalsym:iPTR):$func)
- // Emits: (tBL:isVoid (texternalsym:i32):$func)
- // Pattern complexity = 6 cost = 1 size = 0
- if ((Subtarget->isThumb()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetExternalSymbol) {
- SDNode *Result = Emit_4(N, ARM::tBL, 1);
+ // Pattern: (ARMtcall:isVoid (texternalsym:iPTR):$func)
+ // Emits: (tBLr9:isVoid (texternalsym:i32):$func)
+ // Pattern complexity = 6 cost = 1 size = 0
+ if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
+ SDNode *Result = Emit_4(N, ARM::tBLr9, 1);
return Result;
}
}
// Pattern: (ARMtcall:isVoid (texternalsym:iPTR):$func)
- // Emits: (tBLr9:isVoid (texternalsym:i32):$func)
+ // Emits: (tBL:isVoid (texternalsym:i32):$func)
// Pattern complexity = 6 cost = 1 size = 0
- if ((Subtarget->isThumb()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetExternalSymbol) {
- SDNode *Result = Emit_4(N, ARM::tBLr9, 1);
+ if ((Subtarget->isThumb()) && (!Subtarget->isTargetDarwin())) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
+ SDNode *Result = Emit_4(N, ARM::tBL, 1);
return Result;
}
}
@@ -6675,8 +6514,8 @@ SDNode *Select_ARMISD_tCALL(const SDValue &N) {
// Emits: (tBLXr:isVoid GPR:i32:$func)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (!Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_4(N, ARM::tBLXr, 1);
return Result;
@@ -6687,8 +6526,8 @@ SDNode *Select_ARMISD_tCALL(const SDValue &N) {
// Emits: (tBLXr_r9:isVoid GPR:i32:$func)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb()) && (Subtarget->hasV5TOps()) && (Subtarget->isTargetDarwin())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_4(N, ARM::tBLXr_r9, 1);
return Result;
@@ -6699,1019 +6538,1019 @@ SDNode *Select_ARMISD_tCALL(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_51(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_51(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, N10, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_52(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_52(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, N100, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_53(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_53(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, N10, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_54(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_54(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, N100, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_55(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_55(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_56(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_56(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, N1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_57(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_57(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 7);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 7);
}
-DISABLE_INLINE SDNode *Emit_58(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_58(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N01, N1, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
}
-DISABLE_INLINE SDNode *Emit_59(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_59(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N01, N1, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_60(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_60(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N100, N110, N0, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_61(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_61(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N100, N110, N0, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_62(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_62(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N100, N110, N0, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_63(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_63(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N100, N1010, N0, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_64(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_64(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N100, N1010, N0, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_65(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_65(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { Tmp0, N0, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_66(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_66(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { Tmp0, N0, N1, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_67(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_67(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp3 = Transform_imm_neg_XFORM(Tmp2.getNode());
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { Tmp0, N0, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_68(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_68(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
}
-DISABLE_INLINE SDNode *Emit_69(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_69(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_imm_neg_XFORM(Tmp1.getNode());
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_70(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_70(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_t2_so_imm_neg_XFORM(Tmp1.getNode());
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_71(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_71(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_t2_so_imm2part_1(Tmp1.getNode());
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, Ops0, 5), 0);
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, Ops0, 5), 0);
SDValue Tmp7 = Transform_t2_so_imm2part_2(Tmp1.getNode());
SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { Tmp6, Tmp7, Tmp8, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
}
-DISABLE_INLINE SDNode *Emit_72(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_72(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_t2_so_neg_imm2part_1(Tmp1.getNode());
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, Ops0, 5), 0);
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, Ops0, 5), 0);
SDValue Tmp7 = Transform_t2_so_neg_imm2part_2(Tmp1.getNode());
SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { Tmp6, Tmp7, Tmp8, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
}
-DISABLE_INLINE SDNode *Emit_73(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_73(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_so_imm_neg_XFORM(Tmp1.getNode());
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_74(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_74(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_so_imm2part_1(Tmp1.getNode());
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, Ops0, 5), 0);
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, Ops0, 5), 0);
SDValue Tmp7 = Transform_so_imm2part_2(Tmp1.getNode());
SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { Tmp6, Tmp7, Tmp8, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
}
-DISABLE_INLINE SDNode *Emit_75(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_75(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_so_neg_imm2part_1(Tmp1.getNode());
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, Ops0, 5), 0);
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, Ops0, 5), 0);
SDValue Tmp7 = Transform_so_neg_imm2part_2(Tmp1.getNode());
SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { Tmp6, Tmp7, Tmp8, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
-}
-DISABLE_INLINE SDNode *Emit_76(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N1000 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- SDValue N111 = N11.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
+}
+DISABLE_INLINE SDNode *Emit_76(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue Tmp11 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp12 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1000, N1100, N0, Tmp11, Tmp12 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_77(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_77(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N10, N11, N0, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_78(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N1000 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_78(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1000, N110, N0, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_79(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_79(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N10, N110, N0, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_80(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- SDValue N111 = N11.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_80(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N100, N1100, N0, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_81(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_81(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N100, N11, N0, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_82(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N1010 = N101.getOperand(0);
- SDValue N10100 = N1010.getOperand(0);
- SDValue N10101 = N1010.getOperand(1);
- SDValue N1011 = N101.getOperand(1);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_82(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N10100 = N1010.getNode()->getOperand(0);
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N100, N10100, N0, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_83(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_83(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N100, N101, N0, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_84(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_84(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, N00, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_85(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_85(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N001)->getZExtValue()), MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, N000, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_86(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_86(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, N00, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_87(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_87(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N001)->getZExtValue()), MVT::i32);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, N000, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_88(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_88(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 7);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 7);
}
-DISABLE_INLINE SDNode *Emit_89(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_89(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N10, N11, N0, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_90(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_90(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N000, N010, N1, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_91(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_91(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N110, N100, N0, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_92(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_92(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N000, N010, N1, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_93(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_93(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N010, N000, N1, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_94(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_94(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N110, N100, N0, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_95(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_95(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N000, N010, N1, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_96(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_96(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N010, N000, N1, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_97(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N1000 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_97(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N101, N1000, N0, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_98(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_98(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N000, N0010, N1, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_99(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_99(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N001, N0000, N1, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_100(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N1000 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_100(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N101, N1000, N0, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_101(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_101(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N000, N0010, N1, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_102(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_102(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N001, N0000, N1, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_103(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_103(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_104(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N1000 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- SDValue N111 = N11.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_104(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue Tmp11 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp12 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1100, N1000, N0, Tmp11, Tmp12 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_105(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_105(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp11 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp12 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0000, N0100, N1, Tmp11, Tmp12 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_106(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_106(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp11 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp12 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0100, N0000, N1, Tmp11, Tmp12 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_107(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- SDValue N111 = N11.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_107(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1100, N100, N0, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_108(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_108(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0000, N010, N1, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_109(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_109(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0100, N000, N1, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_110(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_110(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N11, N100, N0, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_111(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_111(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N010, N1, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_112(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_112(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N01, N000, N1, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_113(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N1000 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_113(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N110, N1000, N0, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_114(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_114(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N000, N0100, N1, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_115(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_115(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N010, N0000, N1, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_116(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_116(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N110, N10, N0, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_117(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_117(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N000, N01, N1, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_118(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_118(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N010, N00, N1, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_119(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N1000 = N100.getOperand(0);
- SDValue N10000 = N1000.getOperand(0);
- SDValue N10001 = N1000.getOperand(1);
- SDValue N1001 = N100.getOperand(1);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_119(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N10000 = N1000.getNode()->getOperand(0);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N101, N10000, N0, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_120(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N0010 = N001.getOperand(0);
- SDValue N00100 = N0010.getOperand(0);
- SDValue N00101 = N0010.getOperand(1);
- SDValue N0011 = N001.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_120(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N00100 = N0010.getNode()->getOperand(0);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N000, N00100, N1, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_121(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N0000 = N000.getOperand(0);
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- SDValue N0001 = N000.getOperand(1);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_121(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp9 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp10 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N001, N00000, N1, Tmp9, Tmp10 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_122(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_122(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N101, N100, N0, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_123(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_123(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N000, N001, N1, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_124(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_124(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N001, N000, N1, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-SDNode *Select_ISD_ADD_i32(const SDValue &N) {
+SDNode *Select_ISD_ADD_i32(SDNode *N) {
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1001);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(16)) {
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp6) {
int64_t CN7 = Tmp6->getSExtValue();
if (CN7 == INT64_C(16) &&
@@ -7747,38 +7586,38 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::SHL) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N001);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(16)) {
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp6) {
int64_t CN7 = Tmp6->getSExtValue();
if (CN7 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N0001.getValueType() == MVT::i32 &&
N001.getValueType() == MVT::i32 &&
N0101.getValueType() == MVT::i32 &&
@@ -7813,22 +7652,22 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
// Pattern: (add:i32 GPR:i32:$LHS, (and:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 255:i32))
// Emits: (UXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
// Pattern complexity = 34 cost = 1 size = 0
if (CheckAndMask(N10, Tmp0, INT64_C(255)) &&
- N10.getOpcode() == ISD::ROTR) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant &&
+ N10.getNode()->getOpcode() == ISD::ROTR) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant &&
Predicate_rot_imm(N101.getNode()) &&
N101.getValueType() == MVT::i32) {
SDNode *Result = Emit_54(N, ARM::UXTABrr_rot, MVT::i32);
@@ -7840,10 +7679,10 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (UXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
// Pattern complexity = 34 cost = 1 size = 0
if (CheckAndMask(N10, Tmp0, INT64_C(65535)) &&
- N10.getOpcode() == ISD::ROTR) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant &&
+ N10.getNode()->getOpcode() == ISD::ROTR) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant &&
Predicate_rot_imm(N101.getNode()) &&
N101.getValueType() == MVT::i32) {
SDNode *Result = Emit_54(N, ARM::UXTAHrr_rot, MVT::i32);
@@ -7854,22 +7693,22 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
// Pattern: (add:i32 GPR:i32:$LHS, (and:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 255:i32))
// Emits: (t2UXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
// Pattern complexity = 34 cost = 1 size = 0
if (CheckAndMask(N10, Tmp0, INT64_C(255)) &&
- N10.getOpcode() == ISD::ROTR) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant &&
+ N10.getNode()->getOpcode() == ISD::ROTR) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant &&
Predicate_rot_imm(N101.getNode()) &&
N101.getValueType() == MVT::i32) {
SDNode *Result = Emit_54(N, ARM::t2UXTABrr_rot, MVT::i32);
@@ -7881,10 +7720,10 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (t2UXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
// Pattern complexity = 34 cost = 1 size = 0
if (CheckAndMask(N10, Tmp0, INT64_C(65535)) &&
- N10.getOpcode() == ISD::ROTR) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant &&
+ N10.getNode()->getOpcode() == ISD::ROTR) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant &&
Predicate_rot_imm(N101.getNode()) &&
N101.getValueType() == MVT::i32) {
SDNode *Result = Emit_54(N, ARM::t2UXTAHrr_rot, MVT::i32);
@@ -7895,23 +7734,23 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
// Pattern: (add:i32 (and:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 255:i32), GPR:i32:$LHS)
// Emits: (UXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
// Pattern complexity = 34 cost = 1 size = 0
if (CheckAndMask(N00, Tmp0, INT64_C(255)) &&
- N00.getOpcode() == ISD::ROTR) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant &&
+ N00.getNode()->getOpcode() == ISD::ROTR) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant &&
Predicate_rot_imm(N001.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N001.getValueType() == MVT::i32) {
SDNode *Result = Emit_87(N, ARM::UXTABrr_rot, MVT::i32);
return Result;
@@ -7923,12 +7762,12 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (UXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
// Pattern complexity = 34 cost = 1 size = 0
if (CheckAndMask(N00, Tmp0, INT64_C(65535)) &&
- N00.getOpcode() == ISD::ROTR) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant &&
+ N00.getNode()->getOpcode() == ISD::ROTR) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant &&
Predicate_rot_imm(N001.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N001.getValueType() == MVT::i32) {
SDNode *Result = Emit_87(N, ARM::UXTAHrr_rot, MVT::i32);
return Result;
@@ -7939,23 +7778,23 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
// Pattern: (add:i32 (and:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 255:i32), GPR:i32:$LHS)
// Emits: (t2UXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
// Pattern complexity = 34 cost = 1 size = 0
if (CheckAndMask(N00, Tmp0, INT64_C(255)) &&
- N00.getOpcode() == ISD::ROTR) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant &&
+ N00.getNode()->getOpcode() == ISD::ROTR) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant &&
Predicate_rot_imm(N001.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N001.getValueType() == MVT::i32) {
SDNode *Result = Emit_87(N, ARM::t2UXTABrr_rot, MVT::i32);
return Result;
@@ -7967,12 +7806,12 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (t2UXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
// Pattern complexity = 34 cost = 1 size = 0
if (CheckAndMask(N00, Tmp0, INT64_C(65535)) &&
- N00.getOpcode() == ISD::ROTR) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant &&
+ N00.getNode()->getOpcode() == ISD::ROTR) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant &&
Predicate_rot_imm(N001.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N001.getValueType() == MVT::i32) {
SDNode *Result = Emit_87(N, ARM::t2UXTAHrr_rot, MVT::i32);
return Result;
@@ -7983,34 +7822,34 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getNode()->getOperand(0);
// Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32), (sra:i32 GPR:i32:$b, 16:i32)))
// Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 30 cost = 1 size = 0
- if (N100.getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1001);
+ if (N100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(16) &&
@@ -8031,23 +7870,23 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32)))
// Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 30 cost = 1 size = 0
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(16) &&
@@ -8070,27 +7909,27 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32)), 16:i32))
// Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 30 cost = 1 size = 0
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::SRA) {
- SDValue N1010 = N101.getOperand(0);
- if (N1010.getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getOperand(0);
- SDValue N10101 = N1010.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10101);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ if (N1010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10101.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1011 = N101.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1011);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1011.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(16) &&
@@ -8113,27 +7952,27 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32)))
// Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 30 cost = 1 size = 0
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(16) &&
@@ -8153,35 +7992,35 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getNode()->getOperand(0);
// Pattern: (add:i32 (mul:i32 (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32), (sra:i32 GPR:i32:$b, 16:i32)), GPR:i32:$acc)
// Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 30 cost = 1 size = 0
- if (N000.getOpcode() == ISD::SHL) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (N000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N001);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N0001.getValueType() == MVT::i32 &&
N001.getValueType() == MVT::i32 &&
N011.getValueType() == MVT::i32) {
@@ -8200,27 +8039,27 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32)), GPR:i32:$acc)
// Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 30 cost = 1 size = 0
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N001.getValueType() == MVT::i32 &&
N0101.getValueType() == MVT::i32 &&
N011.getValueType() == MVT::i32) {
@@ -8242,28 +8081,28 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 30 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1001);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(16) &&
@@ -8283,36 +8122,36 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getNode()->getOperand(0);
// Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32)), GPR:i32:$acc)
// Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 30 cost = 1 size = 0
{
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N001.getValueType() == MVT::i32 &&
N0101.getValueType() == MVT::i32 &&
N011.getValueType() == MVT::i32) {
@@ -8332,27 +8171,27 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), (sra:i32 GPR:i32:$a, 16:i32)), GPR:i32:$acc)
// Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 30 cost = 1 size = 0
- if (N000.getOpcode() == ISD::SHL) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (N000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N001);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N0001.getValueType() == MVT::i32 &&
N001.getValueType() == MVT::i32 &&
N011.getValueType() == MVT::i32) {
@@ -8374,28 +8213,28 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 30 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::SRA) {
- SDValue N1000 = N100.getOperand(0);
- if (N1000.getOpcode() == ISD::SHL) {
- SDValue N10000 = N1000.getOperand(0);
- SDValue N10001 = N1000.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10001);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10000 = N1000.getNode()->getOperand(0);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1001);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(16) &&
@@ -8415,36 +8254,36 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::MUL) {
- SDValue N000 = N00.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
// Pattern: (add:i32 (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32)), 16:i32), GPR:i32:$acc)
// Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 30 cost = 1 size = 0
{
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::SRA) {
- SDValue N0010 = N001.getOperand(0);
- if (N0010.getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getOperand(0);
- SDValue N00101 = N0010.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00101);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ if (N0010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getNode()->getOperand(0);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00101.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N00101.getValueType() == MVT::i32 &&
N0011.getValueType() == MVT::i32 &&
N01.getValueType() == MVT::i32) {
@@ -8464,27 +8303,27 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (sra:i32 (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), GPR:i32:$a), 16:i32), GPR:i32:$acc)
// Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 30 cost = 1 size = 0
- if (N000.getOpcode() == ISD::SRA) {
- SDValue N0000 = N000.getOperand(0);
- if (N0000.getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00001);
+ if (N000.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ if (N0000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0001);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N00001.getValueType() == MVT::i32 &&
N0001.getValueType() == MVT::i32 &&
N01.getValueType() == MVT::i32) {
@@ -8503,12 +8342,12 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
// Pattern: (add:i32 GPR:i32:$LHS, (and:i32 GPR:i32:$RHS, 255:i32))
@@ -8530,12 +8369,12 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
// Pattern: (add:i32 GPR:i32:$LHS, (and:i32 GPR:i32:$RHS, 255:i32))
@@ -8557,11 +8396,11 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
// Pattern: (add:i32 (and:i32 GPR:i32:$RHS, 255:i32), GPR:i32:$LHS)
@@ -8583,11 +8422,11 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
// Pattern: (add:i32 (and:i32 GPR:i32:$RHS, 255:i32), GPR:i32:$LHS)
@@ -8609,26 +8448,26 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 GPR:i32:$b, 16:i32)))
// Emits: (SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 22 cost = 1 size = 0
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16) &&
@@ -8647,20 +8486,20 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 GPR:i32:$b, 16:i32)), 16:i32))
// Emits: (SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 22 cost = 1 size = 0
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::SRA) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1011);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1011.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16) &&
@@ -8677,26 +8516,26 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 GPR:i32:$b, 16:i32)))
// Emits: (t2SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 22 cost = 1 size = 0
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16) &&
@@ -8715,20 +8554,20 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 GPR:i32:$b, 16:i32)), 16:i32))
// Emits: (t2SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 22 cost = 1 size = 0
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::SRA) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1011);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1011.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16) &&
@@ -8745,27 +8584,27 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 GPR:i32:$a, 16:i32)))
// Emits: (SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 22 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16) &&
@@ -8781,24 +8620,24 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N001.getValueType() == MVT::i32 &&
N011.getValueType() == MVT::i32) {
@@ -8828,21 +8667,21 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 22 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::SRA) {
- SDValue N1000 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1001);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16) &&
@@ -8858,29 +8697,29 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::MUL) {
- SDValue N000 = N00.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
// Pattern: (add:i32 (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 GPR:i32:$b, 16:i32)), 16:i32), GPR:i32:$acc)
// Emits: (SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 22 cost = 1 size = 0
{
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::SRA) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N0011.getValueType() == MVT::i32 &&
N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_101(N, ARM::SMLAWT, MVT::i32);
@@ -8896,20 +8735,20 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (sra:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32:$a), 16:i32), GPR:i32:$acc)
// Emits: (SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 22 cost = 1 size = 0
- if (N000.getOpcode() == ISD::SRA) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (N000.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N0001.getValueType() == MVT::i32 &&
N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_102(N, ARM::SMLAWT, MVT::i32);
@@ -8924,27 +8763,27 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sra:i32 GPR:i32:$a, 16:i32)))
// Emits: (t2SMLATT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 22 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16) &&
@@ -8960,24 +8799,24 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N001.getValueType() == MVT::i32 &&
N011.getValueType() == MVT::i32) {
@@ -9007,21 +8846,21 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (t2SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 22 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::SRA) {
- SDValue N1000 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1001);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16) &&
@@ -9037,29 +8876,29 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::MUL) {
- SDValue N000 = N00.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
// Pattern: (add:i32 (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 GPR:i32:$b, 16:i32)), 16:i32), GPR:i32:$acc)
// Emits: (t2SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 22 cost = 1 size = 0
{
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::SRA) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N0011.getValueType() == MVT::i32 &&
N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_101(N, ARM::t2SMLAWT, MVT::i32);
@@ -9075,20 +8914,20 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (sra:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32:$a), 16:i32), GPR:i32:$acc)
// Emits: (t2SMLAWT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 22 cost = 1 size = 0
- if (N000.getOpcode() == ISD::SRA) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (N000.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N0001.getValueType() == MVT::i32 &&
N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_102(N, ARM::t2SMLAWT, MVT::i32);
@@ -9103,23 +8942,23 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sra:i32 GPR:i32:$b, 16:i32)))
// Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
- if (N10.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (cast<VTSDNode>(N101)->getVT() == MVT::i16) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ if (N10.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N101.getNode())->getVT() == MVT::i16) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -9135,18 +8974,18 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sext_inreg:i32 GPR:i32:$b, i16:Other)))
// Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
- if (N10.getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ if (N10.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (cast<VTSDNode>(N111)->getVT() == MVT::i16 &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N111.getNode())->getVT() == MVT::i16 &&
N101.getValueType() == MVT::i32) {
SDNode *Result = Emit_61(N, ARM::SMLATB, MVT::i32);
return Result;
@@ -9160,17 +8999,17 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 GPR:i32:$a, (sext_inreg:i32 GPR:i32:$b, i16:Other)), 16:i32))
// Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- if (cast<VTSDNode>(N1011)->getVT() == MVT::i16) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N1011.getNode())->getVT() == MVT::i16) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -9185,23 +9024,23 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sra:i32 GPR:i32:$b, 16:i32)))
// Emits: (t2SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
- if (N10.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (cast<VTSDNode>(N101)->getVT() == MVT::i16) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ if (N10.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N101.getNode())->getVT() == MVT::i16) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -9217,18 +9056,18 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sext_inreg:i32 GPR:i32:$b, i16:Other)))
// Emits: (t2SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
- if (N10.getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ if (N10.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (cast<VTSDNode>(N111)->getVT() == MVT::i16 &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N111.getNode())->getVT() == MVT::i16 &&
N101.getValueType() == MVT::i32) {
SDNode *Result = Emit_61(N, ARM::t2SMLATB, MVT::i32);
return Result;
@@ -9242,17 +9081,17 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 GPR:i32:$a, (sext_inreg:i32 GPR:i32:$b, i16:Other)), 16:i32))
// Emits: (t2SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- if (cast<VTSDNode>(N1011)->getVT() == MVT::i16) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N1011.getNode())->getVT() == MVT::i16) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -9267,27 +9106,27 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sext_inreg:i32 GPR:i32:$a, i16:Other)))
// Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (cast<VTSDNode>(N111)->getVT() == MVT::i16 &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N111.getNode())->getVT() == MVT::i16 &&
N101.getValueType() == MVT::i32) {
SDNode *Result = Emit_91(N, ARM::SMLABT, MVT::i32);
return Result;
@@ -9298,25 +9137,25 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (add:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sra:i32 GPR:i32:$b, 16:i32)), GPR:i32:$acc)
// Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
- if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011);
+ if (N00.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N001.getNode())->getVT() == MVT::i16) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N011.getValueType() == MVT::i32) {
SDNode *Result = Emit_92(N, ARM::SMLABT, MVT::i32);
return Result;
@@ -9330,19 +9169,19 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sext_inreg:i32 GPR:i32:$a, i16:Other)), GPR:i32:$acc)
// Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
- if (N00.getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (N00.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- if (cast<VTSDNode>(N011)->getVT() == MVT::i16) {
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N011.getNode())->getVT() == MVT::i16) {
+ SDValue N1 = N->getOperand(1);
if (N001.getValueType() == MVT::i32) {
SDNode *Result = Emit_93(N, ARM::SMLABT, MVT::i32);
return Result;
@@ -9358,18 +9197,18 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (cast<VTSDNode>(N101)->getVT() == MVT::i16) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N101.getNode())->getVT() == MVT::i16) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -9383,25 +9222,25 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sext_inreg:i32 GPR:i32:$b, i16:Other)), GPR:i32:$acc)
// Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
- if (N00.getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (N00.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- if (cast<VTSDNode>(N011)->getVT() == MVT::i16) {
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N011.getNode())->getVT() == MVT::i16) {
+ SDValue N1 = N->getOperand(1);
if (N001.getValueType() == MVT::i32) {
SDNode *Result = Emit_92(N, ARM::SMLATB, MVT::i32);
return Result;
@@ -9415,19 +9254,19 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), (sra:i32 GPR:i32:$a, 16:i32)), GPR:i32:$acc)
// Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
- if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011);
+ if (N00.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N001.getNode())->getVT() == MVT::i16) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N011.getValueType() == MVT::i32) {
SDNode *Result = Emit_93(N, ARM::SMLATB, MVT::i32);
return Result;
@@ -9443,18 +9282,18 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N1000 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- if (cast<VTSDNode>(N1001)->getVT() == MVT::i16) {
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N1001.getNode())->getVT() == MVT::i16) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -9468,26 +9307,26 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::MUL) {
- SDValue N000 = N00.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
// Pattern: (add:i32 (sra:i32 (mul:i32 GPR:i32:$a, (sext_inreg:i32 GPR:i32:$b, i16:Other)), 16:i32), GPR:i32:$acc)
// Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
{
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- if (cast<VTSDNode>(N0011)->getVT() == MVT::i16) {
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N0011.getNode())->getVT() == MVT::i16) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_98(N, ARM::SMLAWB, MVT::i32);
return Result;
@@ -9501,17 +9340,17 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (sra:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), GPR:i32:$a), 16:i32), GPR:i32:$acc)
// Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
- if (N000.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- if (cast<VTSDNode>(N0001)->getVT() == MVT::i16) {
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N000.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N0001.getNode())->getVT() == MVT::i16) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_99(N, ARM::SMLAWB, MVT::i32);
return Result;
@@ -9524,27 +9363,27 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sext_inreg:i32 GPR:i32:$a, i16:Other)))
// Emits: (t2SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (cast<VTSDNode>(N111)->getVT() == MVT::i16 &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N111.getNode())->getVT() == MVT::i16 &&
N101.getValueType() == MVT::i32) {
SDNode *Result = Emit_91(N, ARM::t2SMLABT, MVT::i32);
return Result;
@@ -9555,25 +9394,25 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (add:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sra:i32 GPR:i32:$b, 16:i32)), GPR:i32:$acc)
// Emits: (t2SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
- if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011);
+ if (N00.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N001.getNode())->getVT() == MVT::i16) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N011.getValueType() == MVT::i32) {
SDNode *Result = Emit_92(N, ARM::t2SMLABT, MVT::i32);
return Result;
@@ -9587,19 +9426,19 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sext_inreg:i32 GPR:i32:$a, i16:Other)), GPR:i32:$acc)
// Emits: (t2SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
- if (N00.getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (N00.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- if (cast<VTSDNode>(N011)->getVT() == MVT::i16) {
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N011.getNode())->getVT() == MVT::i16) {
+ SDValue N1 = N->getOperand(1);
if (N001.getValueType() == MVT::i32) {
SDNode *Result = Emit_93(N, ARM::t2SMLABT, MVT::i32);
return Result;
@@ -9615,18 +9454,18 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (t2SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (cast<VTSDNode>(N101)->getVT() == MVT::i16) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N101.getNode())->getVT() == MVT::i16) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -9640,25 +9479,25 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sext_inreg:i32 GPR:i32:$b, i16:Other)), GPR:i32:$acc)
// Emits: (t2SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
- if (N00.getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (N00.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- if (cast<VTSDNode>(N011)->getVT() == MVT::i16) {
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N011.getNode())->getVT() == MVT::i16) {
+ SDValue N1 = N->getOperand(1);
if (N001.getValueType() == MVT::i32) {
SDNode *Result = Emit_92(N, ARM::t2SMLATB, MVT::i32);
return Result;
@@ -9672,19 +9511,19 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), (sra:i32 GPR:i32:$a, 16:i32)), GPR:i32:$acc)
// Emits: (t2SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
- if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011);
+ if (N00.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N001.getNode())->getVT() == MVT::i16) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N011.getValueType() == MVT::i32) {
SDNode *Result = Emit_93(N, ARM::t2SMLATB, MVT::i32);
return Result;
@@ -9700,18 +9539,18 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (t2SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N1000 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- if (cast<VTSDNode>(N1001)->getVT() == MVT::i16) {
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N1001.getNode())->getVT() == MVT::i16) {
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -9725,26 +9564,26 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::MUL) {
- SDValue N000 = N00.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
// Pattern: (add:i32 (sra:i32 (mul:i32 GPR:i32:$a, (sext_inreg:i32 GPR:i32:$b, i16:Other)), 16:i32), GPR:i32:$acc)
// Emits: (t2SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
{
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- if (cast<VTSDNode>(N0011)->getVT() == MVT::i16) {
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N0011.getNode())->getVT() == MVT::i16) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_98(N, ARM::t2SMLAWB, MVT::i32);
return Result;
@@ -9758,17 +9597,17 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (sra:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), GPR:i32:$a), 16:i32), GPR:i32:$acc)
// Emits: (t2SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 17 cost = 1 size = 0
- if (N000.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- if (cast<VTSDNode>(N0001)->getVT() == MVT::i16) {
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N000.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N0001.getNode())->getVT() == MVT::i16) {
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_99(N, ARM::t2SMLAWB, MVT::i32);
return Result;
@@ -9785,8 +9624,8 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (ADDrs:i32 GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 15 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -9796,20 +9635,20 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (add:i32 GPR:i32:$acc, (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$a, (sra:i32 GPR:i32:$b, 16:i32)))
// Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 15 cost = 1 size = 0
if (Predicate_sext_16_node(N10.getNode())) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -9824,14 +9663,14 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), GPR:i32<<P:Predicate_sext_16_node>>:$b))
// Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 15 cost = 1 size = 0
- if (N10.getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ if (N10.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (Predicate_sext_16_node(N11.getNode()) &&
N101.getValueType() == MVT::i32) {
SDNode *Result = Emit_81(N, ARM::SMLATB, MVT::i32);
@@ -9845,14 +9684,14 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPR:i32:$acc, (sra:i32 (mul:i32 GPR:i32:$a, GPR:i32<<P:Predicate_sext_16_node>>:$b), 16:i32))
// Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 15 cost = 1 size = 0
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
if (Predicate_sext_16_node(N101.getNode())) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -9870,7 +9709,7 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (ADDrs:i32 GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 15 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
SDValue CPTmpN0_0;
SDValue CPTmpN0_1;
SDValue CPTmpN0_2;
@@ -9880,23 +9719,23 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32<<P:Predicate_sext_16_node>>:$a))
// Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 15 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (Predicate_sext_16_node(N11.getNode()) &&
N101.getValueType() == MVT::i32) {
SDNode *Result = Emit_110(N, ARM::SMLABT, MVT::i32);
@@ -9907,22 +9746,22 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (add:i32 (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$a, (sra:i32 GPR:i32:$b, 16:i32)), GPR:i32:$acc)
// Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 15 cost = 1 size = 0
if (Predicate_sext_16_node(N00.getNode())) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N011.getValueType() == MVT::i32) {
SDNode *Result = Emit_111(N, ARM::SMLABT, MVT::i32);
return Result;
@@ -9935,16 +9774,16 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), GPR:i32<<P:Predicate_sext_16_node>>:$a), GPR:i32:$acc)
// Emits: (SMLABT:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 15 cost = 1 size = 0
- if (N00.getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (N00.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
if (Predicate_sext_16_node(N01.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N001.getValueType() == MVT::i32) {
SDNode *Result = Emit_112(N, ARM::SMLABT, MVT::i32);
return Result;
@@ -9959,15 +9798,15 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 15 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
if (Predicate_sext_16_node(N10.getNode())) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRA) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -9980,22 +9819,22 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (add:i32 (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), GPR:i32<<P:Predicate_sext_16_node>>:$b), GPR:i32:$acc)
// Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 15 cost = 1 size = 0
- if (N00.getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (N00.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
if (Predicate_sext_16_node(N01.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N001.getValueType() == MVT::i32) {
SDNode *Result = Emit_117(N, ARM::SMLATB, MVT::i32);
return Result;
@@ -10009,15 +9848,15 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (SMLATB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 15 cost = 1 size = 0
if (Predicate_sext_16_node(N00.getNode())) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N011.getValueType() == MVT::i32) {
SDNode *Result = Emit_118(N, ARM::SMLATB, MVT::i32);
return Result;
@@ -10032,15 +9871,15 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 15 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::MUL) {
- SDValue N100 = N10.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (Predicate_sext_16_node(N100.getNode())) {
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -10053,23 +9892,23 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::MUL) {
- SDValue N000 = N00.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
// Pattern: (add:i32 (sra:i32 (mul:i32 GPR:i32:$a, GPR:i32<<P:Predicate_sext_16_node>>:$b), 16:i32), GPR:i32:$acc)
// Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 15 cost = 1 size = 0
{
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
if (Predicate_sext_16_node(N001.getNode())) {
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_123(N, ARM::SMLAWB, MVT::i32);
return Result;
@@ -10083,13 +9922,13 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (SMLAWB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 15 cost = 1 size = 0
if (Predicate_sext_16_node(N000.getNode())) {
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_124(N, ARM::SMLAWB, MVT::i32);
return Result;
@@ -10101,21 +9940,21 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::ROTR) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::ROTR) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant &&
Predicate_rot_imm(N101.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
// Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i8:Other))
// Emits: (SXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
// Pattern complexity = 13 cost = 1 size = 0
- if (cast<VTSDNode>(N11)->getVT() == MVT::i8 &&
+ if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i8 &&
N101.getValueType() == MVT::i32) {
SDNode *Result = Emit_52(N, ARM::SXTABrr_rot, MVT::i32);
return Result;
@@ -10124,7 +9963,7 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i16:Other))
// Emits: (SXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
// Pattern complexity = 13 cost = 1 size = 0
- if (cast<VTSDNode>(N11)->getVT() == MVT::i16 &&
+ if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i16 &&
N101.getValueType() == MVT::i32) {
SDNode *Result = Emit_52(N, ARM::SXTAHrr_rot, MVT::i32);
return Result;
@@ -10134,21 +9973,21 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::ROTR) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::ROTR) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant &&
Predicate_rot_imm(N101.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
// Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i8:Other))
// Emits: (t2SXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
// Pattern complexity = 13 cost = 1 size = 0
- if (cast<VTSDNode>(N11)->getVT() == MVT::i8 &&
+ if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i8 &&
N101.getValueType() == MVT::i32) {
SDNode *Result = Emit_52(N, ARM::t2SXTABrr_rot, MVT::i32);
return Result;
@@ -10157,7 +9996,7 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i16:Other))
// Emits: (t2SXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
// Pattern complexity = 13 cost = 1 size = 0
- if (cast<VTSDNode>(N11)->getVT() == MVT::i16 &&
+ if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i16 &&
N101.getValueType() == MVT::i32) {
SDNode *Result = Emit_52(N, ARM::t2SXTAHrr_rot, MVT::i32);
return Result;
@@ -10167,21 +10006,21 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::ROTR) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::ROTR) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant &&
Predicate_rot_imm(N001.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
// Pattern: (add:i32 (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i8:Other), GPR:i32:$LHS)
// Emits: (SXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
// Pattern complexity = 13 cost = 1 size = 0
- if (cast<VTSDNode>(N01)->getVT() == MVT::i8) {
- SDValue N1 = N.getOperand(1);
+ if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i8) {
+ SDValue N1 = N->getOperand(1);
if (N001.getValueType() == MVT::i32) {
SDNode *Result = Emit_85(N, ARM::SXTABrr_rot, MVT::i32);
return Result;
@@ -10191,8 +10030,8 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i16:Other), GPR:i32:$LHS)
// Emits: (SXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
// Pattern complexity = 13 cost = 1 size = 0
- if (cast<VTSDNode>(N01)->getVT() == MVT::i16) {
- SDValue N1 = N.getOperand(1);
+ if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i16) {
+ SDValue N1 = N->getOperand(1);
if (N001.getValueType() == MVT::i32) {
SDNode *Result = Emit_85(N, ARM::SXTAHrr_rot, MVT::i32);
return Result;
@@ -10203,21 +10042,21 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::ROTR) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::ROTR) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant &&
Predicate_rot_imm(N001.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
// Pattern: (add:i32 (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i8:Other), GPR:i32:$LHS)
// Emits: (t2SXTABrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
// Pattern complexity = 13 cost = 1 size = 0
- if (cast<VTSDNode>(N01)->getVT() == MVT::i8) {
- SDValue N1 = N.getOperand(1);
+ if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i8) {
+ SDValue N1 = N->getOperand(1);
if (N001.getValueType() == MVT::i32) {
SDNode *Result = Emit_85(N, ARM::t2SXTABrr_rot, MVT::i32);
return Result;
@@ -10227,8 +10066,8 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (sext_inreg:i32 (rotr:i32 GPR:i32:$RHS, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i16:Other), GPR:i32:$LHS)
// Emits: (t2SXTAHrr_rot:i32 GPR:i32:$LHS, GPR:i32:$RHS, (imm:i32):$rot)
// Pattern complexity = 13 cost = 1 size = 0
- if (cast<VTSDNode>(N01)->getVT() == MVT::i16) {
- SDValue N1 = N.getOperand(1);
+ if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i16) {
+ SDValue N1 = N->getOperand(1);
if (N001.getValueType() == MVT::i32) {
SDNode *Result = Emit_85(N, ARM::t2SXTAHrr_rot, MVT::i32);
return Result;
@@ -10243,19 +10082,19 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 12 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (cast<VTSDNode>(N101)->getVT() == MVT::i16) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (cast<VTSDNode>(N111)->getVT() == MVT::i16) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N101.getNode())->getVT() == MVT::i16) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N111.getNode())->getVT() == MVT::i16) {
SDNode *Result = Emit_60(N, ARM::SMLABB, MVT::i32);
return Result;
}
@@ -10265,8 +10104,8 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (add:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Emits: (t2ADDrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
@@ -10283,17 +10122,17 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPR:i32:$acc, (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sext_inreg:i32 GPR:i32:$b, i16:Other)))
// Emits: (t2SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 12 cost = 1 size = 0
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (cast<VTSDNode>(N101)->getVT() == MVT::i16) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (cast<VTSDNode>(N111)->getVT() == MVT::i16) {
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N101.getNode())->getVT() == MVT::i16) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N111.getNode())->getVT() == MVT::i16) {
SDNode *Result = Emit_60(N, ARM::t2SMLABB, MVT::i32);
return Result;
}
@@ -10307,18 +10146,18 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 12 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- if (cast<VTSDNode>(N011)->getVT() == MVT::i16) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N001.getNode())->getVT() == MVT::i16) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N011.getNode())->getVT() == MVT::i16) {
SDNode *Result = Emit_90(N, ARM::SMLABB, MVT::i32);
return Result;
}
@@ -10328,7 +10167,7 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (add:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs)
// Emits: (t2ADDrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
@@ -10345,17 +10184,17 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sext_inreg:i32 GPR:i32:$b, i16:Other)), GPR:i32:$acc)
// Emits: (t2SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 12 cost = 1 size = 0
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- if (cast<VTSDNode>(N011)->getVT() == MVT::i16) {
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N001.getNode())->getVT() == MVT::i16) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N011.getNode())->getVT() == MVT::i16) {
SDNode *Result = Emit_90(N, ARM::t2SMLABB, MVT::i32);
return Result;
}
@@ -10367,25 +10206,25 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_imm0_255_neg>><<X:imm_neg_XFORM>>:$imm)
// Emits: (t2SUBri:i32 GPR:i32:$src, (imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_imm0_255_neg>>:$imm))
// Pattern complexity = 8 cost = 1 size = 0
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_imm0_255_neg(N1.getNode())) {
SDNode *Result = Emit_69(N, ARM::t2SUBri, MVT::i32);
return Result;
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (add:i32 GPR:i32:$acc, (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$a, GPR:i32<<P:Predicate_sext_16_node>>:$b))
// Emits: (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 8 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
if (Predicate_sext_16_node(N10.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (Predicate_sext_16_node(N11.getNode())) {
SDNode *Result = Emit_77(N, ARM::SMLABB, MVT::i32);
return Result;
@@ -10397,10 +10236,10 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$a, GPR:i32<<P:Predicate_sext_16_node>>:$b), GPR:i32:$acc)
// Emits: (SMLABB:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$acc)
// Pattern complexity = 8 cost = 1 size = 0
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
if (Predicate_sext_16_node(N00.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
if (Predicate_sext_16_node(N01.getNode())) {
SDNode *Result = Emit_59(N, ARM::SMLABB, MVT::i32);
return Result;
@@ -10413,18 +10252,18 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (ADDri:i32 GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 7 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N1.getNode())) {
SDNode *Result = Emit_55(N, ARM::ADDri, MVT::i32);
return Result;
}
}
if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (add:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_7>>:$rhs)
// Emits: (tADDi3:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
@@ -10460,9 +10299,9 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (add:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
// Emits: (t2ADDri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
@@ -10502,18 +10341,18 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (SUBri:i32 GPR:i32:$src, (so_imm_neg_XFORM:i32 (imm:i32)<<P:Predicate_so_imm_neg>>:$imm))
// Pattern complexity = 7 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm_neg(N1.getNode())) {
SDNode *Result = Emit_73(N, ARM::SUBri, MVT::i32);
return Result;
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (add:i32 GPR:i32:$LHS, (imm:i32)<<P:Predicate_t2_so_imm2part>>:$RHS)
// Emits: (t2ADDri:i32 (t2ADDri:i32 GPR:i32:$LHS, (t2_so_imm2part_1:i32 (imm:i32):$RHS)), (t2_so_imm2part_2:i32 (imm:i32):$RHS))
@@ -10533,9 +10372,9 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (add:i32 GPR:i32:$LHS, (imm:i32)<<P:Predicate_so_imm2part>>:$RHS)
// Emits: (ADDri:i32 (ADDri:i32 GPR:i32:$LHS, (so_imm2part_1:i32 (imm:i32):$RHS)), (so_imm2part_2:i32 (imm:i32):$RHS))
@@ -10555,16 +10394,16 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
// Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 GPR:i32:$RHS, i8:Other))
// Emits: (SXTABrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
// Pattern complexity = 6 cost = 1 size = 0
- if (cast<VTSDNode>(N11)->getVT() == MVT::i8) {
+ if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i8) {
SDNode *Result = Emit_51(N, ARM::SXTABrr, MVT::i32);
return Result;
}
@@ -10572,7 +10411,7 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 GPR:i32:$RHS, i16:Other))
// Emits: (SXTAHrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
// Pattern complexity = 6 cost = 1 size = 0
- if (cast<VTSDNode>(N11)->getVT() == MVT::i16) {
+ if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i16) {
SDNode *Result = Emit_51(N, ARM::SXTAHrr, MVT::i32);
return Result;
}
@@ -10583,8 +10422,8 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (MLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
// Pattern complexity = 6 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::MUL) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_58(N, ARM::MLA, MVT::i32);
return Result;
}
@@ -10594,24 +10433,24 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (SMMLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
// Pattern complexity = 6 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::MULHS) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MULHS) {
SDNode *Result = Emit_59(N, ARM::SMMLA, MVT::i32);
return Result;
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
// Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 GPR:i32:$RHS, i8:Other))
// Emits: (t2SXTABrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
// Pattern complexity = 6 cost = 1 size = 0
- if (cast<VTSDNode>(N11)->getVT() == MVT::i8) {
+ if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i8) {
SDNode *Result = Emit_51(N, ARM::t2SXTABrr, MVT::i32);
return Result;
}
@@ -10619,7 +10458,7 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPR:i32:$LHS, (sext_inreg:i32 GPR:i32:$RHS, i16:Other))
// Emits: (t2SXTAHrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
// Pattern complexity = 6 cost = 1 size = 0
- if (cast<VTSDNode>(N11)->getVT() == MVT::i16) {
+ if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i16) {
SDNode *Result = Emit_51(N, ARM::t2SXTAHrr, MVT::i32);
return Result;
}
@@ -10629,7 +10468,7 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (mul:i32 GPR:i32:$a, GPR:i32:$b), GPR:i32:$c)
// Emits: (t2MLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::MUL) {
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_59(N, ARM::t2MLA, MVT::i32);
return Result;
}
@@ -10637,21 +10476,21 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (mulhs:i32 GPR:i32:$a, GPR:i32:$b), GPR:i32:$c)
// Emits: (t2SMMLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::MULHS) {
+ if (N0.getNode()->getOpcode() == ISD::MULHS) {
SDNode *Result = Emit_59(N, ARM::t2SMMLA, MVT::i32);
return Result;
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
// Pattern: (add:i32 (sext_inreg:i32 GPR:i32:$RHS, i8:Other), GPR:i32:$LHS)
// Emits: (SXTABrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
// Pattern complexity = 6 cost = 1 size = 0
- if (cast<VTSDNode>(N01)->getVT() == MVT::i8) {
+ if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i8) {
SDNode *Result = Emit_84(N, ARM::SXTABrr, MVT::i32);
return Result;
}
@@ -10659,7 +10498,7 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (sext_inreg:i32 GPR:i32:$RHS, i16:Other), GPR:i32:$LHS)
// Emits: (SXTAHrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
// Pattern complexity = 6 cost = 1 size = 0
- if (cast<VTSDNode>(N01)->getVT() == MVT::i16) {
+ if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i16) {
SDNode *Result = Emit_84(N, ARM::SXTAHrr, MVT::i32);
return Result;
}
@@ -10670,9 +10509,9 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (MLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
// Pattern complexity = 6 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_89(N, ARM::MLA, MVT::i32);
return Result;
}
@@ -10682,23 +10521,23 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Emits: (SMMLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
// Pattern complexity = 6 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MULHS) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MULHS) {
SDNode *Result = Emit_77(N, ARM::SMMLA, MVT::i32);
return Result;
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
// Pattern: (add:i32 (sext_inreg:i32 GPR:i32:$RHS, i8:Other), GPR:i32:$LHS)
// Emits: (t2SXTABrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
// Pattern complexity = 6 cost = 1 size = 0
- if (cast<VTSDNode>(N01)->getVT() == MVT::i8) {
+ if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i8) {
SDNode *Result = Emit_84(N, ARM::t2SXTABrr, MVT::i32);
return Result;
}
@@ -10706,17 +10545,17 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (sext_inreg:i32 GPR:i32:$RHS, i16:Other), GPR:i32:$LHS)
// Emits: (t2SXTAHrr:i32 GPR:i32:$LHS, GPR:i32:$RHS)
// Pattern complexity = 6 cost = 1 size = 0
- if (cast<VTSDNode>(N01)->getVT() == MVT::i16) {
+ if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i16) {
SDNode *Result = Emit_84(N, ARM::t2SXTAHrr, MVT::i32);
return Result;
}
}
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
// Pattern: (add:i32 GPR:i32:$c, (mul:i32 GPR:i32:$a, GPR:i32:$b))
// Emits: (t2MLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::MUL) {
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_77(N, ARM::t2MLA, MVT::i32);
return Result;
}
@@ -10724,7 +10563,7 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPR:i32:$c, (mulhs:i32 GPR:i32:$a, GPR:i32:$b))
// Emits: (t2SMMLA:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::MULHS) {
+ if (N1.getNode()->getOpcode() == ISD::MULHS) {
SDNode *Result = Emit_77(N, ARM::t2SMMLA, MVT::i32);
return Result;
}
@@ -10758,62 +10597,62 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_125(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_125(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, N10, N11, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_126(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_126(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, N10, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_127(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_127(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, N00, N01, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_128(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_128(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, N00, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-SDNode *Select_ISD_ADD_v8i8(const SDValue &N) {
+SDNode *Select_ISD_ADD_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
// Pattern: (add:v8i8 DPR:v8i8:$src1, (NEONvshrs:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM))
// Emits: (VSRAsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VSHRs) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VSHRs) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VSRAsv8i8, MVT::v8i8);
return Result;
}
@@ -10822,10 +10661,10 @@ SDNode *Select_ISD_ADD_v8i8(const SDValue &N) {
// Pattern: (add:v8i8 DPR:v8i8:$src1, (NEONvshru:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM))
// Emits: (VSRAuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VSHRu) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VSHRu) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VSRAuv8i8, MVT::v8i8);
return Result;
}
@@ -10834,10 +10673,10 @@ SDNode *Select_ISD_ADD_v8i8(const SDValue &N) {
// Pattern: (add:v8i8 DPR:v8i8:$src1, (NEONvrshrs:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM))
// Emits: (VRSRAsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VRSHRs) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VRSHRs) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VRSRAsv8i8, MVT::v8i8);
return Result;
}
@@ -10846,10 +10685,10 @@ SDNode *Select_ISD_ADD_v8i8(const SDValue &N) {
// Pattern: (add:v8i8 DPR:v8i8:$src1, (NEONvrshru:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM))
// Emits: (VRSRAuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VRSHRu) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VRSHRu) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VRSRAuv8i8, MVT::v8i8);
return Result;
}
@@ -10859,10 +10698,10 @@ SDNode *Select_ISD_ADD_v8i8(const SDValue &N) {
// Pattern: (add:v8i8 (NEONvshrs:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM), DPR:v8i8:$src1)
// Emits: (VSRAsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VSHRs) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VSHRs) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VSRAsv8i8, MVT::v8i8);
return Result;
}
@@ -10871,10 +10710,10 @@ SDNode *Select_ISD_ADD_v8i8(const SDValue &N) {
// Pattern: (add:v8i8 (NEONvshru:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM), DPR:v8i8:$src1)
// Emits: (VSRAuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VSHRu) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VSHRu) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VSRAuv8i8, MVT::v8i8);
return Result;
}
@@ -10883,10 +10722,10 @@ SDNode *Select_ISD_ADD_v8i8(const SDValue &N) {
// Pattern: (add:v8i8 (NEONvrshrs:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM), DPR:v8i8:$src1)
// Emits: (VRSRAsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VRSHRs) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VRSHRs) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VRSRAsv8i8, MVT::v8i8);
return Result;
}
@@ -10895,10 +10734,10 @@ SDNode *Select_ISD_ADD_v8i8(const SDValue &N) {
// Pattern: (add:v8i8 (NEONvrshru:v8i8 DPR:v8i8:$src2, (imm:i32):$SIMM), DPR:v8i8:$src1)
// Emits: (VRSRAuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VRSHRu) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VRSHRu) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VRSRAuv8i8, MVT::v8i8);
return Result;
}
@@ -10908,8 +10747,8 @@ SDNode *Select_ISD_ADD_v8i8(const SDValue &N) {
// Emits: (VMLAv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
// Pattern complexity = 6 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_125(N, ARM::VMLAv8i8, MVT::v8i8);
return Result;
}
@@ -10918,7 +10757,7 @@ SDNode *Select_ISD_ADD_v8i8(const SDValue &N) {
// Pattern: (add:v8i8 (mul:v8i8 DPR:v8i8:$src2, DPR:v8i8:$src3), DPR:v8i8:$src1)
// Emits: (VMLAv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::MUL) {
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_127(N, ARM::VMLAv8i8, MVT::v8i8);
return Result;
}
@@ -10935,20 +10774,20 @@ SDNode *Select_ISD_ADD_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ADD_v16i8(const SDValue &N) {
+SDNode *Select_ISD_ADD_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
// Pattern: (add:v16i8 QPR:v16i8:$src1, (NEONvshrs:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM))
// Emits: (VSRAsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VSHRs) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VSHRs) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VSRAsv16i8, MVT::v16i8);
return Result;
}
@@ -10957,10 +10796,10 @@ SDNode *Select_ISD_ADD_v16i8(const SDValue &N) {
// Pattern: (add:v16i8 QPR:v16i8:$src1, (NEONvshru:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM))
// Emits: (VSRAuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VSHRu) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VSHRu) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VSRAuv16i8, MVT::v16i8);
return Result;
}
@@ -10969,10 +10808,10 @@ SDNode *Select_ISD_ADD_v16i8(const SDValue &N) {
// Pattern: (add:v16i8 QPR:v16i8:$src1, (NEONvrshrs:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM))
// Emits: (VRSRAsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VRSHRs) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VRSHRs) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VRSRAsv16i8, MVT::v16i8);
return Result;
}
@@ -10981,10 +10820,10 @@ SDNode *Select_ISD_ADD_v16i8(const SDValue &N) {
// Pattern: (add:v16i8 QPR:v16i8:$src1, (NEONvrshru:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM))
// Emits: (VRSRAuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VRSHRu) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VRSHRu) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VRSRAuv16i8, MVT::v16i8);
return Result;
}
@@ -10994,10 +10833,10 @@ SDNode *Select_ISD_ADD_v16i8(const SDValue &N) {
// Pattern: (add:v16i8 (NEONvshrs:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM), QPR:v16i8:$src1)
// Emits: (VSRAsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VSHRs) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VSHRs) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VSRAsv16i8, MVT::v16i8);
return Result;
}
@@ -11006,10 +10845,10 @@ SDNode *Select_ISD_ADD_v16i8(const SDValue &N) {
// Pattern: (add:v16i8 (NEONvshru:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM), QPR:v16i8:$src1)
// Emits: (VSRAuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VSHRu) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VSHRu) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VSRAuv16i8, MVT::v16i8);
return Result;
}
@@ -11018,10 +10857,10 @@ SDNode *Select_ISD_ADD_v16i8(const SDValue &N) {
// Pattern: (add:v16i8 (NEONvrshrs:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM), QPR:v16i8:$src1)
// Emits: (VRSRAsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VRSHRs) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VRSHRs) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VRSRAsv16i8, MVT::v16i8);
return Result;
}
@@ -11030,10 +10869,10 @@ SDNode *Select_ISD_ADD_v16i8(const SDValue &N) {
// Pattern: (add:v16i8 (NEONvrshru:v16i8 QPR:v16i8:$src2, (imm:i32):$SIMM), QPR:v16i8:$src1)
// Emits: (VRSRAuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VRSHRu) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VRSHRu) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VRSRAuv16i8, MVT::v16i8);
return Result;
}
@@ -11043,8 +10882,8 @@ SDNode *Select_ISD_ADD_v16i8(const SDValue &N) {
// Emits: (VMLAv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, QPR:v16i8:$src3)
// Pattern complexity = 6 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_125(N, ARM::VMLAv16i8, MVT::v16i8);
return Result;
}
@@ -11053,7 +10892,7 @@ SDNode *Select_ISD_ADD_v16i8(const SDValue &N) {
// Pattern: (add:v16i8 (mul:v16i8 QPR:v16i8:$src2, QPR:v16i8:$src3), QPR:v16i8:$src1)
// Emits: (VMLAv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, QPR:v16i8:$src3)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::MUL) {
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_127(N, ARM::VMLAv16i8, MVT::v16i8);
return Result;
}
@@ -11070,76 +10909,76 @@ SDNode *Select_ISD_ADD_v16i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_129(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
+DISABLE_INLINE SDNode *Emit_129(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N111)->getZExtValue()), MVT::i32);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, N10, N110, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_130(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_130(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, N11, N100, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_131(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_131(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N011)->getZExtValue()), MVT::i32);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, N00, N010, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_132(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_132(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N001)->getZExtValue()), MVT::i32);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, N01, N000, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
}
-SDNode *Select_ISD_ADD_v4i16(const SDValue &N) {
+SDNode *Select_ISD_ADD_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (add:v4i16 DPR:v4i16:$src1, (mul:v4i16 DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane)))
// Emits: (VMLAslv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_129(N, ARM::VMLAslv4i16, MVT::v4i16);
return Result;
@@ -11150,11 +10989,11 @@ SDNode *Select_ISD_ADD_v4i16(const SDValue &N) {
// Pattern: (add:v4i16 DPR:v4i16:$src1, (mul:v4i16 (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane), DPR:v4i16:$src2))
// Emits: (VMLAslv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
- if (N10.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
+ if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_130(N, ARM::VMLAslv4i16, MVT::v4i16);
return Result;
@@ -11163,19 +11002,19 @@ SDNode *Select_ISD_ADD_v4i16(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (add:v4i16 (mul:v4i16 DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane)), DPR:v4i16:$src1)
// Emits: (VMLAslv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
if (N010.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_131(N, ARM::VMLAslv4i16, MVT::v4i16);
return Result;
@@ -11187,12 +11026,12 @@ SDNode *Select_ISD_ADD_v4i16(const SDValue &N) {
// Pattern: (add:v4i16 (mul:v4i16 (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane), DPR:v4i16:$src2), DPR:v4i16:$src1)
// Emits: (VMLAslv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
- if (N00.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ if (N00.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_132(N, ARM::VMLAslv4i16, MVT::v4i16);
return Result;
@@ -11201,15 +11040,15 @@ SDNode *Select_ISD_ADD_v4i16(const SDValue &N) {
}
}
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
// Pattern: (add:v4i16 DPR:v4i16:$src1, (NEONvshrs:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM))
// Emits: (VSRAsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VSHRs) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VSHRs) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VSRAsv4i16, MVT::v4i16);
return Result;
}
@@ -11218,10 +11057,10 @@ SDNode *Select_ISD_ADD_v4i16(const SDValue &N) {
// Pattern: (add:v4i16 DPR:v4i16:$src1, (NEONvshru:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM))
// Emits: (VSRAuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VSHRu) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VSHRu) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VSRAuv4i16, MVT::v4i16);
return Result;
}
@@ -11230,10 +11069,10 @@ SDNode *Select_ISD_ADD_v4i16(const SDValue &N) {
// Pattern: (add:v4i16 DPR:v4i16:$src1, (NEONvrshrs:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM))
// Emits: (VRSRAsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VRSHRs) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VRSHRs) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VRSRAsv4i16, MVT::v4i16);
return Result;
}
@@ -11242,10 +11081,10 @@ SDNode *Select_ISD_ADD_v4i16(const SDValue &N) {
// Pattern: (add:v4i16 DPR:v4i16:$src1, (NEONvrshru:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM))
// Emits: (VRSRAuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VRSHRu) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VRSHRu) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VRSRAuv4i16, MVT::v4i16);
return Result;
}
@@ -11255,10 +11094,10 @@ SDNode *Select_ISD_ADD_v4i16(const SDValue &N) {
// Pattern: (add:v4i16 (NEONvshrs:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM), DPR:v4i16:$src1)
// Emits: (VSRAsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VSHRs) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VSHRs) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VSRAsv4i16, MVT::v4i16);
return Result;
}
@@ -11267,10 +11106,10 @@ SDNode *Select_ISD_ADD_v4i16(const SDValue &N) {
// Pattern: (add:v4i16 (NEONvshru:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM), DPR:v4i16:$src1)
// Emits: (VSRAuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VSHRu) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VSHRu) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VSRAuv4i16, MVT::v4i16);
return Result;
}
@@ -11279,10 +11118,10 @@ SDNode *Select_ISD_ADD_v4i16(const SDValue &N) {
// Pattern: (add:v4i16 (NEONvrshrs:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM), DPR:v4i16:$src1)
// Emits: (VRSRAsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VRSHRs) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VRSHRs) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VRSRAsv4i16, MVT::v4i16);
return Result;
}
@@ -11291,10 +11130,10 @@ SDNode *Select_ISD_ADD_v4i16(const SDValue &N) {
// Pattern: (add:v4i16 (NEONvrshru:v4i16 DPR:v4i16:$src2, (imm:i32):$SIMM), DPR:v4i16:$src1)
// Emits: (VRSRAuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VRSHRu) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VRSHRu) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VRSRAuv4i16, MVT::v4i16);
return Result;
}
@@ -11304,8 +11143,8 @@ SDNode *Select_ISD_ADD_v4i16(const SDValue &N) {
// Emits: (VMLAv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
// Pattern complexity = 6 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_125(N, ARM::VMLAv4i16, MVT::v4i16);
return Result;
}
@@ -11314,7 +11153,7 @@ SDNode *Select_ISD_ADD_v4i16(const SDValue &N) {
// Pattern: (add:v4i16 (mul:v4i16 DPR:v4i16:$src2, DPR:v4i16:$src3), DPR:v4i16:$src1)
// Emits: (VMLAv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::MUL) {
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_127(N, ARM::VMLAv4i16, MVT::v4i16);
return Result;
}
@@ -11331,87 +11170,87 @@ SDNode *Select_ISD_ADD_v4i16(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_133(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
+DISABLE_INLINE SDNode *Emit_133(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N111)->getZExtValue()), MVT::i32);
SDValue Tmp4 = Transform_DSubReg_i16_reg(Tmp3.getNode());
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N110, Tmp4), 0);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N110, Tmp4), 0);
SDValue Tmp6 = Transform_SubReg_i16_lane(Tmp3.getNode());
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { N0, N10, Tmp5, Tmp6, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 6);
-}
-DISABLE_INLINE SDNode *Emit_134(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 6);
+}
+DISABLE_INLINE SDNode *Emit_134(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
SDValue Tmp4 = Transform_DSubReg_i16_reg(Tmp3.getNode());
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N100, Tmp4), 0);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N100, Tmp4), 0);
SDValue Tmp6 = Transform_SubReg_i16_lane(Tmp3.getNode());
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { N0, N11, Tmp5, Tmp6, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 6);
-}
-DISABLE_INLINE SDNode *Emit_135(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 6);
+}
+DISABLE_INLINE SDNode *Emit_135(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N011)->getZExtValue()), MVT::i32);
SDValue Tmp4 = Transform_DSubReg_i16_reg(Tmp3.getNode());
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N010, Tmp4), 0);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N010, Tmp4), 0);
SDValue Tmp6 = Transform_SubReg_i16_lane(Tmp3.getNode());
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { N1, N00, Tmp5, Tmp6, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 6);
-}
-DISABLE_INLINE SDNode *Emit_136(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 6);
+}
+DISABLE_INLINE SDNode *Emit_136(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N001)->getZExtValue()), MVT::i32);
SDValue Tmp4 = Transform_DSubReg_i16_reg(Tmp3.getNode());
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N000, Tmp4), 0);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N000, Tmp4), 0);
SDValue Tmp6 = Transform_SubReg_i16_lane(Tmp3.getNode());
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { N1, N01, Tmp5, Tmp6, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 6);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 6);
}
-SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
+SDNode *Select_ISD_ADD_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (add:v8i16 QPR:v8i16:$src1, (mul:v8i16 QPR:v8i16:$src2, (NEONvduplane:v8i16 DPR_8:v4i16:$src3, (imm:i32):$lane)))
// Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_129(N, ARM::VMLAslv8i16, MVT::v8i16);
return Result;
@@ -11422,11 +11261,11 @@ SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
// Pattern: (add:v8i16 QPR:v8i16:$src1, (mul:v8i16 (NEONvduplane:v8i16 DPR_8:v4i16:$src3, (imm:i32):$lane), QPR:v8i16:$src2))
// Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
- if (N10.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
+ if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_130(N, ARM::VMLAslv8i16, MVT::v8i16);
return Result;
@@ -11435,19 +11274,19 @@ SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (add:v8i16 (mul:v8i16 QPR:v8i16:$src2, (NEONvduplane:v8i16 DPR_8:v4i16:$src3, (imm:i32):$lane)), QPR:v8i16:$src1)
// Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
if (N010.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_131(N, ARM::VMLAslv8i16, MVT::v8i16);
return Result;
@@ -11459,12 +11298,12 @@ SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
// Pattern: (add:v8i16 (mul:v8i16 (NEONvduplane:v8i16 DPR_8:v4i16:$src3, (imm:i32):$lane), QPR:v8i16:$src2), QPR:v8i16:$src1)
// Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
- if (N00.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ if (N00.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_132(N, ARM::VMLAslv8i16, MVT::v8i16);
return Result;
@@ -11474,21 +11313,21 @@ SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (add:v8i16 QPR:v8i16:$src1, (mul:v8i16 QPR:v8i16:$src2, (NEONvduplane:v8i16 QPR:v8i16:$src3, (imm:i32):$lane)))
// Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src3, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
// Pattern complexity = 12 cost = 2 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_133(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
@@ -11499,11 +11338,11 @@ SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
// Pattern: (add:v8i16 QPR:v8i16:$src1, (mul:v8i16 (NEONvduplane:v8i16 QPR:v8i16:$src3, (imm:i32):$lane), QPR:v8i16:$src2))
// Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src3, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
// Pattern complexity = 12 cost = 2 size = 0
- if (N10.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
+ if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_134(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
@@ -11512,19 +11351,19 @@ SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (add:v8i16 (mul:v8i16 QPR:v8i16:$src2, (NEONvduplane:v8i16 QPR:v8i16:$src3, (imm:i32):$lane)), QPR:v8i16:$src1)
// Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src3, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
// Pattern complexity = 12 cost = 2 size = 0
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
if (N010.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_135(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
@@ -11536,12 +11375,12 @@ SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
// Pattern: (add:v8i16 (mul:v8i16 (NEONvduplane:v8i16 QPR:v8i16:$src3, (imm:i32):$lane), QPR:v8i16:$src2), QPR:v8i16:$src1)
// Emits: (VMLAslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src3, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
// Pattern complexity = 12 cost = 2 size = 0
- if (N00.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ if (N00.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_136(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
@@ -11552,17 +11391,17 @@ SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
}
if ((Subtarget->hasNEON())) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
// Pattern: (add:v8i16 QPR:v8i16:$src1, (NEONvshrs:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM))
// Emits: (VSRAsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VSHRs) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VSHRs) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VSRAsv8i16, MVT::v8i16);
return Result;
}
@@ -11571,10 +11410,10 @@ SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
// Pattern: (add:v8i16 QPR:v8i16:$src1, (NEONvshru:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM))
// Emits: (VSRAuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VSHRu) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VSHRu) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VSRAuv8i16, MVT::v8i16);
return Result;
}
@@ -11583,10 +11422,10 @@ SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
// Pattern: (add:v8i16 QPR:v8i16:$src1, (NEONvrshrs:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM))
// Emits: (VRSRAsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VRSHRs) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VRSHRs) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VRSRAsv8i16, MVT::v8i16);
return Result;
}
@@ -11595,10 +11434,10 @@ SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
// Pattern: (add:v8i16 QPR:v8i16:$src1, (NEONvrshru:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM))
// Emits: (VRSRAuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VRSHRu) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VRSHRu) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VRSRAuv8i16, MVT::v8i16);
return Result;
}
@@ -11608,10 +11447,10 @@ SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
// Pattern: (add:v8i16 (NEONvshrs:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM), QPR:v8i16:$src1)
// Emits: (VSRAsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VSHRs) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VSHRs) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VSRAsv8i16, MVT::v8i16);
return Result;
}
@@ -11620,10 +11459,10 @@ SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
// Pattern: (add:v8i16 (NEONvshru:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM), QPR:v8i16:$src1)
// Emits: (VSRAuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VSHRu) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VSHRu) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VSRAuv8i16, MVT::v8i16);
return Result;
}
@@ -11632,10 +11471,10 @@ SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
// Pattern: (add:v8i16 (NEONvrshrs:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM), QPR:v8i16:$src1)
// Emits: (VRSRAsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VRSHRs) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VRSHRs) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VRSRAsv8i16, MVT::v8i16);
return Result;
}
@@ -11644,10 +11483,10 @@ SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
// Pattern: (add:v8i16 (NEONvrshru:v8i16 QPR:v8i16:$src2, (imm:i32):$SIMM), QPR:v8i16:$src1)
// Emits: (VRSRAuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VRSHRu) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VRSHRu) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VRSRAuv8i16, MVT::v8i16);
return Result;
}
@@ -11657,8 +11496,8 @@ SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
// Emits: (VMLAv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, QPR:v8i16:$src3)
// Pattern complexity = 6 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_125(N, ARM::VMLAv8i16, MVT::v8i16);
return Result;
}
@@ -11667,7 +11506,7 @@ SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
// Pattern: (add:v8i16 (mul:v8i16 QPR:v8i16:$src2, QPR:v8i16:$src3), QPR:v8i16:$src1)
// Emits: (VMLAv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, QPR:v8i16:$src3)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::MUL) {
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_127(N, ARM::VMLAv8i16, MVT::v8i16);
return Result;
}
@@ -11684,24 +11523,24 @@ SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ADD_v2i32(const SDValue &N) {
+SDNode *Select_ISD_ADD_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (add:v2i32 DPR:v2i32:$src1, (mul:v2i32 DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane)))
// Emits: (VMLAslv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_129(N, ARM::VMLAslv2i32, MVT::v2i32);
return Result;
@@ -11712,11 +11551,11 @@ SDNode *Select_ISD_ADD_v2i32(const SDValue &N) {
// Pattern: (add:v2i32 DPR:v2i32:$src1, (mul:v2i32 (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane), DPR:v2i32:$src2))
// Emits: (VMLAslv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
- if (N10.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
+ if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_130(N, ARM::VMLAslv2i32, MVT::v2i32);
return Result;
@@ -11725,19 +11564,19 @@ SDNode *Select_ISD_ADD_v2i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (add:v2i32 (mul:v2i32 DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane)), DPR:v2i32:$src1)
// Emits: (VMLAslv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
if (N010.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_131(N, ARM::VMLAslv2i32, MVT::v2i32);
return Result;
@@ -11749,12 +11588,12 @@ SDNode *Select_ISD_ADD_v2i32(const SDValue &N) {
// Pattern: (add:v2i32 (mul:v2i32 (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane), DPR:v2i32:$src2), DPR:v2i32:$src1)
// Emits: (VMLAslv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
- if (N00.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ if (N00.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_132(N, ARM::VMLAslv2i32, MVT::v2i32);
return Result;
@@ -11763,15 +11602,15 @@ SDNode *Select_ISD_ADD_v2i32(const SDValue &N) {
}
}
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
// Pattern: (add:v2i32 DPR:v2i32:$src1, (NEONvshrs:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM))
// Emits: (VSRAsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VSHRs) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VSHRs) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VSRAsv2i32, MVT::v2i32);
return Result;
}
@@ -11780,10 +11619,10 @@ SDNode *Select_ISD_ADD_v2i32(const SDValue &N) {
// Pattern: (add:v2i32 DPR:v2i32:$src1, (NEONvshru:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM))
// Emits: (VSRAuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VSHRu) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VSHRu) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VSRAuv2i32, MVT::v2i32);
return Result;
}
@@ -11792,10 +11631,10 @@ SDNode *Select_ISD_ADD_v2i32(const SDValue &N) {
// Pattern: (add:v2i32 DPR:v2i32:$src1, (NEONvrshrs:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM))
// Emits: (VRSRAsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VRSHRs) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VRSHRs) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VRSRAsv2i32, MVT::v2i32);
return Result;
}
@@ -11804,10 +11643,10 @@ SDNode *Select_ISD_ADD_v2i32(const SDValue &N) {
// Pattern: (add:v2i32 DPR:v2i32:$src1, (NEONvrshru:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM))
// Emits: (VRSRAuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VRSHRu) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VRSHRu) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VRSRAuv2i32, MVT::v2i32);
return Result;
}
@@ -11817,10 +11656,10 @@ SDNode *Select_ISD_ADD_v2i32(const SDValue &N) {
// Pattern: (add:v2i32 (NEONvshrs:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM), DPR:v2i32:$src1)
// Emits: (VSRAsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VSHRs) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VSHRs) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VSRAsv2i32, MVT::v2i32);
return Result;
}
@@ -11829,10 +11668,10 @@ SDNode *Select_ISD_ADD_v2i32(const SDValue &N) {
// Pattern: (add:v2i32 (NEONvshru:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM), DPR:v2i32:$src1)
// Emits: (VSRAuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VSHRu) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VSHRu) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VSRAuv2i32, MVT::v2i32);
return Result;
}
@@ -11841,10 +11680,10 @@ SDNode *Select_ISD_ADD_v2i32(const SDValue &N) {
// Pattern: (add:v2i32 (NEONvrshrs:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM), DPR:v2i32:$src1)
// Emits: (VRSRAsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VRSHRs) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VRSHRs) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VRSRAsv2i32, MVT::v2i32);
return Result;
}
@@ -11853,10 +11692,10 @@ SDNode *Select_ISD_ADD_v2i32(const SDValue &N) {
// Pattern: (add:v2i32 (NEONvrshru:v2i32 DPR:v2i32:$src2, (imm:i32):$SIMM), DPR:v2i32:$src1)
// Emits: (VRSRAuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VRSHRu) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VRSHRu) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VRSRAuv2i32, MVT::v2i32);
return Result;
}
@@ -11866,8 +11705,8 @@ SDNode *Select_ISD_ADD_v2i32(const SDValue &N) {
// Emits: (VMLAv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 6 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_125(N, ARM::VMLAv2i32, MVT::v2i32);
return Result;
}
@@ -11876,7 +11715,7 @@ SDNode *Select_ISD_ADD_v2i32(const SDValue &N) {
// Pattern: (add:v2i32 (mul:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src3), DPR:v2i32:$src1)
// Emits: (VMLAv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::MUL) {
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_127(N, ARM::VMLAv2i32, MVT::v2i32);
return Result;
}
@@ -11893,87 +11732,87 @@ SDNode *Select_ISD_ADD_v2i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_137(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
+DISABLE_INLINE SDNode *Emit_137(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N111)->getZExtValue()), MVT::i32);
SDValue Tmp4 = Transform_DSubReg_i32_reg(Tmp3.getNode());
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N110, Tmp4), 0);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N110, Tmp4), 0);
SDValue Tmp6 = Transform_SubReg_i32_lane(Tmp3.getNode());
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { N0, N10, Tmp5, Tmp6, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 6);
-}
-DISABLE_INLINE SDNode *Emit_138(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 6);
+}
+DISABLE_INLINE SDNode *Emit_138(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
SDValue Tmp4 = Transform_DSubReg_i32_reg(Tmp3.getNode());
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N100, Tmp4), 0);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N100, Tmp4), 0);
SDValue Tmp6 = Transform_SubReg_i32_lane(Tmp3.getNode());
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { N0, N11, Tmp5, Tmp6, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 6);
-}
-DISABLE_INLINE SDNode *Emit_139(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 6);
+}
+DISABLE_INLINE SDNode *Emit_139(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N011)->getZExtValue()), MVT::i32);
SDValue Tmp4 = Transform_DSubReg_i32_reg(Tmp3.getNode());
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N010, Tmp4), 0);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N010, Tmp4), 0);
SDValue Tmp6 = Transform_SubReg_i32_lane(Tmp3.getNode());
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { N1, N00, Tmp5, Tmp6, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 6);
-}
-DISABLE_INLINE SDNode *Emit_140(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 6);
+}
+DISABLE_INLINE SDNode *Emit_140(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N001)->getZExtValue()), MVT::i32);
SDValue Tmp4 = Transform_DSubReg_i32_reg(Tmp3.getNode());
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N000, Tmp4), 0);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N000, Tmp4), 0);
SDValue Tmp6 = Transform_SubReg_i32_lane(Tmp3.getNode());
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { N1, N01, Tmp5, Tmp6, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 6);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 6);
}
-SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
+SDNode *Select_ISD_ADD_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (add:v4i32 QPR:v4i32:$src1, (mul:v4i32 QPR:v4i32:$src2, (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane)))
// Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_129(N, ARM::VMLAslv4i32, MVT::v4i32);
return Result;
@@ -11984,11 +11823,11 @@ SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
// Pattern: (add:v4i32 QPR:v4i32:$src1, (mul:v4i32 (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane), QPR:v4i32:$src2))
// Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
- if (N10.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
+ if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_130(N, ARM::VMLAslv4i32, MVT::v4i32);
return Result;
@@ -11997,19 +11836,19 @@ SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (add:v4i32 (mul:v4i32 QPR:v4i32:$src2, (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane)), QPR:v4i32:$src1)
// Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
if (N010.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_131(N, ARM::VMLAslv4i32, MVT::v4i32);
return Result;
@@ -12021,12 +11860,12 @@ SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
// Pattern: (add:v4i32 (mul:v4i32 (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane), QPR:v4i32:$src2), QPR:v4i32:$src1)
// Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
- if (N00.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ if (N00.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_132(N, ARM::VMLAslv4i32, MVT::v4i32);
return Result;
@@ -12036,21 +11875,21 @@ SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (add:v4i32 QPR:v4i32:$src1, (mul:v4i32 QPR:v4i32:$src2, (NEONvduplane:v4i32 QPR:v4i32:$src3, (imm:i32):$lane)))
// Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 12 cost = 2 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_137(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
@@ -12061,11 +11900,11 @@ SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
// Pattern: (add:v4i32 QPR:v4i32:$src1, (mul:v4i32 (NEONvduplane:v4i32 QPR:v4i32:$src3, (imm:i32):$lane), QPR:v4i32:$src2))
// Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 12 cost = 2 size = 0
- if (N10.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
+ if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_138(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
@@ -12074,19 +11913,19 @@ SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (add:v4i32 (mul:v4i32 QPR:v4i32:$src2, (NEONvduplane:v4i32 QPR:v4i32:$src3, (imm:i32):$lane)), QPR:v4i32:$src1)
// Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 12 cost = 2 size = 0
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
if (N010.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_139(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
@@ -12098,12 +11937,12 @@ SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
// Pattern: (add:v4i32 (mul:v4i32 (NEONvduplane:v4i32 QPR:v4i32:$src3, (imm:i32):$lane), QPR:v4i32:$src2), QPR:v4i32:$src1)
// Emits: (VMLAslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 12 cost = 2 size = 0
- if (N00.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ if (N00.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_140(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
@@ -12114,17 +11953,17 @@ SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
}
if ((Subtarget->hasNEON())) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
// Pattern: (add:v4i32 QPR:v4i32:$src1, (NEONvshrs:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM))
// Emits: (VSRAsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VSHRs) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VSHRs) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VSRAsv4i32, MVT::v4i32);
return Result;
}
@@ -12133,10 +11972,10 @@ SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
// Pattern: (add:v4i32 QPR:v4i32:$src1, (NEONvshru:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM))
// Emits: (VSRAuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VSHRu) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VSHRu) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VSRAuv4i32, MVT::v4i32);
return Result;
}
@@ -12145,10 +11984,10 @@ SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
// Pattern: (add:v4i32 QPR:v4i32:$src1, (NEONvrshrs:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM))
// Emits: (VRSRAsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VRSHRs) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VRSHRs) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VRSRAsv4i32, MVT::v4i32);
return Result;
}
@@ -12157,10 +11996,10 @@ SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
// Pattern: (add:v4i32 QPR:v4i32:$src1, (NEONvrshru:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM))
// Emits: (VRSRAuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VRSHRu) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VRSHRu) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VRSRAuv4i32, MVT::v4i32);
return Result;
}
@@ -12170,10 +12009,10 @@ SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
// Pattern: (add:v4i32 (NEONvshrs:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM), QPR:v4i32:$src1)
// Emits: (VSRAsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VSHRs) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VSHRs) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VSRAsv4i32, MVT::v4i32);
return Result;
}
@@ -12182,10 +12021,10 @@ SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
// Pattern: (add:v4i32 (NEONvshru:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM), QPR:v4i32:$src1)
// Emits: (VSRAuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VSHRu) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VSHRu) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VSRAuv4i32, MVT::v4i32);
return Result;
}
@@ -12194,10 +12033,10 @@ SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
// Pattern: (add:v4i32 (NEONvrshrs:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM), QPR:v4i32:$src1)
// Emits: (VRSRAsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VRSHRs) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VRSHRs) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VRSRAsv4i32, MVT::v4i32);
return Result;
}
@@ -12206,10 +12045,10 @@ SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
// Pattern: (add:v4i32 (NEONvrshru:v4i32 QPR:v4i32:$src2, (imm:i32):$SIMM), QPR:v4i32:$src1)
// Emits: (VRSRAuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VRSHRu) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VRSHRu) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VRSRAuv4i32, MVT::v4i32);
return Result;
}
@@ -12219,8 +12058,8 @@ SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
// Emits: (VMLAv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
// Pattern complexity = 6 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_125(N, ARM::VMLAv4i32, MVT::v4i32);
return Result;
}
@@ -12229,7 +12068,7 @@ SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
// Pattern: (add:v4i32 (mul:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src3), QPR:v4i32:$src1)
// Emits: (VMLAv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::MUL) {
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_127(N, ARM::VMLAv4i32, MVT::v4i32);
return Result;
}
@@ -12246,20 +12085,20 @@ SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ADD_v1i64(const SDValue &N) {
+SDNode *Select_ISD_ADD_v1i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
// Pattern: (add:v1i64 DPR:v1i64:$src1, (NEONvshrs:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM))
// Emits: (VSRAsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VSHRs) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VSHRs) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VSRAsv1i64, MVT::v1i64);
return Result;
}
@@ -12268,10 +12107,10 @@ SDNode *Select_ISD_ADD_v1i64(const SDValue &N) {
// Pattern: (add:v1i64 DPR:v1i64:$src1, (NEONvshru:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM))
// Emits: (VSRAuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VSHRu) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VSHRu) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VSRAuv1i64, MVT::v1i64);
return Result;
}
@@ -12280,10 +12119,10 @@ SDNode *Select_ISD_ADD_v1i64(const SDValue &N) {
// Pattern: (add:v1i64 DPR:v1i64:$src1, (NEONvrshrs:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM))
// Emits: (VRSRAsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VRSHRs) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VRSHRs) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VRSRAsv1i64, MVT::v1i64);
return Result;
}
@@ -12292,10 +12131,10 @@ SDNode *Select_ISD_ADD_v1i64(const SDValue &N) {
// Pattern: (add:v1i64 DPR:v1i64:$src1, (NEONvrshru:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM))
// Emits: (VRSRAuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VRSHRu) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VRSHRu) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VRSRAuv1i64, MVT::v1i64);
return Result;
}
@@ -12305,10 +12144,10 @@ SDNode *Select_ISD_ADD_v1i64(const SDValue &N) {
// Pattern: (add:v1i64 (NEONvshrs:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM), DPR:v1i64:$src1)
// Emits: (VSRAsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VSHRs) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VSHRs) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VSRAsv1i64, MVT::v1i64);
return Result;
}
@@ -12317,10 +12156,10 @@ SDNode *Select_ISD_ADD_v1i64(const SDValue &N) {
// Pattern: (add:v1i64 (NEONvshru:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM), DPR:v1i64:$src1)
// Emits: (VSRAuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VSHRu) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VSHRu) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VSRAuv1i64, MVT::v1i64);
return Result;
}
@@ -12329,10 +12168,10 @@ SDNode *Select_ISD_ADD_v1i64(const SDValue &N) {
// Pattern: (add:v1i64 (NEONvrshrs:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM), DPR:v1i64:$src1)
// Emits: (VRSRAsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VRSHRs) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VRSHRs) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VRSRAsv1i64, MVT::v1i64);
return Result;
}
@@ -12341,10 +12180,10 @@ SDNode *Select_ISD_ADD_v1i64(const SDValue &N) {
// Pattern: (add:v1i64 (NEONvrshru:v1i64 DPR:v1i64:$src2, (imm:i32):$SIMM), DPR:v1i64:$src1)
// Emits: (VRSRAuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VRSHRu) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VRSHRu) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VRSRAuv1i64, MVT::v1i64);
return Result;
}
@@ -12362,20 +12201,20 @@ SDNode *Select_ISD_ADD_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ADD_v2i64(const SDValue &N) {
+SDNode *Select_ISD_ADD_v2i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
// Pattern: (add:v2i64 QPR:v2i64:$src1, (NEONvshrs:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM))
// Emits: (VSRAsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VSHRs) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VSHRs) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VSRAsv2i64, MVT::v2i64);
return Result;
}
@@ -12384,10 +12223,10 @@ SDNode *Select_ISD_ADD_v2i64(const SDValue &N) {
// Pattern: (add:v2i64 QPR:v2i64:$src1, (NEONvshru:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM))
// Emits: (VSRAuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VSHRu) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VSHRu) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VSRAuv2i64, MVT::v2i64);
return Result;
}
@@ -12396,10 +12235,10 @@ SDNode *Select_ISD_ADD_v2i64(const SDValue &N) {
// Pattern: (add:v2i64 QPR:v2i64:$src1, (NEONvrshrs:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM))
// Emits: (VRSRAsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VRSHRs) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VRSHRs) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VRSRAsv2i64, MVT::v2i64);
return Result;
}
@@ -12408,10 +12247,10 @@ SDNode *Select_ISD_ADD_v2i64(const SDValue &N) {
// Pattern: (add:v2i64 QPR:v2i64:$src1, (NEONvrshru:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM))
// Emits: (VRSRAuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ARMISD::VRSHRu) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ARMISD::VRSHRu) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_126(N, ARM::VRSRAuv2i64, MVT::v2i64);
return Result;
}
@@ -12421,10 +12260,10 @@ SDNode *Select_ISD_ADD_v2i64(const SDValue &N) {
// Pattern: (add:v2i64 (NEONvshrs:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM), QPR:v2i64:$src1)
// Emits: (VSRAsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VSHRs) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VSHRs) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VSRAsv2i64, MVT::v2i64);
return Result;
}
@@ -12433,10 +12272,10 @@ SDNode *Select_ISD_ADD_v2i64(const SDValue &N) {
// Pattern: (add:v2i64 (NEONvshru:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM), QPR:v2i64:$src1)
// Emits: (VSRAuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VSHRu) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VSHRu) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VSRAuv2i64, MVT::v2i64);
return Result;
}
@@ -12445,10 +12284,10 @@ SDNode *Select_ISD_ADD_v2i64(const SDValue &N) {
// Pattern: (add:v2i64 (NEONvrshrs:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM), QPR:v2i64:$src1)
// Emits: (VRSRAsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VRSHRs) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VRSHRs) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VRSRAsv2i64, MVT::v2i64);
return Result;
}
@@ -12457,10 +12296,10 @@ SDNode *Select_ISD_ADD_v2i64(const SDValue &N) {
// Pattern: (add:v2i64 (NEONvrshru:v2i64 QPR:v2i64:$src2, (imm:i32):$SIMM), QPR:v2i64:$src1)
// Emits: (VRSRAuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2, (imm:i32):$SIMM)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VRSHRu) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ARMISD::VRSHRu) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_128(N, ARM::VRSRAuv2i64, MVT::v2i64);
return Result;
}
@@ -12478,121 +12317,121 @@ SDNode *Select_ISD_ADD_v2i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_141(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_141(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 4);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 4);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_142(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_142(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, N1, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 4);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 4);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_143(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_143(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 6);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_144(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_144(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 5);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 5);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_145(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_145(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { Tmp0, N0, Tmp2, Tmp3, Tmp4 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 5);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 5);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_146(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_146(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { Tmp0, N0, N1, Tmp3, Tmp4 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 5);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 5);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_147(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_147(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp3 = Transform_imm_neg_XFORM(Tmp2.getNode());
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { Tmp0, N0, Tmp3, Tmp4, Tmp5 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 5);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 5);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_148(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_148(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 6);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_149(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_149(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 5);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 5);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-SDNode *Select_ISD_ADDC_i32(const SDValue &N) {
+SDNode *Select_ISD_ADDC_i32(SDNode *N) {
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (addc:i32 GPR:i32:$a, so_reg:i32:$b)
// Emits: (ADDSrs:i32 GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 15 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -12614,13 +12453,13 @@ SDNode *Select_ISD_ADDC_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (addc:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Emits: (t2ADDSrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -12644,9 +12483,9 @@ SDNode *Select_ISD_ADDC_i32(const SDValue &N) {
// Emits: (ADDSri:i32 GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 7 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N1.getNode())) {
SDNode *Result = Emit_141(N, ARM::ADDSri, MVT::i32);
return Result;
@@ -12657,18 +12496,18 @@ SDNode *Select_ISD_ADDC_i32(const SDValue &N) {
// Emits: (t2ADDSri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 7 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_t2_so_imm(N1.getNode())) {
SDNode *Result = Emit_141(N, ARM::t2ADDSri, MVT::i32);
return Result;
}
}
if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (addc:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_7>>:$rhs)
// Emits: (tADDi3:i32 tGPR:i32:$lhs, (imm:i32)<<P:Predicate_imm0_7>>:$rhs)
@@ -12732,165 +12571,165 @@ SDNode *Select_ISD_ADDC_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_150(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_150(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag = N.getOperand(2);
+ SDValue InFlag = N->getOperand(2);
SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3, Tmp4, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 6);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_151(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_151(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag = N.getOperand(2);
+ SDValue InFlag = N->getOperand(2);
SDValue Ops0[] = { N0, N1, Tmp2, Tmp3, Tmp4, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 6);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_152(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_152(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag = N.getOperand(2);
+ SDValue InFlag = N->getOperand(2);
SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp2, Tmp3, Tmp4, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 8);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_153(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_153(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue InFlag = N.getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, Tmp1, InFlag);
+ SDValue InFlag = N->getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, Tmp1, InFlag);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_154(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue InFlag = N.getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, N1, InFlag);
+DISABLE_INLINE SDNode *Emit_154(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue InFlag = N->getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, N1, InFlag);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_155(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue InFlag = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_155(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue InFlag = N->getOperand(2);
SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 5);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 5);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_156(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_156(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag = N.getOperand(2);
+ SDValue InFlag = N->getOperand(2);
SDValue Ops0[] = { Tmp0, N0, N1, Tmp3, Tmp4, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 6);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_157(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_157(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag = N.getOperand(2);
+ SDValue InFlag = N->getOperand(2);
SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, Tmp2, Tmp3, Tmp4, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 7);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_158(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue InFlag = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_158(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue InFlag = N->getOperand(2);
SDValue Ops0[] = { N0, CPTmpN1_0, CPTmpN1_1, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 4);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 4);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_159(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_159(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag = N.getOperand(2);
+ SDValue InFlag = N->getOperand(2);
SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2, Tmp2, Tmp3, Tmp4, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 8);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_160(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue InFlag = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_160(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue InFlag = N->getOperand(2);
SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 5);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 5);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_161(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_161(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag = N.getOperand(2);
+ SDValue InFlag = N->getOperand(2);
SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, Tmp2, Tmp3, Tmp4, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 7);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_162(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue InFlag = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_162(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue InFlag = N->getOperand(2);
SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 4);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 4);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
+SDNode *Select_ISD_ADDE_i32(SDNode *N) {
// Pattern: (adde:i32 GPR:i32:$a, so_reg:i32:$b)
// Emits: (ADCrs:i32 GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 15 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (!N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ if ((!Subtarget->isThumb()) && (!N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -12903,9 +12742,9 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
// Pattern: (adde:i32 GPR:i32:$a, so_reg:i32:$b)
// Emits: (ADCSSrs:i32 GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 15 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ if ((!Subtarget->isThumb()) && (N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -12918,8 +12757,8 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
// Pattern: (adde:i32 so_reg:i32:$b, GPR:i32:$a)
// Emits: (ADCrs:i32 GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 15 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (!N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
+ if ((!Subtarget->isThumb()) && (!N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
SDValue CPTmpN0_0;
SDValue CPTmpN0_1;
SDValue CPTmpN0_2;
@@ -12932,8 +12771,8 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
// Pattern: (adde:i32 so_reg:i32:$b, GPR:i32:$a)
// Emits: (ADCSSrs:i32 GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 15 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
+ if ((!Subtarget->isThumb()) && (N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
SDValue CPTmpN0_0;
SDValue CPTmpN0_1;
SDValue CPTmpN0_2;
@@ -12946,9 +12785,9 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
// Pattern: (adde:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Emits: (t2ADCrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 12 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (!N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ if ((Subtarget->isThumb2()) && (!N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -12960,9 +12799,9 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
// Pattern: (adde:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Emits: (t2ADCSrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 12 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ if ((Subtarget->isThumb2()) && (N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -12974,8 +12813,8 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
// Pattern: (adde:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs)
// Emits: (t2ADCrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 12 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (!N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
+ if ((Subtarget->isThumb2()) && (!N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
SDValue CPTmpN0_0;
SDValue CPTmpN0_1;
if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
@@ -12987,8 +12826,8 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
// Pattern: (adde:i32 t2_so_reg:i32:$rhs, GPR:i32:$lhs)
// Emits: (t2ADCSrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 12 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
+ if ((Subtarget->isThumb2()) && (N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
SDValue CPTmpN0_0;
SDValue CPTmpN0_1;
if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
@@ -13000,10 +12839,10 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
// Pattern: (adde:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
// Emits: (ADCri:i32 GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 7 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (!N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ if ((!Subtarget->isThumb()) && (!N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N1.getNode())) {
SDNode *Result = Emit_150(N, ARM::ADCri, MVT::i32);
return Result;
@@ -13013,10 +12852,10 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
// Pattern: (adde:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
// Emits: (ADCSSri:i32 GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 7 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ if ((!Subtarget->isThumb()) && (N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N1.getNode())) {
SDNode *Result = Emit_153(N, ARM::ADCSSri, MVT::i32);
return Result;
@@ -13026,10 +12865,10 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
// Pattern: (adde:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
// Emits: (t2ADCri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (!N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ if ((Subtarget->isThumb2()) && (!N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_t2_so_imm(N1.getNode())) {
SDNode *Result = Emit_150(N, ARM::t2ADCri, MVT::i32);
return Result;
@@ -13039,10 +12878,10 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
// Pattern: (adde:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
// Emits: (t2ADCSri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ if ((Subtarget->isThumb2()) && (N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_t2_so_imm(N1.getNode())) {
SDNode *Result = Emit_153(N, ARM::t2ADCSri, MVT::i32);
return Result;
@@ -13052,7 +12891,7 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
// Pattern: (adde:i32 GPR:i32:$a, GPR:i32:$b)
// Emits: (ADCrr:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (!N.getNode()->hasAnyUseOfValue(1))) {
+ if ((!Subtarget->isThumb()) && (!N->hasAnyUseOfValue(1))) {
SDNode *Result = Emit_151(N, ARM::ADCrr, MVT::i32);
return Result;
}
@@ -13060,7 +12899,7 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
// Pattern: (adde:i32 GPR:i32:$a, GPR:i32:$b)
// Emits: (ADCSSrr:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (N.getNode()->hasAnyUseOfValue(1))) {
+ if ((!Subtarget->isThumb()) && (N->hasAnyUseOfValue(1))) {
SDNode *Result = Emit_154(N, ARM::ADCSSrr, MVT::i32);
return Result;
}
@@ -13076,7 +12915,7 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
// Pattern: (adde:i32 GPR:i32:$lhs, GPR:i32:$rhs)
// Emits: (t2ADCrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
// Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (!N.getNode()->hasAnyUseOfValue(1))) {
+ if ((Subtarget->isThumb2()) && (!N->hasAnyUseOfValue(1))) {
SDNode *Result = Emit_151(N, ARM::t2ADCrr, MVT::i32);
return Result;
}
@@ -13084,7 +12923,7 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
// Pattern: (adde:i32 GPR:i32:$lhs, GPR:i32:$rhs)
// Emits: (t2ADCSrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
// Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (N.getNode()->hasAnyUseOfValue(1))) {
+ if ((Subtarget->isThumb2()) && (N->hasAnyUseOfValue(1))) {
SDNode *Result = Emit_154(N, ARM::t2ADCSrr, MVT::i32);
return Result;
}
@@ -13093,219 +12932,219 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_163(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_163(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2, Tmp3);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_164(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+DISABLE_INLINE SDNode *Emit_164(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_165(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_165(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N10)->getZExtValue()), MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_166(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_166(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, N10, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_167(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN10_0, SDValue &CPTmpN10_1, SDValue &CPTmpN10_2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_167(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN10_0, SDValue &CPTmpN10_1, SDValue &CPTmpN10_2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, CPTmpN10_0, CPTmpN10_1, CPTmpN10_2, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 7);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 7);
}
-DISABLE_INLINE SDNode *Emit_168(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_168(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { Tmp0, N0, N10, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_169(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN10_0, SDValue &CPTmpN10_1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_169(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN10_0, SDValue &CPTmpN10_1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, CPTmpN10_0, CPTmpN10_1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
}
-DISABLE_INLINE SDNode *Emit_170(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+DISABLE_INLINE SDNode *Emit_170(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0x18ULL, MVT::i32);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_171(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+DISABLE_INLINE SDNode *Emit_171(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0x8ULL, MVT::i32);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_172(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_172(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_t2_so_imm_not_XFORM(Tmp1.getNode());
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_173(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_173(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_so_imm_not_XFORM(Tmp1.getNode());
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_174(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_174(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_175(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_175(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N00)->getZExtValue()), MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, Tmp1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_176(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_176(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, Tmp1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_177(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_177(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, N00, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_178(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN00_0, SDValue &CPTmpN00_1, SDValue &CPTmpN00_2) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_178(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN00_0, SDValue &CPTmpN00_1, SDValue &CPTmpN00_2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 7);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 7);
}
-DISABLE_INLINE SDNode *Emit_179(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_179(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { Tmp0, N1, N00, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_180(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN00_0, SDValue &CPTmpN00_1) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_180(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN00_0, SDValue &CPTmpN00_1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, CPTmpN00_0, CPTmpN00_1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
}
-SDNode *Select_ISD_AND_i32(const SDValue &N) {
+SDNode *Select_ISD_AND_i32(SDNode *N) {
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0 &&
CheckAndMask(N0, Tmp0, INT64_C(16711935))) {
// Pattern: (and:i32 (shl:i32 GPR:i32:$Src, 8:i32), 16711935:i32)
// Emits: (t2UXTB16r_rot:i32 GPR:i32:$Src, 24:i32)
// Pattern complexity = 32 cost = 1 size = 0
- if (N0.getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01);
+ if (N0.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8) &&
@@ -13319,10 +13158,10 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Pattern: (and:i32 (srl:i32 GPR:i32:$Src, 8:i32), 16711935:i32)
// Emits: (t2UXTB16r_rot:i32 GPR:i32:$Src, 8:i32)
// Pattern complexity = 32 cost = 1 size = 0
- if (N0.getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01);
+ if (N0.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8) &&
@@ -13335,19 +13174,19 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
if (CheckAndMask(N0, Tmp0, INT64_C(16711935))) {
// Pattern: (and:i32 (shl:i32 GPR:i32:$Src, 8:i32), 16711935:i32)
// Emits: (UXTB16r_rot:i32 GPR:i32:$Src, 24:i32)
// Pattern complexity = 32 cost = 1 size = 0
- if (N0.getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01);
+ if (N0.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8) &&
@@ -13361,10 +13200,10 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Pattern: (and:i32 (srl:i32 GPR:i32:$Src, 8:i32), 16711935:i32)
// Emits: (UXTB16r_rot:i32 GPR:i32:$Src, 8:i32)
// Pattern complexity = 32 cost = 1 size = 0
- if (N0.getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01);
+ if (N0.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8) &&
@@ -13380,10 +13219,10 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (UXTBr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
// Pattern complexity = 31 cost = 1 size = 0
if (CheckAndMask(N0, Tmp0, INT64_C(255)) &&
- N0.getOpcode() == ISD::ROTR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ N0.getNode()->getOpcode() == ISD::ROTR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_rot_imm(N01.getNode()) &&
N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_164(N, ARM::UXTBr_rot, MVT::i32);
@@ -13395,10 +13234,10 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (UXTHr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
// Pattern complexity = 31 cost = 1 size = 0
if (CheckAndMask(N0, Tmp0, INT64_C(65535)) &&
- N0.getOpcode() == ISD::ROTR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ N0.getNode()->getOpcode() == ISD::ROTR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_rot_imm(N01.getNode()) &&
N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_164(N, ARM::UXTHr_rot, MVT::i32);
@@ -13410,10 +13249,10 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (UXTB16r_rot:i32 GPR:i32:$src, (imm:i32):$rot)
// Pattern complexity = 31 cost = 1 size = 0
if (CheckAndMask(N0, Tmp0, INT64_C(16711935)) &&
- N0.getOpcode() == ISD::ROTR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ N0.getNode()->getOpcode() == ISD::ROTR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_rot_imm(N01.getNode()) &&
N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_164(N, ARM::UXTB16r_rot, MVT::i32);
@@ -13423,19 +13262,19 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
// Pattern: (and:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), 255:i32)
// Emits: (t2UXTBr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
// Pattern complexity = 31 cost = 1 size = 0
if (CheckAndMask(N0, Tmp0, INT64_C(255)) &&
- N0.getOpcode() == ISD::ROTR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ N0.getNode()->getOpcode() == ISD::ROTR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_rot_imm(N01.getNode()) &&
N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_164(N, ARM::t2UXTBr_rot, MVT::i32);
@@ -13447,10 +13286,10 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (t2UXTHr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
// Pattern complexity = 31 cost = 1 size = 0
if (CheckAndMask(N0, Tmp0, INT64_C(65535)) &&
- N0.getOpcode() == ISD::ROTR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ N0.getNode()->getOpcode() == ISD::ROTR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_rot_imm(N01.getNode()) &&
N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_164(N, ARM::t2UXTHr_rot, MVT::i32);
@@ -13462,10 +13301,10 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (t2UXTB16r_rot:i32 GPR:i32:$src, (imm:i32):$rot)
// Pattern complexity = 31 cost = 1 size = 0
if (CheckAndMask(N0, Tmp0, INT64_C(16711935)) &&
- N0.getOpcode() == ISD::ROTR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ N0.getNode()->getOpcode() == ISD::ROTR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_rot_imm(N01.getNode()) &&
N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_164(N, ARM::t2UXTB16r_rot, MVT::i32);
@@ -13475,9 +13314,9 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
// Pattern: (and:i32 GPR:i32:$src, 255:i32)
@@ -13506,9 +13345,9 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
// Pattern: (and:i32 GPR:i32:$src, 255:i32)
@@ -13537,21 +13376,21 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (and:i32 GPR:i32:$a, (xor:i32 so_reg:i32:$b, (imm:i32)<<P:Predicate_immAllOnes>>))
// Emits: (BICrs:i32 GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 22 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
SDValue CPTmpN10_0;
SDValue CPTmpN10_1;
SDValue CPTmpN10_2;
if (SelectShifterOperandReg(N, N10, CPTmpN10_0, CPTmpN10_1, CPTmpN10_2)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N11.getNode())) {
SDNode *Result = Emit_167(N, ARM::BICrs, MVT::i32, CPTmpN10_0, CPTmpN10_1, CPTmpN10_2);
return Result;
@@ -13563,14 +13402,14 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Pattern: (and:i32 (xor:i32 so_reg:i32:$b, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$a)
// Emits: (BICrs:i32 GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 22 cost = 1 size = 0
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
SDValue CPTmpN00_0;
SDValue CPTmpN00_1;
SDValue CPTmpN00_2;
if (SelectShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N01.getNode())) {
SDNode *Result = Emit_178(N, ARM::BICrs, MVT::i32, CPTmpN00_0, CPTmpN00_1, CPTmpN00_2);
return Result;
@@ -13579,20 +13418,20 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (and:i32 GPR:i32:$lhs, (xor:i32 t2_so_reg:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>))
// Emits: (t2BICrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 19 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
SDValue CPTmpN10_0;
SDValue CPTmpN10_1;
if (SelectT2ShifterOperandReg(N, N10, CPTmpN10_0, CPTmpN10_1)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N11.getNode())) {
SDNode *Result = Emit_169(N, ARM::t2BICrs, MVT::i32, CPTmpN10_0, CPTmpN10_1);
return Result;
@@ -13604,13 +13443,13 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Pattern: (and:i32 (xor:i32 t2_so_reg:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$lhs)
// Emits: (t2BICrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 19 cost = 1 size = 0
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
SDValue CPTmpN00_0;
SDValue CPTmpN00_1;
if (SelectT2ShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N01.getNode())) {
SDNode *Result = Emit_180(N, ARM::t2BICrs, MVT::i32, CPTmpN00_0, CPTmpN00_1);
return Result;
@@ -13619,13 +13458,13 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (and:i32 GPR:i32:$a, so_reg:i32:$b)
// Emits: (ANDrs:i32 GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 15 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -13651,13 +13490,13 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Pattern: (and:i32 GPR:i32:$a, (xor:i32 (imm:i32)<<P:Predicate_so_imm>>:$b, (imm:i32)<<P:Predicate_immAllOnes>>))
// Emits: (BICri:i32 GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 14 cost = 1 size = 0
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N10.getNode())) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N11.getNode())) {
SDNode *Result = Emit_165(N, ARM::BICri, MVT::i32);
return Result;
@@ -13670,14 +13509,14 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (t2BICri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 14 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::Constant &&
Predicate_t2_so_imm(N10.getNode())) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N11.getNode())) {
SDNode *Result = Emit_165(N, ARM::t2BICri, MVT::i32);
return Result;
@@ -13686,19 +13525,19 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (and:i32 GPR:i32:$a, (xor:i32 (imm:i32)<<P:Predicate_immAllOnes>>, (imm:i32)<<P:Predicate_so_imm>>:$b))
// Emits: (BICri:i32 GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 14 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N10.getNode())) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N11.getNode())) {
SDNode *Result = Emit_174(N, ARM::BICri, MVT::i32);
return Result;
@@ -13706,16 +13545,16 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (and:i32 (xor:i32 (imm:i32)<<P:Predicate_so_imm>>:$b, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$a)
// Emits: (BICri:i32 GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 14 cost = 1 size = 0
if (Predicate_so_imm(N00.getNode())) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N01.getNode())) {
SDNode *Result = Emit_175(N, ARM::BICri, MVT::i32);
return Result;
@@ -13726,8 +13565,8 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (BICri:i32 GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 14 cost = 1 size = 0
if (Predicate_immAllOnes(N00.getNode())) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N01.getNode())) {
SDNode *Result = Emit_176(N, ARM::BICri, MVT::i32);
return Result;
@@ -13737,19 +13576,19 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (and:i32 GPR:i32:$lhs, (xor:i32 (imm:i32)<<P:Predicate_immAllOnes>>, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs))
// Emits: (t2BICri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 14 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N10.getNode())) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_t2_so_imm(N11.getNode())) {
SDNode *Result = Emit_174(N, ARM::t2BICri, MVT::i32);
return Result;
@@ -13757,16 +13596,16 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (and:i32 (xor:i32 (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$lhs)
// Emits: (t2BICri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 14 cost = 1 size = 0
if (Predicate_t2_so_imm(N00.getNode())) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N01.getNode())) {
SDNode *Result = Emit_175(N, ARM::t2BICri, MVT::i32);
return Result;
@@ -13777,8 +13616,8 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (t2BICri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 14 cost = 1 size = 0
if (Predicate_immAllOnes(N00.getNode())) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_t2_so_imm(N01.getNode())) {
SDNode *Result = Emit_176(N, ARM::t2BICri, MVT::i32);
return Result;
@@ -13791,7 +13630,7 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (t2ANDrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -13815,12 +13654,12 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (BICrr:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 10 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N11.getNode())) {
SDNode *Result = Emit_166(N, ARM::BICrr, MVT::i32);
return Result;
@@ -13832,12 +13671,12 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (tBIC:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
// Pattern complexity = 10 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N11.getNode())) {
SDNode *Result = Emit_168(N, ARM::tBIC, MVT::i32);
return Result;
@@ -13849,12 +13688,12 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (t2BICrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
// Pattern complexity = 10 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N11.getNode())) {
SDNode *Result = Emit_166(N, ARM::t2BICrr, MVT::i32);
return Result;
@@ -13866,11 +13705,11 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (BICrr:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 10 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N01.getNode())) {
SDNode *Result = Emit_177(N, ARM::BICrr, MVT::i32);
return Result;
@@ -13882,11 +13721,11 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (tBIC:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
// Pattern complexity = 10 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N01.getNode())) {
SDNode *Result = Emit_179(N, ARM::tBIC, MVT::i32);
return Result;
@@ -13898,11 +13737,11 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (t2BICrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
// Pattern complexity = 10 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N01.getNode())) {
SDNode *Result = Emit_177(N, ARM::t2BICrr, MVT::i32);
return Result;
@@ -13910,9 +13749,9 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
// Pattern: (and:i32 tGPR:i32:$src, 255:i32)
@@ -13937,9 +13776,9 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (ANDri:i32 GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 7 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N1.getNode())) {
SDNode *Result = Emit_55(N, ARM::ANDri, MVT::i32);
return Result;
@@ -13950,18 +13789,18 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (BFC:i32 GPR:i32:$src, (imm:i32):$imm)
// Pattern complexity = 7 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_bf_inv_mask_imm(N1.getNode())) {
SDNode *Result = Emit_35(N, ARM::BFC, MVT::i32);
return Result;
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (and:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
// Emits: (t2ANDri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
@@ -13994,9 +13833,9 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (BICri:i32 GPR:i32:$src, (so_imm_not_XFORM:i32 (imm:i32)<<P:Predicate_so_imm_not>>:$imm))
// Pattern complexity = 7 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm_not(N1.getNode())) {
SDNode *Result = Emit_173(N, ARM::BICri, MVT::i32);
return Result;
@@ -14030,41 +13869,41 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_181(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_181(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, N11, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_182(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_182(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, N01, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-SDNode *Select_ISD_AND_v2i32(const SDValue &N) {
+SDNode *Select_ISD_AND_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v2i32 DPR:v2i32:$src1, (xor:v2i32 DPR:v2i32:$src2, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>))
// Emits: (VBICd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 10 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N11.getNode())) {
SDNode *Result = Emit_51(N, ARM::VBICd, MVT::v2i32);
return Result;
@@ -14074,22 +13913,22 @@ SDNode *Select_ISD_AND_v2i32(const SDValue &N) {
// Pattern: (and:v2i32 DPR:v2i32:$src1, (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src2))
// Emits: (VBICd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 10 cost = 1 size = 0
- if (N10.getOpcode() == ISD::BIT_CONVERT &&
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N10.getNode())) {
SDNode *Result = Emit_181(N, ARM::VBICd, MVT::v2i32);
return Result;
}
}
}
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (and:v2i32 (xor:v2i32 DPR:v2i32:$src2, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>), DPR:v2i32:$src1)
// Emits: (VBICd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 10 cost = 1 size = 0
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N01.getNode())) {
SDNode *Result = Emit_84(N, ARM::VBICd, MVT::v2i32);
return Result;
@@ -14099,7 +13938,7 @@ SDNode *Select_ISD_AND_v2i32(const SDValue &N) {
// Pattern: (and:v2i32 (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src2), DPR:v2i32:$src1)
// Emits: (VBICd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 10 cost = 1 size = 0
- if (N00.getOpcode() == ISD::BIT_CONVERT &&
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N00.getNode())) {
SDNode *Result = Emit_182(N, ARM::VBICd, MVT::v2i32);
return Result;
@@ -14118,21 +13957,21 @@ SDNode *Select_ISD_AND_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_AND_v4i32(const SDValue &N) {
+SDNode *Select_ISD_AND_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v4i32 QPR:v4i32:$src1, (xor:v4i32 QPR:v4i32:$src2, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>))
// Emits: (VBICq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 10 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N11.getNode())) {
SDNode *Result = Emit_51(N, ARM::VBICq, MVT::v4i32);
return Result;
@@ -14142,22 +13981,22 @@ SDNode *Select_ISD_AND_v4i32(const SDValue &N) {
// Pattern: (and:v4i32 QPR:v4i32:$src1, (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src2))
// Emits: (VBICq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 10 cost = 1 size = 0
- if (N10.getOpcode() == ISD::BIT_CONVERT &&
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N10.getNode())) {
SDNode *Result = Emit_181(N, ARM::VBICq, MVT::v4i32);
return Result;
}
}
}
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (and:v4i32 (xor:v4i32 QPR:v4i32:$src2, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>), QPR:v4i32:$src1)
// Emits: (VBICq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 10 cost = 1 size = 0
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N01.getNode())) {
SDNode *Result = Emit_84(N, ARM::VBICq, MVT::v4i32);
return Result;
@@ -14167,7 +14006,7 @@ SDNode *Select_ISD_AND_v4i32(const SDValue &N) {
// Pattern: (and:v4i32 (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src2), QPR:v4i32:$src1)
// Emits: (VBICq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 10 cost = 1 size = 0
- if (N00.getOpcode() == ISD::BIT_CONVERT &&
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N00.getNode())) {
SDNode *Result = Emit_182(N, ARM::VBICq, MVT::v4i32);
return Result;
@@ -14186,28 +14025,28 @@ SDNode *Select_ISD_AND_v4i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_183(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_183(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { N1, N2, N3, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 4);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 4);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-SDNode *Select_ISD_ATOMIC_CMP_SWAP_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
+SDNode *Select_ISD_ATOMIC_CMP_SWAP_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
// Pattern: (atomic_cmp_swap:i32 GPR:i32:$ptr, GPR:i32:$old, GPR:i32:$new)<<P:Predicate_atomic_cmp_swap_8>>
// Emits: (ATOMIC_CMP_SWAP_I8:i32 GPR:i32:$ptr, GPR:i32:$old, GPR:i32:$new)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_cmp_swap_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_atomic_cmp_swap_8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_183(N, ARM::ATOMIC_CMP_SWAP_I8, MVT::i32);
return Result;
@@ -14217,10 +14056,10 @@ SDNode *Select_ISD_ATOMIC_CMP_SWAP_i32(const SDValue &N) {
// Pattern: (atomic_cmp_swap:i32 GPR:i32:$ptr, GPR:i32:$old, GPR:i32:$new)<<P:Predicate_atomic_cmp_swap_16>>
// Emits: (ATOMIC_CMP_SWAP_I16:i32 GPR:i32:$ptr, GPR:i32:$old, GPR:i32:$new)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_cmp_swap_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_atomic_cmp_swap_16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_183(N, ARM::ATOMIC_CMP_SWAP_I16, MVT::i32);
return Result;
@@ -14230,10 +14069,10 @@ SDNode *Select_ISD_ATOMIC_CMP_SWAP_i32(const SDValue &N) {
// Pattern: (atomic_cmp_swap:i32 GPR:i32:$ptr, GPR:i32:$old, GPR:i32:$new)<<P:Predicate_atomic_cmp_swap_32>>
// Emits: (ATOMIC_CMP_SWAP_I32:i32 GPR:i32:$ptr, GPR:i32:$old, GPR:i32:$new)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_cmp_swap_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_atomic_cmp_swap_32(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_183(N, ARM::ATOMIC_CMP_SWAP_I32, MVT::i32);
return Result;
@@ -14244,25 +14083,25 @@ SDNode *Select_ISD_ATOMIC_CMP_SWAP_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_184(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_184(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, N1, N2, Chain);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, N1, N2, Chain);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-SDNode *Select_ISD_ATOMIC_LOAD_ADD_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
+SDNode *Select_ISD_ATOMIC_LOAD_ADD_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
// Pattern: (atomic_load_add:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_add_8>>
// Emits: (ATOMIC_LOAD_ADD_I8:i32 GPR:i32:$ptr, GPR:i32:$incr)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_add_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_load_add_8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_ADD_I8, MVT::i32);
return Result;
@@ -14272,9 +14111,9 @@ SDNode *Select_ISD_ATOMIC_LOAD_ADD_i32(const SDValue &N) {
// Pattern: (atomic_load_add:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_add_16>>
// Emits: (ATOMIC_LOAD_ADD_I16:i32 GPR:i32:$ptr, GPR:i32:$incr)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_add_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_load_add_16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_ADD_I16, MVT::i32);
return Result;
@@ -14284,9 +14123,9 @@ SDNode *Select_ISD_ATOMIC_LOAD_ADD_i32(const SDValue &N) {
// Pattern: (atomic_load_add:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_add_32>>
// Emits: (ATOMIC_LOAD_ADD_I32:i32 GPR:i32:$ptr, GPR:i32:$incr)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_add_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_load_add_32(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_ADD_I32, MVT::i32);
return Result;
@@ -14297,15 +14136,15 @@ SDNode *Select_ISD_ATOMIC_LOAD_ADD_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_AND_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
+SDNode *Select_ISD_ATOMIC_LOAD_AND_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
// Pattern: (atomic_load_and:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_and_8>>
// Emits: (ATOMIC_LOAD_AND_I8:i32 GPR:i32:$ptr, GPR:i32:$incr)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_and_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_load_and_8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_AND_I8, MVT::i32);
return Result;
@@ -14315,9 +14154,9 @@ SDNode *Select_ISD_ATOMIC_LOAD_AND_i32(const SDValue &N) {
// Pattern: (atomic_load_and:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_and_16>>
// Emits: (ATOMIC_LOAD_AND_I16:i32 GPR:i32:$ptr, GPR:i32:$incr)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_and_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_load_and_16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_AND_I16, MVT::i32);
return Result;
@@ -14327,9 +14166,9 @@ SDNode *Select_ISD_ATOMIC_LOAD_AND_i32(const SDValue &N) {
// Pattern: (atomic_load_and:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_and_32>>
// Emits: (ATOMIC_LOAD_AND_I32:i32 GPR:i32:$ptr, GPR:i32:$incr)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_and_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_load_and_32(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_AND_I32, MVT::i32);
return Result;
@@ -14340,15 +14179,15 @@ SDNode *Select_ISD_ATOMIC_LOAD_AND_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_NAND_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
+SDNode *Select_ISD_ATOMIC_LOAD_NAND_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
// Pattern: (atomic_load_nand:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_nand_8>>
// Emits: (ATOMIC_LOAD_NAND_I8:i32 GPR:i32:$ptr, GPR:i32:$incr)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_nand_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_load_nand_8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_NAND_I8, MVT::i32);
return Result;
@@ -14358,9 +14197,9 @@ SDNode *Select_ISD_ATOMIC_LOAD_NAND_i32(const SDValue &N) {
// Pattern: (atomic_load_nand:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_nand_16>>
// Emits: (ATOMIC_LOAD_NAND_I16:i32 GPR:i32:$ptr, GPR:i32:$incr)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_nand_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_load_nand_16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_NAND_I16, MVT::i32);
return Result;
@@ -14370,9 +14209,9 @@ SDNode *Select_ISD_ATOMIC_LOAD_NAND_i32(const SDValue &N) {
// Pattern: (atomic_load_nand:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_nand_32>>
// Emits: (ATOMIC_LOAD_NAND_I32:i32 GPR:i32:$ptr, GPR:i32:$incr)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_nand_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_load_nand_32(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_NAND_I32, MVT::i32);
return Result;
@@ -14383,15 +14222,15 @@ SDNode *Select_ISD_ATOMIC_LOAD_NAND_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_OR_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
+SDNode *Select_ISD_ATOMIC_LOAD_OR_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
// Pattern: (atomic_load_or:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_or_8>>
// Emits: (ATOMIC_LOAD_OR_I8:i32 GPR:i32:$ptr, GPR:i32:$incr)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_or_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_load_or_8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_OR_I8, MVT::i32);
return Result;
@@ -14401,9 +14240,9 @@ SDNode *Select_ISD_ATOMIC_LOAD_OR_i32(const SDValue &N) {
// Pattern: (atomic_load_or:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_or_16>>
// Emits: (ATOMIC_LOAD_OR_I16:i32 GPR:i32:$ptr, GPR:i32:$incr)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_or_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_load_or_16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_OR_I16, MVT::i32);
return Result;
@@ -14413,9 +14252,9 @@ SDNode *Select_ISD_ATOMIC_LOAD_OR_i32(const SDValue &N) {
// Pattern: (atomic_load_or:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_or_32>>
// Emits: (ATOMIC_LOAD_OR_I32:i32 GPR:i32:$ptr, GPR:i32:$incr)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_or_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_load_or_32(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_OR_I32, MVT::i32);
return Result;
@@ -14426,15 +14265,15 @@ SDNode *Select_ISD_ATOMIC_LOAD_OR_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_SUB_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
+SDNode *Select_ISD_ATOMIC_LOAD_SUB_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
// Pattern: (atomic_load_sub:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_sub_8>>
// Emits: (ATOMIC_LOAD_SUB_I8:i32 GPR:i32:$ptr, GPR:i32:$incr)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_sub_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_load_sub_8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_SUB_I8, MVT::i32);
return Result;
@@ -14444,9 +14283,9 @@ SDNode *Select_ISD_ATOMIC_LOAD_SUB_i32(const SDValue &N) {
// Pattern: (atomic_load_sub:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_sub_16>>
// Emits: (ATOMIC_LOAD_SUB_I16:i32 GPR:i32:$ptr, GPR:i32:$incr)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_sub_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_load_sub_16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_SUB_I16, MVT::i32);
return Result;
@@ -14456,9 +14295,9 @@ SDNode *Select_ISD_ATOMIC_LOAD_SUB_i32(const SDValue &N) {
// Pattern: (atomic_load_sub:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_sub_32>>
// Emits: (ATOMIC_LOAD_SUB_I32:i32 GPR:i32:$ptr, GPR:i32:$incr)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_sub_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_load_sub_32(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_SUB_I32, MVT::i32);
return Result;
@@ -14469,15 +14308,15 @@ SDNode *Select_ISD_ATOMIC_LOAD_SUB_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_XOR_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
+SDNode *Select_ISD_ATOMIC_LOAD_XOR_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
// Pattern: (atomic_load_xor:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_xor_8>>
// Emits: (ATOMIC_LOAD_XOR_I8:i32 GPR:i32:$ptr, GPR:i32:$incr)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_xor_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_load_xor_8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_XOR_I8, MVT::i32);
return Result;
@@ -14487,9 +14326,9 @@ SDNode *Select_ISD_ATOMIC_LOAD_XOR_i32(const SDValue &N) {
// Pattern: (atomic_load_xor:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_xor_16>>
// Emits: (ATOMIC_LOAD_XOR_I16:i32 GPR:i32:$ptr, GPR:i32:$incr)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_xor_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_load_xor_16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_XOR_I16, MVT::i32);
return Result;
@@ -14499,9 +14338,9 @@ SDNode *Select_ISD_ATOMIC_LOAD_XOR_i32(const SDValue &N) {
// Pattern: (atomic_load_xor:i32 GPR:i32:$ptr, GPR:i32:$incr)<<P:Predicate_atomic_load_xor_32>>
// Emits: (ATOMIC_LOAD_XOR_I32:i32 GPR:i32:$ptr, GPR:i32:$incr)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_load_xor_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_load_xor_32(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_LOAD_XOR_I32, MVT::i32);
return Result;
@@ -14512,15 +14351,15 @@ SDNode *Select_ISD_ATOMIC_LOAD_XOR_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_SWAP_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
+SDNode *Select_ISD_ATOMIC_SWAP_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
// Pattern: (atomic_swap:i32 GPR:i32:$ptr, GPR:i32:$new)<<P:Predicate_atomic_swap_8>>
// Emits: (ATOMIC_SWAP_I8:i32 GPR:i32:$ptr, GPR:i32:$new)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_swap_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_swap_8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_SWAP_I8, MVT::i32);
return Result;
@@ -14530,9 +14369,9 @@ SDNode *Select_ISD_ATOMIC_SWAP_i32(const SDValue &N) {
// Pattern: (atomic_swap:i32 GPR:i32:$ptr, GPR:i32:$new)<<P:Predicate_atomic_swap_16>>
// Emits: (ATOMIC_SWAP_I16:i32 GPR:i32:$ptr, GPR:i32:$new)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_swap_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_swap_16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_SWAP_I16, MVT::i32);
return Result;
@@ -14542,9 +14381,9 @@ SDNode *Select_ISD_ATOMIC_SWAP_i32(const SDValue &N) {
// Pattern: (atomic_swap:i32 GPR:i32:$ptr, GPR:i32:$new)<<P:Predicate_atomic_swap_32>>
// Emits: (ATOMIC_SWAP_I32:i32 GPR:i32:$ptr, GPR:i32:$new)
// Pattern complexity = 4 cost = 11 size = 0
- if (Predicate_atomic_swap_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_atomic_swap_32(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_184(N, ARM::ATOMIC_SWAP_I32, MVT::i32);
return Result;
@@ -14555,9 +14394,9 @@ SDNode *Select_ISD_ATOMIC_SWAP_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_i32(const SDValue &N) {
+SDNode *Select_ISD_BIT_CONVERT_i32(SDNode *N) {
if ((Subtarget->hasVFP2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
SDNode *Result = Emit_31(N, ARM::VMOVRS, MVT::i32);
return Result;
@@ -14568,9 +14407,9 @@ SDNode *Select_ISD_BIT_CONVERT_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_f32(const SDValue &N) {
+SDNode *Select_ISD_BIT_CONVERT_f32(SDNode *N) {
if ((Subtarget->hasVFP2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_31(N, ARM::VMOVSR, MVT::f32);
return Result;
@@ -14581,13 +14420,13 @@ SDNode *Select_ISD_BIT_CONVERT_f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_185(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- ReplaceUses(N, N0);
+DISABLE_INLINE SDNode *Emit_185(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ ReplaceUses(SDValue(N, 0), N0);
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_f64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_BIT_CONVERT_f64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:f64 DPR:v1i64:$src)
// Emits: DPR:f64:$src
@@ -14633,8 +14472,8 @@ SDNode *Select_ISD_BIT_CONVERT_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v8i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_BIT_CONVERT_v8i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v8i8 DPR:v1i64:$src)
// Emits: DPR:v8i8:$src
@@ -14680,8 +14519,8 @@ SDNode *Select_ISD_BIT_CONVERT_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v16i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_BIT_CONVERT_v16i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v16i8 QPR:v2i64:$src)
// Emits: QPR:v16i8:$src
@@ -14727,8 +14566,8 @@ SDNode *Select_ISD_BIT_CONVERT_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v4i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_BIT_CONVERT_v4i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v4i16 DPR:v1i64:$src)
// Emits: DPR:v4i16:$src
@@ -14774,8 +14613,8 @@ SDNode *Select_ISD_BIT_CONVERT_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v8i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_BIT_CONVERT_v8i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v8i16 QPR:v2i64:$src)
// Emits: QPR:v8i16:$src
@@ -14821,8 +14660,8 @@ SDNode *Select_ISD_BIT_CONVERT_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v2i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_BIT_CONVERT_v2i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v2i32 DPR:v1i64:$src)
// Emits: DPR:v2i32:$src
@@ -14868,8 +14707,8 @@ SDNode *Select_ISD_BIT_CONVERT_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v4i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_BIT_CONVERT_v4i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v4i32 QPR:v2i64:$src)
// Emits: QPR:v4i32:$src
@@ -14915,8 +14754,8 @@ SDNode *Select_ISD_BIT_CONVERT_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v1i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_BIT_CONVERT_v1i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v1i64 DPR:v2i32:$src)
// Emits: DPR:v1i64:$src
@@ -14962,8 +14801,8 @@ SDNode *Select_ISD_BIT_CONVERT_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v2i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_BIT_CONVERT_v2i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v2i64 QPR:v4i32:$src)
// Emits: QPR:v2i64:$src
@@ -15009,8 +14848,8 @@ SDNode *Select_ISD_BIT_CONVERT_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v2f32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_BIT_CONVERT_v2f32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v2f32 DPR:f64:$src)
// Emits: DPR:v2f32:$src
@@ -15056,8 +14895,8 @@ SDNode *Select_ISD_BIT_CONVERT_v2f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v4f32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_BIT_CONVERT_v4f32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v4f32 QPR:v2i64:$src)
// Emits: QPR:v4f32:$src
@@ -15103,8 +14942,8 @@ SDNode *Select_ISD_BIT_CONVERT_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v2f64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_BIT_CONVERT_v2f64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v2f64 QPR:v2i64:$src)
// Emits: QPR:v2f64:$src
@@ -15150,15 +14989,15 @@ SDNode *Select_ISD_BIT_CONVERT_v2f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BR(const SDValue &N) {
+SDNode *Select_ISD_BR(SDNode *N) {
// Pattern: (br:isVoid (bb:Other):$target)
// Emits: (B:isVoid (bb:Other):$target)
// Pattern complexity = 3 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BasicBlock) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BasicBlock) {
SDNode *Result = Emit_34(N, ARM::B);
return Result;
}
@@ -15168,9 +15007,9 @@ SDNode *Select_ISD_BR(const SDValue &N) {
// Emits: (tB:isVoid (bb:Other):$target)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BasicBlock) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BasicBlock) {
SDNode *Result = Emit_34(N, ARM::tB);
return Result;
}
@@ -15180,9 +15019,9 @@ SDNode *Select_ISD_BR(const SDValue &N) {
// Emits: (t2B:isVoid (bb:Other):$target)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BasicBlock) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BasicBlock) {
SDNode *Result = Emit_34(N, ARM::t2B);
return Result;
}
@@ -15192,14 +15031,14 @@ SDNode *Select_ISD_BR(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BRIND(const SDValue &N) {
+SDNode *Select_ISD_BRIND(SDNode *N) {
// Pattern: (brind:isVoid GPR:i32:$dst)
// Emits: (BRIND:isVoid GPR:i32:$dst)
// Pattern complexity = 3 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_34(N, ARM::BRIND);
return Result;
@@ -15210,8 +15049,8 @@ SDNode *Select_ISD_BRIND(const SDValue &N) {
// Emits: (tBRIND:isVoid GPR:i32:$dst)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_34(N, ARM::tBRIND);
return Result;
@@ -15222,7 +15061,7 @@ SDNode *Select_ISD_BRIND(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BSWAP_i32(const SDValue &N) {
+SDNode *Select_ISD_BSWAP_i32(SDNode *N) {
// Pattern: (bswap:i32 GPR:i32:$src)
// Emits: (REV:i32 GPR:i32:$src)
@@ -15252,15 +15091,15 @@ SDNode *Select_ISD_BSWAP_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_186(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp1 = Transform_VMOV_get_imm8(N.getNode());
+DISABLE_INLINE SDNode *Emit_186(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp1 = Transform_VMOV_get_imm8(SDValue(N, 0).getNode());
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1, Tmp2, Tmp3);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1, Tmp2, Tmp3);
}
-SDNode *Select_ISD_BUILD_VECTOR_v8i8(const SDValue &N) {
+SDNode *Select_ISD_BUILD_VECTOR_v8i8(SDNode *N) {
if ((Subtarget->hasNEON()) &&
- Predicate_vmovImm8(N.getNode())) {
+ Predicate_vmovImm8(N)) {
SDNode *Result = Emit_186(N, ARM::VMOVv8i8, MVT::v8i8);
return Result;
}
@@ -15269,9 +15108,9 @@ SDNode *Select_ISD_BUILD_VECTOR_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BUILD_VECTOR_v16i8(const SDValue &N) {
+SDNode *Select_ISD_BUILD_VECTOR_v16i8(SDNode *N) {
if ((Subtarget->hasNEON()) &&
- Predicate_vmovImm8(N.getNode())) {
+ Predicate_vmovImm8(N)) {
SDNode *Result = Emit_186(N, ARM::VMOVv16i8, MVT::v16i8);
return Result;
}
@@ -15280,15 +15119,15 @@ SDNode *Select_ISD_BUILD_VECTOR_v16i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_187(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp1 = Transform_VMOV_get_imm16(N.getNode());
+DISABLE_INLINE SDNode *Emit_187(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp1 = Transform_VMOV_get_imm16(SDValue(N, 0).getNode());
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1, Tmp2, Tmp3);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1, Tmp2, Tmp3);
}
-SDNode *Select_ISD_BUILD_VECTOR_v4i16(const SDValue &N) {
+SDNode *Select_ISD_BUILD_VECTOR_v4i16(SDNode *N) {
if ((Subtarget->hasNEON()) &&
- Predicate_vmovImm16(N.getNode())) {
+ Predicate_vmovImm16(N)) {
SDNode *Result = Emit_187(N, ARM::VMOVv4i16, MVT::v4i16);
return Result;
}
@@ -15297,9 +15136,9 @@ SDNode *Select_ISD_BUILD_VECTOR_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BUILD_VECTOR_v8i16(const SDValue &N) {
+SDNode *Select_ISD_BUILD_VECTOR_v8i16(SDNode *N) {
if ((Subtarget->hasNEON()) &&
- Predicate_vmovImm16(N.getNode())) {
+ Predicate_vmovImm16(N)) {
SDNode *Result = Emit_187(N, ARM::VMOVv8i16, MVT::v8i16);
return Result;
}
@@ -15308,15 +15147,15 @@ SDNode *Select_ISD_BUILD_VECTOR_v8i16(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_188(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp1 = Transform_VMOV_get_imm32(N.getNode());
+DISABLE_INLINE SDNode *Emit_188(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp1 = Transform_VMOV_get_imm32(SDValue(N, 0).getNode());
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1, Tmp2, Tmp3);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1, Tmp2, Tmp3);
}
-SDNode *Select_ISD_BUILD_VECTOR_v2i32(const SDValue &N) {
+SDNode *Select_ISD_BUILD_VECTOR_v2i32(SDNode *N) {
if ((Subtarget->hasNEON()) &&
- Predicate_vmovImm32(N.getNode())) {
+ Predicate_vmovImm32(N)) {
SDNode *Result = Emit_188(N, ARM::VMOVv2i32, MVT::v2i32);
return Result;
}
@@ -15325,9 +15164,9 @@ SDNode *Select_ISD_BUILD_VECTOR_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BUILD_VECTOR_v4i32(const SDValue &N) {
+SDNode *Select_ISD_BUILD_VECTOR_v4i32(SDNode *N) {
if ((Subtarget->hasNEON()) &&
- Predicate_vmovImm32(N.getNode())) {
+ Predicate_vmovImm32(N)) {
SDNode *Result = Emit_188(N, ARM::VMOVv4i32, MVT::v4i32);
return Result;
}
@@ -15336,15 +15175,15 @@ SDNode *Select_ISD_BUILD_VECTOR_v4i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_189(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp1 = Transform_VMOV_get_imm64(N.getNode());
+DISABLE_INLINE SDNode *Emit_189(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp1 = Transform_VMOV_get_imm64(SDValue(N, 0).getNode());
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1, Tmp2, Tmp3);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1, Tmp2, Tmp3);
}
-SDNode *Select_ISD_BUILD_VECTOR_v1i64(const SDValue &N) {
+SDNode *Select_ISD_BUILD_VECTOR_v1i64(SDNode *N) {
if ((Subtarget->hasNEON()) &&
- Predicate_vmovImm64(N.getNode())) {
+ Predicate_vmovImm64(N)) {
SDNode *Result = Emit_189(N, ARM::VMOVv1i64, MVT::v1i64);
return Result;
}
@@ -15353,9 +15192,9 @@ SDNode *Select_ISD_BUILD_VECTOR_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BUILD_VECTOR_v2i64(const SDValue &N) {
+SDNode *Select_ISD_BUILD_VECTOR_v2i64(SDNode *N) {
if ((Subtarget->hasNEON()) &&
- Predicate_vmovImm64(N.getNode())) {
+ Predicate_vmovImm64(N)) {
SDNode *Result = Emit_189(N, ARM::VMOVv2i64, MVT::v2i64);
return Result;
}
@@ -15364,24 +15203,24 @@ SDNode *Select_ISD_BUILD_VECTOR_v2i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_190(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_190(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
SDValue Ops0[] = { N1, N2, Tmp2, Tmp3, Chain, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 6 : 5);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 6 : 5);
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -15390,24 +15229,24 @@ DISABLE_INLINE SDNode *Emit_190(const SDValue &N, unsigned Opc0) {
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_191(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_191(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
SDValue Ops0[] = { Tmp0, Tmp1, Chain, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 4 : 3);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 4 : 3);
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -15416,17 +15255,17 @@ DISABLE_INLINE SDNode *Emit_191(const SDValue &N, unsigned Opc0) {
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_ISD_CALLSEQ_END(const SDValue &N) {
+SDNode *Select_ISD_CALLSEQ_END(SDNode *N) {
// Pattern: (ARMcallseq_end:isVoid (timm:i32):$amt1, (timm:i32):$amt2)
// Emits: (ADJCALLSTACKUP:isVoid (timm:i32):$amt1, (timm:i32):$amt2)
// Pattern complexity = 9 cost = 1 size = 0
{
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetConstant) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::TargetConstant) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TargetConstant) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::TargetConstant) {
SDNode *Result = Emit_190(N, ARM::ADJCALLSTACKUP);
return Result;
}
@@ -15437,11 +15276,11 @@ SDNode *Select_ISD_CALLSEQ_END(const SDValue &N) {
// Emits: (tADJCALLSTACKUP:isVoid (imm:i32):$amt1, (imm:i32):$amt2)
// Pattern complexity = 9 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_191(N, ARM::tADJCALLSTACKUP);
return Result;
}
@@ -15452,18 +15291,18 @@ SDNode *Select_ISD_CALLSEQ_END(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_192(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_192(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, Tmp1, Tmp2, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, 4);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, 4);
Chain = SDValue(ResNode, 0);
SDValue InFlag(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -15472,16 +15311,16 @@ DISABLE_INLINE SDNode *Emit_192(const SDValue &N, unsigned Opc0) {
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_193(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_193(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Tmp0, Chain);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Tmp0, Chain);
Chain = SDValue(ResNode, 0);
SDValue InFlag(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -15490,15 +15329,15 @@ DISABLE_INLINE SDNode *Emit_193(const SDValue &N, unsigned Opc0) {
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_ISD_CALLSEQ_START(const SDValue &N) {
+SDNode *Select_ISD_CALLSEQ_START(SDNode *N) {
// Pattern: (ARMcallseq_start:isVoid (timm:i32):$amt)
// Emits: (ADJCALLSTACKDOWN:isVoid (timm:i32):$amt)
// Pattern complexity = 6 cost = 1 size = 0
{
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetConstant) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TargetConstant) {
SDNode *Result = Emit_192(N, ARM::ADJCALLSTACKDOWN);
return Result;
}
@@ -15508,9 +15347,9 @@ SDNode *Select_ISD_CALLSEQ_START(const SDValue &N) {
// Emits: (tADJCALLSTACKDOWN:isVoid (imm:i32):$amt)
// Pattern complexity = 6 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_193(N, ARM::tADJCALLSTACKDOWN);
return Result;
}
@@ -15520,7 +15359,7 @@ SDNode *Select_ISD_CALLSEQ_START(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_CTLZ_i32(const SDValue &N) {
+SDNode *Select_ISD_CTLZ_i32(SDNode *N) {
// Pattern: (ctlz:i32 GPR:i32:$src)
// Emits: (CLZ:i32 GPR:i32:$src)
@@ -15542,38 +15381,38 @@ SDNode *Select_ISD_CTLZ_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_194(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_194(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { Tmp0, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_195(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_195(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0, Tmp1, Tmp2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp0, Tmp1, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_196(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_196(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
SDValue Tmp1 = Transform_so_imm_not_XFORM(Tmp0.getNode());
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { Tmp1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_197(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_197(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { Tmp0, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_198(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+DISABLE_INLINE SDNode *Emit_198(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
SDValue Tmp1 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
@@ -15581,14 +15420,14 @@ DISABLE_INLINE SDNode *Emit_198(const SDValue &N, unsigned Opc0, unsigned Opc1,
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { Tmp1, Tmp3, Tmp4, Tmp5 };
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, Ops0, 4), 0);
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, Ops0, 4), 0);
SDValue Tmp7 = Transform_thumb_immshifted_shamt(Tmp2.getNode());
SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { Tmp0, Tmp6, Tmp7, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
}
-DISABLE_INLINE SDNode *Emit_199(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+DISABLE_INLINE SDNode *Emit_199(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
SDValue Tmp1 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
@@ -15596,28 +15435,28 @@ DISABLE_INLINE SDNode *Emit_199(const SDValue &N, unsigned Opc0, unsigned Opc1,
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { Tmp1, Tmp3, Tmp4, Tmp5 };
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, Ops0, 4), 0);
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, Ops0, 4), 0);
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { Tmp0, Tmp6, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 4);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 4);
}
-DISABLE_INLINE SDNode *Emit_200(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_200(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
SDValue Tmp1 = Transform_t2_so_imm_not_XFORM(Tmp0.getNode());
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { Tmp1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-SDNode *Select_ISD_Constant_i32(const SDValue &N) {
+SDNode *Select_ISD_Constant_i32(SDNode *N) {
// Pattern: (imm:i32)<<P:Predicate_t2_so_imm>>:$src
// Emits: (t2MOVi:i32 (imm:i32):$src)
// Pattern complexity = 5 cost = 1 size = 0
if ((Subtarget->isThumb2()) &&
- Predicate_t2_so_imm(N.getNode())) {
+ Predicate_t2_so_imm(N)) {
SDNode *Result = Emit_194(N, ARM::t2MOVi, MVT::i32);
return Result;
}
@@ -15626,7 +15465,7 @@ SDNode *Select_ISD_Constant_i32(const SDValue &N) {
// Emits: (MOVi:i32 (imm:i32):$src)
// Pattern complexity = 4 cost = 1 size = 0
if ((!Subtarget->isThumb()) &&
- Predicate_so_imm(N.getNode())) {
+ Predicate_so_imm(N)) {
SDNode *Result = Emit_194(N, ARM::MOVi, MVT::i32);
return Result;
}
@@ -15635,7 +15474,7 @@ SDNode *Select_ISD_Constant_i32(const SDValue &N) {
// Emits: (MOVi16:i32 (imm:i32):$src)
// Pattern complexity = 4 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops()) &&
- Predicate_imm0_65535(N.getNode())) {
+ Predicate_imm0_65535(N)) {
SDNode *Result = Emit_195(N, ARM::MOVi16, MVT::i32);
return Result;
}
@@ -15644,7 +15483,7 @@ SDNode *Select_ISD_Constant_i32(const SDValue &N) {
// Emits: (MVNi:i32 (so_imm_not_XFORM:i32 (imm:i32):$imm))
// Pattern complexity = 4 cost = 1 size = 0
if ((!Subtarget->isThumb()) &&
- Predicate_so_imm_not(N.getNode())) {
+ Predicate_so_imm_not(N)) {
SDNode *Result = Emit_196(N, ARM::MVNi, MVT::i32);
return Result;
}
@@ -15653,7 +15492,7 @@ SDNode *Select_ISD_Constant_i32(const SDValue &N) {
// Emits: (MOVi2pieces:i32 (imm:i32):$src)
// Pattern complexity = 4 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (!Subtarget->hasV6T2Ops()) &&
- Predicate_so_imm2part(N.getNode())) {
+ Predicate_so_imm2part(N)) {
SDNode *Result = Emit_195(N, ARM::MOVi2pieces, MVT::i32);
return Result;
}
@@ -15662,7 +15501,7 @@ SDNode *Select_ISD_Constant_i32(const SDValue &N) {
// Emits: (tMOVi8:i32 (imm:i32):$src)
// Pattern complexity = 4 cost = 1 size = 0
if ((Subtarget->isThumb1Only()) &&
- Predicate_imm0_255(N.getNode())) {
+ Predicate_imm0_255(N)) {
SDNode *Result = Emit_197(N, ARM::tMOVi8, MVT::i32);
return Result;
}
@@ -15671,7 +15510,7 @@ SDNode *Select_ISD_Constant_i32(const SDValue &N) {
// Pattern: (imm:i32)<<P:Predicate_imm0_65535>>:$src
// Emits: (t2MOVi16:i32 (imm:i32):$src)
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_imm0_65535(N.getNode())) {
+ if (Predicate_imm0_65535(N)) {
SDNode *Result = Emit_195(N, ARM::t2MOVi16, MVT::i32);
return Result;
}
@@ -15679,7 +15518,7 @@ SDNode *Select_ISD_Constant_i32(const SDValue &N) {
// Pattern: (imm:i32)<<P:Predicate_t2_so_imm_not>><<X:t2_so_imm_not_XFORM>>:$src
// Emits: (t2MVNi:i32 (t2_so_imm_not_XFORM:i32 (imm:i32)<<P:Predicate_t2_so_imm_not>>:$src))
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_t2_so_imm_not(N.getNode())) {
+ if (Predicate_t2_so_imm_not(N)) {
SDNode *Result = Emit_200(N, ARM::t2MVNi, MVT::i32);
return Result;
}
@@ -15689,7 +15528,7 @@ SDNode *Select_ISD_Constant_i32(const SDValue &N) {
// Pattern: (imm:i32)<<P:Predicate_thumb_immshifted>>:$src
// Emits: (tLSLri:i32 (tMOVi8:i32 (thumb_immshifted_val:i32 (imm:i32):$src)), (thumb_immshifted_shamt:i32 (imm:i32):$src))
// Pattern complexity = 4 cost = 2 size = 0
- if (Predicate_thumb_immshifted(N.getNode())) {
+ if (Predicate_thumb_immshifted(N)) {
SDNode *Result = Emit_198(N, ARM::tMOVi8, ARM::tLSLri, MVT::i32, MVT::i32);
return Result;
}
@@ -15697,7 +15536,7 @@ SDNode *Select_ISD_Constant_i32(const SDValue &N) {
// Pattern: (imm:i32)<<P:Predicate_imm0_255_comp>>:$src
// Emits: (tMVN:i32 (tMOVi8:i32 (imm_comp_XFORM:i32 (imm:i32):$src)))
// Pattern complexity = 4 cost = 2 size = 0
- if (Predicate_imm0_255_comp(N.getNode())) {
+ if (Predicate_imm0_255_comp(N)) {
SDNode *Result = Emit_199(N, ARM::tMOVi8, ARM::tMVN, MVT::i32, MVT::i32);
return Result;
}
@@ -15723,15 +15562,15 @@ SDNode *Select_ISD_Constant_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_201(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_201(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue Tmp0 = CurDAG->getTargetConstantFP(*cast<ConstantFPSDNode>(N)->getConstantFPValue(), cast<ConstantFPSDNode>(N)->getValueType(0));
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0, Tmp1, Tmp2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp0, Tmp1, Tmp2);
}
-SDNode *Select_ISD_ConstantFP_f32(const SDValue &N) {
+SDNode *Select_ISD_ConstantFP_f32(SDNode *N) {
if ((Subtarget->hasVFP3()) &&
- Predicate_vfp_f32imm(N.getNode())) {
+ Predicate_vfp_f32imm(N)) {
SDNode *Result = Emit_201(N, ARM::FCONSTS, MVT::f32);
return Result;
}
@@ -15740,9 +15579,9 @@ SDNode *Select_ISD_ConstantFP_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ConstantFP_f64(const SDValue &N) {
+SDNode *Select_ISD_ConstantFP_f64(SDNode *N) {
if ((Subtarget->hasVFP3()) &&
- Predicate_vfp_f64imm(N.getNode())) {
+ Predicate_vfp_f64imm(N)) {
SDNode *Result = Emit_201(N, ARM::FCONSTD, MVT::f64);
return Result;
}
@@ -15751,15 +15590,15 @@ SDNode *Select_ISD_ConstantFP_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i32(const SDValue &N) {
+SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i32(SDNode *N) {
// Pattern: (extractelt:i32 DPR:v2i32:$src, (imm:iPTR):$lane)
// Emits: (VGETLNi32:i32 DPR:v2i32:$src, (imm:i32):$lane)
// Pattern complexity = 6 cost = 1 size = 0
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_35(N, ARM::VGETLNi32, MVT::i32);
return Result;
@@ -15769,9 +15608,9 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i32(const SDValue &N) {
// Pattern: (extractelt:i32 QPR:v4i32:$src, (imm:iPTR):$lane)
// Emits: (VGETLNi32:i32 (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 6 cost = 2 size = 0
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_48(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VGETLNi32, MVT::v2i32, MVT::i32);
return Result;
@@ -15781,28 +15620,28 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_202(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_202(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp4 = Transform_SSubReg_f32_reg(Tmp3.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2, Tmp4);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2, Tmp4);
}
-DISABLE_INLINE SDNode *Emit_203(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_203(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp4 = Transform_SSubReg_f32_reg(Tmp3.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2, Tmp4);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2, Tmp4);
}
-SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (extractelt:f32 DPR:v2f32:$src1, (imm:iPTR):$src2)
// Emits: (EXTRACT_SUBREG:f32 (COPY_TO_REGCLASS:v2f32 DPR:v2f32:$src1, DPR_VFP2:f64), (SSubReg_f32_reg:i32 (imm:i32):$src2))
@@ -15825,17 +15664,17 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_204(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_204(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_DSubReg_f64_reg(Tmp1.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2);
}
-SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2f64) {
SDNode *Result = Emit_204(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::f64);
return Result;
@@ -15845,7 +15684,7 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FABS_f32(const SDValue &N) {
+SDNode *Select_ISD_FABS_f32(SDNode *N) {
// Pattern: (fabs:f32 SPR:f32:$a)
// Emits: (VABSS:f32 SPR:f32:$a)
@@ -15867,7 +15706,7 @@ SDNode *Select_ISD_FABS_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FABS_f64(const SDValue &N) {
+SDNode *Select_ISD_FABS_f64(SDNode *N) {
if ((Subtarget->hasVFP2())) {
SDNode *Result = Emit_31(N, ARM::VABSD, MVT::f64);
return Result;
@@ -15877,55 +15716,55 @@ SDNode *Select_ISD_FABS_f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_205(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_205(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, N000, N001, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_206(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, unsigned Opc4, unsigned Opc5, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3, MVT::SimpleValueType VT4, MVT::SimpleValueType VT5) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
+DISABLE_INLINE SDNode *Emit_206(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, unsigned Opc4, unsigned Opc5, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3, MVT::SimpleValueType VT4, MVT::SimpleValueType VT5) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp0(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
SDValue Tmp2 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- SDValue Tmp3(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp0, N0, Tmp2), 0);
- SDValue Tmp4(CurDAG->getMachineNode(Opc2, N.getDebugLoc(), VT2), 0);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp0, N0, Tmp2), 0);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc2, N->getDebugLoc(), VT2), 0);
SDValue Tmp6 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- SDValue Tmp7(CurDAG->getMachineNode(Opc3, N.getDebugLoc(), VT3, Tmp4, N1, Tmp6), 0);
+ SDValue Tmp7(CurDAG->getMachineNode(Opc3, N->getDebugLoc(), VT3, Tmp4, N1, Tmp6), 0);
SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops4[] = { Tmp3, Tmp7, Tmp8, Tmp9 };
- SDValue Tmp10(CurDAG->getMachineNode(Opc4, N.getDebugLoc(), VT4, Ops4, 4), 0);
+ SDValue Tmp10(CurDAG->getMachineNode(Opc4, N->getDebugLoc(), VT4, Ops4, 4), 0);
SDValue Tmp11 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc5, VT5, Tmp10, Tmp11);
-}
-DISABLE_INLINE SDNode *Emit_207(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc5, VT5, Tmp10, Tmp11);
+}
+DISABLE_INLINE SDNode *Emit_207(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, N100, N101, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-SDNode *Select_ISD_FADD_f32(const SDValue &N) {
+SDNode *Select_ISD_FADD_f32(SDNode *N) {
if ((Subtarget->hasVFP2()) && (!Subtarget->useNEONForSinglePrecisionFP())) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fadd:f32 (fneg:f32 (fmul:f32 SPR:f32:$a, SPR:f32:$b)), SPR:f32:$dstin)
// Emits: (VMLSS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FNEG) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FNEG) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_205(N, ARM::VMLSS, MVT::f32);
return Result;
}
@@ -15935,10 +15774,10 @@ SDNode *Select_ISD_FADD_f32(const SDValue &N) {
// Emits: (VMLSS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
// Pattern complexity = 9 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FNEG) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::FMUL) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FNEG) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_207(N, ARM::VMLSS, MVT::f32);
return Result;
}
@@ -15948,7 +15787,7 @@ SDNode *Select_ISD_FADD_f32(const SDValue &N) {
// Pattern: (fadd:f32 (fmul:f32 SPR:f32:$a, SPR:f32:$b), SPR:f32:$dstin)
// Emits: (VMLAS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_127(N, ARM::VMLAS, MVT::f32);
return Result;
}
@@ -15956,8 +15795,8 @@ SDNode *Select_ISD_FADD_f32(const SDValue &N) {
// Pattern: (fadd:f32 SPR:f32:$dstin, (fmul:f32 SPR:f32:$a, SPR:f32:$b))
// Emits: (VMLAS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
// Pattern complexity = 6 cost = 1 size = 0
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FMUL) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_125(N, ARM::VMLAS, MVT::f32);
return Result;
}
@@ -15982,17 +15821,17 @@ SDNode *Select_ISD_FADD_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FADD_f64(const SDValue &N) {
+SDNode *Select_ISD_FADD_f64(SDNode *N) {
if ((Subtarget->hasVFP2())) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fadd:f64 (fneg:f64 (fmul:f64 DPR:f64:$a, DPR:f64:$b)), DPR:f64:$dstin)
// Emits: (VMLSD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FNEG) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FNEG) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_205(N, ARM::VMLSD, MVT::f64);
return Result;
}
@@ -16002,10 +15841,10 @@ SDNode *Select_ISD_FADD_f64(const SDValue &N) {
// Emits: (VMLSD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
// Pattern complexity = 9 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FNEG) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::FMUL) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FNEG) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_207(N, ARM::VMLSD, MVT::f64);
return Result;
}
@@ -16015,7 +15854,7 @@ SDNode *Select_ISD_FADD_f64(const SDValue &N) {
// Pattern: (fadd:f64 (fmul:f64 DPR:f64:$a, DPR:f64:$b), DPR:f64:$dstin)
// Emits: (VMLAD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_127(N, ARM::VMLAD, MVT::f64);
return Result;
}
@@ -16023,8 +15862,8 @@ SDNode *Select_ISD_FADD_f64(const SDValue &N) {
// Pattern: (fadd:f64 DPR:f64:$dstin, (fmul:f64 DPR:f64:$a, DPR:f64:$b))
// Emits: (VMLAD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
// Pattern complexity = 6 cost = 1 size = 0
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FMUL) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_125(N, ARM::VMLAD, MVT::f64);
return Result;
}
@@ -16041,24 +15880,24 @@ SDNode *Select_ISD_FADD_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FADD_v2f32(const SDValue &N) {
+SDNode *Select_ISD_FADD_v2f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FMUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FMUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (fadd:v2f32 DPR:v2f32:$src1, (fmul:v2f32 DPR:v2f32:$src2, (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane)))
// Emits: (VMLAslfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_129(N, ARM::VMLAslfd, MVT::v2f32);
return Result;
@@ -16069,11 +15908,11 @@ SDNode *Select_ISD_FADD_v2f32(const SDValue &N) {
// Pattern: (fadd:v2f32 DPR:v2f32:$src1, (fmul:v2f32 (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane), DPR:v2f32:$src2))
// Emits: (VMLAslfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
- if (N10.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
+ if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_130(N, ARM::VMLAslfd, MVT::v2f32);
return Result;
@@ -16082,19 +15921,19 @@ SDNode *Select_ISD_FADD_v2f32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::FMUL) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::FMUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (fadd:v2f32 (fmul:v2f32 DPR:v2f32:$src2, (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane)), DPR:v2f32:$src1)
// Emits: (VMLAslfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
if (N010.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_131(N, ARM::VMLAslfd, MVT::v2f32);
return Result;
@@ -16106,12 +15945,12 @@ SDNode *Select_ISD_FADD_v2f32(const SDValue &N) {
// Pattern: (fadd:v2f32 (fmul:v2f32 (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane), DPR:v2f32:$src2), DPR:v2f32:$src1)
// Emits: (VMLAslfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
- if (N00.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ if (N00.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_132(N, ARM::VMLAslfd, MVT::v2f32);
return Result;
@@ -16124,8 +15963,8 @@ SDNode *Select_ISD_FADD_v2f32(const SDValue &N) {
// Emits: (VMLAfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR:v2f32:$src3)
// Pattern complexity = 6 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FMUL) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_125(N, ARM::VMLAfd, MVT::v2f32);
return Result;
}
@@ -16134,7 +15973,7 @@ SDNode *Select_ISD_FADD_v2f32(const SDValue &N) {
// Pattern: (fadd:v2f32 (fmul:v2f32 DPR:v2f32:$src2, DPR:v2f32:$src3), DPR:v2f32:$src1)
// Emits: (VMLAfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR:v2f32:$src3)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_127(N, ARM::VMLAfd, MVT::v2f32);
return Result;
}
@@ -16151,23 +15990,23 @@ SDNode *Select_ISD_FADD_v2f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FADD_v4f32(const SDValue &N) {
+SDNode *Select_ISD_FADD_v4f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FMUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FMUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (fadd:v4f32 QPR:v4f32:$src1, (fmul:v4f32 QPR:v4f32:$src2, (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane)))
// Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_129(N, ARM::VMLAslfq, MVT::v4f32);
return Result;
@@ -16178,11 +16017,11 @@ SDNode *Select_ISD_FADD_v4f32(const SDValue &N) {
// Pattern: (fadd:v4f32 QPR:v4f32:$src1, (fmul:v4f32 (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane), QPR:v4f32:$src2))
// Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
- if (N10.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
+ if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_130(N, ARM::VMLAslfq, MVT::v4f32);
return Result;
@@ -16191,19 +16030,19 @@ SDNode *Select_ISD_FADD_v4f32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::FMUL) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::FMUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (fadd:v4f32 (fmul:v4f32 QPR:v4f32:$src2, (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane)), QPR:v4f32:$src1)
// Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
if (N010.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_131(N, ARM::VMLAslfq, MVT::v4f32);
return Result;
@@ -16215,12 +16054,12 @@ SDNode *Select_ISD_FADD_v4f32(const SDValue &N) {
// Pattern: (fadd:v4f32 (fmul:v4f32 (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane), QPR:v4f32:$src2), QPR:v4f32:$src1)
// Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
- if (N00.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ if (N00.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_132(N, ARM::VMLAslfq, MVT::v4f32);
return Result;
@@ -16230,21 +16069,21 @@ SDNode *Select_ISD_FADD_v4f32(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FMUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FMUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (fadd:v4f32 QPR:v4f32:$src1, (fmul:v4f32 QPR:v4f32:$src2, (NEONvduplane:v4f32 QPR:v4f32:$src3, (imm:i32):$lane)))
// Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 12 cost = 2 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_137(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
return Result;
@@ -16255,11 +16094,11 @@ SDNode *Select_ISD_FADD_v4f32(const SDValue &N) {
// Pattern: (fadd:v4f32 QPR:v4f32:$src1, (fmul:v4f32 (NEONvduplane:v4f32 QPR:v4f32:$src3, (imm:i32):$lane), QPR:v4f32:$src2))
// Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 12 cost = 2 size = 0
- if (N10.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
+ if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_138(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
return Result;
@@ -16268,19 +16107,19 @@ SDNode *Select_ISD_FADD_v4f32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::FMUL) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::FMUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (fadd:v4f32 (fmul:v4f32 QPR:v4f32:$src2, (NEONvduplane:v4f32 QPR:v4f32:$src3, (imm:i32):$lane)), QPR:v4f32:$src1)
// Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 12 cost = 2 size = 0
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
if (N010.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_139(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
return Result;
@@ -16292,12 +16131,12 @@ SDNode *Select_ISD_FADD_v4f32(const SDValue &N) {
// Pattern: (fadd:v4f32 (fmul:v4f32 (NEONvduplane:v4f32 QPR:v4f32:$src3, (imm:i32):$lane), QPR:v4f32:$src2), QPR:v4f32:$src1)
// Emits: (VMLAslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 12 cost = 2 size = 0
- if (N00.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ if (N00.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_140(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
return Result;
@@ -16308,14 +16147,14 @@ SDNode *Select_ISD_FADD_v4f32(const SDValue &N) {
}
if ((Subtarget->hasNEON())) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fadd:v4f32 QPR:v4f32:$src1, (fmul:v4f32 QPR:v4f32:$src2, QPR:v4f32:$src3))
// Emits: (VMLAfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, QPR:v4f32:$src3)
// Pattern complexity = 6 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FMUL) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_125(N, ARM::VMLAfq, MVT::v4f32);
return Result;
}
@@ -16324,7 +16163,7 @@ SDNode *Select_ISD_FADD_v4f32(const SDValue &N) {
// Pattern: (fadd:v4f32 (fmul:v4f32 QPR:v4f32:$src2, QPR:v4f32:$src3), QPR:v4f32:$src1)
// Emits: (VMLAfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, QPR:v4f32:$src3)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_127(N, ARM::VMLAfq, MVT::v4f32);
return Result;
}
@@ -16341,7 +16180,7 @@ SDNode *Select_ISD_FADD_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FDIV_f32(const SDValue &N) {
+SDNode *Select_ISD_FDIV_f32(SDNode *N) {
if ((Subtarget->hasVFP2())) {
SDNode *Result = Emit_44(N, ARM::VDIVS, MVT::f32);
return Result;
@@ -16351,7 +16190,7 @@ SDNode *Select_ISD_FDIV_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FDIV_f64(const SDValue &N) {
+SDNode *Select_ISD_FDIV_f64(SDNode *N) {
if ((Subtarget->hasVFP2())) {
SDNode *Result = Emit_44(N, ARM::VDIVD, MVT::f64);
return Result;
@@ -16361,32 +16200,32 @@ SDNode *Select_ISD_FDIV_f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_208(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_208(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_209(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
+DISABLE_INLINE SDNode *Emit_209(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N10, N0, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-SDNode *Select_ISD_FMUL_f32(const SDValue &N) {
+SDNode *Select_ISD_FMUL_f32(SDNode *N) {
if ((!HonorSignDependentRoundingFPMath())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fmul:f32 (fneg:f32 SPR:f32:$a), SPR:f32:$b)
// Emits: (VNMULS:f32 SPR:f32:$a, SPR:f32:$b)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FNEG) {
+ if (N0.getNode()->getOpcode() == ISD::FNEG) {
SDNode *Result = Emit_208(N, ARM::VNMULS, MVT::f32);
return Result;
}
@@ -16394,8 +16233,8 @@ SDNode *Select_ISD_FMUL_f32(const SDValue &N) {
// Pattern: (fmul:f32 SPR:f32:$b, (fneg:f32 SPR:f32:$a))
// Emits: (VNMULS:f32 SPR:f32:$a, SPR:f32:$b)
// Pattern complexity = 6 cost = 1 size = 0
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FNEG) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FNEG) {
SDNode *Result = Emit_209(N, ARM::VNMULS, MVT::f32);
return Result;
}
@@ -16421,14 +16260,14 @@ SDNode *Select_ISD_FMUL_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
+SDNode *Select_ISD_FMUL_f64(SDNode *N) {
if ((!HonorSignDependentRoundingFPMath())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fmul:f64 (fneg:f64 DPR:f64:$a), DPR:f64:$b)
// Emits: (VNMULD:f64 DPR:f64:$a, DPR:f64:$b)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FNEG) {
+ if (N0.getNode()->getOpcode() == ISD::FNEG) {
SDNode *Result = Emit_208(N, ARM::VNMULD, MVT::f64);
return Result;
}
@@ -16436,8 +16275,8 @@ SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
// Pattern: (fmul:f64 DPR:f64:$b, (fneg:f64 DPR:f64:$a))
// Emits: (VNMULD:f64 DPR:f64:$a, DPR:f64:$b)
// Pattern complexity = 6 cost = 1 size = 0
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FNEG) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FNEG) {
SDNode *Result = Emit_209(N, ARM::VNMULD, MVT::f64);
return Result;
}
@@ -16455,20 +16294,20 @@ SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FMUL_v2f32(const SDValue &N) {
+SDNode *Select_ISD_FMUL_v2f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fmul:v2f32 DPR:v2f32:$src1, (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src2, (imm:i32):$lane))
// Emits: (VMULslfd:v2f32 DPR:v2f32:$src1, DPR_VFP2:v2f32:$src2, (imm:i32):$lane)
// Pattern complexity = 9 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_126(N, ARM::VMULslfd, MVT::v2f32);
return Result;
@@ -16479,11 +16318,11 @@ SDNode *Select_ISD_FMUL_v2f32(const SDValue &N) {
// Pattern: (fmul:v2f32 (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src2, (imm:i32):$lane), DPR:v2f32:$src1)
// Emits: (VMULslfd:v2f32 DPR:v2f32:$src1, DPR_VFP2:v2f32:$src2, (imm:i32):$lane)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
+ if (N0.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_128(N, ARM::VMULslfd, MVT::v2f32);
return Result;
@@ -16503,47 +16342,47 @@ SDNode *Select_ISD_FMUL_v2f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_210(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_210(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
SDValue Tmp3 = Transform_DSubReg_i32_reg(Tmp2.getNode());
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N10, Tmp3), 0);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N10, Tmp3), 0);
SDValue Tmp5 = Transform_SubReg_i32_lane(Tmp2.getNode());
SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { N0, Tmp4, Tmp5, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
}
-DISABLE_INLINE SDNode *Emit_211(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_211(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
SDValue Tmp3 = Transform_DSubReg_i32_reg(Tmp2.getNode());
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N00, Tmp3), 0);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N00, Tmp3), 0);
SDValue Tmp5 = Transform_SubReg_i32_lane(Tmp2.getNode());
SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { N1, Tmp4, Tmp5, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
}
-SDNode *Select_ISD_FMUL_v4f32(const SDValue &N) {
+SDNode *Select_ISD_FMUL_v4f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fmul:v4f32 QPR:v4f32:$src1, (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src2, (imm:i32):$lane))
// Emits: (VMULslfq:v4f32 QPR:v4f32:$src1, DPR_VFP2:v2f32:$src2, (imm:i32):$lane)
// Pattern complexity = 9 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_126(N, ARM::VMULslfq, MVT::v4f32);
return Result;
@@ -16554,11 +16393,11 @@ SDNode *Select_ISD_FMUL_v4f32(const SDValue &N) {
// Pattern: (fmul:v4f32 (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src2, (imm:i32):$lane), QPR:v4f32:$src1)
// Emits: (VMULslfq:v4f32 QPR:v4f32:$src1, DPR_VFP2:v2f32:$src2, (imm:i32):$lane)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
+ if (N0.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_128(N, ARM::VMULslfq, MVT::v4f32);
return Result;
@@ -16567,17 +16406,17 @@ SDNode *Select_ISD_FMUL_v4f32(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fmul:v4f32 QPR:v4f32:$src1, (NEONvduplane:v4f32 QPR:v4f32:$src2, (imm:i32):$lane))
// Emits: (VMULslfq:v4f32 QPR:v4f32:$src1, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 9 cost = 2 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_210(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslfq, MVT::v2f32, MVT::v4f32);
return Result;
@@ -16588,11 +16427,11 @@ SDNode *Select_ISD_FMUL_v4f32(const SDValue &N) {
// Pattern: (fmul:v4f32 (NEONvduplane:v4f32 QPR:v4f32:$src2, (imm:i32):$lane), QPR:v4f32:$src1)
// Emits: (VMULslfq:v4f32 QPR:v4f32:$src1, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 9 cost = 2 size = 0
- if (N0.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
+ if (N0.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_211(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslfq, MVT::v2f32, MVT::v4f32);
return Result;
@@ -16613,23 +16452,23 @@ SDNode *Select_ISD_FMUL_v4f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_212(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+DISABLE_INLINE SDNode *Emit_212(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N01, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-SDNode *Select_ISD_FNEG_f32(const SDValue &N) {
+SDNode *Select_ISD_FNEG_f32(SDNode *N) {
// Pattern: (fneg:f32 (fmul:f32 SPR:f32:$a, SPR:f32:$b))
// Emits: (VNMULS:f32 SPR:f32:$a, SPR:f32:$b)
// Pattern complexity = 6 cost = 1 size = 0
if ((Subtarget->hasVFP2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::FMUL) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_212(N, ARM::VNMULS, MVT::f32);
return Result;
}
@@ -16655,15 +16494,15 @@ SDNode *Select_ISD_FNEG_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FNEG_f64(const SDValue &N) {
+SDNode *Select_ISD_FNEG_f64(SDNode *N) {
if ((Subtarget->hasVFP2())) {
// Pattern: (fneg:f64 (fmul:f64 DPR:f64:$a, DPR:f64:$b))
// Emits: (VNMULD:f64 DPR:f64:$a, DPR:f64:$b)
// Pattern complexity = 6 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::FMUL) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_212(N, ARM::VNMULD, MVT::f64);
return Result;
}
@@ -16680,7 +16519,7 @@ SDNode *Select_ISD_FNEG_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FNEG_v2f32(const SDValue &N) {
+SDNode *Select_ISD_FNEG_v2f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
SDNode *Result = Emit_31(N, ARM::VNEGf32d, MVT::v2f32);
return Result;
@@ -16690,7 +16529,7 @@ SDNode *Select_ISD_FNEG_v2f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FNEG_v4f32(const SDValue &N) {
+SDNode *Select_ISD_FNEG_v4f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
SDNode *Result = Emit_31(N, ARM::VNEGf32q, MVT::v4f32);
return Result;
@@ -16700,9 +16539,9 @@ SDNode *Select_ISD_FNEG_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FP_EXTEND_f64(const SDValue &N) {
+SDNode *Select_ISD_FP_EXTEND_f64(SDNode *N) {
if ((Subtarget->hasVFP2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
SDNode *Result = Emit_31(N, ARM::VCVTDS, MVT::f64);
return Result;
@@ -16713,9 +16552,9 @@ SDNode *Select_ISD_FP_EXTEND_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FP_ROUND_f32(const SDValue &N) {
+SDNode *Select_ISD_FP_ROUND_f32(SDNode *N) {
if ((Subtarget->hasVFP2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f64) {
SDNode *Result = Emit_31(N, ARM::VCVTSD, MVT::f32);
return Result;
@@ -16726,9 +16565,9 @@ SDNode *Select_ISD_FP_ROUND_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FP_TO_SINT_v2i32(const SDValue &N) {
+SDNode *Select_ISD_FP_TO_SINT_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_31(N, ARM::VCVTf2sd, MVT::v2i32);
return Result;
@@ -16739,9 +16578,9 @@ SDNode *Select_ISD_FP_TO_SINT_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FP_TO_SINT_v4i32(const SDValue &N) {
+SDNode *Select_ISD_FP_TO_SINT_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_31(N, ARM::VCVTf2sq, MVT::v4i32);
return Result;
@@ -16752,9 +16591,9 @@ SDNode *Select_ISD_FP_TO_SINT_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FP_TO_UINT_v2i32(const SDValue &N) {
+SDNode *Select_ISD_FP_TO_UINT_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_31(N, ARM::VCVTf2ud, MVT::v2i32);
return Result;
@@ -16765,9 +16604,9 @@ SDNode *Select_ISD_FP_TO_UINT_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FP_TO_UINT_v4i32(const SDValue &N) {
+SDNode *Select_ISD_FP_TO_UINT_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_31(N, ARM::VCVTf2uq, MVT::v4i32);
return Result;
@@ -16778,7 +16617,7 @@ SDNode *Select_ISD_FP_TO_UINT_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FSQRT_f32(const SDValue &N) {
+SDNode *Select_ISD_FSQRT_f32(SDNode *N) {
if ((Subtarget->hasVFP2())) {
SDNode *Result = Emit_31(N, ARM::VSQRTS, MVT::f32);
return Result;
@@ -16788,7 +16627,7 @@ SDNode *Select_ISD_FSQRT_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FSQRT_f64(const SDValue &N) {
+SDNode *Select_ISD_FSQRT_f64(SDNode *N) {
if ((Subtarget->hasVFP2())) {
SDNode *Result = Emit_31(N, ARM::VSQRTD, MVT::f64);
return Result;
@@ -16798,16 +16637,16 @@ SDNode *Select_ISD_FSQRT_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FSUB_f32(const SDValue &N) {
+SDNode *Select_ISD_FSUB_f32(SDNode *N) {
if ((Subtarget->hasVFP2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fsub:f32 (fneg:f32 (fmul:f32 SPR:f32:$a, SPR:f32:$b)), SPR:f32:$dstin)
// Emits: (VNMLAS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FNEG) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FNEG) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_205(N, ARM::VNMLAS, MVT::f32);
return Result;
}
@@ -16816,7 +16655,7 @@ SDNode *Select_ISD_FSUB_f32(const SDValue &N) {
// Pattern: (fsub:f32 (fmul:f32 SPR:f32:$a, SPR:f32:$b), SPR:f32:$dstin)
// Emits: (VNMLSS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_127(N, ARM::VNMLSS, MVT::f32);
return Result;
}
@@ -16826,9 +16665,9 @@ SDNode *Select_ISD_FSUB_f32(const SDValue &N) {
// Emits: (VMLSS:f32 SPR:f32:$dstin, SPR:f32:$a, SPR:f32:$b)
// Pattern complexity = 6 cost = 1 size = 0
if ((!Subtarget->useNEONForSinglePrecisionFP())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FMUL) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_125(N, ARM::VMLSS, MVT::f32);
return Result;
}
@@ -16854,16 +16693,16 @@ SDNode *Select_ISD_FSUB_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
+SDNode *Select_ISD_FSUB_f64(SDNode *N) {
if ((Subtarget->hasVFP2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fsub:f64 (fneg:f64 (fmul:f64 DPR:f64:$a, DPR:f64:$b)), DPR:f64:$dstin)
// Emits: (VNMLAD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FNEG) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FNEG) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_205(N, ARM::VNMLAD, MVT::f64);
return Result;
}
@@ -16872,7 +16711,7 @@ SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
// Pattern: (fsub:f64 (fmul:f64 DPR:f64:$a, DPR:f64:$b), DPR:f64:$dstin)
// Emits: (VNMLSD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_127(N, ARM::VNMLSD, MVT::f64);
return Result;
}
@@ -16882,9 +16721,9 @@ SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
// Emits: (VMLSD:f64 DPR:f64:$dstin, DPR:f64:$a, DPR:f64:$b)
// Pattern complexity = 6 cost = 1 size = 0
if ((!Subtarget->useNEONForSinglePrecisionFP())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FMUL) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_125(N, ARM::VMLSD, MVT::f64);
return Result;
}
@@ -16902,24 +16741,24 @@ SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FSUB_v2f32(const SDValue &N) {
+SDNode *Select_ISD_FSUB_v2f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FMUL) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FMUL) {
{
- SDValue N10 = N1.getOperand(0);
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (fsub:v2f32 DPR:v2f32:$src1, (fmul:v2f32 DPR:v2f32:$src2, (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane)))
// Emits: (VMLSslfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_129(N, ARM::VMLSslfd, MVT::v2f32);
return Result;
@@ -16930,11 +16769,11 @@ SDNode *Select_ISD_FSUB_v2f32(const SDValue &N) {
// Pattern: (fsub:v2f32 DPR:v2f32:$src1, (fmul:v2f32 (NEONvduplane:v2f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane), DPR:v2f32:$src2))
// Emits: (VMLSslfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
- if (N10.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
+ if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_130(N, ARM::VMLSslfd, MVT::v2f32);
return Result;
@@ -16962,22 +16801,22 @@ SDNode *Select_ISD_FSUB_v2f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FSUB_v4f32(const SDValue &N) {
+SDNode *Select_ISD_FSUB_v4f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FMUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FMUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (fsub:v4f32 QPR:v4f32:$src1, (fmul:v4f32 QPR:v4f32:$src2, (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane)))
// Emits: (VMLSslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_129(N, ARM::VMLSslfq, MVT::v4f32);
return Result;
@@ -16988,11 +16827,11 @@ SDNode *Select_ISD_FSUB_v4f32(const SDValue &N) {
// Pattern: (fsub:v4f32 QPR:v4f32:$src1, (fmul:v4f32 (NEONvduplane:v4f32 DPR_VFP2:v2f32:$src3, (imm:i32):$lane), QPR:v4f32:$src2))
// Emits: (VMLSslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, DPR_VFP2:v2f32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
- if (N10.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
+ if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_130(N, ARM::VMLSslfq, MVT::v4f32);
return Result;
@@ -17002,20 +16841,20 @@ SDNode *Select_ISD_FSUB_v4f32(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FMUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FMUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (fsub:v4f32 QPR:v4f32:$src1, (fmul:v4f32 QPR:v4f32:$src2, (NEONvduplane:v4f32 QPR:v4f32:$src3, (imm:i32):$lane)))
// Emits: (VMLSslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 12 cost = 2 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_137(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslfq, MVT::v2f32, MVT::v4f32);
return Result;
@@ -17026,11 +16865,11 @@ SDNode *Select_ISD_FSUB_v4f32(const SDValue &N) {
// Pattern: (fsub:v4f32 QPR:v4f32:$src1, (fmul:v4f32 (NEONvduplane:v4f32 QPR:v4f32:$src3, (imm:i32):$lane), QPR:v4f32:$src2))
// Emits: (VMLSslfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, (EXTRACT_SUBREG:v2f32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 12 cost = 2 size = 0
- if (N10.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
+ if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_138(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslfq, MVT::v2f32, MVT::v4f32);
return Result;
@@ -17045,9 +16884,9 @@ SDNode *Select_ISD_FSUB_v4f32(const SDValue &N) {
// Emits: (VMLSfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2, QPR:v4f32:$src3)
// Pattern complexity = 6 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FMUL) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_125(N, ARM::VMLSfq, MVT::v4f32);
return Result;
}
@@ -17064,12 +16903,12 @@ SDNode *Select_ISD_FSUB_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v8i8(const SDValue &N) {
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_50(N, ARM::VSETLNi8, MVT::v8i8);
return Result;
@@ -17080,26 +16919,26 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v8i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_213(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_213(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
SDValue Tmp3 = Transform_DSubReg_i8_reg(Tmp2.getNode());
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp3), 0);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp3), 0);
SDValue Tmp6 = Transform_SubReg_i8_lane(Tmp2.getNode());
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { Tmp4, N1, Tmp6, Tmp7, Tmp8 };
- SDValue Tmp9(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Ops1, 5), 0);
+ SDValue Tmp9(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Ops1, 5), 0);
SDValue Tmp10 = Transform_DSubReg_i8_reg(Tmp2.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc2, VT2, N0, Tmp9, Tmp10);
+ return CurDAG->SelectNodeTo(N, Opc2, VT2, N0, Tmp9, Tmp10);
}
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v16i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v16i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_213(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VSETLNi8, TargetInstrInfo::INSERT_SUBREG, MVT::v8i8, MVT::f64, MVT::v16i8);
return Result;
@@ -17109,12 +16948,12 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i16(const SDValue &N) {
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_50(N, ARM::VSETLNi16, MVT::v4i16);
return Result;
@@ -17125,26 +16964,26 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i16(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_214(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_214(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
SDValue Tmp3 = Transform_DSubReg_i16_reg(Tmp2.getNode());
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp3), 0);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp3), 0);
SDValue Tmp6 = Transform_SubReg_i16_lane(Tmp2.getNode());
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { Tmp4, N1, Tmp6, Tmp7, Tmp8 };
- SDValue Tmp9(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Ops1, 5), 0);
+ SDValue Tmp9(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Ops1, 5), 0);
SDValue Tmp10 = Transform_DSubReg_i16_reg(Tmp2.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc2, VT2, N0, Tmp9, Tmp10);
+ return CurDAG->SelectNodeTo(N, Opc2, VT2, N0, Tmp9, Tmp10);
}
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v8i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v8i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_214(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VSETLNi16, TargetInstrInfo::INSERT_SUBREG, MVT::v4i16, MVT::f64, MVT::v8i16);
return Result;
@@ -17154,12 +16993,12 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v2i32(const SDValue &N) {
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_50(N, ARM::VSETLNi32, MVT::v2i32);
return Result;
}
@@ -17169,26 +17008,26 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v2i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_215(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_215(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
SDValue Tmp3 = Transform_DSubReg_i32_reg(Tmp2.getNode());
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp3), 0);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp3), 0);
SDValue Tmp6 = Transform_SubReg_i32_lane(Tmp2.getNode());
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { Tmp4, N1, Tmp6, Tmp7, Tmp8 };
- SDValue Tmp9(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Ops1, 5), 0);
+ SDValue Tmp9(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Ops1, 5), 0);
SDValue Tmp10 = Transform_DSubReg_i32_reg(Tmp2.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc2, VT2, N0, Tmp9, Tmp10);
+ return CurDAG->SelectNodeTo(N, Opc2, VT2, N0, Tmp9, Tmp10);
}
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_215(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VSETLNi32, TargetInstrInfo::INSERT_SUBREG, MVT::v2i32, MVT::f64, MVT::v4i32);
return Result;
}
@@ -17197,21 +17036,21 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_216(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_216(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp1 = CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
SDValue Tmp5 = Transform_SSubReg_f32_reg(Tmp4.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2, N1, Tmp5);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2, N1, Tmp5);
}
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v2f32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v2f32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_216(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::INSERT_SUBREG, MVT::v2f32, MVT::v2f32);
return Result;
}
@@ -17220,21 +17059,21 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v2f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_217(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_217(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp1 = CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
SDValue Tmp5 = Transform_SSubReg_f32_reg(Tmp4.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2, N1, Tmp5);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2, N1, Tmp5);
}
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v4f32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v4f32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_217(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::INSERT_SUBREG, MVT::v4f32, MVT::v4f32);
return Result;
}
@@ -17243,19 +17082,19 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v4f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_218(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_218(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
SDValue Tmp3 = Transform_DSubReg_f64_reg(Tmp2.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, Tmp3);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, Tmp3);
}
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v2f64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v2f64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_218(N, TargetInstrInfo::INSERT_SUBREG, MVT::v2f64);
return Result;
}
@@ -17264,31 +17103,31 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_219(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_219(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, N3, Tmp4, Tmp5, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
}
-SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(105)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
if (SelectAddrMode6(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3)) {
- SDValue N3 = N.getOperand(3);
+ SDValue N3 = N->getOperand(3);
if (N2.getValueType() == MVT::i32) {
// Pattern: (intrinsic_void:isVoid 105:iPTR, addrmode6:i32:$addr, DPR:v8i8:$src)
@@ -17380,72 +17219,72 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_220(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_220(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, N2, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_221(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_221(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, N2, N3, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_222(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_222(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, Tmp3, Tmp4);
-}
-DISABLE_INLINE SDNode *Emit_223(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, Tmp3, Tmp4);
+}
+DISABLE_INLINE SDNode *Emit_223(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, N2, N3, N4, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_224(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_224(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, N2, N3, N4, N5, Tmp7, Tmp8 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 7);
-}
-DISABLE_INLINE SDNode *Emit_225(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
- SDValue N6 = N.getOperand(6);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 7);
+}
+DISABLE_INLINE SDNode *Emit_225(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ SDValue N6 = N->getOperand(6);
SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, N2, N3, N4, N5, N6, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 8);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 8);
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -17453,8 +17292,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VHADDsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(28)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VHADDsv8i8, MVT::v8i8);
@@ -17466,8 +17305,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VHADDuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(29)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VHADDuv8i8, MVT::v8i8);
@@ -17479,8 +17318,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VRHADDsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(91)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VRHADDsv8i8, MVT::v8i8);
@@ -17492,8 +17331,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VRHADDuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(92)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VRHADDuv8i8, MVT::v8i8);
@@ -17505,8 +17344,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VQADDsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(64)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VQADDsv8i8, MVT::v8i8);
@@ -17518,8 +17357,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VQADDuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(65)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VQADDuv8i8, MVT::v8i8);
@@ -17531,8 +17370,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VADDHNv8i8:v8i8 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VADDHNv8i8, MVT::v8i8);
@@ -17544,8 +17383,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VRADDHNv8i8:v8i8 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(88)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VRADDHNv8i8, MVT::v8i8);
@@ -17557,8 +17396,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VMULpd:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(53)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VMULpd, MVT::v8i8);
@@ -17570,8 +17409,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VHSUBsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(30)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VHSUBsv8i8, MVT::v8i8);
@@ -17583,8 +17422,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VHSUBuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(31)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VHSUBuv8i8, MVT::v8i8);
@@ -17596,8 +17435,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VQSUBsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(86)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VQSUBsv8i8, MVT::v8i8);
@@ -17609,8 +17448,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VQSUBuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(87)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VQSUBuv8i8, MVT::v8i8);
@@ -17622,8 +17461,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VSUBHNv8i8:v8i8 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(112)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VSUBHNv8i8, MVT::v8i8);
@@ -17635,8 +17474,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VRSUBHNv8i8:v8i8 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(98)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VRSUBHNv8i8, MVT::v8i8);
@@ -17648,8 +17487,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VABDsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(9)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VABDsv8i8, MVT::v8i8);
@@ -17661,8 +17500,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VABDuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(10)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VABDuv8i8, MVT::v8i8);
@@ -17674,9 +17513,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VABAsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(5)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8 &&
N3.getValueType() == MVT::v8i8) {
@@ -17689,9 +17528,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VABAuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(6)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8 &&
N3.getValueType() == MVT::v8i8) {
@@ -17704,8 +17543,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VMAXsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(39)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VMAXsv8i8, MVT::v8i8);
@@ -17717,8 +17556,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VMAXuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(40)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VMAXuv8i8, MVT::v8i8);
@@ -17730,8 +17569,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VMINsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(41)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VMINsv8i8, MVT::v8i8);
@@ -17743,8 +17582,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VMINuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(42)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VMINuv8i8, MVT::v8i8);
@@ -17756,8 +17595,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VPADDi8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(56)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VPADDi8, MVT::v8i8);
@@ -17769,8 +17608,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VPMAXs8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(59)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VPMAXs8, MVT::v8i8);
@@ -17782,8 +17621,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VPMAXu8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(60)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VPMAXu8, MVT::v8i8);
@@ -17795,8 +17634,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VPMINs8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(61)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VPMINs8, MVT::v8i8);
@@ -17808,8 +17647,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VPMINu8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(62)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VPMINu8, MVT::v8i8);
@@ -17821,8 +17660,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VSHLsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(103)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VSHLsv8i8, MVT::v8i8);
@@ -17834,8 +17673,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VSHLuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(104)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VSHLuv8i8, MVT::v8i8);
@@ -17847,8 +17686,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VRSHLsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(94)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VRSHLsv8i8, MVT::v8i8);
@@ -17860,8 +17699,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VRSHLuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(95)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VRSHLuv8i8, MVT::v8i8);
@@ -17873,8 +17712,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VQSHLsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(83)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VQSHLsv8i8, MVT::v8i8);
@@ -17886,8 +17725,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VQSHLuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(85)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VQSHLuv8i8, MVT::v8i8);
@@ -17899,8 +17738,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VQRSHLsv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(78)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VQRSHLsv8i8, MVT::v8i8);
@@ -17912,8 +17751,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VQRSHLuv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(79)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VQRSHLuv8i8, MVT::v8i8);
@@ -17925,7 +17764,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VABSv8i8:v8i8 DPR:v8i8:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(11)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_222(N, ARM::VABSv8i8, MVT::v8i8);
return Result;
@@ -17936,7 +17775,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VQABSv8i8:v8i8 DPR:v8i8:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(63)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_222(N, ARM::VQABSv8i8, MVT::v8i8);
return Result;
@@ -17947,7 +17786,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VQNEGv8i8:v8i8 DPR:v8i8:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(73)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_222(N, ARM::VQNEGv8i8, MVT::v8i8);
return Result;
@@ -17958,7 +17797,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VCLSv8i8:v8i8 DPR:v8i8:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(21)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_222(N, ARM::VCLSv8i8, MVT::v8i8);
return Result;
@@ -17969,7 +17808,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VCLZv8i8:v8i8 DPR:v8i8:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(22)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_222(N, ARM::VCLZv8i8, MVT::v8i8);
return Result;
@@ -17980,7 +17819,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VCNTd:v8i8 DPR:v8i8:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(23)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_222(N, ARM::VCNTd, MVT::v8i8);
return Result;
@@ -17991,7 +17830,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VMOVNv8i8:v8i8 QPR:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(49)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_222(N, ARM::VMOVNv8i8, MVT::v8i8);
return Result;
@@ -18002,7 +17841,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VQMOVNsv8i8:v8i8 QPR:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(70)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_222(N, ARM::VQMOVNsv8i8, MVT::v8i8);
return Result;
@@ -18013,7 +17852,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VQMOVNuv8i8:v8i8 QPR:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(72)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_222(N, ARM::VQMOVNuv8i8, MVT::v8i8);
return Result;
@@ -18024,7 +17863,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
// Emits: (VQMOVNsuv8i8:v8i8 QPR:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(71)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_222(N, ARM::VQMOVNsuv8i8, MVT::v8i8);
return Result;
@@ -18101,10 +17940,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -18112,8 +17951,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VHADDsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(28)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VHADDsv16i8, MVT::v16i8);
@@ -18125,8 +17964,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VHADDuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(29)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VHADDuv16i8, MVT::v16i8);
@@ -18138,8 +17977,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VRHADDsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(91)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VRHADDsv16i8, MVT::v16i8);
@@ -18151,8 +17990,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VRHADDuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(92)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VRHADDuv16i8, MVT::v16i8);
@@ -18164,8 +18003,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VQADDsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(64)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VQADDsv16i8, MVT::v16i8);
@@ -18177,8 +18016,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VQADDuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(65)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VQADDuv16i8, MVT::v16i8);
@@ -18190,8 +18029,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VMULpq:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(53)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VMULpq, MVT::v16i8);
@@ -18203,8 +18042,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VHSUBsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(30)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VHSUBsv16i8, MVT::v16i8);
@@ -18216,8 +18055,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VHSUBuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(31)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VHSUBuv16i8, MVT::v16i8);
@@ -18229,8 +18068,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VQSUBsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(86)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VQSUBsv16i8, MVT::v16i8);
@@ -18242,8 +18081,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VQSUBuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(87)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VQSUBuv16i8, MVT::v16i8);
@@ -18255,8 +18094,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VABDsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(9)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VABDsv16i8, MVT::v16i8);
@@ -18268,8 +18107,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VABDuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(10)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VABDuv16i8, MVT::v16i8);
@@ -18281,9 +18120,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VABAsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, QPR:v16i8:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(5)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8 &&
N3.getValueType() == MVT::v16i8) {
@@ -18296,9 +18135,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VABAuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, QPR:v16i8:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(6)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8 &&
N3.getValueType() == MVT::v16i8) {
@@ -18311,8 +18150,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VMAXsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(39)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VMAXsv16i8, MVT::v16i8);
@@ -18324,8 +18163,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VMAXuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(40)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VMAXuv16i8, MVT::v16i8);
@@ -18337,8 +18176,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VMINsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(41)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VMINsv16i8, MVT::v16i8);
@@ -18350,8 +18189,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VMINuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(42)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VMINuv16i8, MVT::v16i8);
@@ -18363,8 +18202,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VSHLsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(103)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VSHLsv16i8, MVT::v16i8);
@@ -18376,8 +18215,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VSHLuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(104)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VSHLuv16i8, MVT::v16i8);
@@ -18389,8 +18228,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VRSHLsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(94)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VRSHLsv16i8, MVT::v16i8);
@@ -18402,8 +18241,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VRSHLuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(95)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VRSHLuv16i8, MVT::v16i8);
@@ -18415,8 +18254,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VQSHLsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(83)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VQSHLsv16i8, MVT::v16i8);
@@ -18428,8 +18267,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VQSHLuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(85)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VQSHLuv16i8, MVT::v16i8);
@@ -18441,8 +18280,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VQRSHLsv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(78)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VQRSHLsv16i8, MVT::v16i8);
@@ -18454,8 +18293,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VQRSHLuv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(79)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v16i8 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VQRSHLuv16i8, MVT::v16i8);
@@ -18467,7 +18306,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VABSv16i8:v16i8 QPR:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(11)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_222(N, ARM::VABSv16i8, MVT::v16i8);
return Result;
@@ -18478,7 +18317,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VQABSv16i8:v16i8 QPR:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(63)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_222(N, ARM::VQABSv16i8, MVT::v16i8);
return Result;
@@ -18489,7 +18328,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VQNEGv16i8:v16i8 QPR:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(73)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_222(N, ARM::VQNEGv16i8, MVT::v16i8);
return Result;
@@ -18500,7 +18339,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VCLSv16i8:v16i8 QPR:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(21)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_222(N, ARM::VCLSv16i8, MVT::v16i8);
return Result;
@@ -18511,7 +18350,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VCLZv16i8:v16i8 QPR:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(22)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_222(N, ARM::VCLZv16i8, MVT::v16i8);
return Result;
@@ -18522,7 +18361,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
// Emits: (VCNTq:v16i8 QPR:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(23)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_222(N, ARM::VCNTq, MVT::v16i8);
return Result;
@@ -18535,34 +18374,34 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_226(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
+DISABLE_INLINE SDNode *Emit_226(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N21)->getZExtValue()), MVT::i32);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, N20, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_227(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_227(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N2, N10, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -18570,12 +18409,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VQDMULHslv4i16:v4i16 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(68)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- if (N21.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ if (N21.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16 &&
N20.getValueType() == MVT::v4i16) {
@@ -18589,12 +18428,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VQRDMULHslv4i16:v4i16 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(74)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- if (N21.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ if (N21.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16 &&
N20.getValueType() == MVT::v4i16) {
@@ -18608,12 +18447,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VQDMULHslv4i16:v4i16 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(68)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N10.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
@@ -18628,12 +18467,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VQRDMULHslv4i16:v4i16 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(74)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N10.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
@@ -18648,8 +18487,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VHADDsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(28)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VHADDsv4i16, MVT::v4i16);
@@ -18661,8 +18500,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VHADDuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(29)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VHADDuv4i16, MVT::v4i16);
@@ -18674,8 +18513,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VRHADDsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(91)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VRHADDsv4i16, MVT::v4i16);
@@ -18687,8 +18526,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VRHADDuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(92)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VRHADDuv4i16, MVT::v4i16);
@@ -18700,8 +18539,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VQADDsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(64)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VQADDsv4i16, MVT::v4i16);
@@ -18713,8 +18552,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VQADDuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(65)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VQADDuv4i16, MVT::v4i16);
@@ -18726,8 +18565,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VADDHNv4i16:v4i16 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VADDHNv4i16, MVT::v4i16);
@@ -18739,8 +18578,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VRADDHNv4i16:v4i16 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(88)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VRADDHNv4i16, MVT::v4i16);
@@ -18752,8 +18591,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VQDMULHv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(68)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VQDMULHv4i16, MVT::v4i16);
@@ -18765,8 +18604,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VQRDMULHv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(74)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VQRDMULHv4i16, MVT::v4i16);
@@ -18778,8 +18617,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VHSUBsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(30)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VHSUBsv4i16, MVT::v4i16);
@@ -18791,8 +18630,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VHSUBuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(31)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VHSUBuv4i16, MVT::v4i16);
@@ -18804,8 +18643,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VQSUBsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(86)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VQSUBsv4i16, MVT::v4i16);
@@ -18817,8 +18656,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VQSUBuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(87)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VQSUBuv4i16, MVT::v4i16);
@@ -18830,8 +18669,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VSUBHNv4i16:v4i16 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(112)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VSUBHNv4i16, MVT::v4i16);
@@ -18843,8 +18682,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VRSUBHNv4i16:v4i16 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(98)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VRSUBHNv4i16, MVT::v4i16);
@@ -18856,8 +18695,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VABDsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(9)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VABDsv4i16, MVT::v4i16);
@@ -18869,8 +18708,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VABDuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(10)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VABDuv4i16, MVT::v4i16);
@@ -18882,9 +18721,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VABAsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(5)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16 &&
N3.getValueType() == MVT::v4i16) {
@@ -18897,9 +18736,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VABAuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(6)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16 &&
N3.getValueType() == MVT::v4i16) {
@@ -18912,8 +18751,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VMAXsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(39)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VMAXsv4i16, MVT::v4i16);
@@ -18925,8 +18764,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VMAXuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(40)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VMAXuv4i16, MVT::v4i16);
@@ -18938,8 +18777,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VMINsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(41)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VMINsv4i16, MVT::v4i16);
@@ -18951,8 +18790,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VMINuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(42)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VMINuv4i16, MVT::v4i16);
@@ -18964,8 +18803,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VPADDi16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(56)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VPADDi16, MVT::v4i16);
@@ -18977,7 +18816,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VPADDLsv8i8:v4i16 DPR:v8i8:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(57)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_222(N, ARM::VPADDLsv8i8, MVT::v4i16);
return Result;
@@ -18988,7 +18827,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VPADDLuv8i8:v4i16 DPR:v8i8:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(58)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_222(N, ARM::VPADDLuv8i8, MVT::v4i16);
return Result;
@@ -18999,8 +18838,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VPADALsv8i8:v4i16 DPR:v4i16:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(54)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VPADALsv8i8, MVT::v4i16);
@@ -19012,8 +18851,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VPADALuv8i8:v4i16 DPR:v4i16:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(55)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VPADALuv8i8, MVT::v4i16);
@@ -19025,8 +18864,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VPMAXs16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(59)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VPMAXs16, MVT::v4i16);
@@ -19038,8 +18877,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VPMAXu16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(60)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VPMAXu16, MVT::v4i16);
@@ -19051,8 +18890,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VPMINs16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(61)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VPMINs16, MVT::v4i16);
@@ -19064,8 +18903,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VPMINu16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(62)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VPMINu16, MVT::v4i16);
@@ -19077,8 +18916,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VSHLsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(103)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VSHLsv4i16, MVT::v4i16);
@@ -19090,8 +18929,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VSHLuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(104)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VSHLuv4i16, MVT::v4i16);
@@ -19103,8 +18942,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VRSHLsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(94)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VRSHLsv4i16, MVT::v4i16);
@@ -19116,8 +18955,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VRSHLuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(95)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VRSHLuv4i16, MVT::v4i16);
@@ -19129,8 +18968,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VQSHLsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(83)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VQSHLsv4i16, MVT::v4i16);
@@ -19142,8 +18981,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VQSHLuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(85)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VQSHLuv4i16, MVT::v4i16);
@@ -19155,8 +18994,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VQRSHLsv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(78)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VQRSHLsv4i16, MVT::v4i16);
@@ -19168,8 +19007,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VQRSHLuv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(79)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VQRSHLuv4i16, MVT::v4i16);
@@ -19181,7 +19020,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VABSv4i16:v4i16 DPR:v4i16:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(11)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_222(N, ARM::VABSv4i16, MVT::v4i16);
return Result;
@@ -19192,7 +19031,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VQABSv4i16:v4i16 DPR:v4i16:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(63)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_222(N, ARM::VQABSv4i16, MVT::v4i16);
return Result;
@@ -19203,7 +19042,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VQNEGv4i16:v4i16 DPR:v4i16:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(73)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_222(N, ARM::VQNEGv4i16, MVT::v4i16);
return Result;
@@ -19214,7 +19053,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VCLSv4i16:v4i16 DPR:v4i16:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(21)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_222(N, ARM::VCLSv4i16, MVT::v4i16);
return Result;
@@ -19225,7 +19064,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VCLZv4i16:v4i16 DPR:v4i16:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(22)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_222(N, ARM::VCLZv4i16, MVT::v4i16);
return Result;
@@ -19236,7 +19075,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VMOVNv4i16:v4i16 QPR:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(49)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_222(N, ARM::VMOVNv4i16, MVT::v4i16);
return Result;
@@ -19247,7 +19086,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VQMOVNsv4i16:v4i16 QPR:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(70)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_222(N, ARM::VQMOVNsv4i16, MVT::v4i16);
return Result;
@@ -19258,7 +19097,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VQMOVNuv4i16:v4i16 QPR:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(72)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_222(N, ARM::VQMOVNuv4i16, MVT::v4i16);
return Result;
@@ -19269,7 +19108,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
// Emits: (VQMOVNsuv4i16:v4i16 QPR:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(71)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_222(N, ARM::VQMOVNsuv4i16, MVT::v4i16);
return Result;
@@ -19282,59 +19121,59 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_228(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
+DISABLE_INLINE SDNode *Emit_228(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N21)->getZExtValue()), MVT::i32);
SDValue Tmp5 = Transform_DSubReg_i16_reg(Tmp4.getNode());
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N20, Tmp5), 0);
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N20, Tmp5), 0);
SDValue Tmp7 = Transform_SubReg_i16_lane(Tmp4.getNode());
SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { N1, Tmp6, Tmp7, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
}
-DISABLE_INLINE SDNode *Emit_229(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_229(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N2, N1, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_230(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_230(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N2, N1, N3, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_231(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_231(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
SDValue Tmp5 = Transform_DSubReg_i16_reg(Tmp4.getNode());
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N10, Tmp5), 0);
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N10, Tmp5), 0);
SDValue Tmp7 = Transform_SubReg_i16_lane(Tmp4.getNode());
SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { N2, Tmp6, Tmp7, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -19342,12 +19181,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VQDMULHslv8i16:v8i16 QPR:v8i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(68)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- if (N21.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ if (N21.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16 &&
N20.getValueType() == MVT::v4i16) {
@@ -19361,12 +19200,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VQRDMULHslv8i16:v8i16 QPR:v8i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(74)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- if (N21.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ if (N21.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16 &&
N20.getValueType() == MVT::v4i16) {
@@ -19380,12 +19219,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VQDMULHslv8i16:v8i16 QPR:v8i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(68)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N10.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v8i16) {
@@ -19400,12 +19239,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VQRDMULHslv8i16:v8i16 QPR:v8i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(74)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N10.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v8i16) {
@@ -19418,8 +19257,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -19427,12 +19266,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VQDMULHslv8i16:v8i16 QPR:v8i16:$src1, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src2, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
// Pattern complexity = 14 cost = 2 size = 0
if (CN1 == INT64_C(68)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- if (N21.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ if (N21.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16 &&
N20.getValueType() == MVT::v8i16) {
@@ -19446,12 +19285,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VQRDMULHslv8i16:v8i16 QPR:v8i16:$src1, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src2, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
// Pattern complexity = 14 cost = 2 size = 0
if (CN1 == INT64_C(74)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- if (N21.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ if (N21.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16 &&
N20.getValueType() == MVT::v8i16) {
@@ -19465,12 +19304,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VQDMULHslv8i16:v8i16 QPR:v8i16:$src1, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src2, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
// Pattern complexity = 14 cost = 2 size = 0
if (CN1 == INT64_C(68)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N10.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
@@ -19485,12 +19324,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VQRDMULHslv8i16:v8i16 QPR:v8i16:$src1, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src2, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
// Pattern complexity = 14 cost = 2 size = 0
if (CN1 == INT64_C(74)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N10.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
@@ -19503,8 +19342,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -19512,8 +19351,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VADDLsv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(17)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VADDLsv8i16, MVT::v8i16);
@@ -19525,8 +19364,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VADDLuv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(18)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VADDLuv8i16, MVT::v8i16);
@@ -19538,8 +19377,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VADDWsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(19)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VADDWsv8i16, MVT::v8i16);
@@ -19551,8 +19390,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VADDWuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(20)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VADDWuv8i16, MVT::v8i16);
@@ -19564,8 +19403,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VHADDsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(28)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VHADDsv8i16, MVT::v8i16);
@@ -19577,8 +19416,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VHADDuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(29)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VHADDuv8i16, MVT::v8i16);
@@ -19590,8 +19429,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VRHADDsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(91)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VRHADDsv8i16, MVT::v8i16);
@@ -19603,8 +19442,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VRHADDuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(92)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VRHADDuv8i16, MVT::v8i16);
@@ -19616,8 +19455,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VQADDsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(64)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VQADDsv8i16, MVT::v8i16);
@@ -19629,8 +19468,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VQADDuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(65)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VQADDuv8i16, MVT::v8i16);
@@ -19642,8 +19481,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VQDMULHv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(68)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VQDMULHv8i16, MVT::v8i16);
@@ -19655,8 +19494,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VQRDMULHv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(74)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VQRDMULHv8i16, MVT::v8i16);
@@ -19668,8 +19507,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VMULLsv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(51)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VMULLsv8i16, MVT::v8i16);
@@ -19681,8 +19520,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VMULLuv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(52)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VMULLuv8i16, MVT::v8i16);
@@ -19694,8 +19533,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VMULLp:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(50)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VMULLp, MVT::v8i16);
@@ -19707,9 +19546,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VMLALsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(43)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i8 &&
N3.getValueType() == MVT::v8i8) {
@@ -19722,9 +19561,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VMLALuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(44)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i8 &&
N3.getValueType() == MVT::v8i8) {
@@ -19737,9 +19576,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VMLSLsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(45)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i8 &&
N3.getValueType() == MVT::v8i8) {
@@ -19752,9 +19591,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VMLSLuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(46)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i8 &&
N3.getValueType() == MVT::v8i8) {
@@ -19767,8 +19606,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VSUBLsv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(113)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VSUBLsv8i16, MVT::v8i16);
@@ -19780,8 +19619,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VSUBLuv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(114)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VSUBLuv8i16, MVT::v8i16);
@@ -19793,8 +19632,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VSUBWsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(115)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VSUBWsv8i16, MVT::v8i16);
@@ -19806,8 +19645,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VSUBWuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(116)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VSUBWuv8i16, MVT::v8i16);
@@ -19819,8 +19658,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VHSUBsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(30)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VHSUBsv8i16, MVT::v8i16);
@@ -19832,8 +19671,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VHSUBuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(31)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VHSUBuv8i16, MVT::v8i16);
@@ -19845,8 +19684,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VQSUBsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(86)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VQSUBsv8i16, MVT::v8i16);
@@ -19858,8 +19697,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VQSUBuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(87)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VQSUBuv8i16, MVT::v8i16);
@@ -19871,8 +19710,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VABDsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(9)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VABDsv8i16, MVT::v8i16);
@@ -19884,8 +19723,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VABDuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(10)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VABDuv8i16, MVT::v8i16);
@@ -19897,8 +19736,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VABDLsv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(7)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VABDLsv8i16, MVT::v8i16);
@@ -19910,8 +19749,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VABDLuv8i16:v8i16 DPR:v8i8:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_220(N, ARM::VABDLuv8i16, MVT::v8i16);
@@ -19923,9 +19762,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VABAsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, QPR:v8i16:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(5)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16 &&
N3.getValueType() == MVT::v8i16) {
@@ -19938,9 +19777,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VABAuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, QPR:v8i16:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(6)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16 &&
N3.getValueType() == MVT::v8i16) {
@@ -19953,9 +19792,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VABALsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(3)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i8 &&
N3.getValueType() == MVT::v8i8) {
@@ -19968,9 +19807,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VABALuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(4)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i8 &&
N3.getValueType() == MVT::v8i8) {
@@ -19983,8 +19822,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VMAXsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(39)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VMAXsv8i16, MVT::v8i16);
@@ -19996,8 +19835,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VMAXuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(40)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VMAXuv8i16, MVT::v8i16);
@@ -20009,8 +19848,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VMINsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(41)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VMINsv8i16, MVT::v8i16);
@@ -20022,8 +19861,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VMINuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(42)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VMINuv8i16, MVT::v8i16);
@@ -20035,7 +19874,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VPADDLsv16i8:v8i16 QPR:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(57)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_222(N, ARM::VPADDLsv16i8, MVT::v8i16);
return Result;
@@ -20046,7 +19885,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VPADDLuv16i8:v8i16 QPR:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(58)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_222(N, ARM::VPADDLuv16i8, MVT::v8i16);
return Result;
@@ -20057,8 +19896,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VPADALsv16i8:v8i16 QPR:v8i16:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(54)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VPADALsv16i8, MVT::v8i16);
@@ -20070,8 +19909,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VPADALuv16i8:v8i16 QPR:v8i16:$src1, QPR:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(55)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_220(N, ARM::VPADALuv16i8, MVT::v8i16);
@@ -20083,8 +19922,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VSHLsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(103)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VSHLsv8i16, MVT::v8i16);
@@ -20096,8 +19935,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VSHLuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(104)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VSHLuv8i16, MVT::v8i16);
@@ -20109,8 +19948,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VRSHLsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(94)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VRSHLsv8i16, MVT::v8i16);
@@ -20122,8 +19961,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VRSHLuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(95)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VRSHLuv8i16, MVT::v8i16);
@@ -20135,8 +19974,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VQSHLsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(83)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VQSHLsv8i16, MVT::v8i16);
@@ -20148,8 +19987,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VQSHLuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(85)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VQSHLuv8i16, MVT::v8i16);
@@ -20161,8 +20000,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VQRSHLsv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(78)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VQRSHLsv8i16, MVT::v8i16);
@@ -20174,8 +20013,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VQRSHLuv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(79)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VQRSHLuv8i16, MVT::v8i16);
@@ -20187,7 +20026,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VABSv8i16:v8i16 QPR:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(11)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_222(N, ARM::VABSv8i16, MVT::v8i16);
return Result;
@@ -20198,7 +20037,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VQABSv8i16:v8i16 QPR:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(63)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_222(N, ARM::VQABSv8i16, MVT::v8i16);
return Result;
@@ -20209,7 +20048,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VQNEGv8i16:v8i16 QPR:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(73)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_222(N, ARM::VQNEGv8i16, MVT::v8i16);
return Result;
@@ -20220,7 +20059,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VCLSv8i16:v8i16 QPR:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(21)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_222(N, ARM::VCLSv8i16, MVT::v8i16);
return Result;
@@ -20231,7 +20070,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VCLZv8i16:v8i16 QPR:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(22)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_222(N, ARM::VCLZv8i16, MVT::v8i16);
return Result;
@@ -20242,7 +20081,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VMOVLsv8i16:v8i16 DPR:v8i8:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(47)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_222(N, ARM::VMOVLsv8i16, MVT::v8i16);
return Result;
@@ -20253,7 +20092,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VMOVLuv8i16:v8i16 DPR:v8i8:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(48)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i8) {
SDNode *Result = Emit_222(N, ARM::VMOVLuv8i16, MVT::v8i16);
return Result;
@@ -20264,8 +20103,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VADDWsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(19)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_229(N, ARM::VADDWsv8i16, MVT::v8i16);
@@ -20277,8 +20116,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VADDWuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(20)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_229(N, ARM::VADDWuv8i16, MVT::v8i16);
@@ -20290,9 +20129,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VMLALsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(43)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i16 &&
N3.getValueType() == MVT::v8i8) {
@@ -20305,9 +20144,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VMLALuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(44)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i16 &&
N3.getValueType() == MVT::v8i8) {
@@ -20320,9 +20159,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VMLSLsv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(45)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i16 &&
N3.getValueType() == MVT::v8i8) {
@@ -20335,9 +20174,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
// Emits: (VMLSLuv8i16:v8i16 QPR:v8i16:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(46)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v8i8 &&
N2.getValueType() == MVT::v8i16 &&
N3.getValueType() == MVT::v8i8) {
@@ -20352,20 +20191,20 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_232(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_232(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -20373,12 +20212,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VQDMULHslv2i32:v2i32 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(68)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- if (N21.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ if (N21.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32 &&
N20.getValueType() == MVT::v2i32) {
@@ -20392,12 +20231,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VQRDMULHslv2i32:v2i32 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(74)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- if (N21.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ if (N21.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32 &&
N20.getValueType() == MVT::v2i32) {
@@ -20411,12 +20250,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VQDMULHslv2i32:v2i32 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(68)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N10.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
@@ -20431,12 +20270,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VQRDMULHslv2i32:v2i32 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(74)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N10.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
@@ -20451,9 +20290,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VCVTf2xsd:v2i32 DPR:v2f32:$src, (imm:i32):$SIMM)
// Pattern complexity = 11 cost = 1 size = 0
if (CN1 == INT64_C(24)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_232(N, ARM::VCVTf2xsd, MVT::v2i32);
return Result;
@@ -20464,9 +20303,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VCVTf2xud:v2i32 DPR:v2f32:$src, (imm:i32):$SIMM)
// Pattern complexity = 11 cost = 1 size = 0
if (CN1 == INT64_C(25)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_232(N, ARM::VCVTf2xud, MVT::v2i32);
return Result;
@@ -20477,8 +20316,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VHADDsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(28)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VHADDsv2i32, MVT::v2i32);
@@ -20490,8 +20329,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VHADDuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(29)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VHADDuv2i32, MVT::v2i32);
@@ -20503,8 +20342,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VRHADDsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(91)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VRHADDsv2i32, MVT::v2i32);
@@ -20516,8 +20355,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VRHADDuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(92)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VRHADDuv2i32, MVT::v2i32);
@@ -20529,8 +20368,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VQADDsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(64)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VQADDsv2i32, MVT::v2i32);
@@ -20542,8 +20381,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VQADDuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(65)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VQADDuv2i32, MVT::v2i32);
@@ -20555,8 +20394,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VADDHNv2i32:v2i32 QPR:v2i64:$src1, QPR:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_220(N, ARM::VADDHNv2i32, MVT::v2i32);
@@ -20568,8 +20407,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VRADDHNv2i32:v2i32 QPR:v2i64:$src1, QPR:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(88)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_220(N, ARM::VRADDHNv2i32, MVT::v2i32);
@@ -20581,8 +20420,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VQDMULHv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(68)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VQDMULHv2i32, MVT::v2i32);
@@ -20594,8 +20433,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VQRDMULHv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(74)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VQRDMULHv2i32, MVT::v2i32);
@@ -20607,8 +20446,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VHSUBsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(30)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VHSUBsv2i32, MVT::v2i32);
@@ -20620,8 +20459,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VHSUBuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(31)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VHSUBuv2i32, MVT::v2i32);
@@ -20633,8 +20472,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VQSUBsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(86)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VQSUBsv2i32, MVT::v2i32);
@@ -20646,8 +20485,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VQSUBuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(87)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VQSUBuv2i32, MVT::v2i32);
@@ -20659,8 +20498,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VSUBHNv2i32:v2i32 QPR:v2i64:$src1, QPR:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(112)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_220(N, ARM::VSUBHNv2i32, MVT::v2i32);
@@ -20672,8 +20511,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VRSUBHNv2i32:v2i32 QPR:v2i64:$src1, QPR:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(98)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_220(N, ARM::VRSUBHNv2i32, MVT::v2i32);
@@ -20701,8 +20540,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VABDsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(9)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VABDsv2i32, MVT::v2i32);
@@ -20714,8 +20553,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VABDuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(10)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VABDuv2i32, MVT::v2i32);
@@ -20727,9 +20566,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VABAsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(5)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32 &&
N3.getValueType() == MVT::v2i32) {
@@ -20742,9 +20581,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VABAuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(6)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32 &&
N3.getValueType() == MVT::v2i32) {
@@ -20757,8 +20596,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VMAXsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(39)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VMAXsv2i32, MVT::v2i32);
@@ -20770,8 +20609,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VMAXuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(40)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VMAXuv2i32, MVT::v2i32);
@@ -20783,8 +20622,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VMINsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(41)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VMINsv2i32, MVT::v2i32);
@@ -20796,8 +20635,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VMINuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(42)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VMINuv2i32, MVT::v2i32);
@@ -20809,8 +20648,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VPADDi32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(56)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VPADDi32, MVT::v2i32);
@@ -20822,7 +20661,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VPADDLsv4i16:v2i32 DPR:v4i16:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(57)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_222(N, ARM::VPADDLsv4i16, MVT::v2i32);
return Result;
@@ -20833,7 +20672,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VPADDLuv4i16:v2i32 DPR:v4i16:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(58)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_222(N, ARM::VPADDLuv4i16, MVT::v2i32);
return Result;
@@ -20844,8 +20683,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VPADALsv4i16:v2i32 DPR:v2i32:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(54)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VPADALsv4i16, MVT::v2i32);
@@ -20857,8 +20696,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VPADALuv4i16:v2i32 DPR:v2i32:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(55)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VPADALuv4i16, MVT::v2i32);
@@ -20870,8 +20709,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VPMAXs32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(59)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VPMAXs32, MVT::v2i32);
@@ -20883,8 +20722,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VPMAXu32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(60)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VPMAXu32, MVT::v2i32);
@@ -20896,8 +20735,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VPMINs32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(61)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VPMINs32, MVT::v2i32);
@@ -20909,8 +20748,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VPMINu32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(62)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VPMINu32, MVT::v2i32);
@@ -20922,7 +20761,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VRECPEd:v2i32 DPR:v2i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(89)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_222(N, ARM::VRECPEd, MVT::v2i32);
return Result;
@@ -20933,7 +20772,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VRSQRTEd:v2i32 DPR:v2i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(96)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_222(N, ARM::VRSQRTEd, MVT::v2i32);
return Result;
@@ -20944,8 +20783,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VSHLsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(103)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VSHLsv2i32, MVT::v2i32);
@@ -20957,8 +20796,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VSHLuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(104)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VSHLuv2i32, MVT::v2i32);
@@ -20970,8 +20809,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VRSHLsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(94)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VRSHLsv2i32, MVT::v2i32);
@@ -20983,8 +20822,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VRSHLuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(95)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VRSHLuv2i32, MVT::v2i32);
@@ -20996,8 +20835,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VQSHLsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(83)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VQSHLsv2i32, MVT::v2i32);
@@ -21009,8 +20848,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VQSHLuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(85)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VQSHLuv2i32, MVT::v2i32);
@@ -21022,8 +20861,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VQRSHLsv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(78)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VQRSHLsv2i32, MVT::v2i32);
@@ -21035,8 +20874,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VQRSHLuv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(79)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VQRSHLuv2i32, MVT::v2i32);
@@ -21048,7 +20887,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VABSv2i32:v2i32 DPR:v2i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(11)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_222(N, ARM::VABSv2i32, MVT::v2i32);
return Result;
@@ -21059,7 +20898,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VQABSv2i32:v2i32 DPR:v2i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(63)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_222(N, ARM::VQABSv2i32, MVT::v2i32);
return Result;
@@ -21070,7 +20909,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VQNEGv2i32:v2i32 DPR:v2i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(73)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_222(N, ARM::VQNEGv2i32, MVT::v2i32);
return Result;
@@ -21081,7 +20920,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VCLSv2i32:v2i32 DPR:v2i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(21)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_222(N, ARM::VCLSv2i32, MVT::v2i32);
return Result;
@@ -21092,7 +20931,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VCLZv2i32:v2i32 DPR:v2i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(22)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_222(N, ARM::VCLZv2i32, MVT::v2i32);
return Result;
@@ -21103,7 +20942,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VMOVNv2i32:v2i32 QPR:v2i64:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(49)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_222(N, ARM::VMOVNv2i32, MVT::v2i32);
return Result;
@@ -21114,7 +20953,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VQMOVNsv2i32:v2i32 QPR:v2i64:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(70)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_222(N, ARM::VQMOVNsv2i32, MVT::v2i32);
return Result;
@@ -21125,7 +20964,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VQMOVNuv2i32:v2i32 QPR:v2i64:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(72)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_222(N, ARM::VQMOVNuv2i32, MVT::v2i32);
return Result;
@@ -21136,7 +20975,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
// Emits: (VQMOVNsuv2i32:v2i32 QPR:v2i64:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(71)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_222(N, ARM::VQMOVNsuv2i32, MVT::v2i32);
return Result;
@@ -21149,66 +20988,66 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_233(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
+DISABLE_INLINE SDNode *Emit_233(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N31)->getZExtValue()), MVT::i32);
SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, N2, N30, Tmp5, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_234(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_234(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N21)->getZExtValue()), MVT::i32);
SDValue Tmp5 = Transform_DSubReg_i32_reg(Tmp4.getNode());
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N20, Tmp5), 0);
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N20, Tmp5), 0);
SDValue Tmp7 = Transform_SubReg_i32_lane(Tmp4.getNode());
SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { N1, Tmp6, Tmp7, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
-}
-DISABLE_INLINE SDNode *Emit_235(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
+}
+DISABLE_INLINE SDNode *Emit_235(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N31)->getZExtValue()), MVT::i32);
SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N2, N1, N30, Tmp5, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_236(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_236(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
SDValue Tmp5 = Transform_DSubReg_i32_reg(Tmp4.getNode());
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N10, Tmp5), 0);
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N10, Tmp5), 0);
SDValue Tmp7 = Transform_SubReg_i32_lane(Tmp4.getNode());
SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { N2, Tmp6, Tmp7, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -21216,12 +21055,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQDMULHslv4i32:v4i32 QPR:v4i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(68)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- if (N21.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ if (N21.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32 &&
N20.getValueType() == MVT::v2i32) {
@@ -21235,12 +21074,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQRDMULHslv4i32:v4i32 QPR:v4i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(74)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- if (N21.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ if (N21.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32 &&
N20.getValueType() == MVT::v2i32) {
@@ -21254,12 +21093,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMULLslsv4i16:v4i32 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(51)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- if (N21.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ if (N21.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16 &&
N20.getValueType() == MVT::v4i16) {
@@ -21273,12 +21112,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMULLsluv4i16:v4i32 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(52)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- if (N21.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ if (N21.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16 &&
N20.getValueType() == MVT::v4i16) {
@@ -21292,12 +21131,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQDMULLslv4i16:v4i32 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(69)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- if (N21.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ if (N21.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16 &&
N20.getValueType() == MVT::v4i16) {
@@ -21311,13 +21150,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMLALslsv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(43)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i16 &&
N3.getValueType() == MVT::v4i16 &&
@@ -21332,13 +21171,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMLALsluv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(44)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i16 &&
N3.getValueType() == MVT::v4i16 &&
@@ -21353,13 +21192,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQDMLALslv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(66)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i16 &&
N3.getValueType() == MVT::v4i16 &&
@@ -21374,13 +21213,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMLSLslsv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(45)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i16 &&
N3.getValueType() == MVT::v4i16 &&
@@ -21395,13 +21234,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMLSLsluv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(46)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i16 &&
N3.getValueType() == MVT::v4i16 &&
@@ -21416,13 +21255,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQDMLSLslv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(67)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i16 &&
N3.getValueType() == MVT::v4i16 &&
@@ -21437,12 +21276,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQDMULHslv4i32:v4i32 QPR:v4i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(68)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N10.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v4i32) {
@@ -21457,12 +21296,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQRDMULHslv4i32:v4i32 QPR:v4i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(74)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N10.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v4i32) {
@@ -21477,12 +21316,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMULLslsv4i16:v4i32 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(51)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N10.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
@@ -21497,12 +21336,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMULLsluv4i16:v4i32 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(52)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N10.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
@@ -21517,12 +21356,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQDMULLslv4i16:v4i32 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(69)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N10.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
@@ -21537,13 +21376,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMLALslsv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(43)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i32 &&
N3.getValueType() == MVT::v4i16 &&
@@ -21558,13 +21397,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMLALsluv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(44)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i32 &&
N3.getValueType() == MVT::v4i16 &&
@@ -21579,13 +21418,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQDMLALslv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(66)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i32 &&
N3.getValueType() == MVT::v4i16 &&
@@ -21600,13 +21439,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMLSLslsv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(45)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i32 &&
N3.getValueType() == MVT::v4i16 &&
@@ -21621,13 +21460,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMLSLsluv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(46)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i32 &&
N3.getValueType() == MVT::v4i16 &&
@@ -21642,13 +21481,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQDMLSLslv4i16:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(67)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i32 &&
N3.getValueType() == MVT::v4i16 &&
@@ -21661,8 +21500,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -21670,12 +21509,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQDMULHslv4i32:v4i32 QPR:v4i32:$src1, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 14 cost = 2 size = 0
if (CN1 == INT64_C(68)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- if (N21.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ if (N21.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32 &&
N20.getValueType() == MVT::v4i32) {
@@ -21689,12 +21528,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQRDMULHslv4i32:v4i32 QPR:v4i32:$src1, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 14 cost = 2 size = 0
if (CN1 == INT64_C(74)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- if (N21.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ if (N21.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32 &&
N20.getValueType() == MVT::v4i32) {
@@ -21708,12 +21547,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQDMULHslv4i32:v4i32 QPR:v4i32:$src1, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 14 cost = 2 size = 0
if (CN1 == INT64_C(68)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N10.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
@@ -21728,12 +21567,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQRDMULHslv4i32:v4i32 QPR:v4i32:$src1, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 14 cost = 2 size = 0
if (CN1 == INT64_C(74)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N10.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
@@ -21746,8 +21585,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -21755,9 +21594,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VCVTf2xsq:v4i32 QPR:v4f32:$src, (imm:i32):$SIMM)
// Pattern complexity = 11 cost = 1 size = 0
if (CN1 == INT64_C(24)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_232(N, ARM::VCVTf2xsq, MVT::v4i32);
return Result;
@@ -21768,9 +21607,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VCVTf2xuq:v4i32 QPR:v4f32:$src, (imm:i32):$SIMM)
// Pattern complexity = 11 cost = 1 size = 0
if (CN1 == INT64_C(25)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_232(N, ARM::VCVTf2xuq, MVT::v4i32);
return Result;
@@ -21781,8 +21620,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VADDLsv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(17)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VADDLsv4i32, MVT::v4i32);
@@ -21794,8 +21633,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VADDLuv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(18)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VADDLuv4i32, MVT::v4i32);
@@ -21807,8 +21646,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VADDWsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(19)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VADDWsv4i32, MVT::v4i32);
@@ -21820,8 +21659,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VADDWuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(20)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VADDWuv4i32, MVT::v4i32);
@@ -21833,8 +21672,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VHADDsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(28)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VHADDsv4i32, MVT::v4i32);
@@ -21846,8 +21685,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VHADDuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(29)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VHADDuv4i32, MVT::v4i32);
@@ -21859,8 +21698,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VRHADDsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(91)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VRHADDsv4i32, MVT::v4i32);
@@ -21872,8 +21711,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VRHADDuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(92)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VRHADDuv4i32, MVT::v4i32);
@@ -21885,8 +21724,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQADDsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(64)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VQADDsv4i32, MVT::v4i32);
@@ -21898,8 +21737,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQADDuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(65)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VQADDuv4i32, MVT::v4i32);
@@ -21911,8 +21750,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQDMULHv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(68)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VQDMULHv4i32, MVT::v4i32);
@@ -21924,8 +21763,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQRDMULHv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(74)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VQRDMULHv4i32, MVT::v4i32);
@@ -21937,8 +21776,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMULLsv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(51)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VMULLsv4i32, MVT::v4i32);
@@ -21950,8 +21789,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMULLuv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(52)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VMULLuv4i32, MVT::v4i32);
@@ -21963,8 +21802,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQDMULLv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(69)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VQDMULLv4i32, MVT::v4i32);
@@ -21976,9 +21815,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMLALsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(43)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i16 &&
N3.getValueType() == MVT::v4i16) {
@@ -21991,9 +21830,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMLALuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(44)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i16 &&
N3.getValueType() == MVT::v4i16) {
@@ -22006,9 +21845,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQDMLALv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(66)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i16 &&
N3.getValueType() == MVT::v4i16) {
@@ -22021,9 +21860,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMLSLsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(45)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i16 &&
N3.getValueType() == MVT::v4i16) {
@@ -22036,9 +21875,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMLSLuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(46)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i16 &&
N3.getValueType() == MVT::v4i16) {
@@ -22051,9 +21890,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQDMLSLv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(67)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i16 &&
N3.getValueType() == MVT::v4i16) {
@@ -22066,8 +21905,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VSUBLsv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(113)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VSUBLsv4i32, MVT::v4i32);
@@ -22079,8 +21918,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VSUBLuv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(114)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VSUBLuv4i32, MVT::v4i32);
@@ -22092,8 +21931,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VSUBWsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(115)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VSUBWsv4i32, MVT::v4i32);
@@ -22105,8 +21944,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VSUBWuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(116)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VSUBWuv4i32, MVT::v4i32);
@@ -22118,8 +21957,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VHSUBsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(30)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VHSUBsv4i32, MVT::v4i32);
@@ -22131,8 +21970,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VHSUBuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(31)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VHSUBuv4i32, MVT::v4i32);
@@ -22144,8 +21983,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQSUBsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(86)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VQSUBsv4i32, MVT::v4i32);
@@ -22157,8 +21996,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQSUBuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(87)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VQSUBuv4i32, MVT::v4i32);
@@ -22186,8 +22025,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VABDsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(9)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VABDsv4i32, MVT::v4i32);
@@ -22199,8 +22038,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VABDuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(10)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VABDuv4i32, MVT::v4i32);
@@ -22212,8 +22051,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VABDLsv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(7)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VABDLsv4i32, MVT::v4i32);
@@ -22225,8 +22064,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VABDLuv4i32:v4i32 DPR:v4i16:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_220(N, ARM::VABDLuv4i32, MVT::v4i32);
@@ -22238,9 +22077,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VABAsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(5)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32 &&
N3.getValueType() == MVT::v4i32) {
@@ -22253,9 +22092,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VABAuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(6)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32 &&
N3.getValueType() == MVT::v4i32) {
@@ -22268,9 +22107,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VABALsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(3)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i16 &&
N3.getValueType() == MVT::v4i16) {
@@ -22283,9 +22122,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VABALuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(4)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i16 &&
N3.getValueType() == MVT::v4i16) {
@@ -22298,8 +22137,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMAXsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(39)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VMAXsv4i32, MVT::v4i32);
@@ -22311,8 +22150,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMAXuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(40)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VMAXuv4i32, MVT::v4i32);
@@ -22324,8 +22163,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMINsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(41)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VMINsv4i32, MVT::v4i32);
@@ -22337,8 +22176,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMINuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(42)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VMINuv4i32, MVT::v4i32);
@@ -22350,7 +22189,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VPADDLsv8i16:v4i32 QPR:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(57)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_222(N, ARM::VPADDLsv8i16, MVT::v4i32);
return Result;
@@ -22361,7 +22200,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VPADDLuv8i16:v4i32 QPR:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(58)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_222(N, ARM::VPADDLuv8i16, MVT::v4i32);
return Result;
@@ -22372,8 +22211,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VPADALsv8i16:v4i32 QPR:v4i32:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(54)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VPADALsv8i16, MVT::v4i32);
@@ -22385,8 +22224,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VPADALuv8i16:v4i32 QPR:v4i32:$src1, QPR:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(55)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_220(N, ARM::VPADALuv8i16, MVT::v4i32);
@@ -22398,7 +22237,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VRECPEq:v4i32 QPR:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(89)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_222(N, ARM::VRECPEq, MVT::v4i32);
return Result;
@@ -22409,7 +22248,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VRSQRTEq:v4i32 QPR:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(96)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_222(N, ARM::VRSQRTEq, MVT::v4i32);
return Result;
@@ -22420,8 +22259,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VSHLsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(103)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VSHLsv4i32, MVT::v4i32);
@@ -22433,8 +22272,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VSHLuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(104)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VSHLuv4i32, MVT::v4i32);
@@ -22446,8 +22285,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VRSHLsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(94)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VRSHLsv4i32, MVT::v4i32);
@@ -22459,8 +22298,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VRSHLuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(95)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VRSHLuv4i32, MVT::v4i32);
@@ -22472,8 +22311,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQSHLsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(83)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VQSHLsv4i32, MVT::v4i32);
@@ -22485,8 +22324,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQSHLuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(85)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VQSHLuv4i32, MVT::v4i32);
@@ -22498,8 +22337,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQRSHLsv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(78)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VQRSHLsv4i32, MVT::v4i32);
@@ -22511,8 +22350,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQRSHLuv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(79)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VQRSHLuv4i32, MVT::v4i32);
@@ -22524,7 +22363,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VABSv4i32:v4i32 QPR:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(11)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_222(N, ARM::VABSv4i32, MVT::v4i32);
return Result;
@@ -22535,7 +22374,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQABSv4i32:v4i32 QPR:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(63)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_222(N, ARM::VQABSv4i32, MVT::v4i32);
return Result;
@@ -22546,7 +22385,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQNEGv4i32:v4i32 QPR:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(73)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_222(N, ARM::VQNEGv4i32, MVT::v4i32);
return Result;
@@ -22557,7 +22396,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VCLSv4i32:v4i32 QPR:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(21)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_222(N, ARM::VCLSv4i32, MVT::v4i32);
return Result;
@@ -22568,7 +22407,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VCLZv4i32:v4i32 QPR:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(22)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_222(N, ARM::VCLZv4i32, MVT::v4i32);
return Result;
@@ -22579,7 +22418,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMOVLsv4i32:v4i32 DPR:v4i16:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(47)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_222(N, ARM::VMOVLsv4i32, MVT::v4i32);
return Result;
@@ -22590,7 +22429,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMOVLuv4i32:v4i32 DPR:v4i16:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(48)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_222(N, ARM::VMOVLuv4i32, MVT::v4i32);
return Result;
@@ -22601,8 +22440,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VADDWsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(19)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_229(N, ARM::VADDWsv4i32, MVT::v4i32);
@@ -22614,8 +22453,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VADDWuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(20)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_229(N, ARM::VADDWuv4i32, MVT::v4i32);
@@ -22627,9 +22466,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMLALsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(43)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i32 &&
N3.getValueType() == MVT::v4i16) {
@@ -22642,9 +22481,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMLALuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(44)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i32 &&
N3.getValueType() == MVT::v4i16) {
@@ -22657,9 +22496,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQDMLALv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(66)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i32 &&
N3.getValueType() == MVT::v4i16) {
@@ -22672,9 +22511,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMLSLsv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(45)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i32 &&
N3.getValueType() == MVT::v4i16) {
@@ -22687,9 +22526,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VMLSLuv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(46)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i32 &&
N3.getValueType() == MVT::v4i16) {
@@ -22702,9 +22541,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
// Emits: (VQDMLSLv4i32:v4i32 QPR:v4i32:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(67)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v4i16 &&
N2.getValueType() == MVT::v4i32 &&
N3.getValueType() == MVT::v4i16) {
@@ -22719,10 +22558,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -22730,8 +22569,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
// Emits: (VQADDsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(64)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v1i64 &&
N2.getValueType() == MVT::v1i64) {
SDNode *Result = Emit_220(N, ARM::VQADDsv1i64, MVT::v1i64);
@@ -22743,8 +22582,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
// Emits: (VQADDuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(65)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v1i64 &&
N2.getValueType() == MVT::v1i64) {
SDNode *Result = Emit_220(N, ARM::VQADDuv1i64, MVT::v1i64);
@@ -22756,8 +22595,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
// Emits: (VQSUBsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(86)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v1i64 &&
N2.getValueType() == MVT::v1i64) {
SDNode *Result = Emit_220(N, ARM::VQSUBsv1i64, MVT::v1i64);
@@ -22769,8 +22608,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
// Emits: (VQSUBuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(87)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v1i64 &&
N2.getValueType() == MVT::v1i64) {
SDNode *Result = Emit_220(N, ARM::VQSUBuv1i64, MVT::v1i64);
@@ -22782,7 +22621,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
// Emits: (VPADDLsv2i32:v1i64 DPR:v2i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(57)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_222(N, ARM::VPADDLsv2i32, MVT::v1i64);
return Result;
@@ -22793,7 +22632,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
// Emits: (VPADDLuv2i32:v1i64 DPR:v2i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(58)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_222(N, ARM::VPADDLuv2i32, MVT::v1i64);
return Result;
@@ -22804,8 +22643,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
// Emits: (VPADALsv2i32:v1i64 DPR:v1i64:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(54)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v1i64 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VPADALsv2i32, MVT::v1i64);
@@ -22817,8 +22656,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
// Emits: (VPADALuv2i32:v1i64 DPR:v1i64:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(55)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v1i64 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VPADALuv2i32, MVT::v1i64);
@@ -22830,8 +22669,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
// Emits: (VSHLsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(103)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v1i64 &&
N2.getValueType() == MVT::v1i64) {
SDNode *Result = Emit_220(N, ARM::VSHLsv1i64, MVT::v1i64);
@@ -22843,8 +22682,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
// Emits: (VSHLuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(104)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v1i64 &&
N2.getValueType() == MVT::v1i64) {
SDNode *Result = Emit_220(N, ARM::VSHLuv1i64, MVT::v1i64);
@@ -22856,8 +22695,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
// Emits: (VRSHLsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(94)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v1i64 &&
N2.getValueType() == MVT::v1i64) {
SDNode *Result = Emit_220(N, ARM::VRSHLsv1i64, MVT::v1i64);
@@ -22869,8 +22708,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
// Emits: (VRSHLuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(95)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v1i64 &&
N2.getValueType() == MVT::v1i64) {
SDNode *Result = Emit_220(N, ARM::VRSHLuv1i64, MVT::v1i64);
@@ -22882,8 +22721,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
// Emits: (VQSHLsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(83)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v1i64 &&
N2.getValueType() == MVT::v1i64) {
SDNode *Result = Emit_220(N, ARM::VQSHLsv1i64, MVT::v1i64);
@@ -22895,8 +22734,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
// Emits: (VQSHLuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(85)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v1i64 &&
N2.getValueType() == MVT::v1i64) {
SDNode *Result = Emit_220(N, ARM::VQSHLuv1i64, MVT::v1i64);
@@ -22908,8 +22747,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
// Emits: (VQRSHLsv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(78)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v1i64 &&
N2.getValueType() == MVT::v1i64) {
SDNode *Result = Emit_220(N, ARM::VQRSHLsv1i64, MVT::v1i64);
@@ -22921,8 +22760,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
// Emits: (VQRSHLuv1i64:v1i64 DPR:v1i64:$src1, DPR:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(79)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v1i64 &&
N2.getValueType() == MVT::v1i64) {
SDNode *Result = Emit_220(N, ARM::VQRSHLuv1i64, MVT::v1i64);
@@ -22936,10 +22775,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -22947,12 +22786,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMULLslsv2i32:v2i64 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(51)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- if (N21.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ if (N21.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32 &&
N20.getValueType() == MVT::v2i32) {
@@ -22966,12 +22805,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMULLsluv2i32:v2i64 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(52)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- if (N21.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ if (N21.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32 &&
N20.getValueType() == MVT::v2i32) {
@@ -22985,12 +22824,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VQDMULLslv2i32:v2i64 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(69)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N20 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- if (N21.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ if (N21.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32 &&
N20.getValueType() == MVT::v2i32) {
@@ -23004,13 +22843,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMLALslsv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(43)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i32 &&
N3.getValueType() == MVT::v2i32 &&
@@ -23025,13 +22864,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMLALsluv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(44)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i32 &&
N3.getValueType() == MVT::v2i32 &&
@@ -23046,13 +22885,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VQDMLALslv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(66)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i32 &&
N3.getValueType() == MVT::v2i32 &&
@@ -23067,13 +22906,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMLSLslsv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(45)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i32 &&
N3.getValueType() == MVT::v2i32 &&
@@ -23088,13 +22927,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMLSLsluv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(46)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i32 &&
N3.getValueType() == MVT::v2i32 &&
@@ -23109,13 +22948,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VQDMLSLslv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(67)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i32 &&
N3.getValueType() == MVT::v2i32 &&
@@ -23130,12 +22969,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMULLslsv2i32:v2i64 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(51)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N10.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
@@ -23150,12 +22989,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMULLsluv2i32:v2i64 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(52)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N10.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
@@ -23170,12 +23009,12 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VQDMULLslv2i32:v2i64 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(69)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N10.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
@@ -23190,13 +23029,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMLALslsv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(43)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i64 &&
N3.getValueType() == MVT::v2i32 &&
@@ -23211,13 +23050,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMLALsluv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(44)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i64 &&
N3.getValueType() == MVT::v2i32 &&
@@ -23232,13 +23071,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VQDMLALslv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(66)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i64 &&
N3.getValueType() == MVT::v2i32 &&
@@ -23253,13 +23092,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMLSLslsv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(45)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i64 &&
N3.getValueType() == MVT::v2i32 &&
@@ -23274,13 +23113,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMLSLsluv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(46)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i64 &&
N3.getValueType() == MVT::v2i32 &&
@@ -23295,13 +23134,13 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VQDMLSLslv2i32:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 14 cost = 1 size = 0
if (CN1 == INT64_C(67)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N30 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- if (N31.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N30 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ if (N31.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i64 &&
N3.getValueType() == MVT::v2i32 &&
@@ -23316,8 +23155,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VADDLsv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(17)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VADDLsv2i64, MVT::v2i64);
@@ -23329,8 +23168,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VADDLuv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(18)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VADDLuv2i64, MVT::v2i64);
@@ -23342,8 +23181,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VADDWsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(19)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VADDWsv2i64, MVT::v2i64);
@@ -23355,8 +23194,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VADDWuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(20)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VADDWuv2i64, MVT::v2i64);
@@ -23368,8 +23207,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VQADDsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(64)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_220(N, ARM::VQADDsv2i64, MVT::v2i64);
@@ -23381,8 +23220,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VQADDuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(65)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_220(N, ARM::VQADDuv2i64, MVT::v2i64);
@@ -23394,8 +23233,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMULLsv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(51)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VMULLsv2i64, MVT::v2i64);
@@ -23407,8 +23246,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMULLuv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(52)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VMULLuv2i64, MVT::v2i64);
@@ -23420,8 +23259,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VQDMULLv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(69)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VQDMULLv2i64, MVT::v2i64);
@@ -23433,9 +23272,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMLALsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(43)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i32 &&
N3.getValueType() == MVT::v2i32) {
@@ -23448,9 +23287,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMLALuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(44)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i32 &&
N3.getValueType() == MVT::v2i32) {
@@ -23463,9 +23302,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VQDMLALv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(66)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i32 &&
N3.getValueType() == MVT::v2i32) {
@@ -23478,9 +23317,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMLSLsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(45)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i32 &&
N3.getValueType() == MVT::v2i32) {
@@ -23493,9 +23332,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMLSLuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(46)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i32 &&
N3.getValueType() == MVT::v2i32) {
@@ -23508,9 +23347,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VQDMLSLv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(67)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i32 &&
N3.getValueType() == MVT::v2i32) {
@@ -23523,8 +23362,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VSUBLsv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(113)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VSUBLsv2i64, MVT::v2i64);
@@ -23536,8 +23375,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VSUBLuv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(114)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VSUBLuv2i64, MVT::v2i64);
@@ -23549,8 +23388,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VSUBWsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(115)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VSUBWsv2i64, MVT::v2i64);
@@ -23562,8 +23401,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VSUBWuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(116)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VSUBWuv2i64, MVT::v2i64);
@@ -23575,8 +23414,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VQSUBsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(86)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_220(N, ARM::VQSUBsv2i64, MVT::v2i64);
@@ -23588,8 +23427,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VQSUBuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(87)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_220(N, ARM::VQSUBuv2i64, MVT::v2i64);
@@ -23601,8 +23440,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VABDLsv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(7)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VABDLsv2i64, MVT::v2i64);
@@ -23614,8 +23453,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VABDLuv2i64:v2i64 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_220(N, ARM::VABDLuv2i64, MVT::v2i64);
@@ -23627,9 +23466,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VABALsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(3)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i32 &&
N3.getValueType() == MVT::v2i32) {
@@ -23642,9 +23481,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VABALuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(4)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i32 &&
N3.getValueType() == MVT::v2i32) {
@@ -23657,7 +23496,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VPADDLsv4i32:v2i64 QPR:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(57)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_222(N, ARM::VPADDLsv4i32, MVT::v2i64);
return Result;
@@ -23668,7 +23507,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VPADDLuv4i32:v2i64 QPR:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(58)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_222(N, ARM::VPADDLuv4i32, MVT::v2i64);
return Result;
@@ -23679,8 +23518,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VPADALsv4i32:v2i64 QPR:v2i64:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(54)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VPADALsv4i32, MVT::v2i64);
@@ -23692,8 +23531,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VPADALuv4i32:v2i64 QPR:v2i64:$src1, QPR:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(55)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_220(N, ARM::VPADALuv4i32, MVT::v2i64);
@@ -23705,8 +23544,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VSHLsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(103)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_220(N, ARM::VSHLsv2i64, MVT::v2i64);
@@ -23718,8 +23557,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VSHLuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(104)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_220(N, ARM::VSHLuv2i64, MVT::v2i64);
@@ -23731,8 +23570,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VRSHLsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(94)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_220(N, ARM::VRSHLsv2i64, MVT::v2i64);
@@ -23744,8 +23583,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VRSHLuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(95)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_220(N, ARM::VRSHLuv2i64, MVT::v2i64);
@@ -23757,8 +23596,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VQSHLsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(83)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_220(N, ARM::VQSHLsv2i64, MVT::v2i64);
@@ -23770,8 +23609,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VQSHLuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(85)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_220(N, ARM::VQSHLuv2i64, MVT::v2i64);
@@ -23783,8 +23622,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VQRSHLsv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(78)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_220(N, ARM::VQRSHLsv2i64, MVT::v2i64);
@@ -23796,8 +23635,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VQRSHLuv2i64:v2i64 QPR:v2i64:$src1, QPR:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(79)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i64 &&
N2.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_220(N, ARM::VQRSHLuv2i64, MVT::v2i64);
@@ -23809,7 +23648,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMOVLsv2i64:v2i64 DPR:v2i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(47)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_222(N, ARM::VMOVLsv2i64, MVT::v2i64);
return Result;
@@ -23820,7 +23659,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMOVLuv2i64:v2i64 DPR:v2i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(48)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_222(N, ARM::VMOVLuv2i64, MVT::v2i64);
return Result;
@@ -23831,8 +23670,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VADDWsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(19)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_229(N, ARM::VADDWsv2i64, MVT::v2i64);
@@ -23844,8 +23683,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VADDWuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(20)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_229(N, ARM::VADDWuv2i64, MVT::v2i64);
@@ -23857,9 +23696,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMLALsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(43)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i64 &&
N3.getValueType() == MVT::v2i32) {
@@ -23872,9 +23711,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMLALuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(44)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i64 &&
N3.getValueType() == MVT::v2i32) {
@@ -23887,9 +23726,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VQDMLALv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(66)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i64 &&
N3.getValueType() == MVT::v2i32) {
@@ -23902,9 +23741,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMLSLsv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(45)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i64 &&
N3.getValueType() == MVT::v2i32) {
@@ -23917,9 +23756,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VMLSLuv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(46)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i64 &&
N3.getValueType() == MVT::v2i32) {
@@ -23932,9 +23771,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
// Emits: (VQDMLSLv2i64:v2i64 QPR:v2i64:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(67)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
if (N1.getValueType() == MVT::v2i32 &&
N2.getValueType() == MVT::v2i64 &&
N3.getValueType() == MVT::v2i32) {
@@ -23949,10 +23788,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f32(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -23960,9 +23799,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f32(const SDValue &N) {
// Emits: (VCVTxs2fd:v2f32 DPR:v2i32:$src, (imm:i32):$SIMM)
// Pattern complexity = 11 cost = 1 size = 0
if (CN1 == INT64_C(26)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_232(N, ARM::VCVTxs2fd, MVT::v2f32);
return Result;
@@ -23973,9 +23812,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f32(const SDValue &N) {
// Emits: (VCVTxu2fd:v2f32 DPR:v2i32:$src, (imm:i32):$SIMM)
// Pattern complexity = 11 cost = 1 size = 0
if (CN1 == INT64_C(27)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_232(N, ARM::VCVTxu2fd, MVT::v2f32);
return Result;
@@ -23986,8 +23825,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f32(const SDValue &N) {
// Emits: (VABDfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(9)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2f32 &&
N2.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_220(N, ARM::VABDfd, MVT::v2f32);
@@ -23999,8 +23838,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f32(const SDValue &N) {
// Emits: (VMAXfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(39)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2f32 &&
N2.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_220(N, ARM::VMAXfd, MVT::v2f32);
@@ -24012,8 +23851,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f32(const SDValue &N) {
// Emits: (VMINfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(41)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2f32 &&
N2.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_220(N, ARM::VMINfd, MVT::v2f32);
@@ -24025,8 +23864,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f32(const SDValue &N) {
// Emits: (VPADDf:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(56)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2f32 &&
N2.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_220(N, ARM::VPADDf, MVT::v2f32);
@@ -24038,8 +23877,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f32(const SDValue &N) {
// Emits: (VPMAXf:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(59)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2f32 &&
N2.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_220(N, ARM::VPMAXf, MVT::v2f32);
@@ -24051,8 +23890,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f32(const SDValue &N) {
// Emits: (VPMINf:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(61)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2f32 &&
N2.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_220(N, ARM::VPMINf, MVT::v2f32);
@@ -24064,7 +23903,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f32(const SDValue &N) {
// Emits: (VRECPEfd:v2f32 DPR:v2f32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(89)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_222(N, ARM::VRECPEfd, MVT::v2f32);
return Result;
@@ -24075,8 +23914,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f32(const SDValue &N) {
// Emits: (VRECPSfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(90)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2f32 &&
N2.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_220(N, ARM::VRECPSfd, MVT::v2f32);
@@ -24088,7 +23927,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f32(const SDValue &N) {
// Emits: (VRSQRTEfd:v2f32 DPR:v2f32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(96)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_222(N, ARM::VRSQRTEfd, MVT::v2f32);
return Result;
@@ -24099,8 +23938,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f32(const SDValue &N) {
// Emits: (VRSQRTSfd:v2f32 DPR:v2f32:$src1, DPR:v2f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(97)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v2f32 &&
N2.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_220(N, ARM::VRSQRTSfd, MVT::v2f32);
@@ -24112,7 +23951,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f32(const SDValue &N) {
// Emits: (VABSfd:v2f32 DPR:v2f32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(11)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_222(N, ARM::VABSfd, MVT::v2f32);
return Result;
@@ -24125,10 +23964,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -24136,9 +23975,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (VCVTxs2fq:v4f32 QPR:v4i32:$src, (imm:i32):$SIMM)
// Pattern complexity = 11 cost = 1 size = 0
if (CN1 == INT64_C(26)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_232(N, ARM::VCVTxs2fq, MVT::v4f32);
return Result;
@@ -24149,9 +23988,9 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (VCVTxu2fq:v4f32 QPR:v4i32:$src, (imm:i32):$SIMM)
// Pattern complexity = 11 cost = 1 size = 0
if (CN1 == INT64_C(27)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_232(N, ARM::VCVTxu2fq, MVT::v4f32);
return Result;
@@ -24162,8 +24001,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (VABDfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(9)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4f32 &&
N2.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_220(N, ARM::VABDfq, MVT::v4f32);
@@ -24175,8 +24014,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (VMAXfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(39)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4f32 &&
N2.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_220(N, ARM::VMAXfq, MVT::v4f32);
@@ -24188,8 +24027,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (VMINfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(41)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4f32 &&
N2.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_220(N, ARM::VMINfq, MVT::v4f32);
@@ -24201,7 +24040,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (VRECPEfq:v4f32 QPR:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(89)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_222(N, ARM::VRECPEfq, MVT::v4f32);
return Result;
@@ -24212,8 +24051,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (VRECPSfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(90)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4f32 &&
N2.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_220(N, ARM::VRECPSfq, MVT::v4f32);
@@ -24225,7 +24064,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (VRSQRTEfq:v4f32 QPR:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(96)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_222(N, ARM::VRSQRTEfq, MVT::v4f32);
return Result;
@@ -24236,8 +24075,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (VRSQRTSfq:v4f32 QPR:v4f32:$src1, QPR:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(97)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1.getValueType() == MVT::v4f32 &&
N2.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_220(N, ARM::VRSQRTSfq, MVT::v4f32);
@@ -24249,7 +24088,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
// Emits: (VABSfq:v4f32 QPR:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(11)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_222(N, ARM::VABSfq, MVT::v4f32);
return Result;
@@ -24262,24 +24101,24 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_237(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_237(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, Tmp3, Tmp4, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v8i8(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -24297,15 +24136,15 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -24323,15 +24162,15 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4i16(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -24349,15 +24188,15 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v8i16(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -24375,15 +24214,15 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2i32(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -24401,15 +24240,15 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4i32(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -24427,15 +24266,15 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v1i64(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v1i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -24453,15 +24292,15 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2i64(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -24479,15 +24318,15 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2f32(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -24505,15 +24344,15 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4f32(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -24531,122 +24370,122 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_238(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_238(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, Tmp1, Tmp2, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 5);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 5);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_239(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_239(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp1, Tmp2, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_240(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
+DISABLE_INLINE SDNode *Emit_240(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { N10, Tmp1, Tmp2, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 4);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 4);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_241(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_241(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp1, Tmp2, Chain };
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, MVT::Other, Ops0, 6), 0);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, MVT::Other, Ops0, 6), 0);
Chain = SDValue(Tmp3.getNode(), 1);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
MachineSDNode::mmo_iterator MemRefs1 = MF->allocateMemRefsArray(1);
MemRefs1[0] = cast<MemSDNode>(N)->getMemOperand();
- SDNode *ResNode = CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp3, Tmp4, Tmp5);
+ SDNode *ResNode = CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp3, Tmp4, Tmp5);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs1, MemRefs1 + 1);
- ReplaceUses(SDValue(N.getNode(), 1), Chain);
+ ReplaceUses(SDValue(N, 1), Chain);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_242(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_242(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
SDValue Tmp1 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp3, Tmp4, Chain };
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, MVT::Other, Ops0, 6), 0);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, MVT::Other, Ops0, 6), 0);
Chain = SDValue(Tmp5.getNode(), 1);
SDValue Tmp6 = CurDAG->getTargetConstant(0x18ULL, MVT::i32);
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { Tmp1, Tmp5, Tmp6, Tmp7, Tmp8 };
- SDValue Tmp9(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Ops1, 5), 0);
+ SDValue Tmp9(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Ops1, 5), 0);
SDValue Tmp10 = CurDAG->getTargetConstant(0x18ULL, MVT::i32);
SDValue Tmp11 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp12 = CurDAG->getRegister(0, MVT::i32);
MachineSDNode::mmo_iterator MemRefs2 = MF->allocateMemRefsArray(1);
MemRefs2[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops2[] = { Tmp0, Tmp9, Tmp10, Tmp11, Tmp12 };
- SDNode *ResNode = CurDAG->getMachineNode(Opc2, N.getDebugLoc(), VT2, Ops2, 5);
+ SDNode *ResNode = CurDAG->getMachineNode(Opc2, N->getDebugLoc(), VT2, Ops2, 5);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs2, MemRefs2 + 1);
- ReplaceUses(SDValue(N.getNode(), 1), Chain);
+ ReplaceUses(SDValue(N, 1), Chain);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_243(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_243(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
SDValue Tmp1 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, Tmp3, Tmp4, Chain };
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, MVT::Other, Ops0, 6), 0);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, MVT::Other, Ops0, 6), 0);
Chain = SDValue(Tmp5.getNode(), 1);
SDValue Tmp6 = CurDAG->getTargetConstant(0x10ULL, MVT::i32);
SDValue Tmp7 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp8 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { Tmp1, Tmp5, Tmp6, Tmp7, Tmp8 };
- SDValue Tmp9(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Ops1, 5), 0);
+ SDValue Tmp9(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Ops1, 5), 0);
SDValue Tmp10 = CurDAG->getTargetConstant(0x10ULL, MVT::i32);
SDValue Tmp11 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp12 = CurDAG->getRegister(0, MVT::i32);
MachineSDNode::mmo_iterator MemRefs2 = MF->allocateMemRefsArray(1);
MemRefs2[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops2[] = { Tmp0, Tmp9, Tmp10, Tmp11, Tmp12 };
- SDNode *ResNode = CurDAG->getMachineNode(Opc2, N.getDebugLoc(), VT2, Ops2, 5);
+ SDNode *ResNode = CurDAG->getMachineNode(Opc2, N->getDebugLoc(), VT2, Ops2, 5);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs2, MemRefs2 + 1);
- ReplaceUses(SDValue(N.getNode(), 1), Chain);
+ ReplaceUses(SDValue(N, 1), Chain);
return ResNode;
}
-SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
+SDNode *Select_ISD_LOAD_i32(SDNode *N) {
if ((!Subtarget->isThumb())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N)) {
// Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>>
// Emits: (PICLDR:i32 addrmodepc:i32:$addr)
// Pattern complexity = 23 cost = 1 size = 0
- if (Predicate_load(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_load(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
@@ -24655,13 +24494,13 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return Result;
}
}
- if (Predicate_zextload(N.getNode())) {
+ if (Predicate_zextload(N)) {
// Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
// Emits: (PICLDRH:i32 addrmodepc:i32:$addr)
// Pattern complexity = 23 cost = 1 size = 0
- if (Predicate_zextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
@@ -24674,8 +24513,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
// Emits: (PICLDRB:i32 addrmodepc:i32:$addr)
// Pattern complexity = 23 cost = 1 size = 0
- if (Predicate_zextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
@@ -24685,13 +24524,13 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
}
}
}
- if (Predicate_sextload(N.getNode())) {
+ if (Predicate_sextload(N)) {
// Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
// Emits: (PICLDRSH:i32 addrmodepc:i32:$addr)
// Pattern complexity = 23 cost = 1 size = 0
- if (Predicate_sextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
@@ -24704,8 +24543,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
// Emits: (PICLDRSB:i32 addrmodepc:i32:$addr)
// Pattern complexity = 23 cost = 1 size = 0
- if (Predicate_sextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
@@ -24718,15 +24557,15 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode()) &&
- Predicate_sextload(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N) &&
+ Predicate_sextload(N)) {
// Pattern: (ld:i32 t_addrmode_rr:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
// Emits: (tLDRSB:i32 t_addrmode_rr:i32:$addr)
// Pattern complexity = 23 cost = 1 size = 0
- if (Predicate_sextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectThumbAddrModeRR(N, N1, CPTmpN1_0, CPTmpN1_1) &&
@@ -24739,8 +24578,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 t_addrmode_rr:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
// Emits: (tLDRSH:i32 t_addrmode_rr:i32:$addr)
// Pattern complexity = 23 cost = 1 size = 0
- if (Predicate_sextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectThumbAddrModeRR(N, N1, CPTmpN1_0, CPTmpN1_1) &&
@@ -24752,14 +24591,14 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N)) {
// Pattern: (ld:i32 addrmode2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>>
// Emits: (LDR:i32 addrmode2:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_load(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_load(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -24769,13 +24608,13 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return Result;
}
}
- if (Predicate_zextload(N.getNode())) {
+ if (Predicate_zextload(N)) {
// Pattern: (ld:i32 addrmode3:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
// Emits: (LDRH:i32 addrmode3:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_zextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -24789,8 +24628,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 addrmode2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
// Emits: (LDRB:i32 addrmode2:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_zextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -24801,13 +24640,13 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
}
}
}
- if (Predicate_sextload(N.getNode())) {
+ if (Predicate_sextload(N)) {
// Pattern: (ld:i32 addrmode3:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
// Emits: (LDRSH:i32 addrmode3:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_sextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -24821,8 +24660,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 addrmode3:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
// Emits: (LDRSB:i32 addrmode3:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_sextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -24836,14 +24675,14 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N)) {
// Pattern: (ld:i32 t_addrmode_s4:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>>
// Emits: (tLDR:i32 t_addrmode_s4:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_load(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_load(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -24853,13 +24692,13 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return Result;
}
}
- if (Predicate_zextload(N.getNode())) {
+ if (Predicate_zextload(N)) {
// Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
// Emits: (tLDRB:i32 t_addrmode_s1:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_zextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -24873,8 +24712,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 t_addrmode_s2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
// Emits: (tLDRH:i32 t_addrmode_s2:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_zextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -24888,14 +24727,14 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N)) {
// Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>>
// Emits: (t2LDRs:i32 t2addrmode_so_reg:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_load(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_load(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -24905,13 +24744,13 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return Result;
}
}
- if (Predicate_zextload(N.getNode())) {
+ if (Predicate_zextload(N)) {
// Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
// Emits: (t2LDRHs:i32 t2addrmode_so_reg:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_zextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -24925,8 +24764,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
// Emits: (t2LDRBs:i32 t2addrmode_so_reg:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_zextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -24937,13 +24776,13 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
}
}
}
- if (Predicate_sextload(N.getNode())) {
+ if (Predicate_sextload(N)) {
// Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
// Emits: (t2LDRSHs:i32 t2addrmode_so_reg:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_sextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -24957,8 +24796,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
// Emits: (t2LDRSBs:i32 t2addrmode_so_reg:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_sextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -24972,15 +24811,15 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N)) {
// Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
// Emits: (tLDRB:i32 t_addrmode_s1:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_zextload(N.getNode()) &&
- Predicate_zextloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextload(N) &&
+ Predicate_zextloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -24990,13 +24829,13 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return Result;
}
}
- if (Predicate_extload(N.getNode())) {
+ if (Predicate_extload(N)) {
// Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
// Emits: (tLDRB:i32 t_addrmode_s1:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_extloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -25010,8 +24849,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
// Emits: (tLDRB:i32 t_addrmode_s1:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_extloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -25025,8 +24864,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 t_addrmode_s2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
// Emits: (tLDRH:i32 t_addrmode_s2:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_extloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -25040,15 +24879,15 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N)) {
// Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
// Emits: (t2LDRBs:i32 t2addrmode_so_reg:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_zextload(N.getNode()) &&
- Predicate_zextloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextload(N) &&
+ Predicate_zextloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -25058,13 +24897,13 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return Result;
}
}
- if (Predicate_extload(N.getNode())) {
+ if (Predicate_extload(N)) {
// Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
// Emits: (t2LDRBs:i32 t2addrmode_so_reg:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_extloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -25078,8 +24917,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
// Emits: (t2LDRBs:i32 t2addrmode_so_reg:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_extloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -25093,8 +24932,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
// Emits: (t2LDRHs:i32 t2addrmode_so_reg:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_extloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -25108,15 +24947,15 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N)) {
// Pattern: (ld:i32 addrmode2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
// Emits: (LDRB:i32 addrmode2:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_zextload(N.getNode()) &&
- Predicate_zextloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextload(N) &&
+ Predicate_zextloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -25126,13 +24965,13 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return Result;
}
}
- if (Predicate_extload(N.getNode())) {
+ if (Predicate_extload(N)) {
// Pattern: (ld:i32 addrmode2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
// Emits: (LDRB:i32 addrmode2:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_extloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -25146,8 +24985,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 addrmode2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
// Emits: (LDRB:i32 addrmode2:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_extloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -25161,8 +25000,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 addrmode3:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
// Emits: (LDRH:i32 addrmode3:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_extloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -25176,15 +25015,15 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode()) &&
- Predicate_sextload(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N) &&
+ Predicate_sextload(N)) {
// Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
// Emits: (tSXTB:i32 (tLDRB:i32 t_addrmode_s1:i32:$addr))
// Pattern complexity = 16 cost = 2 size = 0
- if (Predicate_sextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -25198,8 +25037,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 t_addrmode_s2:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
// Emits: (tSXTH:i32 (tLDRH:i32 t_addrmode_s2:i32:$addr))
// Pattern complexity = 16 cost = 2 size = 0
- if (Predicate_sextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -25212,15 +25051,15 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode())) {
- if (Predicate_sextload(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N)) {
+ if (Predicate_sextload(N)) {
// Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
// Emits: (tASRri:i32 (tLSLri:i32 (tLDRB:i32 t_addrmode_s1:i32:$addr), 24:i32), 24:i32)
// Pattern complexity = 16 cost = 3 size = 0
- if (Predicate_sextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -25234,8 +25073,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
// Emits: (tASRri:i32 (tLSLri:i32 (tLDRH:i32 t_addrmode_s1:i32:$addr), 16:i32), 16:i32)
// Pattern complexity = 16 cost = 3 size = 0
- if (Predicate_sextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -25250,8 +25089,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 t_addrmode_sp:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>>
// Emits: (tLDRspi:i32 t_addrmode_sp:i32:$addr)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_load(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_load(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectThumbAddrModeSP(N, N1, CPTmpN1_0, CPTmpN1_1) &&
@@ -25263,10 +25102,10 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode())) {
- if (Predicate_load(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N)) {
+ if (Predicate_load(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -25288,9 +25127,9 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return Result;
}
}
- if (Predicate_zextload(N.getNode())) {
- if (Predicate_zextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextload(N)) {
+ if (Predicate_zextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -25312,8 +25151,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return Result;
}
}
- if (Predicate_zextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -25336,9 +25175,9 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
}
}
}
- if (Predicate_sextload(N.getNode())) {
- if (Predicate_sextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextload(N)) {
+ if (Predicate_sextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -25360,8 +25199,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return Result;
}
}
- if (Predicate_sextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -25384,9 +25223,9 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
}
}
}
- if (Predicate_zextload(N.getNode()) &&
- Predicate_zextloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextload(N) &&
+ Predicate_zextloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -25408,9 +25247,9 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return Result;
}
}
- if (Predicate_extload(N.getNode())) {
- if (Predicate_extloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extload(N)) {
+ if (Predicate_extloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -25432,8 +25271,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return Result;
}
}
- if (Predicate_extloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -25455,8 +25294,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return Result;
}
}
- if (Predicate_extloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -25482,15 +25321,15 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode()) &&
- Predicate_extload(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N) &&
+ Predicate_extload(N)) {
// Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
// Emits: (PICLDRB:i32 addrmodepc:i32:$addr)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_extloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
@@ -25503,8 +25342,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 addrmodepc:i32:$addr)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
// Emits: (PICLDRH:i32 addrmodepc:i32:$addr)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_extloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrModePC(N, N1, CPTmpN1_0, CPTmpN1_1) &&
@@ -25520,13 +25359,13 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Emits: (tLDRpci:i32 (tconstpool:i32):$addr)
// Pattern complexity = 10 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode()) &&
- Predicate_load(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::Wrapper) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::TargetConstantPool) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N) &&
+ Predicate_load(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::Wrapper) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
SDNode *Result = Emit_240(N, ARM::tLDRpci, MVT::i32);
return Result;
}
@@ -25534,32 +25373,32 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N)) {
// Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>>
// Emits: (t2LDRpci:i32 (tconstpool:i32):$addr)
// Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_load(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::Wrapper) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::TargetConstantPool) {
+ if (Predicate_load(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::Wrapper) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
SDNode *Result = Emit_240(N, ARM::t2LDRpci, MVT::i32);
return Result;
}
}
}
- if (Predicate_zextload(N.getNode())) {
+ if (Predicate_zextload(N)) {
// Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
// Emits: (t2LDRHpci:i32 (tconstpool:i32):$addr)
// Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_zextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::Wrapper) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::TargetConstantPool) {
+ if (Predicate_zextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::Wrapper) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
SDNode *Result = Emit_240(N, ARM::t2LDRHpci, MVT::i32);
return Result;
}
@@ -25569,27 +25408,27 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
// Emits: (t2LDRBpci:i32 (tconstpool:i32):$addr)
// Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_zextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::Wrapper) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::TargetConstantPool) {
+ if (Predicate_zextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::Wrapper) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
SDNode *Result = Emit_240(N, ARM::t2LDRBpci, MVT::i32);
return Result;
}
}
}
}
- if (Predicate_sextload(N.getNode())) {
+ if (Predicate_sextload(N)) {
// Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
// Emits: (t2LDRSHpci:i32 (tconstpool:i32):$addr)
// Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_sextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::Wrapper) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::TargetConstantPool) {
+ if (Predicate_sextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::Wrapper) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
SDNode *Result = Emit_240(N, ARM::t2LDRSHpci, MVT::i32);
return Result;
}
@@ -25599,11 +25438,11 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
// Emits: (t2LDRSBpci:i32 (tconstpool:i32):$addr)
// Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_sextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::Wrapper) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::TargetConstantPool) {
+ if (Predicate_sextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::Wrapper) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
SDNode *Result = Emit_240(N, ARM::t2LDRSBpci, MVT::i32);
return Result;
}
@@ -25614,27 +25453,27 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
// Emits: (t2LDRBpci:i32 (tconstpool:i32):$addr)
// Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_zextload(N.getNode()) &&
- Predicate_zextloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::Wrapper) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::TargetConstantPool) {
+ if (Predicate_zextload(N) &&
+ Predicate_zextloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::Wrapper) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
SDNode *Result = Emit_240(N, ARM::t2LDRBpci, MVT::i32);
return Result;
}
}
}
- if (Predicate_extload(N.getNode())) {
+ if (Predicate_extload(N)) {
// Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
// Emits: (t2LDRBpci:i32 (tconstpool:i32):$addr)
// Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_extloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::Wrapper) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::TargetConstantPool) {
+ if (Predicate_extloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::Wrapper) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
SDNode *Result = Emit_240(N, ARM::t2LDRBpci, MVT::i32);
return Result;
}
@@ -25644,11 +25483,11 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
// Emits: (t2LDRBpci:i32 (tconstpool:i32):$addr)
// Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_extloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::Wrapper) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::TargetConstantPool) {
+ if (Predicate_extloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::Wrapper) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
SDNode *Result = Emit_240(N, ARM::t2LDRBpci, MVT::i32);
return Result;
}
@@ -25658,11 +25497,11 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
// Emits: (t2LDRHpci:i32 (tconstpool:i32):$addr)
// Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_extloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::Wrapper) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::TargetConstantPool) {
+ if (Predicate_extloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::Wrapper) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
SDNode *Result = Emit_240(N, ARM::t2LDRHpci, MVT::i32);
return Result;
}
@@ -25676,12 +25515,12 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_LOAD_f32(const SDValue &N) {
+SDNode *Select_ISD_LOAD_f32(SDNode *N) {
if ((Subtarget->hasVFP2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode()) &&
- Predicate_load(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N) &&
+ Predicate_load(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrMode5(N, N1, CPTmpN1_0, CPTmpN1_1) &&
@@ -25696,12 +25535,12 @@ SDNode *Select_ISD_LOAD_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_LOAD_f64(const SDValue &N) {
+SDNode *Select_ISD_LOAD_f64(SDNode *N) {
if ((Subtarget->hasVFP2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode()) &&
- Predicate_load(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N) &&
+ Predicate_load(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrMode5(N, N1, CPTmpN1_0, CPTmpN1_1) &&
@@ -25716,12 +25555,12 @@ SDNode *Select_ISD_LOAD_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_LOAD_v2f64(const SDValue &N) {
+SDNode *Select_ISD_LOAD_v2f64(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode()) &&
- Predicate_load(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N) &&
+ Predicate_load(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrMode4(N, N1, CPTmpN1_0, CPTmpN1_1) &&
@@ -25736,223 +25575,223 @@ SDNode *Select_ISD_LOAD_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_244(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_244(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N10, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_245(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_245(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N10, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_246(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_246(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N10, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_247(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_247(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp10 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp11 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N000, N100, Tmp10, Tmp11 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_248(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_248(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N000, N10, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_249(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_249(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, N10, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_250(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_250(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N100, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_251(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_251(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N1, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_252(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_252(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N10, N00, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_253(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_253(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N10, N00, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_254(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_254(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp10 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp11 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N100, N000, Tmp10, Tmp11 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_255(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_255(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N100, N00, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_256(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_256(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, N00, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_257(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_257(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N10, N000, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_258(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_258(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N10, N0, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-SDNode *Select_ISD_MUL_i32(const SDValue &N) {
+SDNode *Select_ISD_MUL_i32(SDNode *N) {
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::SHL) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(16)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp6) {
int64_t CN7 = Tmp6->getSExtValue();
if (CN7 == INT64_C(16) &&
@@ -25983,8 +25822,8 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
// Pattern: (mul:i32 (sra:i32 (shl:i32 GPR:i32:$a, 16:i32), 16:i32), (sra:i32 GPR:i32:$b, 16:i32))
// Emits: (SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 27 cost = 1 size = 0
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(16) &&
@@ -26002,23 +25841,23 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
}
}
{
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(16) &&
@@ -26052,23 +25891,23 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
// Pattern: (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), (sra:i32 GPR:i32:$a, 16:i32))
// Emits: (SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 27 cost = 1 size = 0
- if (N00.getOpcode() == ISD::SHL) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (N00.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(16) &&
@@ -26089,16 +25928,16 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
// Pattern: (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sra:i32 GPR:i32:$b, 16:i32))
// Emits: (SMULTT:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 19 cost = 1 size = 0
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16) &&
@@ -26118,19 +25957,19 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
// Emits: (t2SMULTT:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 19 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16) &&
@@ -26150,19 +25989,19 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
// Emits: (SMULTT:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 19 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16) &&
@@ -26182,19 +26021,19 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
// Emits: (t2SMULTT:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 19 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16) &&
@@ -26210,20 +26049,20 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sra:i32 GPR:i32:$b, 16:i32))
// Emits: (SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 14 cost = 1 size = 0
- if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (cast<VTSDNode>(N01)->getVT() == MVT::i16) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N0.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i16) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -26239,18 +26078,18 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
// Pattern: (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sext_inreg:i32 GPR:i32:$b, i16:Other))
// Emits: (SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 14 cost = 1 size = 0
- if (N0.getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N0.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (cast<VTSDNode>(N11)->getVT() == MVT::i16 &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i16 &&
N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_245(N, ARM::SMULTB, MVT::i32);
return Result;
@@ -26261,20 +26100,20 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sra:i32 GPR:i32:$b, 16:i32))
// Emits: (t2SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 14 cost = 1 size = 0
- if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (cast<VTSDNode>(N01)->getVT() == MVT::i16) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N0.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i16) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -26290,18 +26129,18 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
// Pattern: (mul:i32 (sra:i32 GPR:i32:$a, 16:i32), (sext_inreg:i32 GPR:i32:$b, i16:Other))
// Emits: (t2SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 14 cost = 1 size = 0
- if (N0.getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N0.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (cast<VTSDNode>(N11)->getVT() == MVT::i16 &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i16 &&
N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_245(N, ARM::t2SMULTB, MVT::i32);
return Result;
@@ -26312,23 +26151,23 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sext_inreg:i32 GPR:i32:$a, i16:Other))
// Emits: (SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 14 cost = 1 size = 0
- if (N0.getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N0.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (cast<VTSDNode>(N11)->getVT() == MVT::i16 &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i16 &&
N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_252(N, ARM::SMULBT, MVT::i32);
return Result;
@@ -26341,15 +26180,15 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
// Pattern: (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), (sra:i32 GPR:i32:$a, 16:i32))
// Emits: (SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 14 cost = 1 size = 0
- if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (cast<VTSDNode>(N01)->getVT() == MVT::i16) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N0.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i16) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -26363,23 +26202,23 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (mul:i32 (sra:i32 GPR:i32:$b, 16:i32), (sext_inreg:i32 GPR:i32:$a, i16:Other))
// Emits: (t2SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 14 cost = 1 size = 0
- if (N0.getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N0.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (cast<VTSDNode>(N11)->getVT() == MVT::i16 &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i16 &&
N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_252(N, ARM::t2SMULBT, MVT::i32);
return Result;
@@ -26392,15 +26231,15 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
// Pattern: (mul:i32 (sext_inreg:i32 GPR:i32:$b, i16:Other), (sra:i32 GPR:i32:$a, 16:i32))
// Emits: (t2SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 14 cost = 1 size = 0
- if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (cast<VTSDNode>(N01)->getVT() == MVT::i16) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N0.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i16) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -26414,17 +26253,17 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (mul:i32 GPR:i32<<P:Predicate_sext_16_node>>:$a, (sra:i32 GPR:i32:$b, 16:i32))
// Emits: (SMULBT:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 12 cost = 1 size = 0
if (Predicate_sext_16_node(N0.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -26435,14 +26274,14 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::SRA) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N0.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (Predicate_sext_16_node(N1.getNode()) &&
N01.getValueType() == MVT::i32) {
@@ -26468,11 +26307,11 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
// Emits: (SMULTB:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 12 cost = 1 size = 0
if (Predicate_sext_16_node(N0.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRA) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -26487,15 +26326,15 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
// Pattern: (mul:i32 (sext_inreg:i32 GPR:i32:$a, i16:Other), (sext_inreg:i32 GPR:i32:$b, i16:Other))
// Emits: (SMULBB:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (cast<VTSDNode>(N01)->getVT() == MVT::i16) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (cast<VTSDNode>(N11)->getVT() == MVT::i16) {
+ if (N0.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i16) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i16) {
SDNode *Result = Emit_244(N, ARM::SMULBB, MVT::i32);
return Result;
}
@@ -26508,16 +26347,16 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
// Emits: (t2SMULBB:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 9 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (cast<VTSDNode>(N01)->getVT() == MVT::i16) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (cast<VTSDNode>(N11)->getVT() == MVT::i16) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N01.getNode())->getVT() == MVT::i16) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N11.getNode())->getVT() == MVT::i16) {
SDNode *Result = Emit_244(N, ARM::t2SMULBB, MVT::i32);
return Result;
}
@@ -26530,9 +26369,9 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
// Emits: (SMULBB:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 5 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (Predicate_sext_16_node(N0.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (Predicate_sext_16_node(N1.getNode())) {
SDNode *Result = Emit_44(N, ARM::SMULBB, MVT::i32);
return Result;
@@ -26568,7 +26407,7 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_MUL_v8i8(const SDValue &N) {
+SDNode *Select_ISD_MUL_v8i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
SDNode *Result = Emit_44(N, ARM::VMULv8i8, MVT::v8i8);
return Result;
@@ -26578,7 +26417,7 @@ SDNode *Select_ISD_MUL_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_MUL_v16i8(const SDValue &N) {
+SDNode *Select_ISD_MUL_v16i8(SDNode *N) {
if ((Subtarget->hasNEON())) {
SDNode *Result = Emit_44(N, ARM::VMULv16i8, MVT::v16i8);
return Result;
@@ -26588,20 +26427,20 @@ SDNode *Select_ISD_MUL_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_MUL_v4i16(const SDValue &N) {
+SDNode *Select_ISD_MUL_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (mul:v4i16 DPR:v4i16:$src1, (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane))
// Emits: (VMULslv4i16:v4i16 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
// Pattern complexity = 9 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_126(N, ARM::VMULslv4i16, MVT::v4i16);
return Result;
@@ -26612,11 +26451,11 @@ SDNode *Select_ISD_MUL_v4i16(const SDValue &N) {
// Pattern: (mul:v4i16 (NEONvduplane:v4i16 DPR_8:v4i16:$src2, (imm:i32):$lane), DPR:v4i16:$src1)
// Emits: (VMULslv4i16:v4i16 DPR:v4i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
+ if (N0.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_128(N, ARM::VMULslv4i16, MVT::v4i16);
return Result;
@@ -26636,47 +26475,47 @@ SDNode *Select_ISD_MUL_v4i16(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_259(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_259(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
SDValue Tmp3 = Transform_DSubReg_i16_reg(Tmp2.getNode());
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N10, Tmp3), 0);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N10, Tmp3), 0);
SDValue Tmp5 = Transform_SubReg_i16_lane(Tmp2.getNode());
SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { N0, Tmp4, Tmp5, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
}
-DISABLE_INLINE SDNode *Emit_260(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_260(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
SDValue Tmp3 = Transform_DSubReg_i16_reg(Tmp2.getNode());
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N00, Tmp3), 0);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N00, Tmp3), 0);
SDValue Tmp5 = Transform_SubReg_i16_lane(Tmp2.getNode());
SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { N1, Tmp4, Tmp5, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
}
-SDNode *Select_ISD_MUL_v8i16(const SDValue &N) {
+SDNode *Select_ISD_MUL_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (mul:v8i16 QPR:v8i16:$src1, (NEONvduplane:v8i16 DPR_8:v4i16:$src2, (imm:i32):$lane))
// Emits: (VMULslv8i16:v8i16 QPR:v8i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
// Pattern complexity = 9 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_126(N, ARM::VMULslv8i16, MVT::v8i16);
return Result;
@@ -26687,11 +26526,11 @@ SDNode *Select_ISD_MUL_v8i16(const SDValue &N) {
// Pattern: (mul:v8i16 (NEONvduplane:v8i16 DPR_8:v4i16:$src2, (imm:i32):$lane), QPR:v8i16:$src1)
// Emits: (VMULslv8i16:v8i16 QPR:v8i16:$src1, DPR_8:v4i16:$src2, (imm:i32):$lane)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
+ if (N0.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_128(N, ARM::VMULslv8i16, MVT::v8i16);
return Result;
@@ -26700,17 +26539,17 @@ SDNode *Select_ISD_MUL_v8i16(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (mul:v8i16 QPR:v8i16:$src1, (NEONvduplane:v8i16 QPR:v8i16:$src2, (imm:i32):$lane))
// Emits: (VMULslv8i16:v8i16 QPR:v8i16:$src1, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src2, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
// Pattern complexity = 9 cost = 2 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_259(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
@@ -26721,11 +26560,11 @@ SDNode *Select_ISD_MUL_v8i16(const SDValue &N) {
// Pattern: (mul:v8i16 (NEONvduplane:v8i16 QPR:v8i16:$src2, (imm:i32):$lane), QPR:v8i16:$src1)
// Emits: (VMULslv8i16:v8i16 QPR:v8i16:$src1, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src2, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
// Pattern complexity = 9 cost = 2 size = 0
- if (N0.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
+ if (N0.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_260(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
@@ -26746,20 +26585,20 @@ SDNode *Select_ISD_MUL_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_MUL_v2i32(const SDValue &N) {
+SDNode *Select_ISD_MUL_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (mul:v2i32 DPR:v2i32:$src1, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane))
// Emits: (VMULslv2i32:v2i32 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
// Pattern complexity = 9 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_126(N, ARM::VMULslv2i32, MVT::v2i32);
return Result;
@@ -26770,11 +26609,11 @@ SDNode *Select_ISD_MUL_v2i32(const SDValue &N) {
// Pattern: (mul:v2i32 (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane), DPR:v2i32:$src1)
// Emits: (VMULslv2i32:v2i32 DPR:v2i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
+ if (N0.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_128(N, ARM::VMULslv2i32, MVT::v2i32);
return Result;
@@ -26794,19 +26633,19 @@ SDNode *Select_ISD_MUL_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_MUL_v4i32(const SDValue &N) {
+SDNode *Select_ISD_MUL_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (mul:v4i32 QPR:v4i32:$src1, (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane))
// Emits: (VMULslv4i32:v4i32 QPR:v4i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
// Pattern complexity = 9 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_126(N, ARM::VMULslv4i32, MVT::v4i32);
return Result;
@@ -26817,11 +26656,11 @@ SDNode *Select_ISD_MUL_v4i32(const SDValue &N) {
// Pattern: (mul:v4i32 (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src2, (imm:i32):$lane), QPR:v4i32:$src1)
// Emits: (VMULslv4i32:v4i32 QPR:v4i32:$src1, DPR_VFP2:v2i32:$src2, (imm:i32):$lane)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
+ if (N0.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_128(N, ARM::VMULslv4i32, MVT::v4i32);
return Result;
@@ -26830,17 +26669,17 @@ SDNode *Select_ISD_MUL_v4i32(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (mul:v4i32 QPR:v4i32:$src1, (NEONvduplane:v4i32 QPR:v4i32:$src2, (imm:i32):$lane))
// Emits: (VMULslv4i32:v4i32 QPR:v4i32:$src1, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 9 cost = 2 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_210(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
@@ -26851,11 +26690,11 @@ SDNode *Select_ISD_MUL_v4i32(const SDValue &N) {
// Pattern: (mul:v4i32 (NEONvduplane:v4i32 QPR:v4i32:$src2, (imm:i32):$lane), QPR:v4i32:$src1)
// Emits: (VMULslv4i32:v4i32 QPR:v4i32:$src1, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src2, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 9 cost = 2 size = 0
- if (N0.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
+ if (N0.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_211(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
@@ -26876,7 +26715,7 @@ SDNode *Select_ISD_MUL_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_MULHS_i32(const SDValue &N) {
+SDNode *Select_ISD_MULHS_i32(SDNode *N) {
// Pattern: (mulhs:i32 GPR:i32:$a, GPR:i32:$b)
// Emits: (SMMUL:i32 GPR:i32:$a, GPR:i32:$b)
@@ -26898,309 +26737,309 @@ SDNode *Select_ISD_MULHS_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_261(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_261(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp3 = Transform_hi16(Tmp2.getNode());
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_262(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N1000 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- SDValue N11000 = N1100.getOperand(0);
- SDValue N11001 = N1100.getOperand(1);
- SDValue N111 = N11.getOperand(1);
- SDValue N1110 = N111.getOperand(0);
- SDValue N1111 = N111.getOperand(1);
- SDValue N11100 = N1110.getOperand(0);
- SDValue N11101 = N1110.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_262(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue N11000 = N1100.getNode()->getOperand(0);
+ SDValue N11001 = N1100.getNode()->getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ SDValue N11100 = N1110.getNode()->getOperand(0);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
SDValue Tmp13 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp14 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N000, Tmp13, Tmp14);
-}
-DISABLE_INLINE SDNode *Emit_263(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N000, Tmp13, Tmp14);
+}
+DISABLE_INLINE SDNode *Emit_263(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N100, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_264(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_264(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xFFFFULL, MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_265(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_265(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N10, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_266(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_266(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N10, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_267(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_267(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0x10ULL, MVT::i32);
SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N10, Tmp5, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_268(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N1000 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- SDValue N10000 = N1000.getOperand(0);
- SDValue N10001 = N1000.getOperand(1);
- SDValue N101 = N10.getOperand(1);
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- SDValue N10100 = N1010.getOperand(0);
- SDValue N10101 = N1010.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_268(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue N10000 = N1000.getNode()->getOperand(0);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ SDValue N10100 = N1010.getNode()->getOperand(0);
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
SDValue Tmp13 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp14 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N000, Tmp13, Tmp14);
-}
-DISABLE_INLINE SDNode *Emit_269(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- SDValue N001 = N00.getOperand(1);
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- SDValue N00100 = N0010.getOperand(0);
- SDValue N00101 = N0010.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N000, Tmp13, Tmp14);
+}
+DISABLE_INLINE SDNode *Emit_269(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ SDValue N00100 = N0010.getNode()->getOperand(0);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue Tmp13 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp14 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00000, Tmp13, Tmp14);
-}
-DISABLE_INLINE SDNode *Emit_270(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- SDValue N01000 = N0100.getOperand(0);
- SDValue N01001 = N0100.getOperand(1);
- SDValue N011 = N01.getOperand(1);
- SDValue N0110 = N011.getOperand(0);
- SDValue N0111 = N011.getOperand(1);
- SDValue N01100 = N0110.getOperand(0);
- SDValue N01101 = N0110.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N00000, Tmp13, Tmp14);
+}
+DISABLE_INLINE SDNode *Emit_270(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ SDValue N01000 = N0100.getNode()->getOperand(0);
+ SDValue N01001 = N0100.getNode()->getOperand(1);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N0110 = N011.getNode()->getOperand(0);
+ SDValue N0111 = N011.getNode()->getOperand(1);
+ SDValue N01100 = N0110.getNode()->getOperand(0);
+ SDValue N01101 = N0110.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue Tmp13 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp14 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0000, Tmp13, Tmp14);
-}
-DISABLE_INLINE SDNode *Emit_271(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0000, Tmp13, Tmp14);
+}
+DISABLE_INLINE SDNode *Emit_271(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N001)->getZExtValue()), MVT::i32);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N10, N000, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_272(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_272(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
SDValue Tmp5 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp6 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N10, N00, Tmp4, Tmp5, Tmp6 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_273(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_273(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N10, N00, Tmp3, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_274(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_274(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp5 = CurDAG->getTargetConstant(0x10ULL, MVT::i32);
SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N10, N00, Tmp5, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-SDNode *Select_ISD_OR_i32(const SDValue &N) {
+SDNode *Select_ISD_OR_i32(SDNode *N) {
// Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))))
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0 &&
CheckAndMask(N00, Tmp0, INT64_C(255)) &&
- N00.getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001);
+ N00.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::OR) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::AND) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::OR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::AND) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp3 &&
CheckAndMask(N100, Tmp3, INT64_C(65280)) &&
- N100.getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getOperand(0);
+ N100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
if (N000 == N1000) {
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::OR) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp6 &&
CheckAndMask(N1100, Tmp6, INT64_C(16711680)) &&
- N1100.getOpcode() == ISD::SRL) {
- SDValue N11000 = N1100.getOperand(0);
+ N1100.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N11000 = N1100.getNode()->getOperand(0);
if (N000 == N11000) {
- SDValue N11001 = N1100.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ SDValue N11001 = N1100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getOperand(0);
- SDValue N1111 = N111.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
if (Tmp9 &&
CheckAndMask(N1110, Tmp9, INT64_C(4278190080)) &&
- N1110.getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getOperand(0);
+ N1110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
if (N000 == N11100) {
- SDValue N11101 = N1110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -27237,66 +27076,66 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0 &&
CheckAndMask(N00, Tmp0, INT64_C(255)) &&
- N00.getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001);
+ N00.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::OR) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::AND) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::OR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::AND) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp3 &&
CheckAndMask(N100, Tmp3, INT64_C(65280)) &&
- N100.getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getOperand(0);
+ N100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
if (N000 == N1000) {
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::OR) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp6 &&
CheckAndMask(N1100, Tmp6, INT64_C(16711680)) &&
- N1100.getOpcode() == ISD::SRL) {
- SDValue N11000 = N1100.getOperand(0);
+ N1100.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N11000 = N1100.getNode()->getOperand(0);
if (N000 == N11000) {
- SDValue N11001 = N1100.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ SDValue N11001 = N1100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getOperand(0);
- SDValue N1111 = N111.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
if (Tmp9 &&
CheckAndMask(N1110, Tmp9, INT64_C(4278190080)) &&
- N1110.getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getOperand(0);
+ N1110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
if (N000 == N11100) {
- SDValue N11101 = N1110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -27333,66 +27172,66 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0 &&
CheckAndMask(N00, Tmp0, INT64_C(255)) &&
- N00.getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001);
+ N00.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::OR) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::AND) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::OR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::AND) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp3 &&
CheckAndMask(N100, Tmp3, INT64_C(65280)) &&
- N100.getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getOperand(0);
+ N100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
if (N000 == N1000) {
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::OR) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp6 &&
CheckAndMask(N1100, Tmp6, INT64_C(16711680)) &&
- N1100.getOpcode() == ISD::SRL) {
- SDValue N11000 = N1100.getOperand(0);
+ N1100.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N11000 = N1100.getNode()->getOperand(0);
if (N000 == N11000) {
- SDValue N11001 = N1100.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ SDValue N11001 = N1100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getOperand(0);
- SDValue N1111 = N111.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
if (Tmp9 &&
CheckAndMask(N1110, Tmp9, INT64_C(4278190080)) &&
- N1110.getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getOperand(0);
+ N1110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
if (N000 == N11100) {
- SDValue N11101 = N1110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -27425,70 +27264,70 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0 &&
CheckAndMask(N00, Tmp0, INT64_C(255)) &&
- N00.getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001);
+ N00.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::OR) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::OR) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::AND) {
- SDValue N1000 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N1001);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::OR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::OR) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp3) {
// Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)))
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1000, Tmp3, INT64_C(16711680)) &&
- N1000.getOpcode() == ISD::SRL) {
- SDValue N10000 = N1000.getOperand(0);
+ N1000.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10000 = N1000.getNode()->getOperand(0);
if (N000 == N10000) {
- SDValue N10001 = N1000.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
if (Tmp6 &&
CheckAndMask(N1010, Tmp6, INT64_C(65280)) &&
- N1010.getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getOperand(0);
+ N1010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
if (N000 == N10100) {
- SDValue N10101 = N1010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp9 &&
CheckAndMask(N110, Tmp9, INT64_C(4278190080)) &&
- N110.getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getOperand(0);
+ N110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
if (N000 == N1100) {
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -27517,41 +27356,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1000, Tmp3, INT64_C(65280)) &&
- N1000.getOpcode() == ISD::SHL) {
- SDValue N10000 = N1000.getOperand(0);
+ N1000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10000 = N1000.getNode()->getOperand(0);
if (N000 == N10000) {
- SDValue N10001 = N1000.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
if (Tmp6 &&
CheckAndMask(N1010, Tmp6, INT64_C(4278190080)) &&
- N1010.getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getOperand(0);
+ N1010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
if (N000 == N10100) {
- SDValue N10101 = N1010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp9 &&
CheckAndMask(N110, Tmp9, INT64_C(16711680)) &&
- N110.getOpcode() == ISD::SRL) {
- SDValue N1100 = N110.getOperand(0);
+ N110.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
if (N000 == N1100) {
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -27580,41 +27419,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1000, Tmp3, INT64_C(4278190080)) &&
- N1000.getOpcode() == ISD::SHL) {
- SDValue N10000 = N1000.getOperand(0);
+ N1000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10000 = N1000.getNode()->getOperand(0);
if (N000 == N10000) {
- SDValue N10001 = N1000.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
if (Tmp6 &&
CheckAndMask(N1010, Tmp6, INT64_C(65280)) &&
- N1010.getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getOperand(0);
+ N1010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
if (N000 == N10100) {
- SDValue N10101 = N1010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp9 &&
CheckAndMask(N110, Tmp9, INT64_C(16711680)) &&
- N110.getOpcode() == ISD::SRL) {
- SDValue N1100 = N110.getOperand(0);
+ N110.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
if (N000 == N1100) {
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -27643,41 +27482,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1000, Tmp3, INT64_C(16711680)) &&
- N1000.getOpcode() == ISD::SRL) {
- SDValue N10000 = N1000.getOperand(0);
+ N1000.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10000 = N1000.getNode()->getOperand(0);
if (N000 == N10000) {
- SDValue N10001 = N1000.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
if (Tmp6 &&
CheckAndMask(N1010, Tmp6, INT64_C(4278190080)) &&
- N1010.getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getOperand(0);
+ N1010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
if (N000 == N10100) {
- SDValue N10101 = N1010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp9 &&
CheckAndMask(N110, Tmp9, INT64_C(65280)) &&
- N110.getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getOperand(0);
+ N110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
if (N000 == N1100) {
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -27706,41 +27545,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1000, Tmp3, INT64_C(4278190080)) &&
- N1000.getOpcode() == ISD::SHL) {
- SDValue N10000 = N1000.getOperand(0);
+ N1000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10000 = N1000.getNode()->getOperand(0);
if (N000 == N10000) {
- SDValue N10001 = N1000.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
if (Tmp6 &&
CheckAndMask(N1010, Tmp6, INT64_C(16711680)) &&
- N1010.getOpcode() == ISD::SRL) {
- SDValue N10100 = N1010.getOperand(0);
+ N1010.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
if (N000 == N10100) {
- SDValue N10101 = N1010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp9 &&
CheckAndMask(N110, Tmp9, INT64_C(65280)) &&
- N110.getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getOperand(0);
+ N110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
if (N000 == N1100) {
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -27767,53 +27606,53 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
}
- if (N10.getOpcode() == ISD::AND) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101);
+ if (N10.getNode()->getOpcode() == ISD::AND) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp3) {
if (CheckAndMask(N100, Tmp3, INT64_C(4278190080)) &&
- N100.getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getOperand(0);
+ N100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
if (N000 == N1000) {
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::OR) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp6) {
// Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32))))
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1100, Tmp6, INT64_C(65280)) &&
- N1100.getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getOperand(0);
+ N1100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getNode()->getOperand(0);
if (N000 == N11000) {
- SDValue N11001 = N1100.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ SDValue N11001 = N1100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getOperand(0);
- SDValue N1111 = N111.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
if (Tmp9 &&
CheckAndMask(N1110, Tmp9, INT64_C(16711680)) &&
- N1110.getOpcode() == ISD::SRL) {
- SDValue N11100 = N1110.getOperand(0);
+ N1110.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
if (N000 == N11100) {
- SDValue N11101 = N1110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -27837,26 +27676,26 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1100, Tmp6, INT64_C(16711680)) &&
- N1100.getOpcode() == ISD::SRL) {
- SDValue N11000 = N1100.getOperand(0);
+ N1100.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N11000 = N1100.getNode()->getOperand(0);
if (N000 == N11000) {
- SDValue N11001 = N1100.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ SDValue N11001 = N1100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getOperand(0);
- SDValue N1111 = N111.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
if (Tmp9 &&
CheckAndMask(N1110, Tmp9, INT64_C(65280)) &&
- N1110.getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getOperand(0);
+ N1110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
if (N000 == N11100) {
- SDValue N11101 = N1110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -27883,47 +27722,47 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if (CheckAndMask(N100, Tmp3, INT64_C(16711680)) &&
- N100.getOpcode() == ISD::SRL) {
- SDValue N1000 = N100.getOperand(0);
+ N100.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
if (N000 == N1000) {
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::OR) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp6) {
// Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))))
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1100, Tmp6, INT64_C(65280)) &&
- N1100.getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getOperand(0);
+ N1100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getNode()->getOperand(0);
if (N000 == N11000) {
- SDValue N11001 = N1100.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ SDValue N11001 = N1100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getOperand(0);
- SDValue N1111 = N111.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
if (Tmp9 &&
CheckAndMask(N1110, Tmp9, INT64_C(4278190080)) &&
- N1110.getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getOperand(0);
+ N1110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
if (N000 == N11100) {
- SDValue N11101 = N1110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -27947,26 +27786,26 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1100, Tmp6, INT64_C(4278190080)) &&
- N1100.getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getOperand(0);
+ N1100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getNode()->getOperand(0);
if (N000 == N11000) {
- SDValue N11001 = N1100.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ SDValue N11001 = N1100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getOperand(0);
- SDValue N1111 = N111.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
if (Tmp9 &&
CheckAndMask(N1110, Tmp9, INT64_C(65280)) &&
- N1110.getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getOperand(0);
+ N1110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
if (N000 == N11100) {
- SDValue N11101 = N1110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -27997,43 +27836,43 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N100, Tmp3, INT64_C(65280)) &&
- N100.getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getOperand(0);
+ N100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
if (N000 == N1000) {
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::OR) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp6 &&
CheckAndMask(N1100, Tmp6, INT64_C(4278190080)) &&
- N1100.getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getOperand(0);
+ N1100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getNode()->getOperand(0);
if (N000 == N11000) {
- SDValue N11001 = N1100.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ SDValue N11001 = N1100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getOperand(0);
- SDValue N1111 = N111.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
if (Tmp9 &&
CheckAndMask(N1110, Tmp9, INT64_C(16711680)) &&
- N1110.getOpcode() == ISD::SRL) {
- SDValue N11100 = N1110.getOperand(0);
+ N1110.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
if (N000 == N11100) {
- SDValue N11101 = N1110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -28065,69 +27904,69 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::OR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::OR) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::AND) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (N0.getNode()->getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::OR) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp0) {
// Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0000, Tmp0, INT64_C(65280)) &&
- N0000.getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ N0000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp3 &&
CheckAndMask(N0010, Tmp3, INT64_C(16711680)) &&
- N0010.getOpcode() == ISD::SRL) {
- SDValue N00100 = N0010.getOperand(0);
+ N0010.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00100 = N0010.getNode()->getOperand(0);
if (N00000 == N00100) {
- SDValue N00101 = N0010.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::AND) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp6 &&
CheckAndMask(N010, Tmp6, INT64_C(4278190080)) &&
- N010.getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getOperand(0);
+ N010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
if (N00000 == N0100) {
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N00000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -28160,55 +27999,55 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0000, Tmp0, INT64_C(16711680)) &&
- N0000.getOpcode() == ISD::SRL) {
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ N0000.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp3 &&
CheckAndMask(N0010, Tmp3, INT64_C(65280)) &&
- N0010.getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getOperand(0);
+ N0010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getNode()->getOperand(0);
if (N00000 == N00100) {
- SDValue N00101 = N0010.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::AND) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp6 &&
CheckAndMask(N010, Tmp6, INT64_C(4278190080)) &&
- N010.getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getOperand(0);
+ N010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
if (N00000 == N0100) {
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N00000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -28241,55 +28080,55 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0000, Tmp0, INT64_C(65280)) &&
- N0000.getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ N0000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp3 &&
CheckAndMask(N0010, Tmp3, INT64_C(4278190080)) &&
- N0010.getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getOperand(0);
+ N0010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getNode()->getOperand(0);
if (N00000 == N00100) {
- SDValue N00101 = N0010.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::AND) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp6 &&
CheckAndMask(N010, Tmp6, INT64_C(16711680)) &&
- N010.getOpcode() == ISD::SRL) {
- SDValue N0100 = N010.getOperand(0);
+ N010.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
if (N00000 == N0100) {
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N00000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -28322,55 +28161,55 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0000, Tmp0, INT64_C(4278190080)) &&
- N0000.getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ N0000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp3 &&
CheckAndMask(N0010, Tmp3, INT64_C(65280)) &&
- N0010.getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getOperand(0);
+ N0010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getNode()->getOperand(0);
if (N00000 == N00100) {
- SDValue N00101 = N0010.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::AND) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp6 &&
CheckAndMask(N010, Tmp6, INT64_C(16711680)) &&
- N010.getOpcode() == ISD::SRL) {
- SDValue N0100 = N010.getOperand(0);
+ N010.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
if (N00000 == N0100) {
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N00000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -28403,55 +28242,55 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0000, Tmp0, INT64_C(16711680)) &&
- N0000.getOpcode() == ISD::SRL) {
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ N0000.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp3 &&
CheckAndMask(N0010, Tmp3, INT64_C(4278190080)) &&
- N0010.getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getOperand(0);
+ N0010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getNode()->getOperand(0);
if (N00000 == N00100) {
- SDValue N00101 = N0010.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::AND) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp6 &&
CheckAndMask(N010, Tmp6, INT64_C(65280)) &&
- N010.getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getOperand(0);
+ N010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
if (N00000 == N0100) {
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N00000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -28484,55 +28323,55 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0000, Tmp0, INT64_C(4278190080)) &&
- N0000.getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ N0000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp3 &&
CheckAndMask(N0010, Tmp3, INT64_C(16711680)) &&
- N0010.getOpcode() == ISD::SRL) {
- SDValue N00100 = N0010.getOperand(0);
+ N0010.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00100 = N0010.getNode()->getOperand(0);
if (N00000 == N00100) {
- SDValue N00101 = N0010.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::AND) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp6 &&
CheckAndMask(N010, Tmp6, INT64_C(65280)) &&
- N010.getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getOperand(0);
+ N010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
if (N00000 == N0100) {
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N00000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -28563,67 +28402,67 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
}
- if (N00.getOpcode() == ISD::AND) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (N00.getNode()->getOpcode() == ISD::AND) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp0) {
if (CheckAndMask(N000, Tmp0, INT64_C(4278190080)) &&
- N000.getOpcode() == ISD::SHL) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001);
+ N000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::OR) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::OR) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp3) {
// Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0100, Tmp3, INT64_C(65280)) &&
- N0100.getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getOperand(0);
+ N0100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getNode()->getOperand(0);
if (N0000 == N01000) {
- SDValue N01001 = N0100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ SDValue N01001 = N0100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getOperand(0);
- SDValue N0111 = N011.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getNode()->getOperand(0);
+ SDValue N0111 = N011.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
if (Tmp6 &&
CheckAndMask(N0110, Tmp6, INT64_C(16711680)) &&
- N0110.getOpcode() == ISD::SRL) {
- SDValue N01100 = N0110.getOperand(0);
+ N0110.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N01100 = N0110.getNode()->getOperand(0);
if (N0000 == N01100) {
- SDValue N01101 = N0110.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ SDValue N01101 = N0110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N0000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -28652,41 +28491,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0100, Tmp3, INT64_C(16711680)) &&
- N0100.getOpcode() == ISD::SRL) {
- SDValue N01000 = N0100.getOperand(0);
+ N0100.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N01000 = N0100.getNode()->getOperand(0);
if (N0000 == N01000) {
- SDValue N01001 = N0100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ SDValue N01001 = N0100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getOperand(0);
- SDValue N0111 = N011.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getNode()->getOperand(0);
+ SDValue N0111 = N011.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
if (Tmp6 &&
CheckAndMask(N0110, Tmp6, INT64_C(65280)) &&
- N0110.getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getOperand(0);
+ N0110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getNode()->getOperand(0);
if (N0000 == N01100) {
- SDValue N01101 = N0110.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ SDValue N01101 = N0110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N0000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -28717,61 +28556,61 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if (CheckAndMask(N000, Tmp0, INT64_C(16711680)) &&
- N000.getOpcode() == ISD::SRL) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001);
+ N000.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::OR) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::OR) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp3) {
// Pattern: (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0100, Tmp3, INT64_C(65280)) &&
- N0100.getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getOperand(0);
+ N0100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getNode()->getOperand(0);
if (N0000 == N01000) {
- SDValue N01001 = N0100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ SDValue N01001 = N0100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getOperand(0);
- SDValue N0111 = N011.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getNode()->getOperand(0);
+ SDValue N0111 = N011.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
if (Tmp6 &&
CheckAndMask(N0110, Tmp6, INT64_C(4278190080)) &&
- N0110.getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getOperand(0);
+ N0110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getNode()->getOperand(0);
if (N0000 == N01100) {
- SDValue N01101 = N0110.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ SDValue N01101 = N0110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N0000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -28800,41 +28639,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0100, Tmp3, INT64_C(4278190080)) &&
- N0100.getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getOperand(0);
+ N0100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getNode()->getOperand(0);
if (N0000 == N01000) {
- SDValue N01001 = N0100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ SDValue N01001 = N0100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getOperand(0);
- SDValue N0111 = N011.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getNode()->getOperand(0);
+ SDValue N0111 = N011.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
if (Tmp6 &&
CheckAndMask(N0110, Tmp6, INT64_C(65280)) &&
- N0110.getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getOperand(0);
+ N0110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getNode()->getOperand(0);
if (N0000 == N01100) {
- SDValue N01101 = N0110.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ SDValue N01101 = N0110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N0000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -28865,61 +28704,61 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if (CheckAndMask(N000, Tmp0, INT64_C(65280)) &&
- N000.getOpcode() == ISD::SHL) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001);
+ N000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::OR) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::OR) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp3) {
// Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0100, Tmp3, INT64_C(16711680)) &&
- N0100.getOpcode() == ISD::SRL) {
- SDValue N01000 = N0100.getOperand(0);
+ N0100.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N01000 = N0100.getNode()->getOperand(0);
if (N0000 == N01000) {
- SDValue N01001 = N0100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ SDValue N01001 = N0100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getOperand(0);
- SDValue N0111 = N011.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getNode()->getOperand(0);
+ SDValue N0111 = N011.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
if (Tmp6 &&
CheckAndMask(N0110, Tmp6, INT64_C(4278190080)) &&
- N0110.getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getOperand(0);
+ N0110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getNode()->getOperand(0);
if (N0000 == N01100) {
- SDValue N01101 = N0110.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ SDValue N01101 = N0110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N0000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -28948,41 +28787,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0100, Tmp3, INT64_C(4278190080)) &&
- N0100.getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getOperand(0);
+ N0100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getNode()->getOperand(0);
if (N0000 == N01000) {
- SDValue N01001 = N0100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ SDValue N01001 = N0100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getOperand(0);
- SDValue N0111 = N011.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getNode()->getOperand(0);
+ SDValue N0111 = N011.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
if (Tmp6 &&
CheckAndMask(N0110, Tmp6, INT64_C(16711680)) &&
- N0110.getOpcode() == ISD::SRL) {
- SDValue N01100 = N0110.getOperand(0);
+ N0110.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N01100 = N0110.getNode()->getOperand(0);
if (N0000 == N01100) {
- SDValue N01101 = N0110.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ SDValue N01101 = N0110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N0000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -29017,70 +28856,70 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0 &&
CheckAndMask(N00, Tmp0, INT64_C(255)) &&
- N00.getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001);
+ N00.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::OR) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::OR) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::AND) {
- SDValue N1000 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N1001);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::OR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::OR) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp3) {
// Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32)))
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1000, Tmp3, INT64_C(16711680)) &&
- N1000.getOpcode() == ISD::SRL) {
- SDValue N10000 = N1000.getOperand(0);
+ N1000.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10000 = N1000.getNode()->getOperand(0);
if (N000 == N10000) {
- SDValue N10001 = N1000.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
if (Tmp6 &&
CheckAndMask(N1010, Tmp6, INT64_C(65280)) &&
- N1010.getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getOperand(0);
+ N1010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
if (N000 == N10100) {
- SDValue N10101 = N1010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp9 &&
CheckAndMask(N110, Tmp9, INT64_C(4278190080)) &&
- N110.getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getOperand(0);
+ N110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
if (N000 == N1100) {
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -29109,41 +28948,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1000, Tmp3, INT64_C(65280)) &&
- N1000.getOpcode() == ISD::SHL) {
- SDValue N10000 = N1000.getOperand(0);
+ N1000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10000 = N1000.getNode()->getOperand(0);
if (N000 == N10000) {
- SDValue N10001 = N1000.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
if (Tmp6 &&
CheckAndMask(N1010, Tmp6, INT64_C(4278190080)) &&
- N1010.getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getOperand(0);
+ N1010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
if (N000 == N10100) {
- SDValue N10101 = N1010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp9 &&
CheckAndMask(N110, Tmp9, INT64_C(16711680)) &&
- N110.getOpcode() == ISD::SRL) {
- SDValue N1100 = N110.getOperand(0);
+ N110.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
if (N000 == N1100) {
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -29172,41 +29011,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1000, Tmp3, INT64_C(4278190080)) &&
- N1000.getOpcode() == ISD::SHL) {
- SDValue N10000 = N1000.getOperand(0);
+ N1000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10000 = N1000.getNode()->getOperand(0);
if (N000 == N10000) {
- SDValue N10001 = N1000.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
if (Tmp6 &&
CheckAndMask(N1010, Tmp6, INT64_C(65280)) &&
- N1010.getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getOperand(0);
+ N1010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
if (N000 == N10100) {
- SDValue N10101 = N1010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp9 &&
CheckAndMask(N110, Tmp9, INT64_C(16711680)) &&
- N110.getOpcode() == ISD::SRL) {
- SDValue N1100 = N110.getOperand(0);
+ N110.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
if (N000 == N1100) {
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -29235,41 +29074,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1000, Tmp3, INT64_C(16711680)) &&
- N1000.getOpcode() == ISD::SRL) {
- SDValue N10000 = N1000.getOperand(0);
+ N1000.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10000 = N1000.getNode()->getOperand(0);
if (N000 == N10000) {
- SDValue N10001 = N1000.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
if (Tmp6 &&
CheckAndMask(N1010, Tmp6, INT64_C(4278190080)) &&
- N1010.getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getOperand(0);
+ N1010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
if (N000 == N10100) {
- SDValue N10101 = N1010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp9 &&
CheckAndMask(N110, Tmp9, INT64_C(65280)) &&
- N110.getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getOperand(0);
+ N110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
if (N000 == N1100) {
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -29298,41 +29137,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1000, Tmp3, INT64_C(4278190080)) &&
- N1000.getOpcode() == ISD::SHL) {
- SDValue N10000 = N1000.getOperand(0);
+ N1000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10000 = N1000.getNode()->getOperand(0);
if (N000 == N10000) {
- SDValue N10001 = N1000.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
if (Tmp6 &&
CheckAndMask(N1010, Tmp6, INT64_C(16711680)) &&
- N1010.getOpcode() == ISD::SRL) {
- SDValue N10100 = N1010.getOperand(0);
+ N1010.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
if (N000 == N10100) {
- SDValue N10101 = N1010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp9 &&
CheckAndMask(N110, Tmp9, INT64_C(65280)) &&
- N110.getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getOperand(0);
+ N110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
if (N000 == N1100) {
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -29359,53 +29198,53 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
}
- if (N10.getOpcode() == ISD::AND) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101);
+ if (N10.getNode()->getOpcode() == ISD::AND) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp3) {
if (CheckAndMask(N100, Tmp3, INT64_C(4278190080)) &&
- N100.getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getOperand(0);
+ N100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
if (N000 == N1000) {
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::OR) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp6) {
// Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32))))
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1100, Tmp6, INT64_C(65280)) &&
- N1100.getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getOperand(0);
+ N1100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getNode()->getOperand(0);
if (N000 == N11000) {
- SDValue N11001 = N1100.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ SDValue N11001 = N1100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getOperand(0);
- SDValue N1111 = N111.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
if (Tmp9 &&
CheckAndMask(N1110, Tmp9, INT64_C(16711680)) &&
- N1110.getOpcode() == ISD::SRL) {
- SDValue N11100 = N1110.getOperand(0);
+ N1110.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
if (N000 == N11100) {
- SDValue N11101 = N1110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -29429,26 +29268,26 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1100, Tmp6, INT64_C(16711680)) &&
- N1100.getOpcode() == ISD::SRL) {
- SDValue N11000 = N1100.getOperand(0);
+ N1100.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N11000 = N1100.getNode()->getOperand(0);
if (N000 == N11000) {
- SDValue N11001 = N1100.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ SDValue N11001 = N1100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getOperand(0);
- SDValue N1111 = N111.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
if (Tmp9 &&
CheckAndMask(N1110, Tmp9, INT64_C(65280)) &&
- N1110.getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getOperand(0);
+ N1110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
if (N000 == N11100) {
- SDValue N11101 = N1110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -29475,47 +29314,47 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if (CheckAndMask(N100, Tmp3, INT64_C(16711680)) &&
- N100.getOpcode() == ISD::SRL) {
- SDValue N1000 = N100.getOperand(0);
+ N100.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
if (N000 == N1000) {
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::OR) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp6) {
// Pattern: (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32))))
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1100, Tmp6, INT64_C(65280)) &&
- N1100.getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getOperand(0);
+ N1100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getNode()->getOperand(0);
if (N000 == N11000) {
- SDValue N11001 = N1100.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ SDValue N11001 = N1100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getOperand(0);
- SDValue N1111 = N111.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
if (Tmp9 &&
CheckAndMask(N1110, Tmp9, INT64_C(4278190080)) &&
- N1110.getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getOperand(0);
+ N1110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
if (N000 == N11100) {
- SDValue N11101 = N1110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -29539,26 +29378,26 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1100, Tmp6, INT64_C(4278190080)) &&
- N1100.getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getOperand(0);
+ N1100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getNode()->getOperand(0);
if (N000 == N11000) {
- SDValue N11001 = N1100.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ SDValue N11001 = N1100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getOperand(0);
- SDValue N1111 = N111.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
if (Tmp9 &&
CheckAndMask(N1110, Tmp9, INT64_C(65280)) &&
- N1110.getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getOperand(0);
+ N1110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
if (N000 == N11100) {
- SDValue N11101 = N1110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -29589,43 +29428,43 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N100, Tmp3, INT64_C(65280)) &&
- N100.getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getOperand(0);
+ N100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
if (N000 == N1000) {
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::OR) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp6 &&
CheckAndMask(N1100, Tmp6, INT64_C(4278190080)) &&
- N1100.getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getOperand(0);
+ N1100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getNode()->getOperand(0);
if (N000 == N11000) {
- SDValue N11001 = N1100.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ SDValue N11001 = N1100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getOperand(0);
- SDValue N1111 = N111.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
if (Tmp9 &&
CheckAndMask(N1110, Tmp9, INT64_C(16711680)) &&
- N1110.getOpcode() == ISD::SRL) {
- SDValue N11100 = N1110.getOperand(0);
+ N1110.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
if (N000 == N11100) {
- SDValue N11101 = N1110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -29657,69 +29496,69 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::OR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::OR) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::AND) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (N0.getNode()->getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::OR) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp0) {
// Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0000, Tmp0, INT64_C(65280)) &&
- N0000.getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ N0000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp3 &&
CheckAndMask(N0010, Tmp3, INT64_C(16711680)) &&
- N0010.getOpcode() == ISD::SRL) {
- SDValue N00100 = N0010.getOperand(0);
+ N0010.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00100 = N0010.getNode()->getOperand(0);
if (N00000 == N00100) {
- SDValue N00101 = N0010.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::AND) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp6 &&
CheckAndMask(N010, Tmp6, INT64_C(4278190080)) &&
- N010.getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getOperand(0);
+ N010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
if (N00000 == N0100) {
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N00000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -29752,55 +29591,55 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0000, Tmp0, INT64_C(16711680)) &&
- N0000.getOpcode() == ISD::SRL) {
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ N0000.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp3 &&
CheckAndMask(N0010, Tmp3, INT64_C(65280)) &&
- N0010.getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getOperand(0);
+ N0010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getNode()->getOperand(0);
if (N00000 == N00100) {
- SDValue N00101 = N0010.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::AND) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp6 &&
CheckAndMask(N010, Tmp6, INT64_C(4278190080)) &&
- N010.getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getOperand(0);
+ N010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
if (N00000 == N0100) {
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N00000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -29833,55 +29672,55 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0000, Tmp0, INT64_C(65280)) &&
- N0000.getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ N0000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp3 &&
CheckAndMask(N0010, Tmp3, INT64_C(4278190080)) &&
- N0010.getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getOperand(0);
+ N0010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getNode()->getOperand(0);
if (N00000 == N00100) {
- SDValue N00101 = N0010.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::AND) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp6 &&
CheckAndMask(N010, Tmp6, INT64_C(16711680)) &&
- N010.getOpcode() == ISD::SRL) {
- SDValue N0100 = N010.getOperand(0);
+ N010.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
if (N00000 == N0100) {
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N00000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -29914,55 +29753,55 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0000, Tmp0, INT64_C(4278190080)) &&
- N0000.getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ N0000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp3 &&
CheckAndMask(N0010, Tmp3, INT64_C(65280)) &&
- N0010.getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getOperand(0);
+ N0010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getNode()->getOperand(0);
if (N00000 == N00100) {
- SDValue N00101 = N0010.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::AND) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp6 &&
CheckAndMask(N010, Tmp6, INT64_C(16711680)) &&
- N010.getOpcode() == ISD::SRL) {
- SDValue N0100 = N010.getOperand(0);
+ N010.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
if (N00000 == N0100) {
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N00000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -29995,55 +29834,55 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0000, Tmp0, INT64_C(16711680)) &&
- N0000.getOpcode() == ISD::SRL) {
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ N0000.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp3 &&
CheckAndMask(N0010, Tmp3, INT64_C(4278190080)) &&
- N0010.getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getOperand(0);
+ N0010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getNode()->getOperand(0);
if (N00000 == N00100) {
- SDValue N00101 = N0010.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::AND) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp6 &&
CheckAndMask(N010, Tmp6, INT64_C(65280)) &&
- N010.getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getOperand(0);
+ N010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
if (N00000 == N0100) {
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N00000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -30076,55 +29915,55 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0000, Tmp0, INT64_C(4278190080)) &&
- N0000.getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ N0000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp3 &&
CheckAndMask(N0010, Tmp3, INT64_C(16711680)) &&
- N0010.getOpcode() == ISD::SRL) {
- SDValue N00100 = N0010.getOperand(0);
+ N0010.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00100 = N0010.getNode()->getOperand(0);
if (N00000 == N00100) {
- SDValue N00101 = N0010.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::AND) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp6 &&
CheckAndMask(N010, Tmp6, INT64_C(65280)) &&
- N010.getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getOperand(0);
+ N010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
if (N00000 == N0100) {
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N00000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -30155,67 +29994,67 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
}
- if (N00.getOpcode() == ISD::AND) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (N00.getNode()->getOpcode() == ISD::AND) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp0) {
if (CheckAndMask(N000, Tmp0, INT64_C(4278190080)) &&
- N000.getOpcode() == ISD::SHL) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001);
+ N000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::OR) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::OR) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp3) {
// Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32))), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0100, Tmp3, INT64_C(65280)) &&
- N0100.getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getOperand(0);
+ N0100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getNode()->getOperand(0);
if (N0000 == N01000) {
- SDValue N01001 = N0100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ SDValue N01001 = N0100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getOperand(0);
- SDValue N0111 = N011.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getNode()->getOperand(0);
+ SDValue N0111 = N011.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
if (Tmp6 &&
CheckAndMask(N0110, Tmp6, INT64_C(16711680)) &&
- N0110.getOpcode() == ISD::SRL) {
- SDValue N01100 = N0110.getOperand(0);
+ N0110.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N01100 = N0110.getNode()->getOperand(0);
if (N0000 == N01100) {
- SDValue N01101 = N0110.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ SDValue N01101 = N0110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N0000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -30244,41 +30083,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0100, Tmp3, INT64_C(16711680)) &&
- N0100.getOpcode() == ISD::SRL) {
- SDValue N01000 = N0100.getOperand(0);
+ N0100.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N01000 = N0100.getNode()->getOperand(0);
if (N0000 == N01000) {
- SDValue N01001 = N0100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ SDValue N01001 = N0100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getOperand(0);
- SDValue N0111 = N011.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getNode()->getOperand(0);
+ SDValue N0111 = N011.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
if (Tmp6 &&
CheckAndMask(N0110, Tmp6, INT64_C(65280)) &&
- N0110.getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getOperand(0);
+ N0110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getNode()->getOperand(0);
if (N0000 == N01100) {
- SDValue N01101 = N0110.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ SDValue N01101 = N0110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N0000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -30309,61 +30148,61 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if (CheckAndMask(N000, Tmp0, INT64_C(16711680)) &&
- N000.getOpcode() == ISD::SRL) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001);
+ N000.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::OR) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::OR) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp3) {
// Pattern: (or:i32 (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32))), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0100, Tmp3, INT64_C(65280)) &&
- N0100.getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getOperand(0);
+ N0100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getNode()->getOperand(0);
if (N0000 == N01000) {
- SDValue N01001 = N0100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ SDValue N01001 = N0100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getOperand(0);
- SDValue N0111 = N011.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getNode()->getOperand(0);
+ SDValue N0111 = N011.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
if (Tmp6 &&
CheckAndMask(N0110, Tmp6, INT64_C(4278190080)) &&
- N0110.getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getOperand(0);
+ N0110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getNode()->getOperand(0);
if (N0000 == N01100) {
- SDValue N01101 = N0110.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ SDValue N01101 = N0110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N0000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -30392,41 +30231,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0100, Tmp3, INT64_C(4278190080)) &&
- N0100.getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getOperand(0);
+ N0100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getNode()->getOperand(0);
if (N0000 == N01000) {
- SDValue N01001 = N0100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ SDValue N01001 = N0100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getOperand(0);
- SDValue N0111 = N011.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getNode()->getOperand(0);
+ SDValue N0111 = N011.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
if (Tmp6 &&
CheckAndMask(N0110, Tmp6, INT64_C(65280)) &&
- N0110.getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getOperand(0);
+ N0110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getNode()->getOperand(0);
if (N0000 == N01100) {
- SDValue N01101 = N0110.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ SDValue N01101 = N0110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N0000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -30457,61 +30296,61 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if (CheckAndMask(N000, Tmp0, INT64_C(65280)) &&
- N000.getOpcode() == ISD::SHL) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001);
+ N000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::OR) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::OR) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp3) {
// Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 tGPR:i32:$src, 8:i32), 4278190080:i32))), (and:i32 (srl:i32 tGPR:i32:$src, 8:i32), 255:i32))
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0100, Tmp3, INT64_C(16711680)) &&
- N0100.getOpcode() == ISD::SRL) {
- SDValue N01000 = N0100.getOperand(0);
+ N0100.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N01000 = N0100.getNode()->getOperand(0);
if (N0000 == N01000) {
- SDValue N01001 = N0100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ SDValue N01001 = N0100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getOperand(0);
- SDValue N0111 = N011.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getNode()->getOperand(0);
+ SDValue N0111 = N011.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
if (Tmp6 &&
CheckAndMask(N0110, Tmp6, INT64_C(4278190080)) &&
- N0110.getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getOperand(0);
+ N0110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getNode()->getOperand(0);
if (N0000 == N01100) {
- SDValue N01101 = N0110.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ SDValue N01101 = N0110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N0000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -30540,41 +30379,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (tREV16:i32 tGPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0100, Tmp3, INT64_C(4278190080)) &&
- N0100.getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getOperand(0);
+ N0100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getNode()->getOperand(0);
if (N0000 == N01000) {
- SDValue N01001 = N0100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ SDValue N01001 = N0100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getOperand(0);
- SDValue N0111 = N011.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getNode()->getOperand(0);
+ SDValue N0111 = N011.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
if (Tmp6 &&
CheckAndMask(N0110, Tmp6, INT64_C(16711680)) &&
- N0110.getOpcode() == ISD::SRL) {
- SDValue N01100 = N0110.getOperand(0);
+ N0110.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N01100 = N0110.getNode()->getOperand(0);
if (N0000 == N01100) {
- SDValue N01101 = N0110.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ SDValue N01101 = N0110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N0000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -30609,70 +30448,70 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0 &&
CheckAndMask(N00, Tmp0, INT64_C(255)) &&
- N00.getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001);
+ N00.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::OR) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::OR) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::AND) {
- SDValue N1000 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N1001);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::OR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::OR) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp3) {
// Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)))
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1000, Tmp3, INT64_C(16711680)) &&
- N1000.getOpcode() == ISD::SRL) {
- SDValue N10000 = N1000.getOperand(0);
+ N1000.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10000 = N1000.getNode()->getOperand(0);
if (N000 == N10000) {
- SDValue N10001 = N1000.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
if (Tmp6 &&
CheckAndMask(N1010, Tmp6, INT64_C(65280)) &&
- N1010.getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getOperand(0);
+ N1010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
if (N000 == N10100) {
- SDValue N10101 = N1010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp9 &&
CheckAndMask(N110, Tmp9, INT64_C(4278190080)) &&
- N110.getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getOperand(0);
+ N110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
if (N000 == N1100) {
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -30701,41 +30540,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1000, Tmp3, INT64_C(65280)) &&
- N1000.getOpcode() == ISD::SHL) {
- SDValue N10000 = N1000.getOperand(0);
+ N1000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10000 = N1000.getNode()->getOperand(0);
if (N000 == N10000) {
- SDValue N10001 = N1000.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
if (Tmp6 &&
CheckAndMask(N1010, Tmp6, INT64_C(4278190080)) &&
- N1010.getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getOperand(0);
+ N1010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
if (N000 == N10100) {
- SDValue N10101 = N1010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp9 &&
CheckAndMask(N110, Tmp9, INT64_C(16711680)) &&
- N110.getOpcode() == ISD::SRL) {
- SDValue N1100 = N110.getOperand(0);
+ N110.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
if (N000 == N1100) {
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -30764,41 +30603,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1000, Tmp3, INT64_C(4278190080)) &&
- N1000.getOpcode() == ISD::SHL) {
- SDValue N10000 = N1000.getOperand(0);
+ N1000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10000 = N1000.getNode()->getOperand(0);
if (N000 == N10000) {
- SDValue N10001 = N1000.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
if (Tmp6 &&
CheckAndMask(N1010, Tmp6, INT64_C(65280)) &&
- N1010.getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getOperand(0);
+ N1010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
if (N000 == N10100) {
- SDValue N10101 = N1010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp9 &&
CheckAndMask(N110, Tmp9, INT64_C(16711680)) &&
- N110.getOpcode() == ISD::SRL) {
- SDValue N1100 = N110.getOperand(0);
+ N110.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
if (N000 == N1100) {
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -30827,41 +30666,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1000, Tmp3, INT64_C(16711680)) &&
- N1000.getOpcode() == ISD::SRL) {
- SDValue N10000 = N1000.getOperand(0);
+ N1000.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10000 = N1000.getNode()->getOperand(0);
if (N000 == N10000) {
- SDValue N10001 = N1000.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
if (Tmp6 &&
CheckAndMask(N1010, Tmp6, INT64_C(4278190080)) &&
- N1010.getOpcode() == ISD::SHL) {
- SDValue N10100 = N1010.getOperand(0);
+ N1010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
if (N000 == N10100) {
- SDValue N10101 = N1010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp9 &&
CheckAndMask(N110, Tmp9, INT64_C(65280)) &&
- N110.getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getOperand(0);
+ N110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
if (N000 == N1100) {
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -30890,41 +30729,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1000, Tmp3, INT64_C(4278190080)) &&
- N1000.getOpcode() == ISD::SHL) {
- SDValue N10000 = N1000.getOperand(0);
+ N1000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10000 = N1000.getNode()->getOperand(0);
if (N000 == N10000) {
- SDValue N10001 = N1000.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N10001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::AND) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1011.getNode());
if (Tmp6 &&
CheckAndMask(N1010, Tmp6, INT64_C(16711680)) &&
- N1010.getOpcode() == ISD::SRL) {
- SDValue N10100 = N1010.getOperand(0);
+ N1010.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
if (N000 == N10100) {
- SDValue N10101 = N1010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101);
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N10101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp9 &&
CheckAndMask(N110, Tmp9, INT64_C(65280)) &&
- N110.getOpcode() == ISD::SHL) {
- SDValue N1100 = N110.getOperand(0);
+ N110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
if (N000 == N1100) {
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -30951,53 +30790,53 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
}
- if (N10.getOpcode() == ISD::AND) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101);
+ if (N10.getNode()->getOpcode() == ISD::AND) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp3) {
if (CheckAndMask(N100, Tmp3, INT64_C(4278190080)) &&
- N100.getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getOperand(0);
+ N100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
if (N000 == N1000) {
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::OR) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp6) {
// Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32))))
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1100, Tmp6, INT64_C(65280)) &&
- N1100.getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getOperand(0);
+ N1100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getNode()->getOperand(0);
if (N000 == N11000) {
- SDValue N11001 = N1100.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ SDValue N11001 = N1100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getOperand(0);
- SDValue N1111 = N111.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
if (Tmp9 &&
CheckAndMask(N1110, Tmp9, INT64_C(16711680)) &&
- N1110.getOpcode() == ISD::SRL) {
- SDValue N11100 = N1110.getOperand(0);
+ N1110.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
if (N000 == N11100) {
- SDValue N11101 = N1110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -31021,26 +30860,26 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1100, Tmp6, INT64_C(16711680)) &&
- N1100.getOpcode() == ISD::SRL) {
- SDValue N11000 = N1100.getOperand(0);
+ N1100.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N11000 = N1100.getNode()->getOperand(0);
if (N000 == N11000) {
- SDValue N11001 = N1100.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ SDValue N11001 = N1100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getOperand(0);
- SDValue N1111 = N111.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
if (Tmp9 &&
CheckAndMask(N1110, Tmp9, INT64_C(65280)) &&
- N1110.getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getOperand(0);
+ N1110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
if (N000 == N11100) {
- SDValue N11101 = N1110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -31067,47 +30906,47 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if (CheckAndMask(N100, Tmp3, INT64_C(16711680)) &&
- N100.getOpcode() == ISD::SRL) {
- SDValue N1000 = N100.getOperand(0);
+ N100.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
if (N000 == N1000) {
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::OR) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp6) {
// Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))))
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1100, Tmp6, INT64_C(65280)) &&
- N1100.getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getOperand(0);
+ N1100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getNode()->getOperand(0);
if (N000 == N11000) {
- SDValue N11001 = N1100.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ SDValue N11001 = N1100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getOperand(0);
- SDValue N1111 = N111.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
if (Tmp9 &&
CheckAndMask(N1110, Tmp9, INT64_C(4278190080)) &&
- N1110.getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getOperand(0);
+ N1110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
if (N000 == N11100) {
- SDValue N11101 = N1110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -31131,26 +30970,26 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N1100, Tmp6, INT64_C(4278190080)) &&
- N1100.getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getOperand(0);
+ N1100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getNode()->getOperand(0);
if (N000 == N11000) {
- SDValue N11001 = N1100.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ SDValue N11001 = N1100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getOperand(0);
- SDValue N1111 = N111.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
if (Tmp9 &&
CheckAndMask(N1110, Tmp9, INT64_C(65280)) &&
- N1110.getOpcode() == ISD::SHL) {
- SDValue N11100 = N1110.getOperand(0);
+ N1110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
if (N000 == N11100) {
- SDValue N11101 = N1110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -31181,43 +31020,43 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N100, Tmp3, INT64_C(65280)) &&
- N100.getOpcode() == ISD::SHL) {
- SDValue N1000 = N100.getOperand(0);
+ N100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
if (N000 == N1000) {
- SDValue N1001 = N100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::OR) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::AND) {
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::OR) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N1101.getNode());
if (Tmp6 &&
CheckAndMask(N1100, Tmp6, INT64_C(4278190080)) &&
- N1100.getOpcode() == ISD::SHL) {
- SDValue N11000 = N1100.getOperand(0);
+ N1100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N11000 = N1100.getNode()->getOperand(0);
if (N000 == N11000) {
- SDValue N11001 = N1100.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001);
+ SDValue N11001 = N1100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N11001.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::AND) {
- SDValue N1110 = N111.getOperand(0);
- SDValue N1111 = N111.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::AND) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N1111.getNode());
if (Tmp9 &&
CheckAndMask(N1110, Tmp9, INT64_C(16711680)) &&
- N1110.getOpcode() == ISD::SRL) {
- SDValue N11100 = N1110.getOperand(0);
+ N1110.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
if (N000 == N11100) {
- SDValue N11101 = N1110.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N11101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -31249,69 +31088,69 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::OR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::OR) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::AND) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (N0.getNode()->getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::OR) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp0) {
// Pattern: (or:i32 (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32)), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32)), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0000, Tmp0, INT64_C(65280)) &&
- N0000.getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ N0000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp3 &&
CheckAndMask(N0010, Tmp3, INT64_C(16711680)) &&
- N0010.getOpcode() == ISD::SRL) {
- SDValue N00100 = N0010.getOperand(0);
+ N0010.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00100 = N0010.getNode()->getOperand(0);
if (N00000 == N00100) {
- SDValue N00101 = N0010.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::AND) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp6 &&
CheckAndMask(N010, Tmp6, INT64_C(4278190080)) &&
- N010.getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getOperand(0);
+ N010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
if (N00000 == N0100) {
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N00000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -31344,55 +31183,55 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0000, Tmp0, INT64_C(16711680)) &&
- N0000.getOpcode() == ISD::SRL) {
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ N0000.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp3 &&
CheckAndMask(N0010, Tmp3, INT64_C(65280)) &&
- N0010.getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getOperand(0);
+ N0010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getNode()->getOperand(0);
if (N00000 == N00100) {
- SDValue N00101 = N0010.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::AND) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp6 &&
CheckAndMask(N010, Tmp6, INT64_C(4278190080)) &&
- N010.getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getOperand(0);
+ N010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
if (N00000 == N0100) {
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N00000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -31425,55 +31264,55 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0000, Tmp0, INT64_C(65280)) &&
- N0000.getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ N0000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp3 &&
CheckAndMask(N0010, Tmp3, INT64_C(4278190080)) &&
- N0010.getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getOperand(0);
+ N0010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getNode()->getOperand(0);
if (N00000 == N00100) {
- SDValue N00101 = N0010.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::AND) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp6 &&
CheckAndMask(N010, Tmp6, INT64_C(16711680)) &&
- N010.getOpcode() == ISD::SRL) {
- SDValue N0100 = N010.getOperand(0);
+ N010.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
if (N00000 == N0100) {
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N00000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -31506,55 +31345,55 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0000, Tmp0, INT64_C(4278190080)) &&
- N0000.getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ N0000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp3 &&
CheckAndMask(N0010, Tmp3, INT64_C(65280)) &&
- N0010.getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getOperand(0);
+ N0010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getNode()->getOperand(0);
if (N00000 == N00100) {
- SDValue N00101 = N0010.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::AND) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp6 &&
CheckAndMask(N010, Tmp6, INT64_C(16711680)) &&
- N010.getOpcode() == ISD::SRL) {
- SDValue N0100 = N010.getOperand(0);
+ N010.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
if (N00000 == N0100) {
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N00000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -31587,55 +31426,55 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0000, Tmp0, INT64_C(16711680)) &&
- N0000.getOpcode() == ISD::SRL) {
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ N0000.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp3 &&
CheckAndMask(N0010, Tmp3, INT64_C(4278190080)) &&
- N0010.getOpcode() == ISD::SHL) {
- SDValue N00100 = N0010.getOperand(0);
+ N0010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00100 = N0010.getNode()->getOperand(0);
if (N00000 == N00100) {
- SDValue N00101 = N0010.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::AND) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp6 &&
CheckAndMask(N010, Tmp6, INT64_C(65280)) &&
- N010.getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getOperand(0);
+ N010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
if (N00000 == N0100) {
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N00000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -31668,55 +31507,55 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0000, Tmp0, INT64_C(4278190080)) &&
- N0000.getOpcode() == ISD::SHL) {
- SDValue N00000 = N0000.getOperand(0);
- SDValue N00001 = N0000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001);
+ N0000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00000 = N0000.getNode()->getOperand(0);
+ SDValue N00001 = N0000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N00001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::AND) {
- SDValue N0010 = N001.getOperand(0);
- SDValue N0011 = N001.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0010 = N001.getNode()->getOperand(0);
+ SDValue N0011 = N001.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0011.getNode());
if (Tmp3 &&
CheckAndMask(N0010, Tmp3, INT64_C(16711680)) &&
- N0010.getOpcode() == ISD::SRL) {
- SDValue N00100 = N0010.getOperand(0);
+ N0010.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00100 = N0010.getNode()->getOperand(0);
if (N00000 == N00100) {
- SDValue N00101 = N0010.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101);
+ SDValue N00101 = N0010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N00101.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::AND) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::AND) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp6 &&
CheckAndMask(N010, Tmp6, INT64_C(65280)) &&
- N010.getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getOperand(0);
+ N010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
if (N00000 == N0100) {
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N00000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -31747,67 +31586,67 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
}
- if (N00.getOpcode() == ISD::AND) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ if (N00.getNode()->getOpcode() == ISD::AND) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp0) {
if (CheckAndMask(N000, Tmp0, INT64_C(4278190080)) &&
- N000.getOpcode() == ISD::SHL) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001);
+ N000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::OR) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::OR) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp3) {
// Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0100, Tmp3, INT64_C(65280)) &&
- N0100.getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getOperand(0);
+ N0100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getNode()->getOperand(0);
if (N0000 == N01000) {
- SDValue N01001 = N0100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ SDValue N01001 = N0100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getOperand(0);
- SDValue N0111 = N011.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getNode()->getOperand(0);
+ SDValue N0111 = N011.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
if (Tmp6 &&
CheckAndMask(N0110, Tmp6, INT64_C(16711680)) &&
- N0110.getOpcode() == ISD::SRL) {
- SDValue N01100 = N0110.getOperand(0);
+ N0110.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N01100 = N0110.getNode()->getOperand(0);
if (N0000 == N01100) {
- SDValue N01101 = N0110.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ SDValue N01101 = N0110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N0000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -31836,41 +31675,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0100, Tmp3, INT64_C(16711680)) &&
- N0100.getOpcode() == ISD::SRL) {
- SDValue N01000 = N0100.getOperand(0);
+ N0100.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N01000 = N0100.getNode()->getOperand(0);
if (N0000 == N01000) {
- SDValue N01001 = N0100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ SDValue N01001 = N0100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getOperand(0);
- SDValue N0111 = N011.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getNode()->getOperand(0);
+ SDValue N0111 = N011.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
if (Tmp6 &&
CheckAndMask(N0110, Tmp6, INT64_C(65280)) &&
- N0110.getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getOperand(0);
+ N0110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getNode()->getOperand(0);
if (N0000 == N01100) {
- SDValue N01101 = N0110.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ SDValue N01101 = N0110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N0000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -31901,61 +31740,61 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if (CheckAndMask(N000, Tmp0, INT64_C(16711680)) &&
- N000.getOpcode() == ISD::SRL) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001);
+ N000.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::OR) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::OR) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp3) {
// Pattern: (or:i32 (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0100, Tmp3, INT64_C(65280)) &&
- N0100.getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getOperand(0);
+ N0100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getNode()->getOperand(0);
if (N0000 == N01000) {
- SDValue N01001 = N0100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ SDValue N01001 = N0100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getOperand(0);
- SDValue N0111 = N011.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getNode()->getOperand(0);
+ SDValue N0111 = N011.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
if (Tmp6 &&
CheckAndMask(N0110, Tmp6, INT64_C(4278190080)) &&
- N0110.getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getOperand(0);
+ N0110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getNode()->getOperand(0);
if (N0000 == N01100) {
- SDValue N01101 = N0110.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ SDValue N01101 = N0110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N0000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -31984,41 +31823,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0100, Tmp3, INT64_C(4278190080)) &&
- N0100.getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getOperand(0);
+ N0100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getNode()->getOperand(0);
if (N0000 == N01000) {
- SDValue N01001 = N0100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ SDValue N01001 = N0100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getOperand(0);
- SDValue N0111 = N011.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getNode()->getOperand(0);
+ SDValue N0111 = N011.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
if (Tmp6 &&
CheckAndMask(N0110, Tmp6, INT64_C(65280)) &&
- N0110.getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getOperand(0);
+ N0110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getNode()->getOperand(0);
if (N0000 == N01100) {
- SDValue N01101 = N0110.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ SDValue N01101 = N0110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N0000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -32049,61 +31888,61 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if (CheckAndMask(N000, Tmp0, INT64_C(65280)) &&
- N000.getOpcode() == ISD::SHL) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001);
+ N000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::OR) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::OR) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp3) {
// Pattern: (or:i32 (or:i32 (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 65280:i32), (or:i32 (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 16711680:i32), (and:i32 (shl:i32 GPR:i32:$src, 8:i32), 4278190080:i32))), (and:i32 (srl:i32 GPR:i32:$src, 8:i32), 255:i32))
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0100, Tmp3, INT64_C(16711680)) &&
- N0100.getOpcode() == ISD::SRL) {
- SDValue N01000 = N0100.getOperand(0);
+ N0100.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N01000 = N0100.getNode()->getOperand(0);
if (N0000 == N01000) {
- SDValue N01001 = N0100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ SDValue N01001 = N0100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getOperand(0);
- SDValue N0111 = N011.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getNode()->getOperand(0);
+ SDValue N0111 = N011.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
if (Tmp6 &&
CheckAndMask(N0110, Tmp6, INT64_C(4278190080)) &&
- N0110.getOpcode() == ISD::SHL) {
- SDValue N01100 = N0110.getOperand(0);
+ N0110.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01100 = N0110.getNode()->getOperand(0);
if (N0000 == N01100) {
- SDValue N01101 = N0110.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ SDValue N01101 = N0110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N0000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -32132,41 +31971,41 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2REV16:i32 GPR:i32:$src)
// Pattern complexity = 73 cost = 1 size = 0
if (CheckAndMask(N0100, Tmp3, INT64_C(4278190080)) &&
- N0100.getOpcode() == ISD::SHL) {
- SDValue N01000 = N0100.getOperand(0);
+ N0100.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N01000 = N0100.getNode()->getOperand(0);
if (N0000 == N01000) {
- SDValue N01001 = N0100.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001);
+ SDValue N01001 = N0100.getNode()->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N01001.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(8)) {
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::AND) {
- SDValue N0110 = N011.getOperand(0);
- SDValue N0111 = N011.getOperand(1);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0110 = N011.getNode()->getOperand(0);
+ SDValue N0111 = N011.getNode()->getOperand(1);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N0111.getNode());
if (Tmp6 &&
CheckAndMask(N0110, Tmp6, INT64_C(16711680)) &&
- N0110.getOpcode() == ISD::SRL) {
- SDValue N01100 = N0110.getOperand(0);
+ N0110.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N01100 = N0110.getNode()->getOperand(0);
if (N0000 == N01100) {
- SDValue N01101 = N0110.getOperand(1);
- ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101);
+ SDValue N01101 = N0110.getNode()->getOperand(1);
+ ConstantSDNode *Tmp7 = dyn_cast<ConstantSDNode>(N01101.getNode());
if (Tmp7) {
int64_t CN8 = Tmp7->getSExtValue();
if (CN8 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp9 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp9 &&
CheckAndMask(N10, Tmp9, INT64_C(255)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N0000 == N100) {
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp10 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp10) {
int64_t CN11 = Tmp10->getSExtValue();
if (CN11 == INT64_C(8) &&
@@ -32205,24 +32044,24 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
// Pattern complexity = 26 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0 &&
CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp1 &&
CheckAndMask(N10, Tmp1, INT64_C(65535)) &&
- N10.getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant &&
+ N10.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant &&
Predicate_imm16_31(N101.getNode()) &&
N101.getValueType() == MVT::i32) {
SDNode *Result = Emit_263(N, ARM::PKHTB, MVT::i32);
@@ -32234,28 +32073,28 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0 &&
CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp1 &&
CheckAndMask(N10, Tmp1, INT64_C(65535))) {
// Pattern: (or:i32 (and:i32 GPR:i32:$src1, 4294901760:i32), (and:i32 (sra:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt), 65535:i32))
// Emits: (t2PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
// Pattern complexity = 26 cost = 1 size = 0
- if (N10.getOpcode() == ISD::SRA) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant &&
+ if (N10.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant &&
Predicate_imm16_31(N101.getNode()) &&
N101.getValueType() == MVT::i32) {
SDNode *Result = Emit_263(N, ARM::t2PKHTB, MVT::i32);
@@ -32266,10 +32105,10 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Pattern: (or:i32 (and:i32 GPR:i32:$src1, 4294901760:i32), (and:i32 (srl:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt), 65535:i32))
// Emits: (t2PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt)
// Pattern complexity = 26 cost = 1 size = 0
- if (N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant &&
+ if (N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant &&
Predicate_imm1_15(N101.getNode()) &&
N101.getValueType() == MVT::i32) {
SDNode *Result = Emit_263(N, ARM::t2PKHTB, MVT::i32);
@@ -32282,28 +32121,28 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
// Pattern: (or:i32 (and:i32 GPR:i32:$src1, 4294901760:i32), (and:i32 (srl:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt), 65535:i32))
// Emits: (PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt)
// Pattern complexity = 26 cost = 1 size = 0
if (CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp1 &&
CheckAndMask(N10, Tmp1, INT64_C(65535)) &&
- N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant &&
+ N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant &&
Predicate_imm1_15(N101.getNode()) &&
N101.getValueType() == MVT::i32) {
SDNode *Result = Emit_263(N, ARM::PKHTB, MVT::i32);
@@ -32317,16 +32156,16 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
// Pattern complexity = 26 cost = 1 size = 0
if (CheckAndMask(N00, Tmp0, INT64_C(65535)) &&
- N00.getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant &&
+ N00.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant &&
Predicate_imm16_31(N001.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp1 &&
CheckAndMask(N10, Tmp1, INT64_C(4294901760)) &&
N001.getValueType() == MVT::i32) {
@@ -32340,27 +32179,27 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0 &&
CheckAndMask(N00, Tmp0, INT64_C(65535))) {
// Pattern: (or:i32 (and:i32 (sra:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt), 65535:i32), (and:i32 GPR:i32:$src1, 4294901760:i32))
// Emits: (t2PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
// Pattern complexity = 26 cost = 1 size = 0
- if (N00.getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant &&
+ if (N00.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant &&
Predicate_imm16_31(N001.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp1 &&
CheckAndMask(N10, Tmp1, INT64_C(4294901760)) &&
N001.getValueType() == MVT::i32) {
@@ -32374,16 +32213,16 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt), 65535:i32), (and:i32 GPR:i32:$src1, 4294901760:i32))
// Emits: (t2PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt)
// Pattern complexity = 26 cost = 1 size = 0
- if (N00.getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant &&
+ if (N00.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant &&
Predicate_imm1_15(N001.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp1 &&
CheckAndMask(N10, Tmp1, INT64_C(4294901760)) &&
N001.getValueType() == MVT::i32) {
@@ -32397,27 +32236,27 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0 &&
CheckAndMask(N00, Tmp0, INT64_C(65535))) {
// Pattern: (or:i32 (and:i32 (srl:i32 GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt), 65535:i32), (and:i32 GPR:i32:$src1, 4294901760:i32))
// Emits: (PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm1_15>>:$shamt)
// Pattern complexity = 26 cost = 1 size = 0
- if (N00.getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant &&
+ if (N00.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant &&
Predicate_imm1_15(N001.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp1 &&
CheckAndMask(N10, Tmp1, INT64_C(4294901760)) &&
N001.getValueType() == MVT::i32) {
@@ -32431,17 +32270,17 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Pattern: (or:i32 (and:i32 GPR:i32:$src1, 65535:i32), (and:i32 (shl:i32 GPR:i32:$src2, (imm:i32):$shamt), 4294901760:i32))
// Emits: (PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
// Pattern complexity = 25 cost = 1 size = 0
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp1 &&
CheckAndMask(N10, Tmp1, INT64_C(4294901760)) &&
- N10.getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant &&
+ N10.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant &&
N101.getValueType() == MVT::i32) {
SDNode *Result = Emit_263(N, ARM::PKHBT, MVT::i32);
return Result;
@@ -32456,24 +32295,24 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
// Pattern complexity = 25 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0 &&
CheckAndMask(N00, Tmp0, INT64_C(65535))) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp1 &&
CheckAndMask(N10, Tmp1, INT64_C(4294901760)) &&
- N10.getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant &&
+ N10.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant &&
N101.getValueType() == MVT::i32) {
SDNode *Result = Emit_263(N, ARM::t2PKHBT, MVT::i32);
return Result;
@@ -32488,22 +32327,22 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
// Pattern complexity = 25 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0 &&
CheckAndMask(N00, Tmp0, INT64_C(4294901760)) &&
- N00.getOpcode() == ISD::SHL) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ N00.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp1 &&
CheckAndMask(N10, Tmp1, INT64_C(65535)) &&
N001.getValueType() == MVT::i32) {
@@ -32516,26 +32355,26 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (or:i32 (and:i32 (shl:i32 GPR:i32:$src2, (imm:i32):$shamt), 4294901760:i32), (and:i32 GPR:i32:$src1, 65535:i32))
// Emits: (t2PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32):$shamt)
// Pattern complexity = 25 cost = 1 size = 0
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0 &&
CheckAndMask(N00, Tmp0, INT64_C(4294901760)) &&
- N00.getOpcode() == ISD::SHL) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ N00.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp1 &&
CheckAndMask(N10, Tmp1, INT64_C(65535)) &&
N001.getValueType() == MVT::i32) {
@@ -32551,14 +32390,14 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2ORNrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 19 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
SDValue CPTmpN10_0;
SDValue CPTmpN10_1;
if (SelectT2ShifterOperandReg(N, N10, CPTmpN10_0, CPTmpN10_1)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N11.getNode())) {
SDNode *Result = Emit_169(N, ARM::t2ORNrs, MVT::i32, CPTmpN10_0, CPTmpN10_1);
return Result;
@@ -32566,21 +32405,21 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
// Pattern: (or:i32 (and:i32 GPR:i32:$src1, 65535:i32), (and:i32 GPR:i32:$src2, 4294901760:i32))
// Emits: (t2PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, 0:i32)
// Pattern complexity = 19 cost = 1 size = 0
if (CheckAndMask(N00, Tmp0, INT64_C(65535))) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp1 &&
CheckAndMask(N10, Tmp1, INT64_C(4294901760))) {
SDNode *Result = Emit_265(N, ARM::t2PKHBT, MVT::i32);
@@ -32593,11 +32432,11 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, 16:i32)
// Pattern complexity = 19 cost = 1 size = 0
if (CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(16) &&
@@ -32612,22 +32451,22 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
// Pattern: (or:i32 (and:i32 GPR:i32:$src1, 65535:i32), (and:i32 GPR:i32:$src2, 4294901760:i32))
// Emits: (PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, 0:i32)
// Pattern complexity = 19 cost = 1 size = 0
if (CheckAndMask(N00, Tmp0, INT64_C(65535))) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp1 &&
CheckAndMask(N10, Tmp1, INT64_C(4294901760))) {
SDNode *Result = Emit_265(N, ARM::PKHBT, MVT::i32);
@@ -32640,11 +32479,11 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, 16:i32)
// Pattern complexity = 19 cost = 1 size = 0
if (CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(16) &&
@@ -32659,18 +32498,18 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (or:i32 (xor:i32 t2_so_reg:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$lhs)
// Emits: (t2ORNrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 19 cost = 1 size = 0
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
SDValue CPTmpN00_0;
SDValue CPTmpN00_1;
if (SelectT2ShifterOperandReg(N, N00, CPTmpN00_0, CPTmpN00_1)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N01.getNode())) {
SDNode *Result = Emit_180(N, ARM::t2ORNrs, MVT::i32, CPTmpN00_0, CPTmpN00_1);
return Result;
@@ -32681,17 +32520,17 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Pattern: (or:i32 (and:i32 GPR:i32:$src2, 4294901760:i32), (and:i32 GPR:i32:$src1, 65535:i32))
// Emits: (t2PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, 0:i32)
// Pattern complexity = 19 cost = 1 size = 0
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0 &&
CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp1 &&
CheckAndMask(N10, Tmp1, INT64_C(65535))) {
SDNode *Result = Emit_272(N, ARM::t2PKHBT, MVT::i32);
@@ -32704,18 +32543,18 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Pattern: (or:i32 (srl:i32 GPR:i32:$src2, 16:i32), (and:i32 GPR:i32:$src1, 4294901760:i32))
// Emits: (t2PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, 16:i32)
// Pattern complexity = 19 cost = 1 size = 0
- if (N0.getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N0.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp2 &&
CheckAndMask(N10, Tmp2, INT64_C(4294901760)) &&
N01.getValueType() == MVT::i32) {
@@ -32728,22 +32567,22 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (or:i32 (and:i32 GPR:i32:$src2, 4294901760:i32), (and:i32 GPR:i32:$src1, 65535:i32))
// Emits: (PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, 0:i32)
// Pattern complexity = 19 cost = 1 size = 0
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0 &&
CheckAndMask(N00, Tmp0, INT64_C(4294901760))) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp1 &&
CheckAndMask(N10, Tmp1, INT64_C(65535))) {
SDNode *Result = Emit_272(N, ARM::PKHBT, MVT::i32);
@@ -32756,18 +32595,18 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Pattern: (or:i32 (srl:i32 GPR:i32:$src2, 16:i32), (and:i32 GPR:i32:$src1, 4294901760:i32))
// Emits: (PKHTB:i32 GPR:i32:$src1, GPR:i32:$src2, 16:i32)
// Pattern complexity = 19 cost = 1 size = 0
- if (N0.getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N0.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp2 &&
CheckAndMask(N10, Tmp2, INT64_C(4294901760)) &&
N01.getValueType() == MVT::i32) {
@@ -32784,18 +32623,18 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt)
// Pattern complexity = 18 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0 &&
CheckAndMask(N00, Tmp0, INT64_C(65535))) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_imm16_31(N11.getNode()) &&
N11.getValueType() == MVT::i32) {
SDNode *Result = Emit_266(N, ARM::t2PKHBT, MVT::i32);
@@ -32810,18 +32649,18 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt)
// Pattern complexity = 18 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0 &&
CheckAndMask(N00, Tmp0, INT64_C(65535))) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_imm16_31(N11.getNode()) &&
N11.getValueType() == MVT::i32) {
SDNode *Result = Emit_266(N, ARM::PKHBT, MVT::i32);
@@ -32836,17 +32675,17 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt)
// Pattern complexity = 18 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_imm16_31(N01.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(65535)) &&
N01.getValueType() == MVT::i32) {
@@ -32862,17 +32701,17 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (PKHBT:i32 GPR:i32:$src1, GPR:i32:$src2, (imm:i32)<<P:Predicate_imm16_31>>:$shamt)
// Pattern complexity = 18 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_imm16_31(N01.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(65535)) &&
N01.getValueType() == MVT::i32) {
@@ -32888,15 +32727,15 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (MOVTi16:i32 GPR:i32:$src, (hi16:i32 (imm:i32):$imm))
// Pattern complexity = 15 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0 &&
CheckAndMask(N00, Tmp0, INT64_C(65535))) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_lo16AllZero(N1.getNode())) {
SDNode *Result = Emit_261(N, ARM::MOVTi16, MVT::i32);
return Result;
@@ -32909,8 +32748,8 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (ORRrs:i32 GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 15 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -32924,15 +32763,15 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2MOVTi16:i32 GPR:i32:$src, (hi16:i32 (imm:i32):$imm))
// Pattern complexity = 15 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0 &&
CheckAndMask(N00, Tmp0, INT64_C(65535))) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_lo16AllZero(N1.getNode())) {
SDNode *Result = Emit_261(N, ARM::t2MOVTi16, MVT::i32);
return Result;
@@ -32945,7 +32784,7 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (ORRrs:i32 GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 15 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
SDValue CPTmpN0_0;
SDValue CPTmpN0_1;
SDValue CPTmpN0_2;
@@ -32955,19 +32794,19 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (or:i32 GPR:i32:$lhs, (xor:i32 (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>))
// Emits: (t2ORNri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 14 cost = 1 size = 0
if (Predicate_t2_so_imm(N10.getNode())) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N11.getNode())) {
SDNode *Result = Emit_165(N, ARM::t2ORNri, MVT::i32);
return Result;
@@ -32978,8 +32817,8 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2ORNri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 14 cost = 1 size = 0
if (Predicate_immAllOnes(N10.getNode())) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_t2_so_imm(N11.getNode())) {
SDNode *Result = Emit_174(N, ARM::t2ORNri, MVT::i32);
return Result;
@@ -32988,16 +32827,16 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::Constant) {
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (or:i32 (xor:i32 (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$lhs)
// Emits: (t2ORNri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 14 cost = 1 size = 0
if (Predicate_t2_so_imm(N00.getNode())) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N01.getNode())) {
SDNode *Result = Emit_175(N, ARM::t2ORNri, MVT::i32);
return Result;
@@ -33008,8 +32847,8 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2ORNri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 14 cost = 1 size = 0
if (Predicate_immAllOnes(N00.getNode())) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_t2_so_imm(N01.getNode())) {
SDNode *Result = Emit_176(N, ARM::t2ORNri, MVT::i32);
return Result;
@@ -33022,7 +32861,7 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2ORRrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -33047,11 +32886,11 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (t2ORNrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
// Pattern complexity = 10 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N11.getNode())) {
SDNode *Result = Emit_166(N, ARM::t2ORNrr, MVT::i32);
return Result;
@@ -33062,10 +32901,10 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Pattern: (or:i32 (xor:i32 GPR:i32:$rhs, (imm:i32)<<P:Predicate_immAllOnes>>), GPR:i32:$lhs)
// Emits: (t2ORNrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
// Pattern complexity = 10 cost = 1 size = 0
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N01.getNode())) {
SDNode *Result = Emit_177(N, ARM::t2ORNrr, MVT::i32);
return Result;
@@ -33075,8 +32914,8 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Pattern: (or:i32 GPR:i32:$src, 4294901760:i32)
// Emits: (t2MOVTi16:i32 GPR:i32:$src, 65535:i32)
// Pattern complexity = 8 cost = 1 size = 0
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0 &&
CheckOrMask(N0, Tmp0, INT64_C(4294901760))) {
SDNode *Result = Emit_264(N, ARM::t2MOVTi16, MVT::i32);
@@ -33088,9 +32927,9 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (MOVTi16:i32 GPR:i32:$src, 65535:i32)
// Pattern complexity = 8 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0 &&
CheckOrMask(N0, Tmp0, INT64_C(4294901760))) {
SDNode *Result = Emit_264(N, ARM::MOVTi16, MVT::i32);
@@ -33102,18 +32941,18 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (ORRri:i32 GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 7 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N1.getNode())) {
SDNode *Result = Emit_55(N, ARM::ORRri, MVT::i32);
return Result;
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (or:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
// Emits: (t2ORRri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
@@ -33146,9 +32985,9 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Emits: (ORRri:i32 (ORRri:i32 GPR:i32:$LHS, (so_imm2part_1:i32 (imm:i32):$RHS)), (so_imm2part_2:i32 (imm:i32):$RHS))
// Pattern complexity = 7 cost = 2 size = 0
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm2part(N1.getNode())) {
SDNode *Result = Emit_74(N, ARM::ORRri, ARM::ORRri, MVT::i32, MVT::i32);
return Result;
@@ -33182,197 +33021,197 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_275(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
+DISABLE_INLINE SDNode *Emit_275(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N01, N00, N10, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_276(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_276(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N01, N00, N11, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_277(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_277(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N01, N10, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_278(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_278(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N01, N11, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_279(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_279(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N010, N10, N00, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_280(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_280(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N010, N11, N00, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_281(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_281(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N011, N10, N00, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_282(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_282(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N011, N11, N00, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_283(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_283(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N000, N10, N01, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_284(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_284(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N000, N11, N01, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_285(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_285(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N001, N10, N01, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_286(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_286(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N001, N11, N01, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-SDNode *Select_ISD_OR_v2i32(const SDValue &N) {
+SDNode *Select_ISD_OR_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
{
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::XOR) {
- SDValue N110 = N11.getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N110 = N11.getNode()->getOperand(0);
// Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1), (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>)))
// Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
if (N01 == N110) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N111.getNode())) {
SDNode *Result = Emit_275(N, ARM::VBSLd, MVT::v2i32);
return Result;
@@ -33382,9 +33221,9 @@ SDNode *Select_ISD_OR_v2i32(const SDValue &N) {
// Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1), (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1)))
// Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
- if (N110.getOpcode() == ISD::BIT_CONVERT &&
+ if (N110.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N110.getNode())) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
if (N01 == N111) {
SDNode *Result = Emit_275(N, ARM::VBSLd, MVT::v2i32);
return Result;
@@ -33392,15 +33231,15 @@ SDNode *Select_ISD_OR_v2i32(const SDValue &N) {
}
}
}
- if (N10.getOpcode() == ISD::XOR) {
- SDValue N100 = N10.getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N100 = N10.getNode()->getOperand(0);
// Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1), (and:v2i32 (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>), DPR:v2i32:$src3))
// Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
if (N01 == N100) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N101.getNode())) {
SDNode *Result = Emit_276(N, ARM::VBSLd, MVT::v2i32);
return Result;
@@ -33410,9 +33249,9 @@ SDNode *Select_ISD_OR_v2i32(const SDValue &N) {
// Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1), (and:v2i32 (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1), DPR:v2i32:$src3))
// Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
- if (N100.getOpcode() == ISD::BIT_CONVERT &&
+ if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N100.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
if (N01 == N101) {
SDNode *Result = Emit_276(N, ARM::VBSLd, MVT::v2i32);
return Result;
@@ -33420,16 +33259,16 @@ SDNode *Select_ISD_OR_v2i32(const SDValue &N) {
}
}
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::XOR) {
- SDValue N110 = N11.getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N110 = N11.getNode()->getOperand(0);
// Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2), (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>)))
// Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
if (N00 == N110) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N111.getNode())) {
SDNode *Result = Emit_277(N, ARM::VBSLd, MVT::v2i32);
return Result;
@@ -33439,9 +33278,9 @@ SDNode *Select_ISD_OR_v2i32(const SDValue &N) {
// Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2), (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1)))
// Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
- if (N110.getOpcode() == ISD::BIT_CONVERT &&
+ if (N110.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N110.getNode())) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
if (N00 == N111) {
SDNode *Result = Emit_277(N, ARM::VBSLd, MVT::v2i32);
return Result;
@@ -33449,15 +33288,15 @@ SDNode *Select_ISD_OR_v2i32(const SDValue &N) {
}
}
}
- if (N10.getOpcode() == ISD::XOR) {
- SDValue N100 = N10.getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N100 = N10.getNode()->getOperand(0);
// Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2), (and:v2i32 (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>), DPR:v2i32:$src3))
// Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
if (N00 == N100) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N101.getNode())) {
SDNode *Result = Emit_278(N, ARM::VBSLd, MVT::v2i32);
return Result;
@@ -33467,9 +33306,9 @@ SDNode *Select_ISD_OR_v2i32(const SDValue &N) {
// Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2), (and:v2i32 (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1), DPR:v2i32:$src3))
// Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
- if (N100.getOpcode() == ISD::BIT_CONVERT &&
+ if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N100.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
if (N00 == N101) {
SDNode *Result = Emit_278(N, ARM::VBSLd, MVT::v2i32);
return Result;
@@ -33478,21 +33317,21 @@ SDNode *Select_ISD_OR_v2i32(const SDValue &N) {
}
}
}
- if (N01.getOpcode() == ISD::XOR) {
- SDValue N010 = N01.getOperand(0);
+ if (N01.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N010 = N01.getNode()->getOperand(0);
{
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N011.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>)), (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1))
// Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N010 == N11) {
SDNode *Result = Emit_279(N, ARM::VBSLd, MVT::v2i32);
return Result;
@@ -33509,18 +33348,18 @@ SDNode *Select_ISD_OR_v2i32(const SDValue &N) {
}
}
}
- if (N010.getOpcode() == ISD::BIT_CONVERT &&
+ if (N010.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N010.getNode())) {
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (or:v2i32 (and:v2i32 DPR:v2i32:$src3, (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1)), (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1))
// Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N011 == N11) {
SDNode *Result = Emit_281(N, ARM::VBSLd, MVT::v2i32);
return Result;
@@ -33538,22 +33377,22 @@ SDNode *Select_ISD_OR_v2i32(const SDValue &N) {
}
}
}
- if (N00.getOpcode() == ISD::XOR) {
- SDValue N000 = N00.getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N000 = N00.getNode()->getOperand(0);
{
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N001.getNode())) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (or:v2i32 (and:v2i32 (xor:v2i32 DPR:v2i32:$src1, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>), DPR:v2i32:$src3), (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1))
// Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N000 == N11) {
SDNode *Result = Emit_283(N, ARM::VBSLd, MVT::v2i32);
return Result;
@@ -33570,19 +33409,19 @@ SDNode *Select_ISD_OR_v2i32(const SDValue &N) {
}
}
}
- if (N000.getOpcode() == ISD::BIT_CONVERT &&
+ if (N000.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N000.getNode())) {
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (or:v2i32 (and:v2i32 (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src1), DPR:v2i32:$src3), (and:v2i32 DPR:v2i32:$src2, DPR:v2i32:$src1))
// Emits: (VBSLd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N001 == N11) {
SDNode *Result = Emit_285(N, ARM::VBSLd, MVT::v2i32);
return Result;
@@ -33601,16 +33440,16 @@ SDNode *Select_ISD_OR_v2i32(const SDValue &N) {
}
}
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (or:v2i32 DPR:v2i32:$src1, (xor:v2i32 DPR:v2i32:$src2, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>))
// Emits: (VORNd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 10 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N11.getNode())) {
SDNode *Result = Emit_51(N, ARM::VORNd, MVT::v2i32);
return Result;
@@ -33620,22 +33459,22 @@ SDNode *Select_ISD_OR_v2i32(const SDValue &N) {
// Pattern: (or:v2i32 DPR:v2i32:$src1, (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src2))
// Emits: (VORNd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 10 cost = 1 size = 0
- if (N10.getOpcode() == ISD::BIT_CONVERT &&
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N10.getNode())) {
SDNode *Result = Emit_181(N, ARM::VORNd, MVT::v2i32);
return Result;
}
}
}
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (or:v2i32 (xor:v2i32 DPR:v2i32:$src2, (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>), DPR:v2i32:$src1)
// Emits: (VORNd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 10 cost = 1 size = 0
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N01.getNode())) {
SDNode *Result = Emit_84(N, ARM::VORNd, MVT::v2i32);
return Result;
@@ -33645,7 +33484,7 @@ SDNode *Select_ISD_OR_v2i32(const SDValue &N) {
// Pattern: (or:v2i32 (xor:v2i32 (bitconvert:v2i32)<<P:Predicate_immAllOnesV_bc>>, DPR:v2i32:$src2), DPR:v2i32:$src1)
// Emits: (VORNd:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2)
// Pattern complexity = 10 cost = 1 size = 0
- if (N00.getOpcode() == ISD::BIT_CONVERT &&
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N00.getNode())) {
SDNode *Result = Emit_182(N, ARM::VORNd, MVT::v2i32);
return Result;
@@ -33664,29 +33503,29 @@ SDNode *Select_ISD_OR_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_OR_v4i32(const SDValue &N) {
+SDNode *Select_ISD_OR_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
{
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::XOR) {
- SDValue N110 = N11.getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N110 = N11.getNode()->getOperand(0);
// Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1), (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>)))
// Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
if (N01 == N110) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N111.getNode())) {
SDNode *Result = Emit_275(N, ARM::VBSLq, MVT::v4i32);
return Result;
@@ -33696,9 +33535,9 @@ SDNode *Select_ISD_OR_v4i32(const SDValue &N) {
// Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1), (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1)))
// Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
- if (N110.getOpcode() == ISD::BIT_CONVERT &&
+ if (N110.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N110.getNode())) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
if (N01 == N111) {
SDNode *Result = Emit_275(N, ARM::VBSLq, MVT::v4i32);
return Result;
@@ -33706,15 +33545,15 @@ SDNode *Select_ISD_OR_v4i32(const SDValue &N) {
}
}
}
- if (N10.getOpcode() == ISD::XOR) {
- SDValue N100 = N10.getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N100 = N10.getNode()->getOperand(0);
// Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1), (and:v4i32 (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>), QPR:v4i32:$src3))
// Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
if (N01 == N100) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N101.getNode())) {
SDNode *Result = Emit_276(N, ARM::VBSLq, MVT::v4i32);
return Result;
@@ -33724,9 +33563,9 @@ SDNode *Select_ISD_OR_v4i32(const SDValue &N) {
// Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1), (and:v4i32 (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1), QPR:v4i32:$src3))
// Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
- if (N100.getOpcode() == ISD::BIT_CONVERT &&
+ if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N100.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
if (N01 == N101) {
SDNode *Result = Emit_276(N, ARM::VBSLq, MVT::v4i32);
return Result;
@@ -33734,16 +33573,16 @@ SDNode *Select_ISD_OR_v4i32(const SDValue &N) {
}
}
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::XOR) {
- SDValue N110 = N11.getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N110 = N11.getNode()->getOperand(0);
// Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2), (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>)))
// Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
if (N00 == N110) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N111.getNode())) {
SDNode *Result = Emit_277(N, ARM::VBSLq, MVT::v4i32);
return Result;
@@ -33753,9 +33592,9 @@ SDNode *Select_ISD_OR_v4i32(const SDValue &N) {
// Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2), (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1)))
// Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
- if (N110.getOpcode() == ISD::BIT_CONVERT &&
+ if (N110.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N110.getNode())) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
if (N00 == N111) {
SDNode *Result = Emit_277(N, ARM::VBSLq, MVT::v4i32);
return Result;
@@ -33763,15 +33602,15 @@ SDNode *Select_ISD_OR_v4i32(const SDValue &N) {
}
}
}
- if (N10.getOpcode() == ISD::XOR) {
- SDValue N100 = N10.getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N100 = N10.getNode()->getOperand(0);
// Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2), (and:v4i32 (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>), QPR:v4i32:$src3))
// Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
if (N00 == N100) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N101.getNode())) {
SDNode *Result = Emit_278(N, ARM::VBSLq, MVT::v4i32);
return Result;
@@ -33781,9 +33620,9 @@ SDNode *Select_ISD_OR_v4i32(const SDValue &N) {
// Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2), (and:v4i32 (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1), QPR:v4i32:$src3))
// Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
- if (N100.getOpcode() == ISD::BIT_CONVERT &&
+ if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N100.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
if (N00 == N101) {
SDNode *Result = Emit_278(N, ARM::VBSLq, MVT::v4i32);
return Result;
@@ -33792,21 +33631,21 @@ SDNode *Select_ISD_OR_v4i32(const SDValue &N) {
}
}
}
- if (N01.getOpcode() == ISD::XOR) {
- SDValue N010 = N01.getOperand(0);
+ if (N01.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N010 = N01.getNode()->getOperand(0);
{
- SDValue N011 = N01.getOperand(1);
- if (N011.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (N011.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N011.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>)), (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1))
// Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N010 == N11) {
SDNode *Result = Emit_279(N, ARM::VBSLq, MVT::v4i32);
return Result;
@@ -33823,18 +33662,18 @@ SDNode *Select_ISD_OR_v4i32(const SDValue &N) {
}
}
}
- if (N010.getOpcode() == ISD::BIT_CONVERT &&
+ if (N010.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N010.getNode())) {
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (or:v4i32 (and:v4i32 QPR:v4i32:$src3, (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1)), (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1))
// Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N011 == N11) {
SDNode *Result = Emit_281(N, ARM::VBSLq, MVT::v4i32);
return Result;
@@ -33852,22 +33691,22 @@ SDNode *Select_ISD_OR_v4i32(const SDValue &N) {
}
}
}
- if (N00.getOpcode() == ISD::XOR) {
- SDValue N000 = N00.getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N000 = N00.getNode()->getOperand(0);
{
- SDValue N001 = N00.getOperand(1);
- if (N001.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (N001.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N001.getNode())) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (or:v4i32 (and:v4i32 (xor:v4i32 QPR:v4i32:$src1, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>), QPR:v4i32:$src3), (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1))
// Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N000 == N11) {
SDNode *Result = Emit_283(N, ARM::VBSLq, MVT::v4i32);
return Result;
@@ -33884,19 +33723,19 @@ SDNode *Select_ISD_OR_v4i32(const SDValue &N) {
}
}
}
- if (N000.getOpcode() == ISD::BIT_CONVERT &&
+ if (N000.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N000.getNode())) {
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (or:v4i32 (and:v4i32 (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src1), QPR:v4i32:$src3), (and:v4i32 QPR:v4i32:$src2, QPR:v4i32:$src1))
// Emits: (VBSLq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
// Pattern complexity = 16 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N001 == N11) {
SDNode *Result = Emit_285(N, ARM::VBSLq, MVT::v4i32);
return Result;
@@ -33915,16 +33754,16 @@ SDNode *Select_ISD_OR_v4i32(const SDValue &N) {
}
}
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (or:v4i32 QPR:v4i32:$src1, (xor:v4i32 QPR:v4i32:$src2, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>))
// Emits: (VORNq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 10 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N11.getNode())) {
SDNode *Result = Emit_51(N, ARM::VORNq, MVT::v4i32);
return Result;
@@ -33934,22 +33773,22 @@ SDNode *Select_ISD_OR_v4i32(const SDValue &N) {
// Pattern: (or:v4i32 QPR:v4i32:$src1, (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src2))
// Emits: (VORNq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 10 cost = 1 size = 0
- if (N10.getOpcode() == ISD::BIT_CONVERT &&
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N10.getNode())) {
SDNode *Result = Emit_181(N, ARM::VORNq, MVT::v4i32);
return Result;
}
}
}
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (or:v4i32 (xor:v4i32 QPR:v4i32:$src2, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>), QPR:v4i32:$src1)
// Emits: (VORNq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 10 cost = 1 size = 0
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N01.getNode())) {
SDNode *Result = Emit_84(N, ARM::VORNq, MVT::v4i32);
return Result;
@@ -33959,7 +33798,7 @@ SDNode *Select_ISD_OR_v4i32(const SDValue &N) {
// Pattern: (or:v4i32 (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, QPR:v4i32:$src2), QPR:v4i32:$src1)
// Emits: (VORNq:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2)
// Pattern complexity = 10 cost = 1 size = 0
- if (N00.getOpcode() == ISD::BIT_CONVERT &&
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N00.getNode())) {
SDNode *Result = Emit_182(N, ARM::VORNq, MVT::v4i32);
return Result;
@@ -33978,14 +33817,14 @@ SDNode *Select_ISD_OR_v4i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_287(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN_0, SDValue &CPTmpN_1, SDValue &CPTmpN_2) {
+DISABLE_INLINE SDNode *Emit_287(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN_0, SDValue &CPTmpN_1, SDValue &CPTmpN_2) {
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { CPTmpN_0, CPTmpN_1, CPTmpN_2, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
}
-SDNode *Select_ISD_ROTR_i32(const SDValue &N) {
+SDNode *Select_ISD_ROTR_i32(SDNode *N) {
// Pattern: so_reg:i32:$src
// Emits: (MOVs:i32 so_reg:i32:$src)
@@ -33994,7 +33833,7 @@ SDNode *Select_ISD_ROTR_i32(const SDValue &N) {
SDValue CPTmpN_0;
SDValue CPTmpN_1;
SDValue CPTmpN_2;
- if (SelectShifterOperandReg(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2)) {
+ if (SelectShifterOperandReg(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2)) {
SDNode *Result = Emit_287(N, ARM::MOVs, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2);
return Result;
}
@@ -34004,9 +33843,9 @@ SDNode *Select_ISD_ROTR_i32(const SDValue &N) {
// Emits: (t2RORri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 7 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_imm1_31(N1.getNode()) &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_55(N, ARM::t2RORri, MVT::i32);
@@ -34018,8 +33857,8 @@ SDNode *Select_ISD_ROTR_i32(const SDValue &N) {
// Emits: (tROR:i32 tGPR:i32:$lhs, tGPR:i32:$rhs)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_66(N, ARM::tROR, MVT::i32);
return Result;
@@ -34030,8 +33869,8 @@ SDNode *Select_ISD_ROTR_i32(const SDValue &N) {
// Emits: (t2RORrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_56(N, ARM::t2RORrr, MVT::i32);
return Result;
@@ -34042,17 +33881,17 @@ SDNode *Select_ISD_ROTR_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_288(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
+DISABLE_INLINE SDNode *Emit_288(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Tmp0(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops1[] = { Tmp0, N0, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Ops1, 5);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Ops1, 5);
}
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v8i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v8i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_288(N, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi8, MVT::v8i8, MVT::v8i8);
return Result;
@@ -34062,20 +33901,20 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v8i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_289(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
- SDValue N0 = N.getOperand(0);
- SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
- SDValue Tmp1(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1), 0);
+DISABLE_INLINE SDNode *Emit_289(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Tmp0(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
+ SDValue Tmp1(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1), 0);
SDValue Tmp3 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops2[] = { Tmp1, N0, Tmp3, Tmp4, Tmp5 };
- SDValue Tmp6(CurDAG->getMachineNode(Opc2, N.getDebugLoc(), VT2, Ops2, 5), 0);
+ SDValue Tmp6(CurDAG->getMachineNode(Opc2, N->getDebugLoc(), VT2, Ops2, 5), 0);
SDValue Tmp7 = CurDAG->getTargetConstant(0x5ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc3, VT3, Tmp0, Tmp6, Tmp7);
+ return CurDAG->SelectNodeTo(N, Opc3, VT3, Tmp0, Tmp6, Tmp7);
}
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v16i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v16i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_289(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi8, TargetInstrInfo::INSERT_SUBREG, MVT::v16i8, MVT::v8i8, MVT::f64, MVT::v16i8);
return Result;
@@ -34085,8 +33924,8 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_288(N, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi16, MVT::v4i16, MVT::v4i16);
return Result;
@@ -34096,8 +33935,8 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v8i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v8i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_289(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi16, TargetInstrInfo::INSERT_SUBREG, MVT::v8i16, MVT::v4i16, MVT::f64, MVT::v8i16);
return Result;
@@ -34107,8 +33946,8 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_288(N, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi32, MVT::v2i32, MVT::v2i32);
return Result;
@@ -34118,8 +33957,8 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_289(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi32, TargetInstrInfo::INSERT_SUBREG, MVT::v4i32, MVT::v2i32, MVT::f64, MVT::v4i32);
return Result;
@@ -34129,14 +33968,14 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_290(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
+DISABLE_INLINE SDNode *Emit_290(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Tmp0(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
SDValue Tmp2 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp0, N0, Tmp2);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp0, N0, Tmp2);
}
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
SDNode *Result = Emit_290(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, MVT::v2f32, MVT::v2f32);
return Result;
@@ -34146,8 +33985,8 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v4f32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v4f32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
SDNode *Result = Emit_290(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, MVT::v4f32, MVT::v4f32);
return Result;
@@ -34157,14 +33996,14 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v4f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_291(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
+DISABLE_INLINE SDNode *Emit_291(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Tmp0(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
SDValue Tmp2 = CurDAG->getTargetConstant(0x5ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp0, N0, Tmp2);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp0, N0, Tmp2);
}
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f64) {
SDNode *Result = Emit_291(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, MVT::v2f64, MVT::v2f64);
return Result;
@@ -34174,7 +34013,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SHL_i32(const SDValue &N) {
+SDNode *Select_ISD_SHL_i32(SDNode *N) {
// Pattern: so_reg:i32:$src
// Emits: (MOVs:i32 so_reg:i32:$src)
@@ -34183,7 +34022,7 @@ SDNode *Select_ISD_SHL_i32(const SDValue &N) {
SDValue CPTmpN_0;
SDValue CPTmpN_1;
SDValue CPTmpN_2;
- if (SelectShifterOperandReg(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2)) {
+ if (SelectShifterOperandReg(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2)) {
SDNode *Result = Emit_287(N, ARM::MOVs, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2);
return Result;
}
@@ -34193,9 +34032,9 @@ SDNode *Select_ISD_SHL_i32(const SDValue &N) {
// Emits: (t2LSLri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 7 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_imm1_31(N1.getNode()) &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_55(N, ARM::t2LSLri, MVT::i32);
@@ -34203,13 +34042,13 @@ SDNode *Select_ISD_SHL_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (shl:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
// Emits: (tLSLri:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_65(N, ARM::tLSLri, MVT::i32);
return Result;
@@ -34228,8 +34067,8 @@ SDNode *Select_ISD_SHL_i32(const SDValue &N) {
// Emits: (t2LSLrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_56(N, ARM::t2LSLrr, MVT::i32);
return Result;
@@ -34240,87 +34079,87 @@ SDNode *Select_ISD_SHL_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_292(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_292(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1, Tmp2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_293(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_293(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_294(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_294(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0000, Tmp6, Tmp7);
-}
-DISABLE_INLINE SDNode *Emit_295(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0000, Tmp6, Tmp7);
+}
+DISABLE_INLINE SDNode *Emit_295(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N000, Tmp6, Tmp7);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N000, Tmp6, Tmp7);
}
-SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
+SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(SDNode *N) {
// Pattern: (sext_inreg:i32 (or:i32 (srl:i32 (and:i32 GPR:i32:$src, 65280:i32), 8:i32), (shl:i32 GPR:i32:$src, 8:i32)), i16:Other)
// Emits: (REVSH:i32 GPR:i32:$src)
// Pattern complexity = 30 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::OR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::AND) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp0 &&
CheckAndMask(N0000, Tmp0, INT64_C(65280))) {
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SHL) {
- SDValue N010 = N01.getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N010 = N01.getNode()->getOperand(0);
if (N0000 == N010) {
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp3) {
int64_t CN4 = Tmp3->getSExtValue();
if (CN4 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (cast<VTSDNode>(N1)->getVT() == MVT::i16 &&
+ SDValue N1 = N->getOperand(1);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16 &&
N001.getValueType() == MVT::i32 &&
N011.getValueType() == MVT::i32) {
SDNode *Result = Emit_294(N, ARM::REVSH, MVT::i32);
@@ -34342,33 +34181,33 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
// Emits: (tREVSH:i32 tGPR:i32:$src)
// Pattern complexity = 30 cost = 1 size = 0
if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::OR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::AND) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp0 &&
CheckAndMask(N0000, Tmp0, INT64_C(65280))) {
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SHL) {
- SDValue N010 = N01.getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N010 = N01.getNode()->getOperand(0);
if (N0000 == N010) {
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp3) {
int64_t CN4 = Tmp3->getSExtValue();
if (CN4 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (cast<VTSDNode>(N1)->getVT() == MVT::i16 &&
+ SDValue N1 = N->getOperand(1);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16 &&
N001.getValueType() == MVT::i32 &&
N011.getValueType() == MVT::i32) {
SDNode *Result = Emit_294(N, ARM::tREVSH, MVT::i32);
@@ -34390,33 +34229,33 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
// Emits: (t2REVSH:i32 GPR:i32:$src)
// Pattern complexity = 30 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::OR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::SRL) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::AND) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp0 &&
CheckAndMask(N0000, Tmp0, INT64_C(65280))) {
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SHL) {
- SDValue N010 = N01.getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N010 = N01.getNode()->getOperand(0);
if (N0000 == N010) {
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp3) {
int64_t CN4 = Tmp3->getSExtValue();
if (CN4 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (cast<VTSDNode>(N1)->getVT() == MVT::i16 &&
+ SDValue N1 = N->getOperand(1);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16 &&
N001.getValueType() == MVT::i32 &&
N011.getValueType() == MVT::i32) {
SDNode *Result = Emit_294(N, ARM::t2REVSH, MVT::i32);
@@ -34438,33 +34277,33 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
// Emits: (REVSH:i32 GPR:i32:$src)
// Pattern complexity = 30 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::OR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::SHL) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SRL) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp2 &&
CheckAndMask(N0100, Tmp2, INT64_C(65280)) &&
N000 == N0100) {
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp3) {
int64_t CN4 = Tmp3->getSExtValue();
if (CN4 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (cast<VTSDNode>(N1)->getVT() == MVT::i16 &&
+ SDValue N1 = N->getOperand(1);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16 &&
N001.getValueType() == MVT::i32 &&
N011.getValueType() == MVT::i32) {
SDNode *Result = Emit_295(N, ARM::REVSH, MVT::i32);
@@ -34485,33 +34324,33 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
// Emits: (tREVSH:i32 tGPR:i32:$src)
// Pattern complexity = 30 cost = 1 size = 0
if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::OR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::SHL) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SRL) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp2 &&
CheckAndMask(N0100, Tmp2, INT64_C(65280)) &&
N000 == N0100) {
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp3) {
int64_t CN4 = Tmp3->getSExtValue();
if (CN4 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (cast<VTSDNode>(N1)->getVT() == MVT::i16 &&
+ SDValue N1 = N->getOperand(1);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16 &&
N001.getValueType() == MVT::i32 &&
N011.getValueType() == MVT::i32) {
SDNode *Result = Emit_295(N, ARM::tREVSH, MVT::i32);
@@ -34532,33 +34371,33 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
// Emits: (t2REVSH:i32 GPR:i32:$src)
// Pattern complexity = 30 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::OR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::SHL) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(8)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SRL) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::AND) {
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::AND) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp2 &&
CheckAndMask(N0100, Tmp2, INT64_C(65280)) &&
N000 == N0100) {
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp3 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp3) {
int64_t CN4 = Tmp3->getSExtValue();
if (CN4 == INT64_C(8)) {
- SDValue N1 = N.getOperand(1);
- if (cast<VTSDNode>(N1)->getVT() == MVT::i16 &&
+ SDValue N1 = N->getOperand(1);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16 &&
N001.getValueType() == MVT::i32 &&
N011.getValueType() == MVT::i32) {
SDNode *Result = Emit_295(N, ARM::t2REVSH, MVT::i32);
@@ -34575,18 +34414,18 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::ROTR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::ROTR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_rot_imm(N01.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
// Pattern: (sext_inreg:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i8:Other)
// Emits: (SXTBr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
// Pattern complexity = 10 cost = 1 size = 0
- if (cast<VTSDNode>(N1)->getVT() == MVT::i8 &&
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8 &&
N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_293(N, ARM::SXTBr_rot, MVT::i32);
return Result;
@@ -34595,7 +34434,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
// Pattern: (sext_inreg:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i16:Other)
// Emits: (SXTHr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
// Pattern complexity = 10 cost = 1 size = 0
- if (cast<VTSDNode>(N1)->getVT() == MVT::i16 &&
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16 &&
N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_293(N, ARM::SXTHr_rot, MVT::i32);
return Result;
@@ -34604,18 +34443,18 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::ROTR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::ROTR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_rot_imm(N01.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
// Pattern: (sext_inreg:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i8:Other)
// Emits: (t2SXTBr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
// Pattern complexity = 10 cost = 1 size = 0
- if (cast<VTSDNode>(N1)->getVT() == MVT::i8 &&
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8 &&
N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_293(N, ARM::t2SXTBr_rot, MVT::i32);
return Result;
@@ -34624,7 +34463,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
// Pattern: (sext_inreg:i32 (rotr:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_rot_imm>>:$rot), i16:Other)
// Emits: (t2SXTHr_rot:i32 GPR:i32:$src, (imm:i32):$rot)
// Pattern complexity = 10 cost = 1 size = 0
- if (cast<VTSDNode>(N1)->getVT() == MVT::i16 &&
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16 &&
N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_293(N, ARM::t2SXTHr_rot, MVT::i32);
return Result;
@@ -34633,13 +34472,13 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (sext_inreg:i32 GPR:i32:$src, i8:Other)
// Emits: (SXTBr:i32 GPR:i32:$src)
// Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
SDNode *Result = Emit_292(N, ARM::SXTBr, MVT::i32);
return Result;
}
@@ -34647,19 +34486,19 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
// Pattern: (sext_inreg:i32 GPR:i32:$src, i16:Other)
// Emits: (SXTHr:i32 GPR:i32:$src)
// Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
SDNode *Result = Emit_292(N, ARM::SXTHr, MVT::i32);
return Result;
}
}
if ((Subtarget->isThumb1Only()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (sext_inreg:i32 tGPR:i32:$src, i8:Other)
// Emits: (tSXTB:i32 tGPR:i32:$src)
// Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
SDNode *Result = Emit_292(N, ARM::tSXTB, MVT::i32);
return Result;
}
@@ -34667,19 +34506,19 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
// Pattern: (sext_inreg:i32 tGPR:i32:$src, i16:Other)
// Emits: (tSXTH:i32 tGPR:i32:$src)
// Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
SDNode *Result = Emit_292(N, ARM::tSXTH, MVT::i32);
return Result;
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (sext_inreg:i32 GPR:i32:$src, i8:Other)
// Emits: (t2SXTBr:i32 GPR:i32:$src)
// Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
SDNode *Result = Emit_292(N, ARM::t2SXTBr, MVT::i32);
return Result;
}
@@ -34687,7 +34526,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
// Pattern: (sext_inreg:i32 GPR:i32:$src, i16:Other)
// Emits: (t2SXTHr:i32 GPR:i32:$src)
// Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
SDNode *Result = Emit_292(N, ARM::t2SXTHr, MVT::i32);
return Result;
}
@@ -34697,9 +34536,9 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SINT_TO_FP_v2f32(const SDValue &N) {
+SDNode *Select_ISD_SINT_TO_FP_v2f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_31(N, ARM::VCVTs2fd, MVT::v2f32);
return Result;
@@ -34710,9 +34549,9 @@ SDNode *Select_ISD_SINT_TO_FP_v2f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SINT_TO_FP_v4f32(const SDValue &N) {
+SDNode *Select_ISD_SINT_TO_FP_v4f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_31(N, ARM::VCVTs2fq, MVT::v4f32);
return Result;
@@ -34723,129 +34562,129 @@ SDNode *Select_ISD_SINT_TO_FP_v4f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_296(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_296(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N010, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_297(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_297(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N010, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_298(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_298(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N0100, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_299(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_299(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N00, N01, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_300(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_300(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N01, N000, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_301(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_301(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp6 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp7 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N01, N000, Tmp6, Tmp7 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_302(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_302(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp8 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp9 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N01, N0000, Tmp8, Tmp9 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_303(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_303(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N01, N00, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-SDNode *Select_ISD_SRA_i32(const SDValue &N) {
+SDNode *Select_ISD_SRA_i32(SDNode *N) {
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32)), 16:i32)
// Emits: (SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 27 cost = 1 size = 0
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::SHL) {
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0101);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0101.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(16) &&
@@ -34867,23 +34706,23 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
// Pattern: (sra:i32 (mul:i32 (sra:i32 (shl:i32 GPR:i32:$b, 16:i32), 16:i32), GPR:i32:$a), 16:i32)
// Emits: (SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 27 cost = 1 size = 0
- if (N00.getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::SHL) {
- SDValue N0000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001);
+ if (N00.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N0000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N001);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(16) &&
@@ -34904,16 +34743,16 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
// Pattern: (sra:i32 (mul:i32 GPR:i32:$a, (sra:i32 GPR:i32:$b, 16:i32)), 16:i32)
// Emits: (SMULWT:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 19 cost = 1 size = 0
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16) &&
@@ -34933,19 +34772,19 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
// Emits: (t2SMULWT:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 19 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SRA) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N011.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16) &&
@@ -34965,19 +34804,19 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
// Emits: (SMULWT:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 19 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16) &&
@@ -34997,19 +34836,19 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
// Emits: (t2SMULWT:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 19 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::SRA) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SRA) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N001.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(16) &&
@@ -35029,16 +34868,16 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
// Emits: (SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 14 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- if (cast<VTSDNode>(N011)->getVT() == MVT::i16) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N011.getNode())->getVT() == MVT::i16) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -35056,16 +34895,16 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
// Emits: (t2SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 14 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- if (cast<VTSDNode>(N011)->getVT() == MVT::i16) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N011.getNode())->getVT() == MVT::i16) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -35083,16 +34922,16 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
// Emits: (SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 14 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N001.getNode())->getVT() == MVT::i16) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -35110,16 +34949,16 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
// Emits: (t2SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 14 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ if (cast<VTSDNode>(N001.getNode())->getVT() == MVT::i16) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -35140,24 +34979,24 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
SDValue CPTmpN_0;
SDValue CPTmpN_1;
SDValue CPTmpN_2;
- if (SelectShifterOperandReg(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2)) {
+ if (SelectShifterOperandReg(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2)) {
SDNode *Result = Emit_287(N, ARM::MOVs, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2);
return Result;
}
}
if ((!Subtarget->isThumb()) && (Subtarget->hasV5TEOps())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::MUL) {
- SDValue N00 = N0.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (sra:i32 (mul:i32 GPR:i32:$a, GPR:i32<<P:Predicate_sext_16_node>>:$b), 16:i32)
// Emits: (SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
if (Predicate_sext_16_node(N01.getNode())) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -35173,9 +35012,9 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
// Emits: (SMULWB:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 12 cost = 1 size = 0
if (Predicate_sext_16_node(N00.getNode())) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16) &&
@@ -35192,9 +35031,9 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
// Emits: (t2ASRri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 7 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_imm1_31(N1.getNode()) &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_55(N, ARM::t2ASRri, MVT::i32);
@@ -35202,13 +35041,13 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (sra:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
// Emits: (tASRri:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_65(N, ARM::tASRri, MVT::i32);
return Result;
@@ -35227,8 +35066,8 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
// Emits: (t2ASRrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_56(N, ARM::t2ASRrr, MVT::i32);
return Result;
@@ -35239,7 +35078,7 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SRL_i32(const SDValue &N) {
+SDNode *Select_ISD_SRL_i32(SDNode *N) {
// Pattern: so_reg:i32:$src
// Emits: (MOVs:i32 so_reg:i32:$src)
@@ -35248,7 +35087,7 @@ SDNode *Select_ISD_SRL_i32(const SDValue &N) {
SDValue CPTmpN_0;
SDValue CPTmpN_1;
SDValue CPTmpN_2;
- if (SelectShifterOperandReg(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2)) {
+ if (SelectShifterOperandReg(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2)) {
SDNode *Result = Emit_287(N, ARM::MOVs, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2);
return Result;
}
@@ -35258,9 +35097,9 @@ SDNode *Select_ISD_SRL_i32(const SDValue &N) {
// Emits: (t2LSRri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 7 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_imm1_31(N1.getNode()) &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_55(N, ARM::t2LSRri, MVT::i32);
@@ -35268,13 +35107,13 @@ SDNode *Select_ISD_SRL_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (srl:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
// Emits: (tLSRri:i32 tGPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_65(N, ARM::tLSRri, MVT::i32);
return Result;
@@ -35293,8 +35132,8 @@ SDNode *Select_ISD_SRL_i32(const SDValue &N) {
// Emits: (t2LSRrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_56(N, ARM::t2LSRrr, MVT::i32);
return Result;
@@ -35305,46 +35144,46 @@ SDNode *Select_ISD_SRL_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_304(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN3_0, SDValue &CPTmpN3_1) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_304(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN3_0, SDValue &CPTmpN3_1) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { N1, N2, CPTmpN3_0, CPTmpN3_1, Tmp3, Tmp4, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_305(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN3_0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_305(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN3_0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue Tmp3 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { N1, N2, CPTmpN3_0, Tmp3, Tmp4, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-SDNode *Select_ISD_STORE_i32(const SDValue &N) {
+SDNode *Select_ISD_STORE_i32(SDNode *N) {
if ((!Subtarget->isThumb())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_istore(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_istore(N)) {
// Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)<<P:Predicate_istore>><<P:Predicate_pre_store>>
// Emits: (STR_PRE:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_pre_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_pre_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
SDValue CPTmpN3_1;
if (SelectAddrMode2Offset(N, N3, CPTmpN3_0, CPTmpN3_1) &&
@@ -35358,10 +35197,10 @@ SDNode *Select_ISD_STORE_i32(const SDValue &N) {
// Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)<<P:Predicate_istore>><<P:Predicate_post_store>>
// Emits: (STR_POST:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_post_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_post_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
SDValue CPTmpN3_1;
if (SelectAddrMode2Offset(N, N3, CPTmpN3_0, CPTmpN3_1) &&
@@ -35372,16 +35211,16 @@ SDNode *Select_ISD_STORE_i32(const SDValue &N) {
}
}
}
- if (Predicate_itruncstore(N.getNode())) {
+ if (Predicate_itruncstore(N)) {
// Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, am3offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti16>>
// Emits: (STRH_PRE:i32 GPR:i32:$src, GPR:i32:$base, am3offset:i32:$offset)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_pre_truncst(N.getNode()) &&
- Predicate_pre_truncsti16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_pre_truncst(N) &&
+ Predicate_pre_truncsti16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
SDValue CPTmpN3_1;
if (SelectAddrMode3Offset(N, N3, CPTmpN3_0, CPTmpN3_1) &&
@@ -35395,11 +35234,11 @@ SDNode *Select_ISD_STORE_i32(const SDValue &N) {
// Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, am3offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_post_truncst>><<P:Predicate_post_truncsti16>>
// Emits: (STRH_POST:i32 GPR:i32:$src, GPR:i32:$base, am3offset:i32:$offset)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_post_truncst(N.getNode()) &&
- Predicate_post_truncsti16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_post_truncst(N) &&
+ Predicate_post_truncsti16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
SDValue CPTmpN3_1;
if (SelectAddrMode3Offset(N, N3, CPTmpN3_0, CPTmpN3_1) &&
@@ -35413,11 +35252,11 @@ SDNode *Select_ISD_STORE_i32(const SDValue &N) {
// Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti8>>
// Emits: (STRB_PRE:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_pre_truncst(N.getNode()) &&
- Predicate_pre_truncsti8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_pre_truncst(N) &&
+ Predicate_pre_truncsti8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
SDValue CPTmpN3_1;
if (SelectAddrMode2Offset(N, N3, CPTmpN3_0, CPTmpN3_1) &&
@@ -35431,11 +35270,11 @@ SDNode *Select_ISD_STORE_i32(const SDValue &N) {
// Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_post_truncst>><<P:Predicate_post_truncsti8>>
// Emits: (STRB_POST:i32 GPR:i32:$src, GPR:i32:$base, am2offset:i32:$offset)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_post_truncst(N.getNode()) &&
- Predicate_post_truncsti8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_post_truncst(N) &&
+ Predicate_post_truncsti8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
SDValue CPTmpN3_1;
if (SelectAddrMode2Offset(N, N3, CPTmpN3_0, CPTmpN3_1) &&
@@ -35448,16 +35287,16 @@ SDNode *Select_ISD_STORE_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_istore(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_istore(N)) {
// Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)<<P:Predicate_istore>><<P:Predicate_pre_store>>
// Emits: (t2STR_PRE:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)
// Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_pre_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_pre_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
if (SelectT2AddrModeImm8Offset(N, N3, CPTmpN3_0) &&
N1.getValueType() == MVT::i32 &&
@@ -35470,10 +35309,10 @@ SDNode *Select_ISD_STORE_i32(const SDValue &N) {
// Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)<<P:Predicate_istore>><<P:Predicate_post_store>>
// Emits: (t2STR_POST:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)
// Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_post_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_post_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
if (SelectT2AddrModeImm8Offset(N, N3, CPTmpN3_0) &&
N1.getValueType() == MVT::i32 &&
@@ -35483,16 +35322,16 @@ SDNode *Select_ISD_STORE_i32(const SDValue &N) {
}
}
}
- if (Predicate_itruncstore(N.getNode())) {
+ if (Predicate_itruncstore(N)) {
// Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti16>>
// Emits: (t2STRH_PRE:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)
// Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_pre_truncst(N.getNode()) &&
- Predicate_pre_truncsti16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_pre_truncst(N) &&
+ Predicate_pre_truncsti16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
if (SelectT2AddrModeImm8Offset(N, N3, CPTmpN3_0) &&
N1.getValueType() == MVT::i32 &&
@@ -35505,11 +35344,11 @@ SDNode *Select_ISD_STORE_i32(const SDValue &N) {
// Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_post_truncst>><<P:Predicate_post_truncsti16>>
// Emits: (t2STRH_POST:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)
// Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_post_truncst(N.getNode()) &&
- Predicate_post_truncsti16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_post_truncst(N) &&
+ Predicate_post_truncsti16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
if (SelectT2AddrModeImm8Offset(N, N3, CPTmpN3_0) &&
N1.getValueType() == MVT::i32 &&
@@ -35522,11 +35361,11 @@ SDNode *Select_ISD_STORE_i32(const SDValue &N) {
// Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti8>>
// Emits: (t2STRB_PRE:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)
// Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_pre_truncst(N.getNode()) &&
- Predicate_pre_truncsti8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_pre_truncst(N) &&
+ Predicate_pre_truncsti8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
if (SelectT2AddrModeImm8Offset(N, N3, CPTmpN3_0) &&
N1.getValueType() == MVT::i32 &&
@@ -35539,11 +35378,11 @@ SDNode *Select_ISD_STORE_i32(const SDValue &N) {
// Pattern: (ist:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)<<P:Predicate_itruncstore>><<P:Predicate_post_truncst>><<P:Predicate_post_truncsti8>>
// Emits: (t2STRB_POST:i32 GPR:i32:$src, GPR:i32:$base, t2am_imm8_offset:i32:$offset)
// Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_post_truncst(N.getNode()) &&
- Predicate_post_truncsti8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_post_truncst(N) &&
+ Predicate_post_truncsti8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
if (SelectT2AddrModeImm8Offset(N, N3, CPTmpN3_0) &&
N1.getValueType() == MVT::i32 &&
@@ -35559,43 +35398,43 @@ SDNode *Select_ISD_STORE_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_306(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_306(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, Tmp2, Tmp3, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 6);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_307(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_307(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, Tmp2, Tmp3, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-SDNode *Select_ISD_STORE(const SDValue &N) {
+SDNode *Select_ISD_STORE(SDNode *N) {
if ((!Subtarget->isThumb())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N)) {
// Pattern: (st:isVoid GPR:i32:$src, addrmodepc:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (PICSTR:isVoid GPR:i32:$src, addrmodepc:i32:$addr)
// Pattern complexity = 23 cost = 1 size = 0
- if (Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrModePC(N, N2, CPTmpN2_0, CPTmpN2_1) &&
@@ -35605,14 +35444,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
return Result;
}
}
- if (Predicate_truncstore(N.getNode())) {
+ if (Predicate_truncstore(N)) {
// Pattern: (st:isVoid GPR:i32:$src, addrmodepc:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
// Emits: (PICSTRH:isVoid GPR:i32:$src, addrmodepc:i32:$addr)
// Pattern complexity = 23 cost = 1 size = 0
- if (Predicate_truncstorei16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstorei16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrModePC(N, N2, CPTmpN2_0, CPTmpN2_1) &&
@@ -35626,9 +35465,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid GPR:i32:$src, addrmodepc:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
// Emits: (PICSTRB:isVoid GPR:i32:$src, addrmodepc:i32:$addr)
// Pattern complexity = 23 cost = 1 size = 0
- if (Predicate_truncstorei8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstorei8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrModePC(N, N2, CPTmpN2_0, CPTmpN2_1) &&
@@ -35643,9 +35482,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid GPR:i32:$src, addrmode2:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (STR:isVoid GPR:i32:$src, addrmode2:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -35656,14 +35495,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
return Result;
}
}
- if (Predicate_truncstore(N.getNode())) {
+ if (Predicate_truncstore(N)) {
// Pattern: (st:isVoid GPR:i32:$src, addrmode3:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
// Emits: (STRH:isVoid GPR:i32:$src, addrmode3:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_truncstorei16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstorei16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -35678,9 +35517,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid GPR:i32:$src, addrmode2:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
// Emits: (STRB:isVoid GPR:i32:$src, addrmode2:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_truncstorei8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstorei8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -35695,15 +35534,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N)) {
// Pattern: (st:isVoid tGPR:i32:$src, t_addrmode_s4:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (tSTR:isVoid tGPR:i32:$src, t_addrmode_s4:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -35714,14 +35553,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
return Result;
}
}
- if (Predicate_truncstore(N.getNode())) {
+ if (Predicate_truncstore(N)) {
// Pattern: (st:isVoid tGPR:i32:$src, t_addrmode_s1:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
// Emits: (tSTRB:isVoid tGPR:i32:$src, t_addrmode_s1:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_truncstorei8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstorei8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -35736,9 +35575,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid tGPR:i32:$src, t_addrmode_s2:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
// Emits: (tSTRH:isVoid tGPR:i32:$src, t_addrmode_s2:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_truncstorei16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstorei16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -35753,15 +35592,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N)) {
// Pattern: (st:isVoid GPR:i32:$src, t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (t2STRs:isVoid GPR:i32:$src, t2addrmode_so_reg:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -35772,14 +35611,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
return Result;
}
}
- if (Predicate_truncstore(N.getNode())) {
+ if (Predicate_truncstore(N)) {
// Pattern: (st:isVoid GPR:i32:$src, t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
// Emits: (t2STRBs:isVoid GPR:i32:$src, t2addrmode_so_reg:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_truncstorei8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstorei8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -35794,9 +35633,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid GPR:i32:$src, t2addrmode_so_reg:i32:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
// Emits: (t2STRHs:isVoid GPR:i32:$src, t2addrmode_so_reg:i32:$addr)
// Pattern complexity = 16 cost = 1 size = 0
- if (Predicate_truncstorei16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstorei16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -35815,11 +35654,11 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (tSTRspi:isVoid tGPR:i32:$src, t_addrmode_sp:i32:$addr)
// Pattern complexity = 13 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectThumbAddrModeSP(N, N2, CPTmpN2_0, CPTmpN2_1) &&
@@ -35831,11 +35670,11 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode())) {
- if (Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N)) {
+ if (Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -35859,10 +35698,10 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
return Result;
}
}
- if (Predicate_truncstore(N.getNode())) {
- if (Predicate_truncstorei8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstore(N)) {
+ if (Predicate_truncstorei8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -35886,9 +35725,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
return Result;
}
}
- if (Predicate_truncstorei16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstorei16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -35916,11 +35755,11 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
if ((Subtarget->hasVFP2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrMode5(N, N2, CPTmpN2_0, CPTmpN2_1)) {
@@ -35950,11 +35789,11 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (VSTRQ:isVoid QPR:v2f64:$src, addrmode4:i32:$addr)
// Pattern complexity = 13 cost = 1 size = 0
if ((Subtarget->hasNEON())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrMode4(N, N2, CPTmpN2_0, CPTmpN2_1) &&
@@ -35970,51 +35809,51 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_308(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_308(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, Tmp1, Tmp2, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_309(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_309(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
SDValue Tmp4 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp5 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { Tmp2, N1, Tmp4, Tmp5 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_310(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_310(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_311(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_311(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 5);
}
-SDNode *Select_ISD_SUB_i32(const SDValue &N) {
+SDNode *Select_ISD_SUB_i32(SDNode *N) {
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (sub:i32 GPR:i32:$a, so_reg:i32:$b)
// Emits: (SUBrs:i32 GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 15 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -36036,13 +35875,13 @@ SDNode *Select_ISD_SUB_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (sub:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Emits: (t2SUBrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -36066,8 +35905,8 @@ SDNode *Select_ISD_SUB_i32(const SDValue &N) {
// Emits: (tRSB:i32 tGPR:i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -36077,14 +35916,14 @@ SDNode *Select_ISD_SUB_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (sub:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
// Emits: (SUBri:i32 GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 7 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N1.getNode())) {
SDNode *Result = Emit_55(N, ARM::SUBri, MVT::i32);
return Result;
@@ -36094,17 +35933,17 @@ SDNode *Select_ISD_SUB_i32(const SDValue &N) {
// Pattern: (sub:i32 (imm:i32)<<P:Predicate_so_imm>>:$b, GPR:i32:$a)
// Emits: (RSBri:i32 GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 7 cost = 1 size = 0
- if (N0.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N0.getNode())) {
SDNode *Result = Emit_308(N, ARM::RSBri, MVT::i32);
return Result;
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (sub:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
// Emits: (t2SUBri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
@@ -36127,7 +35966,7 @@ SDNode *Select_ISD_SUB_i32(const SDValue &N) {
// Pattern: (sub:i32 (imm:i32)<<P:Predicate_t2_so_imm>>:$lhs, GPR:i32:$rhs)
// Emits: (t2RSBri:i32 GPR:i32:$rhs, (imm:i32):$lhs)
// Pattern complexity = 7 cost = 1 size = 0
- if (N0.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::Constant &&
Predicate_t2_so_imm(N0.getNode())) {
SDNode *Result = Emit_310(N, ARM::t2RSBri, MVT::i32);
return Result;
@@ -36138,9 +35977,9 @@ SDNode *Select_ISD_SUB_i32(const SDValue &N) {
// Emits: (MLS:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
// Pattern complexity = 6 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_77(N, ARM::MLS, MVT::i32);
return Result;
}
@@ -36150,21 +35989,21 @@ SDNode *Select_ISD_SUB_i32(const SDValue &N) {
// Emits: (SMMLS:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
// Pattern complexity = 6 cost = 1 size = 0
if ((!Subtarget->isThumb()) && (Subtarget->hasV6Ops())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MULHS) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MULHS) {
SDNode *Result = Emit_77(N, ARM::SMMLS, MVT::i32);
return Result;
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (sub:i32 GPR:i32:$c, (mul:i32 GPR:i32:$a, GPR:i32:$b))
// Emits: (t2MLS:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::MUL) {
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_77(N, ARM::t2MLS, MVT::i32);
return Result;
}
@@ -36172,7 +36011,7 @@ SDNode *Select_ISD_SUB_i32(const SDValue &N) {
// Pattern: (sub:i32 GPR:i32:$c, (mulhs:i32 GPR:i32:$a, GPR:i32:$b))
// Emits: (t2SMMLS:i32 GPR:i32:$a, GPR:i32:$b, GPR:i32:$c)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::MULHS) {
+ if (N1.getNode()->getOpcode() == ISD::MULHS) {
SDNode *Result = Emit_77(N, ARM::t2SMMLS, MVT::i32);
return Result;
}
@@ -36206,21 +36045,21 @@ SDNode *Select_ISD_SUB_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_312(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_312(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, Tmp1, Tmp2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, Tmp1, Tmp2);
}
-SDNode *Select_ISD_SUB_v8i8(const SDValue &N) {
+SDNode *Select_ISD_SUB_v8i8(SDNode *N) {
// Pattern: (sub:v8i8 (build_vector:v8i8)<<P:Predicate_immAllZerosV>>, DPR:v8i8:$src)
// Emits: (VNEGs8d:v8i8 DPR:v8i8:$src)
// Pattern complexity = 7 cost = 1 size = 0
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllZerosV(N0.getNode())) {
SDNode *Result = Emit_312(N, ARM::VNEGs8d, MVT::v8i8);
return Result;
@@ -36231,8 +36070,8 @@ SDNode *Select_ISD_SUB_v8i8(const SDValue &N) {
// Emits: (VNEGs8d:v8i8 DPR:f64:$src)
// Pattern complexity = 7 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllZerosV_bc(N0.getNode())) {
SDNode *Result = Emit_312(N, ARM::VNEGs8d, MVT::v8i8);
return Result;
@@ -36244,9 +36083,9 @@ SDNode *Select_ISD_SUB_v8i8(const SDValue &N) {
// Emits: (VMLSv8i8:v8i8 DPR:v8i8:$src1, DPR:v8i8:$src2, DPR:v8i8:$src3)
// Pattern complexity = 6 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_125(N, ARM::VMLSv8i8, MVT::v8i8);
return Result;
}
@@ -36263,14 +36102,14 @@ SDNode *Select_ISD_SUB_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SUB_v16i8(const SDValue &N) {
+SDNode *Select_ISD_SUB_v16i8(SDNode *N) {
// Pattern: (sub:v16i8 (build_vector:v16i8)<<P:Predicate_immAllZerosV>>, QPR:v16i8:$src)
// Emits: (VNEGs8q:v16i8 QPR:v16i8:$src)
// Pattern complexity = 7 cost = 1 size = 0
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllZerosV(N0.getNode())) {
SDNode *Result = Emit_312(N, ARM::VNEGs8q, MVT::v16i8);
return Result;
@@ -36281,8 +36120,8 @@ SDNode *Select_ISD_SUB_v16i8(const SDValue &N) {
// Emits: (VNEGs8q:v16i8 QPR:v16i8:$src)
// Pattern complexity = 7 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllZerosV_bc(N0.getNode())) {
SDNode *Result = Emit_312(N, ARM::VNEGs8q, MVT::v16i8);
return Result;
@@ -36294,9 +36133,9 @@ SDNode *Select_ISD_SUB_v16i8(const SDValue &N) {
// Emits: (VMLSv16i8:v16i8 QPR:v16i8:$src1, QPR:v16i8:$src2, QPR:v16i8:$src3)
// Pattern complexity = 6 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_125(N, ARM::VMLSv16i8, MVT::v16i8);
return Result;
}
@@ -36313,23 +36152,23 @@ SDNode *Select_ISD_SUB_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SUB_v4i16(const SDValue &N) {
+SDNode *Select_ISD_SUB_v4i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (sub:v4i16 DPR:v4i16:$src1, (mul:v4i16 DPR:v4i16:$src2, (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane)))
// Emits: (VMLSslv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_129(N, ARM::VMLSslv4i16, MVT::v4i16);
return Result;
@@ -36340,11 +36179,11 @@ SDNode *Select_ISD_SUB_v4i16(const SDValue &N) {
// Pattern: (sub:v4i16 DPR:v4i16:$src1, (mul:v4i16 (NEONvduplane:v4i16 DPR_8:v4i16:$src3, (imm:i32):$lane), DPR:v4i16:$src2))
// Emits: (VMLSslv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
- if (N10.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
+ if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_130(N, ARM::VMLSslv4i16, MVT::v4i16);
return Result;
@@ -36357,7 +36196,7 @@ SDNode *Select_ISD_SUB_v4i16(const SDValue &N) {
// Pattern: (sub:v4i16 (build_vector:v4i16)<<P:Predicate_immAllZerosV>>, DPR:v4i16:$src)
// Emits: (VNEGs16d:v4i16 DPR:v4i16:$src)
// Pattern complexity = 7 cost = 1 size = 0
- if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllZerosV(N0.getNode())) {
SDNode *Result = Emit_312(N, ARM::VNEGs16d, MVT::v4i16);
return Result;
@@ -36368,8 +36207,8 @@ SDNode *Select_ISD_SUB_v4i16(const SDValue &N) {
// Emits: (VNEGs16d:v4i16 DPR:f64:$src)
// Pattern complexity = 7 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllZerosV_bc(N0.getNode())) {
SDNode *Result = Emit_312(N, ARM::VNEGs16d, MVT::v4i16);
return Result;
@@ -36381,9 +36220,9 @@ SDNode *Select_ISD_SUB_v4i16(const SDValue &N) {
// Emits: (VMLSv4i16:v4i16 DPR:v4i16:$src1, DPR:v4i16:$src2, DPR:v4i16:$src3)
// Pattern complexity = 6 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_125(N, ARM::VMLSv4i16, MVT::v4i16);
return Result;
}
@@ -36400,22 +36239,22 @@ SDNode *Select_ISD_SUB_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SUB_v8i16(const SDValue &N) {
+SDNode *Select_ISD_SUB_v8i16(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (sub:v8i16 QPR:v8i16:$src1, (mul:v8i16 QPR:v8i16:$src2, (NEONvduplane:v8i16 DPR_8:v4i16:$src3, (imm:i32):$lane)))
// Emits: (VMLSslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_129(N, ARM::VMLSslv8i16, MVT::v8i16);
return Result;
@@ -36426,11 +36265,11 @@ SDNode *Select_ISD_SUB_v8i16(const SDValue &N) {
// Pattern: (sub:v8i16 QPR:v8i16:$src1, (mul:v8i16 (NEONvduplane:v8i16 DPR_8:v4i16:$src3, (imm:i32):$lane), QPR:v8i16:$src2))
// Emits: (VMLSslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, DPR_8:v4i16:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
- if (N10.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
+ if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4i16) {
SDNode *Result = Emit_130(N, ARM::VMLSslv8i16, MVT::v8i16);
return Result;
@@ -36440,20 +36279,20 @@ SDNode *Select_ISD_SUB_v8i16(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (sub:v8i16 QPR:v8i16:$src1, (mul:v8i16 QPR:v8i16:$src2, (NEONvduplane:v8i16 QPR:v8i16:$src3, (imm:i32):$lane)))
// Emits: (VMLSslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src3, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
// Pattern complexity = 12 cost = 2 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_133(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
@@ -36464,11 +36303,11 @@ SDNode *Select_ISD_SUB_v8i16(const SDValue &N) {
// Pattern: (sub:v8i16 QPR:v8i16:$src1, (mul:v8i16 (NEONvduplane:v8i16 QPR:v8i16:$src3, (imm:i32):$lane), QPR:v8i16:$src2))
// Emits: (VMLSslv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src3, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
// Pattern complexity = 12 cost = 2 size = 0
- if (N10.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
+ if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_134(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
@@ -36482,8 +36321,8 @@ SDNode *Select_ISD_SUB_v8i16(const SDValue &N) {
// Emits: (VNEGs16q:v8i16 QPR:v8i16:$src)
// Pattern complexity = 7 cost = 1 size = 0
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllZerosV(N0.getNode())) {
SDNode *Result = Emit_312(N, ARM::VNEGs16q, MVT::v8i16);
return Result;
@@ -36494,8 +36333,8 @@ SDNode *Select_ISD_SUB_v8i16(const SDValue &N) {
// Emits: (VNEGs16q:v8i16 QPR:v16i8:$src)
// Pattern complexity = 7 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllZerosV_bc(N0.getNode())) {
SDNode *Result = Emit_312(N, ARM::VNEGs16q, MVT::v8i16);
return Result;
@@ -36507,9 +36346,9 @@ SDNode *Select_ISD_SUB_v8i16(const SDValue &N) {
// Emits: (VMLSv8i16:v8i16 QPR:v8i16:$src1, QPR:v8i16:$src2, QPR:v8i16:$src3)
// Pattern complexity = 6 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_125(N, ARM::VMLSv8i16, MVT::v8i16);
return Result;
}
@@ -36526,23 +36365,23 @@ SDNode *Select_ISD_SUB_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SUB_v2i32(const SDValue &N) {
+SDNode *Select_ISD_SUB_v2i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (sub:v2i32 DPR:v2i32:$src1, (mul:v2i32 DPR:v2i32:$src2, (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane)))
// Emits: (VMLSslv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_129(N, ARM::VMLSslv2i32, MVT::v2i32);
return Result;
@@ -36553,11 +36392,11 @@ SDNode *Select_ISD_SUB_v2i32(const SDValue &N) {
// Pattern: (sub:v2i32 DPR:v2i32:$src1, (mul:v2i32 (NEONvduplane:v2i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane), DPR:v2i32:$src2))
// Emits: (VMLSslv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
- if (N10.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
+ if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_130(N, ARM::VMLSslv2i32, MVT::v2i32);
return Result;
@@ -36570,7 +36409,7 @@ SDNode *Select_ISD_SUB_v2i32(const SDValue &N) {
// Pattern: (sub:v2i32 (build_vector:v2i32)<<P:Predicate_immAllZerosV>>, DPR:v2i32:$src)
// Emits: (VNEGs32d:v2i32 DPR:v2i32:$src)
// Pattern complexity = 7 cost = 1 size = 0
- if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllZerosV(N0.getNode())) {
SDNode *Result = Emit_312(N, ARM::VNEGs32d, MVT::v2i32);
return Result;
@@ -36581,8 +36420,8 @@ SDNode *Select_ISD_SUB_v2i32(const SDValue &N) {
// Emits: (VNEGs32d:v2i32 DPR:f64:$src)
// Pattern complexity = 7 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllZerosV_bc(N0.getNode())) {
SDNode *Result = Emit_312(N, ARM::VNEGs32d, MVT::v2i32);
return Result;
@@ -36594,9 +36433,9 @@ SDNode *Select_ISD_SUB_v2i32(const SDValue &N) {
// Emits: (VMLSv2i32:v2i32 DPR:v2i32:$src1, DPR:v2i32:$src2, DPR:v2i32:$src3)
// Pattern complexity = 6 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_125(N, ARM::VMLSv2i32, MVT::v2i32);
return Result;
}
@@ -36613,22 +36452,22 @@ SDNode *Select_ISD_SUB_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SUB_v4i32(const SDValue &N) {
+SDNode *Select_ISD_SUB_v4i32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (sub:v4i32 QPR:v4i32:$src1, (mul:v4i32 QPR:v4i32:$src2, (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane)))
// Emits: (VMLSslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_129(N, ARM::VMLSslv4i32, MVT::v4i32);
return Result;
@@ -36639,11 +36478,11 @@ SDNode *Select_ISD_SUB_v4i32(const SDValue &N) {
// Pattern: (sub:v4i32 QPR:v4i32:$src1, (mul:v4i32 (NEONvduplane:v4i32 DPR_VFP2:v2i32:$src3, (imm:i32):$lane), QPR:v4i32:$src2))
// Emits: (VMLSslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, DPR_VFP2:v2i32:$src3, (imm:i32):$lane)
// Pattern complexity = 12 cost = 1 size = 0
- if (N10.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
+ if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_130(N, ARM::VMLSslv4i32, MVT::v4i32);
return Result;
@@ -36653,20 +36492,20 @@ SDNode *Select_ISD_SUB_v4i32(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (sub:v4i32 QPR:v4i32:$src1, (mul:v4i32 QPR:v4i32:$src2, (NEONvduplane:v4i32 QPR:v4i32:$src3, (imm:i32):$lane)))
// Emits: (VMLSslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 12 cost = 2 size = 0
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_137(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
@@ -36677,11 +36516,11 @@ SDNode *Select_ISD_SUB_v4i32(const SDValue &N) {
// Pattern: (sub:v4i32 QPR:v4i32:$src1, (mul:v4i32 (NEONvduplane:v4i32 QPR:v4i32:$src3, (imm:i32):$lane), QPR:v4i32:$src2))
// Emits: (VMLSslv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, (EXTRACT_SUBREG:v2i32 QPR:v16i8:$src3, (DSubReg_i32_reg:i32 (imm:i32):$lane)), (SubReg_i32_lane:i32 (imm:i32):$lane))
// Pattern complexity = 12 cost = 2 size = 0
- if (N10.getOpcode() == ARMISD::VDUPLANE) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
+ if (N10.getNode()->getOpcode() == ARMISD::VDUPLANE) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_138(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
@@ -36695,8 +36534,8 @@ SDNode *Select_ISD_SUB_v4i32(const SDValue &N) {
// Emits: (VNEGs32q:v4i32 QPR:v4i32:$src)
// Pattern complexity = 7 cost = 1 size = 0
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllZerosV(N0.getNode())) {
SDNode *Result = Emit_312(N, ARM::VNEGs32q, MVT::v4i32);
return Result;
@@ -36707,8 +36546,8 @@ SDNode *Select_ISD_SUB_v4i32(const SDValue &N) {
// Emits: (VNEGs32q:v4i32 QPR:v16i8:$src)
// Pattern complexity = 7 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllZerosV_bc(N0.getNode())) {
SDNode *Result = Emit_312(N, ARM::VNEGs32q, MVT::v4i32);
return Result;
@@ -36720,9 +36559,9 @@ SDNode *Select_ISD_SUB_v4i32(const SDValue &N) {
// Emits: (VMLSv4i32:v4i32 QPR:v4i32:$src1, QPR:v4i32:$src2, QPR:v4i32:$src3)
// Pattern complexity = 6 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::MUL) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::MUL) {
SDNode *Result = Emit_125(N, ARM::VMLSv4i32, MVT::v4i32);
return Result;
}
@@ -36739,7 +36578,7 @@ SDNode *Select_ISD_SUB_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SUB_v1i64(const SDValue &N) {
+SDNode *Select_ISD_SUB_v1i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
SDNode *Result = Emit_44(N, ARM::VSUBv1i64, MVT::v1i64);
return Result;
@@ -36749,7 +36588,7 @@ SDNode *Select_ISD_SUB_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SUB_v2i64(const SDValue &N) {
+SDNode *Select_ISD_SUB_v2i64(SDNode *N) {
if ((Subtarget->hasNEON())) {
SDNode *Result = Emit_44(N, ARM::VSUBv2i64, MVT::v2i64);
return Result;
@@ -36759,47 +36598,47 @@ SDNode *Select_ISD_SUB_v2i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_313(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_313(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, Tmp1, Tmp2, Tmp3 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 4);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 4);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_314(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_314(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N1, Tmp1, Tmp2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N1, Tmp1, Tmp2);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_315(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_315(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N1, CPTmpN0_0, CPTmpN0_1, Tmp2 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 4);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 4);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-SDNode *Select_ISD_SUBC_i32(const SDValue &N) {
+SDNode *Select_ISD_SUBC_i32(SDNode *N) {
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (subc:i32 GPR:i32:$a, so_reg:i32:$b)
// Emits: (SUBSrs:i32 GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 15 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -36821,13 +36660,13 @@ SDNode *Select_ISD_SUBC_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (subc:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Emits: (t2SUBSrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -36847,14 +36686,14 @@ SDNode *Select_ISD_SUBC_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (subc:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
// Emits: (SUBSri:i32 GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 7 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N1.getNode())) {
SDNode *Result = Emit_141(N, ARM::SUBSri, MVT::i32);
return Result;
@@ -36864,21 +36703,21 @@ SDNode *Select_ISD_SUBC_i32(const SDValue &N) {
// Pattern: (subc:i32 (imm:i32)<<P:Predicate_so_imm>>:$b, GPR:i32:$a)
// Emits: (RSBSri:i32 GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 7 cost = 1 size = 0
- if (N0.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N0.getNode())) {
SDNode *Result = Emit_313(N, ARM::RSBSri, MVT::i32);
return Result;
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (subc:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
// Emits: (t2SUBSri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 7 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_t2_so_imm(N1.getNode())) {
SDNode *Result = Emit_141(N, ARM::t2SUBSri, MVT::i32);
return Result;
@@ -36888,7 +36727,7 @@ SDNode *Select_ISD_SUBC_i32(const SDValue &N) {
// Pattern: (subc:i32 (imm:i32)<<P:Predicate_t2_so_imm>>:$lhs, GPR:i32:$rhs)
// Emits: (t2RSBSri:i32 GPR:i32:$rhs, (imm:i32):$lhs)
// Pattern complexity = 7 cost = 1 size = 0
- if (N0.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::Constant &&
Predicate_t2_so_imm(N0.getNode())) {
SDNode *Result = Emit_314(N, ARM::t2RSBSri, MVT::i32);
return Result;
@@ -36923,38 +36762,38 @@ SDNode *Select_ISD_SUBC_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_316(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_316(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp4 = CurDAG->getRegister(0, MVT::i32);
- SDValue InFlag = N.getOperand(2);
+ SDValue InFlag = N->getOperand(2);
SDValue Ops0[] = { N1, Tmp1, Tmp2, Tmp3, Tmp4, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, Ops0, 6);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_317(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_317(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
- SDValue InFlag = N.getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N1, Tmp1, InFlag);
+ SDValue InFlag = N->getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N1, Tmp1, InFlag);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
+SDNode *Select_ISD_SUBE_i32(SDNode *N) {
// Pattern: (sube:i32 GPR:i32:$a, so_reg:i32:$b)
// Emits: (SBCrs:i32 GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 15 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (!N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ if ((!Subtarget->isThumb()) && (!N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -36967,9 +36806,9 @@ SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
// Pattern: (sube:i32 GPR:i32:$a, so_reg:i32:$b)
// Emits: (SBCSSrs:i32 GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 15 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ if ((!Subtarget->isThumb()) && (N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -36978,8 +36817,8 @@ SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
return Result;
}
}
- if ((!Subtarget->isThumb()) && (!N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
+ if ((!Subtarget->isThumb()) && (!N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
SDValue CPTmpN0_0;
SDValue CPTmpN0_1;
SDValue CPTmpN0_2;
@@ -37004,9 +36843,9 @@ SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
// Pattern: (sube:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Emits: (t2SBCrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 12 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (!N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ if ((Subtarget->isThumb2()) && (!N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -37018,9 +36857,9 @@ SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
// Pattern: (sube:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Emits: (t2SBCSrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 12 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ if ((Subtarget->isThumb2()) && (N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -37032,10 +36871,10 @@ SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
// Pattern: (sube:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
// Emits: (SBCri:i32 GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 7 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (!N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ if ((!Subtarget->isThumb()) && (!N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N1.getNode())) {
SDNode *Result = Emit_150(N, ARM::SBCri, MVT::i32);
return Result;
@@ -37045,18 +36884,18 @@ SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
// Pattern: (sube:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
// Emits: (SBCSSri:i32 GPR:i32:$a, (imm:i32):$b)
// Pattern complexity = 7 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ if ((!Subtarget->isThumb()) && (N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N1.getNode())) {
SDNode *Result = Emit_153(N, ARM::SBCSSri, MVT::i32);
return Result;
}
}
- if ((!Subtarget->isThumb()) && (!N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::Constant &&
+ if ((!Subtarget->isThumb()) && (!N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm(N0.getNode())) {
// Pattern: (sube:i32 (imm:i32)<<P:Predicate_so_imm>>:$b, GPR:i32:$a)
@@ -37078,10 +36917,10 @@ SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
// Pattern: (sube:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
// Emits: (t2SBCri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (!N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ if ((Subtarget->isThumb2()) && (!N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_t2_so_imm(N1.getNode())) {
SDNode *Result = Emit_150(N, ARM::t2SBCri, MVT::i32);
return Result;
@@ -37091,10 +36930,10 @@ SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
// Pattern: (sube:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
// Emits: (t2SBCSri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
// Pattern complexity = 7 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (N.getNode()->hasAnyUseOfValue(1))) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ if ((Subtarget->isThumb2()) && (N->hasAnyUseOfValue(1))) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_t2_so_imm(N1.getNode())) {
SDNode *Result = Emit_153(N, ARM::t2SBCSri, MVT::i32);
return Result;
@@ -37104,7 +36943,7 @@ SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
// Pattern: (sube:i32 GPR:i32:$a, GPR:i32:$b)
// Emits: (SBCrr:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (!N.getNode()->hasAnyUseOfValue(1))) {
+ if ((!Subtarget->isThumb()) && (!N->hasAnyUseOfValue(1))) {
SDNode *Result = Emit_151(N, ARM::SBCrr, MVT::i32);
return Result;
}
@@ -37112,7 +36951,7 @@ SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
// Pattern: (sube:i32 GPR:i32:$a, GPR:i32:$b)
// Emits: (SBCSSrr:i32 GPR:i32:$a, GPR:i32:$b)
// Pattern complexity = 3 cost = 1 size = 0
- if ((!Subtarget->isThumb()) && (N.getNode()->hasAnyUseOfValue(1))) {
+ if ((!Subtarget->isThumb()) && (N->hasAnyUseOfValue(1))) {
SDNode *Result = Emit_154(N, ARM::SBCSSrr, MVT::i32);
return Result;
}
@@ -37128,7 +36967,7 @@ SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
// Pattern: (sube:i32 GPR:i32:$lhs, GPR:i32:$rhs)
// Emits: (t2SBCrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
// Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (!N.getNode()->hasAnyUseOfValue(1))) {
+ if ((Subtarget->isThumb2()) && (!N->hasAnyUseOfValue(1))) {
SDNode *Result = Emit_151(N, ARM::t2SBCrr, MVT::i32);
return Result;
}
@@ -37136,7 +36975,7 @@ SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
// Pattern: (sube:i32 GPR:i32:$lhs, GPR:i32:$rhs)
// Emits: (t2SBCSrr:i32 GPR:i32:$lhs, GPR:i32:$rhs)
// Pattern complexity = 3 cost = 1 size = 0
- if ((Subtarget->isThumb2()) && (N.getNode()->hasAnyUseOfValue(1))) {
+ if ((Subtarget->isThumb2()) && (N->hasAnyUseOfValue(1))) {
SDNode *Result = Emit_154(N, ARM::t2SBCSrr, MVT::i32);
return Result;
}
@@ -37145,9 +36984,9 @@ SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_UINT_TO_FP_v2f32(const SDValue &N) {
+SDNode *Select_ISD_UINT_TO_FP_v2f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::v2i32) {
SDNode *Result = Emit_31(N, ARM::VCVTu2fd, MVT::v2f32);
return Result;
@@ -37158,9 +36997,9 @@ SDNode *Select_ISD_UINT_TO_FP_v2f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_UINT_TO_FP_v4f32(const SDValue &N) {
+SDNode *Select_ISD_UINT_TO_FP_v4f32(SDNode *N) {
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_31(N, ARM::VCVTu2fq, MVT::v4f32);
return Result;
@@ -37171,74 +37010,74 @@ SDNode *Select_ISD_UINT_TO_FP_v4f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_318(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_318(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_319(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_319(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1, SDValue &CPTmpN0_2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { CPTmpN0_0, CPTmpN0_1, CPTmpN0_2, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 6);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 6);
}
-DISABLE_INLINE SDNode *Emit_320(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_320(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp0 = CurDAG->getRegister(ARM::CPSR, MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { Tmp0, N0, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_321(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_321(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { Tmp0, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_322(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_322(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0_0, SDValue &CPTmpN0_1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { CPTmpN0_0, CPTmpN0_1, Tmp1, Tmp2 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_323(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_323(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp1 = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Tmp2 = CurDAG->getRegister(0, MVT::i32);
SDValue Tmp3 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops0[] = { Tmp0, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-SDNode *Select_ISD_XOR_i32(const SDValue &N) {
+SDNode *Select_ISD_XOR_i32(SDNode *N) {
// Pattern: (xor:i32 so_reg:i32:$src, (imm:i32)<<P:Predicate_immAllOnes>>)
// Emits: (MVNs:i32 so_reg:i32:$src)
// Pattern complexity = 19 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
SDValue CPTmpN0_0;
SDValue CPTmpN0_1;
SDValue CPTmpN0_2;
if (SelectShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N1.getNode())) {
SDNode *Result = Emit_319(N, ARM::MVNs, MVT::i32, CPTmpN0_0, CPTmpN0_1, CPTmpN0_2);
return Result;
@@ -37250,12 +37089,12 @@ SDNode *Select_ISD_XOR_i32(const SDValue &N) {
// Emits: (t2MVNs:i32 t2_so_reg:i32:$src)
// Pattern complexity = 17 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
SDValue CPTmpN0_0;
SDValue CPTmpN0_1;
if (SelectT2ShifterOperandReg(N, N0, CPTmpN0_0, CPTmpN0_1)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N1.getNode())) {
SDNode *Result = Emit_322(N, ARM::t2MVNs, MVT::i32, CPTmpN0_0, CPTmpN0_1);
return Result;
@@ -37263,13 +37102,13 @@ SDNode *Select_ISD_XOR_i32(const SDValue &N) {
}
}
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (xor:i32 GPR:i32:$a, so_reg:i32:$b)
// Emits: (EORrs:i32 GPR:i32:$a, so_reg:i32:$b)
// Pattern complexity = 15 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -37291,13 +37130,13 @@ SDNode *Select_ISD_XOR_i32(const SDValue &N) {
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (xor:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Emits: (t2EORrs:i32 GPR:i32:$lhs, t2_so_reg:i32:$rhs)
// Pattern complexity = 12 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectT2ShifterOperandReg(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -37309,10 +37148,10 @@ SDNode *Select_ISD_XOR_i32(const SDValue &N) {
// Pattern: (xor:i32 (imm:i32)<<P:Predicate_t2_so_imm>>:$src, (imm:i32)<<P:Predicate_immAllOnes>>)
// Emits: (t2MVNi:i32 (imm:i32):$src)
// Pattern complexity = 12 cost = 1 size = 0
- if (N0.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::Constant &&
Predicate_t2_so_imm(N0.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N1.getNode())) {
SDNode *Result = Emit_321(N, ARM::t2MVNi, MVT::i32);
return Result;
@@ -37334,10 +37173,10 @@ SDNode *Select_ISD_XOR_i32(const SDValue &N) {
// Pattern: (xor:i32 (imm:i32)<<P:Predicate_immAllOnes>>, (imm:i32)<<P:Predicate_t2_so_imm>>:$src)
// Emits: (t2MVNi:i32 (imm:i32):$src)
// Pattern complexity = 12 cost = 1 size = 0
- if (N0.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N0.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_t2_so_imm(N1.getNode())) {
SDNode *Result = Emit_323(N, ARM::t2MVNi, MVT::i32);
return Result;
@@ -37347,17 +37186,17 @@ SDNode *Select_ISD_XOR_i32(const SDValue &N) {
// Pattern: (xor:i32 GPR:i32:$src, (imm:i32)<<P:Predicate_immAllOnes>>)
// Emits: (t2MVNr:i32 GPR:i32:$src)
// Pattern complexity = 8 cost = 1 size = 0
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N1.getNode())) {
SDNode *Result = Emit_292(N, ARM::t2MVNr, MVT::i32);
return Result;
}
}
if ((!Subtarget->isThumb())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (xor:i32 GPR:i32:$a, (imm:i32)<<P:Predicate_so_imm>>:$b)
// Emits: (EORri:i32 GPR:i32:$a, (imm:i32):$b)
@@ -37381,18 +37220,18 @@ SDNode *Select_ISD_XOR_i32(const SDValue &N) {
// Emits: (tMVN:i32 tGPR:i32:$src)
// Pattern complexity = 7 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N1.getNode())) {
SDNode *Result = Emit_320(N, ARM::tMVN, MVT::i32);
return Result;
}
}
if ((Subtarget->isThumb2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (xor:i32 GPR:i32:$lhs, (imm:i32)<<P:Predicate_t2_so_imm>>:$rhs)
// Emits: (t2EORri:i32 GPR:i32:$lhs, (imm:i32):$rhs)
@@ -37417,9 +37256,9 @@ SDNode *Select_ISD_XOR_i32(const SDValue &N) {
// Emits: (EORri:i32 (EORri:i32 GPR:i32:$LHS, (so_imm2part_1:i32 (imm:i32):$RHS)), (so_imm2part_2:i32 (imm:i32):$RHS))
// Pattern complexity = 7 cost = 2 size = 0
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_so_imm2part(N1.getNode())) {
SDNode *Result = Emit_74(N, ARM::EORri, ARM::EORri, MVT::i32, MVT::i32);
return Result;
@@ -37453,15 +37292,15 @@ SDNode *Select_ISD_XOR_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_XOR_v2i32(const SDValue &N) {
+SDNode *Select_ISD_XOR_v2i32(SDNode *N) {
// Pattern: (xor:v2i32 DPR:v2i32:$src, (build_vector:v2i32)<<P:Predicate_immAllOnesV>>)
// Emits: (VMVNd:v2i32 DPR:v2i32:$src)
// Pattern complexity = 7 cost = 1 size = 0
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N1.getNode())) {
SDNode *Result = Emit_292(N, ARM::VMVNd, MVT::v2i32);
return Result;
@@ -37472,9 +37311,9 @@ SDNode *Select_ISD_XOR_v2i32(const SDValue &N) {
// Emits: (VMVNd:v2i32 DPR:f64:$src)
// Pattern complexity = 7 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N1.getNode())) {
SDNode *Result = Emit_292(N, ARM::VMVNd, MVT::v2i32);
return Result;
@@ -37485,8 +37324,8 @@ SDNode *Select_ISD_XOR_v2i32(const SDValue &N) {
// Emits: (VMVNd:v2i32 DPR:v2i32:$src)
// Pattern complexity = 7 cost = 1 size = 0
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N0.getNode())) {
SDNode *Result = Emit_312(N, ARM::VMVNd, MVT::v2i32);
return Result;
@@ -37497,8 +37336,8 @@ SDNode *Select_ISD_XOR_v2i32(const SDValue &N) {
// Emits: (VMVNd:v2i32 DPR:f64:$src)
// Pattern complexity = 7 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N0.getNode())) {
SDNode *Result = Emit_312(N, ARM::VMVNd, MVT::v2i32);
return Result;
@@ -37517,15 +37356,15 @@ SDNode *Select_ISD_XOR_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_XOR_v4i32(const SDValue &N) {
+SDNode *Select_ISD_XOR_v4i32(SDNode *N) {
// Pattern: (xor:v4i32 QPR:v4i32:$src, (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)
// Emits: (VMVNq:v4i32 QPR:v4i32:$src)
// Pattern complexity = 7 cost = 1 size = 0
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N1.getNode())) {
SDNode *Result = Emit_292(N, ARM::VMVNq, MVT::v4i32);
return Result;
@@ -37536,9 +37375,9 @@ SDNode *Select_ISD_XOR_v4i32(const SDValue &N) {
// Emits: (VMVNq:v4i32 QPR:v16i8:$src)
// Pattern complexity = 7 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N1.getNode())) {
SDNode *Result = Emit_292(N, ARM::VMVNq, MVT::v4i32);
return Result;
@@ -37549,8 +37388,8 @@ SDNode *Select_ISD_XOR_v4i32(const SDValue &N) {
// Emits: (VMVNq:v4i32 QPR:v4i32:$src)
// Pattern complexity = 7 cost = 1 size = 0
if ((Subtarget->hasNEON())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N0.getNode())) {
SDNode *Result = Emit_312(N, ARM::VMVNq, MVT::v4i32);
return Result;
@@ -37561,8 +37400,8 @@ SDNode *Select_ISD_XOR_v4i32(const SDValue &N) {
// Emits: (VMVNq:v4i32 QPR:v16i8:$src)
// Pattern complexity = 7 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N0.getNode())) {
SDNode *Result = Emit_312(N, ARM::VMVNq, MVT::v4i32);
return Result;
@@ -37582,11 +37421,11 @@ SDNode *Select_ISD_XOR_v4i32(const SDValue &N) {
}
// The main instruction selector code.
-SDNode *SelectCode(SDValue N) {
- MVT::SimpleValueType NVT = N.getNode()->getValueType(0).getSimpleVT().SimpleTy;
- switch (N.getOpcode()) {
+SDNode *SelectCode(SDNode *N) {
+ MVT::SimpleValueType NVT = N->getValueType(0).getSimpleVT().SimpleTy;
+ switch (N->getOpcode()) {
default:
- assert(!N.isMachineOpcode() && "Node already selected!");
+ assert(!N->isMachineOpcode() && "Node already selected!");
break;
case ISD::EntryToken: // These nodes remain the same.
case ISD::BasicBlock:
@@ -37608,7 +37447,7 @@ SDNode *SelectCode(SDValue N) {
}
case ISD::AssertSext:
case ISD::AssertZext: {
- ReplaceUses(N, N.getOperand(0));
+ ReplaceUses(SDValue(N, 0), N->getOperand(0));
return NULL;
}
case ISD::INLINEASM: return Select_INLINEASM(N);
@@ -37694,6 +37533,15 @@ SDNode *SelectCode(SDValue N) {
}
break;
}
+ case ARMISD::RBIT: {
+ switch (NVT) {
+ case MVT::i32:
+ return Select_ARMISD_RBIT_i32(N);
+ default:
+ break;
+ }
+ break;
+ }
case ARMISD::RET_FLAG: {
return Select_ARMISD_RET_FLAG(N);
break;
@@ -39105,9 +38953,9 @@ SDNode *SelectCode(SDValue N) {
}
} // end of big switch.
- if (N.getOpcode() != ISD::INTRINSIC_W_CHAIN &&
- N.getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
- N.getOpcode() != ISD::INTRINSIC_VOID) {
+ if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
+ N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
+ N->getOpcode() != ISD::INTRINSIC_VOID) {
CannotYetSelect(N);
} else {
CannotYetSelectIntrinsic(N);
diff --git a/libclamav/c++/ARMGenInstrInfo.inc b/libclamav/c++/ARMGenInstrInfo.inc
index d542084..017af5b 100644
--- a/libclamav/c++/ARMGenInstrInfo.inc
+++ b/libclamav/c++/ARMGenInstrInfo.inc
@@ -11,16 +11,15 @@ namespace llvm {
static const unsigned ImplicitList1[] = { ARM::CPSR, 0 };
static const TargetRegisterClass* Barriers1[] = { &ARM::CCRRegClass, NULL };
static const unsigned ImplicitList2[] = { ARM::SP, 0 };
-static const TargetRegisterClass* Barriers2[] = { &ARM::JustSPRegClass, NULL };
-static const TargetRegisterClass* Barriers3[] = { &ARM::CCRRegClass, &ARM::DPR_8RegClass, NULL };
+static const TargetRegisterClass* Barriers2[] = { &ARM::CCRRegClass, &ARM::DPR_8RegClass, NULL };
static const unsigned ImplicitList3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12, ARM::LR, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::CPSR, ARM::FPSCR, 0 };
static const unsigned ImplicitList4[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R9, ARM::R12, ARM::LR, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::CPSR, ARM::FPSCR, 0 };
static const unsigned ImplicitList5[] = { ARM::FPSCR, 0 };
-static const TargetRegisterClass* Barriers4[] = { &ARM::DPRRegClass, &ARM::DPR_8RegClass, &ARM::DPR_VFP2RegClass, &ARM::tGPRRegClass, NULL };
+static const TargetRegisterClass* Barriers3[] = { &ARM::DPRRegClass, &ARM::DPR_8RegClass, &ARM::DPR_VFP2RegClass, &ARM::tGPRRegClass, NULL };
static const unsigned ImplicitList6[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, 0 };
static const unsigned ImplicitList7[] = { ARM::R0, ARM::R12, ARM::LR, ARM::CPSR, 0 };
static const unsigned ImplicitList8[] = { ARM::LR, 0 };
-static const TargetRegisterClass* Barriers5[] = { &ARM::tGPRRegClass, NULL };
+static const TargetRegisterClass* Barriers4[] = { &ARM::tGPRRegClass, NULL };
static const unsigned ImplicitList9[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, 0 };
static const unsigned ImplicitList10[] = { ARM::R0, ARM::LR, 0 };
@@ -173,7 +172,7 @@ static const TargetOperandInfo OperandInfo147[] = { { ARM::tGPRRegClassID, 0, 0
static const TargetOperandInfo OperandInfo148[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo149[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo150[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
-static const TargetOperandInfo OperandInfo151[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::JustSPRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
+static const TargetOperandInfo OperandInfo151[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo152[] = { { ARM::tGPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo153[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::tGPRRegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo154[] = { { ARM::tGPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, };
@@ -194,1512 +193,1514 @@ static const TargetInstrDesc ARMInsts[] = {
{ 8, 1, 1, 128, "IMPLICIT_DEF", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo14 }, // Inst #8 = IMPLICIT_DEF
{ 9, 4, 1, 128, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo42 }, // Inst #9 = SUBREG_TO_REG
{ 10, 3, 1, 128, "COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo24 }, // Inst #10 = COPY_TO_REGCLASS
- { 11, 3, 1, 88, "ADCSSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #11 = ADCSSri
- { 12, 3, 1, 89, "ADCSSrr", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #12 = ADCSSrr
- { 13, 5, 1, 91, "ADCSSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #13 = ADCSSrs
- { 14, 6, 1, 88, "ADCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #14 = ADCri
- { 15, 6, 1, 89, "ADCrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #15 = ADCrr
- { 16, 8, 1, 91, "ADCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #16 = ADCrs
- { 17, 5, 1, 88, "ADDSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #17 = ADDSri
- { 18, 5, 1, 89, "ADDSrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #18 = ADDSrr
- { 19, 7, 1, 91, "ADDSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #19 = ADDSrs
- { 20, 6, 1, 88, "ADDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #20 = ADDri
- { 21, 6, 1, 89, "ADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #21 = ADDrr
- { 22, 8, 1, 91, "ADDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #22 = ADDrs
- { 23, 3, 0, 128, "ADJCALLSTACKDOWN", 0|(1<<TID::Predicable), 0|(1<<4), ImplicitList2, ImplicitList2, Barriers2, OperandInfo11 }, // Inst #23 = ADJCALLSTACKDOWN
- { 24, 4, 0, 128, "ADJCALLSTACKUP", 0|(1<<TID::Predicable), 0|(1<<4), ImplicitList2, ImplicitList2, Barriers2, OperandInfo12 }, // Inst #24 = ADJCALLSTACKUP
- { 25, 6, 1, 88, "ANDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #25 = ANDri
- { 26, 6, 1, 89, "ANDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #26 = ANDrr
- { 27, 8, 1, 91, "ANDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #27 = ANDrs
- { 28, 4, 1, 128, "ATOMIC_CMP_SWAP_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #28 = ATOMIC_CMP_SWAP_I16
- { 29, 4, 1, 128, "ATOMIC_CMP_SWAP_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #29 = ATOMIC_CMP_SWAP_I32
- { 30, 4, 1, 128, "ATOMIC_CMP_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #30 = ATOMIC_CMP_SWAP_I8
- { 31, 3, 1, 128, "ATOMIC_LOAD_ADD_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #31 = ATOMIC_LOAD_ADD_I16
- { 32, 3, 1, 128, "ATOMIC_LOAD_ADD_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #32 = ATOMIC_LOAD_ADD_I32
- { 33, 3, 1, 128, "ATOMIC_LOAD_ADD_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #33 = ATOMIC_LOAD_ADD_I8
- { 34, 3, 1, 128, "ATOMIC_LOAD_AND_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #34 = ATOMIC_LOAD_AND_I16
- { 35, 3, 1, 128, "ATOMIC_LOAD_AND_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #35 = ATOMIC_LOAD_AND_I32
- { 36, 3, 1, 128, "ATOMIC_LOAD_AND_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #36 = ATOMIC_LOAD_AND_I8
- { 37, 3, 1, 128, "ATOMIC_LOAD_NAND_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #37 = ATOMIC_LOAD_NAND_I16
- { 38, 3, 1, 128, "ATOMIC_LOAD_NAND_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #38 = ATOMIC_LOAD_NAND_I32
- { 39, 3, 1, 128, "ATOMIC_LOAD_NAND_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #39 = ATOMIC_LOAD_NAND_I8
- { 40, 3, 1, 128, "ATOMIC_LOAD_OR_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #40 = ATOMIC_LOAD_OR_I16
- { 41, 3, 1, 128, "ATOMIC_LOAD_OR_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #41 = ATOMIC_LOAD_OR_I32
- { 42, 3, 1, 128, "ATOMIC_LOAD_OR_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #42 = ATOMIC_LOAD_OR_I8
- { 43, 3, 1, 128, "ATOMIC_LOAD_SUB_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #43 = ATOMIC_LOAD_SUB_I16
- { 44, 3, 1, 128, "ATOMIC_LOAD_SUB_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #44 = ATOMIC_LOAD_SUB_I32
- { 45, 3, 1, 128, "ATOMIC_LOAD_SUB_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #45 = ATOMIC_LOAD_SUB_I8
- { 46, 3, 1, 128, "ATOMIC_LOAD_XOR_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #46 = ATOMIC_LOAD_XOR_I16
- { 47, 3, 1, 128, "ATOMIC_LOAD_XOR_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #47 = ATOMIC_LOAD_XOR_I32
- { 48, 3, 1, 128, "ATOMIC_LOAD_XOR_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #48 = ATOMIC_LOAD_XOR_I8
- { 49, 3, 1, 128, "ATOMIC_SWAP_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #49 = ATOMIC_SWAP_I16
- { 50, 3, 1, 128, "ATOMIC_SWAP_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #50 = ATOMIC_SWAP_I32
- { 51, 3, 1, 128, "ATOMIC_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #51 = ATOMIC_SWAP_I8
- { 52, 1, 0, 0, "B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #52 = B
- { 53, 5, 1, 126, "BFC", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #53 = BFC
- { 54, 6, 1, 88, "BICri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #54 = BICri
- { 55, 6, 1, 89, "BICrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #55 = BICrr
- { 56, 8, 1, 91, "BICrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #56 = BICrs
- { 57, 1, 0, 0, "BL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers3, OperandInfo14 }, // Inst #57 = BL
- { 58, 1, 0, 0, "BLX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(3<<9), NULL, ImplicitList3, Barriers3, OperandInfo16 }, // Inst #58 = BLX
- { 59, 1, 0, 0, "BLXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(3<<9), NULL, ImplicitList4, Barriers3, OperandInfo16 }, // Inst #59 = BLXr9
- { 60, 3, 0, 0, "BL_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers3, OperandInfo11 }, // Inst #60 = BL_pred
- { 61, 1, 0, 0, "BLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers3, OperandInfo14 }, // Inst #61 = BLr9
- { 62, 3, 0, 0, "BLr9_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers3, OperandInfo11 }, // Inst #62 = BLr9_pred
- { 63, 1, 0, 0, "BRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #63 = BRIND
- { 64, 4, 0, 0, "BR_JTadd", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo17 }, // Inst #64 = BR_JTadd
- { 65, 5, 0, 0, "BR_JTm", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo18 }, // Inst #65 = BR_JTm
- { 66, 3, 0, 0, "BR_JTr", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo19 }, // Inst #66 = BR_JTr
- { 67, 1, 0, 0, "BX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList3, Barriers3, OperandInfo16 }, // Inst #67 = BX
- { 68, 2, 0, 0, "BX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo20 }, // Inst #68 = BX_RET
- { 69, 1, 0, 0, "BXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList4, Barriers3, OperandInfo16 }, // Inst #69 = BXr9
- { 70, 3, 0, 0, "Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #70 = Bcc
- { 71, 4, 1, 125, "CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #71 = CLZ
- { 72, 4, 0, 97, "CMNri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #72 = CMNri
- { 73, 4, 0, 98, "CMNrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #73 = CMNrr
- { 74, 6, 0, 100, "CMNrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #74 = CMNrs
- { 75, 4, 0, 97, "CMNzri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #75 = CMNzri
- { 76, 4, 0, 98, "CMNzrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #76 = CMNzrr
- { 77, 6, 0, 100, "CMNzrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #77 = CMNzrs
- { 78, 4, 0, 97, "CMPri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #78 = CMPri
- { 79, 4, 0, 98, "CMPrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #79 = CMPrr
- { 80, 6, 0, 100, "CMPrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #80 = CMPrs
- { 81, 4, 0, 97, "CMPzri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #81 = CMPzri
- { 82, 4, 0, 98, "CMPzrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #82 = CMPzrr
- { 83, 6, 0, 100, "CMPzrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #83 = CMPzrs
- { 84, 3, 0, 128, "CONSTPOOL_ENTRY", 0|(1<<TID::NotDuplicable), 0|(1<<4), NULL, NULL, NULL, OperandInfo24 }, // Inst #84 = CONSTPOOL_ENTRY
- { 85, 6, 1, 88, "EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #85 = EORri
- { 86, 6, 1, 89, "EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #86 = EORrr
- { 87, 8, 1, 91, "EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #87 = EORrs
- { 88, 4, 1, 26, "FCONSTD", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(3<<4)|(22<<9)|(1<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #88 = FCONSTD
- { 89, 4, 1, 26, "FCONSTS", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(3<<4)|(22<<9)|(1<<17), NULL, NULL, NULL, OperandInfo26 }, // Inst #89 = FCONSTS
- { 90, 2, 0, 82, "FMSTAT", 0|(1<<TID::Predicable), 0|(3<<4)|(22<<9)|(1<<17), ImplicitList5, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #90 = FMSTAT
- { 91, 1, 0, 128, "Int_MemBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 }, // Inst #91 = Int_MemBarrierV6
- { 92, 0, 0, 128, "Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #92 = Int_MemBarrierV7
- { 93, 1, 0, 128, "Int_SyncBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 }, // Inst #93 = Int_SyncBarrierV6
- { 94, 0, 0, 128, "Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #94 = Int_SyncBarrierV7
- { 95, 1, 0, 128, "Int_eh_sjlj_setjmp", 0, 0|(1<<4), NULL, ImplicitList6, Barriers4, OperandInfo16 }, // Inst #95 = Int_eh_sjlj_setjmp
- { 96, 5, 0, 103, "LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #96 = LDM
- { 97, 5, 0, 0, "LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #97 = LDM_RET
- { 98, 6, 1, 104, "LDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #98 = LDR
- { 99, 6, 1, 104, "LDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #99 = LDRB
- { 100, 7, 2, 105, "LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #100 = LDRB_POST
- { 101, 7, 2, 105, "LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(1<<7)|(6<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #101 = LDRB_PRE
- { 102, 7, 2, 104, "LDRD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo10 }, // Inst #102 = LDRD
- { 103, 4, 1, 128, "LDREX", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #103 = LDREX
- { 104, 4, 1, 128, "LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #104 = LDREXB
- { 105, 5, 2, 128, "LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #105 = LDREXD
- { 106, 4, 1, 128, "LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #106 = LDREXH
- { 107, 6, 1, 104, "LDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #107 = LDRH
- { 108, 7, 2, 105, "LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #108 = LDRH_POST
- { 109, 7, 2, 105, "LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #109 = LDRH_PRE
- { 110, 6, 1, 104, "LDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #110 = LDRSB
- { 111, 7, 2, 105, "LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #111 = LDRSB_POST
- { 112, 7, 2, 105, "LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #112 = LDRSB_PRE
- { 113, 6, 1, 104, "LDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #113 = LDRSH
- { 114, 7, 2, 105, "LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #114 = LDRSH_POST
- { 115, 7, 2, 105, "LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #115 = LDRSH_PRE
- { 116, 7, 2, 105, "LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #116 = LDR_POST
- { 117, 7, 2, 105, "LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(1<<7)|(6<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #117 = LDR_PRE
- { 118, 6, 1, 104, "LDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #118 = LDRcp
- { 119, 4, 1, 88, "LEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo22 }, // Inst #119 = LEApcrel
- { 120, 5, 1, 88, "LEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo30 }, // Inst #120 = LEApcrelJT
- { 121, 7, 1, 109, "MLA", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #121 = MLA
- { 122, 6, 1, 109, "MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #122 = MLS
- { 123, 5, 1, 93, "MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo15 }, // Inst #123 = MOVCCi
- { 124, 5, 1, 94, "MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo33 }, // Inst #124 = MOVCCr
- { 125, 7, 1, 96, "MOVCCs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo34 }, // Inst #125 = MOVCCs
- { 126, 5, 1, 111, "MOVTi16", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo15 }, // Inst #126 = MOVTi16
- { 127, 5, 1, 111, "MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo35 }, // Inst #127 = MOVi
- { 128, 4, 1, 111, "MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #128 = MOVi16
- { 129, 4, 1, 111, "MOVi2pieces", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|1|(2<<4), NULL, NULL, NULL, OperandInfo22 }, // Inst #129 = MOVi2pieces
- { 130, 4, 1, 111, "MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|1|(2<<4), NULL, NULL, NULL, OperandInfo22 }, // Inst #130 = MOVi32imm
- { 131, 5, 1, 112, "MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo36 }, // Inst #131 = MOVr
- { 132, 5, 1, 113, "MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(1<<15), ImplicitList1, NULL, NULL, OperandInfo36 }, // Inst #132 = MOVrx
- { 133, 7, 1, 114, "MOVs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo37 }, // Inst #133 = MOVs
- { 134, 4, 1, 113, "MOVsra_flag", 0|(1<<TID::Predicable), 0|1|(3<<4)|(1<<15), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #134 = MOVsra_flag
- { 135, 4, 1, 113, "MOVsrl_flag", 0|(1<<TID::Predicable), 0|1|(3<<4)|(1<<15), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #135 = MOVsrl_flag
- { 136, 6, 1, 116, "MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #136 = MUL
- { 137, 5, 1, 111, "MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo35 }, // Inst #137 = MVNi
- { 138, 5, 1, 112, "MVNr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo36 }, // Inst #138 = MVNr
- { 139, 7, 1, 114, "MVNs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo37 }, // Inst #139 = MVNs
- { 140, 6, 1, 88, "ORRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #140 = ORRri
- { 141, 6, 1, 89, "ORRrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #141 = ORRrr
- { 142, 8, 1, 91, "ORRrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #142 = ORRrs
- { 143, 5, 1, 89, "PICADD", 0|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #143 = PICADD
- { 144, 5, 1, 104, "PICLDR", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #144 = PICLDR
- { 145, 5, 1, 104, "PICLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #145 = PICLDRB
- { 146, 5, 1, 104, "PICLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #146 = PICLDRH
- { 147, 5, 1, 104, "PICLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #147 = PICLDRSB
- { 148, 5, 1, 104, "PICLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #148 = PICLDRSH
- { 149, 5, 0, 121, "PICSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #149 = PICSTR
- { 150, 5, 0, 121, "PICSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #150 = PICSTRB
- { 151, 5, 0, 121, "PICSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #151 = PICSTRH
- { 152, 6, 1, 90, "PKHBT", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #152 = PKHBT
- { 153, 6, 1, 90, "PKHTB", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #153 = PKHTB
- { 154, 4, 1, 125, "REV", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #154 = REV
- { 155, 4, 1, 125, "REV16", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #155 = REV16
- { 156, 4, 1, 125, "REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #156 = REVSH
- { 157, 5, 1, 88, "RSBSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #157 = RSBSri
- { 158, 7, 1, 91, "RSBSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #158 = RSBSrs
- { 159, 6, 1, 88, "RSBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #159 = RSBri
- { 160, 8, 1, 91, "RSBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #160 = RSBrs
- { 161, 3, 1, 88, "RSCSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #161 = RSCSri
- { 162, 5, 1, 91, "RSCSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #162 = RSCSrs
- { 163, 6, 1, 88, "RSCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #163 = RSCri
- { 164, 8, 1, 91, "RSCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #164 = RSCrs
- { 165, 3, 1, 88, "SBCSSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #165 = SBCSSri
- { 166, 3, 1, 89, "SBCSSrr", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #166 = SBCSSrr
- { 167, 5, 1, 91, "SBCSSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #167 = SBCSSrs
- { 168, 6, 1, 88, "SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #168 = SBCri
- { 169, 6, 1, 89, "SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #169 = SBCrr
- { 170, 8, 1, 91, "SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #170 = SBCrs
- { 171, 6, 1, 88, "SBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #171 = SBFX
- { 172, 6, 1, 108, "SMLABB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #172 = SMLABB
- { 173, 6, 1, 108, "SMLABT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #173 = SMLABT
- { 174, 7, 2, 110, "SMLAL", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #174 = SMLAL
- { 175, 6, 1, 108, "SMLATB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #175 = SMLATB
- { 176, 6, 1, 108, "SMLATT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #176 = SMLATT
- { 177, 6, 1, 108, "SMLAWB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #177 = SMLAWB
- { 178, 6, 1, 108, "SMLAWT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #178 = SMLAWT
- { 179, 6, 1, 109, "SMMLA", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #179 = SMMLA
- { 180, 6, 1, 109, "SMMLS", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #180 = SMMLS
- { 181, 5, 1, 116, "SMMUL", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #181 = SMMUL
- { 182, 5, 1, 116, "SMULBB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #182 = SMULBB
- { 183, 5, 1, 116, "SMULBT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #183 = SMULBT
- { 184, 7, 2, 117, "SMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #184 = SMULL
- { 185, 5, 1, 116, "SMULTB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #185 = SMULTB
- { 186, 5, 1, 116, "SMULTT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #186 = SMULTT
- { 187, 5, 1, 115, "SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #187 = SMULWB
- { 188, 5, 1, 115, "SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #188 = SMULWT
- { 189, 5, 0, 120, "STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #189 = STM
- { 190, 6, 0, 121, "STR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(7<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #190 = STR
- { 191, 6, 0, 121, "STRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(7<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #191 = STRB
- { 192, 7, 1, 122, "STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #192 = STRB_POST
- { 193, 7, 1, 122, "STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #193 = STRB_PRE
- { 194, 7, 0, 121, "STRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo10 }, // Inst #194 = STRD
- { 195, 5, 1, 128, "STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #195 = STREX
- { 196, 5, 1, 128, "STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #196 = STREXB
- { 197, 6, 1, 128, "STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo41 }, // Inst #197 = STREXD
- { 198, 5, 1, 128, "STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #198 = STREXH
- { 199, 6, 0, 121, "STRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #199 = STRH
- { 200, 7, 1, 122, "STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(2<<7)|(9<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #200 = STRH_POST
- { 201, 7, 1, 122, "STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(1<<7)|(9<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #201 = STRH_PRE
- { 202, 7, 1, 122, "STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #202 = STR_POST
- { 203, 7, 1, 122, "STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #203 = STR_PRE
- { 204, 5, 1, 88, "SUBSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #204 = SUBSri
- { 205, 5, 1, 89, "SUBSrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #205 = SUBSrr
- { 206, 7, 1, 91, "SUBSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #206 = SUBSrs
- { 207, 6, 1, 88, "SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #207 = SUBri
- { 208, 6, 1, 89, "SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #208 = SUBrr
- { 209, 8, 1, 91, "SUBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #209 = SUBrs
- { 210, 5, 1, 89, "SXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #210 = SXTABrr
- { 211, 6, 1, 90, "SXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #211 = SXTABrr_rot
- { 212, 5, 1, 89, "SXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #212 = SXTAHrr
- { 213, 6, 1, 90, "SXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #213 = SXTAHrr_rot
- { 214, 4, 1, 125, "SXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #214 = SXTBr
- { 215, 5, 1, 126, "SXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #215 = SXTBr_rot
- { 216, 4, 1, 125, "SXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #216 = SXTHr
- { 217, 5, 1, 126, "SXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #217 = SXTHr_rot
- { 218, 4, 0, 97, "TEQri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #218 = TEQri
- { 219, 4, 0, 98, "TEQrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #219 = TEQrr
- { 220, 6, 0, 100, "TEQrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #220 = TEQrs
- { 221, 0, 0, 0, "TPsoft", 0|(1<<TID::Call), 0|(3<<4)|(2<<9), NULL, ImplicitList7, Barriers1, 0 }, // Inst #221 = TPsoft
- { 222, 4, 0, 97, "TSTri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #222 = TSTri
- { 223, 4, 0, 98, "TSTrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #223 = TSTrr
- { 224, 6, 0, 100, "TSTrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #224 = TSTrs
- { 225, 6, 1, 88, "UBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #225 = UBFX
- { 226, 6, 2, 110, "UMAAL", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #226 = UMAAL
- { 227, 7, 2, 110, "UMLAL", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #227 = UMLAL
- { 228, 7, 2, 117, "UMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #228 = UMULL
- { 229, 5, 1, 89, "UXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #229 = UXTABrr
- { 230, 6, 1, 90, "UXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #230 = UXTABrr_rot
- { 231, 5, 1, 89, "UXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #231 = UXTAHrr
- { 232, 6, 1, 90, "UXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #232 = UXTAHrr_rot
- { 233, 4, 1, 125, "UXTB16r", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #233 = UXTB16r
- { 234, 5, 1, 126, "UXTB16r_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #234 = UXTB16r_rot
- { 235, 4, 1, 125, "UXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #235 = UXTBr
- { 236, 5, 1, 126, "UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #236 = UXTBr_rot
- { 237, 4, 1, 125, "UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #237 = UXTHr
- { 238, 5, 1, 126, "UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #238 = UXTHr_rot
- { 239, 6, 1, 17, "VABALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #239 = VABALsv2i64
- { 240, 6, 1, 17, "VABALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #240 = VABALsv4i32
- { 241, 6, 1, 17, "VABALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #241 = VABALsv8i16
- { 242, 6, 1, 17, "VABALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #242 = VABALuv2i64
- { 243, 6, 1, 17, "VABALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #243 = VABALuv4i32
- { 244, 6, 1, 17, "VABALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #244 = VABALuv8i16
- { 245, 6, 1, 18, "VABAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #245 = VABAsv16i8
- { 246, 6, 1, 19, "VABAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #246 = VABAsv2i32
- { 247, 6, 1, 17, "VABAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #247 = VABAsv4i16
- { 248, 6, 1, 20, "VABAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #248 = VABAsv4i32
- { 249, 6, 1, 18, "VABAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #249 = VABAsv8i16
- { 250, 6, 1, 17, "VABAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #250 = VABAsv8i8
- { 251, 6, 1, 18, "VABAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #251 = VABAuv16i8
- { 252, 6, 1, 19, "VABAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #252 = VABAuv2i32
- { 253, 6, 1, 17, "VABAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #253 = VABAuv4i16
- { 254, 6, 1, 20, "VABAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #254 = VABAuv4i32
- { 255, 6, 1, 18, "VABAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #255 = VABAuv8i16
- { 256, 6, 1, 17, "VABAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #256 = VABAuv8i8
- { 257, 5, 1, 4, "VABDLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #257 = VABDLsv2i64
- { 258, 5, 1, 4, "VABDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #258 = VABDLsv4i32
- { 259, 5, 1, 4, "VABDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #259 = VABDLsv8i16
- { 260, 5, 1, 4, "VABDLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #260 = VABDLuv2i64
- { 261, 5, 1, 4, "VABDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #261 = VABDLuv4i32
- { 262, 5, 1, 4, "VABDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #262 = VABDLuv8i16
- { 263, 5, 1, 1, "VABDfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #263 = VABDfd
- { 264, 5, 1, 2, "VABDfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #264 = VABDfq
- { 265, 5, 1, 4, "VABDsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #265 = VABDsv16i8
- { 266, 5, 1, 3, "VABDsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #266 = VABDsv2i32
- { 267, 5, 1, 3, "VABDsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #267 = VABDsv4i16
- { 268, 5, 1, 4, "VABDsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #268 = VABDsv4i32
- { 269, 5, 1, 4, "VABDsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #269 = VABDsv8i16
- { 270, 5, 1, 3, "VABDsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #270 = VABDsv8i8
- { 271, 5, 1, 4, "VABDuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #271 = VABDuv16i8
- { 272, 5, 1, 3, "VABDuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #272 = VABDuv2i32
- { 273, 5, 1, 3, "VABDuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #273 = VABDuv4i16
- { 274, 5, 1, 4, "VABDuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #274 = VABDuv4i32
- { 275, 5, 1, 4, "VABDuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #275 = VABDuv8i16
- { 276, 5, 1, 3, "VABDuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #276 = VABDuv8i8
- { 277, 4, 1, 87, "VABSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #277 = VABSD
- { 278, 4, 1, 86, "VABSS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #278 = VABSS
- { 279, 4, 1, 57, "VABSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #279 = VABSfd
- { 280, 4, 1, 57, "VABSfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #280 = VABSfd_sfp
- { 281, 4, 1, 58, "VABSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #281 = VABSfq
- { 282, 4, 1, 60, "VABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #282 = VABSv16i8
- { 283, 4, 1, 59, "VABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #283 = VABSv2i32
- { 284, 4, 1, 59, "VABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #284 = VABSv4i16
- { 285, 4, 1, 60, "VABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #285 = VABSv4i32
- { 286, 4, 1, 60, "VABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #286 = VABSv8i16
- { 287, 4, 1, 59, "VABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #287 = VABSv8i8
- { 288, 5, 1, 1, "VACGEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #288 = VACGEd
- { 289, 5, 1, 2, "VACGEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #289 = VACGEq
- { 290, 5, 1, 1, "VACGTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #290 = VACGTd
- { 291, 5, 1, 2, "VACGTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #291 = VACGTq
- { 292, 5, 1, 62, "VADDD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #292 = VADDD
- { 293, 5, 1, 3, "VADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #293 = VADDHNv2i32
- { 294, 5, 1, 3, "VADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #294 = VADDHNv4i16
- { 295, 5, 1, 3, "VADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #295 = VADDHNv8i8
- { 296, 5, 1, 44, "VADDLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #296 = VADDLsv2i64
- { 297, 5, 1, 44, "VADDLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #297 = VADDLsv4i32
- { 298, 5, 1, 44, "VADDLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #298 = VADDLsv8i16
- { 299, 5, 1, 44, "VADDLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #299 = VADDLuv2i64
- { 300, 5, 1, 44, "VADDLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #300 = VADDLuv4i32
- { 301, 5, 1, 44, "VADDLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #301 = VADDLuv8i16
- { 302, 5, 1, 61, "VADDS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #302 = VADDS
- { 303, 5, 1, 47, "VADDWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #303 = VADDWsv2i64
- { 304, 5, 1, 47, "VADDWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #304 = VADDWsv4i32
- { 305, 5, 1, 47, "VADDWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #305 = VADDWsv8i16
- { 306, 5, 1, 47, "VADDWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #306 = VADDWuv2i64
- { 307, 5, 1, 47, "VADDWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #307 = VADDWuv4i32
- { 308, 5, 1, 47, "VADDWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #308 = VADDWuv8i16
- { 309, 5, 1, 1, "VADDfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #309 = VADDfd
- { 310, 5, 1, 1, "VADDfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #310 = VADDfd_sfp
- { 311, 5, 1, 2, "VADDfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #311 = VADDfq
- { 312, 5, 1, 6, "VADDv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #312 = VADDv16i8
- { 313, 5, 1, 5, "VADDv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #313 = VADDv1i64
- { 314, 5, 1, 5, "VADDv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #314 = VADDv2i32
- { 315, 5, 1, 6, "VADDv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #315 = VADDv2i64
- { 316, 5, 1, 5, "VADDv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #316 = VADDv4i16
- { 317, 5, 1, 6, "VADDv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #317 = VADDv4i32
- { 318, 5, 1, 6, "VADDv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #318 = VADDv8i16
- { 319, 5, 1, 5, "VADDv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #319 = VADDv8i8
- { 320, 5, 1, 5, "VANDd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #320 = VANDd
- { 321, 5, 1, 6, "VANDq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #321 = VANDq
- { 322, 5, 1, 5, "VBICd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #322 = VBICd
- { 323, 5, 1, 6, "VBICq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #323 = VBICq
- { 324, 6, 1, 7, "VBSLd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #324 = VBSLd
- { 325, 6, 1, 8, "VBSLq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #325 = VBSLq
- { 326, 5, 1, 1, "VCEQfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #326 = VCEQfd
- { 327, 5, 1, 2, "VCEQfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #327 = VCEQfq
- { 328, 5, 1, 4, "VCEQv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #328 = VCEQv16i8
- { 329, 5, 1, 3, "VCEQv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #329 = VCEQv2i32
- { 330, 5, 1, 3, "VCEQv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #330 = VCEQv4i16
- { 331, 5, 1, 4, "VCEQv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #331 = VCEQv4i32
- { 332, 5, 1, 4, "VCEQv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #332 = VCEQv8i16
- { 333, 5, 1, 3, "VCEQv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #333 = VCEQv8i8
- { 334, 5, 1, 1, "VCGEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #334 = VCGEfd
- { 335, 5, 1, 2, "VCGEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #335 = VCGEfq
- { 336, 5, 1, 4, "VCGEsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #336 = VCGEsv16i8
- { 337, 5, 1, 3, "VCGEsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #337 = VCGEsv2i32
- { 338, 5, 1, 3, "VCGEsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #338 = VCGEsv4i16
- { 339, 5, 1, 4, "VCGEsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #339 = VCGEsv4i32
- { 340, 5, 1, 4, "VCGEsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #340 = VCGEsv8i16
- { 341, 5, 1, 3, "VCGEsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #341 = VCGEsv8i8
- { 342, 5, 1, 4, "VCGEuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #342 = VCGEuv16i8
- { 343, 5, 1, 3, "VCGEuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #343 = VCGEuv2i32
- { 344, 5, 1, 3, "VCGEuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #344 = VCGEuv4i16
- { 345, 5, 1, 4, "VCGEuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #345 = VCGEuv4i32
- { 346, 5, 1, 4, "VCGEuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #346 = VCGEuv8i16
- { 347, 5, 1, 3, "VCGEuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #347 = VCGEuv8i8
- { 348, 5, 1, 1, "VCGTfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #348 = VCGTfd
- { 349, 5, 1, 2, "VCGTfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #349 = VCGTfq
- { 350, 5, 1, 4, "VCGTsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #350 = VCGTsv16i8
- { 351, 5, 1, 3, "VCGTsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #351 = VCGTsv2i32
- { 352, 5, 1, 3, "VCGTsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #352 = VCGTsv4i16
- { 353, 5, 1, 4, "VCGTsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #353 = VCGTsv4i32
- { 354, 5, 1, 4, "VCGTsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #354 = VCGTsv8i16
- { 355, 5, 1, 3, "VCGTsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #355 = VCGTsv8i8
- { 356, 5, 1, 4, "VCGTuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #356 = VCGTuv16i8
- { 357, 5, 1, 3, "VCGTuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #357 = VCGTuv2i32
- { 358, 5, 1, 3, "VCGTuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #358 = VCGTuv4i16
- { 359, 5, 1, 4, "VCGTuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #359 = VCGTuv4i32
- { 360, 5, 1, 4, "VCGTuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #360 = VCGTuv8i16
- { 361, 5, 1, 3, "VCGTuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #361 = VCGTuv8i8
- { 362, 4, 1, 8, "VCLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #362 = VCLSv16i8
- { 363, 4, 1, 7, "VCLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #363 = VCLSv2i32
- { 364, 4, 1, 7, "VCLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #364 = VCLSv4i16
- { 365, 4, 1, 8, "VCLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #365 = VCLSv4i32
- { 366, 4, 1, 8, "VCLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #366 = VCLSv8i16
- { 367, 4, 1, 7, "VCLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #367 = VCLSv8i8
- { 368, 4, 1, 8, "VCLZv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #368 = VCLZv16i8
- { 369, 4, 1, 7, "VCLZv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #369 = VCLZv2i32
- { 370, 4, 1, 7, "VCLZv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #370 = VCLZv4i16
- { 371, 4, 1, 8, "VCLZv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #371 = VCLZv4i32
- { 372, 4, 1, 8, "VCLZv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #372 = VCLZv8i16
- { 373, 4, 1, 7, "VCLZv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #373 = VCLZv8i8
- { 374, 4, 0, 64, "VCMPED", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo49 }, // Inst #374 = VCMPED
- { 375, 4, 0, 63, "VCMPES", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo50 }, // Inst #375 = VCMPES
- { 376, 3, 0, 64, "VCMPEZD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo57 }, // Inst #376 = VCMPEZD
- { 377, 3, 0, 63, "VCMPEZS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo58 }, // Inst #377 = VCMPEZS
- { 378, 4, 1, 7, "VCNTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #378 = VCNTd
- { 379, 4, 1, 8, "VCNTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #379 = VCNTq
- { 380, 4, 1, 66, "VCVTDS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #380 = VCVTDS
- { 381, 4, 1, 69, "VCVTSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #381 = VCVTSD
- { 382, 4, 1, 57, "VCVTf2sd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #382 = VCVTf2sd
- { 383, 4, 1, 57, "VCVTf2sd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #383 = VCVTf2sd_sfp
- { 384, 4, 1, 58, "VCVTf2sq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #384 = VCVTf2sq
- { 385, 4, 1, 57, "VCVTf2ud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #385 = VCVTf2ud
- { 386, 4, 1, 57, "VCVTf2ud_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #386 = VCVTf2ud_sfp
- { 387, 4, 1, 58, "VCVTf2uq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #387 = VCVTf2uq
- { 388, 5, 1, 57, "VCVTf2xsd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #388 = VCVTf2xsd
- { 389, 5, 1, 58, "VCVTf2xsq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #389 = VCVTf2xsq
- { 390, 5, 1, 57, "VCVTf2xud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #390 = VCVTf2xud
- { 391, 5, 1, 58, "VCVTf2xuq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #391 = VCVTf2xuq
- { 392, 4, 1, 57, "VCVTs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #392 = VCVTs2fd
- { 393, 4, 1, 57, "VCVTs2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #393 = VCVTs2fd_sfp
- { 394, 4, 1, 58, "VCVTs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #394 = VCVTs2fq
- { 395, 4, 1, 57, "VCVTu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #395 = VCVTu2fd
- { 396, 4, 1, 57, "VCVTu2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #396 = VCVTu2fd_sfp
- { 397, 4, 1, 58, "VCVTu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #397 = VCVTu2fq
- { 398, 5, 1, 57, "VCVTxs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #398 = VCVTxs2fd
- { 399, 5, 1, 58, "VCVTxs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #399 = VCVTxs2fq
- { 400, 5, 1, 57, "VCVTxu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #400 = VCVTxu2fd
- { 401, 5, 1, 58, "VCVTxu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #401 = VCVTxu2fq
- { 402, 5, 1, 72, "VDIVD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #402 = VDIVD
- { 403, 5, 1, 71, "VDIVS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #403 = VDIVS
- { 404, 4, 1, 24, "VDUP16d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo63 }, // Inst #404 = VDUP16d
- { 405, 4, 1, 24, "VDUP16q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo64 }, // Inst #405 = VDUP16q
- { 406, 4, 1, 24, "VDUP32d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo63 }, // Inst #406 = VDUP32d
- { 407, 4, 1, 24, "VDUP32q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo64 }, // Inst #407 = VDUP32q
- { 408, 4, 1, 24, "VDUP8d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo63 }, // Inst #408 = VDUP8d
- { 409, 4, 1, 24, "VDUP8q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo64 }, // Inst #409 = VDUP8q
- { 410, 5, 1, 21, "VDUPLN16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #410 = VDUPLN16d
- { 411, 5, 1, 21, "VDUPLN16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #411 = VDUPLN16q
- { 412, 5, 1, 21, "VDUPLN32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #412 = VDUPLN32d
- { 413, 5, 1, 21, "VDUPLN32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #413 = VDUPLN32q
- { 414, 5, 1, 21, "VDUPLN8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #414 = VDUPLN8d
- { 415, 5, 1, 21, "VDUPLN8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #415 = VDUPLN8q
- { 416, 5, 1, 21, "VDUPLNfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #416 = VDUPLNfd
- { 417, 5, 1, 21, "VDUPLNfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #417 = VDUPLNfq
- { 418, 4, 1, 24, "VDUPfd", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo63 }, // Inst #418 = VDUPfd
- { 419, 4, 1, 21, "VDUPfdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #419 = VDUPfdf
- { 420, 4, 1, 24, "VDUPfq", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo64 }, // Inst #420 = VDUPfq
- { 421, 4, 1, 21, "VDUPfqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #421 = VDUPfqf
- { 422, 5, 1, 5, "VEORd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #422 = VEORd
- { 423, 5, 1, 6, "VEORq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #423 = VEORq
- { 424, 6, 1, 9, "VEXTd16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #424 = VEXTd16
- { 425, 6, 1, 9, "VEXTd32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #425 = VEXTd32
- { 426, 6, 1, 9, "VEXTd8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #426 = VEXTd8
- { 427, 6, 1, 9, "VEXTdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #427 = VEXTdf
- { 428, 6, 1, 10, "VEXTq16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #428 = VEXTq16
- { 429, 6, 1, 10, "VEXTq32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #429 = VEXTq32
- { 430, 6, 1, 10, "VEXTq8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #430 = VEXTq8
- { 431, 6, 1, 10, "VEXTqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #431 = VEXTqf
- { 432, 5, 1, 28, "VGETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo69 }, // Inst #432 = VGETLNi32
- { 433, 5, 1, 28, "VGETLNs16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo69 }, // Inst #433 = VGETLNs16
- { 434, 5, 1, 28, "VGETLNs8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo69 }, // Inst #434 = VGETLNs8
- { 435, 5, 1, 28, "VGETLNu16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo69 }, // Inst #435 = VGETLNu16
- { 436, 5, 1, 28, "VGETLNu8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo69 }, // Inst #436 = VGETLNu8
- { 437, 5, 1, 4, "VHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #437 = VHADDsv16i8
- { 438, 5, 1, 3, "VHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #438 = VHADDsv2i32
- { 439, 5, 1, 3, "VHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #439 = VHADDsv4i16
- { 440, 5, 1, 4, "VHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #440 = VHADDsv4i32
- { 441, 5, 1, 4, "VHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #441 = VHADDsv8i16
- { 442, 5, 1, 3, "VHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #442 = VHADDsv8i8
- { 443, 5, 1, 4, "VHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #443 = VHADDuv16i8
- { 444, 5, 1, 3, "VHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #444 = VHADDuv2i32
- { 445, 5, 1, 3, "VHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #445 = VHADDuv4i16
- { 446, 5, 1, 4, "VHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #446 = VHADDuv4i32
- { 447, 5, 1, 4, "VHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #447 = VHADDuv8i16
- { 448, 5, 1, 3, "VHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #448 = VHADDuv8i8
- { 449, 5, 1, 4, "VHSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #449 = VHSUBsv16i8
- { 450, 5, 1, 3, "VHSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #450 = VHSUBsv2i32
- { 451, 5, 1, 3, "VHSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #451 = VHSUBsv4i16
- { 452, 5, 1, 4, "VHSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #452 = VHSUBsv4i32
- { 453, 5, 1, 4, "VHSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #453 = VHSUBsv8i16
- { 454, 5, 1, 3, "VHSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #454 = VHSUBsv8i8
- { 455, 5, 1, 4, "VHSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #455 = VHSUBuv16i8
- { 456, 5, 1, 3, "VHSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #456 = VHSUBuv2i32
- { 457, 5, 1, 3, "VHSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #457 = VHSUBuv4i16
- { 458, 5, 1, 4, "VHSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #458 = VHSUBuv4i32
- { 459, 5, 1, 4, "VHSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #459 = VHSUBuv8i16
- { 460, 5, 1, 3, "VHSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #460 = VHSUBuv8i8
- { 461, 7, 1, 11, "VLD1d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #461 = VLD1d16
- { 462, 7, 1, 11, "VLD1d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #462 = VLD1d32
- { 463, 7, 1, 11, "VLD1d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #463 = VLD1d64
- { 464, 7, 1, 11, "VLD1d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #464 = VLD1d8
- { 465, 7, 1, 11, "VLD1df", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #465 = VLD1df
- { 466, 7, 1, 11, "VLD1q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #466 = VLD1q16
- { 467, 7, 1, 11, "VLD1q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #467 = VLD1q32
- { 468, 7, 1, 11, "VLD1q64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #468 = VLD1q64
- { 469, 7, 1, 11, "VLD1q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #469 = VLD1q8
- { 470, 7, 1, 11, "VLD1qf", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #470 = VLD1qf
- { 471, 11, 2, 12, "VLD2LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #471 = VLD2LNd16
- { 472, 11, 2, 12, "VLD2LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #472 = VLD2LNd32
- { 473, 11, 2, 12, "VLD2LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #473 = VLD2LNd8
- { 474, 11, 2, 12, "VLD2LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #474 = VLD2LNq16a
- { 475, 11, 2, 12, "VLD2LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #475 = VLD2LNq16b
- { 476, 11, 2, 12, "VLD2LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #476 = VLD2LNq32a
- { 477, 11, 2, 12, "VLD2LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #477 = VLD2LNq32b
- { 478, 8, 2, 12, "VLD2d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #478 = VLD2d16
- { 479, 8, 2, 12, "VLD2d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #479 = VLD2d32
- { 480, 8, 2, 11, "VLD2d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #480 = VLD2d64
- { 481, 8, 2, 12, "VLD2d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #481 = VLD2d8
- { 482, 10, 4, 12, "VLD2q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #482 = VLD2q16
- { 483, 10, 4, 12, "VLD2q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #483 = VLD2q32
- { 484, 10, 4, 12, "VLD2q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #484 = VLD2q8
- { 485, 13, 3, 13, "VLD3LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #485 = VLD3LNd16
- { 486, 13, 3, 13, "VLD3LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #486 = VLD3LNd32
- { 487, 13, 3, 13, "VLD3LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #487 = VLD3LNd8
- { 488, 13, 3, 13, "VLD3LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #488 = VLD3LNq16a
- { 489, 13, 3, 13, "VLD3LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #489 = VLD3LNq16b
- { 490, 13, 3, 13, "VLD3LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #490 = VLD3LNq32a
- { 491, 13, 3, 13, "VLD3LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #491 = VLD3LNq32b
- { 492, 9, 3, 13, "VLD3d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #492 = VLD3d16
- { 493, 9, 3, 13, "VLD3d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #493 = VLD3d32
- { 494, 9, 3, 11, "VLD3d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #494 = VLD3d64
- { 495, 9, 3, 13, "VLD3d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #495 = VLD3d8
- { 496, 10, 4, 13, "VLD3q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #496 = VLD3q16a
- { 497, 10, 4, 13, "VLD3q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #497 = VLD3q16b
- { 498, 10, 4, 13, "VLD3q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #498 = VLD3q32a
- { 499, 10, 4, 13, "VLD3q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #499 = VLD3q32b
- { 500, 10, 4, 13, "VLD3q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #500 = VLD3q8a
- { 501, 10, 4, 13, "VLD3q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #501 = VLD3q8b
- { 502, 15, 4, 14, "VLD4LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #502 = VLD4LNd16
- { 503, 15, 4, 14, "VLD4LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #503 = VLD4LNd32
- { 504, 15, 4, 14, "VLD4LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #504 = VLD4LNd8
- { 505, 15, 4, 14, "VLD4LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #505 = VLD4LNq16a
- { 506, 15, 4, 14, "VLD4LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #506 = VLD4LNq16b
- { 507, 15, 4, 14, "VLD4LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #507 = VLD4LNq32a
- { 508, 15, 4, 14, "VLD4LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #508 = VLD4LNq32b
- { 509, 10, 4, 14, "VLD4d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #509 = VLD4d16
- { 510, 10, 4, 14, "VLD4d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #510 = VLD4d32
- { 511, 10, 4, 11, "VLD4d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #511 = VLD4d64
- { 512, 10, 4, 14, "VLD4d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #512 = VLD4d8
- { 513, 11, 5, 14, "VLD4q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #513 = VLD4q16a
- { 514, 11, 5, 14, "VLD4q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #514 = VLD4q16b
- { 515, 11, 5, 14, "VLD4q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #515 = VLD4q32a
- { 516, 11, 5, 14, "VLD4q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #516 = VLD4q32b
- { 517, 11, 5, 14, "VLD4q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #517 = VLD4q8a
- { 518, 11, 5, 14, "VLD4q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #518 = VLD4q8b
- { 519, 5, 0, 75, "VLDMD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #519 = VLDMD
- { 520, 5, 0, 75, "VLDMS", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #520 = VLDMS
- { 521, 5, 1, 74, "VLDRD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #521 = VLDRD
- { 522, 5, 1, 75, "VLDRQ", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #522 = VLDRQ
- { 523, 5, 1, 73, "VLDRS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #523 = VLDRS
- { 524, 5, 1, 1, "VMAXfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #524 = VMAXfd
- { 525, 5, 1, 2, "VMAXfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #525 = VMAXfq
- { 526, 5, 1, 4, "VMAXsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #526 = VMAXsv16i8
- { 527, 5, 1, 3, "VMAXsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #527 = VMAXsv2i32
- { 528, 5, 1, 3, "VMAXsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #528 = VMAXsv4i16
- { 529, 5, 1, 4, "VMAXsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #529 = VMAXsv4i32
- { 530, 5, 1, 4, "VMAXsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #530 = VMAXsv8i16
- { 531, 5, 1, 3, "VMAXsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #531 = VMAXsv8i8
- { 532, 5, 1, 4, "VMAXuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #532 = VMAXuv16i8
- { 533, 5, 1, 3, "VMAXuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #533 = VMAXuv2i32
- { 534, 5, 1, 3, "VMAXuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #534 = VMAXuv4i16
- { 535, 5, 1, 4, "VMAXuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #535 = VMAXuv4i32
- { 536, 5, 1, 4, "VMAXuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #536 = VMAXuv8i16
- { 537, 5, 1, 3, "VMAXuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #537 = VMAXuv8i8
- { 538, 5, 1, 1, "VMINfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #538 = VMINfd
- { 539, 5, 1, 2, "VMINfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #539 = VMINfq
- { 540, 5, 1, 4, "VMINsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #540 = VMINsv16i8
- { 541, 5, 1, 3, "VMINsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #541 = VMINsv2i32
- { 542, 5, 1, 3, "VMINsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #542 = VMINsv4i16
- { 543, 5, 1, 4, "VMINsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #543 = VMINsv4i32
- { 544, 5, 1, 4, "VMINsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #544 = VMINsv8i16
- { 545, 5, 1, 3, "VMINsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #545 = VMINsv8i8
- { 546, 5, 1, 4, "VMINuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #546 = VMINuv16i8
- { 547, 5, 1, 3, "VMINuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #547 = VMINuv2i32
- { 548, 5, 1, 3, "VMINuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #548 = VMINuv4i16
- { 549, 5, 1, 4, "VMINuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #549 = VMINuv4i32
- { 550, 5, 1, 4, "VMINuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #550 = VMINuv8i16
- { 551, 5, 1, 3, "VMINuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #551 = VMINuv8i8
- { 552, 6, 1, 77, "VMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #552 = VMLAD
- { 553, 7, 1, 19, "VMLALslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #553 = VMLALslsv2i32
- { 554, 7, 1, 17, "VMLALslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #554 = VMLALslsv4i16
- { 555, 7, 1, 19, "VMLALsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #555 = VMLALsluv2i32
- { 556, 7, 1, 17, "VMLALsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #556 = VMLALsluv4i16
- { 557, 6, 1, 17, "VMLALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #557 = VMLALsv2i64
- { 558, 6, 1, 17, "VMLALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #558 = VMLALsv4i32
- { 559, 6, 1, 17, "VMLALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #559 = VMLALsv8i16
- { 560, 6, 1, 17, "VMLALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #560 = VMLALuv2i64
- { 561, 6, 1, 17, "VMLALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #561 = VMLALuv4i32
- { 562, 6, 1, 17, "VMLALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #562 = VMLALuv8i16
- { 563, 6, 1, 76, "VMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #563 = VMLAS
- { 564, 6, 1, 15, "VMLAfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #564 = VMLAfd
- { 565, 6, 1, 16, "VMLAfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #565 = VMLAfq
- { 566, 7, 1, 15, "VMLAslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #566 = VMLAslfd
- { 567, 7, 1, 16, "VMLAslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #567 = VMLAslfq
- { 568, 7, 1, 19, "VMLAslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #568 = VMLAslv2i32
- { 569, 7, 1, 17, "VMLAslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #569 = VMLAslv4i16
- { 570, 7, 1, 20, "VMLAslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #570 = VMLAslv4i32
- { 571, 7, 1, 18, "VMLAslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #571 = VMLAslv8i16
- { 572, 6, 1, 18, "VMLAv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #572 = VMLAv16i8
- { 573, 6, 1, 19, "VMLAv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #573 = VMLAv2i32
- { 574, 6, 1, 17, "VMLAv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #574 = VMLAv4i16
- { 575, 6, 1, 20, "VMLAv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #575 = VMLAv4i32
- { 576, 6, 1, 18, "VMLAv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #576 = VMLAv8i16
- { 577, 6, 1, 17, "VMLAv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #577 = VMLAv8i8
- { 578, 6, 1, 77, "VMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #578 = VMLSD
- { 579, 7, 1, 19, "VMLSLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #579 = VMLSLslsv2i32
- { 580, 7, 1, 17, "VMLSLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #580 = VMLSLslsv4i16
- { 581, 7, 1, 19, "VMLSLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #581 = VMLSLsluv2i32
- { 582, 7, 1, 17, "VMLSLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #582 = VMLSLsluv4i16
- { 583, 6, 1, 17, "VMLSLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #583 = VMLSLsv2i64
- { 584, 6, 1, 17, "VMLSLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #584 = VMLSLsv4i32
- { 585, 6, 1, 17, "VMLSLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #585 = VMLSLsv8i16
- { 586, 6, 1, 17, "VMLSLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #586 = VMLSLuv2i64
- { 587, 6, 1, 17, "VMLSLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #587 = VMLSLuv4i32
- { 588, 6, 1, 17, "VMLSLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #588 = VMLSLuv8i16
- { 589, 6, 1, 76, "VMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #589 = VMLSS
- { 590, 6, 1, 15, "VMLSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #590 = VMLSfd
- { 591, 6, 1, 16, "VMLSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #591 = VMLSfq
- { 592, 7, 1, 15, "VMLSslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #592 = VMLSslfd
- { 593, 7, 1, 16, "VMLSslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #593 = VMLSslfq
- { 594, 7, 1, 19, "VMLSslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #594 = VMLSslv2i32
- { 595, 7, 1, 17, "VMLSslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #595 = VMLSslv4i16
- { 596, 7, 1, 20, "VMLSslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #596 = VMLSslv4i32
- { 597, 7, 1, 18, "VMLSslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #597 = VMLSslv8i16
- { 598, 6, 1, 18, "VMLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #598 = VMLSv16i8
- { 599, 6, 1, 19, "VMLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #599 = VMLSv2i32
- { 600, 6, 1, 17, "VMLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #600 = VMLSv4i16
- { 601, 6, 1, 20, "VMLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #601 = VMLSv4i32
- { 602, 6, 1, 18, "VMLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #602 = VMLSv8i16
- { 603, 6, 1, 17, "VMLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #603 = VMLSv8i8
- { 604, 4, 1, 87, "VMOVD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #604 = VMOVD
- { 605, 5, 1, 23, "VMOVDRR", 0|(1<<TID::Predicable), 0|(3<<4)|(19<<9)|(1<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #605 = VMOVDRR
- { 606, 5, 1, 87, "VMOVDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #606 = VMOVDcc
- { 607, 4, 1, 21, "VMOVDneon", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #607 = VMOVDneon
- { 608, 4, 1, 38, "VMOVLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #608 = VMOVLsv2i64
- { 609, 4, 1, 38, "VMOVLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #609 = VMOVLsv4i32
- { 610, 4, 1, 38, "VMOVLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #610 = VMOVLsv8i16
- { 611, 4, 1, 38, "VMOVLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #611 = VMOVLuv2i64
- { 612, 4, 1, 38, "VMOVLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #612 = VMOVLuv4i32
- { 613, 4, 1, 38, "VMOVLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #613 = VMOVLuv8i16
- { 614, 4, 1, 21, "VMOVNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #614 = VMOVNv2i32
- { 615, 4, 1, 21, "VMOVNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #615 = VMOVNv4i16
- { 616, 4, 1, 21, "VMOVNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #616 = VMOVNv8i8
- { 617, 4, 1, 21, "VMOVQ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #617 = VMOVQ
- { 618, 5, 2, 22, "VMOVRRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(17<<9)|(1<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #618 = VMOVRRD
- { 619, 4, 1, 28, "VMOVRS", 0|(1<<TID::Predicable), 0|(3<<4)|(16<<9)|(1<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #619 = VMOVRS
- { 620, 4, 1, 86, "VMOVS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #620 = VMOVS
- { 621, 4, 1, 24, "VMOVSR", 0|(1<<TID::Predicable), 0|(3<<4)|(18<<9)|(1<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #621 = VMOVSR
- { 622, 5, 1, 86, "VMOVScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #622 = VMOVScc
- { 623, 4, 1, 26, "VMOVv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #623 = VMOVv16i8
- { 624, 4, 1, 26, "VMOVv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #624 = VMOVv1i64
- { 625, 4, 1, 26, "VMOVv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #625 = VMOVv2i32
- { 626, 4, 1, 26, "VMOVv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #626 = VMOVv2i64
- { 627, 4, 1, 26, "VMOVv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #627 = VMOVv4i16
- { 628, 4, 1, 26, "VMOVv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #628 = VMOVv4i32
- { 629, 4, 1, 26, "VMOVv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #629 = VMOVv8i16
- { 630, 4, 1, 26, "VMOVv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #630 = VMOVv8i8
- { 631, 5, 1, 79, "VMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #631 = VMULD
- { 632, 5, 1, 29, "VMULLp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #632 = VMULLp
- { 633, 6, 1, 29, "VMULLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #633 = VMULLslsv2i32
- { 634, 6, 1, 29, "VMULLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #634 = VMULLslsv4i16
- { 635, 6, 1, 29, "VMULLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #635 = VMULLsluv2i32
- { 636, 6, 1, 29, "VMULLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #636 = VMULLsluv4i16
- { 637, 5, 1, 29, "VMULLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #637 = VMULLsv2i64
- { 638, 5, 1, 29, "VMULLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #638 = VMULLsv4i32
- { 639, 5, 1, 29, "VMULLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #639 = VMULLsv8i16
- { 640, 5, 1, 29, "VMULLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #640 = VMULLuv2i64
- { 641, 5, 1, 29, "VMULLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #641 = VMULLuv4i32
- { 642, 5, 1, 29, "VMULLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #642 = VMULLuv8i16
- { 643, 5, 1, 78, "VMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #643 = VMULS
- { 644, 5, 1, 1, "VMULfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #644 = VMULfd
- { 645, 5, 1, 1, "VMULfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #645 = VMULfd_sfp
- { 646, 5, 1, 2, "VMULfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #646 = VMULfq
- { 647, 5, 1, 29, "VMULpd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #647 = VMULpd
- { 648, 5, 1, 30, "VMULpq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #648 = VMULpq
- { 649, 6, 1, 1, "VMULslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #649 = VMULslfd
- { 650, 6, 1, 2, "VMULslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #650 = VMULslfq
- { 651, 6, 1, 31, "VMULslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #651 = VMULslv2i32
- { 652, 6, 1, 29, "VMULslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #652 = VMULslv4i16
- { 653, 6, 1, 32, "VMULslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #653 = VMULslv4i32
- { 654, 6, 1, 30, "VMULslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #654 = VMULslv8i16
- { 655, 5, 1, 30, "VMULv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #655 = VMULv16i8
- { 656, 5, 1, 31, "VMULv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #656 = VMULv2i32
- { 657, 5, 1, 29, "VMULv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #657 = VMULv4i16
- { 658, 5, 1, 32, "VMULv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #658 = VMULv4i32
- { 659, 5, 1, 30, "VMULv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #659 = VMULv8i16
- { 660, 5, 1, 29, "VMULv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #660 = VMULv8i8
- { 661, 4, 1, 44, "VMVNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #661 = VMVNd
- { 662, 4, 1, 44, "VMVNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #662 = VMVNq
- { 663, 4, 1, 87, "VNEGD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #663 = VNEGD
- { 664, 5, 1, 87, "VNEGDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #664 = VNEGDcc
- { 665, 4, 1, 86, "VNEGS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #665 = VNEGS
- { 666, 5, 1, 86, "VNEGScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #666 = VNEGScc
- { 667, 4, 1, 57, "VNEGf32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #667 = VNEGf32d
- { 668, 4, 1, 57, "VNEGf32d_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #668 = VNEGf32d_sfp
- { 669, 4, 1, 58, "VNEGf32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #669 = VNEGf32q
- { 670, 4, 1, 44, "VNEGs16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #670 = VNEGs16d
- { 671, 4, 1, 44, "VNEGs16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #671 = VNEGs16q
- { 672, 4, 1, 44, "VNEGs32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #672 = VNEGs32d
- { 673, 4, 1, 44, "VNEGs32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #673 = VNEGs32q
- { 674, 4, 1, 44, "VNEGs8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #674 = VNEGs8d
- { 675, 4, 1, 44, "VNEGs8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #675 = VNEGs8q
- { 676, 6, 1, 77, "VNMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #676 = VNMLAD
- { 677, 6, 1, 76, "VNMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #677 = VNMLAS
- { 678, 6, 1, 77, "VNMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #678 = VNMLSD
- { 679, 6, 1, 76, "VNMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #679 = VNMLSS
- { 680, 5, 1, 79, "VNMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #680 = VNMULD
- { 681, 5, 1, 78, "VNMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #681 = VNMULS
- { 682, 5, 1, 5, "VORNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #682 = VORNd
- { 683, 5, 1, 6, "VORNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #683 = VORNq
- { 684, 5, 1, 5, "VORRd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #684 = VORRd
- { 685, 5, 1, 6, "VORRq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #685 = VORRq
- { 686, 5, 1, 34, "VPADALsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #686 = VPADALsv16i8
- { 687, 5, 1, 33, "VPADALsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #687 = VPADALsv2i32
- { 688, 5, 1, 33, "VPADALsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #688 = VPADALsv4i16
- { 689, 5, 1, 34, "VPADALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #689 = VPADALsv4i32
- { 690, 5, 1, 34, "VPADALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #690 = VPADALsv8i16
- { 691, 5, 1, 33, "VPADALsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #691 = VPADALsv8i8
- { 692, 5, 1, 34, "VPADALuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #692 = VPADALuv16i8
- { 693, 5, 1, 33, "VPADALuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #693 = VPADALuv2i32
- { 694, 5, 1, 33, "VPADALuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #694 = VPADALuv4i16
- { 695, 5, 1, 34, "VPADALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #695 = VPADALuv4i32
- { 696, 5, 1, 34, "VPADALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #696 = VPADALuv8i16
- { 697, 5, 1, 33, "VPADALuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #697 = VPADALuv8i8
- { 698, 4, 1, 44, "VPADDLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #698 = VPADDLsv16i8
- { 699, 4, 1, 44, "VPADDLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #699 = VPADDLsv2i32
- { 700, 4, 1, 44, "VPADDLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #700 = VPADDLsv4i16
- { 701, 4, 1, 44, "VPADDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #701 = VPADDLsv4i32
- { 702, 4, 1, 44, "VPADDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #702 = VPADDLsv8i16
- { 703, 4, 1, 44, "VPADDLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #703 = VPADDLsv8i8
- { 704, 4, 1, 44, "VPADDLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #704 = VPADDLuv16i8
- { 705, 4, 1, 44, "VPADDLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #705 = VPADDLuv2i32
- { 706, 4, 1, 44, "VPADDLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #706 = VPADDLuv4i16
- { 707, 4, 1, 44, "VPADDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #707 = VPADDLuv4i32
- { 708, 4, 1, 44, "VPADDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #708 = VPADDLuv8i16
- { 709, 4, 1, 44, "VPADDLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #709 = VPADDLuv8i8
- { 710, 5, 1, 1, "VPADDf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #710 = VPADDf
- { 711, 5, 1, 5, "VPADDi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #711 = VPADDi16
- { 712, 5, 1, 5, "VPADDi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #712 = VPADDi32
- { 713, 5, 1, 5, "VPADDi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #713 = VPADDi8
- { 714, 5, 1, 3, "VPMAXf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #714 = VPMAXf
- { 715, 5, 1, 3, "VPMAXs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #715 = VPMAXs16
- { 716, 5, 1, 3, "VPMAXs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #716 = VPMAXs32
- { 717, 5, 1, 3, "VPMAXs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #717 = VPMAXs8
- { 718, 5, 1, 3, "VPMAXu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #718 = VPMAXu16
- { 719, 5, 1, 3, "VPMAXu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #719 = VPMAXu32
- { 720, 5, 1, 3, "VPMAXu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #720 = VPMAXu8
- { 721, 5, 1, 3, "VPMINf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #721 = VPMINf
- { 722, 5, 1, 3, "VPMINs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #722 = VPMINs16
- { 723, 5, 1, 3, "VPMINs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #723 = VPMINs32
- { 724, 5, 1, 3, "VPMINs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #724 = VPMINs8
- { 725, 5, 1, 3, "VPMINu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #725 = VPMINu16
- { 726, 5, 1, 3, "VPMINu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #726 = VPMINu32
- { 727, 5, 1, 3, "VPMINu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #727 = VPMINu8
- { 728, 4, 1, 39, "VQABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #728 = VQABSv16i8
- { 729, 4, 1, 38, "VQABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #729 = VQABSv2i32
- { 730, 4, 1, 38, "VQABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #730 = VQABSv4i16
- { 731, 4, 1, 39, "VQABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #731 = VQABSv4i32
- { 732, 4, 1, 39, "VQABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #732 = VQABSv8i16
- { 733, 4, 1, 38, "VQABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #733 = VQABSv8i8
- { 734, 5, 1, 4, "VQADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #734 = VQADDsv16i8
- { 735, 5, 1, 3, "VQADDsv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #735 = VQADDsv1i64
- { 736, 5, 1, 3, "VQADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #736 = VQADDsv2i32
- { 737, 5, 1, 4, "VQADDsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #737 = VQADDsv2i64
- { 738, 5, 1, 3, "VQADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #738 = VQADDsv4i16
- { 739, 5, 1, 4, "VQADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #739 = VQADDsv4i32
- { 740, 5, 1, 4, "VQADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #740 = VQADDsv8i16
- { 741, 5, 1, 3, "VQADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #741 = VQADDsv8i8
- { 742, 5, 1, 4, "VQADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #742 = VQADDuv16i8
- { 743, 5, 1, 3, "VQADDuv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #743 = VQADDuv1i64
- { 744, 5, 1, 3, "VQADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #744 = VQADDuv2i32
- { 745, 5, 1, 4, "VQADDuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #745 = VQADDuv2i64
- { 746, 5, 1, 3, "VQADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #746 = VQADDuv4i16
- { 747, 5, 1, 4, "VQADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #747 = VQADDuv4i32
- { 748, 5, 1, 4, "VQADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #748 = VQADDuv8i16
- { 749, 5, 1, 3, "VQADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #749 = VQADDuv8i8
- { 750, 7, 1, 19, "VQDMLALslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #750 = VQDMLALslv2i32
- { 751, 7, 1, 17, "VQDMLALslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #751 = VQDMLALslv4i16
- { 752, 6, 1, 17, "VQDMLALv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #752 = VQDMLALv2i64
- { 753, 6, 1, 17, "VQDMLALv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #753 = VQDMLALv4i32
- { 754, 7, 1, 19, "VQDMLSLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #754 = VQDMLSLslv2i32
- { 755, 7, 1, 17, "VQDMLSLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #755 = VQDMLSLslv4i16
- { 756, 6, 1, 17, "VQDMLSLv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #756 = VQDMLSLv2i64
- { 757, 6, 1, 17, "VQDMLSLv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #757 = VQDMLSLv4i32
- { 758, 6, 1, 31, "VQDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #758 = VQDMULHslv2i32
- { 759, 6, 1, 29, "VQDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #759 = VQDMULHslv4i16
- { 760, 6, 1, 32, "VQDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #760 = VQDMULHslv4i32
- { 761, 6, 1, 30, "VQDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #761 = VQDMULHslv8i16
- { 762, 5, 1, 31, "VQDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #762 = VQDMULHv2i32
- { 763, 5, 1, 29, "VQDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #763 = VQDMULHv4i16
- { 764, 5, 1, 32, "VQDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #764 = VQDMULHv4i32
- { 765, 5, 1, 30, "VQDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #765 = VQDMULHv8i16
- { 766, 6, 1, 29, "VQDMULLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #766 = VQDMULLslv2i32
- { 767, 6, 1, 29, "VQDMULLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #767 = VQDMULLslv4i16
- { 768, 5, 1, 29, "VQDMULLv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #768 = VQDMULLv2i64
- { 769, 5, 1, 29, "VQDMULLv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #769 = VQDMULLv4i32
- { 770, 4, 1, 38, "VQMOVNsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #770 = VQMOVNsuv2i32
- { 771, 4, 1, 38, "VQMOVNsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #771 = VQMOVNsuv4i16
- { 772, 4, 1, 38, "VQMOVNsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #772 = VQMOVNsuv8i8
- { 773, 4, 1, 38, "VQMOVNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #773 = VQMOVNsv2i32
- { 774, 4, 1, 38, "VQMOVNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #774 = VQMOVNsv4i16
- { 775, 4, 1, 38, "VQMOVNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #775 = VQMOVNsv8i8
- { 776, 4, 1, 38, "VQMOVNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #776 = VQMOVNuv2i32
- { 777, 4, 1, 38, "VQMOVNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #777 = VQMOVNuv4i16
- { 778, 4, 1, 38, "VQMOVNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #778 = VQMOVNuv8i8
- { 779, 4, 1, 39, "VQNEGv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #779 = VQNEGv16i8
- { 780, 4, 1, 38, "VQNEGv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #780 = VQNEGv2i32
- { 781, 4, 1, 38, "VQNEGv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #781 = VQNEGv4i16
- { 782, 4, 1, 39, "VQNEGv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #782 = VQNEGv4i32
- { 783, 4, 1, 39, "VQNEGv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #783 = VQNEGv8i16
- { 784, 4, 1, 38, "VQNEGv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #784 = VQNEGv8i8
- { 785, 6, 1, 31, "VQRDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #785 = VQRDMULHslv2i32
- { 786, 6, 1, 29, "VQRDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #786 = VQRDMULHslv4i16
- { 787, 6, 1, 32, "VQRDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #787 = VQRDMULHslv4i32
- { 788, 6, 1, 30, "VQRDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #788 = VQRDMULHslv8i16
- { 789, 5, 1, 31, "VQRDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #789 = VQRDMULHv2i32
- { 790, 5, 1, 29, "VQRDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #790 = VQRDMULHv4i16
- { 791, 5, 1, 32, "VQRDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #791 = VQRDMULHv4i32
- { 792, 5, 1, 30, "VQRDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #792 = VQRDMULHv8i16
- { 793, 5, 1, 43, "VQRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #793 = VQRSHLsv16i8
- { 794, 5, 1, 42, "VQRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #794 = VQRSHLsv1i64
- { 795, 5, 1, 42, "VQRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #795 = VQRSHLsv2i32
- { 796, 5, 1, 43, "VQRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #796 = VQRSHLsv2i64
- { 797, 5, 1, 42, "VQRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #797 = VQRSHLsv4i16
- { 798, 5, 1, 43, "VQRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #798 = VQRSHLsv4i32
- { 799, 5, 1, 43, "VQRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #799 = VQRSHLsv8i16
- { 800, 5, 1, 42, "VQRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #800 = VQRSHLsv8i8
- { 801, 5, 1, 43, "VQRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #801 = VQRSHLuv16i8
- { 802, 5, 1, 42, "VQRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #802 = VQRSHLuv1i64
- { 803, 5, 1, 42, "VQRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #803 = VQRSHLuv2i32
- { 804, 5, 1, 43, "VQRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #804 = VQRSHLuv2i64
- { 805, 5, 1, 42, "VQRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #805 = VQRSHLuv4i16
- { 806, 5, 1, 43, "VQRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #806 = VQRSHLuv4i32
- { 807, 5, 1, 43, "VQRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #807 = VQRSHLuv8i16
- { 808, 5, 1, 42, "VQRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #808 = VQRSHLuv8i8
- { 809, 5, 1, 42, "VQRSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #809 = VQRSHRNsv2i32
- { 810, 5, 1, 42, "VQRSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #810 = VQRSHRNsv4i16
- { 811, 5, 1, 42, "VQRSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #811 = VQRSHRNsv8i8
- { 812, 5, 1, 42, "VQRSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #812 = VQRSHRNuv2i32
- { 813, 5, 1, 42, "VQRSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #813 = VQRSHRNuv4i16
- { 814, 5, 1, 42, "VQRSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #814 = VQRSHRNuv8i8
- { 815, 5, 1, 42, "VQRSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #815 = VQRSHRUNv2i32
- { 816, 5, 1, 42, "VQRSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #816 = VQRSHRUNv4i16
- { 817, 5, 1, 42, "VQRSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #817 = VQRSHRUNv8i8
- { 818, 5, 1, 42, "VQSHLsiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #818 = VQSHLsiv16i8
- { 819, 5, 1, 42, "VQSHLsiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #819 = VQSHLsiv1i64
- { 820, 5, 1, 42, "VQSHLsiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #820 = VQSHLsiv2i32
- { 821, 5, 1, 42, "VQSHLsiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #821 = VQSHLsiv2i64
- { 822, 5, 1, 42, "VQSHLsiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #822 = VQSHLsiv4i16
- { 823, 5, 1, 42, "VQSHLsiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #823 = VQSHLsiv4i32
- { 824, 5, 1, 42, "VQSHLsiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #824 = VQSHLsiv8i16
- { 825, 5, 1, 42, "VQSHLsiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #825 = VQSHLsiv8i8
- { 826, 5, 1, 42, "VQSHLsuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #826 = VQSHLsuv16i8
- { 827, 5, 1, 42, "VQSHLsuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #827 = VQSHLsuv1i64
- { 828, 5, 1, 42, "VQSHLsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #828 = VQSHLsuv2i32
- { 829, 5, 1, 42, "VQSHLsuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #829 = VQSHLsuv2i64
- { 830, 5, 1, 42, "VQSHLsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #830 = VQSHLsuv4i16
- { 831, 5, 1, 42, "VQSHLsuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #831 = VQSHLsuv4i32
- { 832, 5, 1, 42, "VQSHLsuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #832 = VQSHLsuv8i16
- { 833, 5, 1, 42, "VQSHLsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #833 = VQSHLsuv8i8
- { 834, 5, 1, 43, "VQSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #834 = VQSHLsv16i8
- { 835, 5, 1, 42, "VQSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #835 = VQSHLsv1i64
- { 836, 5, 1, 42, "VQSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #836 = VQSHLsv2i32
- { 837, 5, 1, 43, "VQSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #837 = VQSHLsv2i64
- { 838, 5, 1, 42, "VQSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #838 = VQSHLsv4i16
- { 839, 5, 1, 43, "VQSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #839 = VQSHLsv4i32
- { 840, 5, 1, 43, "VQSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #840 = VQSHLsv8i16
- { 841, 5, 1, 42, "VQSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #841 = VQSHLsv8i8
- { 842, 5, 1, 42, "VQSHLuiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #842 = VQSHLuiv16i8
- { 843, 5, 1, 42, "VQSHLuiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #843 = VQSHLuiv1i64
- { 844, 5, 1, 42, "VQSHLuiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #844 = VQSHLuiv2i32
- { 845, 5, 1, 42, "VQSHLuiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #845 = VQSHLuiv2i64
- { 846, 5, 1, 42, "VQSHLuiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #846 = VQSHLuiv4i16
- { 847, 5, 1, 42, "VQSHLuiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #847 = VQSHLuiv4i32
- { 848, 5, 1, 42, "VQSHLuiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #848 = VQSHLuiv8i16
- { 849, 5, 1, 42, "VQSHLuiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #849 = VQSHLuiv8i8
- { 850, 5, 1, 43, "VQSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #850 = VQSHLuv16i8
- { 851, 5, 1, 42, "VQSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #851 = VQSHLuv1i64
- { 852, 5, 1, 42, "VQSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #852 = VQSHLuv2i32
- { 853, 5, 1, 43, "VQSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #853 = VQSHLuv2i64
- { 854, 5, 1, 42, "VQSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #854 = VQSHLuv4i16
- { 855, 5, 1, 43, "VQSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #855 = VQSHLuv4i32
- { 856, 5, 1, 43, "VQSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #856 = VQSHLuv8i16
- { 857, 5, 1, 42, "VQSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #857 = VQSHLuv8i8
- { 858, 5, 1, 42, "VQSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #858 = VQSHRNsv2i32
- { 859, 5, 1, 42, "VQSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #859 = VQSHRNsv4i16
- { 860, 5, 1, 42, "VQSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #860 = VQSHRNsv8i8
- { 861, 5, 1, 42, "VQSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #861 = VQSHRNuv2i32
- { 862, 5, 1, 42, "VQSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #862 = VQSHRNuv4i16
- { 863, 5, 1, 42, "VQSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #863 = VQSHRNuv8i8
- { 864, 5, 1, 42, "VQSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #864 = VQSHRUNv2i32
- { 865, 5, 1, 42, "VQSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #865 = VQSHRUNv4i16
- { 866, 5, 1, 42, "VQSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #866 = VQSHRUNv8i8
- { 867, 5, 1, 4, "VQSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #867 = VQSUBsv16i8
- { 868, 5, 1, 3, "VQSUBsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #868 = VQSUBsv1i64
- { 869, 5, 1, 3, "VQSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #869 = VQSUBsv2i32
- { 870, 5, 1, 4, "VQSUBsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #870 = VQSUBsv2i64
- { 871, 5, 1, 3, "VQSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #871 = VQSUBsv4i16
- { 872, 5, 1, 4, "VQSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #872 = VQSUBsv4i32
- { 873, 5, 1, 4, "VQSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #873 = VQSUBsv8i16
- { 874, 5, 1, 3, "VQSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #874 = VQSUBsv8i8
- { 875, 5, 1, 4, "VQSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #875 = VQSUBuv16i8
- { 876, 5, 1, 3, "VQSUBuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #876 = VQSUBuv1i64
- { 877, 5, 1, 3, "VQSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #877 = VQSUBuv2i32
- { 878, 5, 1, 4, "VQSUBuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #878 = VQSUBuv2i64
- { 879, 5, 1, 3, "VQSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #879 = VQSUBuv4i16
- { 880, 5, 1, 4, "VQSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #880 = VQSUBuv4i32
- { 881, 5, 1, 4, "VQSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #881 = VQSUBuv8i16
- { 882, 5, 1, 3, "VQSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #882 = VQSUBuv8i8
- { 883, 5, 1, 3, "VRADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #883 = VRADDHNv2i32
- { 884, 5, 1, 3, "VRADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #884 = VRADDHNv4i16
- { 885, 5, 1, 3, "VRADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #885 = VRADDHNv8i8
- { 886, 4, 1, 57, "VRECPEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #886 = VRECPEd
- { 887, 4, 1, 57, "VRECPEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #887 = VRECPEfd
- { 888, 4, 1, 58, "VRECPEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #888 = VRECPEfq
- { 889, 4, 1, 58, "VRECPEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #889 = VRECPEq
- { 890, 5, 1, 40, "VRECPSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #890 = VRECPSfd
- { 891, 5, 1, 41, "VRECPSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #891 = VRECPSfq
- { 892, 4, 1, 21, "VREV16d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #892 = VREV16d8
- { 893, 4, 1, 21, "VREV16q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #893 = VREV16q8
- { 894, 4, 1, 21, "VREV32d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #894 = VREV32d16
- { 895, 4, 1, 21, "VREV32d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #895 = VREV32d8
- { 896, 4, 1, 21, "VREV32q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #896 = VREV32q16
- { 897, 4, 1, 21, "VREV32q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #897 = VREV32q8
- { 898, 4, 1, 21, "VREV64d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #898 = VREV64d16
- { 899, 4, 1, 21, "VREV64d32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #899 = VREV64d32
- { 900, 4, 1, 21, "VREV64d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #900 = VREV64d8
- { 901, 4, 1, 21, "VREV64df", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #901 = VREV64df
- { 902, 4, 1, 21, "VREV64q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #902 = VREV64q16
- { 903, 4, 1, 21, "VREV64q32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #903 = VREV64q32
- { 904, 4, 1, 21, "VREV64q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #904 = VREV64q8
- { 905, 4, 1, 21, "VREV64qf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #905 = VREV64qf
- { 906, 5, 1, 4, "VRHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #906 = VRHADDsv16i8
- { 907, 5, 1, 3, "VRHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #907 = VRHADDsv2i32
- { 908, 5, 1, 3, "VRHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #908 = VRHADDsv4i16
- { 909, 5, 1, 4, "VRHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #909 = VRHADDsv4i32
- { 910, 5, 1, 4, "VRHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #910 = VRHADDsv8i16
- { 911, 5, 1, 3, "VRHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #911 = VRHADDsv8i8
- { 912, 5, 1, 4, "VRHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #912 = VRHADDuv16i8
- { 913, 5, 1, 3, "VRHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #913 = VRHADDuv2i32
- { 914, 5, 1, 3, "VRHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #914 = VRHADDuv4i16
- { 915, 5, 1, 4, "VRHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #915 = VRHADDuv4i32
- { 916, 5, 1, 4, "VRHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #916 = VRHADDuv8i16
- { 917, 5, 1, 3, "VRHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #917 = VRHADDuv8i8
- { 918, 5, 1, 43, "VRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #918 = VRSHLsv16i8
- { 919, 5, 1, 42, "VRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #919 = VRSHLsv1i64
- { 920, 5, 1, 42, "VRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #920 = VRSHLsv2i32
- { 921, 5, 1, 43, "VRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #921 = VRSHLsv2i64
- { 922, 5, 1, 42, "VRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #922 = VRSHLsv4i16
- { 923, 5, 1, 43, "VRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #923 = VRSHLsv4i32
- { 924, 5, 1, 43, "VRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #924 = VRSHLsv8i16
- { 925, 5, 1, 42, "VRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #925 = VRSHLsv8i8
- { 926, 5, 1, 43, "VRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #926 = VRSHLuv16i8
- { 927, 5, 1, 42, "VRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #927 = VRSHLuv1i64
- { 928, 5, 1, 42, "VRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #928 = VRSHLuv2i32
- { 929, 5, 1, 43, "VRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #929 = VRSHLuv2i64
- { 930, 5, 1, 42, "VRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #930 = VRSHLuv4i16
- { 931, 5, 1, 43, "VRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #931 = VRSHLuv4i32
- { 932, 5, 1, 43, "VRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #932 = VRSHLuv8i16
- { 933, 5, 1, 42, "VRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #933 = VRSHLuv8i8
- { 934, 5, 1, 42, "VRSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #934 = VRSHRNv2i32
- { 935, 5, 1, 42, "VRSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #935 = VRSHRNv4i16
- { 936, 5, 1, 42, "VRSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #936 = VRSHRNv8i8
- { 937, 5, 1, 42, "VRSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #937 = VRSHRsv16i8
- { 938, 5, 1, 42, "VRSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #938 = VRSHRsv1i64
- { 939, 5, 1, 42, "VRSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #939 = VRSHRsv2i32
- { 940, 5, 1, 42, "VRSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #940 = VRSHRsv2i64
- { 941, 5, 1, 42, "VRSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #941 = VRSHRsv4i16
- { 942, 5, 1, 42, "VRSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #942 = VRSHRsv4i32
- { 943, 5, 1, 42, "VRSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #943 = VRSHRsv8i16
- { 944, 5, 1, 42, "VRSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #944 = VRSHRsv8i8
- { 945, 5, 1, 42, "VRSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #945 = VRSHRuv16i8
- { 946, 5, 1, 42, "VRSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #946 = VRSHRuv1i64
- { 947, 5, 1, 42, "VRSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #947 = VRSHRuv2i32
- { 948, 5, 1, 42, "VRSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #948 = VRSHRuv2i64
- { 949, 5, 1, 42, "VRSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #949 = VRSHRuv4i16
- { 950, 5, 1, 42, "VRSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #950 = VRSHRuv4i32
- { 951, 5, 1, 42, "VRSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #951 = VRSHRuv8i16
- { 952, 5, 1, 42, "VRSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #952 = VRSHRuv8i8
- { 953, 4, 1, 57, "VRSQRTEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #953 = VRSQRTEd
- { 954, 4, 1, 57, "VRSQRTEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #954 = VRSQRTEfd
- { 955, 4, 1, 58, "VRSQRTEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #955 = VRSQRTEfq
- { 956, 4, 1, 58, "VRSQRTEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #956 = VRSQRTEq
- { 957, 5, 1, 40, "VRSQRTSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #957 = VRSQRTSfd
- { 958, 5, 1, 41, "VRSQRTSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #958 = VRSQRTSfq
- { 959, 6, 1, 33, "VRSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #959 = VRSRAsv16i8
- { 960, 6, 1, 33, "VRSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #960 = VRSRAsv1i64
- { 961, 6, 1, 33, "VRSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #961 = VRSRAsv2i32
- { 962, 6, 1, 33, "VRSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #962 = VRSRAsv2i64
- { 963, 6, 1, 33, "VRSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #963 = VRSRAsv4i16
- { 964, 6, 1, 33, "VRSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #964 = VRSRAsv4i32
- { 965, 6, 1, 33, "VRSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #965 = VRSRAsv8i16
- { 966, 6, 1, 33, "VRSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #966 = VRSRAsv8i8
- { 967, 6, 1, 33, "VRSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #967 = VRSRAuv16i8
- { 968, 6, 1, 33, "VRSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #968 = VRSRAuv1i64
- { 969, 6, 1, 33, "VRSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #969 = VRSRAuv2i32
- { 970, 6, 1, 33, "VRSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #970 = VRSRAuv2i64
- { 971, 6, 1, 33, "VRSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #971 = VRSRAuv4i16
- { 972, 6, 1, 33, "VRSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #972 = VRSRAuv4i32
- { 973, 6, 1, 33, "VRSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #973 = VRSRAuv8i16
- { 974, 6, 1, 33, "VRSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #974 = VRSRAuv8i8
- { 975, 5, 1, 3, "VRSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #975 = VRSUBHNv2i32
- { 976, 5, 1, 3, "VRSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #976 = VRSUBHNv4i16
- { 977, 5, 1, 3, "VRSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #977 = VRSUBHNv8i8
- { 978, 6, 1, 25, "VSETLNi16", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo109 }, // Inst #978 = VSETLNi16
- { 979, 6, 1, 25, "VSETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo109 }, // Inst #979 = VSETLNi32
- { 980, 6, 1, 25, "VSETLNi8", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo109 }, // Inst #980 = VSETLNi8
- { 981, 5, 1, 44, "VSHLLi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #981 = VSHLLi16
- { 982, 5, 1, 44, "VSHLLi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #982 = VSHLLi32
- { 983, 5, 1, 44, "VSHLLi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #983 = VSHLLi8
- { 984, 5, 1, 44, "VSHLLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #984 = VSHLLsv2i64
- { 985, 5, 1, 44, "VSHLLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #985 = VSHLLsv4i32
- { 986, 5, 1, 44, "VSHLLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #986 = VSHLLsv8i16
- { 987, 5, 1, 44, "VSHLLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #987 = VSHLLuv2i64
- { 988, 5, 1, 44, "VSHLLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #988 = VSHLLuv4i32
- { 989, 5, 1, 44, "VSHLLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #989 = VSHLLuv8i16
- { 990, 5, 1, 44, "VSHLiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #990 = VSHLiv16i8
- { 991, 5, 1, 44, "VSHLiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #991 = VSHLiv1i64
- { 992, 5, 1, 44, "VSHLiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #992 = VSHLiv2i32
- { 993, 5, 1, 44, "VSHLiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #993 = VSHLiv2i64
- { 994, 5, 1, 44, "VSHLiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #994 = VSHLiv4i16
- { 995, 5, 1, 44, "VSHLiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #995 = VSHLiv4i32
- { 996, 5, 1, 44, "VSHLiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #996 = VSHLiv8i16
- { 997, 5, 1, 44, "VSHLiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #997 = VSHLiv8i8
- { 998, 5, 1, 45, "VSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #998 = VSHLsv16i8
- { 999, 5, 1, 44, "VSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #999 = VSHLsv1i64
- { 1000, 5, 1, 44, "VSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1000 = VSHLsv2i32
- { 1001, 5, 1, 45, "VSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1001 = VSHLsv2i64
- { 1002, 5, 1, 44, "VSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1002 = VSHLsv4i16
- { 1003, 5, 1, 45, "VSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1003 = VSHLsv4i32
- { 1004, 5, 1, 45, "VSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1004 = VSHLsv8i16
- { 1005, 5, 1, 44, "VSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1005 = VSHLsv8i8
- { 1006, 5, 1, 45, "VSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1006 = VSHLuv16i8
- { 1007, 5, 1, 44, "VSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1007 = VSHLuv1i64
- { 1008, 5, 1, 44, "VSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1008 = VSHLuv2i32
- { 1009, 5, 1, 45, "VSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1009 = VSHLuv2i64
- { 1010, 5, 1, 44, "VSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1010 = VSHLuv4i16
- { 1011, 5, 1, 45, "VSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1011 = VSHLuv4i32
- { 1012, 5, 1, 45, "VSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1012 = VSHLuv8i16
- { 1013, 5, 1, 44, "VSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1013 = VSHLuv8i8
- { 1014, 5, 1, 44, "VSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1014 = VSHRNv2i32
- { 1015, 5, 1, 44, "VSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1015 = VSHRNv4i16
- { 1016, 5, 1, 44, "VSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1016 = VSHRNv8i8
- { 1017, 5, 1, 44, "VSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1017 = VSHRsv16i8
- { 1018, 5, 1, 44, "VSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1018 = VSHRsv1i64
- { 1019, 5, 1, 44, "VSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1019 = VSHRsv2i32
- { 1020, 5, 1, 44, "VSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1020 = VSHRsv2i64
- { 1021, 5, 1, 44, "VSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1021 = VSHRsv4i16
- { 1022, 5, 1, 44, "VSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1022 = VSHRsv4i32
- { 1023, 5, 1, 44, "VSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1023 = VSHRsv8i16
- { 1024, 5, 1, 44, "VSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1024 = VSHRsv8i8
- { 1025, 5, 1, 44, "VSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1025 = VSHRuv16i8
- { 1026, 5, 1, 44, "VSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1026 = VSHRuv1i64
- { 1027, 5, 1, 44, "VSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1027 = VSHRuv2i32
- { 1028, 5, 1, 44, "VSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1028 = VSHRuv2i64
- { 1029, 5, 1, 44, "VSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1029 = VSHRuv4i16
- { 1030, 5, 1, 44, "VSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1030 = VSHRuv4i32
- { 1031, 5, 1, 44, "VSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1031 = VSHRuv8i16
- { 1032, 5, 1, 44, "VSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1032 = VSHRuv8i8
- { 1033, 4, 1, 67, "VSITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1033 = VSITOD
- { 1034, 4, 1, 68, "VSITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #1034 = VSITOS
- { 1035, 6, 1, 45, "VSLIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1035 = VSLIv16i8
- { 1036, 6, 1, 44, "VSLIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1036 = VSLIv1i64
- { 1037, 6, 1, 44, "VSLIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1037 = VSLIv2i32
- { 1038, 6, 1, 45, "VSLIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1038 = VSLIv2i64
- { 1039, 6, 1, 44, "VSLIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1039 = VSLIv4i16
- { 1040, 6, 1, 45, "VSLIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1040 = VSLIv4i32
- { 1041, 6, 1, 45, "VSLIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1041 = VSLIv8i16
- { 1042, 6, 1, 44, "VSLIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1042 = VSLIv8i8
- { 1043, 4, 1, 81, "VSQRTD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #1043 = VSQRTD
- { 1044, 4, 1, 80, "VSQRTS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #1044 = VSQRTS
- { 1045, 6, 1, 33, "VSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1045 = VSRAsv16i8
- { 1046, 6, 1, 33, "VSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1046 = VSRAsv1i64
- { 1047, 6, 1, 33, "VSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1047 = VSRAsv2i32
- { 1048, 6, 1, 33, "VSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1048 = VSRAsv2i64
- { 1049, 6, 1, 33, "VSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1049 = VSRAsv4i16
- { 1050, 6, 1, 33, "VSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1050 = VSRAsv4i32
- { 1051, 6, 1, 33, "VSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1051 = VSRAsv8i16
- { 1052, 6, 1, 33, "VSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1052 = VSRAsv8i8
- { 1053, 6, 1, 33, "VSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1053 = VSRAuv16i8
- { 1054, 6, 1, 33, "VSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1054 = VSRAuv1i64
- { 1055, 6, 1, 33, "VSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1055 = VSRAuv2i32
- { 1056, 6, 1, 33, "VSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1056 = VSRAuv2i64
- { 1057, 6, 1, 33, "VSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1057 = VSRAuv4i16
- { 1058, 6, 1, 33, "VSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1058 = VSRAuv4i32
- { 1059, 6, 1, 33, "VSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1059 = VSRAuv8i16
- { 1060, 6, 1, 33, "VSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1060 = VSRAuv8i8
- { 1061, 6, 1, 45, "VSRIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1061 = VSRIv16i8
- { 1062, 6, 1, 44, "VSRIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1062 = VSRIv1i64
- { 1063, 6, 1, 44, "VSRIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1063 = VSRIv2i32
- { 1064, 6, 1, 45, "VSRIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1064 = VSRIv2i64
- { 1065, 6, 1, 44, "VSRIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1065 = VSRIv4i16
- { 1066, 6, 1, 45, "VSRIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1066 = VSRIv4i32
- { 1067, 6, 1, 45, "VSRIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1067 = VSRIv8i16
- { 1068, 6, 1, 44, "VSRIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1068 = VSRIv8i8
- { 1069, 7, 0, 46, "VST1d16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1069 = VST1d16
- { 1070, 7, 0, 46, "VST1d32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1070 = VST1d32
- { 1071, 7, 0, 46, "VST1d64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1071 = VST1d64
- { 1072, 7, 0, 46, "VST1d8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1072 = VST1d8
- { 1073, 7, 0, 46, "VST1df", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1073 = VST1df
- { 1074, 7, 0, 46, "VST1q16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1074 = VST1q16
- { 1075, 7, 0, 46, "VST1q32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1075 = VST1q32
- { 1076, 7, 0, 46, "VST1q64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1076 = VST1q64
- { 1077, 7, 0, 46, "VST1q8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1077 = VST1q8
- { 1078, 7, 0, 46, "VST1qf", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1078 = VST1qf
- { 1079, 9, 0, 46, "VST2LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1079 = VST2LNd16
- { 1080, 9, 0, 46, "VST2LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1080 = VST2LNd32
- { 1081, 9, 0, 46, "VST2LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1081 = VST2LNd8
- { 1082, 9, 0, 46, "VST2LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1082 = VST2LNq16a
- { 1083, 9, 0, 46, "VST2LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1083 = VST2LNq16b
- { 1084, 9, 0, 46, "VST2LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1084 = VST2LNq32a
- { 1085, 9, 0, 46, "VST2LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1085 = VST2LNq32b
- { 1086, 8, 0, 46, "VST2d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1086 = VST2d16
- { 1087, 8, 0, 46, "VST2d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1087 = VST2d32
- { 1088, 8, 0, 46, "VST2d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1088 = VST2d64
- { 1089, 8, 0, 46, "VST2d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1089 = VST2d8
- { 1090, 10, 0, 46, "VST2q16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1090 = VST2q16
- { 1091, 10, 0, 46, "VST2q32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1091 = VST2q32
- { 1092, 10, 0, 46, "VST2q8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1092 = VST2q8
- { 1093, 10, 0, 46, "VST3LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1093 = VST3LNd16
- { 1094, 10, 0, 46, "VST3LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1094 = VST3LNd32
- { 1095, 10, 0, 46, "VST3LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1095 = VST3LNd8
- { 1096, 10, 0, 46, "VST3LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1096 = VST3LNq16a
- { 1097, 10, 0, 46, "VST3LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1097 = VST3LNq16b
- { 1098, 10, 0, 46, "VST3LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1098 = VST3LNq32a
- { 1099, 10, 0, 46, "VST3LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1099 = VST3LNq32b
- { 1100, 9, 0, 46, "VST3d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1100 = VST3d16
- { 1101, 9, 0, 46, "VST3d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1101 = VST3d32
- { 1102, 9, 0, 46, "VST3d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1102 = VST3d64
- { 1103, 9, 0, 46, "VST3d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1103 = VST3d8
- { 1104, 10, 1, 46, "VST3q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1104 = VST3q16a
- { 1105, 10, 1, 46, "VST3q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1105 = VST3q16b
- { 1106, 10, 1, 46, "VST3q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1106 = VST3q32a
- { 1107, 10, 1, 46, "VST3q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1107 = VST3q32b
- { 1108, 10, 1, 46, "VST3q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1108 = VST3q8a
- { 1109, 10, 1, 46, "VST3q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1109 = VST3q8b
- { 1110, 11, 0, 46, "VST4LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1110 = VST4LNd16
- { 1111, 11, 0, 46, "VST4LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1111 = VST4LNd32
- { 1112, 11, 0, 46, "VST4LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1112 = VST4LNd8
- { 1113, 11, 0, 46, "VST4LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1113 = VST4LNq16a
- { 1114, 11, 0, 46, "VST4LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1114 = VST4LNq16b
- { 1115, 11, 0, 46, "VST4LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1115 = VST4LNq32a
- { 1116, 11, 0, 46, "VST4LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1116 = VST4LNq32b
- { 1117, 10, 0, 46, "VST4d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1117 = VST4d16
- { 1118, 10, 0, 46, "VST4d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1118 = VST4d32
- { 1119, 10, 0, 46, "VST4d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1119 = VST4d64
- { 1120, 10, 0, 46, "VST4d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1120 = VST4d8
- { 1121, 11, 1, 46, "VST4q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1121 = VST4q16a
- { 1122, 11, 1, 46, "VST4q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1122 = VST4q16b
- { 1123, 11, 1, 46, "VST4q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1123 = VST4q32a
- { 1124, 11, 1, 46, "VST4q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1124 = VST4q32b
- { 1125, 11, 1, 46, "VST4q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1125 = VST4q8a
- { 1126, 11, 1, 46, "VST4q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1126 = VST4q8b
- { 1127, 5, 0, 85, "VSTMD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #1127 = VSTMD
- { 1128, 5, 0, 85, "VSTMS", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #1128 = VSTMS
- { 1129, 5, 0, 84, "VSTRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #1129 = VSTRD
- { 1130, 5, 0, 85, "VSTRQ", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1130 = VSTRQ
- { 1131, 5, 0, 83, "VSTRS", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #1131 = VSTRS
- { 1132, 5, 1, 62, "VSUBD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1132 = VSUBD
- { 1133, 5, 1, 3, "VSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1133 = VSUBHNv2i32
- { 1134, 5, 1, 3, "VSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1134 = VSUBHNv4i16
- { 1135, 5, 1, 3, "VSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1135 = VSUBHNv8i8
- { 1136, 5, 1, 44, "VSUBLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1136 = VSUBLsv2i64
- { 1137, 5, 1, 44, "VSUBLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1137 = VSUBLsv4i32
- { 1138, 5, 1, 44, "VSUBLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1138 = VSUBLsv8i16
- { 1139, 5, 1, 44, "VSUBLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1139 = VSUBLuv2i64
- { 1140, 5, 1, 44, "VSUBLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1140 = VSUBLuv4i32
- { 1141, 5, 1, 44, "VSUBLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1141 = VSUBLuv8i16
- { 1142, 5, 1, 61, "VSUBS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #1142 = VSUBS
- { 1143, 5, 1, 47, "VSUBWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1143 = VSUBWsv2i64
- { 1144, 5, 1, 47, "VSUBWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1144 = VSUBWsv4i32
- { 1145, 5, 1, 47, "VSUBWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1145 = VSUBWsv8i16
- { 1146, 5, 1, 47, "VSUBWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1146 = VSUBWuv2i64
- { 1147, 5, 1, 47, "VSUBWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1147 = VSUBWuv4i32
- { 1148, 5, 1, 47, "VSUBWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1148 = VSUBWuv8i16
- { 1149, 5, 1, 1, "VSUBfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1149 = VSUBfd
- { 1150, 5, 1, 1, "VSUBfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1150 = VSUBfd_sfp
- { 1151, 5, 1, 2, "VSUBfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1151 = VSUBfq
- { 1152, 5, 1, 48, "VSUBv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1152 = VSUBv16i8
- { 1153, 5, 1, 47, "VSUBv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1153 = VSUBv1i64
- { 1154, 5, 1, 47, "VSUBv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1154 = VSUBv2i32
- { 1155, 5, 1, 48, "VSUBv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1155 = VSUBv2i64
- { 1156, 5, 1, 47, "VSUBv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1156 = VSUBv4i16
- { 1157, 5, 1, 48, "VSUBv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1157 = VSUBv4i32
- { 1158, 5, 1, 48, "VSUBv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1158 = VSUBv8i16
- { 1159, 5, 1, 47, "VSUBv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1159 = VSUBv8i8
- { 1160, 5, 1, 49, "VTBL1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1160 = VTBL1
- { 1161, 6, 1, 50, "VTBL2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1161 = VTBL2
- { 1162, 7, 1, 51, "VTBL3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1162 = VTBL3
- { 1163, 8, 1, 52, "VTBL4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1163 = VTBL4
- { 1164, 6, 1, 53, "VTBX1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1164 = VTBX1
- { 1165, 7, 1, 54, "VTBX2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #1165 = VTBX2
- { 1166, 8, 1, 55, "VTBX3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1166 = VTBX3
- { 1167, 9, 1, 56, "VTBX4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1167 = VTBX4
- { 1168, 4, 1, 65, "VTOSIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1168 = VTOSIZD
- { 1169, 4, 1, 70, "VTOSIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #1169 = VTOSIZS
- { 1170, 4, 1, 65, "VTOUIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1170 = VTOUIZD
- { 1171, 4, 1, 70, "VTOUIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #1171 = VTOUIZS
- { 1172, 6, 2, 35, "VTRNd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1172 = VTRNd16
- { 1173, 6, 2, 35, "VTRNd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1173 = VTRNd32
- { 1174, 6, 2, 35, "VTRNd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1174 = VTRNd8
- { 1175, 6, 2, 36, "VTRNq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1175 = VTRNq16
- { 1176, 6, 2, 36, "VTRNq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1176 = VTRNq32
- { 1177, 6, 2, 36, "VTRNq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1177 = VTRNq8
- { 1178, 5, 1, 4, "VTSTv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1178 = VTSTv16i8
- { 1179, 5, 1, 3, "VTSTv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1179 = VTSTv2i32
- { 1180, 5, 1, 3, "VTSTv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1180 = VTSTv4i16
- { 1181, 5, 1, 4, "VTSTv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1181 = VTSTv4i32
- { 1182, 5, 1, 4, "VTSTv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1182 = VTSTv8i16
- { 1183, 5, 1, 3, "VTSTv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1183 = VTSTv8i8
- { 1184, 4, 1, 67, "VUITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1184 = VUITOD
- { 1185, 4, 1, 68, "VUITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #1185 = VUITOS
- { 1186, 6, 2, 35, "VUZPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1186 = VUZPd16
- { 1187, 6, 2, 35, "VUZPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1187 = VUZPd32
- { 1188, 6, 2, 35, "VUZPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1188 = VUZPd8
- { 1189, 6, 2, 37, "VUZPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1189 = VUZPq16
- { 1190, 6, 2, 37, "VUZPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1190 = VUZPq32
- { 1191, 6, 2, 37, "VUZPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1191 = VUZPq8
- { 1192, 6, 2, 35, "VZIPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1192 = VZIPd16
- { 1193, 6, 2, 35, "VZIPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1193 = VZIPd32
- { 1194, 6, 2, 35, "VZIPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1194 = VZIPd8
- { 1195, 6, 2, 37, "VZIPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1195 = VZIPq16
- { 1196, 6, 2, 37, "VZIPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1196 = VZIPq32
- { 1197, 6, 2, 37, "VZIPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1197 = VZIPq8
- { 1198, 3, 1, 88, "t2ADCSri", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #1198 = t2ADCSri
- { 1199, 3, 1, 89, "t2ADCSrr", 0|(1<<TID::Commutable), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #1199 = t2ADCSrr
- { 1200, 4, 1, 90, "t2ADCSrs", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo128 }, // Inst #1200 = t2ADCSrs
- { 1201, 6, 1, 88, "t2ADCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #1201 = t2ADCri
- { 1202, 6, 1, 89, "t2ADCrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #1202 = t2ADCrr
- { 1203, 7, 1, 90, "t2ADCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo37 }, // Inst #1203 = t2ADCrs
- { 1204, 5, 1, 88, "t2ADDSri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1204 = t2ADDSri
- { 1205, 5, 1, 89, "t2ADDSrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1205 = t2ADDSrr
- { 1206, 6, 1, 90, "t2ADDSrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1206 = t2ADDSrs
- { 1207, 6, 1, 88, "t2ADDrSPi", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1207 = t2ADDrSPi
- { 1208, 5, 1, 88, "t2ADDrSPi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1208 = t2ADDrSPi12
- { 1209, 7, 1, 90, "t2ADDrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1209 = t2ADDrSPs
- { 1210, 6, 1, 88, "t2ADDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1210 = t2ADDri
- { 1211, 6, 1, 88, "t2ADDri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1211 = t2ADDri12
- { 1212, 6, 1, 89, "t2ADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1212 = t2ADDrr
- { 1213, 7, 1, 90, "t2ADDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1213 = t2ADDrs
- { 1214, 6, 1, 88, "t2ANDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1214 = t2ANDri
- { 1215, 6, 1, 89, "t2ANDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1215 = t2ANDrr
- { 1216, 7, 1, 90, "t2ANDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1216 = t2ANDrs
- { 1217, 6, 1, 113, "t2ASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1217 = t2ASRri
- { 1218, 6, 1, 114, "t2ASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1218 = t2ASRrr
- { 1219, 1, 0, 0, "t2B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1219 = t2B
- { 1220, 5, 1, 126, "t2BFC", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1220 = t2BFC
- { 1221, 6, 1, 88, "t2BICri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1221 = t2BICri
- { 1222, 6, 1, 89, "t2BICrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1222 = t2BICrr
- { 1223, 7, 1, 90, "t2BICrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1223 = t2BICrs
- { 1224, 4, 0, 0, "t2BR_JT", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo17 }, // Inst #1224 = t2BR_JT
- { 1225, 3, 0, 0, "t2Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1225 = t2Bcc
- { 1226, 4, 1, 125, "t2CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1226 = t2CLZ
- { 1227, 4, 0, 97, "t2CMNri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1227 = t2CMNri
- { 1228, 4, 0, 98, "t2CMNrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1228 = t2CMNrr
- { 1229, 5, 0, 99, "t2CMNrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1229 = t2CMNrs
- { 1230, 4, 0, 97, "t2CMNzri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1230 = t2CMNzri
- { 1231, 4, 0, 98, "t2CMNzrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1231 = t2CMNzrr
- { 1232, 5, 0, 99, "t2CMNzrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1232 = t2CMNzrs
- { 1233, 4, 0, 97, "t2CMPri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1233 = t2CMPri
- { 1234, 4, 0, 98, "t2CMPrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1234 = t2CMPrr
- { 1235, 5, 0, 99, "t2CMPrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1235 = t2CMPrs
- { 1236, 4, 0, 97, "t2CMPzri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1236 = t2CMPzri
- { 1237, 4, 0, 98, "t2CMPzrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1237 = t2CMPzrr
- { 1238, 5, 0, 99, "t2CMPzrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1238 = t2CMPzrs
- { 1239, 6, 1, 88, "t2EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1239 = t2EORri
- { 1240, 6, 1, 89, "t2EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1240 = t2EORrr
- { 1241, 7, 1, 90, "t2EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1241 = t2EORrs
- { 1242, 2, 0, 92, "t2IT", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo129 }, // Inst #1242 = t2IT
- { 1243, 0, 0, 128, "t2Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #1243 = t2Int_MemBarrierV7
- { 1244, 0, 0, 128, "t2Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #1244 = t2Int_SyncBarrierV7
- { 1245, 1, 0, 128, "t2Int_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList6, Barriers4, OperandInfo16 }, // Inst #1245 = t2Int_eh_sjlj_setjmp
- { 1246, 5, 0, 103, "t2LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1246 = t2LDM
- { 1247, 5, 0, 0, "t2LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1247 = t2LDM_RET
- { 1248, 6, 2, 102, "t2LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1248 = t2LDRB_POST
- { 1249, 6, 2, 102, "t2LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1249 = t2LDRB_PRE
- { 1250, 5, 1, 101, "t2LDRBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1250 = t2LDRBi12
- { 1251, 5, 1, 101, "t2LDRBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1251 = t2LDRBi8
- { 1252, 4, 1, 101, "t2LDRBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1252 = t2LDRBpci
- { 1253, 6, 1, 104, "t2LDRBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1253 = t2LDRBs
- { 1254, 6, 2, 101, "t2LDRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1254 = t2LDRDi8
- { 1255, 5, 2, 101, "t2LDRDpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1255 = t2LDRDpci
- { 1256, 4, 1, 128, "t2LDREX", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1256 = t2LDREX
- { 1257, 4, 1, 128, "t2LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1257 = t2LDREXB
- { 1258, 5, 2, 128, "t2LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1258 = t2LDREXD
- { 1259, 4, 1, 128, "t2LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1259 = t2LDREXH
- { 1260, 6, 2, 102, "t2LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1260 = t2LDRH_POST
- { 1261, 6, 2, 102, "t2LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1261 = t2LDRH_PRE
- { 1262, 5, 1, 101, "t2LDRHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1262 = t2LDRHi12
- { 1263, 5, 1, 101, "t2LDRHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1263 = t2LDRHi8
- { 1264, 4, 1, 101, "t2LDRHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1264 = t2LDRHpci
- { 1265, 6, 1, 104, "t2LDRHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1265 = t2LDRHs
- { 1266, 6, 2, 102, "t2LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1266 = t2LDRSB_POST
- { 1267, 6, 2, 102, "t2LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1267 = t2LDRSB_PRE
- { 1268, 5, 1, 101, "t2LDRSBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1268 = t2LDRSBi12
- { 1269, 5, 1, 101, "t2LDRSBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1269 = t2LDRSBi8
- { 1270, 4, 1, 101, "t2LDRSBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1270 = t2LDRSBpci
- { 1271, 6, 1, 104, "t2LDRSBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1271 = t2LDRSBs
- { 1272, 6, 2, 102, "t2LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1272 = t2LDRSH_POST
- { 1273, 6, 2, 102, "t2LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1273 = t2LDRSH_PRE
- { 1274, 5, 1, 101, "t2LDRSHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1274 = t2LDRSHi12
- { 1275, 5, 1, 101, "t2LDRSHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1275 = t2LDRSHi8
- { 1276, 4, 1, 101, "t2LDRSHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1276 = t2LDRSHpci
- { 1277, 6, 1, 104, "t2LDRSHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1277 = t2LDRSHs
- { 1278, 6, 2, 102, "t2LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1278 = t2LDR_POST
- { 1279, 6, 2, 102, "t2LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1279 = t2LDR_PRE
- { 1280, 5, 1, 101, "t2LDRi12", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1280 = t2LDRi12
- { 1281, 5, 1, 101, "t2LDRi8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1281 = t2LDRi8
- { 1282, 4, 1, 101, "t2LDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1282 = t2LDRpci
- { 1283, 3, 1, 128, "t2LDRpci_pic", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo19 }, // Inst #1283 = t2LDRpci_pic
- { 1284, 6, 1, 104, "t2LDRs", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1284 = t2LDRs
- { 1285, 4, 1, 88, "t2LEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1285 = t2LEApcrel
- { 1286, 5, 1, 88, "t2LEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo30 }, // Inst #1286 = t2LEApcrelJT
- { 1287, 6, 1, 113, "t2LSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1287 = t2LSLri
- { 1288, 6, 1, 114, "t2LSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1288 = t2LSLrr
- { 1289, 6, 1, 113, "t2LSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1289 = t2LSRri
- { 1290, 6, 1, 114, "t2LSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1290 = t2LSRrr
- { 1291, 6, 1, 109, "t2MLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1291 = t2MLA
- { 1292, 6, 1, 109, "t2MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1292 = t2MLS
- { 1293, 6, 1, 95, "t2MOVCCasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo131 }, // Inst #1293 = t2MOVCCasr
- { 1294, 5, 1, 93, "t2MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1294 = t2MOVCCi
- { 1295, 6, 1, 95, "t2MOVCClsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo131 }, // Inst #1295 = t2MOVCClsl
- { 1296, 6, 1, 95, "t2MOVCClsr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo131 }, // Inst #1296 = t2MOVCClsr
- { 1297, 5, 1, 94, "t2MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #1297 = t2MOVCCr
- { 1298, 6, 1, 95, "t2MOVCCror", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo131 }, // Inst #1298 = t2MOVCCror
- { 1299, 5, 1, 111, "t2MOVTi16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1299 = t2MOVTi16
- { 1300, 5, 1, 111, "t2MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1300 = t2MOVi
- { 1301, 4, 1, 111, "t2MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1301 = t2MOVi16
- { 1302, 4, 1, 111, "t2MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(2<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1302 = t2MOVi32imm
- { 1303, 5, 1, 112, "t2MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #1303 = t2MOVr
- { 1304, 5, 1, 113, "t2MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo36 }, // Inst #1304 = t2MOVrx
- { 1305, 2, 1, 113, "t2MOVsra_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo132 }, // Inst #1305 = t2MOVsra_flag
- { 1306, 2, 1, 113, "t2MOVsrl_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo132 }, // Inst #1306 = t2MOVsrl_flag
- { 1307, 5, 1, 116, "t2MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1307 = t2MUL
- { 1308, 5, 1, 111, "t2MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1308 = t2MVNi
- { 1309, 4, 1, 112, "t2MVNr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1309 = t2MVNr
- { 1310, 5, 1, 113, "t2MVNs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1310 = t2MVNs
- { 1311, 6, 1, 88, "t2ORNri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1311 = t2ORNri
- { 1312, 6, 1, 89, "t2ORNrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1312 = t2ORNrr
- { 1313, 7, 1, 90, "t2ORNrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1313 = t2ORNrs
- { 1314, 6, 1, 88, "t2ORRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1314 = t2ORRri
- { 1315, 6, 1, 89, "t2ORRrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1315 = t2ORRrr
- { 1316, 7, 1, 90, "t2ORRrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1316 = t2ORRrs
- { 1317, 6, 1, 90, "t2PKHBT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1317 = t2PKHBT
- { 1318, 6, 1, 90, "t2PKHTB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1318 = t2PKHTB
- { 1319, 4, 1, 125, "t2REV", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1319 = t2REV
- { 1320, 4, 1, 125, "t2REV16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1320 = t2REV16
- { 1321, 4, 1, 125, "t2REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1321 = t2REVSH
- { 1322, 6, 1, 113, "t2RORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1322 = t2RORri
- { 1323, 6, 1, 114, "t2RORrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1323 = t2RORrr
- { 1324, 4, 1, 88, "t2RSBSri", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo133 }, // Inst #1324 = t2RSBSri
- { 1325, 5, 1, 90, "t2RSBSrs", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo134 }, // Inst #1325 = t2RSBSrs
- { 1326, 5, 1, 88, "t2RSBri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1326 = t2RSBri
- { 1327, 6, 1, 90, "t2RSBrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1327 = t2RSBrs
- { 1328, 3, 1, 88, "t2SBCSri", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #1328 = t2SBCSri
- { 1329, 3, 1, 89, "t2SBCSrr", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #1329 = t2SBCSrr
- { 1330, 4, 1, 90, "t2SBCSrs", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo128 }, // Inst #1330 = t2SBCSrs
- { 1331, 6, 1, 88, "t2SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #1331 = t2SBCri
- { 1332, 6, 1, 89, "t2SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #1332 = t2SBCrr
- { 1333, 7, 1, 90, "t2SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo37 }, // Inst #1333 = t2SBCrs
- { 1334, 6, 1, 88, "t2SBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #1334 = t2SBFX
- { 1335, 6, 1, 108, "t2SMLABB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1335 = t2SMLABB
- { 1336, 6, 1, 108, "t2SMLABT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1336 = t2SMLABT
- { 1337, 6, 2, 110, "t2SMLAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1337 = t2SMLAL
- { 1338, 6, 1, 108, "t2SMLATB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1338 = t2SMLATB
- { 1339, 6, 1, 108, "t2SMLATT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1339 = t2SMLATT
- { 1340, 6, 1, 108, "t2SMLAWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1340 = t2SMLAWB
- { 1341, 6, 1, 108, "t2SMLAWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1341 = t2SMLAWT
- { 1342, 6, 1, 109, "t2SMMLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1342 = t2SMMLA
- { 1343, 6, 1, 109, "t2SMMLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1343 = t2SMMLS
- { 1344, 5, 1, 116, "t2SMMUL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1344 = t2SMMUL
- { 1345, 5, 1, 116, "t2SMULBB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1345 = t2SMULBB
- { 1346, 5, 1, 116, "t2SMULBT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1346 = t2SMULBT
- { 1347, 6, 2, 117, "t2SMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1347 = t2SMULL
- { 1348, 5, 1, 116, "t2SMULTB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1348 = t2SMULTB
- { 1349, 5, 1, 116, "t2SMULTT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1349 = t2SMULTT
- { 1350, 5, 1, 115, "t2SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1350 = t2SMULWB
- { 1351, 5, 1, 115, "t2SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1351 = t2SMULWT
- { 1352, 5, 0, 120, "t2STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1352 = t2STM
- { 1353, 6, 1, 119, "t2STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1353 = t2STRB_POST
- { 1354, 6, 1, 119, "t2STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1354 = t2STRB_PRE
- { 1355, 5, 0, 118, "t2STRBi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1355 = t2STRBi12
- { 1356, 5, 0, 118, "t2STRBi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1356 = t2STRBi8
- { 1357, 6, 0, 121, "t2STRBs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1357 = t2STRBs
- { 1358, 6, 0, 121, "t2STRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1358 = t2STRDi8
- { 1359, 5, 1, 128, "t2STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1359 = t2STREX
- { 1360, 5, 1, 128, "t2STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1360 = t2STREXB
- { 1361, 6, 1, 128, "t2STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo41 }, // Inst #1361 = t2STREXD
- { 1362, 5, 1, 128, "t2STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1362 = t2STREXH
- { 1363, 6, 1, 119, "t2STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1363 = t2STRH_POST
- { 1364, 6, 1, 119, "t2STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1364 = t2STRH_PRE
- { 1365, 5, 0, 118, "t2STRHi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1365 = t2STRHi12
- { 1366, 5, 0, 118, "t2STRHi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1366 = t2STRHi8
- { 1367, 6, 0, 121, "t2STRHs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1367 = t2STRHs
- { 1368, 6, 1, 119, "t2STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1368 = t2STR_POST
- { 1369, 6, 1, 119, "t2STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1369 = t2STR_PRE
- { 1370, 5, 0, 118, "t2STRi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1370 = t2STRi12
- { 1371, 5, 0, 118, "t2STRi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1371 = t2STRi8
- { 1372, 6, 0, 121, "t2STRs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1372 = t2STRs
- { 1373, 5, 1, 88, "t2SUBSri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1373 = t2SUBSri
- { 1374, 5, 1, 89, "t2SUBSrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1374 = t2SUBSrr
- { 1375, 6, 1, 90, "t2SUBSrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1375 = t2SUBSrs
- { 1376, 6, 1, 88, "t2SUBrSPi", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1376 = t2SUBrSPi
- { 1377, 5, 1, 88, "t2SUBrSPi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1377 = t2SUBrSPi12
- { 1378, 3, 1, 128, "t2SUBrSPi12_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1378 = t2SUBrSPi12_
- { 1379, 3, 1, 128, "t2SUBrSPi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1379 = t2SUBrSPi_
- { 1380, 7, 1, 90, "t2SUBrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1380 = t2SUBrSPs
- { 1381, 4, 1, 128, "t2SUBrSPs_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo128 }, // Inst #1381 = t2SUBrSPs_
- { 1382, 6, 1, 88, "t2SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1382 = t2SUBri
- { 1383, 6, 1, 88, "t2SUBri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1383 = t2SUBri12
- { 1384, 6, 1, 89, "t2SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1384 = t2SUBrr
- { 1385, 7, 1, 90, "t2SUBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1385 = t2SUBrs
- { 1386, 5, 1, 89, "t2SXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1386 = t2SXTABrr
- { 1387, 6, 1, 91, "t2SXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1387 = t2SXTABrr_rot
- { 1388, 5, 1, 89, "t2SXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1388 = t2SXTAHrr
- { 1389, 6, 1, 91, "t2SXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1389 = t2SXTAHrr_rot
- { 1390, 4, 1, 125, "t2SXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1390 = t2SXTBr
- { 1391, 5, 1, 126, "t2SXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1391 = t2SXTBr_rot
- { 1392, 4, 1, 125, "t2SXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1392 = t2SXTHr
- { 1393, 5, 1, 126, "t2SXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1393 = t2SXTHr_rot
- { 1394, 3, 0, 0, "t2TBB", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1394 = t2TBB
- { 1395, 3, 0, 0, "t2TBH", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1395 = t2TBH
- { 1396, 4, 0, 97, "t2TEQri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1396 = t2TEQri
- { 1397, 4, 0, 98, "t2TEQrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1397 = t2TEQrr
- { 1398, 5, 0, 99, "t2TEQrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1398 = t2TEQrs
- { 1399, 0, 0, 0, "t2TPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList7, Barriers1, 0 }, // Inst #1399 = t2TPsoft
- { 1400, 4, 0, 97, "t2TSTri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1400 = t2TSTri
- { 1401, 4, 0, 98, "t2TSTrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1401 = t2TSTrr
- { 1402, 5, 0, 99, "t2TSTrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1402 = t2TSTrs
- { 1403, 6, 1, 88, "t2UBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #1403 = t2UBFX
- { 1404, 6, 2, 110, "t2UMAAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1404 = t2UMAAL
- { 1405, 6, 2, 110, "t2UMLAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1405 = t2UMLAL
- { 1406, 6, 2, 117, "t2UMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1406 = t2UMULL
- { 1407, 5, 1, 89, "t2UXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1407 = t2UXTABrr
- { 1408, 6, 1, 91, "t2UXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1408 = t2UXTABrr_rot
- { 1409, 5, 1, 89, "t2UXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1409 = t2UXTAHrr
- { 1410, 6, 1, 91, "t2UXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1410 = t2UXTAHrr_rot
- { 1411, 4, 1, 125, "t2UXTB16r", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1411 = t2UXTB16r
- { 1412, 5, 1, 126, "t2UXTB16r_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1412 = t2UXTB16r_rot
- { 1413, 4, 1, 125, "t2UXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1413 = t2UXTBr
- { 1414, 5, 1, 126, "t2UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1414 = t2UXTBr_rot
- { 1415, 4, 1, 125, "t2UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1415 = t2UXTHr
- { 1416, 5, 1, 126, "t2UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1416 = t2UXTHr_rot
- { 1417, 6, 2, 89, "tADC", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo136 }, // Inst #1417 = tADC
- { 1418, 5, 1, 89, "tADDhirr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #1418 = tADDhirr
- { 1419, 6, 2, 88, "tADDi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1419 = tADDi3
- { 1420, 6, 2, 88, "tADDi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo138 }, // Inst #1420 = tADDi8
- { 1421, 2, 1, 88, "tADDrPCi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo139 }, // Inst #1421 = tADDrPCi
- { 1422, 3, 1, 89, "tADDrSP", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo140 }, // Inst #1422 = tADDrSP
- { 1423, 3, 1, 88, "tADDrSPi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo141 }, // Inst #1423 = tADDrSPi
- { 1424, 6, 2, 89, "tADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo142 }, // Inst #1424 = tADDrr
- { 1425, 3, 1, 88, "tADDspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1425 = tADDspi
- { 1426, 3, 1, 89, "tADDspr", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo140 }, // Inst #1426 = tADDspr
- { 1427, 3, 1, 128, "tADDspr_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo3 }, // Inst #1427 = tADDspr_
- { 1428, 1, 0, 128, "tADJCALLSTACKDOWN", 0, 0|(1<<4), ImplicitList2, ImplicitList2, Barriers2, OperandInfo14 }, // Inst #1428 = tADJCALLSTACKDOWN
- { 1429, 2, 0, 128, "tADJCALLSTACKUP", 0, 0|(1<<4), ImplicitList2, ImplicitList2, Barriers2, OperandInfo129 }, // Inst #1429 = tADJCALLSTACKUP
- { 1430, 6, 2, 89, "tAND", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1430 = tAND
- { 1431, 3, 1, 128, "tANDsp", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, ImplicitList1, Barriers1, OperandInfo144 }, // Inst #1431 = tANDsp
- { 1432, 6, 2, 113, "tASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1432 = tASRri
- { 1433, 6, 2, 114, "tASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1433 = tASRrr
- { 1434, 1, 0, 0, "tB", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1434 = tB
- { 1435, 6, 2, 89, "tBIC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1435 = tBIC
- { 1436, 1, 0, 0, "tBL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers3, OperandInfo14 }, // Inst #1436 = tBL
- { 1437, 1, 0, 0, "tBLXi", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers3, OperandInfo14 }, // Inst #1437 = tBLXi
- { 1438, 1, 0, 0, "tBLXi_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers3, OperandInfo14 }, // Inst #1438 = tBLXi_r9
- { 1439, 1, 0, 0, "tBLXr", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList3, Barriers3, OperandInfo16 }, // Inst #1439 = tBLXr
- { 1440, 1, 0, 0, "tBLXr_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList4, Barriers3, OperandInfo16 }, // Inst #1440 = tBLXr_r9
- { 1441, 1, 0, 0, "tBLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers3, OperandInfo14 }, // Inst #1441 = tBLr9
- { 1442, 1, 0, 0, "tBRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #1442 = tBRIND
- { 1443, 3, 0, 0, "tBR_JTr", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo145 }, // Inst #1443 = tBR_JTr
- { 1444, 1, 0, 0, "tBX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers3, OperandInfo146 }, // Inst #1444 = tBX
- { 1445, 0, 0, 0, "tBX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 }, // Inst #1445 = tBX_RET
- { 1446, 1, 0, 0, "tBX_RET_vararg", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo146 }, // Inst #1446 = tBX_RET_vararg
- { 1447, 1, 0, 0, "tBXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers3, OperandInfo146 }, // Inst #1447 = tBXr9
- { 1448, 3, 0, 0, "tBcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1448 = tBcc
- { 1449, 1, 0, 0, "tBfar", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, ImplicitList8, NULL, OperandInfo14 }, // Inst #1449 = tBfar
- { 1450, 2, 0, 0, "tCBNZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo139 }, // Inst #1450 = tCBNZ
- { 1451, 2, 0, 0, "tCBZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo139 }, // Inst #1451 = tCBZ
- { 1452, 4, 0, 98, "tCMN", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo147 }, // Inst #1452 = tCMN
- { 1453, 4, 0, 98, "tCMNz", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo147 }, // Inst #1453 = tCMNz
- { 1454, 4, 0, 98, "tCMPhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1454 = tCMPhir
- { 1455, 4, 0, 97, "tCMPi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo148 }, // Inst #1455 = tCMPi8
- { 1456, 4, 0, 98, "tCMPr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo147 }, // Inst #1456 = tCMPr
- { 1457, 4, 0, 98, "tCMPzhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1457 = tCMPzhir
- { 1458, 4, 0, 97, "tCMPzi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo148 }, // Inst #1458 = tCMPzi8
- { 1459, 4, 0, 98, "tCMPzr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo147 }, // Inst #1459 = tCMPzr
- { 1460, 6, 2, 89, "tEOR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1460 = tEOR
- { 1461, 1, 0, 128, "tInt_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList9, Barriers5, OperandInfo16 }, // Inst #1461 = tInt_eh_sjlj_setjmp
- { 1462, 5, 0, 103, "tLDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1462 = tLDM
- { 1463, 6, 1, 104, "tLDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1463 = tLDR
- { 1464, 6, 1, 104, "tLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1464 = tLDRB
- { 1465, 6, 1, 104, "tLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1465 = tLDRH
- { 1466, 5, 1, 104, "tLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1466 = tLDRSB
- { 1467, 5, 1, 104, "tLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1467 = tLDRSH
- { 1468, 4, 1, 101, "tLDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1468 = tLDRcp
- { 1469, 4, 1, 101, "tLDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1469 = tLDRpci
- { 1470, 3, 1, 128, "tLDRpci_pic", 0|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo19 }, // Inst #1470 = tLDRpci_pic
- { 1471, 5, 1, 101, "tLDRspi", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1471 = tLDRspi
- { 1472, 4, 1, 88, "tLEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1472 = tLEApcrel
- { 1473, 5, 1, 88, "tLEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo152 }, // Inst #1473 = tLEApcrelJT
- { 1474, 6, 2, 113, "tLSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1474 = tLSLri
- { 1475, 6, 2, 114, "tLSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1475 = tLSLrr
- { 1476, 6, 2, 113, "tLSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1476 = tLSRri
- { 1477, 6, 2, 114, "tLSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1477 = tLSRrr
- { 1478, 5, 1, 93, "tMOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1478 = tMOVCCi
- { 1479, 5, 1, 94, "tMOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #1479 = tMOVCCr
- { 1480, 5, 1, 128, "tMOVCCr_pseudo", 0|(1<<TID::Predicable)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo150 }, // Inst #1480 = tMOVCCr_pseudo
- { 1481, 2, 1, 112, "tMOVSr", 0, 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo153 }, // Inst #1481 = tMOVSr
- { 1482, 2, 1, 112, "tMOVgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo132 }, // Inst #1482 = tMOVgpr2gpr
- { 1483, 2, 1, 112, "tMOVgpr2tgpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1483 = tMOVgpr2tgpr
- { 1484, 5, 2, 111, "tMOVi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo155 }, // Inst #1484 = tMOVi8
- { 1485, 2, 1, 112, "tMOVr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo153 }, // Inst #1485 = tMOVr
- { 1486, 2, 1, 112, "tMOVtgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1486 = tMOVtgpr2gpr
- { 1487, 6, 2, 116, "tMUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1487 = tMUL
- { 1488, 5, 2, 112, "tMVN", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1488 = tMVN
- { 1489, 6, 2, 89, "tORR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1489 = tORR
- { 1490, 3, 1, 89, "tPICADD", 0|(1<<TID::NotDuplicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1490 = tPICADD
- { 1491, 3, 0, 0, "tPOP", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, Barriers2, OperandInfo158 }, // Inst #1491 = tPOP
- { 1492, 3, 0, 0, "tPOP_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo158 }, // Inst #1492 = tPOP_RET
- { 1493, 3, 0, 0, "tPUSH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, Barriers2, OperandInfo158 }, // Inst #1493 = tPUSH
- { 1494, 4, 1, 125, "tREV", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1494 = tREV
- { 1495, 4, 1, 125, "tREV16", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1495 = tREV16
- { 1496, 4, 1, 125, "tREVSH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1496 = tREVSH
- { 1497, 6, 2, 114, "tROR", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1497 = tROR
- { 1498, 5, 2, 88, "tRSB", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1498 = tRSB
- { 1499, 5, 1, 101, "tRestore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1499 = tRestore
- { 1500, 6, 2, 89, "tSBC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo136 }, // Inst #1500 = tSBC
- { 1501, 5, 0, 120, "tSTM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1501 = tSTM
- { 1502, 6, 0, 121, "tSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1502 = tSTR
- { 1503, 6, 0, 121, "tSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1503 = tSTRB
+ { 11, 0, 0, 128, "DEBUG_VALUE", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, 0 }, // Inst #11 = DEBUG_VALUE
+ { 12, 3, 1, 88, "ADCSSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #12 = ADCSSri
+ { 13, 3, 1, 89, "ADCSSrr", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #13 = ADCSSrr
+ { 14, 5, 1, 91, "ADCSSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #14 = ADCSSrs
+ { 15, 6, 1, 88, "ADCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #15 = ADCri
+ { 16, 6, 1, 89, "ADCrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #16 = ADCrr
+ { 17, 8, 1, 91, "ADCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #17 = ADCrs
+ { 18, 5, 1, 88, "ADDSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #18 = ADDSri
+ { 19, 5, 1, 89, "ADDSrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #19 = ADDSrr
+ { 20, 7, 1, 91, "ADDSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #20 = ADDSrs
+ { 21, 6, 1, 88, "ADDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #21 = ADDri
+ { 22, 6, 1, 89, "ADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #22 = ADDrr
+ { 23, 8, 1, 91, "ADDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #23 = ADDrs
+ { 24, 3, 0, 128, "ADJCALLSTACKDOWN", 0|(1<<TID::Predicable), 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo11 }, // Inst #24 = ADJCALLSTACKDOWN
+ { 25, 4, 0, 128, "ADJCALLSTACKUP", 0|(1<<TID::Predicable), 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo12 }, // Inst #25 = ADJCALLSTACKUP
+ { 26, 6, 1, 88, "ANDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #26 = ANDri
+ { 27, 6, 1, 89, "ANDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #27 = ANDrr
+ { 28, 8, 1, 91, "ANDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #28 = ANDrs
+ { 29, 4, 1, 128, "ATOMIC_CMP_SWAP_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #29 = ATOMIC_CMP_SWAP_I16
+ { 30, 4, 1, 128, "ATOMIC_CMP_SWAP_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #30 = ATOMIC_CMP_SWAP_I32
+ { 31, 4, 1, 128, "ATOMIC_CMP_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #31 = ATOMIC_CMP_SWAP_I8
+ { 32, 3, 1, 128, "ATOMIC_LOAD_ADD_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #32 = ATOMIC_LOAD_ADD_I16
+ { 33, 3, 1, 128, "ATOMIC_LOAD_ADD_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #33 = ATOMIC_LOAD_ADD_I32
+ { 34, 3, 1, 128, "ATOMIC_LOAD_ADD_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #34 = ATOMIC_LOAD_ADD_I8
+ { 35, 3, 1, 128, "ATOMIC_LOAD_AND_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #35 = ATOMIC_LOAD_AND_I16
+ { 36, 3, 1, 128, "ATOMIC_LOAD_AND_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #36 = ATOMIC_LOAD_AND_I32
+ { 37, 3, 1, 128, "ATOMIC_LOAD_AND_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #37 = ATOMIC_LOAD_AND_I8
+ { 38, 3, 1, 128, "ATOMIC_LOAD_NAND_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #38 = ATOMIC_LOAD_NAND_I16
+ { 39, 3, 1, 128, "ATOMIC_LOAD_NAND_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #39 = ATOMIC_LOAD_NAND_I32
+ { 40, 3, 1, 128, "ATOMIC_LOAD_NAND_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #40 = ATOMIC_LOAD_NAND_I8
+ { 41, 3, 1, 128, "ATOMIC_LOAD_OR_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #41 = ATOMIC_LOAD_OR_I16
+ { 42, 3, 1, 128, "ATOMIC_LOAD_OR_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #42 = ATOMIC_LOAD_OR_I32
+ { 43, 3, 1, 128, "ATOMIC_LOAD_OR_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #43 = ATOMIC_LOAD_OR_I8
+ { 44, 3, 1, 128, "ATOMIC_LOAD_SUB_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #44 = ATOMIC_LOAD_SUB_I16
+ { 45, 3, 1, 128, "ATOMIC_LOAD_SUB_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #45 = ATOMIC_LOAD_SUB_I32
+ { 46, 3, 1, 128, "ATOMIC_LOAD_SUB_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #46 = ATOMIC_LOAD_SUB_I8
+ { 47, 3, 1, 128, "ATOMIC_LOAD_XOR_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #47 = ATOMIC_LOAD_XOR_I16
+ { 48, 3, 1, 128, "ATOMIC_LOAD_XOR_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #48 = ATOMIC_LOAD_XOR_I32
+ { 49, 3, 1, 128, "ATOMIC_LOAD_XOR_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #49 = ATOMIC_LOAD_XOR_I8
+ { 50, 3, 1, 128, "ATOMIC_SWAP_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #50 = ATOMIC_SWAP_I16
+ { 51, 3, 1, 128, "ATOMIC_SWAP_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #51 = ATOMIC_SWAP_I32
+ { 52, 3, 1, 128, "ATOMIC_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0|(1<<4), ImplicitList1, NULL, NULL, OperandInfo3 }, // Inst #52 = ATOMIC_SWAP_I8
+ { 53, 1, 0, 0, "B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #53 = B
+ { 54, 5, 1, 126, "BFC", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #54 = BFC
+ { 55, 6, 1, 88, "BICri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #55 = BICri
+ { 56, 6, 1, 89, "BICrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #56 = BICrr
+ { 57, 8, 1, 91, "BICrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #57 = BICrs
+ { 58, 1, 0, 0, "BL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #58 = BL
+ { 59, 1, 0, 0, "BLX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(3<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #59 = BLX
+ { 60, 1, 0, 0, "BLXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(3<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #60 = BLXr9
+ { 61, 3, 0, 0, "BL_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers2, OperandInfo11 }, // Inst #61 = BL_pred
+ { 62, 1, 0, 0, "BLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #62 = BLr9
+ { 63, 3, 0, 0, "BLr9_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers2, OperandInfo11 }, // Inst #63 = BLr9_pred
+ { 64, 1, 0, 0, "BRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #64 = BRIND
+ { 65, 4, 0, 0, "BR_JTadd", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo17 }, // Inst #65 = BR_JTadd
+ { 66, 5, 0, 0, "BR_JTm", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo18 }, // Inst #66 = BR_JTm
+ { 67, 3, 0, 0, "BR_JTr", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo19 }, // Inst #67 = BR_JTr
+ { 68, 1, 0, 0, "BX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #68 = BX
+ { 69, 2, 0, 0, "BX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo20 }, // Inst #69 = BX_RET
+ { 70, 1, 0, 0, "BXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #70 = BXr9
+ { 71, 3, 0, 0, "Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #71 = Bcc
+ { 72, 4, 1, 125, "CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #72 = CLZ
+ { 73, 4, 0, 97, "CMNzri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #73 = CMNzri
+ { 74, 4, 0, 98, "CMNzrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #74 = CMNzrr
+ { 75, 6, 0, 100, "CMNzrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #75 = CMNzrs
+ { 76, 4, 0, 97, "CMPri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #76 = CMPri
+ { 77, 4, 0, 98, "CMPrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #77 = CMPrr
+ { 78, 6, 0, 100, "CMPrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #78 = CMPrs
+ { 79, 4, 0, 97, "CMPzri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #79 = CMPzri
+ { 80, 4, 0, 98, "CMPzrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #80 = CMPzrr
+ { 81, 6, 0, 100, "CMPzrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #81 = CMPzrs
+ { 82, 3, 0, 128, "CONSTPOOL_ENTRY", 0|(1<<TID::NotDuplicable), 0|(1<<4), NULL, NULL, NULL, OperandInfo24 }, // Inst #82 = CONSTPOOL_ENTRY
+ { 83, 6, 1, 88, "EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #83 = EORri
+ { 84, 6, 1, 89, "EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #84 = EORrr
+ { 85, 8, 1, 91, "EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #85 = EORrs
+ { 86, 4, 1, 26, "FCONSTD", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(3<<4)|(22<<9)|(1<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #86 = FCONSTD
+ { 87, 4, 1, 26, "FCONSTS", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(3<<4)|(22<<9)|(1<<17), NULL, NULL, NULL, OperandInfo26 }, // Inst #87 = FCONSTS
+ { 88, 2, 0, 82, "FMSTAT", 0|(1<<TID::Predicable), 0|(3<<4)|(22<<9)|(1<<17), ImplicitList5, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #88 = FMSTAT
+ { 89, 1, 0, 128, "Int_MemBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 }, // Inst #89 = Int_MemBarrierV6
+ { 90, 0, 0, 128, "Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #90 = Int_MemBarrierV7
+ { 91, 1, 0, 128, "Int_SyncBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 }, // Inst #91 = Int_SyncBarrierV6
+ { 92, 0, 0, 128, "Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #92 = Int_SyncBarrierV7
+ { 93, 1, 0, 128, "Int_eh_sjlj_setjmp", 0, 0|(1<<4), NULL, ImplicitList6, Barriers3, OperandInfo16 }, // Inst #93 = Int_eh_sjlj_setjmp
+ { 94, 5, 0, 103, "LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #94 = LDM
+ { 95, 5, 0, 0, "LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #95 = LDM_RET
+ { 96, 6, 1, 104, "LDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #96 = LDR
+ { 97, 6, 1, 104, "LDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #97 = LDRB
+ { 98, 7, 2, 105, "LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #98 = LDRB_POST
+ { 99, 7, 2, 105, "LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(1<<7)|(6<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #99 = LDRB_PRE
+ { 100, 7, 2, 104, "LDRD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo10 }, // Inst #100 = LDRD
+ { 101, 4, 1, 128, "LDREX", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #101 = LDREX
+ { 102, 4, 1, 128, "LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #102 = LDREXB
+ { 103, 5, 2, 128, "LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #103 = LDREXD
+ { 104, 4, 1, 128, "LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #104 = LDREXH
+ { 105, 6, 1, 104, "LDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #105 = LDRH
+ { 106, 7, 2, 105, "LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #106 = LDRH_POST
+ { 107, 7, 2, 105, "LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #107 = LDRH_PRE
+ { 108, 6, 1, 104, "LDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #108 = LDRSB
+ { 109, 7, 2, 105, "LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #109 = LDRSB_POST
+ { 110, 7, 2, 105, "LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #110 = LDRSB_PRE
+ { 111, 6, 1, 104, "LDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #111 = LDRSH
+ { 112, 7, 2, 105, "LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #112 = LDRSH_POST
+ { 113, 7, 2, 105, "LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #113 = LDRSH_PRE
+ { 114, 7, 2, 105, "LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #114 = LDR_POST
+ { 115, 7, 2, 105, "LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(1<<7)|(6<<9), NULL, NULL, NULL, OperandInfo29 }, // Inst #115 = LDR_PRE
+ { 116, 6, 1, 104, "LDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #116 = LDRcp
+ { 117, 4, 1, 88, "LEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo22 }, // Inst #117 = LEApcrel
+ { 118, 5, 1, 88, "LEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo30 }, // Inst #118 = LEApcrelJT
+ { 119, 7, 1, 109, "MLA", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #119 = MLA
+ { 120, 6, 1, 109, "MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #120 = MLS
+ { 121, 5, 1, 93, "MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo15 }, // Inst #121 = MOVCCi
+ { 122, 5, 1, 94, "MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo33 }, // Inst #122 = MOVCCr
+ { 123, 7, 1, 96, "MOVCCs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo34 }, // Inst #123 = MOVCCs
+ { 124, 5, 1, 111, "MOVTi16", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo15 }, // Inst #124 = MOVTi16
+ { 125, 5, 1, 111, "MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo35 }, // Inst #125 = MOVi
+ { 126, 4, 1, 111, "MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #126 = MOVi16
+ { 127, 4, 1, 111, "MOVi2pieces", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|1|(2<<4), NULL, NULL, NULL, OperandInfo22 }, // Inst #127 = MOVi2pieces
+ { 128, 4, 1, 111, "MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|1|(2<<4), NULL, NULL, NULL, OperandInfo22 }, // Inst #128 = MOVi32imm
+ { 129, 5, 1, 112, "MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo36 }, // Inst #129 = MOVr
+ { 130, 5, 1, 113, "MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(1<<15), ImplicitList1, NULL, NULL, OperandInfo36 }, // Inst #130 = MOVrx
+ { 131, 7, 1, 114, "MOVs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo37 }, // Inst #131 = MOVs
+ { 132, 4, 1, 113, "MOVsra_flag", 0|(1<<TID::Predicable), 0|1|(3<<4)|(1<<15), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #132 = MOVsra_flag
+ { 133, 4, 1, 113, "MOVsrl_flag", 0|(1<<TID::Predicable), 0|1|(3<<4)|(1<<15), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #133 = MOVsrl_flag
+ { 134, 6, 1, 116, "MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #134 = MUL
+ { 135, 5, 1, 111, "MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo35 }, // Inst #135 = MVNi
+ { 136, 5, 1, 112, "MVNr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo36 }, // Inst #136 = MVNr
+ { 137, 7, 1, 114, "MVNs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo37 }, // Inst #137 = MVNs
+ { 138, 6, 1, 88, "ORRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #138 = ORRri
+ { 139, 6, 1, 89, "ORRrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #139 = ORRrr
+ { 140, 8, 1, 91, "ORRrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #140 = ORRrs
+ { 141, 5, 1, 89, "PICADD", 0|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #141 = PICADD
+ { 142, 5, 1, 104, "PICLDR", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #142 = PICLDR
+ { 143, 5, 1, 104, "PICLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #143 = PICLDRB
+ { 144, 5, 1, 104, "PICLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #144 = PICLDRH
+ { 145, 5, 1, 104, "PICLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #145 = PICLDRSB
+ { 146, 5, 1, 104, "PICLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #146 = PICLDRSH
+ { 147, 5, 0, 121, "PICSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #147 = PICSTR
+ { 148, 5, 0, 121, "PICSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #148 = PICSTRB
+ { 149, 5, 0, 121, "PICSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #149 = PICSTRH
+ { 150, 6, 1, 90, "PKHBT", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #150 = PKHBT
+ { 151, 6, 1, 90, "PKHTB", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #151 = PKHTB
+ { 152, 4, 1, 125, "RBIT", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #152 = RBIT
+ { 153, 4, 1, 125, "REV", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #153 = REV
+ { 154, 4, 1, 125, "REV16", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #154 = REV16
+ { 155, 4, 1, 125, "REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #155 = REVSH
+ { 156, 5, 1, 88, "RSBSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #156 = RSBSri
+ { 157, 7, 1, 91, "RSBSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #157 = RSBSrs
+ { 158, 6, 1, 88, "RSBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #158 = RSBri
+ { 159, 8, 1, 91, "RSBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #159 = RSBrs
+ { 160, 3, 1, 88, "RSCSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #160 = RSCSri
+ { 161, 5, 1, 91, "RSCSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #161 = RSCSrs
+ { 162, 6, 1, 88, "RSCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #162 = RSCri
+ { 163, 8, 1, 91, "RSCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #163 = RSCrs
+ { 164, 3, 1, 88, "SBCSSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #164 = SBCSSri
+ { 165, 3, 1, 89, "SBCSSrr", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #165 = SBCSSrr
+ { 166, 5, 1, 91, "SBCSSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #166 = SBCSSrs
+ { 167, 6, 1, 88, "SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #167 = SBCri
+ { 168, 6, 1, 89, "SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #168 = SBCrr
+ { 169, 8, 1, 91, "SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #169 = SBCrs
+ { 170, 6, 1, 88, "SBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #170 = SBFX
+ { 171, 6, 1, 108, "SMLABB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #171 = SMLABB
+ { 172, 6, 1, 108, "SMLABT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #172 = SMLABT
+ { 173, 7, 2, 110, "SMLAL", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #173 = SMLAL
+ { 174, 6, 1, 108, "SMLATB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #174 = SMLATB
+ { 175, 6, 1, 108, "SMLATT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #175 = SMLATT
+ { 176, 6, 1, 108, "SMLAWB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #176 = SMLAWB
+ { 177, 6, 1, 108, "SMLAWT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #177 = SMLAWT
+ { 178, 6, 1, 109, "SMMLA", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #178 = SMMLA
+ { 179, 6, 1, 109, "SMMLS", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #179 = SMMLS
+ { 180, 5, 1, 116, "SMMUL", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #180 = SMMUL
+ { 181, 5, 1, 116, "SMULBB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #181 = SMULBB
+ { 182, 5, 1, 116, "SMULBT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #182 = SMULBT
+ { 183, 7, 2, 117, "SMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #183 = SMULL
+ { 184, 5, 1, 116, "SMULTB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #184 = SMULTB
+ { 185, 5, 1, 116, "SMULTT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #185 = SMULTT
+ { 186, 5, 1, 115, "SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #186 = SMULWB
+ { 187, 5, 1, 115, "SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #187 = SMULWT
+ { 188, 5, 0, 120, "STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #188 = STM
+ { 189, 6, 0, 121, "STR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(7<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #189 = STR
+ { 190, 6, 0, 121, "STRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(7<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #190 = STRB
+ { 191, 7, 1, 122, "STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #191 = STRB_POST
+ { 192, 7, 1, 122, "STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #192 = STRB_PRE
+ { 193, 7, 0, 121, "STRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo10 }, // Inst #193 = STRD
+ { 194, 5, 1, 128, "STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #194 = STREX
+ { 195, 5, 1, 128, "STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #195 = STREXB
+ { 196, 6, 1, 128, "STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo41 }, // Inst #196 = STREXD
+ { 197, 5, 1, 128, "STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #197 = STREXH
+ { 198, 6, 0, 121, "STRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #198 = STRH
+ { 199, 7, 1, 122, "STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(2<<7)|(9<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #199 = STRH_POST
+ { 200, 7, 1, 122, "STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(1<<7)|(9<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #200 = STRH_PRE
+ { 201, 7, 1, 122, "STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #201 = STR_POST
+ { 202, 7, 1, 122, "STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #202 = STR_PRE
+ { 203, 5, 1, 88, "SUBSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #203 = SUBSri
+ { 204, 5, 1, 89, "SUBSrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #204 = SUBSrr
+ { 205, 7, 1, 91, "SUBSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #205 = SUBSrs
+ { 206, 6, 1, 88, "SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #206 = SUBri
+ { 207, 6, 1, 89, "SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #207 = SUBrr
+ { 208, 8, 1, 91, "SUBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #208 = SUBrs
+ { 209, 5, 1, 89, "SXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #209 = SXTABrr
+ { 210, 6, 1, 90, "SXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #210 = SXTABrr_rot
+ { 211, 5, 1, 89, "SXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #211 = SXTAHrr
+ { 212, 6, 1, 90, "SXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #212 = SXTAHrr_rot
+ { 213, 4, 1, 125, "SXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #213 = SXTBr
+ { 214, 5, 1, 126, "SXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #214 = SXTBr_rot
+ { 215, 4, 1, 125, "SXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #215 = SXTHr
+ { 216, 5, 1, 126, "SXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #216 = SXTHr_rot
+ { 217, 4, 0, 97, "TEQri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #217 = TEQri
+ { 218, 4, 0, 98, "TEQrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #218 = TEQrr
+ { 219, 6, 0, 100, "TEQrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #219 = TEQrs
+ { 220, 0, 0, 0, "TPsoft", 0|(1<<TID::Call), 0|(3<<4)|(2<<9), NULL, ImplicitList7, Barriers1, 0 }, // Inst #220 = TPsoft
+ { 221, 4, 0, 97, "TSTri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #221 = TSTri
+ { 222, 4, 0, 98, "TSTrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #222 = TSTrr
+ { 223, 6, 0, 100, "TSTrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #223 = TSTrs
+ { 224, 6, 1, 88, "UBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #224 = UBFX
+ { 225, 6, 2, 110, "UMAAL", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #225 = UMAAL
+ { 226, 7, 2, 110, "UMLAL", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #226 = UMLAL
+ { 227, 7, 2, 117, "UMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo31 }, // Inst #227 = UMULL
+ { 228, 5, 1, 89, "UXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #228 = UXTABrr
+ { 229, 6, 1, 90, "UXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #229 = UXTABrr_rot
+ { 230, 5, 1, 89, "UXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #230 = UXTAHrr
+ { 231, 6, 1, 90, "UXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #231 = UXTAHrr_rot
+ { 232, 4, 1, 125, "UXTB16r", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #232 = UXTB16r
+ { 233, 5, 1, 126, "UXTB16r_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #233 = UXTB16r_rot
+ { 234, 4, 1, 125, "UXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #234 = UXTBr
+ { 235, 5, 1, 126, "UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #235 = UXTBr_rot
+ { 236, 4, 1, 125, "UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #236 = UXTHr
+ { 237, 5, 1, 126, "UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #237 = UXTHr_rot
+ { 238, 6, 1, 17, "VABALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #238 = VABALsv2i64
+ { 239, 6, 1, 17, "VABALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #239 = VABALsv4i32
+ { 240, 6, 1, 17, "VABALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #240 = VABALsv8i16
+ { 241, 6, 1, 17, "VABALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #241 = VABALuv2i64
+ { 242, 6, 1, 17, "VABALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #242 = VABALuv4i32
+ { 243, 6, 1, 17, "VABALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #243 = VABALuv8i16
+ { 244, 6, 1, 18, "VABAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #244 = VABAsv16i8
+ { 245, 6, 1, 19, "VABAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #245 = VABAsv2i32
+ { 246, 6, 1, 17, "VABAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #246 = VABAsv4i16
+ { 247, 6, 1, 20, "VABAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #247 = VABAsv4i32
+ { 248, 6, 1, 18, "VABAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #248 = VABAsv8i16
+ { 249, 6, 1, 17, "VABAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #249 = VABAsv8i8
+ { 250, 6, 1, 18, "VABAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #250 = VABAuv16i8
+ { 251, 6, 1, 19, "VABAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #251 = VABAuv2i32
+ { 252, 6, 1, 17, "VABAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #252 = VABAuv4i16
+ { 253, 6, 1, 20, "VABAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #253 = VABAuv4i32
+ { 254, 6, 1, 18, "VABAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #254 = VABAuv8i16
+ { 255, 6, 1, 17, "VABAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #255 = VABAuv8i8
+ { 256, 5, 1, 4, "VABDLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #256 = VABDLsv2i64
+ { 257, 5, 1, 4, "VABDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #257 = VABDLsv4i32
+ { 258, 5, 1, 4, "VABDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #258 = VABDLsv8i16
+ { 259, 5, 1, 4, "VABDLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #259 = VABDLuv2i64
+ { 260, 5, 1, 4, "VABDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #260 = VABDLuv4i32
+ { 261, 5, 1, 4, "VABDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #261 = VABDLuv8i16
+ { 262, 5, 1, 1, "VABDfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #262 = VABDfd
+ { 263, 5, 1, 2, "VABDfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #263 = VABDfq
+ { 264, 5, 1, 4, "VABDsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #264 = VABDsv16i8
+ { 265, 5, 1, 3, "VABDsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #265 = VABDsv2i32
+ { 266, 5, 1, 3, "VABDsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #266 = VABDsv4i16
+ { 267, 5, 1, 4, "VABDsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #267 = VABDsv4i32
+ { 268, 5, 1, 4, "VABDsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #268 = VABDsv8i16
+ { 269, 5, 1, 3, "VABDsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #269 = VABDsv8i8
+ { 270, 5, 1, 4, "VABDuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #270 = VABDuv16i8
+ { 271, 5, 1, 3, "VABDuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #271 = VABDuv2i32
+ { 272, 5, 1, 3, "VABDuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #272 = VABDuv4i16
+ { 273, 5, 1, 4, "VABDuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #273 = VABDuv4i32
+ { 274, 5, 1, 4, "VABDuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #274 = VABDuv8i16
+ { 275, 5, 1, 3, "VABDuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #275 = VABDuv8i8
+ { 276, 4, 1, 87, "VABSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #276 = VABSD
+ { 277, 4, 1, 86, "VABSS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #277 = VABSS
+ { 278, 4, 1, 57, "VABSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #278 = VABSfd
+ { 279, 4, 1, 57, "VABSfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #279 = VABSfd_sfp
+ { 280, 4, 1, 58, "VABSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #280 = VABSfq
+ { 281, 4, 1, 60, "VABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #281 = VABSv16i8
+ { 282, 4, 1, 59, "VABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #282 = VABSv2i32
+ { 283, 4, 1, 59, "VABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #283 = VABSv4i16
+ { 284, 4, 1, 60, "VABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #284 = VABSv4i32
+ { 285, 4, 1, 60, "VABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #285 = VABSv8i16
+ { 286, 4, 1, 59, "VABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #286 = VABSv8i8
+ { 287, 5, 1, 1, "VACGEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #287 = VACGEd
+ { 288, 5, 1, 2, "VACGEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #288 = VACGEq
+ { 289, 5, 1, 1, "VACGTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #289 = VACGTd
+ { 290, 5, 1, 2, "VACGTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #290 = VACGTq
+ { 291, 5, 1, 62, "VADDD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #291 = VADDD
+ { 292, 5, 1, 3, "VADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #292 = VADDHNv2i32
+ { 293, 5, 1, 3, "VADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #293 = VADDHNv4i16
+ { 294, 5, 1, 3, "VADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #294 = VADDHNv8i8
+ { 295, 5, 1, 44, "VADDLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #295 = VADDLsv2i64
+ { 296, 5, 1, 44, "VADDLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #296 = VADDLsv4i32
+ { 297, 5, 1, 44, "VADDLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #297 = VADDLsv8i16
+ { 298, 5, 1, 44, "VADDLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #298 = VADDLuv2i64
+ { 299, 5, 1, 44, "VADDLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #299 = VADDLuv4i32
+ { 300, 5, 1, 44, "VADDLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #300 = VADDLuv8i16
+ { 301, 5, 1, 61, "VADDS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #301 = VADDS
+ { 302, 5, 1, 47, "VADDWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #302 = VADDWsv2i64
+ { 303, 5, 1, 47, "VADDWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #303 = VADDWsv4i32
+ { 304, 5, 1, 47, "VADDWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #304 = VADDWsv8i16
+ { 305, 5, 1, 47, "VADDWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #305 = VADDWuv2i64
+ { 306, 5, 1, 47, "VADDWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #306 = VADDWuv4i32
+ { 307, 5, 1, 47, "VADDWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #307 = VADDWuv8i16
+ { 308, 5, 1, 1, "VADDfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #308 = VADDfd
+ { 309, 5, 1, 1, "VADDfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #309 = VADDfd_sfp
+ { 310, 5, 1, 2, "VADDfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #310 = VADDfq
+ { 311, 5, 1, 6, "VADDv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #311 = VADDv16i8
+ { 312, 5, 1, 5, "VADDv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #312 = VADDv1i64
+ { 313, 5, 1, 5, "VADDv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #313 = VADDv2i32
+ { 314, 5, 1, 6, "VADDv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #314 = VADDv2i64
+ { 315, 5, 1, 5, "VADDv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #315 = VADDv4i16
+ { 316, 5, 1, 6, "VADDv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #316 = VADDv4i32
+ { 317, 5, 1, 6, "VADDv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #317 = VADDv8i16
+ { 318, 5, 1, 5, "VADDv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #318 = VADDv8i8
+ { 319, 5, 1, 5, "VANDd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #319 = VANDd
+ { 320, 5, 1, 6, "VANDq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #320 = VANDq
+ { 321, 5, 1, 5, "VBICd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #321 = VBICd
+ { 322, 5, 1, 6, "VBICq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #322 = VBICq
+ { 323, 6, 1, 7, "VBSLd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #323 = VBSLd
+ { 324, 6, 1, 8, "VBSLq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #324 = VBSLq
+ { 325, 5, 1, 1, "VCEQfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #325 = VCEQfd
+ { 326, 5, 1, 2, "VCEQfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #326 = VCEQfq
+ { 327, 5, 1, 4, "VCEQv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #327 = VCEQv16i8
+ { 328, 5, 1, 3, "VCEQv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #328 = VCEQv2i32
+ { 329, 5, 1, 3, "VCEQv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #329 = VCEQv4i16
+ { 330, 5, 1, 4, "VCEQv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #330 = VCEQv4i32
+ { 331, 5, 1, 4, "VCEQv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #331 = VCEQv8i16
+ { 332, 5, 1, 3, "VCEQv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #332 = VCEQv8i8
+ { 333, 5, 1, 1, "VCGEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #333 = VCGEfd
+ { 334, 5, 1, 2, "VCGEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #334 = VCGEfq
+ { 335, 5, 1, 4, "VCGEsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #335 = VCGEsv16i8
+ { 336, 5, 1, 3, "VCGEsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #336 = VCGEsv2i32
+ { 337, 5, 1, 3, "VCGEsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #337 = VCGEsv4i16
+ { 338, 5, 1, 4, "VCGEsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #338 = VCGEsv4i32
+ { 339, 5, 1, 4, "VCGEsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #339 = VCGEsv8i16
+ { 340, 5, 1, 3, "VCGEsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #340 = VCGEsv8i8
+ { 341, 5, 1, 4, "VCGEuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #341 = VCGEuv16i8
+ { 342, 5, 1, 3, "VCGEuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #342 = VCGEuv2i32
+ { 343, 5, 1, 3, "VCGEuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #343 = VCGEuv4i16
+ { 344, 5, 1, 4, "VCGEuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #344 = VCGEuv4i32
+ { 345, 5, 1, 4, "VCGEuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #345 = VCGEuv8i16
+ { 346, 5, 1, 3, "VCGEuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #346 = VCGEuv8i8
+ { 347, 5, 1, 1, "VCGTfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #347 = VCGTfd
+ { 348, 5, 1, 2, "VCGTfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #348 = VCGTfq
+ { 349, 5, 1, 4, "VCGTsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #349 = VCGTsv16i8
+ { 350, 5, 1, 3, "VCGTsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #350 = VCGTsv2i32
+ { 351, 5, 1, 3, "VCGTsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #351 = VCGTsv4i16
+ { 352, 5, 1, 4, "VCGTsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #352 = VCGTsv4i32
+ { 353, 5, 1, 4, "VCGTsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #353 = VCGTsv8i16
+ { 354, 5, 1, 3, "VCGTsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #354 = VCGTsv8i8
+ { 355, 5, 1, 4, "VCGTuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #355 = VCGTuv16i8
+ { 356, 5, 1, 3, "VCGTuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #356 = VCGTuv2i32
+ { 357, 5, 1, 3, "VCGTuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #357 = VCGTuv4i16
+ { 358, 5, 1, 4, "VCGTuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #358 = VCGTuv4i32
+ { 359, 5, 1, 4, "VCGTuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #359 = VCGTuv8i16
+ { 360, 5, 1, 3, "VCGTuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #360 = VCGTuv8i8
+ { 361, 4, 1, 8, "VCLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #361 = VCLSv16i8
+ { 362, 4, 1, 7, "VCLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #362 = VCLSv2i32
+ { 363, 4, 1, 7, "VCLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #363 = VCLSv4i16
+ { 364, 4, 1, 8, "VCLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #364 = VCLSv4i32
+ { 365, 4, 1, 8, "VCLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #365 = VCLSv8i16
+ { 366, 4, 1, 7, "VCLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #366 = VCLSv8i8
+ { 367, 4, 1, 8, "VCLZv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #367 = VCLZv16i8
+ { 368, 4, 1, 7, "VCLZv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #368 = VCLZv2i32
+ { 369, 4, 1, 7, "VCLZv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #369 = VCLZv4i16
+ { 370, 4, 1, 8, "VCLZv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #370 = VCLZv4i32
+ { 371, 4, 1, 8, "VCLZv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #371 = VCLZv8i16
+ { 372, 4, 1, 7, "VCLZv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #372 = VCLZv8i8
+ { 373, 4, 0, 64, "VCMPED", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo49 }, // Inst #373 = VCMPED
+ { 374, 4, 0, 63, "VCMPES", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo50 }, // Inst #374 = VCMPES
+ { 375, 3, 0, 64, "VCMPEZD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo57 }, // Inst #375 = VCMPEZD
+ { 376, 3, 0, 63, "VCMPEZS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo58 }, // Inst #376 = VCMPEZS
+ { 377, 4, 1, 7, "VCNTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #377 = VCNTd
+ { 378, 4, 1, 8, "VCNTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #378 = VCNTq
+ { 379, 4, 1, 66, "VCVTDS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #379 = VCVTDS
+ { 380, 4, 1, 69, "VCVTSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #380 = VCVTSD
+ { 381, 4, 1, 57, "VCVTf2sd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #381 = VCVTf2sd
+ { 382, 4, 1, 57, "VCVTf2sd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #382 = VCVTf2sd_sfp
+ { 383, 4, 1, 58, "VCVTf2sq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #383 = VCVTf2sq
+ { 384, 4, 1, 57, "VCVTf2ud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #384 = VCVTf2ud
+ { 385, 4, 1, 57, "VCVTf2ud_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #385 = VCVTf2ud_sfp
+ { 386, 4, 1, 58, "VCVTf2uq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #386 = VCVTf2uq
+ { 387, 5, 1, 57, "VCVTf2xsd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #387 = VCVTf2xsd
+ { 388, 5, 1, 58, "VCVTf2xsq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #388 = VCVTf2xsq
+ { 389, 5, 1, 57, "VCVTf2xud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #389 = VCVTf2xud
+ { 390, 5, 1, 58, "VCVTf2xuq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #390 = VCVTf2xuq
+ { 391, 4, 1, 57, "VCVTs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #391 = VCVTs2fd
+ { 392, 4, 1, 57, "VCVTs2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #392 = VCVTs2fd_sfp
+ { 393, 4, 1, 58, "VCVTs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #393 = VCVTs2fq
+ { 394, 4, 1, 57, "VCVTu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #394 = VCVTu2fd
+ { 395, 4, 1, 57, "VCVTu2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #395 = VCVTu2fd_sfp
+ { 396, 4, 1, 58, "VCVTu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #396 = VCVTu2fq
+ { 397, 5, 1, 57, "VCVTxs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #397 = VCVTxs2fd
+ { 398, 5, 1, 58, "VCVTxs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #398 = VCVTxs2fq
+ { 399, 5, 1, 57, "VCVTxu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #399 = VCVTxu2fd
+ { 400, 5, 1, 58, "VCVTxu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #400 = VCVTxu2fq
+ { 401, 5, 1, 72, "VDIVD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #401 = VDIVD
+ { 402, 5, 1, 71, "VDIVS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #402 = VDIVS
+ { 403, 4, 1, 24, "VDUP16d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo63 }, // Inst #403 = VDUP16d
+ { 404, 4, 1, 24, "VDUP16q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo64 }, // Inst #404 = VDUP16q
+ { 405, 4, 1, 24, "VDUP32d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo63 }, // Inst #405 = VDUP32d
+ { 406, 4, 1, 24, "VDUP32q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo64 }, // Inst #406 = VDUP32q
+ { 407, 4, 1, 24, "VDUP8d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo63 }, // Inst #407 = VDUP8d
+ { 408, 4, 1, 24, "VDUP8q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo64 }, // Inst #408 = VDUP8q
+ { 409, 5, 1, 21, "VDUPLN16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #409 = VDUPLN16d
+ { 410, 5, 1, 21, "VDUPLN16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #410 = VDUPLN16q
+ { 411, 5, 1, 21, "VDUPLN32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #411 = VDUPLN32d
+ { 412, 5, 1, 21, "VDUPLN32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #412 = VDUPLN32q
+ { 413, 5, 1, 21, "VDUPLN8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #413 = VDUPLN8d
+ { 414, 5, 1, 21, "VDUPLN8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #414 = VDUPLN8q
+ { 415, 5, 1, 21, "VDUPLNfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #415 = VDUPLNfd
+ { 416, 5, 1, 21, "VDUPLNfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #416 = VDUPLNfq
+ { 417, 4, 1, 24, "VDUPfd", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo63 }, // Inst #417 = VDUPfd
+ { 418, 4, 1, 21, "VDUPfdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #418 = VDUPfdf
+ { 419, 4, 1, 24, "VDUPfq", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo64 }, // Inst #419 = VDUPfq
+ { 420, 4, 1, 21, "VDUPfqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #420 = VDUPfqf
+ { 421, 5, 1, 5, "VEORd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #421 = VEORd
+ { 422, 5, 1, 6, "VEORq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #422 = VEORq
+ { 423, 6, 1, 9, "VEXTd16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #423 = VEXTd16
+ { 424, 6, 1, 9, "VEXTd32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #424 = VEXTd32
+ { 425, 6, 1, 9, "VEXTd8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #425 = VEXTd8
+ { 426, 6, 1, 9, "VEXTdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #426 = VEXTdf
+ { 427, 6, 1, 10, "VEXTq16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #427 = VEXTq16
+ { 428, 6, 1, 10, "VEXTq32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #428 = VEXTq32
+ { 429, 6, 1, 10, "VEXTq8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #429 = VEXTq8
+ { 430, 6, 1, 10, "VEXTqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #430 = VEXTqf
+ { 431, 5, 1, 28, "VGETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo69 }, // Inst #431 = VGETLNi32
+ { 432, 5, 1, 28, "VGETLNs16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo69 }, // Inst #432 = VGETLNs16
+ { 433, 5, 1, 28, "VGETLNs8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo69 }, // Inst #433 = VGETLNs8
+ { 434, 5, 1, 28, "VGETLNu16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo69 }, // Inst #434 = VGETLNu16
+ { 435, 5, 1, 28, "VGETLNu8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo69 }, // Inst #435 = VGETLNu8
+ { 436, 5, 1, 4, "VHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #436 = VHADDsv16i8
+ { 437, 5, 1, 3, "VHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #437 = VHADDsv2i32
+ { 438, 5, 1, 3, "VHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #438 = VHADDsv4i16
+ { 439, 5, 1, 4, "VHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #439 = VHADDsv4i32
+ { 440, 5, 1, 4, "VHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #440 = VHADDsv8i16
+ { 441, 5, 1, 3, "VHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #441 = VHADDsv8i8
+ { 442, 5, 1, 4, "VHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #442 = VHADDuv16i8
+ { 443, 5, 1, 3, "VHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #443 = VHADDuv2i32
+ { 444, 5, 1, 3, "VHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #444 = VHADDuv4i16
+ { 445, 5, 1, 4, "VHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #445 = VHADDuv4i32
+ { 446, 5, 1, 4, "VHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #446 = VHADDuv8i16
+ { 447, 5, 1, 3, "VHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #447 = VHADDuv8i8
+ { 448, 5, 1, 4, "VHSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #448 = VHSUBsv16i8
+ { 449, 5, 1, 3, "VHSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #449 = VHSUBsv2i32
+ { 450, 5, 1, 3, "VHSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #450 = VHSUBsv4i16
+ { 451, 5, 1, 4, "VHSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #451 = VHSUBsv4i32
+ { 452, 5, 1, 4, "VHSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #452 = VHSUBsv8i16
+ { 453, 5, 1, 3, "VHSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #453 = VHSUBsv8i8
+ { 454, 5, 1, 4, "VHSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #454 = VHSUBuv16i8
+ { 455, 5, 1, 3, "VHSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #455 = VHSUBuv2i32
+ { 456, 5, 1, 3, "VHSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #456 = VHSUBuv4i16
+ { 457, 5, 1, 4, "VHSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #457 = VHSUBuv4i32
+ { 458, 5, 1, 4, "VHSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #458 = VHSUBuv8i16
+ { 459, 5, 1, 3, "VHSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #459 = VHSUBuv8i8
+ { 460, 7, 1, 11, "VLD1d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #460 = VLD1d16
+ { 461, 7, 1, 11, "VLD1d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #461 = VLD1d32
+ { 462, 7, 1, 11, "VLD1d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #462 = VLD1d64
+ { 463, 7, 1, 11, "VLD1d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #463 = VLD1d8
+ { 464, 7, 1, 11, "VLD1df", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #464 = VLD1df
+ { 465, 7, 1, 11, "VLD1q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #465 = VLD1q16
+ { 466, 7, 1, 11, "VLD1q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #466 = VLD1q32
+ { 467, 7, 1, 11, "VLD1q64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #467 = VLD1q64
+ { 468, 7, 1, 11, "VLD1q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #468 = VLD1q8
+ { 469, 7, 1, 11, "VLD1qf", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #469 = VLD1qf
+ { 470, 11, 2, 12, "VLD2LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #470 = VLD2LNd16
+ { 471, 11, 2, 12, "VLD2LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #471 = VLD2LNd32
+ { 472, 11, 2, 12, "VLD2LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #472 = VLD2LNd8
+ { 473, 11, 2, 12, "VLD2LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #473 = VLD2LNq16a
+ { 474, 11, 2, 12, "VLD2LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #474 = VLD2LNq16b
+ { 475, 11, 2, 12, "VLD2LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #475 = VLD2LNq32a
+ { 476, 11, 2, 12, "VLD2LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #476 = VLD2LNq32b
+ { 477, 8, 2, 12, "VLD2d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #477 = VLD2d16
+ { 478, 8, 2, 12, "VLD2d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #478 = VLD2d32
+ { 479, 8, 2, 11, "VLD2d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #479 = VLD2d64
+ { 480, 8, 2, 12, "VLD2d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo73 }, // Inst #480 = VLD2d8
+ { 481, 10, 4, 12, "VLD2q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #481 = VLD2q16
+ { 482, 10, 4, 12, "VLD2q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #482 = VLD2q32
+ { 483, 10, 4, 12, "VLD2q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #483 = VLD2q8
+ { 484, 13, 3, 13, "VLD3LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #484 = VLD3LNd16
+ { 485, 13, 3, 13, "VLD3LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #485 = VLD3LNd32
+ { 486, 13, 3, 13, "VLD3LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #486 = VLD3LNd8
+ { 487, 13, 3, 13, "VLD3LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #487 = VLD3LNq16a
+ { 488, 13, 3, 13, "VLD3LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #488 = VLD3LNq16b
+ { 489, 13, 3, 13, "VLD3LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #489 = VLD3LNq32a
+ { 490, 13, 3, 13, "VLD3LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #490 = VLD3LNq32b
+ { 491, 9, 3, 13, "VLD3d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #491 = VLD3d16
+ { 492, 9, 3, 13, "VLD3d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #492 = VLD3d32
+ { 493, 9, 3, 11, "VLD3d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #493 = VLD3d64
+ { 494, 9, 3, 13, "VLD3d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #494 = VLD3d8
+ { 495, 10, 4, 13, "VLD3q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #495 = VLD3q16a
+ { 496, 10, 4, 13, "VLD3q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #496 = VLD3q16b
+ { 497, 10, 4, 13, "VLD3q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #497 = VLD3q32a
+ { 498, 10, 4, 13, "VLD3q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #498 = VLD3q32b
+ { 499, 10, 4, 13, "VLD3q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #499 = VLD3q8a
+ { 500, 10, 4, 13, "VLD3q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #500 = VLD3q8b
+ { 501, 15, 4, 14, "VLD4LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #501 = VLD4LNd16
+ { 502, 15, 4, 14, "VLD4LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #502 = VLD4LNd32
+ { 503, 15, 4, 14, "VLD4LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #503 = VLD4LNd8
+ { 504, 15, 4, 14, "VLD4LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #504 = VLD4LNq16a
+ { 505, 15, 4, 14, "VLD4LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #505 = VLD4LNq16b
+ { 506, 15, 4, 14, "VLD4LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #506 = VLD4LNq32a
+ { 507, 15, 4, 14, "VLD4LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #507 = VLD4LNq32b
+ { 508, 10, 4, 14, "VLD4d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #508 = VLD4d16
+ { 509, 10, 4, 14, "VLD4d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #509 = VLD4d32
+ { 510, 10, 4, 11, "VLD4d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #510 = VLD4d64
+ { 511, 10, 4, 14, "VLD4d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo74 }, // Inst #511 = VLD4d8
+ { 512, 11, 5, 14, "VLD4q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #512 = VLD4q16a
+ { 513, 11, 5, 14, "VLD4q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #513 = VLD4q16b
+ { 514, 11, 5, 14, "VLD4q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #514 = VLD4q32a
+ { 515, 11, 5, 14, "VLD4q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #515 = VLD4q32b
+ { 516, 11, 5, 14, "VLD4q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #516 = VLD4q8a
+ { 517, 11, 5, 14, "VLD4q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo79 }, // Inst #517 = VLD4q8b
+ { 518, 5, 0, 75, "VLDMD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #518 = VLDMD
+ { 519, 5, 0, 75, "VLDMS", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #519 = VLDMS
+ { 520, 5, 1, 74, "VLDRD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #520 = VLDRD
+ { 521, 5, 1, 75, "VLDRQ", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #521 = VLDRQ
+ { 522, 5, 1, 73, "VLDRS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #522 = VLDRS
+ { 523, 5, 1, 1, "VMAXfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #523 = VMAXfd
+ { 524, 5, 1, 2, "VMAXfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #524 = VMAXfq
+ { 525, 5, 1, 4, "VMAXsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #525 = VMAXsv16i8
+ { 526, 5, 1, 3, "VMAXsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #526 = VMAXsv2i32
+ { 527, 5, 1, 3, "VMAXsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #527 = VMAXsv4i16
+ { 528, 5, 1, 4, "VMAXsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #528 = VMAXsv4i32
+ { 529, 5, 1, 4, "VMAXsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #529 = VMAXsv8i16
+ { 530, 5, 1, 3, "VMAXsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #530 = VMAXsv8i8
+ { 531, 5, 1, 4, "VMAXuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #531 = VMAXuv16i8
+ { 532, 5, 1, 3, "VMAXuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #532 = VMAXuv2i32
+ { 533, 5, 1, 3, "VMAXuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #533 = VMAXuv4i16
+ { 534, 5, 1, 4, "VMAXuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #534 = VMAXuv4i32
+ { 535, 5, 1, 4, "VMAXuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #535 = VMAXuv8i16
+ { 536, 5, 1, 3, "VMAXuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #536 = VMAXuv8i8
+ { 537, 5, 1, 1, "VMINfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #537 = VMINfd
+ { 538, 5, 1, 2, "VMINfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #538 = VMINfq
+ { 539, 5, 1, 4, "VMINsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #539 = VMINsv16i8
+ { 540, 5, 1, 3, "VMINsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #540 = VMINsv2i32
+ { 541, 5, 1, 3, "VMINsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #541 = VMINsv4i16
+ { 542, 5, 1, 4, "VMINsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #542 = VMINsv4i32
+ { 543, 5, 1, 4, "VMINsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #543 = VMINsv8i16
+ { 544, 5, 1, 3, "VMINsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #544 = VMINsv8i8
+ { 545, 5, 1, 4, "VMINuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #545 = VMINuv16i8
+ { 546, 5, 1, 3, "VMINuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #546 = VMINuv2i32
+ { 547, 5, 1, 3, "VMINuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #547 = VMINuv4i16
+ { 548, 5, 1, 4, "VMINuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #548 = VMINuv4i32
+ { 549, 5, 1, 4, "VMINuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #549 = VMINuv8i16
+ { 550, 5, 1, 3, "VMINuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #550 = VMINuv8i8
+ { 551, 6, 1, 77, "VMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #551 = VMLAD
+ { 552, 7, 1, 19, "VMLALslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #552 = VMLALslsv2i32
+ { 553, 7, 1, 17, "VMLALslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #553 = VMLALslsv4i16
+ { 554, 7, 1, 19, "VMLALsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #554 = VMLALsluv2i32
+ { 555, 7, 1, 17, "VMLALsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #555 = VMLALsluv4i16
+ { 556, 6, 1, 17, "VMLALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #556 = VMLALsv2i64
+ { 557, 6, 1, 17, "VMLALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #557 = VMLALsv4i32
+ { 558, 6, 1, 17, "VMLALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #558 = VMLALsv8i16
+ { 559, 6, 1, 17, "VMLALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #559 = VMLALuv2i64
+ { 560, 6, 1, 17, "VMLALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #560 = VMLALuv4i32
+ { 561, 6, 1, 17, "VMLALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #561 = VMLALuv8i16
+ { 562, 6, 1, 76, "VMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #562 = VMLAS
+ { 563, 6, 1, 15, "VMLAfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #563 = VMLAfd
+ { 564, 6, 1, 16, "VMLAfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #564 = VMLAfq
+ { 565, 7, 1, 15, "VMLAslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #565 = VMLAslfd
+ { 566, 7, 1, 16, "VMLAslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #566 = VMLAslfq
+ { 567, 7, 1, 19, "VMLAslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #567 = VMLAslv2i32
+ { 568, 7, 1, 17, "VMLAslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #568 = VMLAslv4i16
+ { 569, 7, 1, 20, "VMLAslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #569 = VMLAslv4i32
+ { 570, 7, 1, 18, "VMLAslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #570 = VMLAslv8i16
+ { 571, 6, 1, 18, "VMLAv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #571 = VMLAv16i8
+ { 572, 6, 1, 19, "VMLAv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #572 = VMLAv2i32
+ { 573, 6, 1, 17, "VMLAv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #573 = VMLAv4i16
+ { 574, 6, 1, 20, "VMLAv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #574 = VMLAv4i32
+ { 575, 6, 1, 18, "VMLAv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #575 = VMLAv8i16
+ { 576, 6, 1, 17, "VMLAv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #576 = VMLAv8i8
+ { 577, 6, 1, 77, "VMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #577 = VMLSD
+ { 578, 7, 1, 19, "VMLSLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #578 = VMLSLslsv2i32
+ { 579, 7, 1, 17, "VMLSLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #579 = VMLSLslsv4i16
+ { 580, 7, 1, 19, "VMLSLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #580 = VMLSLsluv2i32
+ { 581, 7, 1, 17, "VMLSLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #581 = VMLSLsluv4i16
+ { 582, 6, 1, 17, "VMLSLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #582 = VMLSLsv2i64
+ { 583, 6, 1, 17, "VMLSLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #583 = VMLSLsv4i32
+ { 584, 6, 1, 17, "VMLSLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #584 = VMLSLsv8i16
+ { 585, 6, 1, 17, "VMLSLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #585 = VMLSLuv2i64
+ { 586, 6, 1, 17, "VMLSLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #586 = VMLSLuv4i32
+ { 587, 6, 1, 17, "VMLSLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #587 = VMLSLuv8i16
+ { 588, 6, 1, 76, "VMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #588 = VMLSS
+ { 589, 6, 1, 15, "VMLSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #589 = VMLSfd
+ { 590, 6, 1, 16, "VMLSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #590 = VMLSfq
+ { 591, 7, 1, 15, "VMLSslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #591 = VMLSslfd
+ { 592, 7, 1, 16, "VMLSslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #592 = VMLSslfq
+ { 593, 7, 1, 19, "VMLSslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #593 = VMLSslv2i32
+ { 594, 7, 1, 17, "VMLSslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #594 = VMLSslv4i16
+ { 595, 7, 1, 20, "VMLSslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #595 = VMLSslv4i32
+ { 596, 7, 1, 18, "VMLSslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #596 = VMLSslv8i16
+ { 597, 6, 1, 18, "VMLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #597 = VMLSv16i8
+ { 598, 6, 1, 19, "VMLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #598 = VMLSv2i32
+ { 599, 6, 1, 17, "VMLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #599 = VMLSv4i16
+ { 600, 6, 1, 20, "VMLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #600 = VMLSv4i32
+ { 601, 6, 1, 18, "VMLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo44 }, // Inst #601 = VMLSv8i16
+ { 602, 6, 1, 17, "VMLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #602 = VMLSv8i8
+ { 603, 4, 1, 87, "VMOVD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #603 = VMOVD
+ { 604, 5, 1, 23, "VMOVDRR", 0|(1<<TID::Predicable), 0|(3<<4)|(19<<9)|(1<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #604 = VMOVDRR
+ { 605, 5, 1, 87, "VMOVDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #605 = VMOVDcc
+ { 606, 4, 1, 21, "VMOVDneon", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #606 = VMOVDneon
+ { 607, 4, 1, 38, "VMOVLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #607 = VMOVLsv2i64
+ { 608, 4, 1, 38, "VMOVLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #608 = VMOVLsv4i32
+ { 609, 4, 1, 38, "VMOVLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #609 = VMOVLsv8i16
+ { 610, 4, 1, 38, "VMOVLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #610 = VMOVLuv2i64
+ { 611, 4, 1, 38, "VMOVLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #611 = VMOVLuv4i32
+ { 612, 4, 1, 38, "VMOVLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #612 = VMOVLuv8i16
+ { 613, 4, 1, 21, "VMOVNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #613 = VMOVNv2i32
+ { 614, 4, 1, 21, "VMOVNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #614 = VMOVNv4i16
+ { 615, 4, 1, 21, "VMOVNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #615 = VMOVNv8i8
+ { 616, 4, 1, 21, "VMOVQ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #616 = VMOVQ
+ { 617, 5, 2, 22, "VMOVRRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(17<<9)|(1<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #617 = VMOVRRD
+ { 618, 4, 1, 28, "VMOVRS", 0|(1<<TID::Predicable), 0|(3<<4)|(16<<9)|(1<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #618 = VMOVRS
+ { 619, 4, 1, 86, "VMOVS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #619 = VMOVS
+ { 620, 4, 1, 24, "VMOVSR", 0|(1<<TID::Predicable), 0|(3<<4)|(18<<9)|(1<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #620 = VMOVSR
+ { 621, 5, 1, 86, "VMOVScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #621 = VMOVScc
+ { 622, 4, 1, 26, "VMOVv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #622 = VMOVv16i8
+ { 623, 4, 1, 26, "VMOVv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #623 = VMOVv1i64
+ { 624, 4, 1, 26, "VMOVv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #624 = VMOVv2i32
+ { 625, 4, 1, 26, "VMOVv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #625 = VMOVv2i64
+ { 626, 4, 1, 26, "VMOVv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #626 = VMOVv4i16
+ { 627, 4, 1, 26, "VMOVv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #627 = VMOVv4i32
+ { 628, 4, 1, 26, "VMOVv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #628 = VMOVv8i16
+ { 629, 4, 1, 26, "VMOVv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo25 }, // Inst #629 = VMOVv8i8
+ { 630, 5, 1, 79, "VMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #630 = VMULD
+ { 631, 5, 1, 29, "VMULLp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #631 = VMULLp
+ { 632, 6, 1, 29, "VMULLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #632 = VMULLslsv2i32
+ { 633, 6, 1, 29, "VMULLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #633 = VMULLslsv4i16
+ { 634, 6, 1, 29, "VMULLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #634 = VMULLsluv2i32
+ { 635, 6, 1, 29, "VMULLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #635 = VMULLsluv4i16
+ { 636, 5, 1, 29, "VMULLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #636 = VMULLsv2i64
+ { 637, 5, 1, 29, "VMULLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #637 = VMULLsv4i32
+ { 638, 5, 1, 29, "VMULLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #638 = VMULLsv8i16
+ { 639, 5, 1, 29, "VMULLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #639 = VMULLuv2i64
+ { 640, 5, 1, 29, "VMULLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #640 = VMULLuv4i32
+ { 641, 5, 1, 29, "VMULLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #641 = VMULLuv8i16
+ { 642, 5, 1, 78, "VMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #642 = VMULS
+ { 643, 5, 1, 1, "VMULfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #643 = VMULfd
+ { 644, 5, 1, 1, "VMULfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #644 = VMULfd_sfp
+ { 645, 5, 1, 2, "VMULfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #645 = VMULfq
+ { 646, 5, 1, 29, "VMULpd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #646 = VMULpd
+ { 647, 5, 1, 30, "VMULpq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #647 = VMULpq
+ { 648, 6, 1, 1, "VMULslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #648 = VMULslfd
+ { 649, 6, 1, 2, "VMULslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #649 = VMULslfq
+ { 650, 6, 1, 31, "VMULslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #650 = VMULslv2i32
+ { 651, 6, 1, 29, "VMULslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #651 = VMULslv4i16
+ { 652, 6, 1, 32, "VMULslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #652 = VMULslv4i32
+ { 653, 6, 1, 30, "VMULslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #653 = VMULslv8i16
+ { 654, 5, 1, 30, "VMULv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #654 = VMULv16i8
+ { 655, 5, 1, 31, "VMULv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #655 = VMULv2i32
+ { 656, 5, 1, 29, "VMULv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #656 = VMULv4i16
+ { 657, 5, 1, 32, "VMULv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #657 = VMULv4i32
+ { 658, 5, 1, 30, "VMULv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #658 = VMULv8i16
+ { 659, 5, 1, 29, "VMULv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #659 = VMULv8i8
+ { 660, 4, 1, 44, "VMVNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #660 = VMVNd
+ { 661, 4, 1, 44, "VMVNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #661 = VMVNq
+ { 662, 4, 1, 87, "VNEGD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #662 = VNEGD
+ { 663, 5, 1, 87, "VNEGDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #663 = VNEGDcc
+ { 664, 4, 1, 86, "VNEGS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #664 = VNEGS
+ { 665, 5, 1, 86, "VNEGScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #665 = VNEGScc
+ { 666, 4, 1, 57, "VNEGf32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #666 = VNEGf32d
+ { 667, 4, 1, 57, "VNEGf32d_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo51 }, // Inst #667 = VNEGf32d_sfp
+ { 668, 4, 1, 58, "VNEGf32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #668 = VNEGf32q
+ { 669, 4, 1, 44, "VNEGs16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #669 = VNEGs16d
+ { 670, 4, 1, 44, "VNEGs16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #670 = VNEGs16q
+ { 671, 4, 1, 44, "VNEGs32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #671 = VNEGs32d
+ { 672, 4, 1, 44, "VNEGs32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #672 = VNEGs32q
+ { 673, 4, 1, 44, "VNEGs8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #673 = VNEGs8d
+ { 674, 4, 1, 44, "VNEGs8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #674 = VNEGs8q
+ { 675, 6, 1, 77, "VNMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #675 = VNMLAD
+ { 676, 6, 1, 76, "VNMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #676 = VNMLAS
+ { 677, 6, 1, 77, "VNMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #677 = VNMLSD
+ { 678, 6, 1, 76, "VNMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo85 }, // Inst #678 = VNMLSS
+ { 679, 5, 1, 79, "VNMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #679 = VNMULD
+ { 680, 5, 1, 78, "VNMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #680 = VNMULS
+ { 681, 5, 1, 5, "VORNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #681 = VORNd
+ { 682, 5, 1, 6, "VORNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #682 = VORNq
+ { 683, 5, 1, 5, "VORRd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #683 = VORRd
+ { 684, 5, 1, 6, "VORRq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #684 = VORRq
+ { 685, 5, 1, 34, "VPADALsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #685 = VPADALsv16i8
+ { 686, 5, 1, 33, "VPADALsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #686 = VPADALsv2i32
+ { 687, 5, 1, 33, "VPADALsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #687 = VPADALsv4i16
+ { 688, 5, 1, 34, "VPADALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #688 = VPADALsv4i32
+ { 689, 5, 1, 34, "VPADALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #689 = VPADALsv8i16
+ { 690, 5, 1, 33, "VPADALsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #690 = VPADALsv8i8
+ { 691, 5, 1, 34, "VPADALuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #691 = VPADALuv16i8
+ { 692, 5, 1, 33, "VPADALuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #692 = VPADALuv2i32
+ { 693, 5, 1, 33, "VPADALuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #693 = VPADALuv4i16
+ { 694, 5, 1, 34, "VPADALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #694 = VPADALuv4i32
+ { 695, 5, 1, 34, "VPADALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #695 = VPADALuv8i16
+ { 696, 5, 1, 33, "VPADALuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #696 = VPADALuv8i8
+ { 697, 4, 1, 44, "VPADDLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #697 = VPADDLsv16i8
+ { 698, 4, 1, 44, "VPADDLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #698 = VPADDLsv2i32
+ { 699, 4, 1, 44, "VPADDLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #699 = VPADDLsv4i16
+ { 700, 4, 1, 44, "VPADDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #700 = VPADDLsv4i32
+ { 701, 4, 1, 44, "VPADDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #701 = VPADDLsv8i16
+ { 702, 4, 1, 44, "VPADDLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #702 = VPADDLsv8i8
+ { 703, 4, 1, 44, "VPADDLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #703 = VPADDLuv16i8
+ { 704, 4, 1, 44, "VPADDLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #704 = VPADDLuv2i32
+ { 705, 4, 1, 44, "VPADDLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #705 = VPADDLuv4i16
+ { 706, 4, 1, 44, "VPADDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #706 = VPADDLuv4i32
+ { 707, 4, 1, 44, "VPADDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #707 = VPADDLuv8i16
+ { 708, 4, 1, 44, "VPADDLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #708 = VPADDLuv8i8
+ { 709, 5, 1, 1, "VPADDf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #709 = VPADDf
+ { 710, 5, 1, 5, "VPADDi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #710 = VPADDi16
+ { 711, 5, 1, 5, "VPADDi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #711 = VPADDi32
+ { 712, 5, 1, 5, "VPADDi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #712 = VPADDi8
+ { 713, 5, 1, 3, "VPMAXf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #713 = VPMAXf
+ { 714, 5, 1, 3, "VPMAXs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #714 = VPMAXs16
+ { 715, 5, 1, 3, "VPMAXs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #715 = VPMAXs32
+ { 716, 5, 1, 3, "VPMAXs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #716 = VPMAXs8
+ { 717, 5, 1, 3, "VPMAXu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #717 = VPMAXu16
+ { 718, 5, 1, 3, "VPMAXu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #718 = VPMAXu32
+ { 719, 5, 1, 3, "VPMAXu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #719 = VPMAXu8
+ { 720, 5, 1, 3, "VPMINf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #720 = VPMINf
+ { 721, 5, 1, 3, "VPMINs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #721 = VPMINs16
+ { 722, 5, 1, 3, "VPMINs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #722 = VPMINs32
+ { 723, 5, 1, 3, "VPMINs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #723 = VPMINs8
+ { 724, 5, 1, 3, "VPMINu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #724 = VPMINu16
+ { 725, 5, 1, 3, "VPMINu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #725 = VPMINu32
+ { 726, 5, 1, 3, "VPMINu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #726 = VPMINu8
+ { 727, 4, 1, 39, "VQABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #727 = VQABSv16i8
+ { 728, 4, 1, 38, "VQABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #728 = VQABSv2i32
+ { 729, 4, 1, 38, "VQABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #729 = VQABSv4i16
+ { 730, 4, 1, 39, "VQABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #730 = VQABSv4i32
+ { 731, 4, 1, 39, "VQABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #731 = VQABSv8i16
+ { 732, 4, 1, 38, "VQABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #732 = VQABSv8i8
+ { 733, 5, 1, 4, "VQADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #733 = VQADDsv16i8
+ { 734, 5, 1, 3, "VQADDsv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #734 = VQADDsv1i64
+ { 735, 5, 1, 3, "VQADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #735 = VQADDsv2i32
+ { 736, 5, 1, 4, "VQADDsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #736 = VQADDsv2i64
+ { 737, 5, 1, 3, "VQADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #737 = VQADDsv4i16
+ { 738, 5, 1, 4, "VQADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #738 = VQADDsv4i32
+ { 739, 5, 1, 4, "VQADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #739 = VQADDsv8i16
+ { 740, 5, 1, 3, "VQADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #740 = VQADDsv8i8
+ { 741, 5, 1, 4, "VQADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #741 = VQADDuv16i8
+ { 742, 5, 1, 3, "VQADDuv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #742 = VQADDuv1i64
+ { 743, 5, 1, 3, "VQADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #743 = VQADDuv2i32
+ { 744, 5, 1, 4, "VQADDuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #744 = VQADDuv2i64
+ { 745, 5, 1, 3, "VQADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #745 = VQADDuv4i16
+ { 746, 5, 1, 4, "VQADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #746 = VQADDuv4i32
+ { 747, 5, 1, 4, "VQADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #747 = VQADDuv8i16
+ { 748, 5, 1, 3, "VQADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #748 = VQADDuv8i8
+ { 749, 7, 1, 19, "VQDMLALslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #749 = VQDMLALslv2i32
+ { 750, 7, 1, 17, "VQDMLALslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #750 = VQDMLALslv4i16
+ { 751, 6, 1, 17, "VQDMLALv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #751 = VQDMLALv2i64
+ { 752, 6, 1, 17, "VQDMLALv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #752 = VQDMLALv4i32
+ { 753, 7, 1, 19, "VQDMLSLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #753 = VQDMLSLslv2i32
+ { 754, 7, 1, 17, "VQDMLSLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #754 = VQDMLSLslv4i16
+ { 755, 6, 1, 17, "VQDMLSLv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #755 = VQDMLSLv2i64
+ { 756, 6, 1, 17, "VQDMLSLv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo43 }, // Inst #756 = VQDMLSLv4i32
+ { 757, 6, 1, 31, "VQDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #757 = VQDMULHslv2i32
+ { 758, 6, 1, 29, "VQDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #758 = VQDMULHslv4i16
+ { 759, 6, 1, 32, "VQDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #759 = VQDMULHslv4i32
+ { 760, 6, 1, 30, "VQDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #760 = VQDMULHslv8i16
+ { 761, 5, 1, 31, "VQDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #761 = VQDMULHv2i32
+ { 762, 5, 1, 29, "VQDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #762 = VQDMULHv4i16
+ { 763, 5, 1, 32, "VQDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #763 = VQDMULHv4i32
+ { 764, 5, 1, 30, "VQDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #764 = VQDMULHv8i16
+ { 765, 6, 1, 29, "VQDMULLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #765 = VQDMULLslv2i32
+ { 766, 6, 1, 29, "VQDMULLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #766 = VQDMULLslv4i16
+ { 767, 5, 1, 29, "VQDMULLv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #767 = VQDMULLv2i64
+ { 768, 5, 1, 29, "VQDMULLv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #768 = VQDMULLv4i32
+ { 769, 4, 1, 38, "VQMOVNsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #769 = VQMOVNsuv2i32
+ { 770, 4, 1, 38, "VQMOVNsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #770 = VQMOVNsuv4i16
+ { 771, 4, 1, 38, "VQMOVNsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #771 = VQMOVNsuv8i8
+ { 772, 4, 1, 38, "VQMOVNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #772 = VQMOVNsv2i32
+ { 773, 4, 1, 38, "VQMOVNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #773 = VQMOVNsv4i16
+ { 774, 4, 1, 38, "VQMOVNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #774 = VQMOVNsv8i8
+ { 775, 4, 1, 38, "VQMOVNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #775 = VQMOVNuv2i32
+ { 776, 4, 1, 38, "VQMOVNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #776 = VQMOVNuv4i16
+ { 777, 4, 1, 38, "VQMOVNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #777 = VQMOVNuv8i8
+ { 778, 4, 1, 39, "VQNEGv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #778 = VQNEGv16i8
+ { 779, 4, 1, 38, "VQNEGv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #779 = VQNEGv2i32
+ { 780, 4, 1, 38, "VQNEGv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #780 = VQNEGv4i16
+ { 781, 4, 1, 39, "VQNEGv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #781 = VQNEGv4i32
+ { 782, 4, 1, 39, "VQNEGv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #782 = VQNEGv8i16
+ { 783, 4, 1, 38, "VQNEGv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #783 = VQNEGv8i8
+ { 784, 6, 1, 31, "VQRDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #784 = VQRDMULHslv2i32
+ { 785, 6, 1, 29, "VQRDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #785 = VQRDMULHslv4i16
+ { 786, 6, 1, 32, "VQRDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #786 = VQRDMULHslv4i32
+ { 787, 6, 1, 30, "VQRDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #787 = VQRDMULHslv8i16
+ { 788, 5, 1, 31, "VQRDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #788 = VQRDMULHv2i32
+ { 789, 5, 1, 29, "VQRDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #789 = VQRDMULHv4i16
+ { 790, 5, 1, 32, "VQRDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #790 = VQRDMULHv4i32
+ { 791, 5, 1, 30, "VQRDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #791 = VQRDMULHv8i16
+ { 792, 5, 1, 43, "VQRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #792 = VQRSHLsv16i8
+ { 793, 5, 1, 42, "VQRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #793 = VQRSHLsv1i64
+ { 794, 5, 1, 42, "VQRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #794 = VQRSHLsv2i32
+ { 795, 5, 1, 43, "VQRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #795 = VQRSHLsv2i64
+ { 796, 5, 1, 42, "VQRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #796 = VQRSHLsv4i16
+ { 797, 5, 1, 43, "VQRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #797 = VQRSHLsv4i32
+ { 798, 5, 1, 43, "VQRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #798 = VQRSHLsv8i16
+ { 799, 5, 1, 42, "VQRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #799 = VQRSHLsv8i8
+ { 800, 5, 1, 43, "VQRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #800 = VQRSHLuv16i8
+ { 801, 5, 1, 42, "VQRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #801 = VQRSHLuv1i64
+ { 802, 5, 1, 42, "VQRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #802 = VQRSHLuv2i32
+ { 803, 5, 1, 43, "VQRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #803 = VQRSHLuv2i64
+ { 804, 5, 1, 42, "VQRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #804 = VQRSHLuv4i16
+ { 805, 5, 1, 43, "VQRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #805 = VQRSHLuv4i32
+ { 806, 5, 1, 43, "VQRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #806 = VQRSHLuv8i16
+ { 807, 5, 1, 42, "VQRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #807 = VQRSHLuv8i8
+ { 808, 5, 1, 42, "VQRSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #808 = VQRSHRNsv2i32
+ { 809, 5, 1, 42, "VQRSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #809 = VQRSHRNsv4i16
+ { 810, 5, 1, 42, "VQRSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #810 = VQRSHRNsv8i8
+ { 811, 5, 1, 42, "VQRSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #811 = VQRSHRNuv2i32
+ { 812, 5, 1, 42, "VQRSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #812 = VQRSHRNuv4i16
+ { 813, 5, 1, 42, "VQRSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #813 = VQRSHRNuv8i8
+ { 814, 5, 1, 42, "VQRSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #814 = VQRSHRUNv2i32
+ { 815, 5, 1, 42, "VQRSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #815 = VQRSHRUNv4i16
+ { 816, 5, 1, 42, "VQRSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #816 = VQRSHRUNv8i8
+ { 817, 5, 1, 42, "VQSHLsiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #817 = VQSHLsiv16i8
+ { 818, 5, 1, 42, "VQSHLsiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #818 = VQSHLsiv1i64
+ { 819, 5, 1, 42, "VQSHLsiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #819 = VQSHLsiv2i32
+ { 820, 5, 1, 42, "VQSHLsiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #820 = VQSHLsiv2i64
+ { 821, 5, 1, 42, "VQSHLsiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #821 = VQSHLsiv4i16
+ { 822, 5, 1, 42, "VQSHLsiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #822 = VQSHLsiv4i32
+ { 823, 5, 1, 42, "VQSHLsiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #823 = VQSHLsiv8i16
+ { 824, 5, 1, 42, "VQSHLsiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #824 = VQSHLsiv8i8
+ { 825, 5, 1, 42, "VQSHLsuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #825 = VQSHLsuv16i8
+ { 826, 5, 1, 42, "VQSHLsuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #826 = VQSHLsuv1i64
+ { 827, 5, 1, 42, "VQSHLsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #827 = VQSHLsuv2i32
+ { 828, 5, 1, 42, "VQSHLsuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #828 = VQSHLsuv2i64
+ { 829, 5, 1, 42, "VQSHLsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #829 = VQSHLsuv4i16
+ { 830, 5, 1, 42, "VQSHLsuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #830 = VQSHLsuv4i32
+ { 831, 5, 1, 42, "VQSHLsuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #831 = VQSHLsuv8i16
+ { 832, 5, 1, 42, "VQSHLsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #832 = VQSHLsuv8i8
+ { 833, 5, 1, 43, "VQSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #833 = VQSHLsv16i8
+ { 834, 5, 1, 42, "VQSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #834 = VQSHLsv1i64
+ { 835, 5, 1, 42, "VQSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #835 = VQSHLsv2i32
+ { 836, 5, 1, 43, "VQSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #836 = VQSHLsv2i64
+ { 837, 5, 1, 42, "VQSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #837 = VQSHLsv4i16
+ { 838, 5, 1, 43, "VQSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #838 = VQSHLsv4i32
+ { 839, 5, 1, 43, "VQSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #839 = VQSHLsv8i16
+ { 840, 5, 1, 42, "VQSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #840 = VQSHLsv8i8
+ { 841, 5, 1, 42, "VQSHLuiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #841 = VQSHLuiv16i8
+ { 842, 5, 1, 42, "VQSHLuiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #842 = VQSHLuiv1i64
+ { 843, 5, 1, 42, "VQSHLuiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #843 = VQSHLuiv2i32
+ { 844, 5, 1, 42, "VQSHLuiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #844 = VQSHLuiv2i64
+ { 845, 5, 1, 42, "VQSHLuiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #845 = VQSHLuiv4i16
+ { 846, 5, 1, 42, "VQSHLuiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #846 = VQSHLuiv4i32
+ { 847, 5, 1, 42, "VQSHLuiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #847 = VQSHLuiv8i16
+ { 848, 5, 1, 42, "VQSHLuiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #848 = VQSHLuiv8i8
+ { 849, 5, 1, 43, "VQSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #849 = VQSHLuv16i8
+ { 850, 5, 1, 42, "VQSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #850 = VQSHLuv1i64
+ { 851, 5, 1, 42, "VQSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #851 = VQSHLuv2i32
+ { 852, 5, 1, 43, "VQSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #852 = VQSHLuv2i64
+ { 853, 5, 1, 42, "VQSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #853 = VQSHLuv4i16
+ { 854, 5, 1, 43, "VQSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #854 = VQSHLuv4i32
+ { 855, 5, 1, 43, "VQSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #855 = VQSHLuv8i16
+ { 856, 5, 1, 42, "VQSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #856 = VQSHLuv8i8
+ { 857, 5, 1, 42, "VQSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #857 = VQSHRNsv2i32
+ { 858, 5, 1, 42, "VQSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #858 = VQSHRNsv4i16
+ { 859, 5, 1, 42, "VQSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #859 = VQSHRNsv8i8
+ { 860, 5, 1, 42, "VQSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #860 = VQSHRNuv2i32
+ { 861, 5, 1, 42, "VQSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #861 = VQSHRNuv4i16
+ { 862, 5, 1, 42, "VQSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #862 = VQSHRNuv8i8
+ { 863, 5, 1, 42, "VQSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #863 = VQSHRUNv2i32
+ { 864, 5, 1, 42, "VQSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #864 = VQSHRUNv4i16
+ { 865, 5, 1, 42, "VQSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #865 = VQSHRUNv8i8
+ { 866, 5, 1, 4, "VQSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #866 = VQSUBsv16i8
+ { 867, 5, 1, 3, "VQSUBsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #867 = VQSUBsv1i64
+ { 868, 5, 1, 3, "VQSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #868 = VQSUBsv2i32
+ { 869, 5, 1, 4, "VQSUBsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #869 = VQSUBsv2i64
+ { 870, 5, 1, 3, "VQSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #870 = VQSUBsv4i16
+ { 871, 5, 1, 4, "VQSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #871 = VQSUBsv4i32
+ { 872, 5, 1, 4, "VQSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #872 = VQSUBsv8i16
+ { 873, 5, 1, 3, "VQSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #873 = VQSUBsv8i8
+ { 874, 5, 1, 4, "VQSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #874 = VQSUBuv16i8
+ { 875, 5, 1, 3, "VQSUBuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #875 = VQSUBuv1i64
+ { 876, 5, 1, 3, "VQSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #876 = VQSUBuv2i32
+ { 877, 5, 1, 4, "VQSUBuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #877 = VQSUBuv2i64
+ { 878, 5, 1, 3, "VQSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #878 = VQSUBuv4i16
+ { 879, 5, 1, 4, "VQSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #879 = VQSUBuv4i32
+ { 880, 5, 1, 4, "VQSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #880 = VQSUBuv8i16
+ { 881, 5, 1, 3, "VQSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #881 = VQSUBuv8i8
+ { 882, 5, 1, 3, "VRADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #882 = VRADDHNv2i32
+ { 883, 5, 1, 3, "VRADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #883 = VRADDHNv4i16
+ { 884, 5, 1, 3, "VRADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #884 = VRADDHNv8i8
+ { 885, 4, 1, 57, "VRECPEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #885 = VRECPEd
+ { 886, 4, 1, 57, "VRECPEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #886 = VRECPEfd
+ { 887, 4, 1, 58, "VRECPEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #887 = VRECPEfq
+ { 888, 4, 1, 58, "VRECPEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #888 = VRECPEq
+ { 889, 5, 1, 40, "VRECPSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #889 = VRECPSfd
+ { 890, 5, 1, 41, "VRECPSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #890 = VRECPSfq
+ { 891, 4, 1, 21, "VREV16d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #891 = VREV16d8
+ { 892, 4, 1, 21, "VREV16q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #892 = VREV16q8
+ { 893, 4, 1, 21, "VREV32d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #893 = VREV32d16
+ { 894, 4, 1, 21, "VREV32d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #894 = VREV32d8
+ { 895, 4, 1, 21, "VREV32q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #895 = VREV32q16
+ { 896, 4, 1, 21, "VREV32q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #896 = VREV32q8
+ { 897, 4, 1, 21, "VREV64d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #897 = VREV64d16
+ { 898, 4, 1, 21, "VREV64d32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #898 = VREV64d32
+ { 899, 4, 1, 21, "VREV64d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #899 = VREV64d8
+ { 900, 4, 1, 21, "VREV64df", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #900 = VREV64df
+ { 901, 4, 1, 21, "VREV64q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #901 = VREV64q16
+ { 902, 4, 1, 21, "VREV64q32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #902 = VREV64q32
+ { 903, 4, 1, 21, "VREV64q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #903 = VREV64q8
+ { 904, 4, 1, 21, "VREV64qf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #904 = VREV64qf
+ { 905, 5, 1, 4, "VRHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #905 = VRHADDsv16i8
+ { 906, 5, 1, 3, "VRHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #906 = VRHADDsv2i32
+ { 907, 5, 1, 3, "VRHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #907 = VRHADDsv4i16
+ { 908, 5, 1, 4, "VRHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #908 = VRHADDsv4i32
+ { 909, 5, 1, 4, "VRHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #909 = VRHADDsv8i16
+ { 910, 5, 1, 3, "VRHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #910 = VRHADDsv8i8
+ { 911, 5, 1, 4, "VRHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #911 = VRHADDuv16i8
+ { 912, 5, 1, 3, "VRHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #912 = VRHADDuv2i32
+ { 913, 5, 1, 3, "VRHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #913 = VRHADDuv4i16
+ { 914, 5, 1, 4, "VRHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #914 = VRHADDuv4i32
+ { 915, 5, 1, 4, "VRHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #915 = VRHADDuv8i16
+ { 916, 5, 1, 3, "VRHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #916 = VRHADDuv8i8
+ { 917, 5, 1, 43, "VRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #917 = VRSHLsv16i8
+ { 918, 5, 1, 42, "VRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #918 = VRSHLsv1i64
+ { 919, 5, 1, 42, "VRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #919 = VRSHLsv2i32
+ { 920, 5, 1, 43, "VRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #920 = VRSHLsv2i64
+ { 921, 5, 1, 42, "VRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #921 = VRSHLsv4i16
+ { 922, 5, 1, 43, "VRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #922 = VRSHLsv4i32
+ { 923, 5, 1, 43, "VRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #923 = VRSHLsv8i16
+ { 924, 5, 1, 42, "VRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #924 = VRSHLsv8i8
+ { 925, 5, 1, 43, "VRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #925 = VRSHLuv16i8
+ { 926, 5, 1, 42, "VRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #926 = VRSHLuv1i64
+ { 927, 5, 1, 42, "VRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #927 = VRSHLuv2i32
+ { 928, 5, 1, 43, "VRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #928 = VRSHLuv2i64
+ { 929, 5, 1, 42, "VRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #929 = VRSHLuv4i16
+ { 930, 5, 1, 43, "VRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #930 = VRSHLuv4i32
+ { 931, 5, 1, 43, "VRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #931 = VRSHLuv8i16
+ { 932, 5, 1, 42, "VRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #932 = VRSHLuv8i8
+ { 933, 5, 1, 42, "VRSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #933 = VRSHRNv2i32
+ { 934, 5, 1, 42, "VRSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #934 = VRSHRNv4i16
+ { 935, 5, 1, 42, "VRSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #935 = VRSHRNv8i8
+ { 936, 5, 1, 42, "VRSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #936 = VRSHRsv16i8
+ { 937, 5, 1, 42, "VRSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #937 = VRSHRsv1i64
+ { 938, 5, 1, 42, "VRSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #938 = VRSHRsv2i32
+ { 939, 5, 1, 42, "VRSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #939 = VRSHRsv2i64
+ { 940, 5, 1, 42, "VRSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #940 = VRSHRsv4i16
+ { 941, 5, 1, 42, "VRSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #941 = VRSHRsv4i32
+ { 942, 5, 1, 42, "VRSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #942 = VRSHRsv8i16
+ { 943, 5, 1, 42, "VRSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #943 = VRSHRsv8i8
+ { 944, 5, 1, 42, "VRSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #944 = VRSHRuv16i8
+ { 945, 5, 1, 42, "VRSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #945 = VRSHRuv1i64
+ { 946, 5, 1, 42, "VRSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #946 = VRSHRuv2i32
+ { 947, 5, 1, 42, "VRSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #947 = VRSHRuv2i64
+ { 948, 5, 1, 42, "VRSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #948 = VRSHRuv4i16
+ { 949, 5, 1, 42, "VRSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #949 = VRSHRuv4i32
+ { 950, 5, 1, 42, "VRSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #950 = VRSHRuv8i16
+ { 951, 5, 1, 42, "VRSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #951 = VRSHRuv8i8
+ { 952, 4, 1, 57, "VRSQRTEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #952 = VRSQRTEd
+ { 953, 4, 1, 57, "VRSQRTEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #953 = VRSQRTEfd
+ { 954, 4, 1, 58, "VRSQRTEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #954 = VRSQRTEfq
+ { 955, 4, 1, 58, "VRSQRTEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo52 }, // Inst #955 = VRSQRTEq
+ { 956, 5, 1, 40, "VRSQRTSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #956 = VRSQRTSfd
+ { 957, 5, 1, 41, "VRSQRTSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #957 = VRSQRTSfq
+ { 958, 6, 1, 33, "VRSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #958 = VRSRAsv16i8
+ { 959, 6, 1, 33, "VRSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #959 = VRSRAsv1i64
+ { 960, 6, 1, 33, "VRSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #960 = VRSRAsv2i32
+ { 961, 6, 1, 33, "VRSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #961 = VRSRAsv2i64
+ { 962, 6, 1, 33, "VRSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #962 = VRSRAsv4i16
+ { 963, 6, 1, 33, "VRSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #963 = VRSRAsv4i32
+ { 964, 6, 1, 33, "VRSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #964 = VRSRAsv8i16
+ { 965, 6, 1, 33, "VRSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #965 = VRSRAsv8i8
+ { 966, 6, 1, 33, "VRSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #966 = VRSRAuv16i8
+ { 967, 6, 1, 33, "VRSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #967 = VRSRAuv1i64
+ { 968, 6, 1, 33, "VRSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #968 = VRSRAuv2i32
+ { 969, 6, 1, 33, "VRSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #969 = VRSRAuv2i64
+ { 970, 6, 1, 33, "VRSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #970 = VRSRAuv4i16
+ { 971, 6, 1, 33, "VRSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #971 = VRSRAuv4i32
+ { 972, 6, 1, 33, "VRSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #972 = VRSRAuv8i16
+ { 973, 6, 1, 33, "VRSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #973 = VRSRAuv8i8
+ { 974, 5, 1, 3, "VRSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #974 = VRSUBHNv2i32
+ { 975, 5, 1, 3, "VRSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #975 = VRSUBHNv4i16
+ { 976, 5, 1, 3, "VRSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #976 = VRSUBHNv8i8
+ { 977, 6, 1, 25, "VSETLNi16", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo109 }, // Inst #977 = VSETLNi16
+ { 978, 6, 1, 25, "VSETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo109 }, // Inst #978 = VSETLNi32
+ { 979, 6, 1, 25, "VSETLNi8", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo109 }, // Inst #979 = VSETLNi8
+ { 980, 5, 1, 44, "VSHLLi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #980 = VSHLLi16
+ { 981, 5, 1, 44, "VSHLLi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #981 = VSHLLi32
+ { 982, 5, 1, 44, "VSHLLi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #982 = VSHLLi8
+ { 983, 5, 1, 44, "VSHLLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #983 = VSHLLsv2i64
+ { 984, 5, 1, 44, "VSHLLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #984 = VSHLLsv4i32
+ { 985, 5, 1, 44, "VSHLLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #985 = VSHLLsv8i16
+ { 986, 5, 1, 44, "VSHLLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #986 = VSHLLuv2i64
+ { 987, 5, 1, 44, "VSHLLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #987 = VSHLLuv4i32
+ { 988, 5, 1, 44, "VSHLLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #988 = VSHLLuv8i16
+ { 989, 5, 1, 44, "VSHLiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #989 = VSHLiv16i8
+ { 990, 5, 1, 44, "VSHLiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #990 = VSHLiv1i64
+ { 991, 5, 1, 44, "VSHLiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #991 = VSHLiv2i32
+ { 992, 5, 1, 44, "VSHLiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #992 = VSHLiv2i64
+ { 993, 5, 1, 44, "VSHLiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #993 = VSHLiv4i16
+ { 994, 5, 1, 44, "VSHLiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #994 = VSHLiv4i32
+ { 995, 5, 1, 44, "VSHLiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #995 = VSHLiv8i16
+ { 996, 5, 1, 44, "VSHLiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #996 = VSHLiv8i8
+ { 997, 5, 1, 45, "VSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #997 = VSHLsv16i8
+ { 998, 5, 1, 44, "VSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #998 = VSHLsv1i64
+ { 999, 5, 1, 44, "VSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #999 = VSHLsv2i32
+ { 1000, 5, 1, 45, "VSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1000 = VSHLsv2i64
+ { 1001, 5, 1, 44, "VSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1001 = VSHLsv4i16
+ { 1002, 5, 1, 45, "VSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1002 = VSHLsv4i32
+ { 1003, 5, 1, 45, "VSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1003 = VSHLsv8i16
+ { 1004, 5, 1, 44, "VSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1004 = VSHLsv8i8
+ { 1005, 5, 1, 45, "VSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1005 = VSHLuv16i8
+ { 1006, 5, 1, 44, "VSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1006 = VSHLuv1i64
+ { 1007, 5, 1, 44, "VSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1007 = VSHLuv2i32
+ { 1008, 5, 1, 45, "VSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1008 = VSHLuv2i64
+ { 1009, 5, 1, 44, "VSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1009 = VSHLuv4i16
+ { 1010, 5, 1, 45, "VSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1010 = VSHLuv4i32
+ { 1011, 5, 1, 45, "VSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1011 = VSHLuv8i16
+ { 1012, 5, 1, 44, "VSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1012 = VSHLuv8i8
+ { 1013, 5, 1, 44, "VSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1013 = VSHRNv2i32
+ { 1014, 5, 1, 44, "VSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1014 = VSHRNv4i16
+ { 1015, 5, 1, 44, "VSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #1015 = VSHRNv8i8
+ { 1016, 5, 1, 44, "VSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1016 = VSHRsv16i8
+ { 1017, 5, 1, 44, "VSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1017 = VSHRsv1i64
+ { 1018, 5, 1, 44, "VSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1018 = VSHRsv2i32
+ { 1019, 5, 1, 44, "VSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1019 = VSHRsv2i64
+ { 1020, 5, 1, 44, "VSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1020 = VSHRsv4i16
+ { 1021, 5, 1, 44, "VSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1021 = VSHRsv4i32
+ { 1022, 5, 1, 44, "VSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1022 = VSHRsv8i16
+ { 1023, 5, 1, 44, "VSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1023 = VSHRsv8i8
+ { 1024, 5, 1, 44, "VSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1024 = VSHRuv16i8
+ { 1025, 5, 1, 44, "VSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1025 = VSHRuv1i64
+ { 1026, 5, 1, 44, "VSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1026 = VSHRuv2i32
+ { 1027, 5, 1, 44, "VSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1027 = VSHRuv2i64
+ { 1028, 5, 1, 44, "VSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1028 = VSHRuv4i16
+ { 1029, 5, 1, 44, "VSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1029 = VSHRuv4i32
+ { 1030, 5, 1, 44, "VSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1030 = VSHRuv8i16
+ { 1031, 5, 1, 44, "VSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1031 = VSHRuv8i8
+ { 1032, 4, 1, 67, "VSITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1032 = VSITOD
+ { 1033, 4, 1, 68, "VSITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #1033 = VSITOS
+ { 1034, 6, 1, 45, "VSLIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1034 = VSLIv16i8
+ { 1035, 6, 1, 44, "VSLIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1035 = VSLIv1i64
+ { 1036, 6, 1, 44, "VSLIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1036 = VSLIv2i32
+ { 1037, 6, 1, 45, "VSLIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1037 = VSLIv2i64
+ { 1038, 6, 1, 44, "VSLIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1038 = VSLIv4i16
+ { 1039, 6, 1, 45, "VSLIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1039 = VSLIv4i32
+ { 1040, 6, 1, 45, "VSLIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1040 = VSLIv8i16
+ { 1041, 6, 1, 44, "VSLIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1041 = VSLIv8i8
+ { 1042, 4, 1, 81, "VSQRTD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo49 }, // Inst #1042 = VSQRTD
+ { 1043, 4, 1, 80, "VSQRTS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #1043 = VSQRTS
+ { 1044, 6, 1, 33, "VSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1044 = VSRAsv16i8
+ { 1045, 6, 1, 33, "VSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1045 = VSRAsv1i64
+ { 1046, 6, 1, 33, "VSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1046 = VSRAsv2i32
+ { 1047, 6, 1, 33, "VSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1047 = VSRAsv2i64
+ { 1048, 6, 1, 33, "VSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1048 = VSRAsv4i16
+ { 1049, 6, 1, 33, "VSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1049 = VSRAsv4i32
+ { 1050, 6, 1, 33, "VSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1050 = VSRAsv8i16
+ { 1051, 6, 1, 33, "VSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1051 = VSRAsv8i8
+ { 1052, 6, 1, 33, "VSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1052 = VSRAuv16i8
+ { 1053, 6, 1, 33, "VSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1053 = VSRAuv1i64
+ { 1054, 6, 1, 33, "VSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1054 = VSRAuv2i32
+ { 1055, 6, 1, 33, "VSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1055 = VSRAuv2i64
+ { 1056, 6, 1, 33, "VSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1056 = VSRAuv4i16
+ { 1057, 6, 1, 33, "VSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1057 = VSRAuv4i32
+ { 1058, 6, 1, 33, "VSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1058 = VSRAuv8i16
+ { 1059, 6, 1, 33, "VSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1059 = VSRAuv8i8
+ { 1060, 6, 1, 45, "VSRIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1060 = VSRIv16i8
+ { 1061, 6, 1, 44, "VSRIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1061 = VSRIv1i64
+ { 1062, 6, 1, 44, "VSRIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1062 = VSRIv2i32
+ { 1063, 6, 1, 45, "VSRIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1063 = VSRIv2i64
+ { 1064, 6, 1, 44, "VSRIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1064 = VSRIv4i16
+ { 1065, 6, 1, 45, "VSRIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1065 = VSRIv4i32
+ { 1066, 6, 1, 45, "VSRIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #1066 = VSRIv8i16
+ { 1067, 6, 1, 44, "VSRIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #1067 = VSRIv8i8
+ { 1068, 7, 0, 46, "VST1d16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1068 = VST1d16
+ { 1069, 7, 0, 46, "VST1d32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1069 = VST1d32
+ { 1070, 7, 0, 46, "VST1d64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1070 = VST1d64
+ { 1071, 7, 0, 46, "VST1d8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1071 = VST1d8
+ { 1072, 7, 0, 46, "VST1df", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #1072 = VST1df
+ { 1073, 7, 0, 46, "VST1q16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1073 = VST1q16
+ { 1074, 7, 0, 46, "VST1q32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1074 = VST1q32
+ { 1075, 7, 0, 46, "VST1q64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1075 = VST1q64
+ { 1076, 7, 0, 46, "VST1q8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1076 = VST1q8
+ { 1077, 7, 0, 46, "VST1qf", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #1077 = VST1qf
+ { 1078, 9, 0, 46, "VST2LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1078 = VST2LNd16
+ { 1079, 9, 0, 46, "VST2LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1079 = VST2LNd32
+ { 1080, 9, 0, 46, "VST2LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1080 = VST2LNd8
+ { 1081, 9, 0, 46, "VST2LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1081 = VST2LNq16a
+ { 1082, 9, 0, 46, "VST2LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1082 = VST2LNq16b
+ { 1083, 9, 0, 46, "VST2LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1083 = VST2LNq32a
+ { 1084, 9, 0, 46, "VST2LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #1084 = VST2LNq32b
+ { 1085, 8, 0, 46, "VST2d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1085 = VST2d16
+ { 1086, 8, 0, 46, "VST2d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1086 = VST2d32
+ { 1087, 8, 0, 46, "VST2d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1087 = VST2d64
+ { 1088, 8, 0, 46, "VST2d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #1088 = VST2d8
+ { 1089, 10, 0, 46, "VST2q16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1089 = VST2q16
+ { 1090, 10, 0, 46, "VST2q32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1090 = VST2q32
+ { 1091, 10, 0, 46, "VST2q8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1091 = VST2q8
+ { 1092, 10, 0, 46, "VST3LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1092 = VST3LNd16
+ { 1093, 10, 0, 46, "VST3LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1093 = VST3LNd32
+ { 1094, 10, 0, 46, "VST3LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1094 = VST3LNd8
+ { 1095, 10, 0, 46, "VST3LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1095 = VST3LNq16a
+ { 1096, 10, 0, 46, "VST3LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1096 = VST3LNq16b
+ { 1097, 10, 0, 46, "VST3LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1097 = VST3LNq32a
+ { 1098, 10, 0, 46, "VST3LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #1098 = VST3LNq32b
+ { 1099, 9, 0, 46, "VST3d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1099 = VST3d16
+ { 1100, 9, 0, 46, "VST3d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1100 = VST3d32
+ { 1101, 9, 0, 46, "VST3d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1101 = VST3d64
+ { 1102, 9, 0, 46, "VST3d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #1102 = VST3d8
+ { 1103, 10, 1, 46, "VST3q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1103 = VST3q16a
+ { 1104, 10, 1, 46, "VST3q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1104 = VST3q16b
+ { 1105, 10, 1, 46, "VST3q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1105 = VST3q32a
+ { 1106, 10, 1, 46, "VST3q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1106 = VST3q32b
+ { 1107, 10, 1, 46, "VST3q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1107 = VST3q8a
+ { 1108, 10, 1, 46, "VST3q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1108 = VST3q8b
+ { 1109, 11, 0, 46, "VST4LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1109 = VST4LNd16
+ { 1110, 11, 0, 46, "VST4LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1110 = VST4LNd32
+ { 1111, 11, 0, 46, "VST4LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1111 = VST4LNd8
+ { 1112, 11, 0, 46, "VST4LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1112 = VST4LNq16a
+ { 1113, 11, 0, 46, "VST4LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1113 = VST4LNq16b
+ { 1114, 11, 0, 46, "VST4LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1114 = VST4LNq32a
+ { 1115, 11, 0, 46, "VST4LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1115 = VST4LNq32b
+ { 1116, 10, 0, 46, "VST4d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1116 = VST4d16
+ { 1117, 10, 0, 46, "VST4d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1117 = VST4d32
+ { 1118, 10, 0, 46, "VST4d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1118 = VST4d64
+ { 1119, 10, 0, 46, "VST4d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #1119 = VST4d8
+ { 1120, 11, 1, 46, "VST4q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1120 = VST4q16a
+ { 1121, 11, 1, 46, "VST4q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1121 = VST4q16b
+ { 1122, 11, 1, 46, "VST4q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1122 = VST4q32a
+ { 1123, 11, 1, 46, "VST4q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1123 = VST4q32b
+ { 1124, 11, 1, 46, "VST4q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1124 = VST4q8a
+ { 1125, 11, 1, 46, "VST4q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1125 = VST4q8b
+ { 1126, 5, 0, 85, "VSTMD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #1126 = VSTMD
+ { 1127, 5, 0, 85, "VSTMS", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo28 }, // Inst #1127 = VSTMS
+ { 1128, 5, 0, 84, "VSTRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo80 }, // Inst #1128 = VSTRD
+ { 1129, 5, 0, 85, "VSTRQ", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1129 = VSTRQ
+ { 1130, 5, 0, 83, "VSTRS", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #1130 = VSTRS
+ { 1131, 5, 1, 62, "VSUBD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1131 = VSUBD
+ { 1132, 5, 1, 3, "VSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1132 = VSUBHNv2i32
+ { 1133, 5, 1, 3, "VSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1133 = VSUBHNv4i16
+ { 1134, 5, 1, 3, "VSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo53 }, // Inst #1134 = VSUBHNv8i8
+ { 1135, 5, 1, 44, "VSUBLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1135 = VSUBLsv2i64
+ { 1136, 5, 1, 44, "VSUBLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1136 = VSUBLsv4i32
+ { 1137, 5, 1, 44, "VSUBLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1137 = VSUBLsv8i16
+ { 1138, 5, 1, 44, "VSUBLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1138 = VSUBLuv2i64
+ { 1139, 5, 1, 44, "VSUBLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1139 = VSUBLuv4i32
+ { 1140, 5, 1, 44, "VSUBLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo46 }, // Inst #1140 = VSUBLuv8i16
+ { 1141, 5, 1, 61, "VSUBS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo54 }, // Inst #1141 = VSUBS
+ { 1142, 5, 1, 47, "VSUBWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1142 = VSUBWsv2i64
+ { 1143, 5, 1, 47, "VSUBWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1143 = VSUBWsv4i32
+ { 1144, 5, 1, 47, "VSUBWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1144 = VSUBWsv8i16
+ { 1145, 5, 1, 47, "VSUBWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1145 = VSUBWuv2i64
+ { 1146, 5, 1, 47, "VSUBWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1146 = VSUBWuv4i32
+ { 1147, 5, 1, 47, "VSUBWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo55 }, // Inst #1147 = VSUBWuv8i16
+ { 1148, 5, 1, 1, "VSUBfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1148 = VSUBfd
+ { 1149, 5, 1, 1, "VSUBfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo56 }, // Inst #1149 = VSUBfd_sfp
+ { 1150, 5, 1, 2, "VSUBfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1150 = VSUBfq
+ { 1151, 5, 1, 48, "VSUBv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1151 = VSUBv16i8
+ { 1152, 5, 1, 47, "VSUBv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1152 = VSUBv1i64
+ { 1153, 5, 1, 47, "VSUBv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1153 = VSUBv2i32
+ { 1154, 5, 1, 48, "VSUBv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1154 = VSUBv2i64
+ { 1155, 5, 1, 47, "VSUBv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1155 = VSUBv4i16
+ { 1156, 5, 1, 48, "VSUBv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1156 = VSUBv4i32
+ { 1157, 5, 1, 48, "VSUBv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1157 = VSUBv8i16
+ { 1158, 5, 1, 47, "VSUBv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1158 = VSUBv8i8
+ { 1159, 5, 1, 49, "VTBL1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1159 = VTBL1
+ { 1160, 6, 1, 50, "VTBL2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1160 = VTBL2
+ { 1161, 7, 1, 51, "VTBL3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1161 = VTBL3
+ { 1162, 8, 1, 52, "VTBL4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1162 = VTBL4
+ { 1163, 6, 1, 53, "VTBX1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo45 }, // Inst #1163 = VTBX1
+ { 1164, 7, 1, 54, "VTBX2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #1164 = VTBX2
+ { 1165, 8, 1, 55, "VTBX3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1165 = VTBX3
+ { 1166, 9, 1, 56, "VTBX4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1166 = VTBX4
+ { 1167, 4, 1, 65, "VTOSIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1167 = VTOSIZD
+ { 1168, 4, 1, 70, "VTOSIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #1168 = VTOSIZS
+ { 1169, 4, 1, 65, "VTOUIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #1169 = VTOUIZD
+ { 1170, 4, 1, 70, "VTOUIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #1170 = VTOUIZS
+ { 1171, 6, 2, 35, "VTRNd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1171 = VTRNd16
+ { 1172, 6, 2, 35, "VTRNd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1172 = VTRNd32
+ { 1173, 6, 2, 35, "VTRNd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1173 = VTRNd8
+ { 1174, 6, 2, 36, "VTRNq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1174 = VTRNq16
+ { 1175, 6, 2, 36, "VTRNq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1175 = VTRNq32
+ { 1176, 6, 2, 36, "VTRNq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1176 = VTRNq8
+ { 1177, 5, 1, 4, "VTSTv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1177 = VTSTv16i8
+ { 1178, 5, 1, 3, "VTSTv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1178 = VTSTv2i32
+ { 1179, 5, 1, 3, "VTSTv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1179 = VTSTv4i16
+ { 1180, 5, 1, 4, "VTSTv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1180 = VTSTv4i32
+ { 1181, 5, 1, 4, "VTSTv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo48 }, // Inst #1181 = VTSTv8i16
+ { 1182, 5, 1, 3, "VTSTv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo47 }, // Inst #1182 = VTSTv8i8
+ { 1183, 4, 1, 67, "VUITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1183 = VUITOD
+ { 1184, 4, 1, 68, "VUITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo50 }, // Inst #1184 = VUITOS
+ { 1185, 6, 2, 35, "VUZPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1185 = VUZPd16
+ { 1186, 6, 2, 35, "VUZPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1186 = VUZPd32
+ { 1187, 6, 2, 35, "VUZPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1187 = VUZPd8
+ { 1188, 6, 2, 37, "VUZPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1188 = VUZPq16
+ { 1189, 6, 2, 37, "VUZPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1189 = VUZPq32
+ { 1190, 6, 2, 37, "VUZPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1190 = VUZPq8
+ { 1191, 6, 2, 35, "VZIPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1191 = VZIPd16
+ { 1192, 6, 2, 35, "VZIPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1192 = VZIPd32
+ { 1193, 6, 2, 35, "VZIPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1193 = VZIPd8
+ { 1194, 6, 2, 37, "VZIPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1194 = VZIPq16
+ { 1195, 6, 2, 37, "VZIPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1195 = VZIPq32
+ { 1196, 6, 2, 37, "VZIPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo127 }, // Inst #1196 = VZIPq8
+ { 1197, 3, 1, 88, "t2ADCSri", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #1197 = t2ADCSri
+ { 1198, 3, 1, 89, "t2ADCSrr", 0|(1<<TID::Commutable), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #1198 = t2ADCSrr
+ { 1199, 4, 1, 90, "t2ADCSrs", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo128 }, // Inst #1199 = t2ADCSrs
+ { 1200, 6, 1, 88, "t2ADCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #1200 = t2ADCri
+ { 1201, 6, 1, 89, "t2ADCrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #1201 = t2ADCrr
+ { 1202, 7, 1, 90, "t2ADCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo37 }, // Inst #1202 = t2ADCrs
+ { 1203, 5, 1, 88, "t2ADDSri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1203 = t2ADDSri
+ { 1204, 5, 1, 89, "t2ADDSrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1204 = t2ADDSrr
+ { 1205, 6, 1, 90, "t2ADDSrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1205 = t2ADDSrs
+ { 1206, 6, 1, 88, "t2ADDrSPi", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1206 = t2ADDrSPi
+ { 1207, 5, 1, 88, "t2ADDrSPi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1207 = t2ADDrSPi12
+ { 1208, 7, 1, 90, "t2ADDrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1208 = t2ADDrSPs
+ { 1209, 6, 1, 88, "t2ADDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1209 = t2ADDri
+ { 1210, 6, 1, 88, "t2ADDri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1210 = t2ADDri12
+ { 1211, 6, 1, 89, "t2ADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1211 = t2ADDrr
+ { 1212, 7, 1, 90, "t2ADDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1212 = t2ADDrs
+ { 1213, 6, 1, 88, "t2ANDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1213 = t2ANDri
+ { 1214, 6, 1, 89, "t2ANDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1214 = t2ANDrr
+ { 1215, 7, 1, 90, "t2ANDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1215 = t2ANDrs
+ { 1216, 6, 1, 113, "t2ASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1216 = t2ASRri
+ { 1217, 6, 1, 114, "t2ASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1217 = t2ASRrr
+ { 1218, 1, 0, 0, "t2B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1218 = t2B
+ { 1219, 5, 1, 126, "t2BFC", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1219 = t2BFC
+ { 1220, 6, 1, 88, "t2BICri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1220 = t2BICri
+ { 1221, 6, 1, 89, "t2BICrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1221 = t2BICrr
+ { 1222, 7, 1, 90, "t2BICrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1222 = t2BICrs
+ { 1223, 4, 0, 0, "t2BR_JT", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo17 }, // Inst #1223 = t2BR_JT
+ { 1224, 3, 0, 0, "t2Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1224 = t2Bcc
+ { 1225, 4, 1, 125, "t2CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1225 = t2CLZ
+ { 1226, 4, 0, 97, "t2CMNzri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1226 = t2CMNzri
+ { 1227, 4, 0, 98, "t2CMNzrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1227 = t2CMNzrr
+ { 1228, 5, 0, 99, "t2CMNzrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1228 = t2CMNzrs
+ { 1229, 4, 0, 97, "t2CMPri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1229 = t2CMPri
+ { 1230, 4, 0, 98, "t2CMPrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1230 = t2CMPrr
+ { 1231, 5, 0, 99, "t2CMPrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1231 = t2CMPrs
+ { 1232, 4, 0, 97, "t2CMPzri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1232 = t2CMPzri
+ { 1233, 4, 0, 98, "t2CMPzrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1233 = t2CMPzrr
+ { 1234, 5, 0, 99, "t2CMPzrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1234 = t2CMPzrs
+ { 1235, 6, 1, 88, "t2EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1235 = t2EORri
+ { 1236, 6, 1, 89, "t2EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1236 = t2EORrr
+ { 1237, 7, 1, 90, "t2EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1237 = t2EORrs
+ { 1238, 2, 0, 92, "t2IT", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo129 }, // Inst #1238 = t2IT
+ { 1239, 0, 0, 128, "t2Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #1239 = t2Int_MemBarrierV7
+ { 1240, 0, 0, 128, "t2Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #1240 = t2Int_SyncBarrierV7
+ { 1241, 1, 0, 128, "t2Int_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList6, Barriers3, OperandInfo16 }, // Inst #1241 = t2Int_eh_sjlj_setjmp
+ { 1242, 5, 0, 103, "t2LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1242 = t2LDM
+ { 1243, 5, 0, 0, "t2LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1243 = t2LDM_RET
+ { 1244, 6, 2, 102, "t2LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1244 = t2LDRB_POST
+ { 1245, 6, 2, 102, "t2LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1245 = t2LDRB_PRE
+ { 1246, 5, 1, 101, "t2LDRBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1246 = t2LDRBi12
+ { 1247, 5, 1, 101, "t2LDRBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1247 = t2LDRBi8
+ { 1248, 4, 1, 101, "t2LDRBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1248 = t2LDRBpci
+ { 1249, 6, 1, 104, "t2LDRBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1249 = t2LDRBs
+ { 1250, 6, 2, 101, "t2LDRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1250 = t2LDRDi8
+ { 1251, 5, 2, 101, "t2LDRDpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1251 = t2LDRDpci
+ { 1252, 4, 1, 128, "t2LDREX", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1252 = t2LDREX
+ { 1253, 4, 1, 128, "t2LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1253 = t2LDREXB
+ { 1254, 5, 2, 128, "t2LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1254 = t2LDREXD
+ { 1255, 4, 1, 128, "t2LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1255 = t2LDREXH
+ { 1256, 6, 2, 102, "t2LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1256 = t2LDRH_POST
+ { 1257, 6, 2, 102, "t2LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1257 = t2LDRH_PRE
+ { 1258, 5, 1, 101, "t2LDRHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1258 = t2LDRHi12
+ { 1259, 5, 1, 101, "t2LDRHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1259 = t2LDRHi8
+ { 1260, 4, 1, 101, "t2LDRHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1260 = t2LDRHpci
+ { 1261, 6, 1, 104, "t2LDRHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1261 = t2LDRHs
+ { 1262, 6, 2, 102, "t2LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1262 = t2LDRSB_POST
+ { 1263, 6, 2, 102, "t2LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1263 = t2LDRSB_PRE
+ { 1264, 5, 1, 101, "t2LDRSBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1264 = t2LDRSBi12
+ { 1265, 5, 1, 101, "t2LDRSBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1265 = t2LDRSBi8
+ { 1266, 4, 1, 101, "t2LDRSBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1266 = t2LDRSBpci
+ { 1267, 6, 1, 104, "t2LDRSBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1267 = t2LDRSBs
+ { 1268, 6, 2, 102, "t2LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1268 = t2LDRSH_POST
+ { 1269, 6, 2, 102, "t2LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1269 = t2LDRSH_PRE
+ { 1270, 5, 1, 101, "t2LDRSHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1270 = t2LDRSHi12
+ { 1271, 5, 1, 101, "t2LDRSHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1271 = t2LDRSHi8
+ { 1272, 4, 1, 101, "t2LDRSHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1272 = t2LDRSHpci
+ { 1273, 6, 1, 104, "t2LDRSHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1273 = t2LDRSHs
+ { 1274, 6, 2, 102, "t2LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1274 = t2LDR_POST
+ { 1275, 6, 2, 102, "t2LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo130 }, // Inst #1275 = t2LDR_PRE
+ { 1276, 5, 1, 101, "t2LDRi12", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1276 = t2LDRi12
+ { 1277, 5, 1, 101, "t2LDRi8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1277 = t2LDRi8
+ { 1278, 4, 1, 101, "t2LDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1278 = t2LDRpci
+ { 1279, 3, 1, 128, "t2LDRpci_pic", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo19 }, // Inst #1279 = t2LDRpci_pic
+ { 1280, 6, 1, 104, "t2LDRs", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1280 = t2LDRs
+ { 1281, 4, 1, 88, "t2LEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1281 = t2LEApcrel
+ { 1282, 5, 1, 88, "t2LEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo30 }, // Inst #1282 = t2LEApcrelJT
+ { 1283, 6, 1, 113, "t2LSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1283 = t2LSLri
+ { 1284, 6, 1, 114, "t2LSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1284 = t2LSLrr
+ { 1285, 6, 1, 113, "t2LSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1285 = t2LSRri
+ { 1286, 6, 1, 114, "t2LSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1286 = t2LSRrr
+ { 1287, 6, 1, 109, "t2MLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1287 = t2MLA
+ { 1288, 6, 1, 109, "t2MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1288 = t2MLS
+ { 1289, 6, 1, 95, "t2MOVCCasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo131 }, // Inst #1289 = t2MOVCCasr
+ { 1290, 5, 1, 93, "t2MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1290 = t2MOVCCi
+ { 1291, 6, 1, 95, "t2MOVCClsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo131 }, // Inst #1291 = t2MOVCClsl
+ { 1292, 6, 1, 95, "t2MOVCClsr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo131 }, // Inst #1292 = t2MOVCClsr
+ { 1293, 5, 1, 94, "t2MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #1293 = t2MOVCCr
+ { 1294, 6, 1, 95, "t2MOVCCror", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo131 }, // Inst #1294 = t2MOVCCror
+ { 1295, 5, 1, 111, "t2MOVTi16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1295 = t2MOVTi16
+ { 1296, 5, 1, 111, "t2MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1296 = t2MOVi
+ { 1297, 4, 1, 111, "t2MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1297 = t2MOVi16
+ { 1298, 4, 1, 111, "t2MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(2<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1298 = t2MOVi32imm
+ { 1299, 5, 1, 112, "t2MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #1299 = t2MOVr
+ { 1300, 5, 1, 113, "t2MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo36 }, // Inst #1300 = t2MOVrx
+ { 1301, 2, 1, 113, "t2MOVsra_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo132 }, // Inst #1301 = t2MOVsra_flag
+ { 1302, 2, 1, 113, "t2MOVsrl_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo132 }, // Inst #1302 = t2MOVsrl_flag
+ { 1303, 5, 1, 116, "t2MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1303 = t2MUL
+ { 1304, 5, 1, 111, "t2MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1304 = t2MVNi
+ { 1305, 4, 1, 112, "t2MVNr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1305 = t2MVNr
+ { 1306, 5, 1, 113, "t2MVNs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1306 = t2MVNs
+ { 1307, 6, 1, 88, "t2ORNri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1307 = t2ORNri
+ { 1308, 6, 1, 89, "t2ORNrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1308 = t2ORNrr
+ { 1309, 7, 1, 90, "t2ORNrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1309 = t2ORNrs
+ { 1310, 6, 1, 88, "t2ORRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1310 = t2ORRri
+ { 1311, 6, 1, 89, "t2ORRrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1311 = t2ORRrr
+ { 1312, 7, 1, 90, "t2ORRrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1312 = t2ORRrs
+ { 1313, 6, 1, 90, "t2PKHBT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1313 = t2PKHBT
+ { 1314, 6, 1, 90, "t2PKHTB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1314 = t2PKHTB
+ { 1315, 4, 1, 125, "t2RBIT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1315 = t2RBIT
+ { 1316, 4, 1, 125, "t2REV", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1316 = t2REV
+ { 1317, 4, 1, 125, "t2REV16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1317 = t2REV16
+ { 1318, 4, 1, 125, "t2REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1318 = t2REVSH
+ { 1319, 6, 1, 113, "t2RORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1319 = t2RORri
+ { 1320, 6, 1, 114, "t2RORrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1320 = t2RORrr
+ { 1321, 4, 1, 88, "t2RSBSri", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo133 }, // Inst #1321 = t2RSBSri
+ { 1322, 5, 1, 90, "t2RSBSrs", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo134 }, // Inst #1322 = t2RSBSrs
+ { 1323, 5, 1, 88, "t2RSBri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1323 = t2RSBri
+ { 1324, 6, 1, 90, "t2RSBrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1324 = t2RSBrs
+ { 1325, 3, 1, 88, "t2SBCSri", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #1325 = t2SBCSri
+ { 1326, 3, 1, 89, "t2SBCSrr", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #1326 = t2SBCSrr
+ { 1327, 4, 1, 90, "t2SBCSrs", 0, 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo128 }, // Inst #1327 = t2SBCSrs
+ { 1328, 6, 1, 88, "t2SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #1328 = t2SBCri
+ { 1329, 6, 1, 89, "t2SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #1329 = t2SBCrr
+ { 1330, 7, 1, 90, "t2SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo37 }, // Inst #1330 = t2SBCrs
+ { 1331, 6, 1, 88, "t2SBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #1331 = t2SBFX
+ { 1332, 6, 1, 108, "t2SMLABB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1332 = t2SMLABB
+ { 1333, 6, 1, 108, "t2SMLABT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1333 = t2SMLABT
+ { 1334, 6, 2, 110, "t2SMLAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1334 = t2SMLAL
+ { 1335, 6, 1, 108, "t2SMLATB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1335 = t2SMLATB
+ { 1336, 6, 1, 108, "t2SMLATT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1336 = t2SMLATT
+ { 1337, 6, 1, 108, "t2SMLAWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1337 = t2SMLAWB
+ { 1338, 6, 1, 108, "t2SMLAWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1338 = t2SMLAWT
+ { 1339, 6, 1, 109, "t2SMMLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1339 = t2SMMLA
+ { 1340, 6, 1, 109, "t2SMMLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1340 = t2SMMLS
+ { 1341, 5, 1, 116, "t2SMMUL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1341 = t2SMMUL
+ { 1342, 5, 1, 116, "t2SMULBB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1342 = t2SMULBB
+ { 1343, 5, 1, 116, "t2SMULBT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1343 = t2SMULBT
+ { 1344, 6, 2, 117, "t2SMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1344 = t2SMULL
+ { 1345, 5, 1, 116, "t2SMULTB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1345 = t2SMULTB
+ { 1346, 5, 1, 116, "t2SMULTT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1346 = t2SMULTT
+ { 1347, 5, 1, 115, "t2SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1347 = t2SMULWB
+ { 1348, 5, 1, 115, "t2SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1348 = t2SMULWT
+ { 1349, 5, 0, 120, "t2STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1349 = t2STM
+ { 1350, 6, 1, 119, "t2STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1350 = t2STRB_POST
+ { 1351, 6, 1, 119, "t2STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1351 = t2STRB_PRE
+ { 1352, 5, 0, 118, "t2STRBi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1352 = t2STRBi12
+ { 1353, 5, 0, 118, "t2STRBi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1353 = t2STRBi8
+ { 1354, 6, 0, 121, "t2STRBs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1354 = t2STRBs
+ { 1355, 6, 0, 121, "t2STRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1355 = t2STRDi8
+ { 1356, 5, 1, 128, "t2STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1356 = t2STREX
+ { 1357, 5, 1, 128, "t2STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1357 = t2STREXB
+ { 1358, 6, 1, 128, "t2STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo41 }, // Inst #1358 = t2STREXD
+ { 1359, 5, 1, 128, "t2STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #1359 = t2STREXH
+ { 1360, 6, 1, 119, "t2STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1360 = t2STRH_POST
+ { 1361, 6, 1, 119, "t2STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1361 = t2STRH_PRE
+ { 1362, 5, 0, 118, "t2STRHi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1362 = t2STRHi12
+ { 1363, 5, 0, 118, "t2STRHi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1363 = t2STRHi8
+ { 1364, 6, 0, 121, "t2STRHs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1364 = t2STRHs
+ { 1365, 6, 1, 119, "t2STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1365 = t2STR_POST
+ { 1366, 6, 1, 119, "t2STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo135 }, // Inst #1366 = t2STR_PRE
+ { 1367, 5, 0, 118, "t2STRi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1367 = t2STRi12
+ { 1368, 5, 0, 118, "t2STRi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1368 = t2STRi8
+ { 1369, 6, 0, 121, "t2STRs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1369 = t2STRs
+ { 1370, 5, 1, 88, "t2SUBSri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1370 = t2SUBSri
+ { 1371, 5, 1, 89, "t2SUBSrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1371 = t2SUBSrr
+ { 1372, 6, 1, 90, "t2SUBSrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1372 = t2SUBSrs
+ { 1373, 6, 1, 88, "t2SUBrSPi", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1373 = t2SUBrSPi
+ { 1374, 5, 1, 88, "t2SUBrSPi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1374 = t2SUBrSPi12
+ { 1375, 3, 1, 128, "t2SUBrSPi12_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1375 = t2SUBrSPi12_
+ { 1376, 3, 1, 128, "t2SUBrSPi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1376 = t2SUBrSPi_
+ { 1377, 7, 1, 90, "t2SUBrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1377 = t2SUBrSPs
+ { 1378, 4, 1, 128, "t2SUBrSPs_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo128 }, // Inst #1378 = t2SUBrSPs_
+ { 1379, 6, 1, 88, "t2SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1379 = t2SUBri
+ { 1380, 6, 1, 88, "t2SUBri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1380 = t2SUBri12
+ { 1381, 6, 1, 89, "t2SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1381 = t2SUBrr
+ { 1382, 7, 1, 90, "t2SUBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #1382 = t2SUBrs
+ { 1383, 5, 1, 89, "t2SXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1383 = t2SXTABrr
+ { 1384, 6, 1, 91, "t2SXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1384 = t2SXTABrr_rot
+ { 1385, 5, 1, 89, "t2SXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1385 = t2SXTAHrr
+ { 1386, 6, 1, 91, "t2SXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1386 = t2SXTAHrr_rot
+ { 1387, 4, 1, 125, "t2SXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1387 = t2SXTBr
+ { 1388, 5, 1, 126, "t2SXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1388 = t2SXTBr_rot
+ { 1389, 4, 1, 125, "t2SXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1389 = t2SXTHr
+ { 1390, 5, 1, 126, "t2SXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1390 = t2SXTHr_rot
+ { 1391, 3, 0, 0, "t2TBB", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1391 = t2TBB
+ { 1392, 3, 0, 0, "t2TBH", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #1392 = t2TBH
+ { 1393, 4, 0, 97, "t2TEQri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1393 = t2TEQri
+ { 1394, 4, 0, 98, "t2TEQrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1394 = t2TEQrr
+ { 1395, 5, 0, 99, "t2TEQrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1395 = t2TEQrs
+ { 1396, 0, 0, 0, "t2TPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList7, Barriers1, 0 }, // Inst #1396 = t2TPsoft
+ { 1397, 4, 0, 97, "t2TSTri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1397 = t2TSTri
+ { 1398, 4, 0, 98, "t2TSTrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1398 = t2TSTrr
+ { 1399, 5, 0, 99, "t2TSTrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1399 = t2TSTrs
+ { 1400, 6, 1, 88, "t2UBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #1400 = t2UBFX
+ { 1401, 6, 2, 110, "t2UMAAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1401 = t2UMAAL
+ { 1402, 6, 2, 110, "t2UMLAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1402 = t2UMLAL
+ { 1403, 6, 2, 117, "t2UMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1403 = t2UMULL
+ { 1404, 5, 1, 89, "t2UXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1404 = t2UXTABrr
+ { 1405, 6, 1, 91, "t2UXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1405 = t2UXTABrr_rot
+ { 1406, 5, 1, 89, "t2UXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1406 = t2UXTAHrr
+ { 1407, 6, 1, 91, "t2UXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #1407 = t2UXTAHrr_rot
+ { 1408, 4, 1, 125, "t2UXTB16r", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1408 = t2UXTB16r
+ { 1409, 5, 1, 126, "t2UXTB16r_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1409 = t2UXTB16r_rot
+ { 1410, 4, 1, 125, "t2UXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1410 = t2UXTBr
+ { 1411, 5, 1, 126, "t2UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1411 = t2UXTBr_rot
+ { 1412, 4, 1, 125, "t2UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1412 = t2UXTHr
+ { 1413, 5, 1, 126, "t2UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1413 = t2UXTHr_rot
+ { 1414, 6, 2, 89, "tADC", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo136 }, // Inst #1414 = tADC
+ { 1415, 5, 1, 89, "tADDhirr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #1415 = tADDhirr
+ { 1416, 6, 2, 88, "tADDi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1416 = tADDi3
+ { 1417, 6, 2, 88, "tADDi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo138 }, // Inst #1417 = tADDi8
+ { 1418, 2, 1, 88, "tADDrPCi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo139 }, // Inst #1418 = tADDrPCi
+ { 1419, 3, 1, 89, "tADDrSP", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo140 }, // Inst #1419 = tADDrSP
+ { 1420, 3, 1, 88, "tADDrSPi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo141 }, // Inst #1420 = tADDrSPi
+ { 1421, 6, 2, 89, "tADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo142 }, // Inst #1421 = tADDrr
+ { 1422, 3, 1, 88, "tADDspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1422 = tADDspi
+ { 1423, 3, 1, 89, "tADDspr", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo140 }, // Inst #1423 = tADDspr
+ { 1424, 3, 1, 128, "tADDspr_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo3 }, // Inst #1424 = tADDspr_
+ { 1425, 1, 0, 128, "tADJCALLSTACKDOWN", 0, 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo14 }, // Inst #1425 = tADJCALLSTACKDOWN
+ { 1426, 2, 0, 128, "tADJCALLSTACKUP", 0, 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo129 }, // Inst #1426 = tADJCALLSTACKUP
+ { 1427, 6, 2, 89, "tAND", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1427 = tAND
+ { 1428, 3, 1, 128, "tANDsp", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, ImplicitList1, Barriers1, OperandInfo144 }, // Inst #1428 = tANDsp
+ { 1429, 6, 2, 113, "tASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1429 = tASRri
+ { 1430, 6, 2, 114, "tASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1430 = tASRrr
+ { 1431, 1, 0, 0, "tB", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1431 = tB
+ { 1432, 6, 2, 89, "tBIC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1432 = tBIC
+ { 1433, 1, 0, 0, "tBL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #1433 = tBL
+ { 1434, 1, 0, 0, "tBLXi", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #1434 = tBLXi
+ { 1435, 1, 0, 0, "tBLXi_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #1435 = tBLXi_r9
+ { 1436, 1, 0, 0, "tBLXr", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #1436 = tBLXr
+ { 1437, 1, 0, 0, "tBLXr_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #1437 = tBLXr_r9
+ { 1438, 1, 0, 0, "tBLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #1438 = tBLr9
+ { 1439, 1, 0, 0, "tBRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #1439 = tBRIND
+ { 1440, 3, 0, 0, "tBR_JTr", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo145 }, // Inst #1440 = tBR_JTr
+ { 1441, 1, 0, 0, "tBX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo146 }, // Inst #1441 = tBX
+ { 1442, 0, 0, 0, "tBX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 }, // Inst #1442 = tBX_RET
+ { 1443, 1, 0, 0, "tBX_RET_vararg", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo146 }, // Inst #1443 = tBX_RET_vararg
+ { 1444, 1, 0, 0, "tBXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo146 }, // Inst #1444 = tBXr9
+ { 1445, 3, 0, 0, "tBcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1445 = tBcc
+ { 1446, 1, 0, 0, "tBfar", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, ImplicitList8, NULL, OperandInfo14 }, // Inst #1446 = tBfar
+ { 1447, 2, 0, 0, "tCBNZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo139 }, // Inst #1447 = tCBNZ
+ { 1448, 2, 0, 0, "tCBZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo139 }, // Inst #1448 = tCBZ
+ { 1449, 4, 0, 98, "tCMNz", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo147 }, // Inst #1449 = tCMNz
+ { 1450, 4, 0, 98, "tCMPhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1450 = tCMPhir
+ { 1451, 4, 0, 97, "tCMPi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo148 }, // Inst #1451 = tCMPi8
+ { 1452, 4, 0, 98, "tCMPr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo147 }, // Inst #1452 = tCMPr
+ { 1453, 4, 0, 98, "tCMPzhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1453 = tCMPzhir
+ { 1454, 4, 0, 97, "tCMPzi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo148 }, // Inst #1454 = tCMPzi8
+ { 1455, 4, 0, 98, "tCMPzr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo147 }, // Inst #1455 = tCMPzr
+ { 1456, 6, 2, 89, "tEOR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1456 = tEOR
+ { 1457, 1, 0, 128, "tInt_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList9, Barriers4, OperandInfo16 }, // Inst #1457 = tInt_eh_sjlj_setjmp
+ { 1458, 5, 0, 103, "tLDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1458 = tLDM
+ { 1459, 6, 1, 104, "tLDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1459 = tLDR
+ { 1460, 6, 1, 104, "tLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1460 = tLDRB
+ { 1461, 6, 1, 104, "tLDRBi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1461 = tLDRBi
+ { 1462, 6, 1, 104, "tLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1462 = tLDRH
+ { 1463, 6, 1, 104, "tLDRHi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1463 = tLDRHi
+ { 1464, 5, 1, 104, "tLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1464 = tLDRSB
+ { 1465, 5, 1, 104, "tLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1465 = tLDRSH
+ { 1466, 4, 1, 101, "tLDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1466 = tLDRcp
+ { 1467, 6, 1, 104, "tLDRi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1467 = tLDRi
+ { 1468, 4, 1, 101, "tLDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1468 = tLDRpci
+ { 1469, 3, 1, 128, "tLDRpci_pic", 0|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo19 }, // Inst #1469 = tLDRpci_pic
+ { 1470, 5, 1, 101, "tLDRspi", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1470 = tLDRspi
+ { 1471, 4, 1, 88, "tLEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1471 = tLEApcrel
+ { 1472, 5, 1, 88, "tLEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo152 }, // Inst #1472 = tLEApcrelJT
+ { 1473, 6, 2, 113, "tLSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1473 = tLSLri
+ { 1474, 6, 2, 114, "tLSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1474 = tLSLrr
+ { 1475, 6, 2, 113, "tLSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1475 = tLSRri
+ { 1476, 6, 2, 114, "tLSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1476 = tLSRrr
+ { 1477, 5, 1, 93, "tMOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1477 = tMOVCCi
+ { 1478, 5, 1, 94, "tMOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #1478 = tMOVCCr
+ { 1479, 5, 1, 128, "tMOVCCr_pseudo", 0|(1<<TID::Predicable)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo150 }, // Inst #1479 = tMOVCCr_pseudo
+ { 1480, 2, 1, 112, "tMOVSr", 0, 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo153 }, // Inst #1480 = tMOVSr
+ { 1481, 2, 1, 112, "tMOVgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo132 }, // Inst #1481 = tMOVgpr2gpr
+ { 1482, 2, 1, 112, "tMOVgpr2tgpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1482 = tMOVgpr2tgpr
+ { 1483, 5, 2, 111, "tMOVi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo155 }, // Inst #1483 = tMOVi8
+ { 1484, 2, 1, 112, "tMOVr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo153 }, // Inst #1484 = tMOVr
+ { 1485, 2, 1, 112, "tMOVtgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1485 = tMOVtgpr2gpr
+ { 1486, 6, 2, 116, "tMUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1486 = tMUL
+ { 1487, 5, 2, 112, "tMVN", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1487 = tMVN
+ { 1488, 6, 2, 89, "tORR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1488 = tORR
+ { 1489, 3, 1, 89, "tPICADD", 0|(1<<TID::NotDuplicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1489 = tPICADD
+ { 1490, 3, 0, 0, "tPOP", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, NULL, OperandInfo158 }, // Inst #1490 = tPOP
+ { 1491, 3, 0, 0, "tPOP_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo158 }, // Inst #1491 = tPOP_RET
+ { 1492, 3, 0, 0, "tPUSH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, NULL, OperandInfo158 }, // Inst #1492 = tPUSH
+ { 1493, 4, 1, 125, "tREV", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1493 = tREV
+ { 1494, 4, 1, 125, "tREV16", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1494 = tREV16
+ { 1495, 4, 1, 125, "tREVSH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1495 = tREVSH
+ { 1496, 6, 2, 114, "tROR", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo136 }, // Inst #1496 = tROR
+ { 1497, 5, 2, 88, "tRSB", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1497 = tRSB
+ { 1498, 5, 1, 101, "tRestore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1498 = tRestore
+ { 1499, 6, 2, 89, "tSBC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo136 }, // Inst #1499 = tSBC
+ { 1500, 5, 0, 120, "tSTM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1500 = tSTM
+ { 1501, 6, 0, 121, "tSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1501 = tSTR
+ { 1502, 6, 0, 121, "tSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1502 = tSTRB
+ { 1503, 6, 0, 121, "tSTRBi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1503 = tSTRBi
{ 1504, 6, 0, 121, "tSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1504 = tSTRH
- { 1505, 5, 0, 118, "tSTRspi", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1505 = tSTRspi
- { 1506, 6, 2, 88, "tSUBi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1506 = tSUBi3
- { 1507, 6, 2, 88, "tSUBi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo138 }, // Inst #1507 = tSUBi8
- { 1508, 6, 2, 89, "tSUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo142 }, // Inst #1508 = tSUBrr
- { 1509, 3, 1, 88, "tSUBspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1509 = tSUBspi
- { 1510, 3, 1, 128, "tSUBspi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1510 = tSUBspi_
- { 1511, 4, 1, 125, "tSXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1511 = tSXTB
- { 1512, 4, 1, 125, "tSXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1512 = tSXTH
- { 1513, 5, 0, 118, "tSpill", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1513 = tSpill
- { 1514, 0, 0, 0, "tTPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList10, NULL, 0 }, // Inst #1514 = tTPsoft
- { 1515, 4, 0, 98, "tTST", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo147 }, // Inst #1515 = tTST
- { 1516, 4, 1, 125, "tUXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1516 = tUXTB
- { 1517, 4, 1, 125, "tUXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1517 = tUXTH
+ { 1505, 6, 0, 121, "tSTRHi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1505 = tSTRHi
+ { 1506, 6, 0, 121, "tSTRi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1506 = tSTRi
+ { 1507, 5, 0, 118, "tSTRspi", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1507 = tSTRspi
+ { 1508, 6, 2, 88, "tSUBi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo137 }, // Inst #1508 = tSUBi3
+ { 1509, 6, 2, 88, "tSUBi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo138 }, // Inst #1509 = tSUBi8
+ { 1510, 6, 2, 89, "tSUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo142 }, // Inst #1510 = tSUBrr
+ { 1511, 3, 1, 88, "tSUBspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo143 }, // Inst #1511 = tSUBspi
+ { 1512, 3, 1, 128, "tSUBspi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1512 = tSUBspi_
+ { 1513, 4, 1, 125, "tSXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1513 = tSXTB
+ { 1514, 4, 1, 125, "tSXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1514 = tSXTH
+ { 1515, 5, 0, 118, "tSpill", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1515 = tSpill
+ { 1516, 0, 0, 0, "tTPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList10, NULL, 0 }, // Inst #1516 = tTPsoft
+ { 1517, 4, 0, 98, "tTST", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo147 }, // Inst #1517 = tTST
+ { 1518, 4, 1, 125, "tUXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1518 = tUXTB
+ { 1519, 4, 1, 125, "tUXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo147 }, // Inst #1519 = tUXTH
};
} // End llvm namespace
diff --git a/libclamav/c++/ARMGenInstrNames.inc b/libclamav/c++/ARMGenInstrNames.inc
index 2ab6a5a..6fe2c7f 100644
--- a/libclamav/c++/ARMGenInstrNames.inc
+++ b/libclamav/c++/ARMGenInstrNames.inc
@@ -21,1514 +21,1516 @@ namespace ARM {
IMPLICIT_DEF = 8,
SUBREG_TO_REG = 9,
COPY_TO_REGCLASS = 10,
- ADCSSri = 11,
- ADCSSrr = 12,
- ADCSSrs = 13,
- ADCri = 14,
- ADCrr = 15,
- ADCrs = 16,
- ADDSri = 17,
- ADDSrr = 18,
- ADDSrs = 19,
- ADDri = 20,
- ADDrr = 21,
- ADDrs = 22,
- ADJCALLSTACKDOWN = 23,
- ADJCALLSTACKUP = 24,
- ANDri = 25,
- ANDrr = 26,
- ANDrs = 27,
- ATOMIC_CMP_SWAP_I16 = 28,
- ATOMIC_CMP_SWAP_I32 = 29,
- ATOMIC_CMP_SWAP_I8 = 30,
- ATOMIC_LOAD_ADD_I16 = 31,
- ATOMIC_LOAD_ADD_I32 = 32,
- ATOMIC_LOAD_ADD_I8 = 33,
- ATOMIC_LOAD_AND_I16 = 34,
- ATOMIC_LOAD_AND_I32 = 35,
- ATOMIC_LOAD_AND_I8 = 36,
- ATOMIC_LOAD_NAND_I16 = 37,
- ATOMIC_LOAD_NAND_I32 = 38,
- ATOMIC_LOAD_NAND_I8 = 39,
- ATOMIC_LOAD_OR_I16 = 40,
- ATOMIC_LOAD_OR_I32 = 41,
- ATOMIC_LOAD_OR_I8 = 42,
- ATOMIC_LOAD_SUB_I16 = 43,
- ATOMIC_LOAD_SUB_I32 = 44,
- ATOMIC_LOAD_SUB_I8 = 45,
- ATOMIC_LOAD_XOR_I16 = 46,
- ATOMIC_LOAD_XOR_I32 = 47,
- ATOMIC_LOAD_XOR_I8 = 48,
- ATOMIC_SWAP_I16 = 49,
- ATOMIC_SWAP_I32 = 50,
- ATOMIC_SWAP_I8 = 51,
- B = 52,
- BFC = 53,
- BICri = 54,
- BICrr = 55,
- BICrs = 56,
- BL = 57,
- BLX = 58,
- BLXr9 = 59,
- BL_pred = 60,
- BLr9 = 61,
- BLr9_pred = 62,
- BRIND = 63,
- BR_JTadd = 64,
- BR_JTm = 65,
- BR_JTr = 66,
- BX = 67,
- BX_RET = 68,
- BXr9 = 69,
- Bcc = 70,
- CLZ = 71,
- CMNri = 72,
- CMNrr = 73,
- CMNrs = 74,
- CMNzri = 75,
- CMNzrr = 76,
- CMNzrs = 77,
- CMPri = 78,
- CMPrr = 79,
- CMPrs = 80,
- CMPzri = 81,
- CMPzrr = 82,
- CMPzrs = 83,
- CONSTPOOL_ENTRY = 84,
- EORri = 85,
- EORrr = 86,
- EORrs = 87,
- FCONSTD = 88,
- FCONSTS = 89,
- FMSTAT = 90,
- Int_MemBarrierV6 = 91,
- Int_MemBarrierV7 = 92,
- Int_SyncBarrierV6 = 93,
- Int_SyncBarrierV7 = 94,
- Int_eh_sjlj_setjmp = 95,
- LDM = 96,
- LDM_RET = 97,
- LDR = 98,
- LDRB = 99,
- LDRB_POST = 100,
- LDRB_PRE = 101,
- LDRD = 102,
- LDREX = 103,
- LDREXB = 104,
- LDREXD = 105,
- LDREXH = 106,
- LDRH = 107,
- LDRH_POST = 108,
- LDRH_PRE = 109,
- LDRSB = 110,
- LDRSB_POST = 111,
- LDRSB_PRE = 112,
- LDRSH = 113,
- LDRSH_POST = 114,
- LDRSH_PRE = 115,
- LDR_POST = 116,
- LDR_PRE = 117,
- LDRcp = 118,
- LEApcrel = 119,
- LEApcrelJT = 120,
- MLA = 121,
- MLS = 122,
- MOVCCi = 123,
- MOVCCr = 124,
- MOVCCs = 125,
- MOVTi16 = 126,
- MOVi = 127,
- MOVi16 = 128,
- MOVi2pieces = 129,
- MOVi32imm = 130,
- MOVr = 131,
- MOVrx = 132,
- MOVs = 133,
- MOVsra_flag = 134,
- MOVsrl_flag = 135,
- MUL = 136,
- MVNi = 137,
- MVNr = 138,
- MVNs = 139,
- ORRri = 140,
- ORRrr = 141,
- ORRrs = 142,
- PICADD = 143,
- PICLDR = 144,
- PICLDRB = 145,
- PICLDRH = 146,
- PICLDRSB = 147,
- PICLDRSH = 148,
- PICSTR = 149,
- PICSTRB = 150,
- PICSTRH = 151,
- PKHBT = 152,
- PKHTB = 153,
- REV = 154,
- REV16 = 155,
- REVSH = 156,
- RSBSri = 157,
- RSBSrs = 158,
- RSBri = 159,
- RSBrs = 160,
- RSCSri = 161,
- RSCSrs = 162,
- RSCri = 163,
- RSCrs = 164,
- SBCSSri = 165,
- SBCSSrr = 166,
- SBCSSrs = 167,
- SBCri = 168,
- SBCrr = 169,
- SBCrs = 170,
- SBFX = 171,
- SMLABB = 172,
- SMLABT = 173,
- SMLAL = 174,
- SMLATB = 175,
- SMLATT = 176,
- SMLAWB = 177,
- SMLAWT = 178,
- SMMLA = 179,
- SMMLS = 180,
- SMMUL = 181,
- SMULBB = 182,
- SMULBT = 183,
- SMULL = 184,
- SMULTB = 185,
- SMULTT = 186,
- SMULWB = 187,
- SMULWT = 188,
- STM = 189,
- STR = 190,
- STRB = 191,
- STRB_POST = 192,
- STRB_PRE = 193,
- STRD = 194,
- STREX = 195,
- STREXB = 196,
- STREXD = 197,
- STREXH = 198,
- STRH = 199,
- STRH_POST = 200,
- STRH_PRE = 201,
- STR_POST = 202,
- STR_PRE = 203,
- SUBSri = 204,
- SUBSrr = 205,
- SUBSrs = 206,
- SUBri = 207,
- SUBrr = 208,
- SUBrs = 209,
- SXTABrr = 210,
- SXTABrr_rot = 211,
- SXTAHrr = 212,
- SXTAHrr_rot = 213,
- SXTBr = 214,
- SXTBr_rot = 215,
- SXTHr = 216,
- SXTHr_rot = 217,
- TEQri = 218,
- TEQrr = 219,
- TEQrs = 220,
- TPsoft = 221,
- TSTri = 222,
- TSTrr = 223,
- TSTrs = 224,
- UBFX = 225,
- UMAAL = 226,
- UMLAL = 227,
- UMULL = 228,
- UXTABrr = 229,
- UXTABrr_rot = 230,
- UXTAHrr = 231,
- UXTAHrr_rot = 232,
- UXTB16r = 233,
- UXTB16r_rot = 234,
- UXTBr = 235,
- UXTBr_rot = 236,
- UXTHr = 237,
- UXTHr_rot = 238,
- VABALsv2i64 = 239,
- VABALsv4i32 = 240,
- VABALsv8i16 = 241,
- VABALuv2i64 = 242,
- VABALuv4i32 = 243,
- VABALuv8i16 = 244,
- VABAsv16i8 = 245,
- VABAsv2i32 = 246,
- VABAsv4i16 = 247,
- VABAsv4i32 = 248,
- VABAsv8i16 = 249,
- VABAsv8i8 = 250,
- VABAuv16i8 = 251,
- VABAuv2i32 = 252,
- VABAuv4i16 = 253,
- VABAuv4i32 = 254,
- VABAuv8i16 = 255,
- VABAuv8i8 = 256,
- VABDLsv2i64 = 257,
- VABDLsv4i32 = 258,
- VABDLsv8i16 = 259,
- VABDLuv2i64 = 260,
- VABDLuv4i32 = 261,
- VABDLuv8i16 = 262,
- VABDfd = 263,
- VABDfq = 264,
- VABDsv16i8 = 265,
- VABDsv2i32 = 266,
- VABDsv4i16 = 267,
- VABDsv4i32 = 268,
- VABDsv8i16 = 269,
- VABDsv8i8 = 270,
- VABDuv16i8 = 271,
- VABDuv2i32 = 272,
- VABDuv4i16 = 273,
- VABDuv4i32 = 274,
- VABDuv8i16 = 275,
- VABDuv8i8 = 276,
- VABSD = 277,
- VABSS = 278,
- VABSfd = 279,
- VABSfd_sfp = 280,
- VABSfq = 281,
- VABSv16i8 = 282,
- VABSv2i32 = 283,
- VABSv4i16 = 284,
- VABSv4i32 = 285,
- VABSv8i16 = 286,
- VABSv8i8 = 287,
- VACGEd = 288,
- VACGEq = 289,
- VACGTd = 290,
- VACGTq = 291,
- VADDD = 292,
- VADDHNv2i32 = 293,
- VADDHNv4i16 = 294,
- VADDHNv8i8 = 295,
- VADDLsv2i64 = 296,
- VADDLsv4i32 = 297,
- VADDLsv8i16 = 298,
- VADDLuv2i64 = 299,
- VADDLuv4i32 = 300,
- VADDLuv8i16 = 301,
- VADDS = 302,
- VADDWsv2i64 = 303,
- VADDWsv4i32 = 304,
- VADDWsv8i16 = 305,
- VADDWuv2i64 = 306,
- VADDWuv4i32 = 307,
- VADDWuv8i16 = 308,
- VADDfd = 309,
- VADDfd_sfp = 310,
- VADDfq = 311,
- VADDv16i8 = 312,
- VADDv1i64 = 313,
- VADDv2i32 = 314,
- VADDv2i64 = 315,
- VADDv4i16 = 316,
- VADDv4i32 = 317,
- VADDv8i16 = 318,
- VADDv8i8 = 319,
- VANDd = 320,
- VANDq = 321,
- VBICd = 322,
- VBICq = 323,
- VBSLd = 324,
- VBSLq = 325,
- VCEQfd = 326,
- VCEQfq = 327,
- VCEQv16i8 = 328,
- VCEQv2i32 = 329,
- VCEQv4i16 = 330,
- VCEQv4i32 = 331,
- VCEQv8i16 = 332,
- VCEQv8i8 = 333,
- VCGEfd = 334,
- VCGEfq = 335,
- VCGEsv16i8 = 336,
- VCGEsv2i32 = 337,
- VCGEsv4i16 = 338,
- VCGEsv4i32 = 339,
- VCGEsv8i16 = 340,
- VCGEsv8i8 = 341,
- VCGEuv16i8 = 342,
- VCGEuv2i32 = 343,
- VCGEuv4i16 = 344,
- VCGEuv4i32 = 345,
- VCGEuv8i16 = 346,
- VCGEuv8i8 = 347,
- VCGTfd = 348,
- VCGTfq = 349,
- VCGTsv16i8 = 350,
- VCGTsv2i32 = 351,
- VCGTsv4i16 = 352,
- VCGTsv4i32 = 353,
- VCGTsv8i16 = 354,
- VCGTsv8i8 = 355,
- VCGTuv16i8 = 356,
- VCGTuv2i32 = 357,
- VCGTuv4i16 = 358,
- VCGTuv4i32 = 359,
- VCGTuv8i16 = 360,
- VCGTuv8i8 = 361,
- VCLSv16i8 = 362,
- VCLSv2i32 = 363,
- VCLSv4i16 = 364,
- VCLSv4i32 = 365,
- VCLSv8i16 = 366,
- VCLSv8i8 = 367,
- VCLZv16i8 = 368,
- VCLZv2i32 = 369,
- VCLZv4i16 = 370,
- VCLZv4i32 = 371,
- VCLZv8i16 = 372,
- VCLZv8i8 = 373,
- VCMPED = 374,
- VCMPES = 375,
- VCMPEZD = 376,
- VCMPEZS = 377,
- VCNTd = 378,
- VCNTq = 379,
- VCVTDS = 380,
- VCVTSD = 381,
- VCVTf2sd = 382,
- VCVTf2sd_sfp = 383,
- VCVTf2sq = 384,
- VCVTf2ud = 385,
- VCVTf2ud_sfp = 386,
- VCVTf2uq = 387,
- VCVTf2xsd = 388,
- VCVTf2xsq = 389,
- VCVTf2xud = 390,
- VCVTf2xuq = 391,
- VCVTs2fd = 392,
- VCVTs2fd_sfp = 393,
- VCVTs2fq = 394,
- VCVTu2fd = 395,
- VCVTu2fd_sfp = 396,
- VCVTu2fq = 397,
- VCVTxs2fd = 398,
- VCVTxs2fq = 399,
- VCVTxu2fd = 400,
- VCVTxu2fq = 401,
- VDIVD = 402,
- VDIVS = 403,
- VDUP16d = 404,
- VDUP16q = 405,
- VDUP32d = 406,
- VDUP32q = 407,
- VDUP8d = 408,
- VDUP8q = 409,
- VDUPLN16d = 410,
- VDUPLN16q = 411,
- VDUPLN32d = 412,
- VDUPLN32q = 413,
- VDUPLN8d = 414,
- VDUPLN8q = 415,
- VDUPLNfd = 416,
- VDUPLNfq = 417,
- VDUPfd = 418,
- VDUPfdf = 419,
- VDUPfq = 420,
- VDUPfqf = 421,
- VEORd = 422,
- VEORq = 423,
- VEXTd16 = 424,
- VEXTd32 = 425,
- VEXTd8 = 426,
- VEXTdf = 427,
- VEXTq16 = 428,
- VEXTq32 = 429,
- VEXTq8 = 430,
- VEXTqf = 431,
- VGETLNi32 = 432,
- VGETLNs16 = 433,
- VGETLNs8 = 434,
- VGETLNu16 = 435,
- VGETLNu8 = 436,
- VHADDsv16i8 = 437,
- VHADDsv2i32 = 438,
- VHADDsv4i16 = 439,
- VHADDsv4i32 = 440,
- VHADDsv8i16 = 441,
- VHADDsv8i8 = 442,
- VHADDuv16i8 = 443,
- VHADDuv2i32 = 444,
- VHADDuv4i16 = 445,
- VHADDuv4i32 = 446,
- VHADDuv8i16 = 447,
- VHADDuv8i8 = 448,
- VHSUBsv16i8 = 449,
- VHSUBsv2i32 = 450,
- VHSUBsv4i16 = 451,
- VHSUBsv4i32 = 452,
- VHSUBsv8i16 = 453,
- VHSUBsv8i8 = 454,
- VHSUBuv16i8 = 455,
- VHSUBuv2i32 = 456,
- VHSUBuv4i16 = 457,
- VHSUBuv4i32 = 458,
- VHSUBuv8i16 = 459,
- VHSUBuv8i8 = 460,
- VLD1d16 = 461,
- VLD1d32 = 462,
- VLD1d64 = 463,
- VLD1d8 = 464,
- VLD1df = 465,
- VLD1q16 = 466,
- VLD1q32 = 467,
- VLD1q64 = 468,
- VLD1q8 = 469,
- VLD1qf = 470,
- VLD2LNd16 = 471,
- VLD2LNd32 = 472,
- VLD2LNd8 = 473,
- VLD2LNq16a = 474,
- VLD2LNq16b = 475,
- VLD2LNq32a = 476,
- VLD2LNq32b = 477,
- VLD2d16 = 478,
- VLD2d32 = 479,
- VLD2d64 = 480,
- VLD2d8 = 481,
- VLD2q16 = 482,
- VLD2q32 = 483,
- VLD2q8 = 484,
- VLD3LNd16 = 485,
- VLD3LNd32 = 486,
- VLD3LNd8 = 487,
- VLD3LNq16a = 488,
- VLD3LNq16b = 489,
- VLD3LNq32a = 490,
- VLD3LNq32b = 491,
- VLD3d16 = 492,
- VLD3d32 = 493,
- VLD3d64 = 494,
- VLD3d8 = 495,
- VLD3q16a = 496,
- VLD3q16b = 497,
- VLD3q32a = 498,
- VLD3q32b = 499,
- VLD3q8a = 500,
- VLD3q8b = 501,
- VLD4LNd16 = 502,
- VLD4LNd32 = 503,
- VLD4LNd8 = 504,
- VLD4LNq16a = 505,
- VLD4LNq16b = 506,
- VLD4LNq32a = 507,
- VLD4LNq32b = 508,
- VLD4d16 = 509,
- VLD4d32 = 510,
- VLD4d64 = 511,
- VLD4d8 = 512,
- VLD4q16a = 513,
- VLD4q16b = 514,
- VLD4q32a = 515,
- VLD4q32b = 516,
- VLD4q8a = 517,
- VLD4q8b = 518,
- VLDMD = 519,
- VLDMS = 520,
- VLDRD = 521,
- VLDRQ = 522,
- VLDRS = 523,
- VMAXfd = 524,
- VMAXfq = 525,
- VMAXsv16i8 = 526,
- VMAXsv2i32 = 527,
- VMAXsv4i16 = 528,
- VMAXsv4i32 = 529,
- VMAXsv8i16 = 530,
- VMAXsv8i8 = 531,
- VMAXuv16i8 = 532,
- VMAXuv2i32 = 533,
- VMAXuv4i16 = 534,
- VMAXuv4i32 = 535,
- VMAXuv8i16 = 536,
- VMAXuv8i8 = 537,
- VMINfd = 538,
- VMINfq = 539,
- VMINsv16i8 = 540,
- VMINsv2i32 = 541,
- VMINsv4i16 = 542,
- VMINsv4i32 = 543,
- VMINsv8i16 = 544,
- VMINsv8i8 = 545,
- VMINuv16i8 = 546,
- VMINuv2i32 = 547,
- VMINuv4i16 = 548,
- VMINuv4i32 = 549,
- VMINuv8i16 = 550,
- VMINuv8i8 = 551,
- VMLAD = 552,
- VMLALslsv2i32 = 553,
- VMLALslsv4i16 = 554,
- VMLALsluv2i32 = 555,
- VMLALsluv4i16 = 556,
- VMLALsv2i64 = 557,
- VMLALsv4i32 = 558,
- VMLALsv8i16 = 559,
- VMLALuv2i64 = 560,
- VMLALuv4i32 = 561,
- VMLALuv8i16 = 562,
- VMLAS = 563,
- VMLAfd = 564,
- VMLAfq = 565,
- VMLAslfd = 566,
- VMLAslfq = 567,
- VMLAslv2i32 = 568,
- VMLAslv4i16 = 569,
- VMLAslv4i32 = 570,
- VMLAslv8i16 = 571,
- VMLAv16i8 = 572,
- VMLAv2i32 = 573,
- VMLAv4i16 = 574,
- VMLAv4i32 = 575,
- VMLAv8i16 = 576,
- VMLAv8i8 = 577,
- VMLSD = 578,
- VMLSLslsv2i32 = 579,
- VMLSLslsv4i16 = 580,
- VMLSLsluv2i32 = 581,
- VMLSLsluv4i16 = 582,
- VMLSLsv2i64 = 583,
- VMLSLsv4i32 = 584,
- VMLSLsv8i16 = 585,
- VMLSLuv2i64 = 586,
- VMLSLuv4i32 = 587,
- VMLSLuv8i16 = 588,
- VMLSS = 589,
- VMLSfd = 590,
- VMLSfq = 591,
- VMLSslfd = 592,
- VMLSslfq = 593,
- VMLSslv2i32 = 594,
- VMLSslv4i16 = 595,
- VMLSslv4i32 = 596,
- VMLSslv8i16 = 597,
- VMLSv16i8 = 598,
- VMLSv2i32 = 599,
- VMLSv4i16 = 600,
- VMLSv4i32 = 601,
- VMLSv8i16 = 602,
- VMLSv8i8 = 603,
- VMOVD = 604,
- VMOVDRR = 605,
- VMOVDcc = 606,
- VMOVDneon = 607,
- VMOVLsv2i64 = 608,
- VMOVLsv4i32 = 609,
- VMOVLsv8i16 = 610,
- VMOVLuv2i64 = 611,
- VMOVLuv4i32 = 612,
- VMOVLuv8i16 = 613,
- VMOVNv2i32 = 614,
- VMOVNv4i16 = 615,
- VMOVNv8i8 = 616,
- VMOVQ = 617,
- VMOVRRD = 618,
- VMOVRS = 619,
- VMOVS = 620,
- VMOVSR = 621,
- VMOVScc = 622,
- VMOVv16i8 = 623,
- VMOVv1i64 = 624,
- VMOVv2i32 = 625,
- VMOVv2i64 = 626,
- VMOVv4i16 = 627,
- VMOVv4i32 = 628,
- VMOVv8i16 = 629,
- VMOVv8i8 = 630,
- VMULD = 631,
- VMULLp = 632,
- VMULLslsv2i32 = 633,
- VMULLslsv4i16 = 634,
- VMULLsluv2i32 = 635,
- VMULLsluv4i16 = 636,
- VMULLsv2i64 = 637,
- VMULLsv4i32 = 638,
- VMULLsv8i16 = 639,
- VMULLuv2i64 = 640,
- VMULLuv4i32 = 641,
- VMULLuv8i16 = 642,
- VMULS = 643,
- VMULfd = 644,
- VMULfd_sfp = 645,
- VMULfq = 646,
- VMULpd = 647,
- VMULpq = 648,
- VMULslfd = 649,
- VMULslfq = 650,
- VMULslv2i32 = 651,
- VMULslv4i16 = 652,
- VMULslv4i32 = 653,
- VMULslv8i16 = 654,
- VMULv16i8 = 655,
- VMULv2i32 = 656,
- VMULv4i16 = 657,
- VMULv4i32 = 658,
- VMULv8i16 = 659,
- VMULv8i8 = 660,
- VMVNd = 661,
- VMVNq = 662,
- VNEGD = 663,
- VNEGDcc = 664,
- VNEGS = 665,
- VNEGScc = 666,
- VNEGf32d = 667,
- VNEGf32d_sfp = 668,
- VNEGf32q = 669,
- VNEGs16d = 670,
- VNEGs16q = 671,
- VNEGs32d = 672,
- VNEGs32q = 673,
- VNEGs8d = 674,
- VNEGs8q = 675,
- VNMLAD = 676,
- VNMLAS = 677,
- VNMLSD = 678,
- VNMLSS = 679,
- VNMULD = 680,
- VNMULS = 681,
- VORNd = 682,
- VORNq = 683,
- VORRd = 684,
- VORRq = 685,
- VPADALsv16i8 = 686,
- VPADALsv2i32 = 687,
- VPADALsv4i16 = 688,
- VPADALsv4i32 = 689,
- VPADALsv8i16 = 690,
- VPADALsv8i8 = 691,
- VPADALuv16i8 = 692,
- VPADALuv2i32 = 693,
- VPADALuv4i16 = 694,
- VPADALuv4i32 = 695,
- VPADALuv8i16 = 696,
- VPADALuv8i8 = 697,
- VPADDLsv16i8 = 698,
- VPADDLsv2i32 = 699,
- VPADDLsv4i16 = 700,
- VPADDLsv4i32 = 701,
- VPADDLsv8i16 = 702,
- VPADDLsv8i8 = 703,
- VPADDLuv16i8 = 704,
- VPADDLuv2i32 = 705,
- VPADDLuv4i16 = 706,
- VPADDLuv4i32 = 707,
- VPADDLuv8i16 = 708,
- VPADDLuv8i8 = 709,
- VPADDf = 710,
- VPADDi16 = 711,
- VPADDi32 = 712,
- VPADDi8 = 713,
- VPMAXf = 714,
- VPMAXs16 = 715,
- VPMAXs32 = 716,
- VPMAXs8 = 717,
- VPMAXu16 = 718,
- VPMAXu32 = 719,
- VPMAXu8 = 720,
- VPMINf = 721,
- VPMINs16 = 722,
- VPMINs32 = 723,
- VPMINs8 = 724,
- VPMINu16 = 725,
- VPMINu32 = 726,
- VPMINu8 = 727,
- VQABSv16i8 = 728,
- VQABSv2i32 = 729,
- VQABSv4i16 = 730,
- VQABSv4i32 = 731,
- VQABSv8i16 = 732,
- VQABSv8i8 = 733,
- VQADDsv16i8 = 734,
- VQADDsv1i64 = 735,
- VQADDsv2i32 = 736,
- VQADDsv2i64 = 737,
- VQADDsv4i16 = 738,
- VQADDsv4i32 = 739,
- VQADDsv8i16 = 740,
- VQADDsv8i8 = 741,
- VQADDuv16i8 = 742,
- VQADDuv1i64 = 743,
- VQADDuv2i32 = 744,
- VQADDuv2i64 = 745,
- VQADDuv4i16 = 746,
- VQADDuv4i32 = 747,
- VQADDuv8i16 = 748,
- VQADDuv8i8 = 749,
- VQDMLALslv2i32 = 750,
- VQDMLALslv4i16 = 751,
- VQDMLALv2i64 = 752,
- VQDMLALv4i32 = 753,
- VQDMLSLslv2i32 = 754,
- VQDMLSLslv4i16 = 755,
- VQDMLSLv2i64 = 756,
- VQDMLSLv4i32 = 757,
- VQDMULHslv2i32 = 758,
- VQDMULHslv4i16 = 759,
- VQDMULHslv4i32 = 760,
- VQDMULHslv8i16 = 761,
- VQDMULHv2i32 = 762,
- VQDMULHv4i16 = 763,
- VQDMULHv4i32 = 764,
- VQDMULHv8i16 = 765,
- VQDMULLslv2i32 = 766,
- VQDMULLslv4i16 = 767,
- VQDMULLv2i64 = 768,
- VQDMULLv4i32 = 769,
- VQMOVNsuv2i32 = 770,
- VQMOVNsuv4i16 = 771,
- VQMOVNsuv8i8 = 772,
- VQMOVNsv2i32 = 773,
- VQMOVNsv4i16 = 774,
- VQMOVNsv8i8 = 775,
- VQMOVNuv2i32 = 776,
- VQMOVNuv4i16 = 777,
- VQMOVNuv8i8 = 778,
- VQNEGv16i8 = 779,
- VQNEGv2i32 = 780,
- VQNEGv4i16 = 781,
- VQNEGv4i32 = 782,
- VQNEGv8i16 = 783,
- VQNEGv8i8 = 784,
- VQRDMULHslv2i32 = 785,
- VQRDMULHslv4i16 = 786,
- VQRDMULHslv4i32 = 787,
- VQRDMULHslv8i16 = 788,
- VQRDMULHv2i32 = 789,
- VQRDMULHv4i16 = 790,
- VQRDMULHv4i32 = 791,
- VQRDMULHv8i16 = 792,
- VQRSHLsv16i8 = 793,
- VQRSHLsv1i64 = 794,
- VQRSHLsv2i32 = 795,
- VQRSHLsv2i64 = 796,
- VQRSHLsv4i16 = 797,
- VQRSHLsv4i32 = 798,
- VQRSHLsv8i16 = 799,
- VQRSHLsv8i8 = 800,
- VQRSHLuv16i8 = 801,
- VQRSHLuv1i64 = 802,
- VQRSHLuv2i32 = 803,
- VQRSHLuv2i64 = 804,
- VQRSHLuv4i16 = 805,
- VQRSHLuv4i32 = 806,
- VQRSHLuv8i16 = 807,
- VQRSHLuv8i8 = 808,
- VQRSHRNsv2i32 = 809,
- VQRSHRNsv4i16 = 810,
- VQRSHRNsv8i8 = 811,
- VQRSHRNuv2i32 = 812,
- VQRSHRNuv4i16 = 813,
- VQRSHRNuv8i8 = 814,
- VQRSHRUNv2i32 = 815,
- VQRSHRUNv4i16 = 816,
- VQRSHRUNv8i8 = 817,
- VQSHLsiv16i8 = 818,
- VQSHLsiv1i64 = 819,
- VQSHLsiv2i32 = 820,
- VQSHLsiv2i64 = 821,
- VQSHLsiv4i16 = 822,
- VQSHLsiv4i32 = 823,
- VQSHLsiv8i16 = 824,
- VQSHLsiv8i8 = 825,
- VQSHLsuv16i8 = 826,
- VQSHLsuv1i64 = 827,
- VQSHLsuv2i32 = 828,
- VQSHLsuv2i64 = 829,
- VQSHLsuv4i16 = 830,
- VQSHLsuv4i32 = 831,
- VQSHLsuv8i16 = 832,
- VQSHLsuv8i8 = 833,
- VQSHLsv16i8 = 834,
- VQSHLsv1i64 = 835,
- VQSHLsv2i32 = 836,
- VQSHLsv2i64 = 837,
- VQSHLsv4i16 = 838,
- VQSHLsv4i32 = 839,
- VQSHLsv8i16 = 840,
- VQSHLsv8i8 = 841,
- VQSHLuiv16i8 = 842,
- VQSHLuiv1i64 = 843,
- VQSHLuiv2i32 = 844,
- VQSHLuiv2i64 = 845,
- VQSHLuiv4i16 = 846,
- VQSHLuiv4i32 = 847,
- VQSHLuiv8i16 = 848,
- VQSHLuiv8i8 = 849,
- VQSHLuv16i8 = 850,
- VQSHLuv1i64 = 851,
- VQSHLuv2i32 = 852,
- VQSHLuv2i64 = 853,
- VQSHLuv4i16 = 854,
- VQSHLuv4i32 = 855,
- VQSHLuv8i16 = 856,
- VQSHLuv8i8 = 857,
- VQSHRNsv2i32 = 858,
- VQSHRNsv4i16 = 859,
- VQSHRNsv8i8 = 860,
- VQSHRNuv2i32 = 861,
- VQSHRNuv4i16 = 862,
- VQSHRNuv8i8 = 863,
- VQSHRUNv2i32 = 864,
- VQSHRUNv4i16 = 865,
- VQSHRUNv8i8 = 866,
- VQSUBsv16i8 = 867,
- VQSUBsv1i64 = 868,
- VQSUBsv2i32 = 869,
- VQSUBsv2i64 = 870,
- VQSUBsv4i16 = 871,
- VQSUBsv4i32 = 872,
- VQSUBsv8i16 = 873,
- VQSUBsv8i8 = 874,
- VQSUBuv16i8 = 875,
- VQSUBuv1i64 = 876,
- VQSUBuv2i32 = 877,
- VQSUBuv2i64 = 878,
- VQSUBuv4i16 = 879,
- VQSUBuv4i32 = 880,
- VQSUBuv8i16 = 881,
- VQSUBuv8i8 = 882,
- VRADDHNv2i32 = 883,
- VRADDHNv4i16 = 884,
- VRADDHNv8i8 = 885,
- VRECPEd = 886,
- VRECPEfd = 887,
- VRECPEfq = 888,
- VRECPEq = 889,
- VRECPSfd = 890,
- VRECPSfq = 891,
- VREV16d8 = 892,
- VREV16q8 = 893,
- VREV32d16 = 894,
- VREV32d8 = 895,
- VREV32q16 = 896,
- VREV32q8 = 897,
- VREV64d16 = 898,
- VREV64d32 = 899,
- VREV64d8 = 900,
- VREV64df = 901,
- VREV64q16 = 902,
- VREV64q32 = 903,
- VREV64q8 = 904,
- VREV64qf = 905,
- VRHADDsv16i8 = 906,
- VRHADDsv2i32 = 907,
- VRHADDsv4i16 = 908,
- VRHADDsv4i32 = 909,
- VRHADDsv8i16 = 910,
- VRHADDsv8i8 = 911,
- VRHADDuv16i8 = 912,
- VRHADDuv2i32 = 913,
- VRHADDuv4i16 = 914,
- VRHADDuv4i32 = 915,
- VRHADDuv8i16 = 916,
- VRHADDuv8i8 = 917,
- VRSHLsv16i8 = 918,
- VRSHLsv1i64 = 919,
- VRSHLsv2i32 = 920,
- VRSHLsv2i64 = 921,
- VRSHLsv4i16 = 922,
- VRSHLsv4i32 = 923,
- VRSHLsv8i16 = 924,
- VRSHLsv8i8 = 925,
- VRSHLuv16i8 = 926,
- VRSHLuv1i64 = 927,
- VRSHLuv2i32 = 928,
- VRSHLuv2i64 = 929,
- VRSHLuv4i16 = 930,
- VRSHLuv4i32 = 931,
- VRSHLuv8i16 = 932,
- VRSHLuv8i8 = 933,
- VRSHRNv2i32 = 934,
- VRSHRNv4i16 = 935,
- VRSHRNv8i8 = 936,
- VRSHRsv16i8 = 937,
- VRSHRsv1i64 = 938,
- VRSHRsv2i32 = 939,
- VRSHRsv2i64 = 940,
- VRSHRsv4i16 = 941,
- VRSHRsv4i32 = 942,
- VRSHRsv8i16 = 943,
- VRSHRsv8i8 = 944,
- VRSHRuv16i8 = 945,
- VRSHRuv1i64 = 946,
- VRSHRuv2i32 = 947,
- VRSHRuv2i64 = 948,
- VRSHRuv4i16 = 949,
- VRSHRuv4i32 = 950,
- VRSHRuv8i16 = 951,
- VRSHRuv8i8 = 952,
- VRSQRTEd = 953,
- VRSQRTEfd = 954,
- VRSQRTEfq = 955,
- VRSQRTEq = 956,
- VRSQRTSfd = 957,
- VRSQRTSfq = 958,
- VRSRAsv16i8 = 959,
- VRSRAsv1i64 = 960,
- VRSRAsv2i32 = 961,
- VRSRAsv2i64 = 962,
- VRSRAsv4i16 = 963,
- VRSRAsv4i32 = 964,
- VRSRAsv8i16 = 965,
- VRSRAsv8i8 = 966,
- VRSRAuv16i8 = 967,
- VRSRAuv1i64 = 968,
- VRSRAuv2i32 = 969,
- VRSRAuv2i64 = 970,
- VRSRAuv4i16 = 971,
- VRSRAuv4i32 = 972,
- VRSRAuv8i16 = 973,
- VRSRAuv8i8 = 974,
- VRSUBHNv2i32 = 975,
- VRSUBHNv4i16 = 976,
- VRSUBHNv8i8 = 977,
- VSETLNi16 = 978,
- VSETLNi32 = 979,
- VSETLNi8 = 980,
- VSHLLi16 = 981,
- VSHLLi32 = 982,
- VSHLLi8 = 983,
- VSHLLsv2i64 = 984,
- VSHLLsv4i32 = 985,
- VSHLLsv8i16 = 986,
- VSHLLuv2i64 = 987,
- VSHLLuv4i32 = 988,
- VSHLLuv8i16 = 989,
- VSHLiv16i8 = 990,
- VSHLiv1i64 = 991,
- VSHLiv2i32 = 992,
- VSHLiv2i64 = 993,
- VSHLiv4i16 = 994,
- VSHLiv4i32 = 995,
- VSHLiv8i16 = 996,
- VSHLiv8i8 = 997,
- VSHLsv16i8 = 998,
- VSHLsv1i64 = 999,
- VSHLsv2i32 = 1000,
- VSHLsv2i64 = 1001,
- VSHLsv4i16 = 1002,
- VSHLsv4i32 = 1003,
- VSHLsv8i16 = 1004,
- VSHLsv8i8 = 1005,
- VSHLuv16i8 = 1006,
- VSHLuv1i64 = 1007,
- VSHLuv2i32 = 1008,
- VSHLuv2i64 = 1009,
- VSHLuv4i16 = 1010,
- VSHLuv4i32 = 1011,
- VSHLuv8i16 = 1012,
- VSHLuv8i8 = 1013,
- VSHRNv2i32 = 1014,
- VSHRNv4i16 = 1015,
- VSHRNv8i8 = 1016,
- VSHRsv16i8 = 1017,
- VSHRsv1i64 = 1018,
- VSHRsv2i32 = 1019,
- VSHRsv2i64 = 1020,
- VSHRsv4i16 = 1021,
- VSHRsv4i32 = 1022,
- VSHRsv8i16 = 1023,
- VSHRsv8i8 = 1024,
- VSHRuv16i8 = 1025,
- VSHRuv1i64 = 1026,
- VSHRuv2i32 = 1027,
- VSHRuv2i64 = 1028,
- VSHRuv4i16 = 1029,
- VSHRuv4i32 = 1030,
- VSHRuv8i16 = 1031,
- VSHRuv8i8 = 1032,
- VSITOD = 1033,
- VSITOS = 1034,
- VSLIv16i8 = 1035,
- VSLIv1i64 = 1036,
- VSLIv2i32 = 1037,
- VSLIv2i64 = 1038,
- VSLIv4i16 = 1039,
- VSLIv4i32 = 1040,
- VSLIv8i16 = 1041,
- VSLIv8i8 = 1042,
- VSQRTD = 1043,
- VSQRTS = 1044,
- VSRAsv16i8 = 1045,
- VSRAsv1i64 = 1046,
- VSRAsv2i32 = 1047,
- VSRAsv2i64 = 1048,
- VSRAsv4i16 = 1049,
- VSRAsv4i32 = 1050,
- VSRAsv8i16 = 1051,
- VSRAsv8i8 = 1052,
- VSRAuv16i8 = 1053,
- VSRAuv1i64 = 1054,
- VSRAuv2i32 = 1055,
- VSRAuv2i64 = 1056,
- VSRAuv4i16 = 1057,
- VSRAuv4i32 = 1058,
- VSRAuv8i16 = 1059,
- VSRAuv8i8 = 1060,
- VSRIv16i8 = 1061,
- VSRIv1i64 = 1062,
- VSRIv2i32 = 1063,
- VSRIv2i64 = 1064,
- VSRIv4i16 = 1065,
- VSRIv4i32 = 1066,
- VSRIv8i16 = 1067,
- VSRIv8i8 = 1068,
- VST1d16 = 1069,
- VST1d32 = 1070,
- VST1d64 = 1071,
- VST1d8 = 1072,
- VST1df = 1073,
- VST1q16 = 1074,
- VST1q32 = 1075,
- VST1q64 = 1076,
- VST1q8 = 1077,
- VST1qf = 1078,
- VST2LNd16 = 1079,
- VST2LNd32 = 1080,
- VST2LNd8 = 1081,
- VST2LNq16a = 1082,
- VST2LNq16b = 1083,
- VST2LNq32a = 1084,
- VST2LNq32b = 1085,
- VST2d16 = 1086,
- VST2d32 = 1087,
- VST2d64 = 1088,
- VST2d8 = 1089,
- VST2q16 = 1090,
- VST2q32 = 1091,
- VST2q8 = 1092,
- VST3LNd16 = 1093,
- VST3LNd32 = 1094,
- VST3LNd8 = 1095,
- VST3LNq16a = 1096,
- VST3LNq16b = 1097,
- VST3LNq32a = 1098,
- VST3LNq32b = 1099,
- VST3d16 = 1100,
- VST3d32 = 1101,
- VST3d64 = 1102,
- VST3d8 = 1103,
- VST3q16a = 1104,
- VST3q16b = 1105,
- VST3q32a = 1106,
- VST3q32b = 1107,
- VST3q8a = 1108,
- VST3q8b = 1109,
- VST4LNd16 = 1110,
- VST4LNd32 = 1111,
- VST4LNd8 = 1112,
- VST4LNq16a = 1113,
- VST4LNq16b = 1114,
- VST4LNq32a = 1115,
- VST4LNq32b = 1116,
- VST4d16 = 1117,
- VST4d32 = 1118,
- VST4d64 = 1119,
- VST4d8 = 1120,
- VST4q16a = 1121,
- VST4q16b = 1122,
- VST4q32a = 1123,
- VST4q32b = 1124,
- VST4q8a = 1125,
- VST4q8b = 1126,
- VSTMD = 1127,
- VSTMS = 1128,
- VSTRD = 1129,
- VSTRQ = 1130,
- VSTRS = 1131,
- VSUBD = 1132,
- VSUBHNv2i32 = 1133,
- VSUBHNv4i16 = 1134,
- VSUBHNv8i8 = 1135,
- VSUBLsv2i64 = 1136,
- VSUBLsv4i32 = 1137,
- VSUBLsv8i16 = 1138,
- VSUBLuv2i64 = 1139,
- VSUBLuv4i32 = 1140,
- VSUBLuv8i16 = 1141,
- VSUBS = 1142,
- VSUBWsv2i64 = 1143,
- VSUBWsv4i32 = 1144,
- VSUBWsv8i16 = 1145,
- VSUBWuv2i64 = 1146,
- VSUBWuv4i32 = 1147,
- VSUBWuv8i16 = 1148,
- VSUBfd = 1149,
- VSUBfd_sfp = 1150,
- VSUBfq = 1151,
- VSUBv16i8 = 1152,
- VSUBv1i64 = 1153,
- VSUBv2i32 = 1154,
- VSUBv2i64 = 1155,
- VSUBv4i16 = 1156,
- VSUBv4i32 = 1157,
- VSUBv8i16 = 1158,
- VSUBv8i8 = 1159,
- VTBL1 = 1160,
- VTBL2 = 1161,
- VTBL3 = 1162,
- VTBL4 = 1163,
- VTBX1 = 1164,
- VTBX2 = 1165,
- VTBX3 = 1166,
- VTBX4 = 1167,
- VTOSIZD = 1168,
- VTOSIZS = 1169,
- VTOUIZD = 1170,
- VTOUIZS = 1171,
- VTRNd16 = 1172,
- VTRNd32 = 1173,
- VTRNd8 = 1174,
- VTRNq16 = 1175,
- VTRNq32 = 1176,
- VTRNq8 = 1177,
- VTSTv16i8 = 1178,
- VTSTv2i32 = 1179,
- VTSTv4i16 = 1180,
- VTSTv4i32 = 1181,
- VTSTv8i16 = 1182,
- VTSTv8i8 = 1183,
- VUITOD = 1184,
- VUITOS = 1185,
- VUZPd16 = 1186,
- VUZPd32 = 1187,
- VUZPd8 = 1188,
- VUZPq16 = 1189,
- VUZPq32 = 1190,
- VUZPq8 = 1191,
- VZIPd16 = 1192,
- VZIPd32 = 1193,
- VZIPd8 = 1194,
- VZIPq16 = 1195,
- VZIPq32 = 1196,
- VZIPq8 = 1197,
- t2ADCSri = 1198,
- t2ADCSrr = 1199,
- t2ADCSrs = 1200,
- t2ADCri = 1201,
- t2ADCrr = 1202,
- t2ADCrs = 1203,
- t2ADDSri = 1204,
- t2ADDSrr = 1205,
- t2ADDSrs = 1206,
- t2ADDrSPi = 1207,
- t2ADDrSPi12 = 1208,
- t2ADDrSPs = 1209,
- t2ADDri = 1210,
- t2ADDri12 = 1211,
- t2ADDrr = 1212,
- t2ADDrs = 1213,
- t2ANDri = 1214,
- t2ANDrr = 1215,
- t2ANDrs = 1216,
- t2ASRri = 1217,
- t2ASRrr = 1218,
- t2B = 1219,
- t2BFC = 1220,
- t2BICri = 1221,
- t2BICrr = 1222,
- t2BICrs = 1223,
- t2BR_JT = 1224,
- t2Bcc = 1225,
- t2CLZ = 1226,
- t2CMNri = 1227,
- t2CMNrr = 1228,
- t2CMNrs = 1229,
- t2CMNzri = 1230,
- t2CMNzrr = 1231,
- t2CMNzrs = 1232,
- t2CMPri = 1233,
- t2CMPrr = 1234,
- t2CMPrs = 1235,
- t2CMPzri = 1236,
- t2CMPzrr = 1237,
- t2CMPzrs = 1238,
- t2EORri = 1239,
- t2EORrr = 1240,
- t2EORrs = 1241,
- t2IT = 1242,
- t2Int_MemBarrierV7 = 1243,
- t2Int_SyncBarrierV7 = 1244,
- t2Int_eh_sjlj_setjmp = 1245,
- t2LDM = 1246,
- t2LDM_RET = 1247,
- t2LDRB_POST = 1248,
- t2LDRB_PRE = 1249,
- t2LDRBi12 = 1250,
- t2LDRBi8 = 1251,
- t2LDRBpci = 1252,
- t2LDRBs = 1253,
- t2LDRDi8 = 1254,
- t2LDRDpci = 1255,
- t2LDREX = 1256,
- t2LDREXB = 1257,
- t2LDREXD = 1258,
- t2LDREXH = 1259,
- t2LDRH_POST = 1260,
- t2LDRH_PRE = 1261,
- t2LDRHi12 = 1262,
- t2LDRHi8 = 1263,
- t2LDRHpci = 1264,
- t2LDRHs = 1265,
- t2LDRSB_POST = 1266,
- t2LDRSB_PRE = 1267,
- t2LDRSBi12 = 1268,
- t2LDRSBi8 = 1269,
- t2LDRSBpci = 1270,
- t2LDRSBs = 1271,
- t2LDRSH_POST = 1272,
- t2LDRSH_PRE = 1273,
- t2LDRSHi12 = 1274,
- t2LDRSHi8 = 1275,
- t2LDRSHpci = 1276,
- t2LDRSHs = 1277,
- t2LDR_POST = 1278,
- t2LDR_PRE = 1279,
- t2LDRi12 = 1280,
- t2LDRi8 = 1281,
- t2LDRpci = 1282,
- t2LDRpci_pic = 1283,
- t2LDRs = 1284,
- t2LEApcrel = 1285,
- t2LEApcrelJT = 1286,
- t2LSLri = 1287,
- t2LSLrr = 1288,
- t2LSRri = 1289,
- t2LSRrr = 1290,
- t2MLA = 1291,
- t2MLS = 1292,
- t2MOVCCasr = 1293,
- t2MOVCCi = 1294,
- t2MOVCClsl = 1295,
- t2MOVCClsr = 1296,
- t2MOVCCr = 1297,
- t2MOVCCror = 1298,
- t2MOVTi16 = 1299,
- t2MOVi = 1300,
- t2MOVi16 = 1301,
- t2MOVi32imm = 1302,
- t2MOVr = 1303,
- t2MOVrx = 1304,
- t2MOVsra_flag = 1305,
- t2MOVsrl_flag = 1306,
- t2MUL = 1307,
- t2MVNi = 1308,
- t2MVNr = 1309,
- t2MVNs = 1310,
- t2ORNri = 1311,
- t2ORNrr = 1312,
- t2ORNrs = 1313,
- t2ORRri = 1314,
- t2ORRrr = 1315,
- t2ORRrs = 1316,
- t2PKHBT = 1317,
- t2PKHTB = 1318,
- t2REV = 1319,
- t2REV16 = 1320,
- t2REVSH = 1321,
- t2RORri = 1322,
- t2RORrr = 1323,
- t2RSBSri = 1324,
- t2RSBSrs = 1325,
- t2RSBri = 1326,
- t2RSBrs = 1327,
- t2SBCSri = 1328,
- t2SBCSrr = 1329,
- t2SBCSrs = 1330,
- t2SBCri = 1331,
- t2SBCrr = 1332,
- t2SBCrs = 1333,
- t2SBFX = 1334,
- t2SMLABB = 1335,
- t2SMLABT = 1336,
- t2SMLAL = 1337,
- t2SMLATB = 1338,
- t2SMLATT = 1339,
- t2SMLAWB = 1340,
- t2SMLAWT = 1341,
- t2SMMLA = 1342,
- t2SMMLS = 1343,
- t2SMMUL = 1344,
- t2SMULBB = 1345,
- t2SMULBT = 1346,
- t2SMULL = 1347,
- t2SMULTB = 1348,
- t2SMULTT = 1349,
- t2SMULWB = 1350,
- t2SMULWT = 1351,
- t2STM = 1352,
- t2STRB_POST = 1353,
- t2STRB_PRE = 1354,
- t2STRBi12 = 1355,
- t2STRBi8 = 1356,
- t2STRBs = 1357,
- t2STRDi8 = 1358,
- t2STREX = 1359,
- t2STREXB = 1360,
- t2STREXD = 1361,
- t2STREXH = 1362,
- t2STRH_POST = 1363,
- t2STRH_PRE = 1364,
- t2STRHi12 = 1365,
- t2STRHi8 = 1366,
- t2STRHs = 1367,
- t2STR_POST = 1368,
- t2STR_PRE = 1369,
- t2STRi12 = 1370,
- t2STRi8 = 1371,
- t2STRs = 1372,
- t2SUBSri = 1373,
- t2SUBSrr = 1374,
- t2SUBSrs = 1375,
- t2SUBrSPi = 1376,
- t2SUBrSPi12 = 1377,
- t2SUBrSPi12_ = 1378,
- t2SUBrSPi_ = 1379,
- t2SUBrSPs = 1380,
- t2SUBrSPs_ = 1381,
- t2SUBri = 1382,
- t2SUBri12 = 1383,
- t2SUBrr = 1384,
- t2SUBrs = 1385,
- t2SXTABrr = 1386,
- t2SXTABrr_rot = 1387,
- t2SXTAHrr = 1388,
- t2SXTAHrr_rot = 1389,
- t2SXTBr = 1390,
- t2SXTBr_rot = 1391,
- t2SXTHr = 1392,
- t2SXTHr_rot = 1393,
- t2TBB = 1394,
- t2TBH = 1395,
- t2TEQri = 1396,
- t2TEQrr = 1397,
- t2TEQrs = 1398,
- t2TPsoft = 1399,
- t2TSTri = 1400,
- t2TSTrr = 1401,
- t2TSTrs = 1402,
- t2UBFX = 1403,
- t2UMAAL = 1404,
- t2UMLAL = 1405,
- t2UMULL = 1406,
- t2UXTABrr = 1407,
- t2UXTABrr_rot = 1408,
- t2UXTAHrr = 1409,
- t2UXTAHrr_rot = 1410,
- t2UXTB16r = 1411,
- t2UXTB16r_rot = 1412,
- t2UXTBr = 1413,
- t2UXTBr_rot = 1414,
- t2UXTHr = 1415,
- t2UXTHr_rot = 1416,
- tADC = 1417,
- tADDhirr = 1418,
- tADDi3 = 1419,
- tADDi8 = 1420,
- tADDrPCi = 1421,
- tADDrSP = 1422,
- tADDrSPi = 1423,
- tADDrr = 1424,
- tADDspi = 1425,
- tADDspr = 1426,
- tADDspr_ = 1427,
- tADJCALLSTACKDOWN = 1428,
- tADJCALLSTACKUP = 1429,
- tAND = 1430,
- tANDsp = 1431,
- tASRri = 1432,
- tASRrr = 1433,
- tB = 1434,
- tBIC = 1435,
- tBL = 1436,
- tBLXi = 1437,
- tBLXi_r9 = 1438,
- tBLXr = 1439,
- tBLXr_r9 = 1440,
- tBLr9 = 1441,
- tBRIND = 1442,
- tBR_JTr = 1443,
- tBX = 1444,
- tBX_RET = 1445,
- tBX_RET_vararg = 1446,
- tBXr9 = 1447,
- tBcc = 1448,
- tBfar = 1449,
- tCBNZ = 1450,
- tCBZ = 1451,
- tCMN = 1452,
- tCMNz = 1453,
- tCMPhir = 1454,
- tCMPi8 = 1455,
- tCMPr = 1456,
- tCMPzhir = 1457,
- tCMPzi8 = 1458,
- tCMPzr = 1459,
- tEOR = 1460,
- tInt_eh_sjlj_setjmp = 1461,
- tLDM = 1462,
- tLDR = 1463,
- tLDRB = 1464,
- tLDRH = 1465,
- tLDRSB = 1466,
- tLDRSH = 1467,
- tLDRcp = 1468,
- tLDRpci = 1469,
- tLDRpci_pic = 1470,
- tLDRspi = 1471,
- tLEApcrel = 1472,
- tLEApcrelJT = 1473,
- tLSLri = 1474,
- tLSLrr = 1475,
- tLSRri = 1476,
- tLSRrr = 1477,
- tMOVCCi = 1478,
- tMOVCCr = 1479,
- tMOVCCr_pseudo = 1480,
- tMOVSr = 1481,
- tMOVgpr2gpr = 1482,
- tMOVgpr2tgpr = 1483,
- tMOVi8 = 1484,
- tMOVr = 1485,
- tMOVtgpr2gpr = 1486,
- tMUL = 1487,
- tMVN = 1488,
- tORR = 1489,
- tPICADD = 1490,
- tPOP = 1491,
- tPOP_RET = 1492,
- tPUSH = 1493,
- tREV = 1494,
- tREV16 = 1495,
- tREVSH = 1496,
- tROR = 1497,
- tRSB = 1498,
- tRestore = 1499,
- tSBC = 1500,
- tSTM = 1501,
- tSTR = 1502,
- tSTRB = 1503,
+ DEBUG_VALUE = 11,
+ ADCSSri = 12,
+ ADCSSrr = 13,
+ ADCSSrs = 14,
+ ADCri = 15,
+ ADCrr = 16,
+ ADCrs = 17,
+ ADDSri = 18,
+ ADDSrr = 19,
+ ADDSrs = 20,
+ ADDri = 21,
+ ADDrr = 22,
+ ADDrs = 23,
+ ADJCALLSTACKDOWN = 24,
+ ADJCALLSTACKUP = 25,
+ ANDri = 26,
+ ANDrr = 27,
+ ANDrs = 28,
+ ATOMIC_CMP_SWAP_I16 = 29,
+ ATOMIC_CMP_SWAP_I32 = 30,
+ ATOMIC_CMP_SWAP_I8 = 31,
+ ATOMIC_LOAD_ADD_I16 = 32,
+ ATOMIC_LOAD_ADD_I32 = 33,
+ ATOMIC_LOAD_ADD_I8 = 34,
+ ATOMIC_LOAD_AND_I16 = 35,
+ ATOMIC_LOAD_AND_I32 = 36,
+ ATOMIC_LOAD_AND_I8 = 37,
+ ATOMIC_LOAD_NAND_I16 = 38,
+ ATOMIC_LOAD_NAND_I32 = 39,
+ ATOMIC_LOAD_NAND_I8 = 40,
+ ATOMIC_LOAD_OR_I16 = 41,
+ ATOMIC_LOAD_OR_I32 = 42,
+ ATOMIC_LOAD_OR_I8 = 43,
+ ATOMIC_LOAD_SUB_I16 = 44,
+ ATOMIC_LOAD_SUB_I32 = 45,
+ ATOMIC_LOAD_SUB_I8 = 46,
+ ATOMIC_LOAD_XOR_I16 = 47,
+ ATOMIC_LOAD_XOR_I32 = 48,
+ ATOMIC_LOAD_XOR_I8 = 49,
+ ATOMIC_SWAP_I16 = 50,
+ ATOMIC_SWAP_I32 = 51,
+ ATOMIC_SWAP_I8 = 52,
+ B = 53,
+ BFC = 54,
+ BICri = 55,
+ BICrr = 56,
+ BICrs = 57,
+ BL = 58,
+ BLX = 59,
+ BLXr9 = 60,
+ BL_pred = 61,
+ BLr9 = 62,
+ BLr9_pred = 63,
+ BRIND = 64,
+ BR_JTadd = 65,
+ BR_JTm = 66,
+ BR_JTr = 67,
+ BX = 68,
+ BX_RET = 69,
+ BXr9 = 70,
+ Bcc = 71,
+ CLZ = 72,
+ CMNzri = 73,
+ CMNzrr = 74,
+ CMNzrs = 75,
+ CMPri = 76,
+ CMPrr = 77,
+ CMPrs = 78,
+ CMPzri = 79,
+ CMPzrr = 80,
+ CMPzrs = 81,
+ CONSTPOOL_ENTRY = 82,
+ EORri = 83,
+ EORrr = 84,
+ EORrs = 85,
+ FCONSTD = 86,
+ FCONSTS = 87,
+ FMSTAT = 88,
+ Int_MemBarrierV6 = 89,
+ Int_MemBarrierV7 = 90,
+ Int_SyncBarrierV6 = 91,
+ Int_SyncBarrierV7 = 92,
+ Int_eh_sjlj_setjmp = 93,
+ LDM = 94,
+ LDM_RET = 95,
+ LDR = 96,
+ LDRB = 97,
+ LDRB_POST = 98,
+ LDRB_PRE = 99,
+ LDRD = 100,
+ LDREX = 101,
+ LDREXB = 102,
+ LDREXD = 103,
+ LDREXH = 104,
+ LDRH = 105,
+ LDRH_POST = 106,
+ LDRH_PRE = 107,
+ LDRSB = 108,
+ LDRSB_POST = 109,
+ LDRSB_PRE = 110,
+ LDRSH = 111,
+ LDRSH_POST = 112,
+ LDRSH_PRE = 113,
+ LDR_POST = 114,
+ LDR_PRE = 115,
+ LDRcp = 116,
+ LEApcrel = 117,
+ LEApcrelJT = 118,
+ MLA = 119,
+ MLS = 120,
+ MOVCCi = 121,
+ MOVCCr = 122,
+ MOVCCs = 123,
+ MOVTi16 = 124,
+ MOVi = 125,
+ MOVi16 = 126,
+ MOVi2pieces = 127,
+ MOVi32imm = 128,
+ MOVr = 129,
+ MOVrx = 130,
+ MOVs = 131,
+ MOVsra_flag = 132,
+ MOVsrl_flag = 133,
+ MUL = 134,
+ MVNi = 135,
+ MVNr = 136,
+ MVNs = 137,
+ ORRri = 138,
+ ORRrr = 139,
+ ORRrs = 140,
+ PICADD = 141,
+ PICLDR = 142,
+ PICLDRB = 143,
+ PICLDRH = 144,
+ PICLDRSB = 145,
+ PICLDRSH = 146,
+ PICSTR = 147,
+ PICSTRB = 148,
+ PICSTRH = 149,
+ PKHBT = 150,
+ PKHTB = 151,
+ RBIT = 152,
+ REV = 153,
+ REV16 = 154,
+ REVSH = 155,
+ RSBSri = 156,
+ RSBSrs = 157,
+ RSBri = 158,
+ RSBrs = 159,
+ RSCSri = 160,
+ RSCSrs = 161,
+ RSCri = 162,
+ RSCrs = 163,
+ SBCSSri = 164,
+ SBCSSrr = 165,
+ SBCSSrs = 166,
+ SBCri = 167,
+ SBCrr = 168,
+ SBCrs = 169,
+ SBFX = 170,
+ SMLABB = 171,
+ SMLABT = 172,
+ SMLAL = 173,
+ SMLATB = 174,
+ SMLATT = 175,
+ SMLAWB = 176,
+ SMLAWT = 177,
+ SMMLA = 178,
+ SMMLS = 179,
+ SMMUL = 180,
+ SMULBB = 181,
+ SMULBT = 182,
+ SMULL = 183,
+ SMULTB = 184,
+ SMULTT = 185,
+ SMULWB = 186,
+ SMULWT = 187,
+ STM = 188,
+ STR = 189,
+ STRB = 190,
+ STRB_POST = 191,
+ STRB_PRE = 192,
+ STRD = 193,
+ STREX = 194,
+ STREXB = 195,
+ STREXD = 196,
+ STREXH = 197,
+ STRH = 198,
+ STRH_POST = 199,
+ STRH_PRE = 200,
+ STR_POST = 201,
+ STR_PRE = 202,
+ SUBSri = 203,
+ SUBSrr = 204,
+ SUBSrs = 205,
+ SUBri = 206,
+ SUBrr = 207,
+ SUBrs = 208,
+ SXTABrr = 209,
+ SXTABrr_rot = 210,
+ SXTAHrr = 211,
+ SXTAHrr_rot = 212,
+ SXTBr = 213,
+ SXTBr_rot = 214,
+ SXTHr = 215,
+ SXTHr_rot = 216,
+ TEQri = 217,
+ TEQrr = 218,
+ TEQrs = 219,
+ TPsoft = 220,
+ TSTri = 221,
+ TSTrr = 222,
+ TSTrs = 223,
+ UBFX = 224,
+ UMAAL = 225,
+ UMLAL = 226,
+ UMULL = 227,
+ UXTABrr = 228,
+ UXTABrr_rot = 229,
+ UXTAHrr = 230,
+ UXTAHrr_rot = 231,
+ UXTB16r = 232,
+ UXTB16r_rot = 233,
+ UXTBr = 234,
+ UXTBr_rot = 235,
+ UXTHr = 236,
+ UXTHr_rot = 237,
+ VABALsv2i64 = 238,
+ VABALsv4i32 = 239,
+ VABALsv8i16 = 240,
+ VABALuv2i64 = 241,
+ VABALuv4i32 = 242,
+ VABALuv8i16 = 243,
+ VABAsv16i8 = 244,
+ VABAsv2i32 = 245,
+ VABAsv4i16 = 246,
+ VABAsv4i32 = 247,
+ VABAsv8i16 = 248,
+ VABAsv8i8 = 249,
+ VABAuv16i8 = 250,
+ VABAuv2i32 = 251,
+ VABAuv4i16 = 252,
+ VABAuv4i32 = 253,
+ VABAuv8i16 = 254,
+ VABAuv8i8 = 255,
+ VABDLsv2i64 = 256,
+ VABDLsv4i32 = 257,
+ VABDLsv8i16 = 258,
+ VABDLuv2i64 = 259,
+ VABDLuv4i32 = 260,
+ VABDLuv8i16 = 261,
+ VABDfd = 262,
+ VABDfq = 263,
+ VABDsv16i8 = 264,
+ VABDsv2i32 = 265,
+ VABDsv4i16 = 266,
+ VABDsv4i32 = 267,
+ VABDsv8i16 = 268,
+ VABDsv8i8 = 269,
+ VABDuv16i8 = 270,
+ VABDuv2i32 = 271,
+ VABDuv4i16 = 272,
+ VABDuv4i32 = 273,
+ VABDuv8i16 = 274,
+ VABDuv8i8 = 275,
+ VABSD = 276,
+ VABSS = 277,
+ VABSfd = 278,
+ VABSfd_sfp = 279,
+ VABSfq = 280,
+ VABSv16i8 = 281,
+ VABSv2i32 = 282,
+ VABSv4i16 = 283,
+ VABSv4i32 = 284,
+ VABSv8i16 = 285,
+ VABSv8i8 = 286,
+ VACGEd = 287,
+ VACGEq = 288,
+ VACGTd = 289,
+ VACGTq = 290,
+ VADDD = 291,
+ VADDHNv2i32 = 292,
+ VADDHNv4i16 = 293,
+ VADDHNv8i8 = 294,
+ VADDLsv2i64 = 295,
+ VADDLsv4i32 = 296,
+ VADDLsv8i16 = 297,
+ VADDLuv2i64 = 298,
+ VADDLuv4i32 = 299,
+ VADDLuv8i16 = 300,
+ VADDS = 301,
+ VADDWsv2i64 = 302,
+ VADDWsv4i32 = 303,
+ VADDWsv8i16 = 304,
+ VADDWuv2i64 = 305,
+ VADDWuv4i32 = 306,
+ VADDWuv8i16 = 307,
+ VADDfd = 308,
+ VADDfd_sfp = 309,
+ VADDfq = 310,
+ VADDv16i8 = 311,
+ VADDv1i64 = 312,
+ VADDv2i32 = 313,
+ VADDv2i64 = 314,
+ VADDv4i16 = 315,
+ VADDv4i32 = 316,
+ VADDv8i16 = 317,
+ VADDv8i8 = 318,
+ VANDd = 319,
+ VANDq = 320,
+ VBICd = 321,
+ VBICq = 322,
+ VBSLd = 323,
+ VBSLq = 324,
+ VCEQfd = 325,
+ VCEQfq = 326,
+ VCEQv16i8 = 327,
+ VCEQv2i32 = 328,
+ VCEQv4i16 = 329,
+ VCEQv4i32 = 330,
+ VCEQv8i16 = 331,
+ VCEQv8i8 = 332,
+ VCGEfd = 333,
+ VCGEfq = 334,
+ VCGEsv16i8 = 335,
+ VCGEsv2i32 = 336,
+ VCGEsv4i16 = 337,
+ VCGEsv4i32 = 338,
+ VCGEsv8i16 = 339,
+ VCGEsv8i8 = 340,
+ VCGEuv16i8 = 341,
+ VCGEuv2i32 = 342,
+ VCGEuv4i16 = 343,
+ VCGEuv4i32 = 344,
+ VCGEuv8i16 = 345,
+ VCGEuv8i8 = 346,
+ VCGTfd = 347,
+ VCGTfq = 348,
+ VCGTsv16i8 = 349,
+ VCGTsv2i32 = 350,
+ VCGTsv4i16 = 351,
+ VCGTsv4i32 = 352,
+ VCGTsv8i16 = 353,
+ VCGTsv8i8 = 354,
+ VCGTuv16i8 = 355,
+ VCGTuv2i32 = 356,
+ VCGTuv4i16 = 357,
+ VCGTuv4i32 = 358,
+ VCGTuv8i16 = 359,
+ VCGTuv8i8 = 360,
+ VCLSv16i8 = 361,
+ VCLSv2i32 = 362,
+ VCLSv4i16 = 363,
+ VCLSv4i32 = 364,
+ VCLSv8i16 = 365,
+ VCLSv8i8 = 366,
+ VCLZv16i8 = 367,
+ VCLZv2i32 = 368,
+ VCLZv4i16 = 369,
+ VCLZv4i32 = 370,
+ VCLZv8i16 = 371,
+ VCLZv8i8 = 372,
+ VCMPED = 373,
+ VCMPES = 374,
+ VCMPEZD = 375,
+ VCMPEZS = 376,
+ VCNTd = 377,
+ VCNTq = 378,
+ VCVTDS = 379,
+ VCVTSD = 380,
+ VCVTf2sd = 381,
+ VCVTf2sd_sfp = 382,
+ VCVTf2sq = 383,
+ VCVTf2ud = 384,
+ VCVTf2ud_sfp = 385,
+ VCVTf2uq = 386,
+ VCVTf2xsd = 387,
+ VCVTf2xsq = 388,
+ VCVTf2xud = 389,
+ VCVTf2xuq = 390,
+ VCVTs2fd = 391,
+ VCVTs2fd_sfp = 392,
+ VCVTs2fq = 393,
+ VCVTu2fd = 394,
+ VCVTu2fd_sfp = 395,
+ VCVTu2fq = 396,
+ VCVTxs2fd = 397,
+ VCVTxs2fq = 398,
+ VCVTxu2fd = 399,
+ VCVTxu2fq = 400,
+ VDIVD = 401,
+ VDIVS = 402,
+ VDUP16d = 403,
+ VDUP16q = 404,
+ VDUP32d = 405,
+ VDUP32q = 406,
+ VDUP8d = 407,
+ VDUP8q = 408,
+ VDUPLN16d = 409,
+ VDUPLN16q = 410,
+ VDUPLN32d = 411,
+ VDUPLN32q = 412,
+ VDUPLN8d = 413,
+ VDUPLN8q = 414,
+ VDUPLNfd = 415,
+ VDUPLNfq = 416,
+ VDUPfd = 417,
+ VDUPfdf = 418,
+ VDUPfq = 419,
+ VDUPfqf = 420,
+ VEORd = 421,
+ VEORq = 422,
+ VEXTd16 = 423,
+ VEXTd32 = 424,
+ VEXTd8 = 425,
+ VEXTdf = 426,
+ VEXTq16 = 427,
+ VEXTq32 = 428,
+ VEXTq8 = 429,
+ VEXTqf = 430,
+ VGETLNi32 = 431,
+ VGETLNs16 = 432,
+ VGETLNs8 = 433,
+ VGETLNu16 = 434,
+ VGETLNu8 = 435,
+ VHADDsv16i8 = 436,
+ VHADDsv2i32 = 437,
+ VHADDsv4i16 = 438,
+ VHADDsv4i32 = 439,
+ VHADDsv8i16 = 440,
+ VHADDsv8i8 = 441,
+ VHADDuv16i8 = 442,
+ VHADDuv2i32 = 443,
+ VHADDuv4i16 = 444,
+ VHADDuv4i32 = 445,
+ VHADDuv8i16 = 446,
+ VHADDuv8i8 = 447,
+ VHSUBsv16i8 = 448,
+ VHSUBsv2i32 = 449,
+ VHSUBsv4i16 = 450,
+ VHSUBsv4i32 = 451,
+ VHSUBsv8i16 = 452,
+ VHSUBsv8i8 = 453,
+ VHSUBuv16i8 = 454,
+ VHSUBuv2i32 = 455,
+ VHSUBuv4i16 = 456,
+ VHSUBuv4i32 = 457,
+ VHSUBuv8i16 = 458,
+ VHSUBuv8i8 = 459,
+ VLD1d16 = 460,
+ VLD1d32 = 461,
+ VLD1d64 = 462,
+ VLD1d8 = 463,
+ VLD1df = 464,
+ VLD1q16 = 465,
+ VLD1q32 = 466,
+ VLD1q64 = 467,
+ VLD1q8 = 468,
+ VLD1qf = 469,
+ VLD2LNd16 = 470,
+ VLD2LNd32 = 471,
+ VLD2LNd8 = 472,
+ VLD2LNq16a = 473,
+ VLD2LNq16b = 474,
+ VLD2LNq32a = 475,
+ VLD2LNq32b = 476,
+ VLD2d16 = 477,
+ VLD2d32 = 478,
+ VLD2d64 = 479,
+ VLD2d8 = 480,
+ VLD2q16 = 481,
+ VLD2q32 = 482,
+ VLD2q8 = 483,
+ VLD3LNd16 = 484,
+ VLD3LNd32 = 485,
+ VLD3LNd8 = 486,
+ VLD3LNq16a = 487,
+ VLD3LNq16b = 488,
+ VLD3LNq32a = 489,
+ VLD3LNq32b = 490,
+ VLD3d16 = 491,
+ VLD3d32 = 492,
+ VLD3d64 = 493,
+ VLD3d8 = 494,
+ VLD3q16a = 495,
+ VLD3q16b = 496,
+ VLD3q32a = 497,
+ VLD3q32b = 498,
+ VLD3q8a = 499,
+ VLD3q8b = 500,
+ VLD4LNd16 = 501,
+ VLD4LNd32 = 502,
+ VLD4LNd8 = 503,
+ VLD4LNq16a = 504,
+ VLD4LNq16b = 505,
+ VLD4LNq32a = 506,
+ VLD4LNq32b = 507,
+ VLD4d16 = 508,
+ VLD4d32 = 509,
+ VLD4d64 = 510,
+ VLD4d8 = 511,
+ VLD4q16a = 512,
+ VLD4q16b = 513,
+ VLD4q32a = 514,
+ VLD4q32b = 515,
+ VLD4q8a = 516,
+ VLD4q8b = 517,
+ VLDMD = 518,
+ VLDMS = 519,
+ VLDRD = 520,
+ VLDRQ = 521,
+ VLDRS = 522,
+ VMAXfd = 523,
+ VMAXfq = 524,
+ VMAXsv16i8 = 525,
+ VMAXsv2i32 = 526,
+ VMAXsv4i16 = 527,
+ VMAXsv4i32 = 528,
+ VMAXsv8i16 = 529,
+ VMAXsv8i8 = 530,
+ VMAXuv16i8 = 531,
+ VMAXuv2i32 = 532,
+ VMAXuv4i16 = 533,
+ VMAXuv4i32 = 534,
+ VMAXuv8i16 = 535,
+ VMAXuv8i8 = 536,
+ VMINfd = 537,
+ VMINfq = 538,
+ VMINsv16i8 = 539,
+ VMINsv2i32 = 540,
+ VMINsv4i16 = 541,
+ VMINsv4i32 = 542,
+ VMINsv8i16 = 543,
+ VMINsv8i8 = 544,
+ VMINuv16i8 = 545,
+ VMINuv2i32 = 546,
+ VMINuv4i16 = 547,
+ VMINuv4i32 = 548,
+ VMINuv8i16 = 549,
+ VMINuv8i8 = 550,
+ VMLAD = 551,
+ VMLALslsv2i32 = 552,
+ VMLALslsv4i16 = 553,
+ VMLALsluv2i32 = 554,
+ VMLALsluv4i16 = 555,
+ VMLALsv2i64 = 556,
+ VMLALsv4i32 = 557,
+ VMLALsv8i16 = 558,
+ VMLALuv2i64 = 559,
+ VMLALuv4i32 = 560,
+ VMLALuv8i16 = 561,
+ VMLAS = 562,
+ VMLAfd = 563,
+ VMLAfq = 564,
+ VMLAslfd = 565,
+ VMLAslfq = 566,
+ VMLAslv2i32 = 567,
+ VMLAslv4i16 = 568,
+ VMLAslv4i32 = 569,
+ VMLAslv8i16 = 570,
+ VMLAv16i8 = 571,
+ VMLAv2i32 = 572,
+ VMLAv4i16 = 573,
+ VMLAv4i32 = 574,
+ VMLAv8i16 = 575,
+ VMLAv8i8 = 576,
+ VMLSD = 577,
+ VMLSLslsv2i32 = 578,
+ VMLSLslsv4i16 = 579,
+ VMLSLsluv2i32 = 580,
+ VMLSLsluv4i16 = 581,
+ VMLSLsv2i64 = 582,
+ VMLSLsv4i32 = 583,
+ VMLSLsv8i16 = 584,
+ VMLSLuv2i64 = 585,
+ VMLSLuv4i32 = 586,
+ VMLSLuv8i16 = 587,
+ VMLSS = 588,
+ VMLSfd = 589,
+ VMLSfq = 590,
+ VMLSslfd = 591,
+ VMLSslfq = 592,
+ VMLSslv2i32 = 593,
+ VMLSslv4i16 = 594,
+ VMLSslv4i32 = 595,
+ VMLSslv8i16 = 596,
+ VMLSv16i8 = 597,
+ VMLSv2i32 = 598,
+ VMLSv4i16 = 599,
+ VMLSv4i32 = 600,
+ VMLSv8i16 = 601,
+ VMLSv8i8 = 602,
+ VMOVD = 603,
+ VMOVDRR = 604,
+ VMOVDcc = 605,
+ VMOVDneon = 606,
+ VMOVLsv2i64 = 607,
+ VMOVLsv4i32 = 608,
+ VMOVLsv8i16 = 609,
+ VMOVLuv2i64 = 610,
+ VMOVLuv4i32 = 611,
+ VMOVLuv8i16 = 612,
+ VMOVNv2i32 = 613,
+ VMOVNv4i16 = 614,
+ VMOVNv8i8 = 615,
+ VMOVQ = 616,
+ VMOVRRD = 617,
+ VMOVRS = 618,
+ VMOVS = 619,
+ VMOVSR = 620,
+ VMOVScc = 621,
+ VMOVv16i8 = 622,
+ VMOVv1i64 = 623,
+ VMOVv2i32 = 624,
+ VMOVv2i64 = 625,
+ VMOVv4i16 = 626,
+ VMOVv4i32 = 627,
+ VMOVv8i16 = 628,
+ VMOVv8i8 = 629,
+ VMULD = 630,
+ VMULLp = 631,
+ VMULLslsv2i32 = 632,
+ VMULLslsv4i16 = 633,
+ VMULLsluv2i32 = 634,
+ VMULLsluv4i16 = 635,
+ VMULLsv2i64 = 636,
+ VMULLsv4i32 = 637,
+ VMULLsv8i16 = 638,
+ VMULLuv2i64 = 639,
+ VMULLuv4i32 = 640,
+ VMULLuv8i16 = 641,
+ VMULS = 642,
+ VMULfd = 643,
+ VMULfd_sfp = 644,
+ VMULfq = 645,
+ VMULpd = 646,
+ VMULpq = 647,
+ VMULslfd = 648,
+ VMULslfq = 649,
+ VMULslv2i32 = 650,
+ VMULslv4i16 = 651,
+ VMULslv4i32 = 652,
+ VMULslv8i16 = 653,
+ VMULv16i8 = 654,
+ VMULv2i32 = 655,
+ VMULv4i16 = 656,
+ VMULv4i32 = 657,
+ VMULv8i16 = 658,
+ VMULv8i8 = 659,
+ VMVNd = 660,
+ VMVNq = 661,
+ VNEGD = 662,
+ VNEGDcc = 663,
+ VNEGS = 664,
+ VNEGScc = 665,
+ VNEGf32d = 666,
+ VNEGf32d_sfp = 667,
+ VNEGf32q = 668,
+ VNEGs16d = 669,
+ VNEGs16q = 670,
+ VNEGs32d = 671,
+ VNEGs32q = 672,
+ VNEGs8d = 673,
+ VNEGs8q = 674,
+ VNMLAD = 675,
+ VNMLAS = 676,
+ VNMLSD = 677,
+ VNMLSS = 678,
+ VNMULD = 679,
+ VNMULS = 680,
+ VORNd = 681,
+ VORNq = 682,
+ VORRd = 683,
+ VORRq = 684,
+ VPADALsv16i8 = 685,
+ VPADALsv2i32 = 686,
+ VPADALsv4i16 = 687,
+ VPADALsv4i32 = 688,
+ VPADALsv8i16 = 689,
+ VPADALsv8i8 = 690,
+ VPADALuv16i8 = 691,
+ VPADALuv2i32 = 692,
+ VPADALuv4i16 = 693,
+ VPADALuv4i32 = 694,
+ VPADALuv8i16 = 695,
+ VPADALuv8i8 = 696,
+ VPADDLsv16i8 = 697,
+ VPADDLsv2i32 = 698,
+ VPADDLsv4i16 = 699,
+ VPADDLsv4i32 = 700,
+ VPADDLsv8i16 = 701,
+ VPADDLsv8i8 = 702,
+ VPADDLuv16i8 = 703,
+ VPADDLuv2i32 = 704,
+ VPADDLuv4i16 = 705,
+ VPADDLuv4i32 = 706,
+ VPADDLuv8i16 = 707,
+ VPADDLuv8i8 = 708,
+ VPADDf = 709,
+ VPADDi16 = 710,
+ VPADDi32 = 711,
+ VPADDi8 = 712,
+ VPMAXf = 713,
+ VPMAXs16 = 714,
+ VPMAXs32 = 715,
+ VPMAXs8 = 716,
+ VPMAXu16 = 717,
+ VPMAXu32 = 718,
+ VPMAXu8 = 719,
+ VPMINf = 720,
+ VPMINs16 = 721,
+ VPMINs32 = 722,
+ VPMINs8 = 723,
+ VPMINu16 = 724,
+ VPMINu32 = 725,
+ VPMINu8 = 726,
+ VQABSv16i8 = 727,
+ VQABSv2i32 = 728,
+ VQABSv4i16 = 729,
+ VQABSv4i32 = 730,
+ VQABSv8i16 = 731,
+ VQABSv8i8 = 732,
+ VQADDsv16i8 = 733,
+ VQADDsv1i64 = 734,
+ VQADDsv2i32 = 735,
+ VQADDsv2i64 = 736,
+ VQADDsv4i16 = 737,
+ VQADDsv4i32 = 738,
+ VQADDsv8i16 = 739,
+ VQADDsv8i8 = 740,
+ VQADDuv16i8 = 741,
+ VQADDuv1i64 = 742,
+ VQADDuv2i32 = 743,
+ VQADDuv2i64 = 744,
+ VQADDuv4i16 = 745,
+ VQADDuv4i32 = 746,
+ VQADDuv8i16 = 747,
+ VQADDuv8i8 = 748,
+ VQDMLALslv2i32 = 749,
+ VQDMLALslv4i16 = 750,
+ VQDMLALv2i64 = 751,
+ VQDMLALv4i32 = 752,
+ VQDMLSLslv2i32 = 753,
+ VQDMLSLslv4i16 = 754,
+ VQDMLSLv2i64 = 755,
+ VQDMLSLv4i32 = 756,
+ VQDMULHslv2i32 = 757,
+ VQDMULHslv4i16 = 758,
+ VQDMULHslv4i32 = 759,
+ VQDMULHslv8i16 = 760,
+ VQDMULHv2i32 = 761,
+ VQDMULHv4i16 = 762,
+ VQDMULHv4i32 = 763,
+ VQDMULHv8i16 = 764,
+ VQDMULLslv2i32 = 765,
+ VQDMULLslv4i16 = 766,
+ VQDMULLv2i64 = 767,
+ VQDMULLv4i32 = 768,
+ VQMOVNsuv2i32 = 769,
+ VQMOVNsuv4i16 = 770,
+ VQMOVNsuv8i8 = 771,
+ VQMOVNsv2i32 = 772,
+ VQMOVNsv4i16 = 773,
+ VQMOVNsv8i8 = 774,
+ VQMOVNuv2i32 = 775,
+ VQMOVNuv4i16 = 776,
+ VQMOVNuv8i8 = 777,
+ VQNEGv16i8 = 778,
+ VQNEGv2i32 = 779,
+ VQNEGv4i16 = 780,
+ VQNEGv4i32 = 781,
+ VQNEGv8i16 = 782,
+ VQNEGv8i8 = 783,
+ VQRDMULHslv2i32 = 784,
+ VQRDMULHslv4i16 = 785,
+ VQRDMULHslv4i32 = 786,
+ VQRDMULHslv8i16 = 787,
+ VQRDMULHv2i32 = 788,
+ VQRDMULHv4i16 = 789,
+ VQRDMULHv4i32 = 790,
+ VQRDMULHv8i16 = 791,
+ VQRSHLsv16i8 = 792,
+ VQRSHLsv1i64 = 793,
+ VQRSHLsv2i32 = 794,
+ VQRSHLsv2i64 = 795,
+ VQRSHLsv4i16 = 796,
+ VQRSHLsv4i32 = 797,
+ VQRSHLsv8i16 = 798,
+ VQRSHLsv8i8 = 799,
+ VQRSHLuv16i8 = 800,
+ VQRSHLuv1i64 = 801,
+ VQRSHLuv2i32 = 802,
+ VQRSHLuv2i64 = 803,
+ VQRSHLuv4i16 = 804,
+ VQRSHLuv4i32 = 805,
+ VQRSHLuv8i16 = 806,
+ VQRSHLuv8i8 = 807,
+ VQRSHRNsv2i32 = 808,
+ VQRSHRNsv4i16 = 809,
+ VQRSHRNsv8i8 = 810,
+ VQRSHRNuv2i32 = 811,
+ VQRSHRNuv4i16 = 812,
+ VQRSHRNuv8i8 = 813,
+ VQRSHRUNv2i32 = 814,
+ VQRSHRUNv4i16 = 815,
+ VQRSHRUNv8i8 = 816,
+ VQSHLsiv16i8 = 817,
+ VQSHLsiv1i64 = 818,
+ VQSHLsiv2i32 = 819,
+ VQSHLsiv2i64 = 820,
+ VQSHLsiv4i16 = 821,
+ VQSHLsiv4i32 = 822,
+ VQSHLsiv8i16 = 823,
+ VQSHLsiv8i8 = 824,
+ VQSHLsuv16i8 = 825,
+ VQSHLsuv1i64 = 826,
+ VQSHLsuv2i32 = 827,
+ VQSHLsuv2i64 = 828,
+ VQSHLsuv4i16 = 829,
+ VQSHLsuv4i32 = 830,
+ VQSHLsuv8i16 = 831,
+ VQSHLsuv8i8 = 832,
+ VQSHLsv16i8 = 833,
+ VQSHLsv1i64 = 834,
+ VQSHLsv2i32 = 835,
+ VQSHLsv2i64 = 836,
+ VQSHLsv4i16 = 837,
+ VQSHLsv4i32 = 838,
+ VQSHLsv8i16 = 839,
+ VQSHLsv8i8 = 840,
+ VQSHLuiv16i8 = 841,
+ VQSHLuiv1i64 = 842,
+ VQSHLuiv2i32 = 843,
+ VQSHLuiv2i64 = 844,
+ VQSHLuiv4i16 = 845,
+ VQSHLuiv4i32 = 846,
+ VQSHLuiv8i16 = 847,
+ VQSHLuiv8i8 = 848,
+ VQSHLuv16i8 = 849,
+ VQSHLuv1i64 = 850,
+ VQSHLuv2i32 = 851,
+ VQSHLuv2i64 = 852,
+ VQSHLuv4i16 = 853,
+ VQSHLuv4i32 = 854,
+ VQSHLuv8i16 = 855,
+ VQSHLuv8i8 = 856,
+ VQSHRNsv2i32 = 857,
+ VQSHRNsv4i16 = 858,
+ VQSHRNsv8i8 = 859,
+ VQSHRNuv2i32 = 860,
+ VQSHRNuv4i16 = 861,
+ VQSHRNuv8i8 = 862,
+ VQSHRUNv2i32 = 863,
+ VQSHRUNv4i16 = 864,
+ VQSHRUNv8i8 = 865,
+ VQSUBsv16i8 = 866,
+ VQSUBsv1i64 = 867,
+ VQSUBsv2i32 = 868,
+ VQSUBsv2i64 = 869,
+ VQSUBsv4i16 = 870,
+ VQSUBsv4i32 = 871,
+ VQSUBsv8i16 = 872,
+ VQSUBsv8i8 = 873,
+ VQSUBuv16i8 = 874,
+ VQSUBuv1i64 = 875,
+ VQSUBuv2i32 = 876,
+ VQSUBuv2i64 = 877,
+ VQSUBuv4i16 = 878,
+ VQSUBuv4i32 = 879,
+ VQSUBuv8i16 = 880,
+ VQSUBuv8i8 = 881,
+ VRADDHNv2i32 = 882,
+ VRADDHNv4i16 = 883,
+ VRADDHNv8i8 = 884,
+ VRECPEd = 885,
+ VRECPEfd = 886,
+ VRECPEfq = 887,
+ VRECPEq = 888,
+ VRECPSfd = 889,
+ VRECPSfq = 890,
+ VREV16d8 = 891,
+ VREV16q8 = 892,
+ VREV32d16 = 893,
+ VREV32d8 = 894,
+ VREV32q16 = 895,
+ VREV32q8 = 896,
+ VREV64d16 = 897,
+ VREV64d32 = 898,
+ VREV64d8 = 899,
+ VREV64df = 900,
+ VREV64q16 = 901,
+ VREV64q32 = 902,
+ VREV64q8 = 903,
+ VREV64qf = 904,
+ VRHADDsv16i8 = 905,
+ VRHADDsv2i32 = 906,
+ VRHADDsv4i16 = 907,
+ VRHADDsv4i32 = 908,
+ VRHADDsv8i16 = 909,
+ VRHADDsv8i8 = 910,
+ VRHADDuv16i8 = 911,
+ VRHADDuv2i32 = 912,
+ VRHADDuv4i16 = 913,
+ VRHADDuv4i32 = 914,
+ VRHADDuv8i16 = 915,
+ VRHADDuv8i8 = 916,
+ VRSHLsv16i8 = 917,
+ VRSHLsv1i64 = 918,
+ VRSHLsv2i32 = 919,
+ VRSHLsv2i64 = 920,
+ VRSHLsv4i16 = 921,
+ VRSHLsv4i32 = 922,
+ VRSHLsv8i16 = 923,
+ VRSHLsv8i8 = 924,
+ VRSHLuv16i8 = 925,
+ VRSHLuv1i64 = 926,
+ VRSHLuv2i32 = 927,
+ VRSHLuv2i64 = 928,
+ VRSHLuv4i16 = 929,
+ VRSHLuv4i32 = 930,
+ VRSHLuv8i16 = 931,
+ VRSHLuv8i8 = 932,
+ VRSHRNv2i32 = 933,
+ VRSHRNv4i16 = 934,
+ VRSHRNv8i8 = 935,
+ VRSHRsv16i8 = 936,
+ VRSHRsv1i64 = 937,
+ VRSHRsv2i32 = 938,
+ VRSHRsv2i64 = 939,
+ VRSHRsv4i16 = 940,
+ VRSHRsv4i32 = 941,
+ VRSHRsv8i16 = 942,
+ VRSHRsv8i8 = 943,
+ VRSHRuv16i8 = 944,
+ VRSHRuv1i64 = 945,
+ VRSHRuv2i32 = 946,
+ VRSHRuv2i64 = 947,
+ VRSHRuv4i16 = 948,
+ VRSHRuv4i32 = 949,
+ VRSHRuv8i16 = 950,
+ VRSHRuv8i8 = 951,
+ VRSQRTEd = 952,
+ VRSQRTEfd = 953,
+ VRSQRTEfq = 954,
+ VRSQRTEq = 955,
+ VRSQRTSfd = 956,
+ VRSQRTSfq = 957,
+ VRSRAsv16i8 = 958,
+ VRSRAsv1i64 = 959,
+ VRSRAsv2i32 = 960,
+ VRSRAsv2i64 = 961,
+ VRSRAsv4i16 = 962,
+ VRSRAsv4i32 = 963,
+ VRSRAsv8i16 = 964,
+ VRSRAsv8i8 = 965,
+ VRSRAuv16i8 = 966,
+ VRSRAuv1i64 = 967,
+ VRSRAuv2i32 = 968,
+ VRSRAuv2i64 = 969,
+ VRSRAuv4i16 = 970,
+ VRSRAuv4i32 = 971,
+ VRSRAuv8i16 = 972,
+ VRSRAuv8i8 = 973,
+ VRSUBHNv2i32 = 974,
+ VRSUBHNv4i16 = 975,
+ VRSUBHNv8i8 = 976,
+ VSETLNi16 = 977,
+ VSETLNi32 = 978,
+ VSETLNi8 = 979,
+ VSHLLi16 = 980,
+ VSHLLi32 = 981,
+ VSHLLi8 = 982,
+ VSHLLsv2i64 = 983,
+ VSHLLsv4i32 = 984,
+ VSHLLsv8i16 = 985,
+ VSHLLuv2i64 = 986,
+ VSHLLuv4i32 = 987,
+ VSHLLuv8i16 = 988,
+ VSHLiv16i8 = 989,
+ VSHLiv1i64 = 990,
+ VSHLiv2i32 = 991,
+ VSHLiv2i64 = 992,
+ VSHLiv4i16 = 993,
+ VSHLiv4i32 = 994,
+ VSHLiv8i16 = 995,
+ VSHLiv8i8 = 996,
+ VSHLsv16i8 = 997,
+ VSHLsv1i64 = 998,
+ VSHLsv2i32 = 999,
+ VSHLsv2i64 = 1000,
+ VSHLsv4i16 = 1001,
+ VSHLsv4i32 = 1002,
+ VSHLsv8i16 = 1003,
+ VSHLsv8i8 = 1004,
+ VSHLuv16i8 = 1005,
+ VSHLuv1i64 = 1006,
+ VSHLuv2i32 = 1007,
+ VSHLuv2i64 = 1008,
+ VSHLuv4i16 = 1009,
+ VSHLuv4i32 = 1010,
+ VSHLuv8i16 = 1011,
+ VSHLuv8i8 = 1012,
+ VSHRNv2i32 = 1013,
+ VSHRNv4i16 = 1014,
+ VSHRNv8i8 = 1015,
+ VSHRsv16i8 = 1016,
+ VSHRsv1i64 = 1017,
+ VSHRsv2i32 = 1018,
+ VSHRsv2i64 = 1019,
+ VSHRsv4i16 = 1020,
+ VSHRsv4i32 = 1021,
+ VSHRsv8i16 = 1022,
+ VSHRsv8i8 = 1023,
+ VSHRuv16i8 = 1024,
+ VSHRuv1i64 = 1025,
+ VSHRuv2i32 = 1026,
+ VSHRuv2i64 = 1027,
+ VSHRuv4i16 = 1028,
+ VSHRuv4i32 = 1029,
+ VSHRuv8i16 = 1030,
+ VSHRuv8i8 = 1031,
+ VSITOD = 1032,
+ VSITOS = 1033,
+ VSLIv16i8 = 1034,
+ VSLIv1i64 = 1035,
+ VSLIv2i32 = 1036,
+ VSLIv2i64 = 1037,
+ VSLIv4i16 = 1038,
+ VSLIv4i32 = 1039,
+ VSLIv8i16 = 1040,
+ VSLIv8i8 = 1041,
+ VSQRTD = 1042,
+ VSQRTS = 1043,
+ VSRAsv16i8 = 1044,
+ VSRAsv1i64 = 1045,
+ VSRAsv2i32 = 1046,
+ VSRAsv2i64 = 1047,
+ VSRAsv4i16 = 1048,
+ VSRAsv4i32 = 1049,
+ VSRAsv8i16 = 1050,
+ VSRAsv8i8 = 1051,
+ VSRAuv16i8 = 1052,
+ VSRAuv1i64 = 1053,
+ VSRAuv2i32 = 1054,
+ VSRAuv2i64 = 1055,
+ VSRAuv4i16 = 1056,
+ VSRAuv4i32 = 1057,
+ VSRAuv8i16 = 1058,
+ VSRAuv8i8 = 1059,
+ VSRIv16i8 = 1060,
+ VSRIv1i64 = 1061,
+ VSRIv2i32 = 1062,
+ VSRIv2i64 = 1063,
+ VSRIv4i16 = 1064,
+ VSRIv4i32 = 1065,
+ VSRIv8i16 = 1066,
+ VSRIv8i8 = 1067,
+ VST1d16 = 1068,
+ VST1d32 = 1069,
+ VST1d64 = 1070,
+ VST1d8 = 1071,
+ VST1df = 1072,
+ VST1q16 = 1073,
+ VST1q32 = 1074,
+ VST1q64 = 1075,
+ VST1q8 = 1076,
+ VST1qf = 1077,
+ VST2LNd16 = 1078,
+ VST2LNd32 = 1079,
+ VST2LNd8 = 1080,
+ VST2LNq16a = 1081,
+ VST2LNq16b = 1082,
+ VST2LNq32a = 1083,
+ VST2LNq32b = 1084,
+ VST2d16 = 1085,
+ VST2d32 = 1086,
+ VST2d64 = 1087,
+ VST2d8 = 1088,
+ VST2q16 = 1089,
+ VST2q32 = 1090,
+ VST2q8 = 1091,
+ VST3LNd16 = 1092,
+ VST3LNd32 = 1093,
+ VST3LNd8 = 1094,
+ VST3LNq16a = 1095,
+ VST3LNq16b = 1096,
+ VST3LNq32a = 1097,
+ VST3LNq32b = 1098,
+ VST3d16 = 1099,
+ VST3d32 = 1100,
+ VST3d64 = 1101,
+ VST3d8 = 1102,
+ VST3q16a = 1103,
+ VST3q16b = 1104,
+ VST3q32a = 1105,
+ VST3q32b = 1106,
+ VST3q8a = 1107,
+ VST3q8b = 1108,
+ VST4LNd16 = 1109,
+ VST4LNd32 = 1110,
+ VST4LNd8 = 1111,
+ VST4LNq16a = 1112,
+ VST4LNq16b = 1113,
+ VST4LNq32a = 1114,
+ VST4LNq32b = 1115,
+ VST4d16 = 1116,
+ VST4d32 = 1117,
+ VST4d64 = 1118,
+ VST4d8 = 1119,
+ VST4q16a = 1120,
+ VST4q16b = 1121,
+ VST4q32a = 1122,
+ VST4q32b = 1123,
+ VST4q8a = 1124,
+ VST4q8b = 1125,
+ VSTMD = 1126,
+ VSTMS = 1127,
+ VSTRD = 1128,
+ VSTRQ = 1129,
+ VSTRS = 1130,
+ VSUBD = 1131,
+ VSUBHNv2i32 = 1132,
+ VSUBHNv4i16 = 1133,
+ VSUBHNv8i8 = 1134,
+ VSUBLsv2i64 = 1135,
+ VSUBLsv4i32 = 1136,
+ VSUBLsv8i16 = 1137,
+ VSUBLuv2i64 = 1138,
+ VSUBLuv4i32 = 1139,
+ VSUBLuv8i16 = 1140,
+ VSUBS = 1141,
+ VSUBWsv2i64 = 1142,
+ VSUBWsv4i32 = 1143,
+ VSUBWsv8i16 = 1144,
+ VSUBWuv2i64 = 1145,
+ VSUBWuv4i32 = 1146,
+ VSUBWuv8i16 = 1147,
+ VSUBfd = 1148,
+ VSUBfd_sfp = 1149,
+ VSUBfq = 1150,
+ VSUBv16i8 = 1151,
+ VSUBv1i64 = 1152,
+ VSUBv2i32 = 1153,
+ VSUBv2i64 = 1154,
+ VSUBv4i16 = 1155,
+ VSUBv4i32 = 1156,
+ VSUBv8i16 = 1157,
+ VSUBv8i8 = 1158,
+ VTBL1 = 1159,
+ VTBL2 = 1160,
+ VTBL3 = 1161,
+ VTBL4 = 1162,
+ VTBX1 = 1163,
+ VTBX2 = 1164,
+ VTBX3 = 1165,
+ VTBX4 = 1166,
+ VTOSIZD = 1167,
+ VTOSIZS = 1168,
+ VTOUIZD = 1169,
+ VTOUIZS = 1170,
+ VTRNd16 = 1171,
+ VTRNd32 = 1172,
+ VTRNd8 = 1173,
+ VTRNq16 = 1174,
+ VTRNq32 = 1175,
+ VTRNq8 = 1176,
+ VTSTv16i8 = 1177,
+ VTSTv2i32 = 1178,
+ VTSTv4i16 = 1179,
+ VTSTv4i32 = 1180,
+ VTSTv8i16 = 1181,
+ VTSTv8i8 = 1182,
+ VUITOD = 1183,
+ VUITOS = 1184,
+ VUZPd16 = 1185,
+ VUZPd32 = 1186,
+ VUZPd8 = 1187,
+ VUZPq16 = 1188,
+ VUZPq32 = 1189,
+ VUZPq8 = 1190,
+ VZIPd16 = 1191,
+ VZIPd32 = 1192,
+ VZIPd8 = 1193,
+ VZIPq16 = 1194,
+ VZIPq32 = 1195,
+ VZIPq8 = 1196,
+ t2ADCSri = 1197,
+ t2ADCSrr = 1198,
+ t2ADCSrs = 1199,
+ t2ADCri = 1200,
+ t2ADCrr = 1201,
+ t2ADCrs = 1202,
+ t2ADDSri = 1203,
+ t2ADDSrr = 1204,
+ t2ADDSrs = 1205,
+ t2ADDrSPi = 1206,
+ t2ADDrSPi12 = 1207,
+ t2ADDrSPs = 1208,
+ t2ADDri = 1209,
+ t2ADDri12 = 1210,
+ t2ADDrr = 1211,
+ t2ADDrs = 1212,
+ t2ANDri = 1213,
+ t2ANDrr = 1214,
+ t2ANDrs = 1215,
+ t2ASRri = 1216,
+ t2ASRrr = 1217,
+ t2B = 1218,
+ t2BFC = 1219,
+ t2BICri = 1220,
+ t2BICrr = 1221,
+ t2BICrs = 1222,
+ t2BR_JT = 1223,
+ t2Bcc = 1224,
+ t2CLZ = 1225,
+ t2CMNzri = 1226,
+ t2CMNzrr = 1227,
+ t2CMNzrs = 1228,
+ t2CMPri = 1229,
+ t2CMPrr = 1230,
+ t2CMPrs = 1231,
+ t2CMPzri = 1232,
+ t2CMPzrr = 1233,
+ t2CMPzrs = 1234,
+ t2EORri = 1235,
+ t2EORrr = 1236,
+ t2EORrs = 1237,
+ t2IT = 1238,
+ t2Int_MemBarrierV7 = 1239,
+ t2Int_SyncBarrierV7 = 1240,
+ t2Int_eh_sjlj_setjmp = 1241,
+ t2LDM = 1242,
+ t2LDM_RET = 1243,
+ t2LDRB_POST = 1244,
+ t2LDRB_PRE = 1245,
+ t2LDRBi12 = 1246,
+ t2LDRBi8 = 1247,
+ t2LDRBpci = 1248,
+ t2LDRBs = 1249,
+ t2LDRDi8 = 1250,
+ t2LDRDpci = 1251,
+ t2LDREX = 1252,
+ t2LDREXB = 1253,
+ t2LDREXD = 1254,
+ t2LDREXH = 1255,
+ t2LDRH_POST = 1256,
+ t2LDRH_PRE = 1257,
+ t2LDRHi12 = 1258,
+ t2LDRHi8 = 1259,
+ t2LDRHpci = 1260,
+ t2LDRHs = 1261,
+ t2LDRSB_POST = 1262,
+ t2LDRSB_PRE = 1263,
+ t2LDRSBi12 = 1264,
+ t2LDRSBi8 = 1265,
+ t2LDRSBpci = 1266,
+ t2LDRSBs = 1267,
+ t2LDRSH_POST = 1268,
+ t2LDRSH_PRE = 1269,
+ t2LDRSHi12 = 1270,
+ t2LDRSHi8 = 1271,
+ t2LDRSHpci = 1272,
+ t2LDRSHs = 1273,
+ t2LDR_POST = 1274,
+ t2LDR_PRE = 1275,
+ t2LDRi12 = 1276,
+ t2LDRi8 = 1277,
+ t2LDRpci = 1278,
+ t2LDRpci_pic = 1279,
+ t2LDRs = 1280,
+ t2LEApcrel = 1281,
+ t2LEApcrelJT = 1282,
+ t2LSLri = 1283,
+ t2LSLrr = 1284,
+ t2LSRri = 1285,
+ t2LSRrr = 1286,
+ t2MLA = 1287,
+ t2MLS = 1288,
+ t2MOVCCasr = 1289,
+ t2MOVCCi = 1290,
+ t2MOVCClsl = 1291,
+ t2MOVCClsr = 1292,
+ t2MOVCCr = 1293,
+ t2MOVCCror = 1294,
+ t2MOVTi16 = 1295,
+ t2MOVi = 1296,
+ t2MOVi16 = 1297,
+ t2MOVi32imm = 1298,
+ t2MOVr = 1299,
+ t2MOVrx = 1300,
+ t2MOVsra_flag = 1301,
+ t2MOVsrl_flag = 1302,
+ t2MUL = 1303,
+ t2MVNi = 1304,
+ t2MVNr = 1305,
+ t2MVNs = 1306,
+ t2ORNri = 1307,
+ t2ORNrr = 1308,
+ t2ORNrs = 1309,
+ t2ORRri = 1310,
+ t2ORRrr = 1311,
+ t2ORRrs = 1312,
+ t2PKHBT = 1313,
+ t2PKHTB = 1314,
+ t2RBIT = 1315,
+ t2REV = 1316,
+ t2REV16 = 1317,
+ t2REVSH = 1318,
+ t2RORri = 1319,
+ t2RORrr = 1320,
+ t2RSBSri = 1321,
+ t2RSBSrs = 1322,
+ t2RSBri = 1323,
+ t2RSBrs = 1324,
+ t2SBCSri = 1325,
+ t2SBCSrr = 1326,
+ t2SBCSrs = 1327,
+ t2SBCri = 1328,
+ t2SBCrr = 1329,
+ t2SBCrs = 1330,
+ t2SBFX = 1331,
+ t2SMLABB = 1332,
+ t2SMLABT = 1333,
+ t2SMLAL = 1334,
+ t2SMLATB = 1335,
+ t2SMLATT = 1336,
+ t2SMLAWB = 1337,
+ t2SMLAWT = 1338,
+ t2SMMLA = 1339,
+ t2SMMLS = 1340,
+ t2SMMUL = 1341,
+ t2SMULBB = 1342,
+ t2SMULBT = 1343,
+ t2SMULL = 1344,
+ t2SMULTB = 1345,
+ t2SMULTT = 1346,
+ t2SMULWB = 1347,
+ t2SMULWT = 1348,
+ t2STM = 1349,
+ t2STRB_POST = 1350,
+ t2STRB_PRE = 1351,
+ t2STRBi12 = 1352,
+ t2STRBi8 = 1353,
+ t2STRBs = 1354,
+ t2STRDi8 = 1355,
+ t2STREX = 1356,
+ t2STREXB = 1357,
+ t2STREXD = 1358,
+ t2STREXH = 1359,
+ t2STRH_POST = 1360,
+ t2STRH_PRE = 1361,
+ t2STRHi12 = 1362,
+ t2STRHi8 = 1363,
+ t2STRHs = 1364,
+ t2STR_POST = 1365,
+ t2STR_PRE = 1366,
+ t2STRi12 = 1367,
+ t2STRi8 = 1368,
+ t2STRs = 1369,
+ t2SUBSri = 1370,
+ t2SUBSrr = 1371,
+ t2SUBSrs = 1372,
+ t2SUBrSPi = 1373,
+ t2SUBrSPi12 = 1374,
+ t2SUBrSPi12_ = 1375,
+ t2SUBrSPi_ = 1376,
+ t2SUBrSPs = 1377,
+ t2SUBrSPs_ = 1378,
+ t2SUBri = 1379,
+ t2SUBri12 = 1380,
+ t2SUBrr = 1381,
+ t2SUBrs = 1382,
+ t2SXTABrr = 1383,
+ t2SXTABrr_rot = 1384,
+ t2SXTAHrr = 1385,
+ t2SXTAHrr_rot = 1386,
+ t2SXTBr = 1387,
+ t2SXTBr_rot = 1388,
+ t2SXTHr = 1389,
+ t2SXTHr_rot = 1390,
+ t2TBB = 1391,
+ t2TBH = 1392,
+ t2TEQri = 1393,
+ t2TEQrr = 1394,
+ t2TEQrs = 1395,
+ t2TPsoft = 1396,
+ t2TSTri = 1397,
+ t2TSTrr = 1398,
+ t2TSTrs = 1399,
+ t2UBFX = 1400,
+ t2UMAAL = 1401,
+ t2UMLAL = 1402,
+ t2UMULL = 1403,
+ t2UXTABrr = 1404,
+ t2UXTABrr_rot = 1405,
+ t2UXTAHrr = 1406,
+ t2UXTAHrr_rot = 1407,
+ t2UXTB16r = 1408,
+ t2UXTB16r_rot = 1409,
+ t2UXTBr = 1410,
+ t2UXTBr_rot = 1411,
+ t2UXTHr = 1412,
+ t2UXTHr_rot = 1413,
+ tADC = 1414,
+ tADDhirr = 1415,
+ tADDi3 = 1416,
+ tADDi8 = 1417,
+ tADDrPCi = 1418,
+ tADDrSP = 1419,
+ tADDrSPi = 1420,
+ tADDrr = 1421,
+ tADDspi = 1422,
+ tADDspr = 1423,
+ tADDspr_ = 1424,
+ tADJCALLSTACKDOWN = 1425,
+ tADJCALLSTACKUP = 1426,
+ tAND = 1427,
+ tANDsp = 1428,
+ tASRri = 1429,
+ tASRrr = 1430,
+ tB = 1431,
+ tBIC = 1432,
+ tBL = 1433,
+ tBLXi = 1434,
+ tBLXi_r9 = 1435,
+ tBLXr = 1436,
+ tBLXr_r9 = 1437,
+ tBLr9 = 1438,
+ tBRIND = 1439,
+ tBR_JTr = 1440,
+ tBX = 1441,
+ tBX_RET = 1442,
+ tBX_RET_vararg = 1443,
+ tBXr9 = 1444,
+ tBcc = 1445,
+ tBfar = 1446,
+ tCBNZ = 1447,
+ tCBZ = 1448,
+ tCMNz = 1449,
+ tCMPhir = 1450,
+ tCMPi8 = 1451,
+ tCMPr = 1452,
+ tCMPzhir = 1453,
+ tCMPzi8 = 1454,
+ tCMPzr = 1455,
+ tEOR = 1456,
+ tInt_eh_sjlj_setjmp = 1457,
+ tLDM = 1458,
+ tLDR = 1459,
+ tLDRB = 1460,
+ tLDRBi = 1461,
+ tLDRH = 1462,
+ tLDRHi = 1463,
+ tLDRSB = 1464,
+ tLDRSH = 1465,
+ tLDRcp = 1466,
+ tLDRi = 1467,
+ tLDRpci = 1468,
+ tLDRpci_pic = 1469,
+ tLDRspi = 1470,
+ tLEApcrel = 1471,
+ tLEApcrelJT = 1472,
+ tLSLri = 1473,
+ tLSLrr = 1474,
+ tLSRri = 1475,
+ tLSRrr = 1476,
+ tMOVCCi = 1477,
+ tMOVCCr = 1478,
+ tMOVCCr_pseudo = 1479,
+ tMOVSr = 1480,
+ tMOVgpr2gpr = 1481,
+ tMOVgpr2tgpr = 1482,
+ tMOVi8 = 1483,
+ tMOVr = 1484,
+ tMOVtgpr2gpr = 1485,
+ tMUL = 1486,
+ tMVN = 1487,
+ tORR = 1488,
+ tPICADD = 1489,
+ tPOP = 1490,
+ tPOP_RET = 1491,
+ tPUSH = 1492,
+ tREV = 1493,
+ tREV16 = 1494,
+ tREVSH = 1495,
+ tROR = 1496,
+ tRSB = 1497,
+ tRestore = 1498,
+ tSBC = 1499,
+ tSTM = 1500,
+ tSTR = 1501,
+ tSTRB = 1502,
+ tSTRBi = 1503,
tSTRH = 1504,
- tSTRspi = 1505,
- tSUBi3 = 1506,
- tSUBi8 = 1507,
- tSUBrr = 1508,
- tSUBspi = 1509,
- tSUBspi_ = 1510,
- tSXTB = 1511,
- tSXTH = 1512,
- tSpill = 1513,
- tTPsoft = 1514,
- tTST = 1515,
- tUXTB = 1516,
- tUXTH = 1517,
- INSTRUCTION_LIST_END = 1518
+ tSTRHi = 1505,
+ tSTRi = 1506,
+ tSTRspi = 1507,
+ tSUBi3 = 1508,
+ tSUBi8 = 1509,
+ tSUBrr = 1510,
+ tSUBspi = 1511,
+ tSUBspi_ = 1512,
+ tSXTB = 1513,
+ tSXTH = 1514,
+ tSpill = 1515,
+ tTPsoft = 1516,
+ tTST = 1517,
+ tUXTB = 1518,
+ tUXTH = 1519,
+ INSTRUCTION_LIST_END = 1520
};
}
} // End llvm namespace
diff --git a/libclamav/c++/ARMGenRegisterInfo.h.inc b/libclamav/c++/ARMGenRegisterInfo.h.inc
index 3c40e2e..1e26e88 100644
--- a/libclamav/c++/ARMGenRegisterInfo.h.inc
+++ b/libclamav/c++/ARMGenRegisterInfo.h.inc
@@ -28,14 +28,13 @@ namespace ARM { // Register classes
DPR_8RegClassID = 3,
DPR_VFP2RegClassID = 4,
GPRRegClassID = 5,
- JustSPRegClassID = 6,
- QPRRegClassID = 7,
- QPR_8RegClassID = 8,
- QPR_VFP2RegClassID = 9,
- SPRRegClassID = 10,
- SPR_8RegClassID = 11,
- SPR_INVALIDRegClassID = 12,
- tGPRRegClassID = 13
+ QPRRegClassID = 6,
+ QPR_8RegClassID = 7,
+ QPR_VFP2RegClassID = 8,
+ SPRRegClassID = 9,
+ SPR_8RegClassID = 10,
+ SPR_INVALIDRegClassID = 11,
+ tGPRRegClassID = 12
};
struct CCRClass : public TargetRegisterClass {
@@ -69,13 +68,6 @@ namespace ARM { // Register classes
};
extern GPRClass GPRRegClass;
static TargetRegisterClass * const GPRRegisterClass = &GPRRegClass;
- struct JustSPClass : public TargetRegisterClass {
- JustSPClass();
-
- iterator allocation_order_end(const MachineFunction &MF) const;
- };
- extern JustSPClass JustSPRegClass;
- static TargetRegisterClass * const JustSPRegisterClass = &JustSPRegClass;
struct QPRClass : public TargetRegisterClass {
QPRClass();
};
diff --git a/libclamav/c++/ARMGenRegisterInfo.inc b/libclamav/c++/ARMGenRegisterInfo.inc
index 8a52344..ec628fb 100644
--- a/libclamav/c++/ARMGenRegisterInfo.inc
+++ b/libclamav/c++/ARMGenRegisterInfo.inc
@@ -31,12 +31,7 @@ namespace { // Register classes...
// GPR Register Class...
static const unsigned GPR[] = {
- ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R12, ARM::R11, ARM::LR, ARM::SP, ARM::PC,
- };
-
- // JustSP Register Class...
- static const unsigned JustSP[] = {
- ARM::SP,
+ ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC,
};
// QPR Register Class...
@@ -99,11 +94,6 @@ namespace { // Register classes...
MVT::i32, MVT::Other
};
- // JustSPVTs Register Class Value Types...
- static const EVT JustSPVTs[] = {
- MVT::i32, MVT::Other
- };
-
// QPRVTs Register Class Value Types...
static const EVT QPRVTs[] = {
MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other
@@ -147,7 +137,6 @@ namespace ARM { // Register class instances
DPR_8Class DPR_8RegClass;
DPR_VFP2Class DPR_VFP2RegClass;
GPRClass GPRRegClass;
- JustSPClass JustSPRegClass;
QPRClass QPRRegClass;
QPR_8Class QPR_8RegClass;
QPR_VFP2Class QPR_VFP2RegClass;
@@ -181,11 +170,6 @@ namespace ARM { // Register class instances
NULL
};
- // JustSP Sub-register Classes...
- static const TargetRegisterClass* const JustSPSubRegClasses[] = {
- NULL
- };
-
// QPR Sub-register Classes...
static const TargetRegisterClass* const QPRSubRegClasses[] = {
&ARM::SPR_INVALIDRegClass, &ARM::SPR_INVALIDRegClass, &ARM::SPR_INVALIDRegClass, &ARM::SPR_INVALIDRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, NULL
@@ -246,11 +230,6 @@ namespace ARM { // Register class instances
NULL
};
- // JustSP Super-register Classes...
- static const TargetRegisterClass* const JustSPSuperRegClasses[] = {
- NULL
- };
-
// QPR Super-register Classes...
static const TargetRegisterClass* const QPRSuperRegClasses[] = {
NULL
@@ -308,12 +287,7 @@ namespace ARM { // Register class instances
// GPR Register Class sub-classes...
static const TargetRegisterClass* const GPRSubclasses[] = {
- &ARM::JustSPRegClass, &ARM::tGPRRegClass, NULL
- };
-
- // JustSP Register Class sub-classes...
- static const TargetRegisterClass* const JustSPSubclasses[] = {
- NULL
+ &ARM::tGPRRegClass, NULL
};
// QPR Register Class sub-classes...
@@ -376,11 +350,6 @@ namespace ARM { // Register class instances
NULL
};
- // JustSP Register Class super-classes...
- static const TargetRegisterClass* const JustSPSuperclasses[] = {
- &ARM::GPRRegClass, NULL
- };
-
// QPR Register Class super-classes...
static const TargetRegisterClass* const QPRSuperclasses[] = {
NULL
@@ -558,13 +527,6 @@ DPR_VFP2Class::DPR_VFP2Class() : TargetRegisterClass(DPR_VFP2RegClassID, "DPR_V
GPRClass::GPRClass() : TargetRegisterClass(GPRRegClassID, "GPR", GPRVTs, GPRSubclasses, GPRSuperclasses, GPRSubRegClasses, GPRSuperRegClasses, 4, 4, 1, GPR, GPR + 16) {}
- JustSPClass::iterator
- JustSPClass::allocation_order_end(const MachineFunction &MF) const {
- return allocation_order_begin(MF);
- }
-
-JustSPClass::JustSPClass() : TargetRegisterClass(JustSPRegClassID, "JustSP", JustSPVTs, JustSPSubclasses, JustSPSuperclasses, JustSPSubRegClasses, JustSPSuperRegClasses, 4, 4, 1, JustSP, JustSP + 1) {}
-
QPRClass::QPRClass() : TargetRegisterClass(QPRRegClassID, "QPR", QPRVTs, QPRSubclasses, QPRSuperclasses, QPRSubRegClasses, QPRSuperRegClasses, 16, 16, 1, QPR, QPR + 16) {}
QPR_8Class::QPR_8Class() : TargetRegisterClass(QPR_8RegClassID, "QPR_8", QPR_8VTs, QPR_8Subclasses, QPR_8Superclasses, QPR_8SubRegClasses, QPR_8SuperRegClasses, 16, 16, 1, QPR_8, QPR_8 + 4) {}
@@ -608,7 +570,6 @@ namespace {
&ARM::DPR_8RegClass,
&ARM::DPR_VFP2RegClass,
&ARM::GPRRegClass,
- &ARM::JustSPRegClass,
&ARM::QPRRegClass,
&ARM::QPR_8RegClass,
&ARM::QPR_VFP2RegClass,
@@ -2687,7 +2648,7 @@ ARM::NoRegister, ARM::NoRegister };
const unsigned D10_AliasSet[] = { ARM::S20, ARM::S21, ARM::Q5, 0 };
const unsigned D11_AliasSet[] = { ARM::S22, ARM::S23, ARM::Q5, 0 };
const unsigned D12_AliasSet[] = { ARM::S24, ARM::S25, ARM::Q6, 0 };
- const unsigned D13_AliasSet[] = { ARM::S26, ARM::S27, ARM::Q6, 0 };
+ const unsigned D13_AliasSet[] = { ARM::S27, ARM::S26, ARM::Q6, 0 };
const unsigned D14_AliasSet[] = { ARM::S28, ARM::S29, ARM::Q7, 0 };
const unsigned D15_AliasSet[] = { ARM::S30, ARM::S31, ARM::Q7, 0 };
const unsigned D16_AliasSet[] = { ARM::Q8, 0 };
@@ -2729,7 +2690,7 @@ ARM::NoRegister, ARM::NoRegister };
const unsigned Q3_AliasSet[] = { ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::D6, ARM::D7, 0 };
const unsigned Q4_AliasSet[] = { ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::D8, ARM::D9, 0 };
const unsigned Q5_AliasSet[] = { ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::D10, ARM::D11, 0 };
- const unsigned Q6_AliasSet[] = { ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::D12, ARM::D13, 0 };
+ const unsigned Q6_AliasSet[] = { ARM::S27, ARM::S24, ARM::S25, ARM::S26, ARM::D12, ARM::D13, 0 };
const unsigned Q7_AliasSet[] = { ARM::S28, ARM::S29, ARM::S30, ARM::S31, ARM::D14, ARM::D15, 0 };
const unsigned Q8_AliasSet[] = { ARM::D16, ARM::D17, 0 };
const unsigned Q9_AliasSet[] = { ARM::D18, ARM::D19, 0 };
@@ -2790,7 +2751,7 @@ ARM::NoRegister, ARM::NoRegister };
const unsigned D10_SubRegsSet[] = { ARM::S20, ARM::S21, 0 };
const unsigned D11_SubRegsSet[] = { ARM::S22, ARM::S23, 0 };
const unsigned D12_SubRegsSet[] = { ARM::S24, ARM::S25, 0 };
- const unsigned D13_SubRegsSet[] = { ARM::S26, ARM::S27, 0 };
+ const unsigned D13_SubRegsSet[] = { ARM::S27, ARM::S26, 0 };
const unsigned D14_SubRegsSet[] = { ARM::S28, ARM::S29, 0 };
const unsigned D15_SubRegsSet[] = { ARM::S30, ARM::S31, 0 };
const unsigned D16_SubRegsSet[] = { 0 };
@@ -2832,7 +2793,7 @@ ARM::NoRegister, ARM::NoRegister };
const unsigned Q3_SubRegsSet[] = { ARM::S12, ARM::S13, ARM::D7, ARM::S14, ARM::S15, ARM::D6, 0 };
const unsigned Q4_SubRegsSet[] = { ARM::S16, ARM::S17, ARM::D9, ARM::S18, ARM::S19, ARM::D8, 0 };
const unsigned Q5_SubRegsSet[] = { ARM::S20, ARM::S21, ARM::D11, ARM::S22, ARM::S23, ARM::D10, 0 };
- const unsigned Q6_SubRegsSet[] = { ARM::S24, ARM::S25, ARM::D13, ARM::S26, ARM::S27, ARM::D12, 0 };
+ const unsigned Q6_SubRegsSet[] = { ARM::D13, ARM::S27, ARM::S24, ARM::S25, ARM::S26, ARM::D12, 0 };
const unsigned Q7_SubRegsSet[] = { ARM::S28, ARM::S29, ARM::D15, ARM::S30, ARM::S31, ARM::D14, 0 };
const unsigned Q8_SubRegsSet[] = { ARM::D16, ARM::D17, 0 };
const unsigned Q9_SubRegsSet[] = { ARM::D18, ARM::D19, 0 };
@@ -3524,7 +3485,7 @@ unsigned ARMGenRegisterInfo::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) c
}
ARMGenRegisterInfo::ARMGenRegisterInfo(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)
- : TargetRegisterInfo(RegisterDescriptors, 100, RegisterClasses, RegisterClasses+13,
+ : TargetRegisterInfo(RegisterDescriptors, 100, RegisterClasses, RegisterClasses+12,
CallFrameSetupOpcode, CallFrameDestroyOpcode,
SubregHashTable, SubregHashTableSize,
SuperregHashTable, SuperregHashTableSize,
diff --git a/libclamav/c++/ARMGenSubtarget.inc b/libclamav/c++/ARMGenSubtarget.inc
index 186cb6a..c70c950 100644
--- a/libclamav/c++/ARMGenSubtarget.inc
+++ b/libclamav/c++/ARMGenSubtarget.inc
@@ -680,8 +680,8 @@ enum {
// subtarget options.
std::string llvm::ARMSubtarget::ParseSubtargetFeatures(const std::string &FS,
const std::string &CPU) {
- DEBUG(errs() << "\nFeatures:" << FS);
- DEBUG(errs() << "\nCPU:" << CPU);
+ DEBUG(dbgs() << "\nFeatures:" << FS);
+ DEBUG(dbgs() << "\nCPU:" << CPU);
SubtargetFeatures Features(FS);
Features.setCPUIfNone(CPU);
uint32_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize,
diff --git a/libclamav/c++/Makefile.am b/libclamav/c++/Makefile.am
index 85630a0..83f75fa 100644
--- a/libclamav/c++/Makefile.am
+++ b/libclamav/c++/Makefile.am
@@ -19,7 +19,7 @@ LLVM_INCLUDES=-I$(top_srcdir)/llvm/include -I$(top_builddir)/llvm/include
# TODO: HP-UX should have -D_REENTRANT -D_HPUX_SOURCE
LLVM_DEFS=-D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -D_DEBUG -D_GNU_SOURCE
AM_CPPFLAGS = -I$(top_srcdir)/../.. -I$(top_srcdir)/.. -I$(top_builddir)/../../ $(LLVM_INCLUDES) $(LLVM_DEFS)
-AM_CXXFLAGS = $(LLVM_CXXFLAGS) -fno-exceptions
+AM_CXXFLAGS = $(LLVM_CXXFLAGS) -fno-exceptions -fno-rtti
ACLOCAL_AMFLAGS=-I m4
if DEBUG_BUILD
LLVM_CONFIG=llvm/Debug/bin/llvm-config
@@ -43,7 +43,7 @@ lli_LDADD=libllvmbitreader.la libllvmfullcodegen.la libllvmjit.la
libclamavcxx_la_LIBADD=libllvmjit.la
libclamavcxx_la_DEPENDENCIES=libllvmjit.la libllvmcodegen.la libllvmsystem.la
libclamavcxx_la_LDFLAGS=-no-undefined
-libclamavcxx_la_CXXFLAGS = $(LLVM_CXXFLAGS)
+libclamavcxx_la_CXXFLAGS = $(LLVM_CXXFLAGS) -fno-rtti
libclamavcxx_la_SOURCES = bytecode2llvm.cpp
if BUILD_X86
libclamavcxx_la_LIBADD+=libllvmx86codegen.la
@@ -148,9 +148,12 @@ if MAINTAINER_MODE
BUILT_SOURCES+=$(TBLGENFILES)
noinst_PROGRAMS = tblgen
tblgen_CXXFLAGS=$(LLVM_CXXFLAGS)
-tblgen_LDADD=libllvmsupport.la libllvmsystem.la
+tblgen_CFLAGS=
#TODO: if VERSIONSCRIPT
-tblgen_LDFLAGS= -Wl,--version-script, at top_srcdir@/llvm/autoconf/ExportMap.map
+tblgen_LDFLAGS=-pthread -Wl,--version-script, at top_srcdir@/llvm/autoconf/ExportMap.map
+# tblgen needs rtti (for now), and we build everything else with -fno-rtti
+# since tblgen is only a maintainer-mode tool, build these files twice (once for
+# libllvmsupport.la -fno-rtti, and once here, with defaults (rtti)).
tblgen_SOURCES=\
llvm/utils/TableGen/AsmMatcherEmitter.cpp\
llvm/utils/TableGen/AsmWriterEmitter.cpp\
@@ -177,7 +180,68 @@ tblgen_SOURCES=\
llvm/utils/TableGen/TableGen.cpp\
llvm/utils/TableGen/TableGenBackend.cpp\
llvm/utils/TableGen/X86DisassemblerTables.cpp\
- llvm/utils/TableGen/X86RecognizableInstr.cpp
+ llvm/utils/TableGen/X86RecognizableInstr.cpp \
+ llvm/lib/System/Alarm.cpp\
+ llvm/lib/System/Atomic.cpp\
+ llvm/lib/System/Disassembler.cpp\
+ llvm/lib/System/DynamicLibrary.cpp\
+ llvm/lib/System/Errno.cpp\
+ llvm/lib/System/Host.cpp\
+ llvm/lib/System/IncludeFile.cpp\
+ llvm/lib/System/Memory.cpp\
+ llvm/lib/System/Mutex.cpp\
+ llvm/lib/System/Path.cpp\
+ llvm/lib/System/Process.cpp\
+ llvm/lib/System/Program.cpp\
+ llvm/lib/System/RWMutex.cpp\
+ llvm/lib/System/Signals.cpp\
+ llvm/lib/System/ThreadLocal.cpp\
+ llvm/lib/System/Threading.cpp\
+ llvm/lib/System/TimeValue.cpp\
+ llvm/lib/Support/APFloat.cpp\
+ llvm/lib/Support/APInt.cpp\
+ llvm/lib/Support/APSInt.cpp\
+ llvm/lib/Support/Allocator.cpp\
+ llvm/lib/Support/CommandLine.cpp\
+ llvm/lib/Support/ConstantRange.cpp\
+ llvm/lib/Support/Debug.cpp\
+ llvm/lib/Support/DeltaAlgorithm.cpp\
+ llvm/lib/Support/Dwarf.cpp\
+ llvm/lib/Support/ErrorHandling.cpp\
+ llvm/lib/Support/FileUtilities.cpp\
+ llvm/lib/Support/FoldingSet.cpp\
+ llvm/lib/Support/FormattedStream.cpp\
+ llvm/lib/Support/GraphWriter.cpp\
+ llvm/lib/Support/IsInf.cpp\
+ llvm/lib/Support/IsNAN.cpp\
+ llvm/lib/Support/ManagedStatic.cpp\
+ llvm/lib/Support/MemoryBuffer.cpp\
+ llvm/lib/Support/MemoryObject.cpp\
+ llvm/lib/Support/PluginLoader.cpp\
+ llvm/lib/Support/PrettyStackTrace.cpp\
+ llvm/lib/Support/Regex.cpp\
+ llvm/lib/Support/SlowOperationInformer.cpp\
+ llvm/lib/Support/SmallPtrSet.cpp\
+ llvm/lib/Support/SmallVector.cpp\
+ llvm/lib/Support/SourceMgr.cpp\
+ llvm/lib/Support/Statistic.cpp\
+ llvm/lib/Support/StringExtras.cpp\
+ llvm/lib/Support/StringMap.cpp\
+ llvm/lib/Support/StringPool.cpp\
+ llvm/lib/Support/StringRef.cpp\
+ llvm/lib/Support/SystemUtils.cpp\
+ llvm/lib/Support/TargetRegistry.cpp\
+ llvm/lib/Support/Timer.cpp\
+ llvm/lib/Support/Triple.cpp\
+ llvm/lib/Support/Twine.cpp\
+ llvm/lib/Support/circular_raw_ostream.cpp\
+ llvm/lib/Support/raw_os_ostream.cpp\
+ llvm/lib/Support/raw_ostream.cpp\
+ llvm/lib/Support/regcomp.c\
+ llvm/lib/Support/regerror.c\
+ llvm/lib/Support/regexec.c\
+ llvm/lib/Support/regfree.c\
+ llvm/lib/Support/regstrlcpy.c
TBLGEN=$(top_builddir)/tblgen
TBLGEN_V=$(AM_V_GEN)$(TBLGEN)
@@ -434,6 +498,7 @@ libllvmjit_la_SOURCES=\
llvm/lib/Support/Twine.cpp\
llvm/lib/Support/circular_raw_ostream.cpp\
llvm/lib/Support/raw_ostream.cpp\
+ llvm/lib/Target/Mangler.cpp\
llvm/lib/Target/SubtargetFeature.cpp\
llvm/lib/Target/TargetData.cpp\
llvm/lib/Target/TargetInstrInfo.cpp\
@@ -450,13 +515,13 @@ libllvmjit_la_SOURCES=\
llvm/lib/VMCore/Dominators.cpp\
llvm/lib/VMCore/Function.cpp\
llvm/lib/VMCore/Globals.cpp\
+ llvm/lib/VMCore/IRBuilder.cpp\
llvm/lib/VMCore/InlineAsm.cpp\
llvm/lib/VMCore/Instruction.cpp\
llvm/lib/VMCore/Instructions.cpp\
llvm/lib/VMCore/IntrinsicInst.cpp\
llvm/lib/VMCore/LLVMContext.cpp\
llvm/lib/VMCore/LeakDetector.cpp\
- llvm/lib/VMCore/Mangler.cpp\
llvm/lib/VMCore/Metadata.cpp\
llvm/lib/VMCore/Module.cpp\
llvm/lib/VMCore/ModuleProvider.cpp\
@@ -470,6 +535,7 @@ libllvmjit_la_SOURCES=\
llvm/lib/VMCore/ValueSymbolTable.cpp\
llvm/lib/VMCore/ValueTypes.cpp\
llvm/lib/VMCore/Verifier.cpp
+
libllvmcodegen_la_SOURCES=\
llvm/lib/Analysis/AliasSetTracker.cpp\
llvm/lib/Analysis/ConstantFolding.cpp\
@@ -505,6 +571,7 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/CodeGen/LiveStackAnalysis.cpp\
llvm/lib/CodeGen/LiveVariables.cpp\
llvm/lib/CodeGen/LowerSubregs.cpp\
+ llvm/lib/CodeGen/MachOWriter.cpp\
llvm/lib/CodeGen/MachineDominators.cpp\
llvm/lib/CodeGen/MachineLICM.cpp\
llvm/lib/CodeGen/MachineLoopInfo.cpp\
@@ -512,7 +579,7 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/CodeGen/MachineSSAUpdater.cpp\
llvm/lib/CodeGen/MachineSink.cpp\
llvm/lib/CodeGen/MachineVerifier.cpp\
- llvm/lib/CodeGen/MaxStackAlignment.cpp\
+ llvm/lib/CodeGen/OptimizeExts.cpp\
llvm/lib/CodeGen/PHIElimination.cpp\
llvm/lib/CodeGen/Passes.cpp\
llvm/lib/CodeGen/PostRASchedulerList.cpp\
@@ -520,7 +587,6 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/CodeGen/ProcessImplicitDefs.cpp\
llvm/lib/CodeGen/PrologEpilogInserter.cpp\
llvm/lib/CodeGen/RegAllocLinearScan.cpp\
- llvm/lib/CodeGen/RegAllocLocal.cpp\
llvm/lib/CodeGen/RegisterCoalescer.cpp\
llvm/lib/CodeGen/RegisterScavenging.cpp\
llvm/lib/CodeGen/ScheduleDAG.cpp\
@@ -563,7 +629,9 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/CodeGen/VirtRegRewriter.cpp\
llvm/lib/MC/MCAsmInfoDarwin.cpp\
llvm/lib/MC/MCAsmStreamer.cpp\
+ llvm/lib/MC/MCAssembler.cpp\
llvm/lib/MC/MCInst.cpp\
+ llvm/lib/MC/MCMachOStreamer.cpp\
llvm/lib/MC/MCStreamer.cpp\
llvm/lib/Target/TargetFrameInfo.cpp\
llvm/lib/Target/TargetSubtarget.cpp\
@@ -586,6 +654,7 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/Transforms/Utils/SimplifyCFG.cpp\
llvm/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp
+
# Used only by make check
libllvmbitreader_la_SOURCES=\
@@ -737,8 +806,6 @@ libllvmfullcodegen_la_SOURCES=\
llvm/lib/CodeGen/GCMetadataPrinter.cpp\
llvm/lib/CodeGen/IfConversion.cpp\
llvm/lib/CodeGen/IntrinsicLowering.cpp\
- llvm/lib/CodeGen/MachOCodeEmitter.cpp\
- llvm/lib/CodeGen/MachOWriter.cpp\
llvm/lib/CodeGen/MachineModuleInfoImpls.cpp\
llvm/lib/CodeGen/OcamlGC.cpp\
llvm/lib/CodeGen/RegAllocLocal.cpp\
@@ -748,6 +815,7 @@ libllvmfullcodegen_la_SOURCES=\
llvm/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp\
llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp\
llvm/lib/Target/Target.cpp\
+ llvm/lib/Target/TargetAsmLexer.cpp\
llvm/lib/Target/TargetELFWriterInfo.cpp\
llvm/lib/Target/TargetIntrinsicInfo.cpp\
llvm/lib/Target/TargetMachOWriterInfo.cpp
diff --git a/libclamav/c++/Makefile.in b/libclamav/c++/Makefile.in
index 512ec3f..adb9c9f 100644
--- a/libclamav/c++/Makefile.in
+++ b/libclamav/c++/Makefile.in
@@ -236,17 +236,18 @@ am_libllvmcodegen_la_OBJECTS = AliasSetTracker.lo ConstantFolding.lo \
ExactHazardRecognizer.lo GCMetadata.lo GCStrategy.lo \
LLVMTargetMachine.lo LatencyPriorityQueue.lo LiveInterval.lo \
LiveIntervalAnalysis.lo LiveStackAnalysis.lo LiveVariables.lo \
- LowerSubregs.lo MachineDominators.lo MachineLICM.lo \
- MachineLoopInfo.lo MachinePassRegistry.lo MachineSSAUpdater.lo \
- MachineSink.lo MachineVerifier.lo MaxStackAlignment.lo \
- PHIElimination.lo Passes.lo PostRASchedulerList.lo \
- PreAllocSplitting.lo ProcessImplicitDefs.lo \
- PrologEpilogInserter.lo RegAllocLinearScan.lo RegAllocLocal.lo \
- RegisterCoalescer.lo RegisterScavenging.lo ScheduleDAG.lo \
- ScheduleDAGEmit.lo ScheduleDAGInstrs.lo ScheduleDAGPrinter.lo \
- CallingConvLower.lo DAGCombiner.lo FastISel.lo \
- FunctionLoweringInfo.lo InstrEmitter.lo LegalizeDAG.lo \
- LegalizeFloatTypes.lo LegalizeIntegerTypes.lo LegalizeTypes.lo \
+ LowerSubregs.lo MachOWriter.lo MachineDominators.lo \
+ MachineLICM.lo MachineLoopInfo.lo MachinePassRegistry.lo \
+ MachineSSAUpdater.lo MachineSink.lo MachineVerifier.lo \
+ OptimizeExts.lo PHIElimination.lo Passes.lo \
+ PostRASchedulerList.lo PreAllocSplitting.lo \
+ ProcessImplicitDefs.lo PrologEpilogInserter.lo \
+ RegAllocLinearScan.lo RegisterCoalescer.lo \
+ RegisterScavenging.lo ScheduleDAG.lo ScheduleDAGEmit.lo \
+ ScheduleDAGInstrs.lo ScheduleDAGPrinter.lo CallingConvLower.lo \
+ DAGCombiner.lo FastISel.lo FunctionLoweringInfo.lo \
+ InstrEmitter.lo LegalizeDAG.lo LegalizeFloatTypes.lo \
+ LegalizeIntegerTypes.lo LegalizeTypes.lo \
LegalizeTypesGeneric.lo LegalizeVectorOps.lo \
LegalizeVectorTypes.lo ScheduleDAGFast.lo ScheduleDAGList.lo \
ScheduleDAGRRList.lo ScheduleDAGSDNodes.lo SelectionDAG.lo \
@@ -257,22 +258,23 @@ am_libllvmcodegen_la_OBJECTS = AliasSetTracker.lo ConstantFolding.lo \
StrongPHIElimination.lo TailDuplication.lo \
TwoAddressInstructionPass.lo UnreachableBlockElim.lo \
VirtRegMap.lo VirtRegRewriter.lo MCAsmInfoDarwin.lo \
- MCAsmStreamer.lo MCInst.lo MCStreamer.lo TargetFrameInfo.lo \
- TargetSubtarget.lo CodeGenPrepare.lo GEPSplitter.lo GVN.lo \
- LoopStrengthReduce.lo AddrModeMatcher.lo BasicBlockUtils.lo \
- BreakCriticalEdges.lo DemoteRegToStack.lo LCSSA.lo Local.lo \
- LoopSimplify.lo LowerInvoke.lo LowerSwitch.lo Mem2Reg.lo \
+ MCAsmStreamer.lo MCAssembler.lo MCInst.lo MCMachOStreamer.lo \
+ MCStreamer.lo TargetFrameInfo.lo TargetSubtarget.lo \
+ CodeGenPrepare.lo GEPSplitter.lo GVN.lo LoopStrengthReduce.lo \
+ AddrModeMatcher.lo BasicBlockUtils.lo BreakCriticalEdges.lo \
+ DemoteRegToStack.lo LCSSA.lo Local.lo LoopSimplify.lo \
+ LowerInvoke.lo LowerSwitch.lo Mem2Reg.lo \
PromoteMemoryToRegister.lo SSAUpdater.lo SimplifyCFG.lo \
UnifyFunctionExitNodes.lo
libllvmcodegen_la_OBJECTS = $(am_libllvmcodegen_la_OBJECTS)
libllvmfullcodegen_la_LIBADD =
am_libllvmfullcodegen_la_OBJECTS = DeadMachineInstructionElim.lo \
GCMetadataPrinter.lo IfConversion.lo IntrinsicLowering.lo \
- MachOCodeEmitter.lo MachOWriter.lo MachineModuleInfoImpls.lo \
- OcamlGC.lo RegAllocLocal.lo RegAllocPBQP.lo ShadowStackGC.lo \
- Execution.lo ExternalFunctions.lo Interpreter.lo Target.lo \
- TargetELFWriterInfo.lo TargetIntrinsicInfo.lo \
- TargetMachOWriterInfo.lo
+ MachineModuleInfoImpls.lo OcamlGC.lo RegAllocLocal.lo \
+ RegAllocPBQP.lo ShadowStackGC.lo Execution.lo \
+ ExternalFunctions.lo Interpreter.lo Target.lo \
+ TargetAsmLexer.lo TargetELFWriterInfo.lo \
+ TargetIntrinsicInfo.lo TargetMachOWriterInfo.lo
libllvmfullcodegen_la_OBJECTS = $(am_libllvmfullcodegen_la_OBJECTS)
libllvminterpreter_la_LIBADD =
am_libllvminterpreter_la_OBJECTS = Execution.lo ExternalFunctions.lo \
@@ -298,16 +300,17 @@ am_libllvmjit_la_OBJECTS = AliasAnalysis.lo BasicAliasAnalysis.lo \
SmallPtrSet.lo SmallVector.lo SourceMgr.lo Statistic.lo \
StringExtras.lo StringMap.lo StringPool.lo StringRef.lo \
TargetRegistry.lo Timer.lo Triple.lo Twine.lo \
- circular_raw_ostream.lo raw_ostream.lo SubtargetFeature.lo \
- TargetData.lo TargetInstrInfo.lo TargetLoweringObjectFile.lo \
- TargetMachine.lo TargetRegisterInfo.lo AsmWriter.lo \
- Attributes.lo AutoUpgrade.lo BasicBlock.lo ConstantFold.lo \
- Constants.lo Core.lo Dominators.lo Function.lo Globals.lo \
+ circular_raw_ostream.lo raw_ostream.lo Mangler.lo \
+ SubtargetFeature.lo TargetData.lo TargetInstrInfo.lo \
+ TargetLoweringObjectFile.lo TargetMachine.lo \
+ TargetRegisterInfo.lo AsmWriter.lo Attributes.lo \
+ AutoUpgrade.lo BasicBlock.lo ConstantFold.lo Constants.lo \
+ Core.lo Dominators.lo Function.lo Globals.lo IRBuilder.lo \
InlineAsm.lo Instruction.lo Instructions.lo IntrinsicInst.lo \
- LLVMContext.lo LeakDetector.lo Mangler.lo Metadata.lo \
- Module.lo ModuleProvider.lo Pass.lo PassManager.lo \
- PrintModulePass.lo Type.lo TypeSymbolTable.lo Use.lo Value.lo \
- ValueSymbolTable.lo ValueTypes.lo Verifier.lo
+ LLVMContext.lo LeakDetector.lo Metadata.lo Module.lo \
+ ModuleProvider.lo Pass.lo PassManager.lo PrintModulePass.lo \
+ Type.lo TypeSymbolTable.lo Use.lo Value.lo ValueSymbolTable.lo \
+ ValueTypes.lo Verifier.lo
libllvmjit_la_OBJECTS = $(am_libllvmjit_la_OBJECTS)
libllvmpowerpccodegen_la_LIBADD =
am__libllvmpowerpccodegen_la_SOURCES_DIST = \
@@ -534,7 +537,47 @@ am__tblgen_SOURCES_DIST = llvm/utils/TableGen/AsmMatcherEmitter.cpp \
llvm/utils/TableGen/TableGen.cpp \
llvm/utils/TableGen/TableGenBackend.cpp \
llvm/utils/TableGen/X86DisassemblerTables.cpp \
- llvm/utils/TableGen/X86RecognizableInstr.cpp
+ llvm/utils/TableGen/X86RecognizableInstr.cpp \
+ llvm/lib/System/Alarm.cpp llvm/lib/System/Atomic.cpp \
+ llvm/lib/System/Disassembler.cpp \
+ llvm/lib/System/DynamicLibrary.cpp llvm/lib/System/Errno.cpp \
+ llvm/lib/System/Host.cpp llvm/lib/System/IncludeFile.cpp \
+ llvm/lib/System/Memory.cpp llvm/lib/System/Mutex.cpp \
+ llvm/lib/System/Path.cpp llvm/lib/System/Process.cpp \
+ llvm/lib/System/Program.cpp llvm/lib/System/RWMutex.cpp \
+ llvm/lib/System/Signals.cpp llvm/lib/System/ThreadLocal.cpp \
+ llvm/lib/System/Threading.cpp llvm/lib/System/TimeValue.cpp \
+ llvm/lib/Support/APFloat.cpp llvm/lib/Support/APInt.cpp \
+ llvm/lib/Support/APSInt.cpp llvm/lib/Support/Allocator.cpp \
+ llvm/lib/Support/CommandLine.cpp \
+ llvm/lib/Support/ConstantRange.cpp llvm/lib/Support/Debug.cpp \
+ llvm/lib/Support/DeltaAlgorithm.cpp llvm/lib/Support/Dwarf.cpp \
+ llvm/lib/Support/ErrorHandling.cpp \
+ llvm/lib/Support/FileUtilities.cpp \
+ llvm/lib/Support/FoldingSet.cpp \
+ llvm/lib/Support/FormattedStream.cpp \
+ llvm/lib/Support/GraphWriter.cpp llvm/lib/Support/IsInf.cpp \
+ llvm/lib/Support/IsNAN.cpp llvm/lib/Support/ManagedStatic.cpp \
+ llvm/lib/Support/MemoryBuffer.cpp \
+ llvm/lib/Support/MemoryObject.cpp \
+ llvm/lib/Support/PluginLoader.cpp \
+ llvm/lib/Support/PrettyStackTrace.cpp \
+ llvm/lib/Support/Regex.cpp \
+ llvm/lib/Support/SlowOperationInformer.cpp \
+ llvm/lib/Support/SmallPtrSet.cpp \
+ llvm/lib/Support/SmallVector.cpp \
+ llvm/lib/Support/SourceMgr.cpp llvm/lib/Support/Statistic.cpp \
+ llvm/lib/Support/StringExtras.cpp \
+ llvm/lib/Support/StringMap.cpp llvm/lib/Support/StringPool.cpp \
+ llvm/lib/Support/StringRef.cpp \
+ llvm/lib/Support/SystemUtils.cpp \
+ llvm/lib/Support/TargetRegistry.cpp llvm/lib/Support/Timer.cpp \
+ llvm/lib/Support/Triple.cpp llvm/lib/Support/Twine.cpp \
+ llvm/lib/Support/circular_raw_ostream.cpp \
+ llvm/lib/Support/raw_os_ostream.cpp \
+ llvm/lib/Support/raw_ostream.cpp llvm/lib/Support/regcomp.c \
+ llvm/lib/Support/regerror.c llvm/lib/Support/regexec.c \
+ llvm/lib/Support/regfree.c llvm/lib/Support/regstrlcpy.c
@MAINTAINER_MODE_TRUE at am_tblgen_OBJECTS = \
@MAINTAINER_MODE_TRUE@ tblgen-AsmMatcherEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-AsmWriterEmitter.$(OBJEXT) \
@@ -561,10 +604,70 @@ am__tblgen_SOURCES_DIST = llvm/utils/TableGen/AsmMatcherEmitter.cpp \
@MAINTAINER_MODE_TRUE@ tblgen-TableGen.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-TableGenBackend.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-X86DisassemblerTables.$(OBJEXT) \
- at MAINTAINER_MODE_TRUE@ tblgen-X86RecognizableInstr.$(OBJEXT)
+ at MAINTAINER_MODE_TRUE@ tblgen-X86RecognizableInstr.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Alarm.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Atomic.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Disassembler.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-DynamicLibrary.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Errno.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Host.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-IncludeFile.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Memory.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Mutex.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Path.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Process.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Program.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-RWMutex.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Signals.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-ThreadLocal.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Threading.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-TimeValue.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-APFloat.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-APInt.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-APSInt.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Allocator.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-CommandLine.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-ConstantRange.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Debug.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-DeltaAlgorithm.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Dwarf.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-ErrorHandling.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-FileUtilities.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-FoldingSet.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-FormattedStream.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-GraphWriter.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-IsInf.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-IsNAN.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-ManagedStatic.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-MemoryBuffer.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-MemoryObject.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-PluginLoader.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-PrettyStackTrace.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Regex.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-SlowOperationInformer.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-SmallPtrSet.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-SmallVector.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-SourceMgr.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Statistic.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-StringExtras.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-StringMap.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-StringPool.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-StringRef.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-SystemUtils.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-TargetRegistry.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Timer.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Triple.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-Twine.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-circular_raw_ostream.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-raw_os_ostream.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-raw_ostream.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-regcomp.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-regerror.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-regexec.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-regfree.$(OBJEXT) \
+ at MAINTAINER_MODE_TRUE@ tblgen-regstrlcpy.$(OBJEXT)
tblgen_OBJECTS = $(am_tblgen_OBJECTS)
- at MAINTAINER_MODE_TRUE@tblgen_DEPENDENCIES = libllvmsupport.la \
- at MAINTAINER_MODE_TRUE@ libllvmsystem.la
+tblgen_LDADD = $(LDADD)
tblgen_LINK = $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) \
$(LIBTOOLFLAGS) --mode=link $(CXXLD) $(tblgen_CXXFLAGS) \
$(CXXFLAGS) $(tblgen_LDFLAGS) $(LDFLAGS) -o $@
@@ -802,7 +905,7 @@ LLVM_INCLUDES = -I$(top_srcdir)/llvm/include -I$(top_builddir)/llvm/include
# TODO: HP-UX should have -D_REENTRANT -D_HPUX_SOURCE
LLVM_DEFS = -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -D_DEBUG -D_GNU_SOURCE
AM_CPPFLAGS = -I$(top_srcdir)/../.. -I$(top_srcdir)/.. -I$(top_builddir)/../../ $(LLVM_INCLUDES) $(LLVM_DEFS)
-AM_CXXFLAGS = $(LLVM_CXXFLAGS) -fno-exceptions
+AM_CXXFLAGS = $(LLVM_CXXFLAGS) -fno-exceptions -fno-rtti
ACLOCAL_AMFLAGS = -I m4
@DEBUG_BUILD_FALSE at LLVM_CONFIG = llvm/Release/bin/llvm-config
@DEBUG_BUILD_TRUE at LLVM_CONFIG = llvm/Debug/bin/llvm-config
@@ -829,7 +932,7 @@ libclamavcxx_la_DEPENDENCIES = libllvmjit.la libllvmcodegen.la \
libllvmsystem.la $(am__append_2) $(am__append_6) \
$(am__append_10)
libclamavcxx_la_LDFLAGS = -no-undefined
-libclamavcxx_la_CXXFLAGS = $(LLVM_CXXFLAGS)
+libclamavcxx_la_CXXFLAGS = $(LLVM_CXXFLAGS) -fno-rtti
libclamavcxx_la_SOURCES = bytecode2llvm.cpp
LLVM_CXXFLAGS = -Woverloaded-virtual -pedantic -Wno-long-long -Wall -W -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-variadic-macros
TBLGENFILES = llvm/include/llvm/Intrinsics.gen X86GenRegisterInfo.h.inc X86GenRegisterNames.inc X86GenRegisterInfo.inc X86GenInstrNames.inc X86GenInstrInfo.inc\
@@ -902,9 +1005,12 @@ libllvmsupport_la_SOURCES = \
llvm/lib/Support/regstrlcpy.c
@MAINTAINER_MODE_TRUE at tblgen_CXXFLAGS = $(LLVM_CXXFLAGS)
- at MAINTAINER_MODE_TRUE@tblgen_LDADD = libllvmsupport.la libllvmsystem.la
+ at MAINTAINER_MODE_TRUE@tblgen_CFLAGS =
#TODO: if VERSIONSCRIPT
- at MAINTAINER_MODE_TRUE@tblgen_LDFLAGS = -Wl,--version-script, at top_srcdir@/llvm/autoconf/ExportMap.map
+ at MAINTAINER_MODE_TRUE@tblgen_LDFLAGS = -pthread -Wl,--version-script, at top_srcdir@/llvm/autoconf/ExportMap.map
+# tblgen needs rtti (for now), and we build everything else with -fno-rtti
+# since tblgen is only a maintainer-mode tool, build these files twice (once for
+# libllvmsupport.la -fno-rtti, and once here, with defaults (rtti)).
@MAINTAINER_MODE_TRUE at tblgen_SOURCES = \
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/AsmMatcherEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/AsmWriterEmitter.cpp\
@@ -931,7 +1037,68 @@ libllvmsupport_la_SOURCES = \
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/TableGen.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/TableGenBackend.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/X86DisassemblerTables.cpp\
- at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/X86RecognizableInstr.cpp
+ at MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/X86RecognizableInstr.cpp \
+ at MAINTAINER_MODE_TRUE@ llvm/lib/System/Alarm.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/System/Atomic.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/System/Disassembler.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/System/DynamicLibrary.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/System/Errno.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/System/Host.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/System/IncludeFile.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/System/Memory.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/System/Mutex.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/System/Path.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/System/Process.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/System/Program.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/System/RWMutex.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/System/Signals.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/System/ThreadLocal.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/System/Threading.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/System/TimeValue.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/APFloat.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/APInt.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/APSInt.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/Allocator.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/CommandLine.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/ConstantRange.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/Debug.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/DeltaAlgorithm.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/Dwarf.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/ErrorHandling.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/FileUtilities.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/FoldingSet.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/FormattedStream.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/GraphWriter.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/IsInf.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/IsNAN.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/ManagedStatic.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/MemoryBuffer.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/MemoryObject.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/PluginLoader.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/PrettyStackTrace.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/Regex.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/SlowOperationInformer.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/SmallPtrSet.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/SmallVector.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/SourceMgr.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/Statistic.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/StringExtras.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/StringMap.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/StringPool.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/StringRef.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/SystemUtils.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/TargetRegistry.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/Timer.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/Triple.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/Twine.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/circular_raw_ostream.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/raw_os_ostream.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/raw_ostream.cpp\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/regcomp.c\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/regerror.c\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/regexec.c\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/regfree.c\
+ at MAINTAINER_MODE_TRUE@ llvm/lib/Support/regstrlcpy.c
@MAINTAINER_MODE_TRUE at TBLGEN = $(top_builddir)/tblgen
@MAINTAINER_MODE_TRUE at TBLGEN_V = $(AM_V_GEN)$(TBLGEN)
@@ -1080,6 +1247,7 @@ libllvmjit_la_SOURCES = \
llvm/lib/Support/Twine.cpp\
llvm/lib/Support/circular_raw_ostream.cpp\
llvm/lib/Support/raw_ostream.cpp\
+ llvm/lib/Target/Mangler.cpp\
llvm/lib/Target/SubtargetFeature.cpp\
llvm/lib/Target/TargetData.cpp\
llvm/lib/Target/TargetInstrInfo.cpp\
@@ -1096,13 +1264,13 @@ libllvmjit_la_SOURCES = \
llvm/lib/VMCore/Dominators.cpp\
llvm/lib/VMCore/Function.cpp\
llvm/lib/VMCore/Globals.cpp\
+ llvm/lib/VMCore/IRBuilder.cpp\
llvm/lib/VMCore/InlineAsm.cpp\
llvm/lib/VMCore/Instruction.cpp\
llvm/lib/VMCore/Instructions.cpp\
llvm/lib/VMCore/IntrinsicInst.cpp\
llvm/lib/VMCore/LLVMContext.cpp\
llvm/lib/VMCore/LeakDetector.cpp\
- llvm/lib/VMCore/Mangler.cpp\
llvm/lib/VMCore/Metadata.cpp\
llvm/lib/VMCore/Module.cpp\
llvm/lib/VMCore/ModuleProvider.cpp\
@@ -1152,6 +1320,7 @@ libllvmcodegen_la_SOURCES = \
llvm/lib/CodeGen/LiveStackAnalysis.cpp\
llvm/lib/CodeGen/LiveVariables.cpp\
llvm/lib/CodeGen/LowerSubregs.cpp\
+ llvm/lib/CodeGen/MachOWriter.cpp\
llvm/lib/CodeGen/MachineDominators.cpp\
llvm/lib/CodeGen/MachineLICM.cpp\
llvm/lib/CodeGen/MachineLoopInfo.cpp\
@@ -1159,7 +1328,7 @@ libllvmcodegen_la_SOURCES = \
llvm/lib/CodeGen/MachineSSAUpdater.cpp\
llvm/lib/CodeGen/MachineSink.cpp\
llvm/lib/CodeGen/MachineVerifier.cpp\
- llvm/lib/CodeGen/MaxStackAlignment.cpp\
+ llvm/lib/CodeGen/OptimizeExts.cpp\
llvm/lib/CodeGen/PHIElimination.cpp\
llvm/lib/CodeGen/Passes.cpp\
llvm/lib/CodeGen/PostRASchedulerList.cpp\
@@ -1167,7 +1336,6 @@ libllvmcodegen_la_SOURCES = \
llvm/lib/CodeGen/ProcessImplicitDefs.cpp\
llvm/lib/CodeGen/PrologEpilogInserter.cpp\
llvm/lib/CodeGen/RegAllocLinearScan.cpp\
- llvm/lib/CodeGen/RegAllocLocal.cpp\
llvm/lib/CodeGen/RegisterCoalescer.cpp\
llvm/lib/CodeGen/RegisterScavenging.cpp\
llvm/lib/CodeGen/ScheduleDAG.cpp\
@@ -1210,7 +1378,9 @@ libllvmcodegen_la_SOURCES = \
llvm/lib/CodeGen/VirtRegRewriter.cpp\
llvm/lib/MC/MCAsmInfoDarwin.cpp\
llvm/lib/MC/MCAsmStreamer.cpp\
+ llvm/lib/MC/MCAssembler.cpp\
llvm/lib/MC/MCInst.cpp\
+ llvm/lib/MC/MCMachOStreamer.cpp\
llvm/lib/MC/MCStreamer.cpp\
llvm/lib/Target/TargetFrameInfo.cpp\
llvm/lib/Target/TargetSubtarget.cpp\
@@ -1362,8 +1532,6 @@ libllvmfullcodegen_la_SOURCES = \
llvm/lib/CodeGen/GCMetadataPrinter.cpp\
llvm/lib/CodeGen/IfConversion.cpp\
llvm/lib/CodeGen/IntrinsicLowering.cpp\
- llvm/lib/CodeGen/MachOCodeEmitter.cpp\
- llvm/lib/CodeGen/MachOWriter.cpp\
llvm/lib/CodeGen/MachineModuleInfoImpls.cpp\
llvm/lib/CodeGen/OcamlGC.cpp\
llvm/lib/CodeGen/RegAllocLocal.cpp\
@@ -1373,6 +1541,7 @@ libllvmfullcodegen_la_SOURCES = \
llvm/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp\
llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp\
llvm/lib/Target/Target.cpp\
+ llvm/lib/Target/TargetAsmLexer.cpp\
llvm/lib/Target/TargetELFWriterInfo.cpp\
llvm/lib/Target/TargetIntrinsicInfo.cpp\
llvm/lib/Target/TargetMachOWriterInfo.cpp
@@ -1646,6 +1815,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/Globals.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/GraphWriter.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/Host.Plo at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/IRBuilder.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/IVUsers.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/IfConversion.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/IncludeFile.Plo at am__quote@
@@ -1694,15 +1864,16 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCAsmInfo.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCAsmInfoDarwin.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCAsmStreamer.Plo at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCAssembler.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCContext.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCExpr.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCInst.Plo at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCMachOStreamer.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCSection.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCSectionELF.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCSectionMachO.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCStreamer.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MCSymbol.Plo at am__quote@
- at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MachOCodeEmitter.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MachOWriter.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MachineBasicBlock.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MachineDominators.Plo at am__quote@
@@ -1721,7 +1892,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MachineVerifier.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/ManagedStatic.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/Mangler.Plo at am__quote@
- at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MaxStackAlignment.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/Mem2Reg.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/Memory.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/MemoryBuffer.Plo at am__quote@
@@ -1735,6 +1905,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/OProfileJITEventListener.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/ObjectCodeEmitter.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/OcamlGC.Plo at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/OptimizeExts.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/PHIElimination.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/PHITransAddr.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/Parser.Plo at am__quote@
@@ -1803,6 +1974,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/SystemUtils.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/TailDuplication.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/Target.Plo at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/TargetAsmLexer.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/TargetData.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/TargetELFWriterInfo.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/TargetFrameInfo.Plo at am__quote@
@@ -1966,32 +2138,93 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/regexec.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/regfree.Plo at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/regstrlcpy.Plo at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-APFloat.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-APInt.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-APSInt.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Alarm.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Allocator.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-AsmMatcherEmitter.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-AsmWriterEmitter.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Atomic.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-CallingConvEmitter.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-ClangDiagnosticsEmitter.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-CodeEmitterGen.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-CodeGenDAGPatterns.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-CodeGenInstruction.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-CodeGenTarget.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-CommandLine.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-ConstantRange.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-DAGISelEmitter.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Debug.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-DeltaAlgorithm.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Disassembler.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-DisassemblerEmitter.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Dwarf.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-DynamicLibrary.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Errno.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-ErrorHandling.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-FastISelEmitter.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-FileUtilities.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-FoldingSet.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-FormattedStream.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-GraphWriter.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Host.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-IncludeFile.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-InstrEnumEmitter.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-InstrInfoEmitter.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-IntrinsicEmitter.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-IsInf.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-IsNAN.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-LLVMCConfigurationEmitter.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-ManagedStatic.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Memory.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-MemoryBuffer.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-MemoryObject.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Mutex.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-OptParserEmitter.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Path.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-PluginLoader.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-PrettyStackTrace.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Process.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Program.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-RWMutex.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Record.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Regex.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-RegisterInfoEmitter.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Signals.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-SlowOperationInformer.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-SmallPtrSet.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-SmallVector.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-SourceMgr.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Statistic.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-StringExtras.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-StringMap.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-StringPool.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-StringRef.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-SubtargetEmitter.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-SystemUtils.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-TGLexer.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-TGParser.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-TGValueTypes.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-TableGen.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-TableGenBackend.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-TargetRegistry.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-ThreadLocal.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Threading.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-TimeValue.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Timer.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Triple.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-Twine.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-X86DisassemblerTables.Po at am__quote@
@AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-X86RecognizableInstr.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-circular_raw_ostream.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-raw_os_ostream.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-raw_ostream.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-regcomp.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-regerror.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-regexec.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-regfree.Po at am__quote@
+ at AMDEP_TRUE@@am__include@ @am__quote at ./$(DEPDIR)/tblgen-regstrlcpy.Po at am__quote@
.c.o:
@am__fastdepCC_TRUE@ $(AM_V_CC)$(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
@@ -2073,6 +2306,86 @@ count-count.obj: llvm/utils/count/count.c
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(count_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o count-count.obj `if test -f 'llvm/utils/count/count.c'; then $(CYGPATH_W) 'llvm/utils/count/count.c'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/count/count.c'; fi`
+tblgen-regcomp.o: llvm/lib/Support/regcomp.c
+ at am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CFLAGS) $(CFLAGS) -MT tblgen-regcomp.o -MD -MP -MF $(DEPDIR)/tblgen-regcomp.Tpo -c -o tblgen-regcomp.o `test -f 'llvm/lib/Support/regcomp.c' || echo '$(srcdir)/'`llvm/lib/Support/regcomp.c
+ at am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-regcomp.Tpo $(DEPDIR)/tblgen-regcomp.Po
+ at am__fastdepCC_FALSE@ $(AM_V_CC) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCC_FALSE@ source='llvm/lib/Support/regcomp.c' object='tblgen-regcomp.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CFLAGS) $(CFLAGS) -c -o tblgen-regcomp.o `test -f 'llvm/lib/Support/regcomp.c' || echo '$(srcdir)/'`llvm/lib/Support/regcomp.c
+
+tblgen-regcomp.obj: llvm/lib/Support/regcomp.c
+ at am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CFLAGS) $(CFLAGS) -MT tblgen-regcomp.obj -MD -MP -MF $(DEPDIR)/tblgen-regcomp.Tpo -c -o tblgen-regcomp.obj `if test -f 'llvm/lib/Support/regcomp.c'; then $(CYGPATH_W) 'llvm/lib/Support/regcomp.c'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/regcomp.c'; fi`
+ at am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-regcomp.Tpo $(DEPDIR)/tblgen-regcomp.Po
+ at am__fastdepCC_FALSE@ $(AM_V_CC) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCC_FALSE@ source='llvm/lib/Support/regcomp.c' object='tblgen-regcomp.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CFLAGS) $(CFLAGS) -c -o tblgen-regcomp.obj `if test -f 'llvm/lib/Support/regcomp.c'; then $(CYGPATH_W) 'llvm/lib/Support/regcomp.c'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/regcomp.c'; fi`
+
+tblgen-regerror.o: llvm/lib/Support/regerror.c
+ at am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CFLAGS) $(CFLAGS) -MT tblgen-regerror.o -MD -MP -MF $(DEPDIR)/tblgen-regerror.Tpo -c -o tblgen-regerror.o `test -f 'llvm/lib/Support/regerror.c' || echo '$(srcdir)/'`llvm/lib/Support/regerror.c
+ at am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-regerror.Tpo $(DEPDIR)/tblgen-regerror.Po
+ at am__fastdepCC_FALSE@ $(AM_V_CC) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCC_FALSE@ source='llvm/lib/Support/regerror.c' object='tblgen-regerror.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CFLAGS) $(CFLAGS) -c -o tblgen-regerror.o `test -f 'llvm/lib/Support/regerror.c' || echo '$(srcdir)/'`llvm/lib/Support/regerror.c
+
+tblgen-regerror.obj: llvm/lib/Support/regerror.c
+ at am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CFLAGS) $(CFLAGS) -MT tblgen-regerror.obj -MD -MP -MF $(DEPDIR)/tblgen-regerror.Tpo -c -o tblgen-regerror.obj `if test -f 'llvm/lib/Support/regerror.c'; then $(CYGPATH_W) 'llvm/lib/Support/regerror.c'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/regerror.c'; fi`
+ at am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-regerror.Tpo $(DEPDIR)/tblgen-regerror.Po
+ at am__fastdepCC_FALSE@ $(AM_V_CC) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCC_FALSE@ source='llvm/lib/Support/regerror.c' object='tblgen-regerror.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CFLAGS) $(CFLAGS) -c -o tblgen-regerror.obj `if test -f 'llvm/lib/Support/regerror.c'; then $(CYGPATH_W) 'llvm/lib/Support/regerror.c'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/regerror.c'; fi`
+
+tblgen-regexec.o: llvm/lib/Support/regexec.c
+ at am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CFLAGS) $(CFLAGS) -MT tblgen-regexec.o -MD -MP -MF $(DEPDIR)/tblgen-regexec.Tpo -c -o tblgen-regexec.o `test -f 'llvm/lib/Support/regexec.c' || echo '$(srcdir)/'`llvm/lib/Support/regexec.c
+ at am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-regexec.Tpo $(DEPDIR)/tblgen-regexec.Po
+ at am__fastdepCC_FALSE@ $(AM_V_CC) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCC_FALSE@ source='llvm/lib/Support/regexec.c' object='tblgen-regexec.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CFLAGS) $(CFLAGS) -c -o tblgen-regexec.o `test -f 'llvm/lib/Support/regexec.c' || echo '$(srcdir)/'`llvm/lib/Support/regexec.c
+
+tblgen-regexec.obj: llvm/lib/Support/regexec.c
+ at am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CFLAGS) $(CFLAGS) -MT tblgen-regexec.obj -MD -MP -MF $(DEPDIR)/tblgen-regexec.Tpo -c -o tblgen-regexec.obj `if test -f 'llvm/lib/Support/regexec.c'; then $(CYGPATH_W) 'llvm/lib/Support/regexec.c'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/regexec.c'; fi`
+ at am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-regexec.Tpo $(DEPDIR)/tblgen-regexec.Po
+ at am__fastdepCC_FALSE@ $(AM_V_CC) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCC_FALSE@ source='llvm/lib/Support/regexec.c' object='tblgen-regexec.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CFLAGS) $(CFLAGS) -c -o tblgen-regexec.obj `if test -f 'llvm/lib/Support/regexec.c'; then $(CYGPATH_W) 'llvm/lib/Support/regexec.c'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/regexec.c'; fi`
+
+tblgen-regfree.o: llvm/lib/Support/regfree.c
+ at am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CFLAGS) $(CFLAGS) -MT tblgen-regfree.o -MD -MP -MF $(DEPDIR)/tblgen-regfree.Tpo -c -o tblgen-regfree.o `test -f 'llvm/lib/Support/regfree.c' || echo '$(srcdir)/'`llvm/lib/Support/regfree.c
+ at am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-regfree.Tpo $(DEPDIR)/tblgen-regfree.Po
+ at am__fastdepCC_FALSE@ $(AM_V_CC) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCC_FALSE@ source='llvm/lib/Support/regfree.c' object='tblgen-regfree.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CFLAGS) $(CFLAGS) -c -o tblgen-regfree.o `test -f 'llvm/lib/Support/regfree.c' || echo '$(srcdir)/'`llvm/lib/Support/regfree.c
+
+tblgen-regfree.obj: llvm/lib/Support/regfree.c
+ at am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CFLAGS) $(CFLAGS) -MT tblgen-regfree.obj -MD -MP -MF $(DEPDIR)/tblgen-regfree.Tpo -c -o tblgen-regfree.obj `if test -f 'llvm/lib/Support/regfree.c'; then $(CYGPATH_W) 'llvm/lib/Support/regfree.c'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/regfree.c'; fi`
+ at am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-regfree.Tpo $(DEPDIR)/tblgen-regfree.Po
+ at am__fastdepCC_FALSE@ $(AM_V_CC) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCC_FALSE@ source='llvm/lib/Support/regfree.c' object='tblgen-regfree.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CFLAGS) $(CFLAGS) -c -o tblgen-regfree.obj `if test -f 'llvm/lib/Support/regfree.c'; then $(CYGPATH_W) 'llvm/lib/Support/regfree.c'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/regfree.c'; fi`
+
+tblgen-regstrlcpy.o: llvm/lib/Support/regstrlcpy.c
+ at am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CFLAGS) $(CFLAGS) -MT tblgen-regstrlcpy.o -MD -MP -MF $(DEPDIR)/tblgen-regstrlcpy.Tpo -c -o tblgen-regstrlcpy.o `test -f 'llvm/lib/Support/regstrlcpy.c' || echo '$(srcdir)/'`llvm/lib/Support/regstrlcpy.c
+ at am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-regstrlcpy.Tpo $(DEPDIR)/tblgen-regstrlcpy.Po
+ at am__fastdepCC_FALSE@ $(AM_V_CC) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCC_FALSE@ source='llvm/lib/Support/regstrlcpy.c' object='tblgen-regstrlcpy.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CFLAGS) $(CFLAGS) -c -o tblgen-regstrlcpy.o `test -f 'llvm/lib/Support/regstrlcpy.c' || echo '$(srcdir)/'`llvm/lib/Support/regstrlcpy.c
+
+tblgen-regstrlcpy.obj: llvm/lib/Support/regstrlcpy.c
+ at am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CFLAGS) $(CFLAGS) -MT tblgen-regstrlcpy.obj -MD -MP -MF $(DEPDIR)/tblgen-regstrlcpy.Tpo -c -o tblgen-regstrlcpy.obj `if test -f 'llvm/lib/Support/regstrlcpy.c'; then $(CYGPATH_W) 'llvm/lib/Support/regstrlcpy.c'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/regstrlcpy.c'; fi`
+ at am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-regstrlcpy.Tpo $(DEPDIR)/tblgen-regstrlcpy.Po
+ at am__fastdepCC_FALSE@ $(AM_V_CC) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCC_FALSE@ source='llvm/lib/Support/regstrlcpy.c' object='tblgen-regstrlcpy.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CFLAGS) $(CFLAGS) -c -o tblgen-regstrlcpy.obj `if test -f 'llvm/lib/Support/regstrlcpy.c'; then $(CYGPATH_W) 'llvm/lib/Support/regstrlcpy.c'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/regstrlcpy.c'; fi`
+
.cc.o:
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXXCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
@@ -2865,6 +3178,14 @@ LowerSubregs.lo: llvm/lib/CodeGen/LowerSubregs.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o LowerSubregs.lo `test -f 'llvm/lib/CodeGen/LowerSubregs.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/LowerSubregs.cpp
+MachOWriter.lo: llvm/lib/CodeGen/MachOWriter.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MachOWriter.lo -MD -MP -MF $(DEPDIR)/MachOWriter.Tpo -c -o MachOWriter.lo `test -f 'llvm/lib/CodeGen/MachOWriter.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachOWriter.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MachOWriter.Tpo $(DEPDIR)/MachOWriter.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/CodeGen/MachOWriter.cpp' object='MachOWriter.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MachOWriter.lo `test -f 'llvm/lib/CodeGen/MachOWriter.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachOWriter.cpp
+
MachineDominators.lo: llvm/lib/CodeGen/MachineDominators.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MachineDominators.lo -MD -MP -MF $(DEPDIR)/MachineDominators.Tpo -c -o MachineDominators.lo `test -f 'llvm/lib/CodeGen/MachineDominators.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachineDominators.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MachineDominators.Tpo $(DEPDIR)/MachineDominators.Plo
@@ -2921,13 +3242,13 @@ MachineVerifier.lo: llvm/lib/CodeGen/MachineVerifier.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MachineVerifier.lo `test -f 'llvm/lib/CodeGen/MachineVerifier.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachineVerifier.cpp
-MaxStackAlignment.lo: llvm/lib/CodeGen/MaxStackAlignment.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MaxStackAlignment.lo -MD -MP -MF $(DEPDIR)/MaxStackAlignment.Tpo -c -o MaxStackAlignment.lo `test -f 'llvm/lib/CodeGen/MaxStackAlignment.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MaxStackAlignment.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MaxStackAlignment.Tpo $(DEPDIR)/MaxStackAlignment.Plo
+OptimizeExts.lo: llvm/lib/CodeGen/OptimizeExts.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT OptimizeExts.lo -MD -MP -MF $(DEPDIR)/OptimizeExts.Tpo -c -o OptimizeExts.lo `test -f 'llvm/lib/CodeGen/OptimizeExts.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/OptimizeExts.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/OptimizeExts.Tpo $(DEPDIR)/OptimizeExts.Plo
@am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/CodeGen/MaxStackAlignment.cpp' object='MaxStackAlignment.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/CodeGen/OptimizeExts.cpp' object='OptimizeExts.lo' libtool=yes @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
- at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MaxStackAlignment.lo `test -f 'llvm/lib/CodeGen/MaxStackAlignment.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MaxStackAlignment.cpp
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o OptimizeExts.lo `test -f 'llvm/lib/CodeGen/OptimizeExts.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/OptimizeExts.cpp
PHIElimination.lo: llvm/lib/CodeGen/PHIElimination.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT PHIElimination.lo -MD -MP -MF $(DEPDIR)/PHIElimination.Tpo -c -o PHIElimination.lo `test -f 'llvm/lib/CodeGen/PHIElimination.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/PHIElimination.cpp
@@ -2985,14 +3306,6 @@ RegAllocLinearScan.lo: llvm/lib/CodeGen/RegAllocLinearScan.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o RegAllocLinearScan.lo `test -f 'llvm/lib/CodeGen/RegAllocLinearScan.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/RegAllocLinearScan.cpp
-RegAllocLocal.lo: llvm/lib/CodeGen/RegAllocLocal.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT RegAllocLocal.lo -MD -MP -MF $(DEPDIR)/RegAllocLocal.Tpo -c -o RegAllocLocal.lo `test -f 'llvm/lib/CodeGen/RegAllocLocal.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/RegAllocLocal.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/RegAllocLocal.Tpo $(DEPDIR)/RegAllocLocal.Plo
- at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/CodeGen/RegAllocLocal.cpp' object='RegAllocLocal.lo' libtool=yes @AMDEPBACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
- at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o RegAllocLocal.lo `test -f 'llvm/lib/CodeGen/RegAllocLocal.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/RegAllocLocal.cpp
-
RegisterCoalescer.lo: llvm/lib/CodeGen/RegisterCoalescer.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT RegisterCoalescer.lo -MD -MP -MF $(DEPDIR)/RegisterCoalescer.Tpo -c -o RegisterCoalescer.lo `test -f 'llvm/lib/CodeGen/RegisterCoalescer.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/RegisterCoalescer.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/RegisterCoalescer.Tpo $(DEPDIR)/RegisterCoalescer.Plo
@@ -3329,6 +3642,14 @@ MCAsmStreamer.lo: llvm/lib/MC/MCAsmStreamer.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MCAsmStreamer.lo `test -f 'llvm/lib/MC/MCAsmStreamer.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCAsmStreamer.cpp
+MCAssembler.lo: llvm/lib/MC/MCAssembler.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MCAssembler.lo -MD -MP -MF $(DEPDIR)/MCAssembler.Tpo -c -o MCAssembler.lo `test -f 'llvm/lib/MC/MCAssembler.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCAssembler.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MCAssembler.Tpo $(DEPDIR)/MCAssembler.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/MC/MCAssembler.cpp' object='MCAssembler.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MCAssembler.lo `test -f 'llvm/lib/MC/MCAssembler.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCAssembler.cpp
+
MCInst.lo: llvm/lib/MC/MCInst.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MCInst.lo -MD -MP -MF $(DEPDIR)/MCInst.Tpo -c -o MCInst.lo `test -f 'llvm/lib/MC/MCInst.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCInst.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MCInst.Tpo $(DEPDIR)/MCInst.Plo
@@ -3337,6 +3658,14 @@ MCInst.lo: llvm/lib/MC/MCInst.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MCInst.lo `test -f 'llvm/lib/MC/MCInst.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCInst.cpp
+MCMachOStreamer.lo: llvm/lib/MC/MCMachOStreamer.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MCMachOStreamer.lo -MD -MP -MF $(DEPDIR)/MCMachOStreamer.Tpo -c -o MCMachOStreamer.lo `test -f 'llvm/lib/MC/MCMachOStreamer.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCMachOStreamer.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MCMachOStreamer.Tpo $(DEPDIR)/MCMachOStreamer.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/MC/MCMachOStreamer.cpp' object='MCMachOStreamer.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MCMachOStreamer.lo `test -f 'llvm/lib/MC/MCMachOStreamer.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCMachOStreamer.cpp
+
MCStreamer.lo: llvm/lib/MC/MCStreamer.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MCStreamer.lo -MD -MP -MF $(DEPDIR)/MCStreamer.Tpo -c -o MCStreamer.lo `test -f 'llvm/lib/MC/MCStreamer.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCStreamer.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MCStreamer.Tpo $(DEPDIR)/MCStreamer.Plo
@@ -3537,22 +3866,6 @@ IntrinsicLowering.lo: llvm/lib/CodeGen/IntrinsicLowering.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o IntrinsicLowering.lo `test -f 'llvm/lib/CodeGen/IntrinsicLowering.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/IntrinsicLowering.cpp
-MachOCodeEmitter.lo: llvm/lib/CodeGen/MachOCodeEmitter.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MachOCodeEmitter.lo -MD -MP -MF $(DEPDIR)/MachOCodeEmitter.Tpo -c -o MachOCodeEmitter.lo `test -f 'llvm/lib/CodeGen/MachOCodeEmitter.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachOCodeEmitter.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MachOCodeEmitter.Tpo $(DEPDIR)/MachOCodeEmitter.Plo
- at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/CodeGen/MachOCodeEmitter.cpp' object='MachOCodeEmitter.lo' libtool=yes @AMDEPBACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
- at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MachOCodeEmitter.lo `test -f 'llvm/lib/CodeGen/MachOCodeEmitter.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachOCodeEmitter.cpp
-
-MachOWriter.lo: llvm/lib/CodeGen/MachOWriter.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MachOWriter.lo -MD -MP -MF $(DEPDIR)/MachOWriter.Tpo -c -o MachOWriter.lo `test -f 'llvm/lib/CodeGen/MachOWriter.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachOWriter.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MachOWriter.Tpo $(DEPDIR)/MachOWriter.Plo
- at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/CodeGen/MachOWriter.cpp' object='MachOWriter.lo' libtool=yes @AMDEPBACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
- at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MachOWriter.lo `test -f 'llvm/lib/CodeGen/MachOWriter.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachOWriter.cpp
-
MachineModuleInfoImpls.lo: llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MachineModuleInfoImpls.lo -MD -MP -MF $(DEPDIR)/MachineModuleInfoImpls.Tpo -c -o MachineModuleInfoImpls.lo `test -f 'llvm/lib/CodeGen/MachineModuleInfoImpls.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MachineModuleInfoImpls.Tpo $(DEPDIR)/MachineModuleInfoImpls.Plo
@@ -3569,6 +3882,14 @@ OcamlGC.lo: llvm/lib/CodeGen/OcamlGC.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o OcamlGC.lo `test -f 'llvm/lib/CodeGen/OcamlGC.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/OcamlGC.cpp
+RegAllocLocal.lo: llvm/lib/CodeGen/RegAllocLocal.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT RegAllocLocal.lo -MD -MP -MF $(DEPDIR)/RegAllocLocal.Tpo -c -o RegAllocLocal.lo `test -f 'llvm/lib/CodeGen/RegAllocLocal.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/RegAllocLocal.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/RegAllocLocal.Tpo $(DEPDIR)/RegAllocLocal.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/CodeGen/RegAllocLocal.cpp' object='RegAllocLocal.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o RegAllocLocal.lo `test -f 'llvm/lib/CodeGen/RegAllocLocal.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/RegAllocLocal.cpp
+
RegAllocPBQP.lo: llvm/lib/CodeGen/RegAllocPBQP.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT RegAllocPBQP.lo -MD -MP -MF $(DEPDIR)/RegAllocPBQP.Tpo -c -o RegAllocPBQP.lo `test -f 'llvm/lib/CodeGen/RegAllocPBQP.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/RegAllocPBQP.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/RegAllocPBQP.Tpo $(DEPDIR)/RegAllocPBQP.Plo
@@ -3617,6 +3938,14 @@ Target.lo: llvm/lib/Target/Target.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o Target.lo `test -f 'llvm/lib/Target/Target.cpp' || echo '$(srcdir)/'`llvm/lib/Target/Target.cpp
+TargetAsmLexer.lo: llvm/lib/Target/TargetAsmLexer.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT TargetAsmLexer.lo -MD -MP -MF $(DEPDIR)/TargetAsmLexer.Tpo -c -o TargetAsmLexer.lo `test -f 'llvm/lib/Target/TargetAsmLexer.cpp' || echo '$(srcdir)/'`llvm/lib/Target/TargetAsmLexer.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/TargetAsmLexer.Tpo $(DEPDIR)/TargetAsmLexer.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Target/TargetAsmLexer.cpp' object='TargetAsmLexer.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o TargetAsmLexer.lo `test -f 'llvm/lib/Target/TargetAsmLexer.cpp' || echo '$(srcdir)/'`llvm/lib/Target/TargetAsmLexer.cpp
+
TargetELFWriterInfo.lo: llvm/lib/Target/TargetELFWriterInfo.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT TargetELFWriterInfo.lo -MD -MP -MF $(DEPDIR)/TargetELFWriterInfo.Tpo -c -o TargetELFWriterInfo.lo `test -f 'llvm/lib/Target/TargetELFWriterInfo.cpp' || echo '$(srcdir)/'`llvm/lib/Target/TargetELFWriterInfo.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/TargetELFWriterInfo.Tpo $(DEPDIR)/TargetELFWriterInfo.Plo
@@ -4137,6 +4466,14 @@ raw_ostream.lo: llvm/lib/Support/raw_ostream.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o raw_ostream.lo `test -f 'llvm/lib/Support/raw_ostream.cpp' || echo '$(srcdir)/'`llvm/lib/Support/raw_ostream.cpp
+Mangler.lo: llvm/lib/Target/Mangler.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT Mangler.lo -MD -MP -MF $(DEPDIR)/Mangler.Tpo -c -o Mangler.lo `test -f 'llvm/lib/Target/Mangler.cpp' || echo '$(srcdir)/'`llvm/lib/Target/Mangler.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/Mangler.Tpo $(DEPDIR)/Mangler.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Target/Mangler.cpp' object='Mangler.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o Mangler.lo `test -f 'llvm/lib/Target/Mangler.cpp' || echo '$(srcdir)/'`llvm/lib/Target/Mangler.cpp
+
SubtargetFeature.lo: llvm/lib/Target/SubtargetFeature.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT SubtargetFeature.lo -MD -MP -MF $(DEPDIR)/SubtargetFeature.Tpo -c -o SubtargetFeature.lo `test -f 'llvm/lib/Target/SubtargetFeature.cpp' || echo '$(srcdir)/'`llvm/lib/Target/SubtargetFeature.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/SubtargetFeature.Tpo $(DEPDIR)/SubtargetFeature.Plo
@@ -4265,6 +4602,14 @@ Globals.lo: llvm/lib/VMCore/Globals.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o Globals.lo `test -f 'llvm/lib/VMCore/Globals.cpp' || echo '$(srcdir)/'`llvm/lib/VMCore/Globals.cpp
+IRBuilder.lo: llvm/lib/VMCore/IRBuilder.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT IRBuilder.lo -MD -MP -MF $(DEPDIR)/IRBuilder.Tpo -c -o IRBuilder.lo `test -f 'llvm/lib/VMCore/IRBuilder.cpp' || echo '$(srcdir)/'`llvm/lib/VMCore/IRBuilder.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/IRBuilder.Tpo $(DEPDIR)/IRBuilder.Plo
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/VMCore/IRBuilder.cpp' object='IRBuilder.lo' libtool=yes @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o IRBuilder.lo `test -f 'llvm/lib/VMCore/IRBuilder.cpp' || echo '$(srcdir)/'`llvm/lib/VMCore/IRBuilder.cpp
+
InlineAsm.lo: llvm/lib/VMCore/InlineAsm.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT InlineAsm.lo -MD -MP -MF $(DEPDIR)/InlineAsm.Tpo -c -o InlineAsm.lo `test -f 'llvm/lib/VMCore/InlineAsm.cpp' || echo '$(srcdir)/'`llvm/lib/VMCore/InlineAsm.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/InlineAsm.Tpo $(DEPDIR)/InlineAsm.Plo
@@ -4313,14 +4658,6 @@ LeakDetector.lo: llvm/lib/VMCore/LeakDetector.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o LeakDetector.lo `test -f 'llvm/lib/VMCore/LeakDetector.cpp' || echo '$(srcdir)/'`llvm/lib/VMCore/LeakDetector.cpp
-Mangler.lo: llvm/lib/VMCore/Mangler.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT Mangler.lo -MD -MP -MF $(DEPDIR)/Mangler.Tpo -c -o Mangler.lo `test -f 'llvm/lib/VMCore/Mangler.cpp' || echo '$(srcdir)/'`llvm/lib/VMCore/Mangler.cpp
- at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/Mangler.Tpo $(DEPDIR)/Mangler.Plo
- at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/VMCore/Mangler.cpp' object='Mangler.lo' libtool=yes @AMDEPBACKSLASH@
- at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
- at am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o Mangler.lo `test -f 'llvm/lib/VMCore/Mangler.cpp' || echo '$(srcdir)/'`llvm/lib/VMCore/Mangler.cpp
-
Metadata.lo: llvm/lib/VMCore/Metadata.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT Metadata.lo -MD -MP -MF $(DEPDIR)/Metadata.Tpo -c -o Metadata.lo `test -f 'llvm/lib/VMCore/Metadata.cpp' || echo '$(srcdir)/'`llvm/lib/VMCore/Metadata.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/Metadata.Tpo $(DEPDIR)/Metadata.Plo
@@ -5961,6 +6298,902 @@ tblgen-X86RecognizableInstr.obj: llvm/utils/TableGen/X86RecognizableInstr.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-X86RecognizableInstr.obj `if test -f 'llvm/utils/TableGen/X86RecognizableInstr.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/X86RecognizableInstr.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/X86RecognizableInstr.cpp'; fi`
+tblgen-Alarm.o: llvm/lib/System/Alarm.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Alarm.o -MD -MP -MF $(DEPDIR)/tblgen-Alarm.Tpo -c -o tblgen-Alarm.o `test -f 'llvm/lib/System/Alarm.cpp' || echo '$(srcdir)/'`llvm/lib/System/Alarm.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Alarm.Tpo $(DEPDIR)/tblgen-Alarm.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Alarm.cpp' object='tblgen-Alarm.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Alarm.o `test -f 'llvm/lib/System/Alarm.cpp' || echo '$(srcdir)/'`llvm/lib/System/Alarm.cpp
+
+tblgen-Alarm.obj: llvm/lib/System/Alarm.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Alarm.obj -MD -MP -MF $(DEPDIR)/tblgen-Alarm.Tpo -c -o tblgen-Alarm.obj `if test -f 'llvm/lib/System/Alarm.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Alarm.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Alarm.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Alarm.Tpo $(DEPDIR)/tblgen-Alarm.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Alarm.cpp' object='tblgen-Alarm.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Alarm.obj `if test -f 'llvm/lib/System/Alarm.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Alarm.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Alarm.cpp'; fi`
+
+tblgen-Atomic.o: llvm/lib/System/Atomic.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Atomic.o -MD -MP -MF $(DEPDIR)/tblgen-Atomic.Tpo -c -o tblgen-Atomic.o `test -f 'llvm/lib/System/Atomic.cpp' || echo '$(srcdir)/'`llvm/lib/System/Atomic.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Atomic.Tpo $(DEPDIR)/tblgen-Atomic.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Atomic.cpp' object='tblgen-Atomic.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Atomic.o `test -f 'llvm/lib/System/Atomic.cpp' || echo '$(srcdir)/'`llvm/lib/System/Atomic.cpp
+
+tblgen-Atomic.obj: llvm/lib/System/Atomic.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Atomic.obj -MD -MP -MF $(DEPDIR)/tblgen-Atomic.Tpo -c -o tblgen-Atomic.obj `if test -f 'llvm/lib/System/Atomic.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Atomic.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Atomic.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Atomic.Tpo $(DEPDIR)/tblgen-Atomic.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Atomic.cpp' object='tblgen-Atomic.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Atomic.obj `if test -f 'llvm/lib/System/Atomic.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Atomic.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Atomic.cpp'; fi`
+
+tblgen-Disassembler.o: llvm/lib/System/Disassembler.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Disassembler.o -MD -MP -MF $(DEPDIR)/tblgen-Disassembler.Tpo -c -o tblgen-Disassembler.o `test -f 'llvm/lib/System/Disassembler.cpp' || echo '$(srcdir)/'`llvm/lib/System/Disassembler.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Disassembler.Tpo $(DEPDIR)/tblgen-Disassembler.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Disassembler.cpp' object='tblgen-Disassembler.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Disassembler.o `test -f 'llvm/lib/System/Disassembler.cpp' || echo '$(srcdir)/'`llvm/lib/System/Disassembler.cpp
+
+tblgen-Disassembler.obj: llvm/lib/System/Disassembler.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Disassembler.obj -MD -MP -MF $(DEPDIR)/tblgen-Disassembler.Tpo -c -o tblgen-Disassembler.obj `if test -f 'llvm/lib/System/Disassembler.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Disassembler.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Disassembler.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Disassembler.Tpo $(DEPDIR)/tblgen-Disassembler.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Disassembler.cpp' object='tblgen-Disassembler.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Disassembler.obj `if test -f 'llvm/lib/System/Disassembler.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Disassembler.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Disassembler.cpp'; fi`
+
+tblgen-DynamicLibrary.o: llvm/lib/System/DynamicLibrary.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DynamicLibrary.o -MD -MP -MF $(DEPDIR)/tblgen-DynamicLibrary.Tpo -c -o tblgen-DynamicLibrary.o `test -f 'llvm/lib/System/DynamicLibrary.cpp' || echo '$(srcdir)/'`llvm/lib/System/DynamicLibrary.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DynamicLibrary.Tpo $(DEPDIR)/tblgen-DynamicLibrary.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/DynamicLibrary.cpp' object='tblgen-DynamicLibrary.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DynamicLibrary.o `test -f 'llvm/lib/System/DynamicLibrary.cpp' || echo '$(srcdir)/'`llvm/lib/System/DynamicLibrary.cpp
+
+tblgen-DynamicLibrary.obj: llvm/lib/System/DynamicLibrary.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DynamicLibrary.obj -MD -MP -MF $(DEPDIR)/tblgen-DynamicLibrary.Tpo -c -o tblgen-DynamicLibrary.obj `if test -f 'llvm/lib/System/DynamicLibrary.cpp'; then $(CYGPATH_W) 'llvm/lib/System/DynamicLibrary.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/DynamicLibrary.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DynamicLibrary.Tpo $(DEPDIR)/tblgen-DynamicLibrary.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/DynamicLibrary.cpp' object='tblgen-DynamicLibrary.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DynamicLibrary.obj `if test -f 'llvm/lib/System/DynamicLibrary.cpp'; then $(CYGPATH_W) 'llvm/lib/System/DynamicLibrary.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/DynamicLibrary.cpp'; fi`
+
+tblgen-Errno.o: llvm/lib/System/Errno.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Errno.o -MD -MP -MF $(DEPDIR)/tblgen-Errno.Tpo -c -o tblgen-Errno.o `test -f 'llvm/lib/System/Errno.cpp' || echo '$(srcdir)/'`llvm/lib/System/Errno.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Errno.Tpo $(DEPDIR)/tblgen-Errno.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Errno.cpp' object='tblgen-Errno.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Errno.o `test -f 'llvm/lib/System/Errno.cpp' || echo '$(srcdir)/'`llvm/lib/System/Errno.cpp
+
+tblgen-Errno.obj: llvm/lib/System/Errno.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Errno.obj -MD -MP -MF $(DEPDIR)/tblgen-Errno.Tpo -c -o tblgen-Errno.obj `if test -f 'llvm/lib/System/Errno.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Errno.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Errno.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Errno.Tpo $(DEPDIR)/tblgen-Errno.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Errno.cpp' object='tblgen-Errno.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Errno.obj `if test -f 'llvm/lib/System/Errno.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Errno.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Errno.cpp'; fi`
+
+tblgen-Host.o: llvm/lib/System/Host.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Host.o -MD -MP -MF $(DEPDIR)/tblgen-Host.Tpo -c -o tblgen-Host.o `test -f 'llvm/lib/System/Host.cpp' || echo '$(srcdir)/'`llvm/lib/System/Host.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Host.Tpo $(DEPDIR)/tblgen-Host.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Host.cpp' object='tblgen-Host.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Host.o `test -f 'llvm/lib/System/Host.cpp' || echo '$(srcdir)/'`llvm/lib/System/Host.cpp
+
+tblgen-Host.obj: llvm/lib/System/Host.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Host.obj -MD -MP -MF $(DEPDIR)/tblgen-Host.Tpo -c -o tblgen-Host.obj `if test -f 'llvm/lib/System/Host.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Host.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Host.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Host.Tpo $(DEPDIR)/tblgen-Host.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Host.cpp' object='tblgen-Host.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Host.obj `if test -f 'llvm/lib/System/Host.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Host.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Host.cpp'; fi`
+
+tblgen-IncludeFile.o: llvm/lib/System/IncludeFile.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-IncludeFile.o -MD -MP -MF $(DEPDIR)/tblgen-IncludeFile.Tpo -c -o tblgen-IncludeFile.o `test -f 'llvm/lib/System/IncludeFile.cpp' || echo '$(srcdir)/'`llvm/lib/System/IncludeFile.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-IncludeFile.Tpo $(DEPDIR)/tblgen-IncludeFile.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/IncludeFile.cpp' object='tblgen-IncludeFile.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-IncludeFile.o `test -f 'llvm/lib/System/IncludeFile.cpp' || echo '$(srcdir)/'`llvm/lib/System/IncludeFile.cpp
+
+tblgen-IncludeFile.obj: llvm/lib/System/IncludeFile.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-IncludeFile.obj -MD -MP -MF $(DEPDIR)/tblgen-IncludeFile.Tpo -c -o tblgen-IncludeFile.obj `if test -f 'llvm/lib/System/IncludeFile.cpp'; then $(CYGPATH_W) 'llvm/lib/System/IncludeFile.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/IncludeFile.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-IncludeFile.Tpo $(DEPDIR)/tblgen-IncludeFile.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/IncludeFile.cpp' object='tblgen-IncludeFile.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-IncludeFile.obj `if test -f 'llvm/lib/System/IncludeFile.cpp'; then $(CYGPATH_W) 'llvm/lib/System/IncludeFile.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/IncludeFile.cpp'; fi`
+
+tblgen-Memory.o: llvm/lib/System/Memory.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Memory.o -MD -MP -MF $(DEPDIR)/tblgen-Memory.Tpo -c -o tblgen-Memory.o `test -f 'llvm/lib/System/Memory.cpp' || echo '$(srcdir)/'`llvm/lib/System/Memory.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Memory.Tpo $(DEPDIR)/tblgen-Memory.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Memory.cpp' object='tblgen-Memory.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Memory.o `test -f 'llvm/lib/System/Memory.cpp' || echo '$(srcdir)/'`llvm/lib/System/Memory.cpp
+
+tblgen-Memory.obj: llvm/lib/System/Memory.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Memory.obj -MD -MP -MF $(DEPDIR)/tblgen-Memory.Tpo -c -o tblgen-Memory.obj `if test -f 'llvm/lib/System/Memory.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Memory.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Memory.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Memory.Tpo $(DEPDIR)/tblgen-Memory.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Memory.cpp' object='tblgen-Memory.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Memory.obj `if test -f 'llvm/lib/System/Memory.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Memory.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Memory.cpp'; fi`
+
+tblgen-Mutex.o: llvm/lib/System/Mutex.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Mutex.o -MD -MP -MF $(DEPDIR)/tblgen-Mutex.Tpo -c -o tblgen-Mutex.o `test -f 'llvm/lib/System/Mutex.cpp' || echo '$(srcdir)/'`llvm/lib/System/Mutex.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Mutex.Tpo $(DEPDIR)/tblgen-Mutex.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Mutex.cpp' object='tblgen-Mutex.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Mutex.o `test -f 'llvm/lib/System/Mutex.cpp' || echo '$(srcdir)/'`llvm/lib/System/Mutex.cpp
+
+tblgen-Mutex.obj: llvm/lib/System/Mutex.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Mutex.obj -MD -MP -MF $(DEPDIR)/tblgen-Mutex.Tpo -c -o tblgen-Mutex.obj `if test -f 'llvm/lib/System/Mutex.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Mutex.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Mutex.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Mutex.Tpo $(DEPDIR)/tblgen-Mutex.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Mutex.cpp' object='tblgen-Mutex.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Mutex.obj `if test -f 'llvm/lib/System/Mutex.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Mutex.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Mutex.cpp'; fi`
+
+tblgen-Path.o: llvm/lib/System/Path.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Path.o -MD -MP -MF $(DEPDIR)/tblgen-Path.Tpo -c -o tblgen-Path.o `test -f 'llvm/lib/System/Path.cpp' || echo '$(srcdir)/'`llvm/lib/System/Path.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Path.Tpo $(DEPDIR)/tblgen-Path.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Path.cpp' object='tblgen-Path.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Path.o `test -f 'llvm/lib/System/Path.cpp' || echo '$(srcdir)/'`llvm/lib/System/Path.cpp
+
+tblgen-Path.obj: llvm/lib/System/Path.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Path.obj -MD -MP -MF $(DEPDIR)/tblgen-Path.Tpo -c -o tblgen-Path.obj `if test -f 'llvm/lib/System/Path.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Path.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Path.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Path.Tpo $(DEPDIR)/tblgen-Path.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Path.cpp' object='tblgen-Path.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Path.obj `if test -f 'llvm/lib/System/Path.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Path.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Path.cpp'; fi`
+
+tblgen-Process.o: llvm/lib/System/Process.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Process.o -MD -MP -MF $(DEPDIR)/tblgen-Process.Tpo -c -o tblgen-Process.o `test -f 'llvm/lib/System/Process.cpp' || echo '$(srcdir)/'`llvm/lib/System/Process.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Process.Tpo $(DEPDIR)/tblgen-Process.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Process.cpp' object='tblgen-Process.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Process.o `test -f 'llvm/lib/System/Process.cpp' || echo '$(srcdir)/'`llvm/lib/System/Process.cpp
+
+tblgen-Process.obj: llvm/lib/System/Process.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Process.obj -MD -MP -MF $(DEPDIR)/tblgen-Process.Tpo -c -o tblgen-Process.obj `if test -f 'llvm/lib/System/Process.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Process.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Process.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Process.Tpo $(DEPDIR)/tblgen-Process.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Process.cpp' object='tblgen-Process.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Process.obj `if test -f 'llvm/lib/System/Process.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Process.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Process.cpp'; fi`
+
+tblgen-Program.o: llvm/lib/System/Program.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Program.o -MD -MP -MF $(DEPDIR)/tblgen-Program.Tpo -c -o tblgen-Program.o `test -f 'llvm/lib/System/Program.cpp' || echo '$(srcdir)/'`llvm/lib/System/Program.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Program.Tpo $(DEPDIR)/tblgen-Program.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Program.cpp' object='tblgen-Program.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Program.o `test -f 'llvm/lib/System/Program.cpp' || echo '$(srcdir)/'`llvm/lib/System/Program.cpp
+
+tblgen-Program.obj: llvm/lib/System/Program.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Program.obj -MD -MP -MF $(DEPDIR)/tblgen-Program.Tpo -c -o tblgen-Program.obj `if test -f 'llvm/lib/System/Program.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Program.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Program.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Program.Tpo $(DEPDIR)/tblgen-Program.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Program.cpp' object='tblgen-Program.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Program.obj `if test -f 'llvm/lib/System/Program.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Program.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Program.cpp'; fi`
+
+tblgen-RWMutex.o: llvm/lib/System/RWMutex.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-RWMutex.o -MD -MP -MF $(DEPDIR)/tblgen-RWMutex.Tpo -c -o tblgen-RWMutex.o `test -f 'llvm/lib/System/RWMutex.cpp' || echo '$(srcdir)/'`llvm/lib/System/RWMutex.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-RWMutex.Tpo $(DEPDIR)/tblgen-RWMutex.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/RWMutex.cpp' object='tblgen-RWMutex.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-RWMutex.o `test -f 'llvm/lib/System/RWMutex.cpp' || echo '$(srcdir)/'`llvm/lib/System/RWMutex.cpp
+
+tblgen-RWMutex.obj: llvm/lib/System/RWMutex.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-RWMutex.obj -MD -MP -MF $(DEPDIR)/tblgen-RWMutex.Tpo -c -o tblgen-RWMutex.obj `if test -f 'llvm/lib/System/RWMutex.cpp'; then $(CYGPATH_W) 'llvm/lib/System/RWMutex.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/RWMutex.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-RWMutex.Tpo $(DEPDIR)/tblgen-RWMutex.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/RWMutex.cpp' object='tblgen-RWMutex.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-RWMutex.obj `if test -f 'llvm/lib/System/RWMutex.cpp'; then $(CYGPATH_W) 'llvm/lib/System/RWMutex.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/RWMutex.cpp'; fi`
+
+tblgen-Signals.o: llvm/lib/System/Signals.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Signals.o -MD -MP -MF $(DEPDIR)/tblgen-Signals.Tpo -c -o tblgen-Signals.o `test -f 'llvm/lib/System/Signals.cpp' || echo '$(srcdir)/'`llvm/lib/System/Signals.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Signals.Tpo $(DEPDIR)/tblgen-Signals.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Signals.cpp' object='tblgen-Signals.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Signals.o `test -f 'llvm/lib/System/Signals.cpp' || echo '$(srcdir)/'`llvm/lib/System/Signals.cpp
+
+tblgen-Signals.obj: llvm/lib/System/Signals.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Signals.obj -MD -MP -MF $(DEPDIR)/tblgen-Signals.Tpo -c -o tblgen-Signals.obj `if test -f 'llvm/lib/System/Signals.cpp'; then $(CYGPATH_W) 'llvm/lib/System/Signals.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/System/Signals.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Signals.Tpo $(DEPDIR)/tblgen-Signals.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/System/Signals.cpp' object='tblgen-Signals.obj' libtool=no @AMDEPBACKSLASH@
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+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/ConstantRange.cpp' object='tblgen-ConstantRange.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-ConstantRange.obj `if test -f 'llvm/lib/Support/ConstantRange.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/ConstantRange.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/ConstantRange.cpp'; fi`
+
+tblgen-Debug.o: llvm/lib/Support/Debug.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Debug.o -MD -MP -MF $(DEPDIR)/tblgen-Debug.Tpo -c -o tblgen-Debug.o `test -f 'llvm/lib/Support/Debug.cpp' || echo '$(srcdir)/'`llvm/lib/Support/Debug.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Debug.Tpo $(DEPDIR)/tblgen-Debug.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
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+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Debug.o `test -f 'llvm/lib/Support/Debug.cpp' || echo '$(srcdir)/'`llvm/lib/Support/Debug.cpp
+
+tblgen-Debug.obj: llvm/lib/Support/Debug.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Debug.obj -MD -MP -MF $(DEPDIR)/tblgen-Debug.Tpo -c -o tblgen-Debug.obj `if test -f 'llvm/lib/Support/Debug.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/Debug.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/Debug.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Debug.Tpo $(DEPDIR)/tblgen-Debug.Po
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+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Debug.obj `if test -f 'llvm/lib/Support/Debug.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/Debug.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/Debug.cpp'; fi`
+
+tblgen-DeltaAlgorithm.o: llvm/lib/Support/DeltaAlgorithm.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DeltaAlgorithm.o -MD -MP -MF $(DEPDIR)/tblgen-DeltaAlgorithm.Tpo -c -o tblgen-DeltaAlgorithm.o `test -f 'llvm/lib/Support/DeltaAlgorithm.cpp' || echo '$(srcdir)/'`llvm/lib/Support/DeltaAlgorithm.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DeltaAlgorithm.Tpo $(DEPDIR)/tblgen-DeltaAlgorithm.Po
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+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/DeltaAlgorithm.cpp' object='tblgen-DeltaAlgorithm.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DeltaAlgorithm.o `test -f 'llvm/lib/Support/DeltaAlgorithm.cpp' || echo '$(srcdir)/'`llvm/lib/Support/DeltaAlgorithm.cpp
+
+tblgen-DeltaAlgorithm.obj: llvm/lib/Support/DeltaAlgorithm.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DeltaAlgorithm.obj -MD -MP -MF $(DEPDIR)/tblgen-DeltaAlgorithm.Tpo -c -o tblgen-DeltaAlgorithm.obj `if test -f 'llvm/lib/Support/DeltaAlgorithm.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/DeltaAlgorithm.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/DeltaAlgorithm.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DeltaAlgorithm.Tpo $(DEPDIR)/tblgen-DeltaAlgorithm.Po
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+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DeltaAlgorithm.obj `if test -f 'llvm/lib/Support/DeltaAlgorithm.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/DeltaAlgorithm.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/DeltaAlgorithm.cpp'; fi`
+
+tblgen-Dwarf.o: llvm/lib/Support/Dwarf.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Dwarf.o -MD -MP -MF $(DEPDIR)/tblgen-Dwarf.Tpo -c -o tblgen-Dwarf.o `test -f 'llvm/lib/Support/Dwarf.cpp' || echo '$(srcdir)/'`llvm/lib/Support/Dwarf.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Dwarf.Tpo $(DEPDIR)/tblgen-Dwarf.Po
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+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/Dwarf.cpp' object='tblgen-Dwarf.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Dwarf.o `test -f 'llvm/lib/Support/Dwarf.cpp' || echo '$(srcdir)/'`llvm/lib/Support/Dwarf.cpp
+
+tblgen-Dwarf.obj: llvm/lib/Support/Dwarf.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Dwarf.obj -MD -MP -MF $(DEPDIR)/tblgen-Dwarf.Tpo -c -o tblgen-Dwarf.obj `if test -f 'llvm/lib/Support/Dwarf.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/Dwarf.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/Dwarf.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Dwarf.Tpo $(DEPDIR)/tblgen-Dwarf.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
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+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Dwarf.obj `if test -f 'llvm/lib/Support/Dwarf.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/Dwarf.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/Dwarf.cpp'; fi`
+
+tblgen-ErrorHandling.o: llvm/lib/Support/ErrorHandling.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-ErrorHandling.o -MD -MP -MF $(DEPDIR)/tblgen-ErrorHandling.Tpo -c -o tblgen-ErrorHandling.o `test -f 'llvm/lib/Support/ErrorHandling.cpp' || echo '$(srcdir)/'`llvm/lib/Support/ErrorHandling.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-ErrorHandling.Tpo $(DEPDIR)/tblgen-ErrorHandling.Po
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+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-ErrorHandling.o `test -f 'llvm/lib/Support/ErrorHandling.cpp' || echo '$(srcdir)/'`llvm/lib/Support/ErrorHandling.cpp
+
+tblgen-ErrorHandling.obj: llvm/lib/Support/ErrorHandling.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-ErrorHandling.obj -MD -MP -MF $(DEPDIR)/tblgen-ErrorHandling.Tpo -c -o tblgen-ErrorHandling.obj `if test -f 'llvm/lib/Support/ErrorHandling.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/ErrorHandling.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/ErrorHandling.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-ErrorHandling.Tpo $(DEPDIR)/tblgen-ErrorHandling.Po
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+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-ErrorHandling.obj `if test -f 'llvm/lib/Support/ErrorHandling.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/ErrorHandling.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/ErrorHandling.cpp'; fi`
+
+tblgen-FileUtilities.o: llvm/lib/Support/FileUtilities.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-FileUtilities.o -MD -MP -MF $(DEPDIR)/tblgen-FileUtilities.Tpo -c -o tblgen-FileUtilities.o `test -f 'llvm/lib/Support/FileUtilities.cpp' || echo '$(srcdir)/'`llvm/lib/Support/FileUtilities.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-FileUtilities.Tpo $(DEPDIR)/tblgen-FileUtilities.Po
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+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-FileUtilities.o `test -f 'llvm/lib/Support/FileUtilities.cpp' || echo '$(srcdir)/'`llvm/lib/Support/FileUtilities.cpp
+
+tblgen-FileUtilities.obj: llvm/lib/Support/FileUtilities.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-FileUtilities.obj -MD -MP -MF $(DEPDIR)/tblgen-FileUtilities.Tpo -c -o tblgen-FileUtilities.obj `if test -f 'llvm/lib/Support/FileUtilities.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/FileUtilities.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/FileUtilities.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-FileUtilities.Tpo $(DEPDIR)/tblgen-FileUtilities.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
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+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-FileUtilities.obj `if test -f 'llvm/lib/Support/FileUtilities.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/FileUtilities.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/FileUtilities.cpp'; fi`
+
+tblgen-FoldingSet.o: llvm/lib/Support/FoldingSet.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-FoldingSet.o -MD -MP -MF $(DEPDIR)/tblgen-FoldingSet.Tpo -c -o tblgen-FoldingSet.o `test -f 'llvm/lib/Support/FoldingSet.cpp' || echo '$(srcdir)/'`llvm/lib/Support/FoldingSet.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-FoldingSet.Tpo $(DEPDIR)/tblgen-FoldingSet.Po
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+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-FoldingSet.o `test -f 'llvm/lib/Support/FoldingSet.cpp' || echo '$(srcdir)/'`llvm/lib/Support/FoldingSet.cpp
+
+tblgen-FoldingSet.obj: llvm/lib/Support/FoldingSet.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-FoldingSet.obj -MD -MP -MF $(DEPDIR)/tblgen-FoldingSet.Tpo -c -o tblgen-FoldingSet.obj `if test -f 'llvm/lib/Support/FoldingSet.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/FoldingSet.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/FoldingSet.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-FoldingSet.Tpo $(DEPDIR)/tblgen-FoldingSet.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
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+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-FoldingSet.obj `if test -f 'llvm/lib/Support/FoldingSet.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/FoldingSet.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/FoldingSet.cpp'; fi`
+
+tblgen-FormattedStream.o: llvm/lib/Support/FormattedStream.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-FormattedStream.o -MD -MP -MF $(DEPDIR)/tblgen-FormattedStream.Tpo -c -o tblgen-FormattedStream.o `test -f 'llvm/lib/Support/FormattedStream.cpp' || echo '$(srcdir)/'`llvm/lib/Support/FormattedStream.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-FormattedStream.Tpo $(DEPDIR)/tblgen-FormattedStream.Po
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+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-FormattedStream.o `test -f 'llvm/lib/Support/FormattedStream.cpp' || echo '$(srcdir)/'`llvm/lib/Support/FormattedStream.cpp
+
+tblgen-FormattedStream.obj: llvm/lib/Support/FormattedStream.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-FormattedStream.obj -MD -MP -MF $(DEPDIR)/tblgen-FormattedStream.Tpo -c -o tblgen-FormattedStream.obj `if test -f 'llvm/lib/Support/FormattedStream.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/FormattedStream.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/FormattedStream.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-FormattedStream.Tpo $(DEPDIR)/tblgen-FormattedStream.Po
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+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-FormattedStream.obj `if test -f 'llvm/lib/Support/FormattedStream.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/FormattedStream.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/FormattedStream.cpp'; fi`
+
+tblgen-GraphWriter.o: llvm/lib/Support/GraphWriter.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-GraphWriter.o -MD -MP -MF $(DEPDIR)/tblgen-GraphWriter.Tpo -c -o tblgen-GraphWriter.o `test -f 'llvm/lib/Support/GraphWriter.cpp' || echo '$(srcdir)/'`llvm/lib/Support/GraphWriter.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-GraphWriter.Tpo $(DEPDIR)/tblgen-GraphWriter.Po
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+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-GraphWriter.o `test -f 'llvm/lib/Support/GraphWriter.cpp' || echo '$(srcdir)/'`llvm/lib/Support/GraphWriter.cpp
+
+tblgen-GraphWriter.obj: llvm/lib/Support/GraphWriter.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-GraphWriter.obj -MD -MP -MF $(DEPDIR)/tblgen-GraphWriter.Tpo -c -o tblgen-GraphWriter.obj `if test -f 'llvm/lib/Support/GraphWriter.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/GraphWriter.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/GraphWriter.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-GraphWriter.Tpo $(DEPDIR)/tblgen-GraphWriter.Po
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+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-GraphWriter.obj `if test -f 'llvm/lib/Support/GraphWriter.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/GraphWriter.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/GraphWriter.cpp'; fi`
+
+tblgen-IsInf.o: llvm/lib/Support/IsInf.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-IsInf.o -MD -MP -MF $(DEPDIR)/tblgen-IsInf.Tpo -c -o tblgen-IsInf.o `test -f 'llvm/lib/Support/IsInf.cpp' || echo '$(srcdir)/'`llvm/lib/Support/IsInf.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-IsInf.Tpo $(DEPDIR)/tblgen-IsInf.Po
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+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-IsInf.o `test -f 'llvm/lib/Support/IsInf.cpp' || echo '$(srcdir)/'`llvm/lib/Support/IsInf.cpp
+
+tblgen-IsInf.obj: llvm/lib/Support/IsInf.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-IsInf.obj -MD -MP -MF $(DEPDIR)/tblgen-IsInf.Tpo -c -o tblgen-IsInf.obj `if test -f 'llvm/lib/Support/IsInf.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/IsInf.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/IsInf.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-IsInf.Tpo $(DEPDIR)/tblgen-IsInf.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/IsInf.cpp' object='tblgen-IsInf.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-IsInf.obj `if test -f 'llvm/lib/Support/IsInf.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/IsInf.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/IsInf.cpp'; fi`
+
+tblgen-IsNAN.o: llvm/lib/Support/IsNAN.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-IsNAN.o -MD -MP -MF $(DEPDIR)/tblgen-IsNAN.Tpo -c -o tblgen-IsNAN.o `test -f 'llvm/lib/Support/IsNAN.cpp' || echo '$(srcdir)/'`llvm/lib/Support/IsNAN.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-IsNAN.Tpo $(DEPDIR)/tblgen-IsNAN.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/IsNAN.cpp' object='tblgen-IsNAN.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-IsNAN.o `test -f 'llvm/lib/Support/IsNAN.cpp' || echo '$(srcdir)/'`llvm/lib/Support/IsNAN.cpp
+
+tblgen-IsNAN.obj: llvm/lib/Support/IsNAN.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-IsNAN.obj -MD -MP -MF $(DEPDIR)/tblgen-IsNAN.Tpo -c -o tblgen-IsNAN.obj `if test -f 'llvm/lib/Support/IsNAN.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/IsNAN.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/IsNAN.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-IsNAN.Tpo $(DEPDIR)/tblgen-IsNAN.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/IsNAN.cpp' object='tblgen-IsNAN.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-IsNAN.obj `if test -f 'llvm/lib/Support/IsNAN.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/IsNAN.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/IsNAN.cpp'; fi`
+
+tblgen-ManagedStatic.o: llvm/lib/Support/ManagedStatic.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-ManagedStatic.o -MD -MP -MF $(DEPDIR)/tblgen-ManagedStatic.Tpo -c -o tblgen-ManagedStatic.o `test -f 'llvm/lib/Support/ManagedStatic.cpp' || echo '$(srcdir)/'`llvm/lib/Support/ManagedStatic.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-ManagedStatic.Tpo $(DEPDIR)/tblgen-ManagedStatic.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/ManagedStatic.cpp' object='tblgen-ManagedStatic.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-ManagedStatic.o `test -f 'llvm/lib/Support/ManagedStatic.cpp' || echo '$(srcdir)/'`llvm/lib/Support/ManagedStatic.cpp
+
+tblgen-ManagedStatic.obj: llvm/lib/Support/ManagedStatic.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-ManagedStatic.obj -MD -MP -MF $(DEPDIR)/tblgen-ManagedStatic.Tpo -c -o tblgen-ManagedStatic.obj `if test -f 'llvm/lib/Support/ManagedStatic.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/ManagedStatic.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/ManagedStatic.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-ManagedStatic.Tpo $(DEPDIR)/tblgen-ManagedStatic.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/ManagedStatic.cpp' object='tblgen-ManagedStatic.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-ManagedStatic.obj `if test -f 'llvm/lib/Support/ManagedStatic.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/ManagedStatic.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/ManagedStatic.cpp'; fi`
+
+tblgen-MemoryBuffer.o: llvm/lib/Support/MemoryBuffer.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-MemoryBuffer.o -MD -MP -MF $(DEPDIR)/tblgen-MemoryBuffer.Tpo -c -o tblgen-MemoryBuffer.o `test -f 'llvm/lib/Support/MemoryBuffer.cpp' || echo '$(srcdir)/'`llvm/lib/Support/MemoryBuffer.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-MemoryBuffer.Tpo $(DEPDIR)/tblgen-MemoryBuffer.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/MemoryBuffer.cpp' object='tblgen-MemoryBuffer.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-MemoryBuffer.o `test -f 'llvm/lib/Support/MemoryBuffer.cpp' || echo '$(srcdir)/'`llvm/lib/Support/MemoryBuffer.cpp
+
+tblgen-MemoryBuffer.obj: llvm/lib/Support/MemoryBuffer.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-MemoryBuffer.obj -MD -MP -MF $(DEPDIR)/tblgen-MemoryBuffer.Tpo -c -o tblgen-MemoryBuffer.obj `if test -f 'llvm/lib/Support/MemoryBuffer.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/MemoryBuffer.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/MemoryBuffer.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-MemoryBuffer.Tpo $(DEPDIR)/tblgen-MemoryBuffer.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/MemoryBuffer.cpp' object='tblgen-MemoryBuffer.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-MemoryBuffer.obj `if test -f 'llvm/lib/Support/MemoryBuffer.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/MemoryBuffer.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/MemoryBuffer.cpp'; fi`
+
+tblgen-MemoryObject.o: llvm/lib/Support/MemoryObject.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-MemoryObject.o -MD -MP -MF $(DEPDIR)/tblgen-MemoryObject.Tpo -c -o tblgen-MemoryObject.o `test -f 'llvm/lib/Support/MemoryObject.cpp' || echo '$(srcdir)/'`llvm/lib/Support/MemoryObject.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-MemoryObject.Tpo $(DEPDIR)/tblgen-MemoryObject.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/MemoryObject.cpp' object='tblgen-MemoryObject.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-MemoryObject.o `test -f 'llvm/lib/Support/MemoryObject.cpp' || echo '$(srcdir)/'`llvm/lib/Support/MemoryObject.cpp
+
+tblgen-MemoryObject.obj: llvm/lib/Support/MemoryObject.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-MemoryObject.obj -MD -MP -MF $(DEPDIR)/tblgen-MemoryObject.Tpo -c -o tblgen-MemoryObject.obj `if test -f 'llvm/lib/Support/MemoryObject.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/MemoryObject.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/MemoryObject.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-MemoryObject.Tpo $(DEPDIR)/tblgen-MemoryObject.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/MemoryObject.cpp' object='tblgen-MemoryObject.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-MemoryObject.obj `if test -f 'llvm/lib/Support/MemoryObject.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/MemoryObject.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/MemoryObject.cpp'; fi`
+
+tblgen-PluginLoader.o: llvm/lib/Support/PluginLoader.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-PluginLoader.o -MD -MP -MF $(DEPDIR)/tblgen-PluginLoader.Tpo -c -o tblgen-PluginLoader.o `test -f 'llvm/lib/Support/PluginLoader.cpp' || echo '$(srcdir)/'`llvm/lib/Support/PluginLoader.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-PluginLoader.Tpo $(DEPDIR)/tblgen-PluginLoader.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/PluginLoader.cpp' object='tblgen-PluginLoader.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-PluginLoader.o `test -f 'llvm/lib/Support/PluginLoader.cpp' || echo '$(srcdir)/'`llvm/lib/Support/PluginLoader.cpp
+
+tblgen-PluginLoader.obj: llvm/lib/Support/PluginLoader.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-PluginLoader.obj -MD -MP -MF $(DEPDIR)/tblgen-PluginLoader.Tpo -c -o tblgen-PluginLoader.obj `if test -f 'llvm/lib/Support/PluginLoader.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/PluginLoader.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/PluginLoader.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-PluginLoader.Tpo $(DEPDIR)/tblgen-PluginLoader.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/PluginLoader.cpp' object='tblgen-PluginLoader.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-PluginLoader.obj `if test -f 'llvm/lib/Support/PluginLoader.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/PluginLoader.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/PluginLoader.cpp'; fi`
+
+tblgen-PrettyStackTrace.o: llvm/lib/Support/PrettyStackTrace.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-PrettyStackTrace.o -MD -MP -MF $(DEPDIR)/tblgen-PrettyStackTrace.Tpo -c -o tblgen-PrettyStackTrace.o `test -f 'llvm/lib/Support/PrettyStackTrace.cpp' || echo '$(srcdir)/'`llvm/lib/Support/PrettyStackTrace.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-PrettyStackTrace.Tpo $(DEPDIR)/tblgen-PrettyStackTrace.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/PrettyStackTrace.cpp' object='tblgen-PrettyStackTrace.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-PrettyStackTrace.o `test -f 'llvm/lib/Support/PrettyStackTrace.cpp' || echo '$(srcdir)/'`llvm/lib/Support/PrettyStackTrace.cpp
+
+tblgen-PrettyStackTrace.obj: llvm/lib/Support/PrettyStackTrace.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-PrettyStackTrace.obj -MD -MP -MF $(DEPDIR)/tblgen-PrettyStackTrace.Tpo -c -o tblgen-PrettyStackTrace.obj `if test -f 'llvm/lib/Support/PrettyStackTrace.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/PrettyStackTrace.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/PrettyStackTrace.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-PrettyStackTrace.Tpo $(DEPDIR)/tblgen-PrettyStackTrace.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/PrettyStackTrace.cpp' object='tblgen-PrettyStackTrace.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-PrettyStackTrace.obj `if test -f 'llvm/lib/Support/PrettyStackTrace.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/PrettyStackTrace.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/PrettyStackTrace.cpp'; fi`
+
+tblgen-Regex.o: llvm/lib/Support/Regex.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Regex.o -MD -MP -MF $(DEPDIR)/tblgen-Regex.Tpo -c -o tblgen-Regex.o `test -f 'llvm/lib/Support/Regex.cpp' || echo '$(srcdir)/'`llvm/lib/Support/Regex.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Regex.Tpo $(DEPDIR)/tblgen-Regex.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/Regex.cpp' object='tblgen-Regex.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Regex.o `test -f 'llvm/lib/Support/Regex.cpp' || echo '$(srcdir)/'`llvm/lib/Support/Regex.cpp
+
+tblgen-Regex.obj: llvm/lib/Support/Regex.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Regex.obj -MD -MP -MF $(DEPDIR)/tblgen-Regex.Tpo -c -o tblgen-Regex.obj `if test -f 'llvm/lib/Support/Regex.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/Regex.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/Regex.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Regex.Tpo $(DEPDIR)/tblgen-Regex.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/Regex.cpp' object='tblgen-Regex.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Regex.obj `if test -f 'llvm/lib/Support/Regex.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/Regex.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/Regex.cpp'; fi`
+
+tblgen-SlowOperationInformer.o: llvm/lib/Support/SlowOperationInformer.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-SlowOperationInformer.o -MD -MP -MF $(DEPDIR)/tblgen-SlowOperationInformer.Tpo -c -o tblgen-SlowOperationInformer.o `test -f 'llvm/lib/Support/SlowOperationInformer.cpp' || echo '$(srcdir)/'`llvm/lib/Support/SlowOperationInformer.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-SlowOperationInformer.Tpo $(DEPDIR)/tblgen-SlowOperationInformer.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/SlowOperationInformer.cpp' object='tblgen-SlowOperationInformer.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-SlowOperationInformer.o `test -f 'llvm/lib/Support/SlowOperationInformer.cpp' || echo '$(srcdir)/'`llvm/lib/Support/SlowOperationInformer.cpp
+
+tblgen-SlowOperationInformer.obj: llvm/lib/Support/SlowOperationInformer.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-SlowOperationInformer.obj -MD -MP -MF $(DEPDIR)/tblgen-SlowOperationInformer.Tpo -c -o tblgen-SlowOperationInformer.obj `if test -f 'llvm/lib/Support/SlowOperationInformer.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/SlowOperationInformer.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/SlowOperationInformer.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-SlowOperationInformer.Tpo $(DEPDIR)/tblgen-SlowOperationInformer.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/SlowOperationInformer.cpp' object='tblgen-SlowOperationInformer.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-SlowOperationInformer.obj `if test -f 'llvm/lib/Support/SlowOperationInformer.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/SlowOperationInformer.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/SlowOperationInformer.cpp'; fi`
+
+tblgen-SmallPtrSet.o: llvm/lib/Support/SmallPtrSet.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-SmallPtrSet.o -MD -MP -MF $(DEPDIR)/tblgen-SmallPtrSet.Tpo -c -o tblgen-SmallPtrSet.o `test -f 'llvm/lib/Support/SmallPtrSet.cpp' || echo '$(srcdir)/'`llvm/lib/Support/SmallPtrSet.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-SmallPtrSet.Tpo $(DEPDIR)/tblgen-SmallPtrSet.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/SmallPtrSet.cpp' object='tblgen-SmallPtrSet.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-SmallPtrSet.o `test -f 'llvm/lib/Support/SmallPtrSet.cpp' || echo '$(srcdir)/'`llvm/lib/Support/SmallPtrSet.cpp
+
+tblgen-SmallPtrSet.obj: llvm/lib/Support/SmallPtrSet.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-SmallPtrSet.obj -MD -MP -MF $(DEPDIR)/tblgen-SmallPtrSet.Tpo -c -o tblgen-SmallPtrSet.obj `if test -f 'llvm/lib/Support/SmallPtrSet.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/SmallPtrSet.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/SmallPtrSet.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-SmallPtrSet.Tpo $(DEPDIR)/tblgen-SmallPtrSet.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/SmallPtrSet.cpp' object='tblgen-SmallPtrSet.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-SmallPtrSet.obj `if test -f 'llvm/lib/Support/SmallPtrSet.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/SmallPtrSet.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/SmallPtrSet.cpp'; fi`
+
+tblgen-SmallVector.o: llvm/lib/Support/SmallVector.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-SmallVector.o -MD -MP -MF $(DEPDIR)/tblgen-SmallVector.Tpo -c -o tblgen-SmallVector.o `test -f 'llvm/lib/Support/SmallVector.cpp' || echo '$(srcdir)/'`llvm/lib/Support/SmallVector.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-SmallVector.Tpo $(DEPDIR)/tblgen-SmallVector.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/SmallVector.cpp' object='tblgen-SmallVector.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-SmallVector.o `test -f 'llvm/lib/Support/SmallVector.cpp' || echo '$(srcdir)/'`llvm/lib/Support/SmallVector.cpp
+
+tblgen-SmallVector.obj: llvm/lib/Support/SmallVector.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-SmallVector.obj -MD -MP -MF $(DEPDIR)/tblgen-SmallVector.Tpo -c -o tblgen-SmallVector.obj `if test -f 'llvm/lib/Support/SmallVector.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/SmallVector.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/SmallVector.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-SmallVector.Tpo $(DEPDIR)/tblgen-SmallVector.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/SmallVector.cpp' object='tblgen-SmallVector.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-SmallVector.obj `if test -f 'llvm/lib/Support/SmallVector.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/SmallVector.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/SmallVector.cpp'; fi`
+
+tblgen-SourceMgr.o: llvm/lib/Support/SourceMgr.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-SourceMgr.o -MD -MP -MF $(DEPDIR)/tblgen-SourceMgr.Tpo -c -o tblgen-SourceMgr.o `test -f 'llvm/lib/Support/SourceMgr.cpp' || echo '$(srcdir)/'`llvm/lib/Support/SourceMgr.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-SourceMgr.Tpo $(DEPDIR)/tblgen-SourceMgr.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/SourceMgr.cpp' object='tblgen-SourceMgr.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-SourceMgr.o `test -f 'llvm/lib/Support/SourceMgr.cpp' || echo '$(srcdir)/'`llvm/lib/Support/SourceMgr.cpp
+
+tblgen-SourceMgr.obj: llvm/lib/Support/SourceMgr.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-SourceMgr.obj -MD -MP -MF $(DEPDIR)/tblgen-SourceMgr.Tpo -c -o tblgen-SourceMgr.obj `if test -f 'llvm/lib/Support/SourceMgr.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/SourceMgr.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/SourceMgr.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-SourceMgr.Tpo $(DEPDIR)/tblgen-SourceMgr.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/SourceMgr.cpp' object='tblgen-SourceMgr.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-SourceMgr.obj `if test -f 'llvm/lib/Support/SourceMgr.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/SourceMgr.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/SourceMgr.cpp'; fi`
+
+tblgen-Statistic.o: llvm/lib/Support/Statistic.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Statistic.o -MD -MP -MF $(DEPDIR)/tblgen-Statistic.Tpo -c -o tblgen-Statistic.o `test -f 'llvm/lib/Support/Statistic.cpp' || echo '$(srcdir)/'`llvm/lib/Support/Statistic.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Statistic.Tpo $(DEPDIR)/tblgen-Statistic.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/Statistic.cpp' object='tblgen-Statistic.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Statistic.o `test -f 'llvm/lib/Support/Statistic.cpp' || echo '$(srcdir)/'`llvm/lib/Support/Statistic.cpp
+
+tblgen-Statistic.obj: llvm/lib/Support/Statistic.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Statistic.obj -MD -MP -MF $(DEPDIR)/tblgen-Statistic.Tpo -c -o tblgen-Statistic.obj `if test -f 'llvm/lib/Support/Statistic.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/Statistic.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/Statistic.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Statistic.Tpo $(DEPDIR)/tblgen-Statistic.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/Statistic.cpp' object='tblgen-Statistic.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Statistic.obj `if test -f 'llvm/lib/Support/Statistic.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/Statistic.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/Statistic.cpp'; fi`
+
+tblgen-StringExtras.o: llvm/lib/Support/StringExtras.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-StringExtras.o -MD -MP -MF $(DEPDIR)/tblgen-StringExtras.Tpo -c -o tblgen-StringExtras.o `test -f 'llvm/lib/Support/StringExtras.cpp' || echo '$(srcdir)/'`llvm/lib/Support/StringExtras.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-StringExtras.Tpo $(DEPDIR)/tblgen-StringExtras.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/StringExtras.cpp' object='tblgen-StringExtras.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-StringExtras.o `test -f 'llvm/lib/Support/StringExtras.cpp' || echo '$(srcdir)/'`llvm/lib/Support/StringExtras.cpp
+
+tblgen-StringExtras.obj: llvm/lib/Support/StringExtras.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-StringExtras.obj -MD -MP -MF $(DEPDIR)/tblgen-StringExtras.Tpo -c -o tblgen-StringExtras.obj `if test -f 'llvm/lib/Support/StringExtras.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/StringExtras.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/StringExtras.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-StringExtras.Tpo $(DEPDIR)/tblgen-StringExtras.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/StringExtras.cpp' object='tblgen-StringExtras.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-StringExtras.obj `if test -f 'llvm/lib/Support/StringExtras.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/StringExtras.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/StringExtras.cpp'; fi`
+
+tblgen-StringMap.o: llvm/lib/Support/StringMap.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-StringMap.o -MD -MP -MF $(DEPDIR)/tblgen-StringMap.Tpo -c -o tblgen-StringMap.o `test -f 'llvm/lib/Support/StringMap.cpp' || echo '$(srcdir)/'`llvm/lib/Support/StringMap.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-StringMap.Tpo $(DEPDIR)/tblgen-StringMap.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/StringMap.cpp' object='tblgen-StringMap.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-StringMap.o `test -f 'llvm/lib/Support/StringMap.cpp' || echo '$(srcdir)/'`llvm/lib/Support/StringMap.cpp
+
+tblgen-StringMap.obj: llvm/lib/Support/StringMap.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-StringMap.obj -MD -MP -MF $(DEPDIR)/tblgen-StringMap.Tpo -c -o tblgen-StringMap.obj `if test -f 'llvm/lib/Support/StringMap.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/StringMap.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/StringMap.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-StringMap.Tpo $(DEPDIR)/tblgen-StringMap.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/StringMap.cpp' object='tblgen-StringMap.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-StringMap.obj `if test -f 'llvm/lib/Support/StringMap.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/StringMap.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/StringMap.cpp'; fi`
+
+tblgen-StringPool.o: llvm/lib/Support/StringPool.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-StringPool.o -MD -MP -MF $(DEPDIR)/tblgen-StringPool.Tpo -c -o tblgen-StringPool.o `test -f 'llvm/lib/Support/StringPool.cpp' || echo '$(srcdir)/'`llvm/lib/Support/StringPool.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-StringPool.Tpo $(DEPDIR)/tblgen-StringPool.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/StringPool.cpp' object='tblgen-StringPool.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-StringPool.o `test -f 'llvm/lib/Support/StringPool.cpp' || echo '$(srcdir)/'`llvm/lib/Support/StringPool.cpp
+
+tblgen-StringPool.obj: llvm/lib/Support/StringPool.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-StringPool.obj -MD -MP -MF $(DEPDIR)/tblgen-StringPool.Tpo -c -o tblgen-StringPool.obj `if test -f 'llvm/lib/Support/StringPool.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/StringPool.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/StringPool.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-StringPool.Tpo $(DEPDIR)/tblgen-StringPool.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/StringPool.cpp' object='tblgen-StringPool.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-StringPool.obj `if test -f 'llvm/lib/Support/StringPool.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/StringPool.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/StringPool.cpp'; fi`
+
+tblgen-StringRef.o: llvm/lib/Support/StringRef.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-StringRef.o -MD -MP -MF $(DEPDIR)/tblgen-StringRef.Tpo -c -o tblgen-StringRef.o `test -f 'llvm/lib/Support/StringRef.cpp' || echo '$(srcdir)/'`llvm/lib/Support/StringRef.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-StringRef.Tpo $(DEPDIR)/tblgen-StringRef.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/StringRef.cpp' object='tblgen-StringRef.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-StringRef.o `test -f 'llvm/lib/Support/StringRef.cpp' || echo '$(srcdir)/'`llvm/lib/Support/StringRef.cpp
+
+tblgen-StringRef.obj: llvm/lib/Support/StringRef.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-StringRef.obj -MD -MP -MF $(DEPDIR)/tblgen-StringRef.Tpo -c -o tblgen-StringRef.obj `if test -f 'llvm/lib/Support/StringRef.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/StringRef.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/StringRef.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-StringRef.Tpo $(DEPDIR)/tblgen-StringRef.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/StringRef.cpp' object='tblgen-StringRef.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-StringRef.obj `if test -f 'llvm/lib/Support/StringRef.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/StringRef.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/StringRef.cpp'; fi`
+
+tblgen-SystemUtils.o: llvm/lib/Support/SystemUtils.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-SystemUtils.o -MD -MP -MF $(DEPDIR)/tblgen-SystemUtils.Tpo -c -o tblgen-SystemUtils.o `test -f 'llvm/lib/Support/SystemUtils.cpp' || echo '$(srcdir)/'`llvm/lib/Support/SystemUtils.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-SystemUtils.Tpo $(DEPDIR)/tblgen-SystemUtils.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/SystemUtils.cpp' object='tblgen-SystemUtils.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-SystemUtils.o `test -f 'llvm/lib/Support/SystemUtils.cpp' || echo '$(srcdir)/'`llvm/lib/Support/SystemUtils.cpp
+
+tblgen-SystemUtils.obj: llvm/lib/Support/SystemUtils.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-SystemUtils.obj -MD -MP -MF $(DEPDIR)/tblgen-SystemUtils.Tpo -c -o tblgen-SystemUtils.obj `if test -f 'llvm/lib/Support/SystemUtils.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/SystemUtils.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/SystemUtils.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-SystemUtils.Tpo $(DEPDIR)/tblgen-SystemUtils.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/SystemUtils.cpp' object='tblgen-SystemUtils.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-SystemUtils.obj `if test -f 'llvm/lib/Support/SystemUtils.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/SystemUtils.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/SystemUtils.cpp'; fi`
+
+tblgen-TargetRegistry.o: llvm/lib/Support/TargetRegistry.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-TargetRegistry.o -MD -MP -MF $(DEPDIR)/tblgen-TargetRegistry.Tpo -c -o tblgen-TargetRegistry.o `test -f 'llvm/lib/Support/TargetRegistry.cpp' || echo '$(srcdir)/'`llvm/lib/Support/TargetRegistry.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-TargetRegistry.Tpo $(DEPDIR)/tblgen-TargetRegistry.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/TargetRegistry.cpp' object='tblgen-TargetRegistry.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-TargetRegistry.o `test -f 'llvm/lib/Support/TargetRegistry.cpp' || echo '$(srcdir)/'`llvm/lib/Support/TargetRegistry.cpp
+
+tblgen-TargetRegistry.obj: llvm/lib/Support/TargetRegistry.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-TargetRegistry.obj -MD -MP -MF $(DEPDIR)/tblgen-TargetRegistry.Tpo -c -o tblgen-TargetRegistry.obj `if test -f 'llvm/lib/Support/TargetRegistry.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/TargetRegistry.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/TargetRegistry.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-TargetRegistry.Tpo $(DEPDIR)/tblgen-TargetRegistry.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/TargetRegistry.cpp' object='tblgen-TargetRegistry.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-TargetRegistry.obj `if test -f 'llvm/lib/Support/TargetRegistry.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/TargetRegistry.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/TargetRegistry.cpp'; fi`
+
+tblgen-Timer.o: llvm/lib/Support/Timer.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Timer.o -MD -MP -MF $(DEPDIR)/tblgen-Timer.Tpo -c -o tblgen-Timer.o `test -f 'llvm/lib/Support/Timer.cpp' || echo '$(srcdir)/'`llvm/lib/Support/Timer.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Timer.Tpo $(DEPDIR)/tblgen-Timer.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/Timer.cpp' object='tblgen-Timer.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Timer.o `test -f 'llvm/lib/Support/Timer.cpp' || echo '$(srcdir)/'`llvm/lib/Support/Timer.cpp
+
+tblgen-Timer.obj: llvm/lib/Support/Timer.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Timer.obj -MD -MP -MF $(DEPDIR)/tblgen-Timer.Tpo -c -o tblgen-Timer.obj `if test -f 'llvm/lib/Support/Timer.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/Timer.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/Timer.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Timer.Tpo $(DEPDIR)/tblgen-Timer.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/Timer.cpp' object='tblgen-Timer.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Timer.obj `if test -f 'llvm/lib/Support/Timer.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/Timer.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/Timer.cpp'; fi`
+
+tblgen-Triple.o: llvm/lib/Support/Triple.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Triple.o -MD -MP -MF $(DEPDIR)/tblgen-Triple.Tpo -c -o tblgen-Triple.o `test -f 'llvm/lib/Support/Triple.cpp' || echo '$(srcdir)/'`llvm/lib/Support/Triple.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Triple.Tpo $(DEPDIR)/tblgen-Triple.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/Triple.cpp' object='tblgen-Triple.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Triple.o `test -f 'llvm/lib/Support/Triple.cpp' || echo '$(srcdir)/'`llvm/lib/Support/Triple.cpp
+
+tblgen-Triple.obj: llvm/lib/Support/Triple.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Triple.obj -MD -MP -MF $(DEPDIR)/tblgen-Triple.Tpo -c -o tblgen-Triple.obj `if test -f 'llvm/lib/Support/Triple.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/Triple.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/Triple.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Triple.Tpo $(DEPDIR)/tblgen-Triple.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/Triple.cpp' object='tblgen-Triple.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Triple.obj `if test -f 'llvm/lib/Support/Triple.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/Triple.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/Triple.cpp'; fi`
+
+tblgen-Twine.o: llvm/lib/Support/Twine.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Twine.o -MD -MP -MF $(DEPDIR)/tblgen-Twine.Tpo -c -o tblgen-Twine.o `test -f 'llvm/lib/Support/Twine.cpp' || echo '$(srcdir)/'`llvm/lib/Support/Twine.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Twine.Tpo $(DEPDIR)/tblgen-Twine.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/Twine.cpp' object='tblgen-Twine.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Twine.o `test -f 'llvm/lib/Support/Twine.cpp' || echo '$(srcdir)/'`llvm/lib/Support/Twine.cpp
+
+tblgen-Twine.obj: llvm/lib/Support/Twine.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-Twine.obj -MD -MP -MF $(DEPDIR)/tblgen-Twine.Tpo -c -o tblgen-Twine.obj `if test -f 'llvm/lib/Support/Twine.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/Twine.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/Twine.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-Twine.Tpo $(DEPDIR)/tblgen-Twine.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/Twine.cpp' object='tblgen-Twine.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-Twine.obj `if test -f 'llvm/lib/Support/Twine.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/Twine.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/Twine.cpp'; fi`
+
+tblgen-circular_raw_ostream.o: llvm/lib/Support/circular_raw_ostream.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-circular_raw_ostream.o -MD -MP -MF $(DEPDIR)/tblgen-circular_raw_ostream.Tpo -c -o tblgen-circular_raw_ostream.o `test -f 'llvm/lib/Support/circular_raw_ostream.cpp' || echo '$(srcdir)/'`llvm/lib/Support/circular_raw_ostream.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-circular_raw_ostream.Tpo $(DEPDIR)/tblgen-circular_raw_ostream.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/circular_raw_ostream.cpp' object='tblgen-circular_raw_ostream.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-circular_raw_ostream.o `test -f 'llvm/lib/Support/circular_raw_ostream.cpp' || echo '$(srcdir)/'`llvm/lib/Support/circular_raw_ostream.cpp
+
+tblgen-circular_raw_ostream.obj: llvm/lib/Support/circular_raw_ostream.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-circular_raw_ostream.obj -MD -MP -MF $(DEPDIR)/tblgen-circular_raw_ostream.Tpo -c -o tblgen-circular_raw_ostream.obj `if test -f 'llvm/lib/Support/circular_raw_ostream.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/circular_raw_ostream.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/circular_raw_ostream.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-circular_raw_ostream.Tpo $(DEPDIR)/tblgen-circular_raw_ostream.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/circular_raw_ostream.cpp' object='tblgen-circular_raw_ostream.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-circular_raw_ostream.obj `if test -f 'llvm/lib/Support/circular_raw_ostream.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/circular_raw_ostream.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/circular_raw_ostream.cpp'; fi`
+
+tblgen-raw_os_ostream.o: llvm/lib/Support/raw_os_ostream.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-raw_os_ostream.o -MD -MP -MF $(DEPDIR)/tblgen-raw_os_ostream.Tpo -c -o tblgen-raw_os_ostream.o `test -f 'llvm/lib/Support/raw_os_ostream.cpp' || echo '$(srcdir)/'`llvm/lib/Support/raw_os_ostream.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-raw_os_ostream.Tpo $(DEPDIR)/tblgen-raw_os_ostream.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/raw_os_ostream.cpp' object='tblgen-raw_os_ostream.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-raw_os_ostream.o `test -f 'llvm/lib/Support/raw_os_ostream.cpp' || echo '$(srcdir)/'`llvm/lib/Support/raw_os_ostream.cpp
+
+tblgen-raw_os_ostream.obj: llvm/lib/Support/raw_os_ostream.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-raw_os_ostream.obj -MD -MP -MF $(DEPDIR)/tblgen-raw_os_ostream.Tpo -c -o tblgen-raw_os_ostream.obj `if test -f 'llvm/lib/Support/raw_os_ostream.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/raw_os_ostream.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/raw_os_ostream.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-raw_os_ostream.Tpo $(DEPDIR)/tblgen-raw_os_ostream.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/raw_os_ostream.cpp' object='tblgen-raw_os_ostream.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-raw_os_ostream.obj `if test -f 'llvm/lib/Support/raw_os_ostream.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/raw_os_ostream.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/raw_os_ostream.cpp'; fi`
+
+tblgen-raw_ostream.o: llvm/lib/Support/raw_ostream.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-raw_ostream.o -MD -MP -MF $(DEPDIR)/tblgen-raw_ostream.Tpo -c -o tblgen-raw_ostream.o `test -f 'llvm/lib/Support/raw_ostream.cpp' || echo '$(srcdir)/'`llvm/lib/Support/raw_ostream.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-raw_ostream.Tpo $(DEPDIR)/tblgen-raw_ostream.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/raw_ostream.cpp' object='tblgen-raw_ostream.o' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-raw_ostream.o `test -f 'llvm/lib/Support/raw_ostream.cpp' || echo '$(srcdir)/'`llvm/lib/Support/raw_ostream.cpp
+
+tblgen-raw_ostream.obj: llvm/lib/Support/raw_ostream.cpp
+ at am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-raw_ostream.obj -MD -MP -MF $(DEPDIR)/tblgen-raw_ostream.Tpo -c -o tblgen-raw_ostream.obj `if test -f 'llvm/lib/Support/raw_ostream.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/raw_ostream.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/raw_ostream.cpp'; fi`
+ at am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-raw_ostream.Tpo $(DEPDIR)/tblgen-raw_ostream.Po
+ at am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Support/raw_ostream.cpp' object='tblgen-raw_ostream.obj' libtool=no @AMDEPBACKSLASH@
+ at AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+ at am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-raw_ostream.obj `if test -f 'llvm/lib/Support/raw_ostream.cpp'; then $(CYGPATH_W) 'llvm/lib/Support/raw_ostream.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/lib/Support/raw_ostream.cpp'; fi`
+
.cpp.o:
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXXCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
diff --git a/libclamav/c++/PPCGenAsmWriter.inc b/libclamav/c++/PPCGenAsmWriter.inc
index c3c2d2d..6cc8ccf 100644
--- a/libclamav/c++/PPCGenAsmWriter.inc
+++ b/libclamav/c++/PPCGenAsmWriter.inc
@@ -21,574 +21,575 @@ void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
0U, // IMPLICIT_DEF
0U, // SUBREG_TO_REG
0U, // COPY_TO_REGCLASS
- 1U, // ADD4
- 6U, // ADD8
- 11U, // ADDC
- 11U, // ADDC8
- 17U, // ADDE
- 17U, // ADDE8
- 4119U, // ADDI
- 4119U, // ADDI8
- 4125U, // ADDIC
- 4125U, // ADDIC8
- 4132U, // ADDICo
- 8236U, // ADDIS
- 8236U, // ADDIS8
- 32819U, // ADDME
- 32819U, // ADDME8
- 32826U, // ADDZE
- 32826U, // ADDZE8
- 272629825U, // ADJCALLSTACKDOWN
- 276824129U, // ADJCALLSTACKUP
- 66U, // AND
- 66U, // AND8
- 71U, // ANDC
- 71U, // ANDC8
- 12365U, // ANDISo
- 12365U, // ANDISo8
- 12373U, // ANDIo
- 12373U, // ANDIo8
- 281018433U, // ATOMIC_CMP_SWAP_I16
- 285212737U, // ATOMIC_CMP_SWAP_I32
- 289407041U, // ATOMIC_CMP_SWAP_I64
- 293601345U, // ATOMIC_CMP_SWAP_I8
- 297795649U, // ATOMIC_LOAD_ADD_I16
- 301989953U, // ATOMIC_LOAD_ADD_I32
- 306184257U, // ATOMIC_LOAD_ADD_I64
- 310378561U, // ATOMIC_LOAD_ADD_I8
- 314572865U, // ATOMIC_LOAD_AND_I16
- 318767169U, // ATOMIC_LOAD_AND_I32
- 322961473U, // ATOMIC_LOAD_AND_I64
- 327155777U, // ATOMIC_LOAD_AND_I8
- 331350081U, // ATOMIC_LOAD_NAND_I16
- 335544385U, // ATOMIC_LOAD_NAND_I32
- 339738689U, // ATOMIC_LOAD_NAND_I64
- 343932993U, // ATOMIC_LOAD_NAND_I8
- 348127297U, // ATOMIC_LOAD_OR_I16
- 352321601U, // ATOMIC_LOAD_OR_I32
- 356515905U, // ATOMIC_LOAD_OR_I64
- 360710209U, // ATOMIC_LOAD_OR_I8
- 364904513U, // ATOMIC_LOAD_SUB_I16
- 369098817U, // ATOMIC_LOAD_SUB_I32
- 373293121U, // ATOMIC_LOAD_SUB_I64
- 377487425U, // ATOMIC_LOAD_SUB_I8
- 381681729U, // ATOMIC_LOAD_XOR_I16
- 385876033U, // ATOMIC_LOAD_XOR_I32
- 390070337U, // ATOMIC_LOAD_XOR_I64
- 394264641U, // ATOMIC_LOAD_XOR_I8
- 398458945U, // ATOMIC_SWAP_I16
- 402653249U, // ATOMIC_SWAP_I32
- 406847553U, // ATOMIC_SWAP_I64
- 411041857U, // ATOMIC_SWAP_I8
- 536871004U, // B
- 952369247U, // BCC
- 1073741921U, // BCTR
- 1073741926U, // BCTRL8_Darwin
- 1073741926U, // BCTRL8_ELF
- 1073741926U, // BCTRL_Darwin
- 1073741926U, // BCTRL_SVR4
- 1493172332U, // BL8_Darwin
- 1493172332U, // BL8_ELF
- 1761607792U, // BLA8_Darwin
- 1761607792U, // BLA8_ELF
- 1761607792U, // BLA_Darwin
- 1761607792U, // BLA_SVR4
- 960495711U, // BLR
- 1493172332U, // BL_Darwin
- 1493172332U, // BL_SVR4
- 117U, // CMPD
- 4219U, // CMPDI
- 130U, // CMPLD
- 12425U, // CMPLDI
- 145U, // CMPLW
- 12440U, // CMPLWI
- 160U, // CMPW
- 4262U, // CMPWI
- 32941U, // CNTLZD
- 32949U, // CNTLZW
- 189U, // CREQV
- 196U, // CROR
- 524477U, // CRSET
- 1879048394U, // DCBA
- 1879048400U, // DCBF
- 1879048406U, // DCBI
- 1879048412U, // DCBST
- 1879048419U, // DCBT
- 1879048425U, // DCBTST
- 1879048433U, // DCBZ
- 1879048439U, // DCBZL
- 254U, // DIVD
- 260U, // DIVDU
- 267U, // DIVW
- 273U, // DIVWU
- 2147483928U, // DSS
- 1073742109U, // DSSALL
- 2415919396U, // DST
- 2415919396U, // DST64
- 2415919401U, // DSTST
- 2415919401U, // DSTST64
- 2415919408U, // DSTSTT
- 2415919408U, // DSTSTT64
- 2415919416U, // DSTT
- 2415919416U, // DSTT64
- 427819073U, // DYNALLOC
- 432013377U, // DYNALLOC8
- 318U, // EQV
- 318U, // EQV8
- 33091U, // EXTSB
- 33091U, // EXTSB8
- 33098U, // EXTSH
- 33098U, // EXTSH8
- 33105U, // EXTSW
- 33105U, // EXTSW_32
- 33105U, // EXTSW_32_64
- 33112U, // FABSD
- 33112U, // FABSS
- 350U, // FADD
- 356U, // FADDS
- 350U, // FADDrtz
- 33131U, // FCFID
- 370U, // FCMPUD
- 370U, // FCMPUS
- 33145U, // FCTIDZ
- 33153U, // FCTIWZ
- 393U, // FDIV
- 399U, // FDIVS
- 406U, // FMADD
- 413U, // FMADDS
- 33189U, // FMRD
- 33189U, // FMRS
- 33189U, // FMRSD
- 426U, // FMSUB
- 433U, // FMSUBS
- 441U, // FMUL
- 447U, // FMULS
- 33222U, // FNABSD
- 33222U, // FNABSS
- 33229U, // FNEGD
- 33229U, // FNEGS
- 467U, // FNMADD
- 475U, // FNMADDS
- 484U, // FNMSUB
- 492U, // FNMSUBS
- 33269U, // FRSP
- 507U, // FSELD
- 507U, // FSELS
- 33281U, // FSQRT
- 33288U, // FSQRTS
- 528U, // FSUB
- 534U, // FSUBS
- 852509U, // LA
- 1049121U, // LBZ
- 1049121U, // LBZ8
- 1311270U, // LBZU
- 1311270U, // LBZU8
- 1573420U, // LBZX
- 1573420U, // LBZX8
- 1835570U, // LD
- 1573430U, // LDARX
- 2097725U, // LDU
- 1573442U, // LDX
- 167772743U, // LDinto_toc
- 2359858U, // LDtoc
- 1073742416U, // LDtoc_restore
- 1049180U, // LFD
- 1311324U, // LFDU
- 1573473U, // LFDX
- 1049191U, // LFS
- 1311335U, // LFSU
- 1573484U, // LFSX
- 1049202U, // LHA
- 1049202U, // LHA8
- 1311351U, // LHAU
- 885367U, // LHAU8
- 1573501U, // LHAX
- 1573501U, // LHAX8
- 1573507U, // LHBRX
- 1049226U, // LHZ
- 1049226U, // LHZ8
- 1311375U, // LHZU
- 1311375U, // LHZU8
- 1573525U, // LHZX
- 1573525U, // LHZX8
- 2622107U, // LI
- 2622107U, // LI8
- 2884255U, // LIS
- 2884255U, // LIS8
- 1573540U, // LVEBX
- 1573547U, // LVEHX
- 1573554U, // LVEWX
- 1573561U, // LVSL
- 1573567U, // LVSR
- 1573573U, // LVX
- 1573578U, // LVXL
- 1835728U, // LWA
- 1573589U, // LWARX
- 1573596U, // LWAX
- 1573602U, // LWBRX
- 1049321U, // LWZ
- 1049321U, // LWZ8
- 1311470U, // LWZU
- 1311470U, // LWZU8
- 1573620U, // LWZX
- 1573620U, // LWZX8
- 33530U, // MCRF
- 150995712U, // MFCR
- 150995718U, // MFCTR
- 150995718U, // MFCTR8
- 150995725U, // MFFS
- 150995731U, // MFLR
- 150995731U, // MFLR8
- 3146496U, // MFOCRF
- 171967257U, // MFVRSAVE
- 150995744U, // MFVSCR
- 2684355368U, // MTCRF
- 150995759U, // MTCTR
- 150995759U, // MTCTR8
- 2952790838U, // MTFSB0
- 2952790846U, // MTFSB1
- 3397387078U, // MTFSF
- 150995789U, // MTLR
- 150995789U, // MTLR8
- 150995795U, // MTVRSAVE
- 150995807U, // MTVSCR
- 871U, // MULHD
- 878U, // MULHDU
- 886U, // MULHW
- 893U, // MULHWU
- 901U, // MULLD
- 5004U, // MULLI
- 915U, // MULLW
- 3489661036U, // MovePCtoLR
- 3489661036U, // MovePCtoLR8
- 922U, // NAND
- 922U, // NAND8
- 33696U, // NEG
- 33696U, // NEG8
- 1073742757U, // NOP
- 937U, // NOR
- 937U, // NOR8
- 942U, // OR
- 942U, // OR4To8
- 942U, // OR8
- 942U, // OR8To4
- 946U, // ORC
- 946U, // ORC8
- 13239U, // ORI
- 13239U, // ORI8
- 13244U, // ORIS
- 13244U, // ORIS8
- 962U, // RLDCL
- 17353U, // RLDICL
- 17361U, // RLDICR
- 3539929U, // RLDIMI
- 3572705U, // RLWIMI
- 21481U, // RLWINM
- 21489U, // RLWINMo
- 1018U, // RLWNM
- 448790593U, // SELECT_CC_F4
- 448790593U, // SELECT_CC_F8
- 448790593U, // SELECT_CC_I4
- 448790593U, // SELECT_CC_I8
- 448790593U, // SELECT_CC_VRRC
- 1025U, // SLD
- 1030U, // SLW
- 452984897U, // SPILL_CR
- 1035U, // SRAD
- 17425U, // SRADI
- 1048U, // SRAW
- 21534U, // SRAWI
- 1061U, // SRD
- 1066U, // SRW
- 1049647U, // STB
- 1049647U, // STB8
- 3409970228U, // STBU
- 3409970228U, // STBU8
- 1573946U, // STBX
- 1573946U, // STBX8
- 1836096U, // STD
- 1573957U, // STDCX
- 3414164557U, // STDU
- 1573971U, // STDUX
- 1573978U, // STDX
- 1573978U, // STDX_32
- 1836096U, // STD_32
- 1049696U, // STFD
- 3409970278U, // STFDU
- 1573997U, // STFDX
- 1574004U, // STFIWX
- 1049724U, // STFS
- 3409970306U, // STFSU
- 1574025U, // STFSX
- 1049744U, // STH
- 1049744U, // STH8
- 1574037U, // STHBRX
- 3409970333U, // STHU
- 3409970333U, // STHU8
- 1574051U, // STHX
- 1574051U, // STHX8
- 1574057U, // STVEBX
- 1574065U, // STVEHX
- 1574073U, // STVEWX
- 1574081U, // STVX
- 1574087U, // STVXL
- 1049806U, // STW
- 1049806U, // STW8
- 1574099U, // STWBRX
- 1574107U, // STWCX
- 3409970403U, // STWU
- 3409970403U, // STWU8
- 1257U, // STWUX
- 1574128U, // STWX
- 1574128U, // STWX8
- 1270U, // SUBF
- 1270U, // SUBF8
- 1276U, // SUBFC
- 1276U, // SUBFC8
- 1283U, // SUBFE
- 1283U, // SUBFE8
- 5386U, // SUBFIC
- 5386U, // SUBFIC8
- 34066U, // SUBFME
- 34066U, // SUBFME8
- 34074U, // SUBFZE
- 34074U, // SUBFZE8
- 1073743138U, // SYNC
- 1493172316U, // TAILB
- 1493172316U, // TAILB8
- 1761608999U, // TAILBA
- 1761608999U, // TAILBA8
- 1073741921U, // TAILBCTR
- 1073741921U, // TAILBCTR8
- 1757447467U, // TCRETURNai
- 1757447480U, // TCRETURNai8
- 1489012038U, // TCRETURNdi
- 1489012051U, // TCRETURNdi8
- 146834785U, // TCRETURNri
- 146834798U, // TCRETURNri8
- 1073743228U, // TRAP
- 34177U, // UPDATE_VRSAVE
- 1424U, // VADDCUW
- 1433U, // VADDFP
- 1441U, // VADDSBS
- 1450U, // VADDSHS
- 1459U, // VADDSWS
- 1468U, // VADDUBM
- 1477U, // VADDUBS
- 1486U, // VADDUHM
- 1495U, // VADDUHS
- 1504U, // VADDUWM
- 1513U, // VADDUWS
- 1522U, // VAND
- 1528U, // VANDC
- 1535U, // VAVGSB
- 1543U, // VAVGSH
- 1551U, // VAVGSW
- 1559U, // VAVGUB
- 1567U, // VAVGUH
- 1575U, // VAVGUW
- 3606063U, // VCFSX
- 3606070U, // VCFUX
- 1597U, // VCMPBFP
- 1606U, // VCMPBFPo
- 1616U, // VCMPEQFP
- 1626U, // VCMPEQFPo
- 1637U, // VCMPEQUB
- 1647U, // VCMPEQUBo
- 1658U, // VCMPEQUH
- 1668U, // VCMPEQUHo
- 1679U, // VCMPEQUW
- 1689U, // VCMPEQUWo
- 1700U, // VCMPGEFP
- 1710U, // VCMPGEFPo
- 1721U, // VCMPGTFP
- 1731U, // VCMPGTFPo
- 1742U, // VCMPGTSB
- 1752U, // VCMPGTSBo
- 1763U, // VCMPGTSH
- 1773U, // VCMPGTSHo
- 1784U, // VCMPGTSW
- 1794U, // VCMPGTSWo
- 1805U, // VCMPGTUB
- 1815U, // VCMPGTUBo
- 1826U, // VCMPGTUH
- 1836U, // VCMPGTUHo
- 1847U, // VCMPGTUW
- 1857U, // VCMPGTUWo
- 3606348U, // VCTSXS
- 3606356U, // VCTUXS
- 34652U, // VEXPTEFP
- 34662U, // VLOGEFP
- 1903U, // VMADDFP
- 1912U, // VMAXFP
- 1920U, // VMAXSB
- 1928U, // VMAXSH
- 1936U, // VMAXSW
- 1944U, // VMAXUB
- 1952U, // VMAXUH
- 1960U, // VMAXUW
- 1968U, // VMHADDSHS
- 1979U, // VMHRADDSHS
- 1991U, // VMINFP
- 1999U, // VMINSB
- 2007U, // VMINSH
- 2015U, // VMINSW
- 2023U, // VMINUB
- 2031U, // VMINUH
- 2039U, // VMINUW
- 2047U, // VMLADDUHM
- 2058U, // VMRGHB
- 2066U, // VMRGHH
- 2074U, // VMRGHW
- 2082U, // VMRGLB
- 2090U, // VMRGLH
- 2098U, // VMRGLW
- 2106U, // VMSUMMBM
- 2116U, // VMSUMSHM
- 2126U, // VMSUMSHS
- 2136U, // VMSUMUBM
- 2146U, // VMSUMUHM
- 2156U, // VMSUMUHS
- 2166U, // VMULESB
- 2175U, // VMULESH
- 2184U, // VMULEUB
- 2193U, // VMULEUH
- 2202U, // VMULOSB
- 2211U, // VMULOSH
- 2220U, // VMULOUB
- 2229U, // VMULOUH
- 2238U, // VNMSUBFP
- 2248U, // VNOR
- 2254U, // VOR
- 2259U, // VPERM
- 2266U, // VPKPX
- 2273U, // VPKSHSS
- 2282U, // VPKSHUS
- 2291U, // VPKSWSS
- 2300U, // VPKSWUS
- 2309U, // VPKUHUM
- 2318U, // VPKUHUS
- 2327U, // VPKUWUM
- 2336U, // VPKUWUS
- 35113U, // VREFP
- 35120U, // VRFIM
- 35127U, // VRFIN
- 35134U, // VRFIP
- 35141U, // VRFIZ
- 2380U, // VRLB
- 2386U, // VRLH
- 2392U, // VRLW
- 35166U, // VRSQRTEFP
- 2409U, // VSEL
- 2415U, // VSL
- 2420U, // VSLB
- 2426U, // VSLDOI
- 2434U, // VSLH
- 2440U, // VSLO
- 2446U, // VSLW
- 3606932U, // VSPLTB
- 3606940U, // VSPLTH
- 3672484U, // VSPLTISB
- 3672494U, // VSPLTISH
- 3672504U, // VSPLTISW
- 3606978U, // VSPLTW
- 2506U, // VSR
- 2511U, // VSRAB
- 2518U, // VSRAH
- 2525U, // VSRAW
- 2532U, // VSRB
- 2538U, // VSRH
- 2544U, // VSRO
- 2550U, // VSRW
- 2556U, // VSUBCUW
- 2565U, // VSUBFP
- 2573U, // VSUBSBS
- 2582U, // VSUBSHS
- 2591U, // VSUBSWS
- 2600U, // VSUBUBM
- 2609U, // VSUBUBS
- 2618U, // VSUBUHM
- 2627U, // VSUBUHS
- 2636U, // VSUBUWM
- 2645U, // VSUBUWS
- 2654U, // VSUM2SWS
- 2664U, // VSUM4SBS
- 2674U, // VSUM4SHS
- 2684U, // VSUM4UBS
- 2694U, // VSUMSWS
- 35471U, // VUPKHPX
- 35480U, // VUPKHSB
- 35489U, // VUPKHSH
- 35498U, // VUPKLPX
- 35507U, // VUPKLSB
- 35516U, // VUPKLSH
- 2757U, // VXOR
- 527045U, // V_SET0
- 2763U, // XOR
- 2763U, // XOR8
- 15056U, // XORI
- 15056U, // XORI8
- 15062U, // XORIS
- 15062U, // XORIS8
+ 1U, // DEBUG_VALUE
+ 268435469U, // ADD4
+ 268435469U, // ADD8
+ 268435474U, // ADDC
+ 268435474U, // ADDC8
+ 268435480U, // ADDE
+ 268435480U, // ADDE8
+ 268439582U, // ADDI
+ 268439582U, // ADDI8
+ 268439588U, // ADDIC
+ 268439588U, // ADDIC8
+ 268439595U, // ADDICo
+ 268443699U, // ADDIS
+ 268443699U, // ADDIS8
+ 268468282U, // ADDME
+ 268468282U, // ADDME8
+ 268468289U, // ADDZE
+ 268468289U, // ADDZE8
+ 541065288U, // ADJCALLSTACKDOWN
+ 545259592U, // ADJCALLSTACKUP
+ 268435529U, // AND
+ 268435529U, // AND8
+ 268435534U, // ANDC
+ 268435534U, // ANDC8
+ 268447828U, // ANDISo
+ 268447828U, // ANDISo8
+ 268447836U, // ANDIo
+ 268447836U, // ANDIo8
+ 549453896U, // ATOMIC_CMP_SWAP_I16
+ 553648200U, // ATOMIC_CMP_SWAP_I32
+ 557842504U, // ATOMIC_CMP_SWAP_I64
+ 562036808U, // ATOMIC_CMP_SWAP_I8
+ 566231112U, // ATOMIC_LOAD_ADD_I16
+ 570425416U, // ATOMIC_LOAD_ADD_I32
+ 574619720U, // ATOMIC_LOAD_ADD_I64
+ 578814024U, // ATOMIC_LOAD_ADD_I8
+ 583008328U, // ATOMIC_LOAD_AND_I16
+ 587202632U, // ATOMIC_LOAD_AND_I32
+ 591396936U, // ATOMIC_LOAD_AND_I64
+ 595591240U, // ATOMIC_LOAD_AND_I8
+ 599785544U, // ATOMIC_LOAD_NAND_I16
+ 603979848U, // ATOMIC_LOAD_NAND_I32
+ 608174152U, // ATOMIC_LOAD_NAND_I64
+ 612368456U, // ATOMIC_LOAD_NAND_I8
+ 616562760U, // ATOMIC_LOAD_OR_I16
+ 620757064U, // ATOMIC_LOAD_OR_I32
+ 624951368U, // ATOMIC_LOAD_OR_I64
+ 629145672U, // ATOMIC_LOAD_OR_I8
+ 633339976U, // ATOMIC_LOAD_SUB_I16
+ 637534280U, // ATOMIC_LOAD_SUB_I32
+ 641728584U, // ATOMIC_LOAD_SUB_I64
+ 645922888U, // ATOMIC_LOAD_SUB_I8
+ 650117192U, // ATOMIC_LOAD_XOR_I16
+ 654311496U, // ATOMIC_LOAD_XOR_I32
+ 658505800U, // ATOMIC_LOAD_XOR_I64
+ 662700104U, // ATOMIC_LOAD_XOR_I8
+ 666894408U, // ATOMIC_SWAP_I16
+ 671088712U, // ATOMIC_SWAP_I32
+ 675283016U, // ATOMIC_SWAP_I64
+ 679477320U, // ATOMIC_SWAP_I8
+ 805306467U, // B
+ 1220804710U, // BCC
+ 104U, // BCTR
+ 109U, // BCTRL8_Darwin
+ 109U, // BCTRL8_ELF
+ 109U, // BCTRL_Darwin
+ 109U, // BCTRL_SVR4
+ 1493172339U, // BL8_Darwin
+ 1493172339U, // BL8_ELF
+ 1761607799U, // BLA8_Darwin
+ 1761607799U, // BLA8_ELF
+ 1761607799U, // BLA_Darwin
+ 1761607799U, // BLA_SVR4
+ 1228931174U, // BLR
+ 1493172339U, // BL_Darwin
+ 1493172339U, // BL_SVR4
+ 268435580U, // CMPD
+ 268439682U, // CMPDI
+ 268435593U, // CMPLD
+ 268447888U, // CMPLDI
+ 268435608U, // CMPLW
+ 268447903U, // CMPLWI
+ 268435623U, // CMPW
+ 268439725U, // CMPWI
+ 268468404U, // CNTLZD
+ 268468412U, // CNTLZW
+ 268435652U, // CREQV
+ 268435659U, // CROR
+ 268959940U, // CRSET
+ 1879048401U, // DCBA
+ 1879048407U, // DCBF
+ 1879048413U, // DCBI
+ 1879048419U, // DCBST
+ 1879048426U, // DCBT
+ 1879048432U, // DCBTST
+ 1879048440U, // DCBZ
+ 1879048446U, // DCBZL
+ 268435717U, // DIVD
+ 268435723U, // DIVDU
+ 268435730U, // DIVW
+ 268435736U, // DIVWU
+ 2147483935U, // DSS
+ 292U, // DSSALL
+ 2415919403U, // DST
+ 2415919403U, // DST64
+ 2415919408U, // DSTST
+ 2415919408U, // DSTST64
+ 2415919415U, // DSTSTT
+ 2415919415U, // DSTSTT64
+ 2415919423U, // DSTT
+ 2415919423U, // DSTT64
+ 696254536U, // DYNALLOC
+ 700448840U, // DYNALLOC8
+ 268435781U, // EQV
+ 268435781U, // EQV8
+ 268468554U, // EXTSB
+ 268468554U, // EXTSB8
+ 268468561U, // EXTSH
+ 268468561U, // EXTSH8
+ 268468568U, // EXTSW
+ 268468568U, // EXTSW_32
+ 268468568U, // EXTSW_32_64
+ 268468575U, // FABSD
+ 268468575U, // FABSS
+ 268435813U, // FADD
+ 268435819U, // FADDS
+ 268435813U, // FADDrtz
+ 268468594U, // FCFID
+ 268435833U, // FCMPUD
+ 268435833U, // FCMPUS
+ 268468608U, // FCTIDZ
+ 268468616U, // FCTIWZ
+ 268435856U, // FDIV
+ 268435862U, // FDIVS
+ 268435869U, // FMADD
+ 268435876U, // FMADDS
+ 268468652U, // FMRD
+ 268468652U, // FMRS
+ 268468652U, // FMRSD
+ 268435889U, // FMSUB
+ 268435896U, // FMSUBS
+ 268435904U, // FMUL
+ 268435910U, // FMULS
+ 268468685U, // FNABSD
+ 268468685U, // FNABSS
+ 268468692U, // FNEGD
+ 268468692U, // FNEGS
+ 268435930U, // FNMADD
+ 268435938U, // FNMADDS
+ 268435947U, // FNMSUB
+ 268435955U, // FNMSUBS
+ 268468732U, // FRSP
+ 268435970U, // FSELD
+ 268435970U, // FSELS
+ 268468744U, // FSQRT
+ 268468751U, // FSQRTS
+ 268435991U, // FSUB
+ 268435997U, // FSUBS
+ 269287972U, // LA
+ 269484584U, // LBZ
+ 269484584U, // LBZ8
+ 269746733U, // LBZU
+ 269746733U, // LBZU8
+ 270008883U, // LBZX
+ 270008883U, // LBZX8
+ 270271033U, // LD
+ 270008893U, // LDARX
+ 270533188U, // LDU
+ 270008905U, // LDX
+ 436208206U, // LDinto_toc
+ 270795321U, // LDtoc
+ 599U, // LDtoc_restore
+ 269484643U, // LFD
+ 269746787U, // LFDU
+ 270008936U, // LFDX
+ 269484654U, // LFS
+ 269746798U, // LFSU
+ 270008947U, // LFSX
+ 269484665U, // LHA
+ 269484665U, // LHA8
+ 269746814U, // LHAU
+ 269320830U, // LHAU8
+ 270008964U, // LHAX
+ 270008964U, // LHAX8
+ 270008970U, // LHBRX
+ 269484689U, // LHZ
+ 269484689U, // LHZ8
+ 269746838U, // LHZU
+ 269746838U, // LHZU8
+ 270008988U, // LHZX
+ 270008988U, // LHZX8
+ 271057570U, // LI
+ 271057570U, // LI8
+ 271319718U, // LIS
+ 271319718U, // LIS8
+ 270009003U, // LVEBX
+ 270009010U, // LVEHX
+ 270009017U, // LVEWX
+ 270009024U, // LVSL
+ 270009030U, // LVSR
+ 270009036U, // LVX
+ 270009041U, // LVXL
+ 270271191U, // LWA
+ 270009052U, // LWARX
+ 270009059U, // LWAX
+ 270009065U, // LWBRX
+ 269484784U, // LWZ
+ 269484784U, // LWZ8
+ 269746933U, // LWZU
+ 269746933U, // LWZU8
+ 270009083U, // LWZX
+ 270009083U, // LWZX8
+ 268468993U, // MCRF
+ 419431175U, // MFCR
+ 419431181U, // MFCTR
+ 419431181U, // MFCTR8
+ 419431188U, // MFFS
+ 419431194U, // MFLR
+ 419431194U, // MFLR8
+ 271581959U, // MFOCRF
+ 440402720U, // MFVRSAVE
+ 419431207U, // MFVSCR
+ 2684355375U, // MTCRF
+ 419431222U, // MTCTR
+ 419431222U, // MTCTR8
+ 2952790845U, // MTFSB0
+ 2952790853U, // MTFSB1
+ 3397387085U, // MTFSF
+ 419431252U, // MTLR
+ 419431252U, // MTLR8
+ 419431258U, // MTVRSAVE
+ 419431270U, // MTVSCR
+ 268436334U, // MULHD
+ 268436341U, // MULHDU
+ 268436349U, // MULHW
+ 268436356U, // MULHWU
+ 268436364U, // MULLD
+ 268440467U, // MULLI
+ 268436378U, // MULLW
+ 3489661043U, // MovePCtoLR
+ 3489661043U, // MovePCtoLR8
+ 268436385U, // NAND
+ 268436385U, // NAND8
+ 268469159U, // NEG
+ 268469159U, // NEG8
+ 940U, // NOP
+ 268436400U, // NOR
+ 268436400U, // NOR8
+ 268436405U, // OR
+ 268436405U, // OR4To8
+ 268436405U, // OR8
+ 268436405U, // OR8To4
+ 268436409U, // ORC
+ 268436409U, // ORC8
+ 268448702U, // ORI
+ 268448702U, // ORI8
+ 268448707U, // ORIS
+ 268448707U, // ORIS8
+ 268436425U, // RLDCL
+ 268452816U, // RLDICL
+ 268452824U, // RLDICR
+ 271975392U, // RLDIMI
+ 272008168U, // RLWIMI
+ 268456944U, // RLWINM
+ 268456952U, // RLWINMo
+ 268436481U, // RLWNM
+ 717226056U, // SELECT_CC_F4
+ 717226056U, // SELECT_CC_F8
+ 717226056U, // SELECT_CC_I4
+ 717226056U, // SELECT_CC_I8
+ 717226056U, // SELECT_CC_VRRC
+ 268436488U, // SLD
+ 268436493U, // SLW
+ 721420360U, // SPILL_CR
+ 268436498U, // SRAD
+ 268452888U, // SRADI
+ 268436511U, // SRAW
+ 268456997U, // SRAWI
+ 268436524U, // SRD
+ 268436529U, // SRW
+ 269485110U, // STB
+ 269485110U, // STB8
+ 3409970235U, // STBU
+ 3409970235U, // STBU8
+ 270009409U, // STBX
+ 270009409U, // STBX8
+ 270271559U, // STD
+ 270009420U, // STDCX
+ 3414164564U, // STDU
+ 270009434U, // STDUX
+ 270009441U, // STDX
+ 270009441U, // STDX_32
+ 270271559U, // STD_32
+ 269485159U, // STFD
+ 3409970285U, // STFDU
+ 270009460U, // STFDX
+ 270009467U, // STFIWX
+ 269485187U, // STFS
+ 3409970313U, // STFSU
+ 270009488U, // STFSX
+ 269485207U, // STH
+ 269485207U, // STH8
+ 270009500U, // STHBRX
+ 3409970340U, // STHU
+ 3409970340U, // STHU8
+ 270009514U, // STHX
+ 270009514U, // STHX8
+ 270009520U, // STVEBX
+ 270009528U, // STVEHX
+ 270009536U, // STVEWX
+ 270009544U, // STVX
+ 270009550U, // STVXL
+ 269485269U, // STW
+ 269485269U, // STW8
+ 270009562U, // STWBRX
+ 270009570U, // STWCX
+ 3409970410U, // STWU
+ 3409970410U, // STWU8
+ 268436720U, // STWUX
+ 270009591U, // STWX
+ 270009591U, // STWX8
+ 268436733U, // SUBF
+ 268436733U, // SUBF8
+ 268436739U, // SUBFC
+ 268436739U, // SUBFC8
+ 268436746U, // SUBFE
+ 268436746U, // SUBFE8
+ 268440849U, // SUBFIC
+ 268440849U, // SUBFIC8
+ 268469529U, // SUBFME
+ 268469529U, // SUBFME8
+ 268469537U, // SUBFZE
+ 268469537U, // SUBFZE8
+ 1321U, // SYNC
+ 1493172323U, // TAILB
+ 1493172323U, // TAILB8
+ 1761609006U, // TAILBA
+ 1761609006U, // TAILBA8
+ 104U, // TAILBCTR
+ 104U, // TAILBCTR8
+ 1757447474U, // TCRETURNai
+ 1757447487U, // TCRETURNai8
+ 1489012045U, // TCRETURNdi
+ 1489012058U, // TCRETURNdi8
+ 415270248U, // TCRETURNri
+ 415270261U, // TCRETURNri8
+ 1411U, // TRAP
+ 268469640U, // UPDATE_VRSAVE
+ 268436887U, // VADDCUW
+ 268436896U, // VADDFP
+ 268436904U, // VADDSBS
+ 268436913U, // VADDSHS
+ 268436922U, // VADDSWS
+ 268436931U, // VADDUBM
+ 268436940U, // VADDUBS
+ 268436949U, // VADDUHM
+ 268436958U, // VADDUHS
+ 268436967U, // VADDUWM
+ 268436976U, // VADDUWS
+ 268436985U, // VAND
+ 268436991U, // VANDC
+ 268436998U, // VAVGSB
+ 268437006U, // VAVGSH
+ 268437014U, // VAVGSW
+ 268437022U, // VAVGUB
+ 268437030U, // VAVGUH
+ 268437038U, // VAVGUW
+ 272041526U, // VCFSX
+ 272041533U, // VCFUX
+ 268437060U, // VCMPBFP
+ 268437069U, // VCMPBFPo
+ 268437079U, // VCMPEQFP
+ 268437089U, // VCMPEQFPo
+ 268437100U, // VCMPEQUB
+ 268437110U, // VCMPEQUBo
+ 268437121U, // VCMPEQUH
+ 268437131U, // VCMPEQUHo
+ 268437142U, // VCMPEQUW
+ 268437152U, // VCMPEQUWo
+ 268437163U, // VCMPGEFP
+ 268437173U, // VCMPGEFPo
+ 268437184U, // VCMPGTFP
+ 268437194U, // VCMPGTFPo
+ 268437205U, // VCMPGTSB
+ 268437215U, // VCMPGTSBo
+ 268437226U, // VCMPGTSH
+ 268437236U, // VCMPGTSHo
+ 268437247U, // VCMPGTSW
+ 268437257U, // VCMPGTSWo
+ 268437268U, // VCMPGTUB
+ 268437278U, // VCMPGTUBo
+ 268437289U, // VCMPGTUH
+ 268437299U, // VCMPGTUHo
+ 268437310U, // VCMPGTUW
+ 268437320U, // VCMPGTUWo
+ 272041811U, // VCTSXS
+ 272041819U, // VCTUXS
+ 268470115U, // VEXPTEFP
+ 268470125U, // VLOGEFP
+ 268437366U, // VMADDFP
+ 268437375U, // VMAXFP
+ 268437383U, // VMAXSB
+ 268437391U, // VMAXSH
+ 268437399U, // VMAXSW
+ 268437407U, // VMAXUB
+ 268437415U, // VMAXUH
+ 268437423U, // VMAXUW
+ 268437431U, // VMHADDSHS
+ 268437442U, // VMHRADDSHS
+ 268437454U, // VMINFP
+ 268437462U, // VMINSB
+ 268437470U, // VMINSH
+ 268437478U, // VMINSW
+ 268437486U, // VMINUB
+ 268437494U, // VMINUH
+ 268437502U, // VMINUW
+ 268437510U, // VMLADDUHM
+ 268437521U, // VMRGHB
+ 268437529U, // VMRGHH
+ 268437537U, // VMRGHW
+ 268437545U, // VMRGLB
+ 268437553U, // VMRGLH
+ 268437561U, // VMRGLW
+ 268437569U, // VMSUMMBM
+ 268437579U, // VMSUMSHM
+ 268437589U, // VMSUMSHS
+ 268437599U, // VMSUMUBM
+ 268437609U, // VMSUMUHM
+ 268437619U, // VMSUMUHS
+ 268437629U, // VMULESB
+ 268437638U, // VMULESH
+ 268437647U, // VMULEUB
+ 268437656U, // VMULEUH
+ 268437665U, // VMULOSB
+ 268437674U, // VMULOSH
+ 268437683U, // VMULOUB
+ 268437692U, // VMULOUH
+ 268437701U, // VNMSUBFP
+ 268437711U, // VNOR
+ 268437717U, // VOR
+ 268437722U, // VPERM
+ 268437729U, // VPKPX
+ 268437736U, // VPKSHSS
+ 268437745U, // VPKSHUS
+ 268437754U, // VPKSWSS
+ 268437763U, // VPKSWUS
+ 268437772U, // VPKUHUM
+ 268437781U, // VPKUHUS
+ 268437790U, // VPKUWUM
+ 268437799U, // VPKUWUS
+ 268470576U, // VREFP
+ 268470583U, // VRFIM
+ 268470590U, // VRFIN
+ 268470597U, // VRFIP
+ 268470604U, // VRFIZ
+ 268437843U, // VRLB
+ 268437849U, // VRLH
+ 268437855U, // VRLW
+ 268470629U, // VRSQRTEFP
+ 268437872U, // VSEL
+ 268437878U, // VSL
+ 268437883U, // VSLB
+ 268437889U, // VSLDOI
+ 268437897U, // VSLH
+ 268437903U, // VSLO
+ 268437909U, // VSLW
+ 272042395U, // VSPLTB
+ 272042403U, // VSPLTH
+ 272107947U, // VSPLTISB
+ 272107957U, // VSPLTISH
+ 272107967U, // VSPLTISW
+ 272042441U, // VSPLTW
+ 268437969U, // VSR
+ 268437974U, // VSRAB
+ 268437981U, // VSRAH
+ 268437988U, // VSRAW
+ 268437995U, // VSRB
+ 268438001U, // VSRH
+ 268438007U, // VSRO
+ 268438013U, // VSRW
+ 268438019U, // VSUBCUW
+ 268438028U, // VSUBFP
+ 268438036U, // VSUBSBS
+ 268438045U, // VSUBSHS
+ 268438054U, // VSUBSWS
+ 268438063U, // VSUBUBM
+ 268438072U, // VSUBUBS
+ 268438081U, // VSUBUHM
+ 268438090U, // VSUBUHS
+ 268438099U, // VSUBUWM
+ 268438108U, // VSUBUWS
+ 268438117U, // VSUM2SWS
+ 268438127U, // VSUM4SBS
+ 268438137U, // VSUM4SHS
+ 268438147U, // VSUM4UBS
+ 268438157U, // VSUMSWS
+ 268470934U, // VUPKHPX
+ 268470943U, // VUPKHSB
+ 268470952U, // VUPKHSH
+ 268470961U, // VUPKLPX
+ 268470970U, // VUPKLSB
+ 268470979U, // VUPKLSH
+ 268438220U, // VXOR
+ 268962508U, // V_SET0
+ 268438226U, // XOR
+ 268438226U, // XOR8
+ 268450519U, // XORI
+ 268450519U, // XORI8
+ 268450525U, // XORIS
+ 268450525U, // XORIS8
0U
};
const char *AsmStrs =
- "add \000add \000addc \000adde \000addi \000addic \000addic. \000addis \000"
- "addme \000addze \000\000and \000andc \000andis. \000andi. \000b \000b\000"
- "bctr\000bctrl\000bl \000bla \000cmpd \000cmpdi \000cmpld \000cmpldi \000"
- "cmplw \000cmplwi \000cmpw \000cmpwi \000cntlzd \000cntlzw \000creqv \000"
- "cror \000dcba \000dcbf \000dcbi \000dcbst \000dcbt \000dcbtst \000dcbz "
- "\000dcbzl \000divd \000divdu \000divw \000divwu \000dss \000dssall\000d"
- "st \000dstst \000dststt \000dstt \000eqv \000extsb \000extsh \000extsw "
- "\000fabs \000fadd \000fadds \000fcfid \000fcmpu \000fctidz \000fctiwz \000"
- "fdiv \000fdivs \000fmadd \000fmadds \000fmr \000fmsub \000fmsubs \000fm"
- "ul \000fmuls \000fnabs \000fneg \000fnmadd \000fnmadds \000fnmsub \000f"
- "nmsubs \000frsp \000fsel \000fsqrt \000fsqrts \000fsub \000fsubs \000la"
- " \000lbz \000lbzu \000lbzx \000ld \000ldarx \000ldu \000ldx \000ld 2, 8"
- "(\000ld 2, 40(1)\000lfd \000lfdx \000lfs \000lfsx \000lha \000lhau \000"
- "lhax \000lhbrx \000lhz \000lhzu \000lhzx \000li \000lis \000lvebx \000l"
- "vehx \000lvewx \000lvsl \000lvsr \000lvx \000lvxl \000lwa \000lwarx \000"
- "lwax \000lwbrx \000lwz \000lwzu \000lwzx \000mcrf \000mfcr \000mfctr \000"
- "mffs \000mflr \000mfspr \000mfvscr \000mtcrf \000mtctr \000mtfsb0 \000m"
- "tfsb1 \000mtfsf \000mtlr \000mtspr 256, \000mtvscr \000mulhd \000mulhdu"
- " \000mulhw \000mulhwu \000mulld \000mulli \000mullw \000nand \000neg \000"
- "nop\000nor \000or \000orc \000ori \000oris \000rldcl \000rldicl \000rld"
- "icr \000rldimi \000rlwimi \000rlwinm \000rlwinm. \000rlwnm \000sld \000"
- "slw \000srad \000sradi \000sraw \000srawi \000srd \000srw \000stb \000s"
- "tbu \000stbx \000std \000stdcx. \000stdu \000stdux \000stdx \000stfd \000"
- "stfdu \000stfdx \000stfiwx \000stfs \000stfsu \000stfsx \000sth \000sth"
- "brx \000sthu \000sthx \000stvebx \000stvehx \000stvewx \000stvx \000stv"
- "xl \000stw \000stwbrx \000stwcx. \000stwu \000stwux \000stwx \000subf \000"
- "subfc \000subfe \000subfic \000subfme \000subfze \000sync\000ba \000#TC"
- "_RETURNa \000#TC_RETURNa8 \000#TC_RETURNd \000#TC_RETURNd8 \000#TC_RETU"
- "RNr \000#TC_RETURNr8 \000trap\000UPDATE_VRSAVE \000vaddcuw \000vaddfp \000"
- "vaddsbs \000vaddshs \000vaddsws \000vaddubm \000vaddubs \000vadduhm \000"
- "vadduhs \000vadduwm \000vadduws \000vand \000vandc \000vavgsb \000vavgs"
- "h \000vavgsw \000vavgub \000vavguh \000vavguw \000vcfsx \000vcfux \000v"
- "cmpbfp \000vcmpbfp. \000vcmpeqfp \000vcmpeqfp. \000vcmpequb \000vcmpequ"
- "b. \000vcmpequh \000vcmpequh. \000vcmpequw \000vcmpequw. \000vcmpgefp \000"
- "vcmpgefp. \000vcmpgtfp \000vcmpgtfp. \000vcmpgtsb \000vcmpgtsb. \000vcm"
- "pgtsh \000vcmpgtsh. \000vcmpgtsw \000vcmpgtsw. \000vcmpgtub \000vcmpgtu"
- "b. \000vcmpgtuh \000vcmpgtuh. \000vcmpgtuw \000vcmpgtuw. \000vctsxs \000"
- "vctuxs \000vexptefp \000vlogefp \000vmaddfp \000vmaxfp \000vmaxsb \000v"
- "maxsh \000vmaxsw \000vmaxub \000vmaxuh \000vmaxuw \000vmhaddshs \000vmh"
- "raddshs \000vminfp \000vminsb \000vminsh \000vminsw \000vminub \000vmin"
- "uh \000vminuw \000vmladduhm \000vmrghb \000vmrghh \000vmrghw \000vmrglb"
- " \000vmrglh \000vmrglw \000vmsummbm \000vmsumshm \000vmsumshs \000vmsum"
- "ubm \000vmsumuhm \000vmsumuhs \000vmulesb \000vmulesh \000vmuleub \000v"
- "muleuh \000vmulosb \000vmulosh \000vmuloub \000vmulouh \000vnmsubfp \000"
- "vnor \000vor \000vperm \000vpkpx \000vpkshss \000vpkshus \000vpkswss \000"
- "vpkswus \000vpkuhum \000vpkuhus \000vpkuwum \000vpkuwus \000vrefp \000v"
- "rfim \000vrfin \000vrfip \000vrfiz \000vrlb \000vrlh \000vrlw \000vrsqr"
- "tefp \000vsel \000vsl \000vslb \000vsldoi \000vslh \000vslo \000vslw \000"
- "vspltb \000vsplth \000vspltisb \000vspltish \000vspltisw \000vspltw \000"
- "vsr \000vsrab \000vsrah \000vsraw \000vsrb \000vsrh \000vsro \000vsrw \000"
- "vsubcuw \000vsubfp \000vsubsbs \000vsubshs \000vsubsws \000vsububm \000"
- "vsububs \000vsubuhm \000vsubuhs \000vsubuwm \000vsubuws \000vsum2sws \000"
- "vsum4sbs \000vsum4shs \000vsum4ubs \000vsumsws \000vupkhpx \000vupkhsb "
- "\000vupkhsh \000vupklpx \000vupklsb \000vupklsh \000vxor \000xor \000xo"
- "ri \000xoris \000";
+ "DEBUG_VALUE\000add \000addc \000adde \000addi \000addic \000addic. \000"
+ "addis \000addme \000addze \000\000and \000andc \000andis. \000andi. \000"
+ "b \000b\000bctr\000bctrl\000bl \000bla \000cmpd \000cmpdi \000cmpld \000"
+ "cmpldi \000cmplw \000cmplwi \000cmpw \000cmpwi \000cntlzd \000cntlzw \000"
+ "creqv \000cror \000dcba \000dcbf \000dcbi \000dcbst \000dcbt \000dcbtst"
+ " \000dcbz \000dcbzl \000divd \000divdu \000divw \000divwu \000dss \000d"
+ "ssall\000dst \000dstst \000dststt \000dstt \000eqv \000extsb \000extsh "
+ "\000extsw \000fabs \000fadd \000fadds \000fcfid \000fcmpu \000fctidz \000"
+ "fctiwz \000fdiv \000fdivs \000fmadd \000fmadds \000fmr \000fmsub \000fm"
+ "subs \000fmul \000fmuls \000fnabs \000fneg \000fnmadd \000fnmadds \000f"
+ "nmsub \000fnmsubs \000frsp \000fsel \000fsqrt \000fsqrts \000fsub \000f"
+ "subs \000la \000lbz \000lbzu \000lbzx \000ld \000ldarx \000ldu \000ldx "
+ "\000ld 2, 8(\000ld 2, 40(1)\000lfd \000lfdx \000lfs \000lfsx \000lha \000"
+ "lhau \000lhax \000lhbrx \000lhz \000lhzu \000lhzx \000li \000lis \000lv"
+ "ebx \000lvehx \000lvewx \000lvsl \000lvsr \000lvx \000lvxl \000lwa \000"
+ "lwarx \000lwax \000lwbrx \000lwz \000lwzu \000lwzx \000mcrf \000mfcr \000"
+ "mfctr \000mffs \000mflr \000mfspr \000mfvscr \000mtcrf \000mtctr \000mt"
+ "fsb0 \000mtfsb1 \000mtfsf \000mtlr \000mtspr 256, \000mtvscr \000mulhd "
+ "\000mulhdu \000mulhw \000mulhwu \000mulld \000mulli \000mullw \000nand "
+ "\000neg \000nop\000nor \000or \000orc \000ori \000oris \000rldcl \000rl"
+ "dicl \000rldicr \000rldimi \000rlwimi \000rlwinm \000rlwinm. \000rlwnm "
+ "\000sld \000slw \000srad \000sradi \000sraw \000srawi \000srd \000srw \000"
+ "stb \000stbu \000stbx \000std \000stdcx. \000stdu \000stdux \000stdx \000"
+ "stfd \000stfdu \000stfdx \000stfiwx \000stfs \000stfsu \000stfsx \000st"
+ "h \000sthbrx \000sthu \000sthx \000stvebx \000stvehx \000stvewx \000stv"
+ "x \000stvxl \000stw \000stwbrx \000stwcx. \000stwu \000stwux \000stwx \000"
+ "subf \000subfc \000subfe \000subfic \000subfme \000subfze \000sync\000b"
+ "a \000#TC_RETURNa \000#TC_RETURNa8 \000#TC_RETURNd \000#TC_RETURNd8 \000"
+ "#TC_RETURNr \000#TC_RETURNr8 \000trap\000UPDATE_VRSAVE \000vaddcuw \000"
+ "vaddfp \000vaddsbs \000vaddshs \000vaddsws \000vaddubm \000vaddubs \000"
+ "vadduhm \000vadduhs \000vadduwm \000vadduws \000vand \000vandc \000vavg"
+ "sb \000vavgsh \000vavgsw \000vavgub \000vavguh \000vavguw \000vcfsx \000"
+ "vcfux \000vcmpbfp \000vcmpbfp. \000vcmpeqfp \000vcmpeqfp. \000vcmpequb "
+ "\000vcmpequb. \000vcmpequh \000vcmpequh. \000vcmpequw \000vcmpequw. \000"
+ "vcmpgefp \000vcmpgefp. \000vcmpgtfp \000vcmpgtfp. \000vcmpgtsb \000vcmp"
+ "gtsb. \000vcmpgtsh \000vcmpgtsh. \000vcmpgtsw \000vcmpgtsw. \000vcmpgtu"
+ "b \000vcmpgtub. \000vcmpgtuh \000vcmpgtuh. \000vcmpgtuw \000vcmpgtuw. \000"
+ "vctsxs \000vctuxs \000vexptefp \000vlogefp \000vmaddfp \000vmaxfp \000v"
+ "maxsb \000vmaxsh \000vmaxsw \000vmaxub \000vmaxuh \000vmaxuw \000vmhadd"
+ "shs \000vmhraddshs \000vminfp \000vminsb \000vminsh \000vminsw \000vmin"
+ "ub \000vminuh \000vminuw \000vmladduhm \000vmrghb \000vmrghh \000vmrghw"
+ " \000vmrglb \000vmrglh \000vmrglw \000vmsummbm \000vmsumshm \000vmsumsh"
+ "s \000vmsumubm \000vmsumuhm \000vmsumuhs \000vmulesb \000vmulesh \000vm"
+ "uleub \000vmuleuh \000vmulosb \000vmulosh \000vmuloub \000vmulouh \000v"
+ "nmsubfp \000vnor \000vor \000vperm \000vpkpx \000vpkshss \000vpkshus \000"
+ "vpkswss \000vpkswus \000vpkuhum \000vpkuhus \000vpkuwum \000vpkuwus \000"
+ "vrefp \000vrfim \000vrfin \000vrfip \000vrfiz \000vrlb \000vrlh \000vrl"
+ "w \000vrsqrtefp \000vsel \000vsl \000vslb \000vsldoi \000vslh \000vslo "
+ "\000vslw \000vspltb \000vsplth \000vspltisb \000vspltish \000vspltisw \000"
+ "vspltw \000vsr \000vsrab \000vsrah \000vsraw \000vsrb \000vsrh \000vsro"
+ " \000vsrw \000vsubcuw \000vsubfp \000vsubsbs \000vsubshs \000vsubsws \000"
+ "vsububm \000vsububs \000vsubuhm \000vsubuhs \000vsubuwm \000vsubuws \000"
+ "vsum2sws \000vsum4sbs \000vsum4shs \000vsum4ubs \000vsumsws \000vupkhpx"
+ " \000vupkhsb \000vupkhsh \000vupklpx \000vupklsb \000vupklsh \000vxor \000"
+ "xor \000xori \000xoris \000";
#ifndef NO_ASM_WRITER_BOILERPLATE
@@ -620,26 +621,26 @@ void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
switch ((Bits >> 28) & 15) {
default: // unreachable.
case 0:
+ // DEBUG_VALUE, BCTR, BCTRL8_Darwin, BCTRL8_ELF, BCTRL_Darwin, BCTRL_SVR4...
+ return;
+ break;
+ case 1:
// ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, ADDI, ADDI8, ADDIC, ADDIC8, ADDI...
printOperand(MI, 0);
break;
- case 1:
+ case 2:
// ADJCALLSTACKDOWN, ADJCALLSTACKUP, ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP...
PrintSpecial(MI, "comment");
break;
- case 2:
+ case 3:
// B
printBranchOperand(MI, 0);
return;
break;
- case 3:
+ case 4:
// BCC, BLR
printPredicateOperand(MI, 0, "cc");
break;
- case 4:
- // BCTR, BCTRL8_Darwin, BCTRL8_ELF, BCTRL_Darwin, BCTRL_SVR4, DSSALL, LDt...
- return;
- break;
case 5:
// BL8_Darwin, BL8_ELF, BL_Darwin, BL_SVR4, TAILB, TAILB8, TCRETURNdi, TC...
printCallOperand(MI, 0);
diff --git a/libclamav/c++/PPCGenCodeEmitter.inc b/libclamav/c++/PPCGenCodeEmitter.inc
index 597195f..ebb9db1 100644
--- a/libclamav/c++/PPCGenCodeEmitter.inc
+++ b/libclamav/c++/PPCGenCodeEmitter.inc
@@ -19,6 +19,7 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
0U,
0U,
0U,
+ 0U,
2080375316U, // ADD4
2080375316U, // ADD8
2080374804U, // ADDC
diff --git a/libclamav/c++/PPCGenDAGISel.inc b/libclamav/c++/PPCGenDAGISel.inc
index 371f730..4ab2322 100644
--- a/libclamav/c++/PPCGenDAGISel.inc
+++ b/libclamav/c++/PPCGenDAGISel.inc
@@ -853,61 +853,61 @@ inline bool Predicate_zextloadi8(SDNode *N) {
}
-DISABLE_INLINE SDNode *Emit_0(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_0(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_1(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_1(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_HI16(Tmp1.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_2(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N10);
-}
-DISABLE_INLINE SDNode *Emit_3(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1);
-}
-DISABLE_INLINE SDNode *Emit_4(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_2(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N10);
+}
+DISABLE_INLINE SDNode *Emit_3(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1);
+}
+DISABLE_INLINE SDNode *Emit_4(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_LO16(Tmp1.getNode());
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp2), 0);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
SDValue Tmp4 = Transform_HA16(Tmp1.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp3, Tmp4);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp3, Tmp4);
}
-DISABLE_INLINE SDNode *Emit_5(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N00);
+DISABLE_INLINE SDNode *Emit_5(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N00);
}
-SDNode *Select_ISD_ADD_i32(const SDValue &N) {
+SDNode *Select_ISD_ADD_i32(SDNode *N) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
// Pattern: (add:i32 GPRC:i32:$rA, (PPClo:i32 (tglobaladdr:i32):$sym, 0:i32))
// Emits: (LA:i32 GPRC:i32:$rA, (tglobaladdr:i32):$sym)
// Pattern complexity = 14 cost = 1 size = 0
- if (N1.getOpcode() == PPCISD::Lo) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N1.getNode()->getOpcode() == PPCISD::Lo) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -917,15 +917,15 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == PPCISD::Hi) {
- SDValue N10 = N1.getOperand(0);
+ if (N1.getNode()->getOpcode() == PPCISD::Hi) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (add:i32 GPRC:i32:$in, (PPChi:i32 (tglobaladdr:i32):$g, 0:i32))
// Emits: (ADDIS:i32 GPRC:i32:$in, (tglobaladdr:i32):$g)
// Pattern complexity = 14 cost = 1 size = 0
- if (N10.getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N10.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -938,9 +938,9 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPRC:i32:$in, (PPChi:i32 (tconstpool:i32):$g, 0:i32))
// Emits: (ADDIS:i32 GPRC:i32:$in, (tconstpool:i32):$g)
// Pattern complexity = 14 cost = 1 size = 0
- if (N10.getOpcode() == ISD::TargetConstantPool) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -953,9 +953,9 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPRC:i32:$in, (PPChi:i32 (tjumptable:i32):$g, 0:i32))
// Emits: (ADDIS:i32 GPRC:i32:$in, (tjumptable:i32):$g)
// Pattern complexity = 14 cost = 1 size = 0
- if (N10.getOpcode() == ISD::TargetJumpTable) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N10.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -968,9 +968,9 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GPRC:i32:$in, (PPChi:i32 (tblockaddress:i32):$g, 0:i32))
// Emits: (ADDIS:i32 GPRC:i32:$in, (tblockaddress:i32):$g)
// Pattern complexity = 14 cost = 1 size = 0
- if (N10.getOpcode() == ISD::TargetBlockAddress) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N10.getNode()->getOpcode() == ISD::TargetBlockAddress) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -985,11 +985,11 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (PPClo:i32 (tglobaladdr:i32):$sym, 0:i32), GPRC:i32:$rA)
// Emits: (LA:i32 GPRC:i32:$rA, (tglobaladdr:i32):$sym)
// Pattern complexity = 14 cost = 1 size = 0
- if (N0.getOpcode() == PPCISD::Lo) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N0.getNode()->getOpcode() == PPCISD::Lo) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -999,15 +999,15 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == PPCISD::Hi) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == PPCISD::Hi) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (add:i32 (PPChi:i32 (tglobaladdr:i32):$g, 0:i32), GPRC:i32:$in)
// Emits: (ADDIS:i32 GPRC:i32:$in, (tglobaladdr:i32):$g)
// Pattern complexity = 14 cost = 1 size = 0
- if (N00.getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N00.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -1020,9 +1020,9 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (PPChi:i32 (tconstpool:i32):$g, 0:i32), GPRC:i32:$in)
// Emits: (ADDIS:i32 GPRC:i32:$in, (tconstpool:i32):$g)
// Pattern complexity = 14 cost = 1 size = 0
- if (N00.getOpcode() == ISD::TargetConstantPool) {
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N00.getNode()->getOpcode() == ISD::TargetConstantPool) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -1035,9 +1035,9 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (PPChi:i32 (tjumptable:i32):$g, 0:i32), GPRC:i32:$in)
// Emits: (ADDIS:i32 GPRC:i32:$in, (tjumptable:i32):$g)
// Pattern complexity = 14 cost = 1 size = 0
- if (N00.getOpcode() == ISD::TargetJumpTable) {
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N00.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -1050,9 +1050,9 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (PPChi:i32 (tblockaddress:i32):$g, 0:i32), GPRC:i32:$in)
// Emits: (ADDIS:i32 GPRC:i32:$in, (tblockaddress:i32):$g)
// Pattern complexity = 14 cost = 1 size = 0
- if (N00.getOpcode() == ISD::TargetBlockAddress) {
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N00.getNode()->getOpcode() == ISD::TargetBlockAddress) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -1062,8 +1062,8 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (add:i32 GPRC:i32:$rA, (imm:i32)<<P:Predicate_immSExt16>>:$imm)
// Emits: (ADDI:i32 GPRC:i32:$rA, (imm:i32):$imm)
@@ -1096,33 +1096,33 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_6(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_6(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_7(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_7(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
SDValue Tmp2 = Transform_HI16(Tmp1.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2);
}
-SDNode *Select_ISD_ADD_i64(const SDValue &N) {
+SDNode *Select_ISD_ADD_i64(SDNode *N) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == PPCISD::Hi) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == PPCISD::Hi) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (add:i64 G8RC:i64:$in, (PPChi:i64 (tglobaladdr:i64):$g, 0:i64))
// Emits: (ADDIS8:i64 G8RC:i64:$in, (tglobaladdr:i64):$g)
// Pattern complexity = 14 cost = 1 size = 0
- if (N10.getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N10.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -1135,9 +1135,9 @@ SDNode *Select_ISD_ADD_i64(const SDValue &N) {
// Pattern: (add:i64 G8RC:i64:$in, (PPChi:i64 (tconstpool:i64):$g, 0:i64))
// Emits: (ADDIS8:i64 G8RC:i64:$in, (tconstpool:i64):$g)
// Pattern complexity = 14 cost = 1 size = 0
- if (N10.getOpcode() == ISD::TargetConstantPool) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -1150,9 +1150,9 @@ SDNode *Select_ISD_ADD_i64(const SDValue &N) {
// Pattern: (add:i64 G8RC:i64:$in, (PPChi:i64 (tjumptable:i64):$g, 0:i64))
// Emits: (ADDIS8:i64 G8RC:i64:$in, (tjumptable:i64):$g)
// Pattern complexity = 14 cost = 1 size = 0
- if (N10.getOpcode() == ISD::TargetJumpTable) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N10.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -1165,9 +1165,9 @@ SDNode *Select_ISD_ADD_i64(const SDValue &N) {
// Pattern: (add:i64 G8RC:i64:$in, (PPChi:i64 (tblockaddress:i64):$g, 0:i64))
// Emits: (ADDIS8:i64 G8RC:i64:$in, (tblockaddress:i64):$g)
// Pattern complexity = 14 cost = 1 size = 0
- if (N10.getOpcode() == ISD::TargetBlockAddress) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N10.getNode()->getOpcode() == ISD::TargetBlockAddress) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -1178,15 +1178,15 @@ SDNode *Select_ISD_ADD_i64(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == PPCISD::Hi) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == PPCISD::Hi) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (add:i64 (PPChi:i64 (tglobaladdr:i64):$g, 0:i64), G8RC:i64:$in)
// Emits: (ADDIS8:i64 G8RC:i64:$in, (tglobaladdr:i64):$g)
// Pattern complexity = 14 cost = 1 size = 0
- if (N00.getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N00.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -1199,9 +1199,9 @@ SDNode *Select_ISD_ADD_i64(const SDValue &N) {
// Pattern: (add:i64 (PPChi:i64 (tconstpool:i64):$g, 0:i64), G8RC:i64:$in)
// Emits: (ADDIS8:i64 G8RC:i64:$in, (tconstpool:i64):$g)
// Pattern complexity = 14 cost = 1 size = 0
- if (N00.getOpcode() == ISD::TargetConstantPool) {
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N00.getNode()->getOpcode() == ISD::TargetConstantPool) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -1214,9 +1214,9 @@ SDNode *Select_ISD_ADD_i64(const SDValue &N) {
// Pattern: (add:i64 (PPChi:i64 (tjumptable:i64):$g, 0:i64), G8RC:i64:$in)
// Emits: (ADDIS8:i64 G8RC:i64:$in, (tjumptable:i64):$g)
// Pattern complexity = 14 cost = 1 size = 0
- if (N00.getOpcode() == ISD::TargetJumpTable) {
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N00.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -1229,9 +1229,9 @@ SDNode *Select_ISD_ADD_i64(const SDValue &N) {
// Pattern: (add:i64 (PPChi:i64 (tblockaddress:i64):$g, 0:i64), G8RC:i64:$in)
// Emits: (ADDIS8:i64 G8RC:i64:$in, (tblockaddress:i64):$g)
// Pattern complexity = 14 cost = 1 size = 0
- if (N00.getOpcode() == ISD::TargetBlockAddress) {
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N00.getNode()->getOpcode() == ISD::TargetBlockAddress) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -1241,8 +1241,8 @@ SDNode *Select_ISD_ADD_i64(const SDValue &N) {
}
}
}
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (add:i64 G8RC:i64:$rA, (imm:i64)<<P:Predicate_immSExt16>>:$imm)
// Emits: (ADDI8:i64 G8RC:i64:$rA, (imm:i64):$imm)
@@ -1269,47 +1269,47 @@ SDNode *Select_ISD_ADD_i64(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_ADD_v16i8(const SDValue &N) {
+SDNode *Select_ISD_ADD_v16i8(SDNode *N) {
SDNode *Result = Emit_3(N, PPC::VADDUBM, MVT::v16i8);
return Result;
}
-SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
+SDNode *Select_ISD_ADD_v8i16(SDNode *N) {
SDNode *Result = Emit_3(N, PPC::VADDUHM, MVT::v8i16);
return Result;
}
-SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
+SDNode *Select_ISD_ADD_v4i32(SDNode *N) {
SDNode *Result = Emit_3(N, PPC::VADDUWM, MVT::v4i32);
return Result;
}
-DISABLE_INLINE SDNode *Emit_8(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_8(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, Tmp1);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, Tmp1);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_9(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, N1);
+DISABLE_INLINE SDNode *Emit_9(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, N1);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-SDNode *Select_ISD_ADDC_i32(const SDValue &N) {
+SDNode *Select_ISD_ADDC_i32(SDNode *N) {
// Pattern: (addc:i32 GPRC:i32:$rA, (imm:i32)<<P:Predicate_immSExt16>>:$imm)
// Emits: (ADDIC:i32 GPRC:i32:$rA, (imm:i32):$imm)
// Pattern complexity = 7 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_immSExt16(N1.getNode())) {
SDNode *Result = Emit_8(N, PPC::ADDIC, MVT::i32);
return Result;
@@ -1323,24 +1323,24 @@ SDNode *Select_ISD_ADDC_i32(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_10(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_10(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, Tmp1);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, Tmp1);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-SDNode *Select_ISD_ADDC_i64(const SDValue &N) {
+SDNode *Select_ISD_ADDC_i64(SDNode *N) {
// Pattern: (addc:i64 G8RC:i64:$rA, (imm:i64)<<P:Predicate_immSExt16>>:$imm)
// Emits: (ADDIC8:i64 G8RC:i64:$rA, (imm:i64):$imm)
// Pattern complexity = 7 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_immSExt16(N1.getNode())) {
SDNode *Result = Emit_10(N, PPC::ADDIC8, MVT::i64);
return Result;
@@ -1354,34 +1354,34 @@ SDNode *Select_ISD_ADDC_i64(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_11(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue InFlag = N.getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, N1, InFlag);
+DISABLE_INLINE SDNode *Emit_11(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue InFlag = N->getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, N1, InFlag);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_12(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue InFlag = N.getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, InFlag);
+DISABLE_INLINE SDNode *Emit_12(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue InFlag = N->getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, InFlag);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
+SDNode *Select_ISD_ADDE_i32(SDNode *N) {
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (adde:i32 GPRC:i32:$rA, 0:i32)
// Emits: (ADDZE:i32 GPRC:i32:$rA)
// Pattern complexity = 8 cost = 1 size = 0
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -1394,7 +1394,7 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
// Pattern: (adde:i32 GPRC:i32:$rA, (imm:i32)<<P:Predicate_immAllOnes>>)
// Emits: (ADDME:i32 GPRC:i32:$rA)
// Pattern complexity = 7 cost = 1 size = 0
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N1.getNode())) {
SDNode *Result = Emit_12(N, PPC::ADDME, MVT::i32);
return Result;
@@ -1408,16 +1408,16 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_ADDE_i64(const SDValue &N) {
+SDNode *Select_ISD_ADDE_i64(SDNode *N) {
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (adde:i64 G8RC:i64:$rA, 0:i64)
// Emits: (ADDZE8:i64 G8RC:i64:$rA)
// Pattern complexity = 8 cost = 1 size = 0
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -1430,7 +1430,7 @@ SDNode *Select_ISD_ADDE_i64(const SDValue &N) {
// Pattern: (adde:i64 G8RC:i64:$rA, (imm:i64)<<P:Predicate_immAllOnes>>)
// Emits: (ADDME8:i64 G8RC:i64:$rA)
// Pattern complexity = 7 cost = 1 size = 0
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N1.getNode())) {
SDNode *Result = Emit_12(N, PPC::ADDME8, MVT::i64);
return Result;
@@ -1444,37 +1444,37 @@ SDNode *Select_ISD_ADDE_i64(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_13(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_13(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_LO16(Tmp1.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_14(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_14(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp3 = Transform_MB(Tmp2.getNode());
SDValue Tmp4 = Transform_ME(Tmp2.getNode());
SDValue Ops0[] = { N00, N01, Tmp3, Tmp4 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-SDNode *Select_ISD_AND_i32(const SDValue &N) {
+SDNode *Select_ISD_AND_i32(SDNode *N) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (and:i32 GPRC:i32:$rS, (xor:i32 GPRC:i32:$rB, (imm:i32)<<P:Predicate_immAllOnes>>))
// Emits: (ANDC:i32 GPRC:i32:$rS, GPRC:i32:$rB)
// Pattern complexity = 10 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N11.getNode())) {
SDNode *Result = Emit_2(N, PPC::ANDC, MVT::i32);
return Result;
@@ -1485,11 +1485,11 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Pattern: (and:i32 (rotl:i32 GPRC:i32:$in, GPRC:i32:$sh), (imm:i32)<<P:Predicate_maskimm32>>:$imm)
// Emits: (RLWNM:i32 GPRC:i32:$in, GPRC:i32:$sh, (MB:i32 (imm:i32)<<P:Predicate_maskimm32>>:$imm), (ME:i32 (imm:i32)<<P:Predicate_maskimm32>>:$imm))
// Pattern complexity = 10 cost = 1 size = 0
- if (N0.getOpcode() == ISD::ROTL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::ROTL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_maskimm32(N1.getNode()) &&
N01.getValueType() == MVT::i32) {
SDNode *Result = Emit_14(N, PPC::RLWNM, MVT::i32);
@@ -1500,17 +1500,17 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Pattern: (and:i32 (xor:i32 GPRC:i32:$rB, (imm:i32)<<P:Predicate_immAllOnes>>), GPRC:i32:$rS)
// Emits: (ANDC:i32 GPRC:i32:$rS, GPRC:i32:$rB)
// Pattern complexity = 10 cost = 1 size = 0
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N01.getNode())) {
SDNode *Result = Emit_5(N, PPC::ANDC, MVT::i32);
return Result;
}
}
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (and:i32 GPRC:i32:$src1, (imm:i32)<<P:Predicate_immZExt16>><<X:LO16>>:$src2)
// Emits: (ANDIo:i32 GPRC:i32:$src1, (LO16:i32 (imm:i32):$src2))
@@ -1537,26 +1537,26 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_15(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_15(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
SDValue Tmp2 = Transform_LO16(Tmp1.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2);
}
-SDNode *Select_ISD_AND_i64(const SDValue &N) {
+SDNode *Select_ISD_AND_i64(SDNode *N) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (and:i64 G8RC:i64:$rS, (xor:i64 G8RC:i64:$rB, (imm:i64)<<P:Predicate_immAllOnes>>))
// Emits: (ANDC8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
// Pattern complexity = 10 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N11.getNode())) {
SDNode *Result = Emit_2(N, PPC::ANDC8, MVT::i64);
return Result;
@@ -1567,17 +1567,17 @@ SDNode *Select_ISD_AND_i64(const SDValue &N) {
// Pattern: (and:i64 (xor:i64 G8RC:i64:$rB, (imm:i64)<<P:Predicate_immAllOnes>>), G8RC:i64:$rS)
// Emits: (ANDC8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
// Pattern complexity = 10 cost = 1 size = 0
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N01.getNode())) {
SDNode *Result = Emit_5(N, PPC::ANDC8, MVT::i64);
return Result;
}
}
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (and:i64 G8RC:i64:$src1, (imm:i64)<<P:Predicate_immZExt16>><<X:LO16>>:$src2)
// Emits: (ANDIo8:i64 G8RC:i64:$src1, (LO16:i32 (imm:i64):$src2))
@@ -1604,34 +1604,34 @@ SDNode *Select_ISD_AND_i64(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_16(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N11);
+DISABLE_INLINE SDNode *Emit_16(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N11);
}
-DISABLE_INLINE SDNode *Emit_17(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N01);
+DISABLE_INLINE SDNode *Emit_17(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N01);
}
-SDNode *Select_ISD_AND_v4i32(const SDValue &N) {
+SDNode *Select_ISD_AND_v4i32(SDNode *N) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
{
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
// Pattern: (and:v4i32 VRRC:v4i32:$vA, (xor:v4i32 VRRC:v4i32:$vB, (build_vector:v4i32)<<P:Predicate_immAllOnesV>>))
// Emits: (VANDC:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 10 cost = 1 size = 0
- if (N11.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N11.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N11.getNode())) {
SDNode *Result = Emit_2(N, PPC::VANDC, MVT::v4i32);
return Result;
@@ -1640,7 +1640,7 @@ SDNode *Select_ISD_AND_v4i32(const SDValue &N) {
// Pattern: (and:v4i32 VRRC:v4i32:$A, (xor:v4i32 VRRC:v4i32:$B, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>))
// Emits: (VANDC:v4i32 VRRC:v16i8:$A, VRRC:v16i8:$B)
// Pattern complexity = 10 cost = 1 size = 0
- if (N11.getOpcode() == ISD::BIT_CONVERT &&
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N11.getNode())) {
SDNode *Result = Emit_2(N, PPC::VANDC, MVT::v4i32);
return Result;
@@ -1650,22 +1650,22 @@ SDNode *Select_ISD_AND_v4i32(const SDValue &N) {
// Pattern: (and:v4i32 VRRC:v4i32:$vA, (xor:v4i32 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>, VRRC:v4i32:$vB))
// Emits: (VANDC:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 10 cost = 1 size = 0
- if (N10.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N10.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N10.getNode())) {
SDNode *Result = Emit_16(N, PPC::VANDC, MVT::v4i32);
return Result;
}
}
}
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (and:v4i32 (xor:v4i32 VRRC:v4i32:$vB, (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VRRC:v4i32:$vA)
// Emits: (VANDC:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 10 cost = 1 size = 0
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N01.getNode())) {
SDNode *Result = Emit_5(N, PPC::VANDC, MVT::v4i32);
return Result;
@@ -1675,7 +1675,7 @@ SDNode *Select_ISD_AND_v4i32(const SDValue &N) {
// Pattern: (and:v4i32 (xor:v4i32 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>, VRRC:v4i32:$vB), VRRC:v4i32:$vA)
// Emits: (VANDC:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 10 cost = 1 size = 0
- if (N00.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N00.getNode())) {
SDNode *Result = Emit_17(N, PPC::VANDC, MVT::v4i32);
return Result;
@@ -1686,25 +1686,25 @@ SDNode *Select_ISD_AND_v4i32(const SDValue &N) {
// Emits: (VANDC:v4i32 VRRC:v16i8:$A, VRRC:v16i8:$B)
// Pattern complexity = 10 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N10.getNode())) {
SDNode *Result = Emit_16(N, PPC::VANDC, MVT::v4i32);
return Result;
}
}
}
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (and:v4i32 (xor:v4i32 VRRC:v4i32:$B, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>), VRRC:v4i32:$A)
// Emits: (VANDC:v4i32 VRRC:v16i8:$A, VRRC:v16i8:$B)
// Pattern complexity = 10 cost = 1 size = 0
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N01.getNode())) {
SDNode *Result = Emit_5(N, PPC::VANDC, MVT::v4i32);
return Result;
@@ -1714,7 +1714,7 @@ SDNode *Select_ISD_AND_v4i32(const SDValue &N) {
// Pattern: (and:v4i32 (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, VRRC:v4i32:$B), VRRC:v4i32:$A)
// Emits: (VANDC:v4i32 VRRC:v16i8:$A, VRRC:v16i8:$B)
// Pattern complexity = 10 cost = 1 size = 0
- if (N00.getOpcode() == ISD::BIT_CONVERT &&
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N00.getNode())) {
SDNode *Result = Emit_17(N, PPC::VANDC, MVT::v4i32);
return Result;
@@ -1729,12 +1729,12 @@ SDNode *Select_ISD_AND_v4i32(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_18(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N0);
+DISABLE_INLINE SDNode *Emit_18(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N0);
}
-SDNode *Select_ISD_ANY_EXTEND_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_ANY_EXTEND_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_18(N, PPC::OR4To8, MVT::i64);
return Result;
@@ -1744,26 +1744,26 @@ SDNode *Select_ISD_ANY_EXTEND_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_19(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_19(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, N2, N3, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 5);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 5);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-SDNode *Select_ISD_ATOMIC_CMP_SWAP_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
+SDNode *Select_ISD_ATOMIC_CMP_SWAP_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
// Pattern: (atomic_cmp_swap:i32 xoaddr:iPTR:$ptr, GPRC:i32:$old, GPRC:i32:$new)<<P:Predicate_atomic_cmp_swap_8>>
// Emits: (ATOMIC_CMP_SWAP_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$old, GPRC:i32:$new)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_cmp_swap_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_cmp_swap_8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -1775,8 +1775,8 @@ SDNode *Select_ISD_ATOMIC_CMP_SWAP_i32(const SDValue &N) {
// Pattern: (atomic_cmp_swap:i32 xoaddr:iPTR:$ptr, GPRC:i32:$old, GPRC:i32:$new)<<P:Predicate_atomic_cmp_swap_16>>
// Emits: (ATOMIC_CMP_SWAP_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$old, GPRC:i32:$new)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_cmp_swap_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_cmp_swap_16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -1788,8 +1788,8 @@ SDNode *Select_ISD_ATOMIC_CMP_SWAP_i32(const SDValue &N) {
// Pattern: (atomic_cmp_swap:i32 xoaddr:iPTR:$ptr, GPRC:i32:$old, GPRC:i32:$new)<<P:Predicate_atomic_cmp_swap_32>>
// Emits: (ATOMIC_CMP_SWAP_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$old, GPRC:i32:$new)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_cmp_swap_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_cmp_swap_32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -1802,10 +1802,10 @@ SDNode *Select_ISD_ATOMIC_CMP_SWAP_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_CMP_SWAP_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_cmp_swap_64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_CMP_SWAP_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_cmp_swap_64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -1818,25 +1818,25 @@ SDNode *Select_ISD_ATOMIC_CMP_SWAP_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_20(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_20(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, N2, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 4);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 4);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-SDNode *Select_ISD_ATOMIC_LOAD_ADD_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
+SDNode *Select_ISD_ATOMIC_LOAD_ADD_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
// Pattern: (atomic_load_add:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_add_8>>
// Emits: (ATOMIC_LOAD_ADD_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_add_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_load_add_8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -1848,8 +1848,8 @@ SDNode *Select_ISD_ATOMIC_LOAD_ADD_i32(const SDValue &N) {
// Pattern: (atomic_load_add:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_add_16>>
// Emits: (ATOMIC_LOAD_ADD_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_add_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_load_add_16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -1861,8 +1861,8 @@ SDNode *Select_ISD_ATOMIC_LOAD_ADD_i32(const SDValue &N) {
// Pattern: (atomic_load_add:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_add_32>>
// Emits: (ATOMIC_LOAD_ADD_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_add_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_load_add_32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -1875,10 +1875,10 @@ SDNode *Select_ISD_ATOMIC_LOAD_ADD_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_ADD_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_add_64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_ADD_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_add_64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -1891,14 +1891,14 @@ SDNode *Select_ISD_ATOMIC_LOAD_ADD_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_AND_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
+SDNode *Select_ISD_ATOMIC_LOAD_AND_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
// Pattern: (atomic_load_and:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_and_8>>
// Emits: (ATOMIC_LOAD_AND_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_and_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_load_and_8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -1910,8 +1910,8 @@ SDNode *Select_ISD_ATOMIC_LOAD_AND_i32(const SDValue &N) {
// Pattern: (atomic_load_and:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_and_16>>
// Emits: (ATOMIC_LOAD_AND_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_and_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_load_and_16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -1923,8 +1923,8 @@ SDNode *Select_ISD_ATOMIC_LOAD_AND_i32(const SDValue &N) {
// Pattern: (atomic_load_and:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_and_32>>
// Emits: (ATOMIC_LOAD_AND_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_and_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_load_and_32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -1937,10 +1937,10 @@ SDNode *Select_ISD_ATOMIC_LOAD_AND_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_AND_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_and_64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_AND_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_and_64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -1953,14 +1953,14 @@ SDNode *Select_ISD_ATOMIC_LOAD_AND_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_NAND_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
+SDNode *Select_ISD_ATOMIC_LOAD_NAND_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
// Pattern: (atomic_load_nand:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_nand_8>>
// Emits: (ATOMIC_LOAD_NAND_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_nand_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_load_nand_8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -1972,8 +1972,8 @@ SDNode *Select_ISD_ATOMIC_LOAD_NAND_i32(const SDValue &N) {
// Pattern: (atomic_load_nand:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_nand_16>>
// Emits: (ATOMIC_LOAD_NAND_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_nand_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_load_nand_16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -1985,8 +1985,8 @@ SDNode *Select_ISD_ATOMIC_LOAD_NAND_i32(const SDValue &N) {
// Pattern: (atomic_load_nand:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_nand_32>>
// Emits: (ATOMIC_LOAD_NAND_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_nand_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_load_nand_32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -1999,10 +1999,10 @@ SDNode *Select_ISD_ATOMIC_LOAD_NAND_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_NAND_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_nand_64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_NAND_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_nand_64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -2015,14 +2015,14 @@ SDNode *Select_ISD_ATOMIC_LOAD_NAND_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_OR_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
+SDNode *Select_ISD_ATOMIC_LOAD_OR_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
// Pattern: (atomic_load_or:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_or_8>>
// Emits: (ATOMIC_LOAD_OR_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_or_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_load_or_8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -2034,8 +2034,8 @@ SDNode *Select_ISD_ATOMIC_LOAD_OR_i32(const SDValue &N) {
// Pattern: (atomic_load_or:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_or_16>>
// Emits: (ATOMIC_LOAD_OR_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_or_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_load_or_16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -2047,8 +2047,8 @@ SDNode *Select_ISD_ATOMIC_LOAD_OR_i32(const SDValue &N) {
// Pattern: (atomic_load_or:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_or_32>>
// Emits: (ATOMIC_LOAD_OR_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_or_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_load_or_32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -2061,10 +2061,10 @@ SDNode *Select_ISD_ATOMIC_LOAD_OR_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_OR_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_or_64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_OR_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_or_64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -2077,14 +2077,14 @@ SDNode *Select_ISD_ATOMIC_LOAD_OR_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_SUB_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
+SDNode *Select_ISD_ATOMIC_LOAD_SUB_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
// Pattern: (atomic_load_sub:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_sub_8>>
// Emits: (ATOMIC_LOAD_SUB_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_sub_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_load_sub_8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -2096,8 +2096,8 @@ SDNode *Select_ISD_ATOMIC_LOAD_SUB_i32(const SDValue &N) {
// Pattern: (atomic_load_sub:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_sub_16>>
// Emits: (ATOMIC_LOAD_SUB_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_sub_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_load_sub_16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -2109,8 +2109,8 @@ SDNode *Select_ISD_ATOMIC_LOAD_SUB_i32(const SDValue &N) {
// Pattern: (atomic_load_sub:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_sub_32>>
// Emits: (ATOMIC_LOAD_SUB_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_sub_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_load_sub_32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -2123,10 +2123,10 @@ SDNode *Select_ISD_ATOMIC_LOAD_SUB_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_SUB_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_sub_64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_SUB_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_sub_64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -2139,14 +2139,14 @@ SDNode *Select_ISD_ATOMIC_LOAD_SUB_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_XOR_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
+SDNode *Select_ISD_ATOMIC_LOAD_XOR_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
// Pattern: (atomic_load_xor:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_xor_8>>
// Emits: (ATOMIC_LOAD_XOR_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_xor_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_load_xor_8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -2158,8 +2158,8 @@ SDNode *Select_ISD_ATOMIC_LOAD_XOR_i32(const SDValue &N) {
// Pattern: (atomic_load_xor:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_xor_16>>
// Emits: (ATOMIC_LOAD_XOR_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_xor_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_load_xor_16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -2171,8 +2171,8 @@ SDNode *Select_ISD_ATOMIC_LOAD_XOR_i32(const SDValue &N) {
// Pattern: (atomic_load_xor:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)<<P:Predicate_atomic_load_xor_32>>
// Emits: (ATOMIC_LOAD_XOR_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$incr)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_load_xor_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_load_xor_32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -2185,10 +2185,10 @@ SDNode *Select_ISD_ATOMIC_LOAD_XOR_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_XOR_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_xor_64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_XOR_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_xor_64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -2201,14 +2201,14 @@ SDNode *Select_ISD_ATOMIC_LOAD_XOR_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_SWAP_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
+SDNode *Select_ISD_ATOMIC_SWAP_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
// Pattern: (atomic_swap:i32 xoaddr:iPTR:$ptr, GPRC:i32:$new)<<P:Predicate_atomic_swap_8>>
// Emits: (ATOMIC_SWAP_I8:i32 xoaddr:iPTR:$ptr, GPRC:i32:$new)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_swap_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_swap_8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -2220,8 +2220,8 @@ SDNode *Select_ISD_ATOMIC_SWAP_i32(const SDValue &N) {
// Pattern: (atomic_swap:i32 xoaddr:iPTR:$ptr, GPRC:i32:$new)<<P:Predicate_atomic_swap_16>>
// Emits: (ATOMIC_SWAP_I16:i32 xoaddr:iPTR:$ptr, GPRC:i32:$new)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_swap_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_swap_16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -2233,8 +2233,8 @@ SDNode *Select_ISD_ATOMIC_SWAP_i32(const SDValue &N) {
// Pattern: (atomic_swap:i32 xoaddr:iPTR:$ptr, GPRC:i32:$new)<<P:Predicate_atomic_swap_32>>
// Emits: (ATOMIC_SWAP_I32:i32 xoaddr:iPTR:$ptr, GPRC:i32:$new)
// Pattern complexity = 13 cost = 11 size = 0
- if (Predicate_atomic_swap_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_atomic_swap_32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -2247,10 +2247,10 @@ SDNode *Select_ISD_ATOMIC_SWAP_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_SWAP_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_swap_64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_SWAP_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_swap_64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -2263,13 +2263,13 @@ SDNode *Select_ISD_ATOMIC_SWAP_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_21(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- ReplaceUses(N, N0);
+DISABLE_INLINE SDNode *Emit_21(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ ReplaceUses(SDValue(N, 0), N0);
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v16i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_BIT_CONVERT_v16i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v16i8 VRRC:v8i16:$src)
// Emits: VRRC:v16i8:$src
@@ -2299,8 +2299,8 @@ SDNode *Select_ISD_BIT_CONVERT_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v8i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_BIT_CONVERT_v8i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v8i16 VRRC:v16i8:$src)
// Emits: VRRC:v8i16:$src
@@ -2330,8 +2330,8 @@ SDNode *Select_ISD_BIT_CONVERT_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v4i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_BIT_CONVERT_v4i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v4i32 VRRC:v16i8:$src)
// Emits: VRRC:v4i32:$src
@@ -2361,8 +2361,8 @@ SDNode *Select_ISD_BIT_CONVERT_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v4f32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_BIT_CONVERT_v4f32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v4f32 VRRC:v16i8:$src)
// Emits: VRRC:v4f32:$src
@@ -2392,15 +2392,15 @@ SDNode *Select_ISD_BIT_CONVERT_v4f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_22(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, N1, Chain);
+DISABLE_INLINE SDNode *Emit_22(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, N1, Chain);
}
-SDNode *Select_ISD_BR(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BasicBlock) {
+SDNode *Select_ISD_BR(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BasicBlock) {
SDNode *Result = Emit_22(N, PPC::B);
return Result;
}
@@ -2409,12 +2409,12 @@ SDNode *Select_ISD_BR(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_23(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp1 = Transform_VSPLTISB_get_imm(N.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1);
+DISABLE_INLINE SDNode *Emit_23(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp1 = Transform_VSPLTISB_get_imm(SDValue(N, 0).getNode());
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1);
}
-SDNode *Select_ISD_BUILD_VECTOR_v16i8(const SDValue &N) {
- if (Predicate_vecspltisb(N.getNode())) {
+SDNode *Select_ISD_BUILD_VECTOR_v16i8(SDNode *N) {
+ if (Predicate_vecspltisb(N)) {
SDNode *Result = Emit_23(N, PPC::VSPLTISB, MVT::v16i8);
return Result;
}
@@ -2423,12 +2423,12 @@ SDNode *Select_ISD_BUILD_VECTOR_v16i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_24(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp1 = Transform_VSPLTISH_get_imm(N.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1);
+DISABLE_INLINE SDNode *Emit_24(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp1 = Transform_VSPLTISH_get_imm(SDValue(N, 0).getNode());
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1);
}
-SDNode *Select_ISD_BUILD_VECTOR_v8i16(const SDValue &N) {
- if (Predicate_vecspltish(N.getNode())) {
+SDNode *Select_ISD_BUILD_VECTOR_v8i16(SDNode *N) {
+ if (Predicate_vecspltish(N)) {
SDNode *Result = Emit_24(N, PPC::VSPLTISH, MVT::v8i16);
return Result;
}
@@ -2437,19 +2437,19 @@ SDNode *Select_ISD_BUILD_VECTOR_v8i16(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_25(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Tmp1 = Transform_VSPLTISW_get_imm(N.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1);
+DISABLE_INLINE SDNode *Emit_25(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Tmp1 = Transform_VSPLTISW_get_imm(SDValue(N, 0).getNode());
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_26(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0);
+DISABLE_INLINE SDNode *Emit_26(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ return CurDAG->SelectNodeTo(N, Opc0, VT0);
}
-SDNode *Select_ISD_BUILD_VECTOR_v4i32(const SDValue &N) {
+SDNode *Select_ISD_BUILD_VECTOR_v4i32(SDNode *N) {
// Pattern: (build_vector:v4i32)<<P:Predicate_vecspltisw>><<X:VSPLTISW_get_imm>>:$SIMM
// Emits: (VSPLTISW:v4i32 (VSPLTISW_get_imm:i32 (build_vector:v4i32):$SIMM))
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_vecspltisw(N.getNode())) {
+ if (Predicate_vecspltisw(N)) {
SDNode *Result = Emit_25(N, PPC::VSPLTISW, MVT::v4i32);
return Result;
}
@@ -2457,7 +2457,7 @@ SDNode *Select_ISD_BUILD_VECTOR_v4i32(const SDValue &N) {
// Pattern: (build_vector:v4i32)<<P:Predicate_immAllZerosV>>
// Emits: (V_SET0:v4i32)
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_immAllZerosV(N.getNode())) {
+ if (Predicate_immAllZerosV(N)) {
SDNode *Result = Emit_26(N, PPC::V_SET0, MVT::v4i32);
return Result;
}
@@ -2466,22 +2466,22 @@ SDNode *Select_ISD_BUILD_VECTOR_v4i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_27(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_27(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
SDValue Ops0[] = { N1, N2, Chain, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 4 : 3);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 4 : 3);
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -2490,12 +2490,12 @@ DISABLE_INLINE SDNode *Emit_27(const SDValue &N, unsigned Opc0) {
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_ISD_CALLSEQ_END(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetConstant) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::TargetConstant) {
+SDNode *Select_ISD_CALLSEQ_END(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TargetConstant) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::TargetConstant) {
SDNode *Result = Emit_27(N, PPC::ADJCALLSTACKUP);
return Result;
}
@@ -2505,15 +2505,15 @@ SDNode *Select_ISD_CALLSEQ_END(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_28(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, N1, Chain);
+DISABLE_INLINE SDNode *Emit_28(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, N1, Chain);
Chain = SDValue(ResNode, 0);
SDValue InFlag(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -2522,10 +2522,10 @@ DISABLE_INLINE SDNode *Emit_28(const SDValue &N, unsigned Opc0) {
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_ISD_CALLSEQ_START(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetConstant) {
+SDNode *Select_ISD_CALLSEQ_START(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TargetConstant) {
SDNode *Result = Emit_28(N, PPC::ADJCALLSTACKDOWN);
return Result;
}
@@ -2534,42 +2534,42 @@ SDNode *Select_ISD_CALLSEQ_START(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_29(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0);
+DISABLE_INLINE SDNode *Emit_29(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0);
}
-SDNode *Select_ISD_CTLZ_i32(const SDValue &N) {
+SDNode *Select_ISD_CTLZ_i32(SDNode *N) {
SDNode *Result = Emit_29(N, PPC::CNTLZW, MVT::i32);
return Result;
}
-SDNode *Select_ISD_CTLZ_i64(const SDValue &N) {
+SDNode *Select_ISD_CTLZ_i64(SDNode *N) {
SDNode *Result = Emit_29(N, PPC::CNTLZD, MVT::i64);
return Result;
}
-DISABLE_INLINE SDNode *Emit_30(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_30(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp0);
}
-DISABLE_INLINE SDNode *Emit_31(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_31(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
SDValue Tmp1 = Transform_HI16(Tmp0.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_32(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+DISABLE_INLINE SDNode *Emit_32(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
SDValue Tmp1 = Transform_HI16(Tmp0.getNode());
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, Tmp1), 0);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, Tmp1), 0);
SDValue Tmp3 = Transform_LO16(Tmp0.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2, Tmp3);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2, Tmp3);
}
-SDNode *Select_ISD_Constant_i32(const SDValue &N) {
+SDNode *Select_ISD_Constant_i32(SDNode *N) {
// Pattern: (imm:i32)<<P:Predicate_immSExt16>>:$imm
// Emits: (LI:i32 (imm:i32):$imm)
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_immSExt16(N.getNode())) {
+ if (Predicate_immSExt16(N)) {
SDNode *Result = Emit_30(N, PPC::LI, MVT::i32);
return Result;
}
@@ -2577,7 +2577,7 @@ SDNode *Select_ISD_Constant_i32(const SDValue &N) {
// Pattern: (imm:i32)<<P:Predicate_imm16ShiftedSExt>><<X:HI16>>:$imm
// Emits: (LIS:i32 (HI16:i32 (imm:i32):$imm))
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_imm16ShiftedSExt(N.getNode())) {
+ if (Predicate_imm16ShiftedSExt(N)) {
SDNode *Result = Emit_31(N, PPC::LIS, MVT::i32);
return Result;
}
@@ -2589,21 +2589,21 @@ SDNode *Select_ISD_Constant_i32(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_33(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_33(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue Tmp0 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i64);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp0);
}
-DISABLE_INLINE SDNode *Emit_34(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_34(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue Tmp0 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i64);
SDValue Tmp1 = Transform_HI16(Tmp0.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1);
}
-SDNode *Select_ISD_Constant_i64(const SDValue &N) {
+SDNode *Select_ISD_Constant_i64(SDNode *N) {
// Pattern: (imm:i64)<<P:Predicate_immSExt16>>:$imm
// Emits: (LI8:i64 (imm:i64):$imm)
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_immSExt16(N.getNode())) {
+ if (Predicate_immSExt16(N)) {
SDNode *Result = Emit_33(N, PPC::LI8, MVT::i64);
return Result;
}
@@ -2611,7 +2611,7 @@ SDNode *Select_ISD_Constant_i64(const SDValue &N) {
// Pattern: (imm:i64)<<P:Predicate_imm16ShiftedSExt>><<X:HI16>>:$imm
// Emits: (LIS8:i64 (HI16:i64 (imm:i64):$imm))
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_imm16ShiftedSExt(N.getNode())) {
+ if (Predicate_imm16ShiftedSExt(N)) {
SDNode *Result = Emit_34(N, PPC::LIS8, MVT::i64);
return Result;
}
@@ -2620,38 +2620,38 @@ SDNode *Select_ISD_Constant_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FABS_f32(const SDValue &N) {
+SDNode *Select_ISD_FABS_f32(SDNode *N) {
SDNode *Result = Emit_29(N, PPC::FABSS, MVT::f32);
return Result;
}
-SDNode *Select_ISD_FABS_f64(const SDValue &N) {
+SDNode *Select_ISD_FABS_f64(SDNode *N) {
SDNode *Result = Emit_29(N, PPC::FABSD, MVT::f64);
return Result;
}
-DISABLE_INLINE SDNode *Emit_35(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N01, N1);
+DISABLE_INLINE SDNode *Emit_35(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, N01, N1);
}
-DISABLE_INLINE SDNode *Emit_36(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N11, N0);
+DISABLE_INLINE SDNode *Emit_36(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N10, N11, N0);
}
-SDNode *Select_ISD_FADD_f32(const SDValue &N) {
+SDNode *Select_ISD_FADD_f32(SDNode *N) {
if ((!NoExcessFPPrecision)) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fadd:f32 (fmul:f32 F4RC:f32:$FRA, F4RC:f32:$FRC), F4RC:f32:$FRB)
// Emits: (FMADDS:f32 F4RC:f32:$FRA, F4RC:f32:$FRC, F4RC:f32:$FRB)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_35(N, PPC::FMADDS, MVT::f32);
return Result;
}
@@ -2659,8 +2659,8 @@ SDNode *Select_ISD_FADD_f32(const SDValue &N) {
// Pattern: (fadd:f32 F4RC:f32:$FRB, (fmul:f32 F4RC:f32:$FRA, F4RC:f32:$FRC))
// Emits: (FMADDS:f32 F4RC:f32:$FRA, F4RC:f32:$FRC, F4RC:f32:$FRB)
// Pattern complexity = 6 cost = 1 size = 0
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FMUL) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_36(N, PPC::FMADDS, MVT::f32);
return Result;
}
@@ -2673,14 +2673,14 @@ SDNode *Select_ISD_FADD_f32(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_FADD_f64(const SDValue &N) {
+SDNode *Select_ISD_FADD_f64(SDNode *N) {
if ((!NoExcessFPPrecision)) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fadd:f64 (fmul:f64 F8RC:f64:$FRA, F8RC:f64:$FRC), F8RC:f64:$FRB)
// Emits: (FMADD:f64 F8RC:f64:$FRA, F8RC:f64:$FRC, F8RC:f64:$FRB)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_35(N, PPC::FMADD, MVT::f64);
return Result;
}
@@ -2688,8 +2688,8 @@ SDNode *Select_ISD_FADD_f64(const SDValue &N) {
// Pattern: (fadd:f64 F8RC:f64:$FRB, (fmul:f64 F8RC:f64:$FRA, F8RC:f64:$FRC))
// Emits: (FMADD:f64 F8RC:f64:$FRA, F8RC:f64:$FRC, F8RC:f64:$FRB)
// Pattern complexity = 6 cost = 1 size = 0
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FMUL) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_36(N, PPC::FMADD, MVT::f64);
return Result;
}
@@ -2702,14 +2702,14 @@ SDNode *Select_ISD_FADD_f64(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_FADD_v4f32(const SDValue &N) {
+SDNode *Select_ISD_FADD_v4f32(SDNode *N) {
if ((!NoExcessFPPrecision)) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fadd:v4f32 (fmul:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vC), VRRC:v4f32:$vB)
// Emits: (VMADDFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vC, VRRC:v4f32:$vB)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_35(N, PPC::VMADDFP, MVT::v4f32);
return Result;
}
@@ -2717,8 +2717,8 @@ SDNode *Select_ISD_FADD_v4f32(const SDValue &N) {
// Pattern: (fadd:v4f32 VRRC:v4f32:$vB, (fmul:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vC))
// Emits: (VMADDFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vC, VRRC:v4f32:$vB)
// Pattern complexity = 6 cost = 1 size = 0
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FMUL) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_36(N, PPC::VMADDFP, MVT::v4f32);
return Result;
}
@@ -2731,68 +2731,68 @@ SDNode *Select_ISD_FADD_v4f32(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_FDIV_f32(const SDValue &N) {
+SDNode *Select_ISD_FDIV_f32(SDNode *N) {
SDNode *Result = Emit_3(N, PPC::FDIVS, MVT::f32);
return Result;
}
-SDNode *Select_ISD_FDIV_f64(const SDValue &N) {
+SDNode *Select_ISD_FDIV_f64(SDNode *N) {
SDNode *Result = Emit_3(N, PPC::FDIV, MVT::f64);
return Result;
}
-SDNode *Select_ISD_FMUL_f32(const SDValue &N) {
+SDNode *Select_ISD_FMUL_f32(SDNode *N) {
SDNode *Result = Emit_3(N, PPC::FMULS, MVT::f32);
return Result;
}
-SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
+SDNode *Select_ISD_FMUL_f64(SDNode *N) {
SDNode *Result = Emit_3(N, PPC::FMUL, MVT::f64);
return Result;
}
-DISABLE_INLINE SDNode *Emit_37(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, N0, N1, Tmp2);
+DISABLE_INLINE SDNode *Emit_37(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, N0, N1, Tmp2);
}
-SDNode *Select_ISD_FMUL_v4f32(const SDValue &N) {
+SDNode *Select_ISD_FMUL_v4f32(SDNode *N) {
SDNode *Result = Emit_37(N, PPC::V_SET0, PPC::VMADDFP, MVT::v4i32, MVT::v4f32);
return Result;
}
-DISABLE_INLINE SDNode *Emit_38(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00);
-}
-DISABLE_INLINE SDNode *Emit_39(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N000, N001, N01);
-}
-DISABLE_INLINE SDNode *Emit_40(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N010, N011, N00);
-}
-SDNode *Select_ISD_FNEG_f32(const SDValue &N) {
+DISABLE_INLINE SDNode *Emit_38(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N00);
+}
+DISABLE_INLINE SDNode *Emit_39(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N000, N001, N01);
+}
+DISABLE_INLINE SDNode *Emit_40(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N010, N011, N00);
+}
+SDNode *Select_ISD_FNEG_f32(SDNode *N) {
if ((!NoExcessFPPrecision)) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fneg:f32 (fadd:f32 (fmul:f32 F4RC:f32:$FRA, F4RC:f32:$FRC), F4RC:f32:$FRB))
// Emits: (FNMADDS:f32 F4RC:f32:$FRA, F4RC:f32:$FRC, F4RC:f32:$FRB)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FADD) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FADD) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_39(N, PPC::FNMADDS, MVT::f32);
return Result;
}
@@ -2801,9 +2801,9 @@ SDNode *Select_ISD_FNEG_f32(const SDValue &N) {
// Pattern: (fneg:f32 (fsub:f32 (fmul:f32 F4RC:f32:$FRA, F4RC:f32:$FRC), F4RC:f32:$FRB))
// Emits: (FNMSUBS:f32 F4RC:f32:$FRA, F4RC:f32:$FRC, F4RC:f32:$FRB)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FSUB) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FSUB) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_39(N, PPC::FNMSUBS, MVT::f32);
return Result;
}
@@ -2812,10 +2812,10 @@ SDNode *Select_ISD_FNEG_f32(const SDValue &N) {
// Pattern: (fneg:f32 (fadd:f32 F4RC:f32:$FRB, (fmul:f32 F4RC:f32:$FRA, F4RC:f32:$FRC)))
// Emits: (FNMADDS:f32 F4RC:f32:$FRA, F4RC:f32:$FRC, F4RC:f32:$FRB)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FADD) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FADD) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_40(N, PPC::FNMADDS, MVT::f32);
return Result;
}
@@ -2826,8 +2826,8 @@ SDNode *Select_ISD_FNEG_f32(const SDValue &N) {
// Emits: (FNABSS:f32 F4RC:f32:$frB)
// Pattern complexity = 6 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::FABS) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::FABS) {
SDNode *Result = Emit_38(N, PPC::FNABSS, MVT::f32);
return Result;
}
@@ -2840,16 +2840,16 @@ SDNode *Select_ISD_FNEG_f32(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_FNEG_f64(const SDValue &N) {
+SDNode *Select_ISD_FNEG_f64(SDNode *N) {
if ((!NoExcessFPPrecision)) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fneg:f64 (fadd:f64 (fmul:f64 F8RC:f64:$FRA, F8RC:f64:$FRC), F8RC:f64:$FRB))
// Emits: (FNMADD:f64 F8RC:f64:$FRA, F8RC:f64:$FRC, F8RC:f64:$FRB)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FADD) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FADD) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_39(N, PPC::FNMADD, MVT::f64);
return Result;
}
@@ -2858,9 +2858,9 @@ SDNode *Select_ISD_FNEG_f64(const SDValue &N) {
// Pattern: (fneg:f64 (fsub:f64 (fmul:f64 F8RC:f64:$FRA, F8RC:f64:$FRC), F8RC:f64:$FRB))
// Emits: (FNMSUB:f64 F8RC:f64:$FRA, F8RC:f64:$FRC, F8RC:f64:$FRB)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FSUB) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FSUB) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_39(N, PPC::FNMSUB, MVT::f64);
return Result;
}
@@ -2869,10 +2869,10 @@ SDNode *Select_ISD_FNEG_f64(const SDValue &N) {
// Pattern: (fneg:f64 (fadd:f64 F8RC:f64:$FRB, (fmul:f64 F8RC:f64:$FRA, F8RC:f64:$FRC)))
// Emits: (FNMADD:f64 F8RC:f64:$FRA, F8RC:f64:$FRC, F8RC:f64:$FRB)
// Pattern complexity = 9 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FADD) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FADD) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_40(N, PPC::FNMADD, MVT::f64);
return Result;
}
@@ -2883,8 +2883,8 @@ SDNode *Select_ISD_FNEG_f64(const SDValue &N) {
// Emits: (FNABSD:f64 F8RC:f64:$frB)
// Pattern complexity = 6 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::FABS) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::FABS) {
SDNode *Result = Emit_38(N, PPC::FNABSD, MVT::f64);
return Result;
}
@@ -2897,8 +2897,8 @@ SDNode *Select_ISD_FNEG_f64(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_FP_EXTEND_f64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_FP_EXTEND_f64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
SDNode *Result = Emit_29(N, PPC::FMRSD, MVT::f64);
return Result;
@@ -2908,8 +2908,8 @@ SDNode *Select_ISD_FP_EXTEND_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FP_ROUND_f32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_FP_ROUND_f32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f64) {
SDNode *Result = Emit_29(N, PPC::FRSP, MVT::f32);
return Result;
@@ -2919,24 +2919,24 @@ SDNode *Select_ISD_FP_ROUND_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FSQRT_f32(const SDValue &N) {
+SDNode *Select_ISD_FSQRT_f32(SDNode *N) {
SDNode *Result = Emit_29(N, PPC::FSQRTS, MVT::f32);
return Result;
}
-SDNode *Select_ISD_FSQRT_f64(const SDValue &N) {
+SDNode *Select_ISD_FSQRT_f64(SDNode *N) {
SDNode *Result = Emit_29(N, PPC::FSQRT, MVT::f64);
return Result;
}
-SDNode *Select_ISD_FSUB_f32(const SDValue &N) {
+SDNode *Select_ISD_FSUB_f32(SDNode *N) {
if ((!NoExcessFPPrecision)) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fsub:f32 (fmul:f32 F4RC:f32:$FRA, F4RC:f32:$FRC), F4RC:f32:$FRB)
// Emits: (FMSUBS:f32 F4RC:f32:$FRA, F4RC:f32:$FRC, F4RC:f32:$FRB)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_35(N, PPC::FMSUBS, MVT::f32);
return Result;
}
@@ -2944,8 +2944,8 @@ SDNode *Select_ISD_FSUB_f32(const SDValue &N) {
// Pattern: (fsub:f32 F4RC:f32:$B, (fmul:f32 F4RC:f32:$A, F4RC:f32:$C))
// Emits: (FNMSUBS:f32 F4RC:f32:$A, F4RC:f32:$C, F4RC:f32:$B)
// Pattern complexity = 6 cost = 1 size = 0
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FMUL) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_36(N, PPC::FNMSUBS, MVT::f32);
return Result;
}
@@ -2958,14 +2958,14 @@ SDNode *Select_ISD_FSUB_f32(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
+SDNode *Select_ISD_FSUB_f64(SDNode *N) {
if ((!NoExcessFPPrecision)) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fsub:f64 (fmul:f64 F8RC:f64:$FRA, F8RC:f64:$FRC), F8RC:f64:$FRB)
// Emits: (FMSUB:f64 F8RC:f64:$FRA, F8RC:f64:$FRC, F8RC:f64:$FRB)
// Pattern complexity = 6 cost = 1 size = 0
- if (N0.getOpcode() == ISD::FMUL) {
+ if (N0.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_35(N, PPC::FMSUB, MVT::f64);
return Result;
}
@@ -2973,8 +2973,8 @@ SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
// Pattern: (fsub:f64 F8RC:f64:$B, (fmul:f64 F8RC:f64:$A, F8RC:f64:$C))
// Emits: (FNMSUB:f64 F8RC:f64:$A, F8RC:f64:$C, F8RC:f64:$B)
// Pattern complexity = 6 cost = 1 size = 0
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FMUL) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_36(N, PPC::FNMSUB, MVT::f64);
return Result;
}
@@ -2987,28 +2987,28 @@ SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_41(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N100, N101, N11);
+DISABLE_INLINE SDNode *Emit_41(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N100, N101, N11);
}
-SDNode *Select_ISD_FSUB_v4f32(const SDValue &N) {
+SDNode *Select_ISD_FSUB_v4f32(SDNode *N) {
// Pattern: (fsub:v4f32 (build_vector:v4f32)<<P:Predicate_V_immneg0>>, (fsub:v4f32 (fmul:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vC), VRRC:v4f32:$vB))
// Emits: (VNMSUBFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vC, VRRC:v4f32:$vB)
// Pattern complexity = 13 cost = 1 size = 0
if ((!NoExcessFPPrecision)) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_V_immneg0(N0.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::FSUB) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::FMUL) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::FSUB) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::FMUL) {
SDNode *Result = Emit_41(N, PPC::VNMSUBFP, MVT::v4f32);
return Result;
}
@@ -3023,86 +3023,86 @@ SDNode *Select_ISD_FSUB_v4f32(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_42(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, CPTmpN2_0, CPTmpN2_1, Chain);
-}
-DISABLE_INLINE SDNode *Emit_43(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain);
-}
-DISABLE_INLINE SDNode *Emit_44(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, N2, Chain);
-}
-DISABLE_INLINE SDNode *Emit_45(const SDValue &N, unsigned Opc0, SDValue &CPTmpN3_0, SDValue &CPTmpN3_1) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_42(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, CPTmpN2_0, CPTmpN2_1, Chain);
+}
+DISABLE_INLINE SDNode *Emit_43(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Chain);
+}
+DISABLE_INLINE SDNode *Emit_44(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, N2, Chain);
+}
+DISABLE_INLINE SDNode *Emit_45(SDNode *N, unsigned Opc0, SDValue &CPTmpN3_0, SDValue &CPTmpN3_1) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue Ops0[] = { N2, CPTmpN3_0, CPTmpN3_1, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_46(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_46(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
SDValue Tmp4 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
SDValue Tmp5 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
SDValue Ops0[] = { Tmp2, Tmp3, Tmp4, Tmp5, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 5);
}
-DISABLE_INLINE SDNode *Emit_47(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_47(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
SDValue Tmp4 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
SDValue Tmp5 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
SDValue Ops0[] = { Tmp2, Tmp3, Tmp4, Tmp5, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_48(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_48(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N4)->getZExtValue()), MVT::i32);
SDValue Ops0[] = { Tmp2, Tmp3, N2, N3, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 5);
-}
-DISABLE_INLINE SDNode *Emit_49(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 5);
+}
+DISABLE_INLINE SDNode *Emit_49(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
SDValue Tmp2 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N4)->getZExtValue()), MVT::i32);
SDValue Ops0[] = { Tmp2, Tmp3, N2, N3, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 5);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 5);
}
-SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_void:isVoid 339:iPTR, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 335:iPTR, xoaddr:iPTR:$dst)
// Emits: (DCBA:isVoid xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(339)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(335)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
@@ -3111,11 +3111,11 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
}
}
- // Pattern: (intrinsic_void:isVoid 340:iPTR, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 336:iPTR, xoaddr:iPTR:$dst)
// Emits: (DCBF:isVoid xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(340)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(336)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
@@ -3124,11 +3124,11 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
}
}
- // Pattern: (intrinsic_void:isVoid 341:iPTR, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 337:iPTR, xoaddr:iPTR:$dst)
// Emits: (DCBI:isVoid xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(341)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(337)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
@@ -3137,11 +3137,11 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
}
}
- // Pattern: (intrinsic_void:isVoid 342:iPTR, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 338:iPTR, xoaddr:iPTR:$dst)
// Emits: (DCBST:isVoid xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(342)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(338)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
@@ -3150,11 +3150,11 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
}
}
- // Pattern: (intrinsic_void:isVoid 343:iPTR, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 339:iPTR, xoaddr:iPTR:$dst)
// Emits: (DCBT:isVoid xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(343)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(339)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
@@ -3163,11 +3163,11 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
}
}
- // Pattern: (intrinsic_void:isVoid 344:iPTR, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 340:iPTR, xoaddr:iPTR:$dst)
// Emits: (DCBTST:isVoid xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(344)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(340)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
@@ -3176,11 +3176,11 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
}
}
- // Pattern: (intrinsic_void:isVoid 345:iPTR, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 341:iPTR, xoaddr:iPTR:$dst)
// Emits: (DCBZ:isVoid xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(345)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(341)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
@@ -3189,11 +3189,11 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
}
}
- // Pattern: (intrinsic_void:isVoid 346:iPTR, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 342:iPTR, xoaddr:iPTR:$dst)
// Emits: (DCBZL:isVoid xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(346)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(342)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
@@ -3202,12 +3202,12 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
}
}
- // Pattern: (intrinsic_void:isVoid 207:iPTR, VRRC:v16i8:$rS, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 203:iPTR, VRRC:v16i8:$rS, xoaddr:iPTR:$dst)
// Emits: (STVEBX:isVoid VRRC:v16i8:$rS, xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(207)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (CN1 == INT64_C(203)) {
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
SDValue CPTmpN3_1;
if (SelectAddrIdxOnly(N, N3, CPTmpN3_0, CPTmpN3_1)) {
@@ -3216,12 +3216,12 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
}
}
- // Pattern: (intrinsic_void:isVoid 208:iPTR, VRRC:v8i16:$rS, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 204:iPTR, VRRC:v8i16:$rS, xoaddr:iPTR:$dst)
// Emits: (STVEHX:isVoid VRRC:v8i16:$rS, xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(208)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (CN1 == INT64_C(204)) {
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
SDValue CPTmpN3_1;
if (SelectAddrIdxOnly(N, N3, CPTmpN3_0, CPTmpN3_1)) {
@@ -3230,12 +3230,12 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
}
}
- // Pattern: (intrinsic_void:isVoid 209:iPTR, VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 205:iPTR, VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
// Emits: (STVEWX:isVoid VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(209)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (CN1 == INT64_C(205)) {
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
SDValue CPTmpN3_1;
if (SelectAddrIdxOnly(N, N3, CPTmpN3_0, CPTmpN3_1)) {
@@ -3244,12 +3244,12 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
}
}
- // Pattern: (intrinsic_void:isVoid 210:iPTR, VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 206:iPTR, VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
// Emits: (STVX:isVoid VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(210)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (CN1 == INT64_C(206)) {
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
SDValue CPTmpN3_1;
if (SelectAddrIdxOnly(N, N3, CPTmpN3_0, CPTmpN3_1)) {
@@ -3258,12 +3258,12 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
}
}
- // Pattern: (intrinsic_void:isVoid 211:iPTR, VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 207:iPTR, VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
// Emits: (STVXL:isVoid VRRC:v4i32:$rS, xoaddr:iPTR:$dst)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(211)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (CN1 == INT64_C(207)) {
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
SDValue CPTmpN3_1;
if (SelectAddrIdxOnly(N, N3, CPTmpN3_0, CPTmpN3_1)) {
@@ -3272,149 +3272,149 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
}
}
- // Pattern: (intrinsic_void:isVoid 192:iPTR, (imm:i32):$STRM)
+ // Pattern: (intrinsic_void:isVoid 188:iPTR, (imm:i32):$STRM)
// Emits: (DSS:isVoid 0:i32, (imm:i32):$STRM, 0:i32, 0:i32)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(192)) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ if (CN1 == INT64_C(188)) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_47(N, PPC::DSS);
return Result;
}
}
- // Pattern: (intrinsic_void:isVoid 194:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Pattern: (intrinsic_void:isVoid 190:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
// Emits: (DST:isVoid 0:i32, (imm:i32):$STRM, GPRC:i32:$rA, GPRC:i32:$rB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(194)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- if (N4.getOpcode() == ISD::Constant &&
+ if (CN1 == INT64_C(190)) {
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ if (N4.getNode()->getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i32) {
SDNode *Result = Emit_48(N, PPC::DST);
return Result;
}
}
- // Pattern: (intrinsic_void:isVoid 197:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Pattern: (intrinsic_void:isVoid 193:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
// Emits: (DSTT:isVoid 1:i32, (imm:i32):$STRM, GPRC:i32:$rA, GPRC:i32:$rB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(197)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- if (N4.getOpcode() == ISD::Constant &&
+ if (CN1 == INT64_C(193)) {
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ if (N4.getNode()->getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i32) {
SDNode *Result = Emit_49(N, PPC::DSTT);
return Result;
}
}
- // Pattern: (intrinsic_void:isVoid 195:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Pattern: (intrinsic_void:isVoid 191:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
// Emits: (DSTST:isVoid 0:i32, (imm:i32):$STRM, GPRC:i32:$rA, GPRC:i32:$rB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(195)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- if (N4.getOpcode() == ISD::Constant &&
+ if (CN1 == INT64_C(191)) {
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ if (N4.getNode()->getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i32) {
SDNode *Result = Emit_48(N, PPC::DSTST);
return Result;
}
}
- // Pattern: (intrinsic_void:isVoid 196:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Pattern: (intrinsic_void:isVoid 192:iPTR, GPRC:i32:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
// Emits: (DSTSTT:isVoid 1:i32, (imm:i32):$STRM, GPRC:i32:$rA, GPRC:i32:$rB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(196)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- if (N4.getOpcode() == ISD::Constant &&
+ if (CN1 == INT64_C(192)) {
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ if (N4.getNode()->getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i32) {
SDNode *Result = Emit_49(N, PPC::DSTSTT);
return Result;
}
}
- // Pattern: (intrinsic_void:isVoid 194:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Pattern: (intrinsic_void:isVoid 190:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
// Emits: (DST64:isVoid 0:i32, (imm:i32):$STRM, G8RC:i64:$rA, GPRC:i32:$rB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(194)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- if (N4.getOpcode() == ISD::Constant &&
+ if (CN1 == INT64_C(190)) {
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ if (N4.getNode()->getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i64) {
SDNode *Result = Emit_48(N, PPC::DST64);
return Result;
}
}
- // Pattern: (intrinsic_void:isVoid 197:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Pattern: (intrinsic_void:isVoid 193:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
// Emits: (DSTT64:isVoid 1:i32, (imm:i32):$STRM, G8RC:i64:$rA, GPRC:i32:$rB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(197)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- if (N4.getOpcode() == ISD::Constant &&
+ if (CN1 == INT64_C(193)) {
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ if (N4.getNode()->getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i64) {
SDNode *Result = Emit_49(N, PPC::DSTT64);
return Result;
}
}
- // Pattern: (intrinsic_void:isVoid 195:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Pattern: (intrinsic_void:isVoid 191:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
// Emits: (DSTST64:isVoid 0:i32, (imm:i32):$STRM, G8RC:i64:$rA, GPRC:i32:$rB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(195)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- if (N4.getOpcode() == ISD::Constant &&
+ if (CN1 == INT64_C(191)) {
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ if (N4.getNode()->getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i64) {
SDNode *Result = Emit_48(N, PPC::DSTST64);
return Result;
}
}
- // Pattern: (intrinsic_void:isVoid 196:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
+ // Pattern: (intrinsic_void:isVoid 192:iPTR, G8RC:i64:$rA, GPRC:i32:$rB, (imm:i32):$STRM)
// Emits: (DSTSTT64:isVoid 1:i32, (imm:i32):$STRM, G8RC:i64:$rA, GPRC:i32:$rB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(196)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- if (N4.getOpcode() == ISD::Constant &&
+ if (CN1 == INT64_C(192)) {
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ if (N4.getNode()->getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i64) {
SDNode *Result = Emit_49(N, PPC::DSTSTT64);
return Result;
}
}
- // Pattern: (intrinsic_void:isVoid 347:iPTR)
+ // Pattern: (intrinsic_void:isVoid 343:iPTR)
// Emits: (SYNC:isVoid)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(347)) {
+ if (CN1 == INT64_C(343)) {
SDNode *Result = Emit_43(N, PPC::SYNC);
return Result;
}
- // Pattern: (intrinsic_void:isVoid 206:iPTR, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_void:isVoid 202:iPTR, VRRC:v4i32:$vB)
// Emits: (MTVSCR:isVoid VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(206)) {
+ if (CN1 == INT64_C(202)) {
SDNode *Result = Emit_44(N, PPC::MTVSCR);
return Result;
}
- // Pattern: (intrinsic_void:isVoid 193:iPTR)
+ // Pattern: (intrinsic_void:isVoid 189:iPTR)
// Emits: (DSSALL:isVoid 1:i32, 0:i32, 0:i32, 0:i32)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(193)) {
+ if (CN1 == INT64_C(189)) {
SDNode *Result = Emit_46(N, PPC::DSSALL);
return Result;
}
@@ -3424,28 +3424,28 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_50(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, CPTmpN1_0, CPTmpN1_1);
+DISABLE_INLINE SDNode *Emit_50(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, CPTmpN1_0, CPTmpN1_1);
}
-DISABLE_INLINE SDNode *Emit_51(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N2);
+DISABLE_INLINE SDNode *Emit_51(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N2);
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 201:iPTR, xoaddr:iPTR:$src)
+ // Pattern: (intrinsic_wo_chain:v16i8 197:iPTR, xoaddr:iPTR:$src)
// Emits: (LVSL:v16i8 xoaddr:iPTR:$src)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(201)) {
- SDValue N1 = N.getOperand(1);
+ if (CN1 == INT64_C(197)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -3454,11 +3454,11 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 202:iPTR, xoaddr:iPTR:$src)
+ // Pattern: (intrinsic_wo_chain:v16i8 198:iPTR, xoaddr:iPTR:$src)
// Emits: (LVSR:v16i8 xoaddr:iPTR:$src)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(202)) {
- SDValue N1 = N.getOperand(1);
+ if (CN1 == INT64_C(198)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -3467,146 +3467,146 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 213:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 209:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VADDSBS:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(213)) {
+ if (CN1 == INT64_C(209)) {
SDNode *Result = Emit_51(N, PPC::VADDSBS, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 216:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 212:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VADDUBS:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(216)) {
+ if (CN1 == INT64_C(212)) {
SDNode *Result = Emit_51(N, PPC::VADDUBS, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 219:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 215:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VAVGSB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(219)) {
+ if (CN1 == INT64_C(215)) {
SDNode *Result = Emit_51(N, PPC::VAVGSB, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 222:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 218:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VAVGUB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(222)) {
+ if (CN1 == INT64_C(218)) {
SDNode *Result = Emit_51(N, PPC::VAVGUB, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 259:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 255:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VMAXSB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(259)) {
+ if (CN1 == INT64_C(255)) {
SDNode *Result = Emit_51(N, PPC::VMAXSB, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 262:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 258:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VMAXUB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(262)) {
+ if (CN1 == INT64_C(258)) {
SDNode *Result = Emit_51(N, PPC::VMAXUB, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 268:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 264:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VMINSB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(268)) {
+ if (CN1 == INT64_C(264)) {
SDNode *Result = Emit_51(N, PPC::VMINSB, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 271:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 267:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VMINUB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(271)) {
+ if (CN1 == INT64_C(267)) {
SDNode *Result = Emit_51(N, PPC::VMINUB, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 322:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 318:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VSUBSBS:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(322)) {
+ if (CN1 == INT64_C(318)) {
SDNode *Result = Emit_51(N, PPC::VSUBSBS, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 325:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 321:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VSUBUBS:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(325)) {
+ if (CN1 == INT64_C(321)) {
SDNode *Result = Emit_51(N, PPC::VSUBUBS, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 303:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 299:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VRLB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(303)) {
+ if (CN1 == INT64_C(299)) {
SDNode *Result = Emit_51(N, PPC::VRLB, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 309:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 305:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VSLB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(309)) {
+ if (CN1 == INT64_C(305)) {
SDNode *Result = Emit_51(N, PPC::VSLB, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 314:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 310:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VSRAB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(314)) {
+ if (CN1 == INT64_C(310)) {
SDNode *Result = Emit_51(N, PPC::VSRAB, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 317:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 313:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VSRB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(317)) {
+ if (CN1 == INT64_C(313)) {
SDNode *Result = Emit_51(N, PPC::VSRB, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 292:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 288:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VPKSHSS:v16i8 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(292)) {
+ if (CN1 == INT64_C(288)) {
SDNode *Result = Emit_51(N, PPC::VPKSHSS, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 293:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 289:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VPKSHUS:v16i8 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(293)) {
+ if (CN1 == INT64_C(289)) {
SDNode *Result = Emit_51(N, PPC::VPKSHUS, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 294:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 290:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VPKSWSS:v16i8 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(294)) {
+ if (CN1 == INT64_C(290)) {
SDNode *Result = Emit_51(N, PPC::VPKSWSS, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 296:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v16i8 292:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VPKUHUS:v16i8 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(296)) {
+ if (CN1 == INT64_C(292)) {
SDNode *Result = Emit_51(N, PPC::VPKUHUS, MVT::v16i8);
return Result;
}
@@ -3616,228 +3616,228 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_52(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N2, N3);
+DISABLE_INLINE SDNode *Emit_52(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N2, N3);
}
-DISABLE_INLINE SDNode *Emit_53(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1);
+DISABLE_INLINE SDNode *Emit_53(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1);
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 265:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
+ // Pattern: (intrinsic_wo_chain:v8i16 261:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
// Emits: (VMHADDSHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(265)) {
+ if (CN1 == INT64_C(261)) {
SDNode *Result = Emit_52(N, PPC::VMHADDSHS, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 266:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
+ // Pattern: (intrinsic_wo_chain:v8i16 262:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
// Emits: (VMHRADDSHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(266)) {
+ if (CN1 == INT64_C(262)) {
SDNode *Result = Emit_52(N, PPC::VMHRADDSHS, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 274:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
+ // Pattern: (intrinsic_wo_chain:v8i16 270:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
// Emits: (VMLADDUHM:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v8i16:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(274)) {
+ if (CN1 == INT64_C(270)) {
SDNode *Result = Emit_52(N, PPC::VMLADDUHM, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 214:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 210:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VADDSHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(214)) {
+ if (CN1 == INT64_C(210)) {
SDNode *Result = Emit_51(N, PPC::VADDSHS, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 217:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 213:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VADDUHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(217)) {
+ if (CN1 == INT64_C(213)) {
SDNode *Result = Emit_51(N, PPC::VADDUHS, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 220:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 216:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VAVGSH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(220)) {
+ if (CN1 == INT64_C(216)) {
SDNode *Result = Emit_51(N, PPC::VAVGSH, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 223:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 219:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VAVGUH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(223)) {
+ if (CN1 == INT64_C(219)) {
SDNode *Result = Emit_51(N, PPC::VAVGUH, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 260:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 256:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VMAXSH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(260)) {
+ if (CN1 == INT64_C(256)) {
SDNode *Result = Emit_51(N, PPC::VMAXSH, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 263:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 259:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VMAXUH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(263)) {
+ if (CN1 == INT64_C(259)) {
SDNode *Result = Emit_51(N, PPC::VMAXUH, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 269:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 265:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VMINSH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(269)) {
+ if (CN1 == INT64_C(265)) {
SDNode *Result = Emit_51(N, PPC::VMINSH, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 272:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 268:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VMINUH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(272)) {
+ if (CN1 == INT64_C(268)) {
SDNode *Result = Emit_51(N, PPC::VMINUH, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 281:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 277:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VMULESB:v8i16 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(281)) {
+ if (CN1 == INT64_C(277)) {
SDNode *Result = Emit_51(N, PPC::VMULESB, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 283:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 279:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VMULEUB:v8i16 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(283)) {
+ if (CN1 == INT64_C(279)) {
SDNode *Result = Emit_51(N, PPC::VMULEUB, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 285:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 281:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VMULOSB:v8i16 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(285)) {
+ if (CN1 == INT64_C(281)) {
SDNode *Result = Emit_51(N, PPC::VMULOSB, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 287:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 283:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Emits: (VMULOUB:v8i16 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(287)) {
+ if (CN1 == INT64_C(283)) {
SDNode *Result = Emit_51(N, PPC::VMULOUB, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 323:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 319:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VSUBSHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(323)) {
+ if (CN1 == INT64_C(319)) {
SDNode *Result = Emit_51(N, PPC::VSUBSHS, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 326:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 322:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VSUBUHS:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(326)) {
+ if (CN1 == INT64_C(322)) {
SDNode *Result = Emit_51(N, PPC::VSUBUHS, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 304:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 300:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VRLH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(304)) {
+ if (CN1 == INT64_C(300)) {
SDNode *Result = Emit_51(N, PPC::VRLH, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 310:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 306:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VSLH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(310)) {
+ if (CN1 == INT64_C(306)) {
SDNode *Result = Emit_51(N, PPC::VSLH, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 315:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 311:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VSRAH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(315)) {
+ if (CN1 == INT64_C(311)) {
SDNode *Result = Emit_51(N, PPC::VSRAH, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 318:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 314:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VSRH:v8i16 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(318)) {
+ if (CN1 == INT64_C(314)) {
SDNode *Result = Emit_51(N, PPC::VSRH, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 291:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 287:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VPKPX:v8i16 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(291)) {
+ if (CN1 == INT64_C(287)) {
SDNode *Result = Emit_51(N, PPC::VPKPX, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 295:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 291:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VPKSWUS:v8i16 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(295)) {
+ if (CN1 == INT64_C(291)) {
SDNode *Result = Emit_51(N, PPC::VPKSWUS, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 297:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 293:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VPKUWUS:v8i16 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(297)) {
+ if (CN1 == INT64_C(293)) {
SDNode *Result = Emit_51(N, PPC::VPKUWUS, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 334:iPTR, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 330:iPTR, VRRC:v16i8:$vB)
// Emits: (VUPKHSB:v8i16 VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(334)) {
+ if (CN1 == INT64_C(330)) {
SDNode *Result = Emit_53(N, PPC::VUPKHSB, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 337:iPTR, VRRC:v16i8:$vB)
+ // Pattern: (intrinsic_wo_chain:v8i16 333:iPTR, VRRC:v16i8:$vB)
// Emits: (VUPKLSB:v8i16 VRRC:v16i8:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(337)) {
+ if (CN1 == INT64_C(333)) {
SDNode *Result = Emit_53(N, PPC::VUPKLSB, MVT::v8i16);
return Result;
}
@@ -3847,367 +3847,367 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_54(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_54(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp2, N1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp2, N1);
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i32 253:iPTR, VRRC:v4f32:$vB, (imm:i32):$UIMM)
+ // Pattern: (intrinsic_wo_chain:v4i32 249:iPTR, VRRC:v4f32:$vB, (imm:i32):$UIMM)
// Emits: (VCTSXS:v4i32 (imm:i32):$UIMM, VRRC:v4f32:$vB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(253)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ if (CN1 == INT64_C(249)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_54(N, PPC::VCTSXS, MVT::v4i32);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 254:iPTR, VRRC:v4f32:$vB, (imm:i32):$UIMM)
+ // Pattern: (intrinsic_wo_chain:v4i32 250:iPTR, VRRC:v4f32:$vB, (imm:i32):$UIMM)
// Emits: (VCTUXS:v4i32 (imm:i32):$UIMM, VRRC:v4f32:$vB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(254)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ if (CN1 == INT64_C(250)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_54(N, PPC::VCTUXS, MVT::v4i32);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 290:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB, VRRC:v16i8:$vC)
+ // Pattern: (intrinsic_wo_chain:v4i32 286:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB, VRRC:v16i8:$vC)
// Emits: (VPERM:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB, VRRC:v16i8:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(290)) {
+ if (CN1 == INT64_C(286)) {
SDNode *Result = Emit_52(N, PPC::VPERM, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 307:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB, VRRC:v4i32:$vC)
+ // Pattern: (intrinsic_wo_chain:v4i32 303:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB, VRRC:v4i32:$vC)
// Emits: (VSEL:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB, VRRC:v4i32:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(307)) {
+ if (CN1 == INT64_C(303)) {
SDNode *Result = Emit_52(N, PPC::VSEL, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 212:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 208:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VADDCUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(212)) {
+ if (CN1 == INT64_C(208)) {
SDNode *Result = Emit_51(N, PPC::VADDCUW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 215:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 211:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VADDSWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(215)) {
+ if (CN1 == INT64_C(211)) {
SDNode *Result = Emit_51(N, PPC::VADDSWS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 218:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 214:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VADDUWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(218)) {
+ if (CN1 == INT64_C(214)) {
SDNode *Result = Emit_51(N, PPC::VADDUWS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 221:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 217:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VAVGSW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(221)) {
+ if (CN1 == INT64_C(217)) {
SDNode *Result = Emit_51(N, PPC::VAVGSW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 224:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 220:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VAVGUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(224)) {
+ if (CN1 == INT64_C(220)) {
SDNode *Result = Emit_51(N, PPC::VAVGUW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 261:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 257:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VMAXSW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(261)) {
+ if (CN1 == INT64_C(257)) {
SDNode *Result = Emit_51(N, PPC::VMAXSW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 264:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 260:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VMAXUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(264)) {
+ if (CN1 == INT64_C(260)) {
SDNode *Result = Emit_51(N, PPC::VMAXUW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 270:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 266:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VMINSW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(270)) {
+ if (CN1 == INT64_C(266)) {
SDNode *Result = Emit_51(N, PPC::VMINSW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 273:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 269:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VMINUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(273)) {
+ if (CN1 == INT64_C(269)) {
SDNode *Result = Emit_51(N, PPC::VMINUW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 275:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB, VRRC:v4i32:$vC)
+ // Pattern: (intrinsic_wo_chain:v4i32 271:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB, VRRC:v4i32:$vC)
// Emits: (VMSUMMBM:v4i32 VRRC:v16i8:$vA, VRRC:v16i8:$vB, VRRC:v4i32:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(275)) {
+ if (CN1 == INT64_C(271)) {
SDNode *Result = Emit_52(N, PPC::VMSUMMBM, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 276:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
+ // Pattern: (intrinsic_wo_chain:v4i32 272:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
// Emits: (VMSUMSHM:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(276)) {
+ if (CN1 == INT64_C(272)) {
SDNode *Result = Emit_52(N, PPC::VMSUMSHM, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 277:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
+ // Pattern: (intrinsic_wo_chain:v4i32 273:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
// Emits: (VMSUMSHS:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(277)) {
+ if (CN1 == INT64_C(273)) {
SDNode *Result = Emit_52(N, PPC::VMSUMSHS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 278:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB, VRRC:v4i32:$vC)
+ // Pattern: (intrinsic_wo_chain:v4i32 274:iPTR, VRRC:v16i8:$vA, VRRC:v16i8:$vB, VRRC:v4i32:$vC)
// Emits: (VMSUMUBM:v4i32 VRRC:v16i8:$vA, VRRC:v16i8:$vB, VRRC:v4i32:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(278)) {
+ if (CN1 == INT64_C(274)) {
SDNode *Result = Emit_52(N, PPC::VMSUMUBM, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 279:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
+ // Pattern: (intrinsic_wo_chain:v4i32 275:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
// Emits: (VMSUMUHM:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(279)) {
+ if (CN1 == INT64_C(275)) {
SDNode *Result = Emit_52(N, PPC::VMSUMUHM, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 280:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
+ // Pattern: (intrinsic_wo_chain:v4i32 276:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
// Emits: (VMSUMUHS:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB, VRRC:v4i32:$vC)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(280)) {
+ if (CN1 == INT64_C(276)) {
SDNode *Result = Emit_52(N, PPC::VMSUMUHS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 282:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 278:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VMULESH:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(282)) {
+ if (CN1 == INT64_C(278)) {
SDNode *Result = Emit_51(N, PPC::VMULESH, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 284:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 280:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VMULEUH:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(284)) {
+ if (CN1 == INT64_C(280)) {
SDNode *Result = Emit_51(N, PPC::VMULEUH, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 286:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 282:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VMULOSH:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(286)) {
+ if (CN1 == INT64_C(282)) {
SDNode *Result = Emit_51(N, PPC::VMULOSH, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 288:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 284:iPTR, VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Emits: (VMULOUH:v4i32 VRRC:v8i16:$vA, VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(288)) {
+ if (CN1 == INT64_C(284)) {
SDNode *Result = Emit_51(N, PPC::VMULOUH, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 321:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 317:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSUBCUW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(321)) {
+ if (CN1 == INT64_C(317)) {
SDNode *Result = Emit_51(N, PPC::VSUBCUW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 324:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 320:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSUBSWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(324)) {
+ if (CN1 == INT64_C(320)) {
SDNode *Result = Emit_51(N, PPC::VSUBSWS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 327:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 323:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSUBUWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(327)) {
+ if (CN1 == INT64_C(323)) {
SDNode *Result = Emit_51(N, PPC::VSUBUWS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 332:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 328:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSUMSWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(332)) {
+ if (CN1 == INT64_C(328)) {
SDNode *Result = Emit_51(N, PPC::VSUMSWS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 328:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 324:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSUM2SWS:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(328)) {
+ if (CN1 == INT64_C(324)) {
SDNode *Result = Emit_51(N, PPC::VSUM2SWS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 329:iPTR, VRRC:v16i8:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 325:iPTR, VRRC:v16i8:$vA, VRRC:v4i32:$vB)
// Emits: (VSUM4SBS:v4i32 VRRC:v16i8:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(329)) {
+ if (CN1 == INT64_C(325)) {
SDNode *Result = Emit_51(N, PPC::VSUM4SBS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 330:iPTR, VRRC:v8i16:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 326:iPTR, VRRC:v8i16:$vA, VRRC:v4i32:$vB)
// Emits: (VSUM4SHS:v4i32 VRRC:v8i16:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(330)) {
+ if (CN1 == INT64_C(326)) {
SDNode *Result = Emit_51(N, PPC::VSUM4SHS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 331:iPTR, VRRC:v16i8:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 327:iPTR, VRRC:v16i8:$vA, VRRC:v4i32:$vB)
// Emits: (VSUM4UBS:v4i32 VRRC:v16i8:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(331)) {
+ if (CN1 == INT64_C(327)) {
SDNode *Result = Emit_51(N, PPC::VSUM4UBS, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 305:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 301:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VRLW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(305)) {
+ if (CN1 == INT64_C(301)) {
SDNode *Result = Emit_51(N, PPC::VRLW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 308:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 304:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSL:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(308)) {
+ if (CN1 == INT64_C(304)) {
SDNode *Result = Emit_51(N, PPC::VSL, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 311:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 307:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSLO:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(311)) {
+ if (CN1 == INT64_C(307)) {
SDNode *Result = Emit_51(N, PPC::VSLO, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 312:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 308:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSLW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(312)) {
+ if (CN1 == INT64_C(308)) {
SDNode *Result = Emit_51(N, PPC::VSLW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 313:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 309:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSR:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(313)) {
+ if (CN1 == INT64_C(309)) {
SDNode *Result = Emit_51(N, PPC::VSR, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 319:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 315:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSRO:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(319)) {
+ if (CN1 == INT64_C(315)) {
SDNode *Result = Emit_51(N, PPC::VSRO, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 316:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 312:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSRAW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(316)) {
+ if (CN1 == INT64_C(312)) {
SDNode *Result = Emit_51(N, PPC::VSRAW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 320:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 316:iPTR, VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Emits: (VSRW:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(320)) {
+ if (CN1 == INT64_C(316)) {
SDNode *Result = Emit_51(N, PPC::VSRW, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 333:iPTR, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 329:iPTR, VRRC:v8i16:$vB)
// Emits: (VUPKHPX:v4i32 VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(333)) {
+ if (CN1 == INT64_C(329)) {
SDNode *Result = Emit_53(N, PPC::VUPKHPX, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 335:iPTR, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 331:iPTR, VRRC:v8i16:$vB)
// Emits: (VUPKHSH:v4i32 VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(335)) {
+ if (CN1 == INT64_C(331)) {
SDNode *Result = Emit_53(N, PPC::VUPKHSH, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 336:iPTR, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 332:iPTR, VRRC:v8i16:$vB)
// Emits: (VUPKLPX:v4i32 VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(336)) {
+ if (CN1 == INT64_C(332)) {
SDNode *Result = Emit_53(N, PPC::VUPKLPX, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 338:iPTR, VRRC:v8i16:$vB)
+ // Pattern: (intrinsic_wo_chain:v4i32 334:iPTR, VRRC:v8i16:$vB)
// Emits: (VUPKLSH:v4i32 VRRC:v8i16:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(338)) {
+ if (CN1 == INT64_C(334)) {
SDNode *Result = Emit_53(N, PPC::VUPKLSH, MVT::v4i32);
return Result;
}
@@ -4217,128 +4217,128 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 225:iPTR, VRRC:v4i32:$vB, (imm:i32):$UIMM)
+ // Pattern: (intrinsic_wo_chain:v4f32 221:iPTR, VRRC:v4i32:$vB, (imm:i32):$UIMM)
// Emits: (VCFSX:v4f32 (imm:i32):$UIMM, VRRC:v4i32:$vB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(225)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ if (CN1 == INT64_C(221)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_54(N, PPC::VCFSX, MVT::v4f32);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 226:iPTR, VRRC:v4i32:$vB, (imm:i32):$UIMM)
+ // Pattern: (intrinsic_wo_chain:v4f32 222:iPTR, VRRC:v4i32:$vB, (imm:i32):$UIMM)
// Emits: (VCFUX:v4f32 (imm:i32):$UIMM, VRRC:v4i32:$vB)
// Pattern complexity = 11 cost = 1 size = 0
- if (CN1 == INT64_C(226)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ if (CN1 == INT64_C(222)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_54(N, PPC::VCFUX, MVT::v4f32);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 255:iPTR, VRRC:v4f32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4f32 251:iPTR, VRRC:v4f32:$vB)
// Emits: (VEXPTEFP:v4f32 VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(255)) {
+ if (CN1 == INT64_C(251)) {
SDNode *Result = Emit_53(N, PPC::VEXPTEFP, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 256:iPTR, VRRC:v4f32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4f32 252:iPTR, VRRC:v4f32:$vB)
// Emits: (VLOGEFP:v4f32 VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(256)) {
+ if (CN1 == INT64_C(252)) {
SDNode *Result = Emit_53(N, PPC::VLOGEFP, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 258:iPTR, VRRC:v4f32:$vA, VRRC:v4f32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4f32 254:iPTR, VRRC:v4f32:$vA, VRRC:v4f32:$vB)
// Emits: (VMAXFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(258)) {
+ if (CN1 == INT64_C(254)) {
SDNode *Result = Emit_51(N, PPC::VMAXFP, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 267:iPTR, VRRC:v4f32:$vA, VRRC:v4f32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4f32 263:iPTR, VRRC:v4f32:$vA, VRRC:v4f32:$vB)
// Emits: (VMINFP:v4f32 VRRC:v4f32:$vA, VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(267)) {
+ if (CN1 == INT64_C(263)) {
SDNode *Result = Emit_51(N, PPC::VMINFP, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 298:iPTR, VRRC:v4f32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4f32 294:iPTR, VRRC:v4f32:$vB)
// Emits: (VREFP:v4f32 VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(298)) {
+ if (CN1 == INT64_C(294)) {
SDNode *Result = Emit_53(N, PPC::VREFP, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 299:iPTR, VRRC:v4f32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4f32 295:iPTR, VRRC:v4f32:$vB)
// Emits: (VRFIM:v4f32 VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(299)) {
+ if (CN1 == INT64_C(295)) {
SDNode *Result = Emit_53(N, PPC::VRFIM, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 300:iPTR, VRRC:v4f32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4f32 296:iPTR, VRRC:v4f32:$vB)
// Emits: (VRFIN:v4f32 VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(300)) {
+ if (CN1 == INT64_C(296)) {
SDNode *Result = Emit_53(N, PPC::VRFIN, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 301:iPTR, VRRC:v4f32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4f32 297:iPTR, VRRC:v4f32:$vB)
// Emits: (VRFIP:v4f32 VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(301)) {
+ if (CN1 == INT64_C(297)) {
SDNode *Result = Emit_53(N, PPC::VRFIP, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 302:iPTR, VRRC:v4f32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4f32 298:iPTR, VRRC:v4f32:$vB)
// Emits: (VRFIZ:v4f32 VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(302)) {
+ if (CN1 == INT64_C(298)) {
SDNode *Result = Emit_53(N, PPC::VRFIZ, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 306:iPTR, VRRC:v4f32:$vB)
+ // Pattern: (intrinsic_wo_chain:v4f32 302:iPTR, VRRC:v4f32:$vB)
// Emits: (VRSQRTEFP:v4f32 VRRC:v4f32:$vB)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(306)) {
+ if (CN1 == INT64_C(302)) {
SDNode *Result = Emit_53(N, PPC::VRSQRTEFP, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 257:iPTR, VRRC:v4f32:$A, VRRC:v4f32:$B, VRRC:v4f32:$C)
+ // Pattern: (intrinsic_wo_chain:v4f32 253:iPTR, VRRC:v4f32:$A, VRRC:v4f32:$B, VRRC:v4f32:$C)
// Emits: (VMADDFP:v4f32 VRRC:v16i8:$A, VRRC:v16i8:$B, VRRC:v16i8:$C)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(257)) {
+ if (CN1 == INT64_C(253)) {
SDNode *Result = Emit_52(N, PPC::VMADDFP, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 289:iPTR, VRRC:v4f32:$A, VRRC:v4f32:$B, VRRC:v4f32:$C)
+ // Pattern: (intrinsic_wo_chain:v4f32 285:iPTR, VRRC:v4f32:$A, VRRC:v4f32:$B, VRRC:v4f32:$C)
// Emits: (VNMSUBFP:v4f32 VRRC:v16i8:$A, VRRC:v16i8:$B, VRRC:v16i8:$C)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(289)) {
+ if (CN1 == INT64_C(285)) {
SDNode *Result = Emit_52(N, PPC::VNMSUBFP, MVT::v4f32);
return Result;
}
@@ -4348,20 +4348,20 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_55(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, CPTmpN2_0, CPTmpN2_1, Chain);
+DISABLE_INLINE SDNode *Emit_55(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, CPTmpN2_0, CPTmpN2_1, Chain);
}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(198)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(194)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
@@ -4375,23 +4375,23 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_56(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Chain);
+DISABLE_INLINE SDNode *Emit_56(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Chain);
}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v8i16(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v8i16(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_w_chain:v8i16 199:iPTR, xoaddr:iPTR:$src)
+ // Pattern: (intrinsic_w_chain:v8i16 195:iPTR, xoaddr:iPTR:$src)
// Emits: (LVEHX:v8i16 xoaddr:iPTR:$src)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(199)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(195)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
@@ -4400,10 +4400,10 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_w_chain:v8i16 205:iPTR)
+ // Pattern: (intrinsic_w_chain:v8i16 201:iPTR)
// Emits: (MFVSCR:v8i16)
// Pattern complexity = 8 cost = 1 size = 0
- if (CN1 == INT64_C(205)) {
+ if (CN1 == INT64_C(201)) {
SDNode *Result = Emit_56(N, PPC::MFVSCR, MVT::v8i16);
return Result;
}
@@ -4413,18 +4413,18 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_w_chain:v4i32 200:iPTR, xoaddr:iPTR:$src)
+ // Pattern: (intrinsic_w_chain:v4i32 196:iPTR, xoaddr:iPTR:$src)
// Emits: (LVEWX:v4i32 xoaddr:iPTR:$src)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(200)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(196)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
@@ -4433,11 +4433,11 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_w_chain:v4i32 203:iPTR, xoaddr:iPTR:$src)
+ // Pattern: (intrinsic_w_chain:v4i32 199:iPTR, xoaddr:iPTR:$src)
// Emits: (LVX:v4i32 xoaddr:iPTR:$src)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(203)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(199)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
@@ -4446,11 +4446,11 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_w_chain:v4i32 204:iPTR, xoaddr:iPTR:$src)
+ // Pattern: (intrinsic_w_chain:v4i32 200:iPTR, xoaddr:iPTR:$src)
// Emits: (LVXL:v4i32 xoaddr:iPTR:$src)
// Pattern complexity = 17 cost = 1 size = 0
- if (CN1 == INT64_C(204)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(200)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
@@ -4464,25 +4464,25 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_57(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_57(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, CPTmpN1_0, CPTmpN1_1, Chain);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, CPTmpN1_0, CPTmpN1_1, Chain);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode())) {
+SDNode *Select_ISD_LOAD_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N)) {
// Pattern: (ld:i32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
// Emits: (LBZ:i32 iaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_zextload(N.getNode()) &&
- Predicate_zextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextload(N) &&
+ Predicate_zextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -4494,9 +4494,9 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
// Emits: (LHA:i32 iaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_sextload(N.getNode()) &&
- Predicate_sextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextload(N) &&
+ Predicate_sextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -4508,9 +4508,9 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
// Emits: (LHZ:i32 iaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_zextload(N.getNode()) &&
- Predicate_zextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextload(N) &&
+ Predicate_zextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -4522,8 +4522,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
// Emits: (LWZ:i32 iaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_load(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_load(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -4535,9 +4535,9 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
// Emits: (LBZX:i32 xaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_zextload(N.getNode()) &&
- Predicate_zextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextload(N) &&
+ Predicate_zextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -4549,9 +4549,9 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
// Emits: (LHAX:i32 xaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_sextload(N.getNode()) &&
- Predicate_sextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextload(N) &&
+ Predicate_sextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -4563,9 +4563,9 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
// Emits: (LHZX:i32 xaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_zextload(N.getNode()) &&
- Predicate_zextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextload(N) &&
+ Predicate_zextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -4577,8 +4577,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
// Emits: (LWZX:i32 xaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_load(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_load(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -4586,9 +4586,9 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return Result;
}
}
- if (Predicate_zextload(N.getNode()) &&
- Predicate_zextloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextload(N) &&
+ Predicate_zextloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -4608,9 +4608,9 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return Result;
}
}
- if (Predicate_extload(N.getNode())) {
- if (Predicate_extloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extload(N)) {
+ if (Predicate_extloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -4630,8 +4630,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return Result;
}
}
- if (Predicate_extloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -4651,8 +4651,8 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return Result;
}
}
- if (Predicate_extloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -4679,16 +4679,16 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode())) {
- if (Predicate_sextload(N.getNode())) {
+SDNode *Select_ISD_LOAD_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N)) {
+ if (Predicate_sextload(N)) {
// Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
// Emits: (LHA8:i64 iaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_sextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -4700,8 +4700,8 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
// Pattern: (ld:i64 ixaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>>
// Emits: (LWA:i64 ixaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_sextloadi32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrImmShift(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -4713,8 +4713,8 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
// Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
// Emits: (LHAX8:i64 xaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_sextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -4726,8 +4726,8 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
// Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>>
// Emits: (LWAX:i64 xaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_sextloadi32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -4736,13 +4736,13 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
}
}
}
- if (Predicate_zextload(N.getNode())) {
+ if (Predicate_zextload(N)) {
// Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
// Emits: (LBZ8:i64 iaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_zextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -4754,8 +4754,8 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
// Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
// Emits: (LHZ8:i64 iaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_zextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -4767,8 +4767,8 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
// Pattern: (ld:i64 iaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>
// Emits: (LWZ8:i64 iaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_zextloadi32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrImm(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -4780,8 +4780,8 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
// Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
// Emits: (LBZX8:i64 xaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_zextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -4793,8 +4793,8 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
// Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
// Emits: (LHZX8:i64 xaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_zextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -4806,8 +4806,8 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
// Pattern: (ld:i64 xaddr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>
// Emits: (LWZX8:i64 xaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_zextloadi32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdx(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -4816,8 +4816,8 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
}
}
}
- if (Predicate_load(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_load(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -4837,9 +4837,9 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
return Result;
}
}
- if (Predicate_zextload(N.getNode()) &&
- Predicate_zextloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextload(N) &&
+ Predicate_zextloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -4859,9 +4859,9 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
return Result;
}
}
- if (Predicate_extload(N.getNode())) {
- if (Predicate_extloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extload(N)) {
+ if (Predicate_extloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -4881,8 +4881,8 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
return Result;
}
}
- if (Predicate_extloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -4902,8 +4902,8 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
return Result;
}
}
- if (Predicate_extloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -4923,8 +4923,8 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
return Result;
}
}
- if (Predicate_extloadi32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -4951,11 +4951,11 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_LOAD_f32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode()) &&
- Predicate_load(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_LOAD_f32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N) &&
+ Predicate_load(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -4980,23 +4980,23 @@ SDNode *Select_ISD_LOAD_f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_58(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp1(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, MVT::Other, CPTmpN1_0, CPTmpN1_1, Chain), 0);
+DISABLE_INLINE SDNode *Emit_58(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp1(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, MVT::Other, CPTmpN1_0, CPTmpN1_1, Chain), 0);
Chain = SDValue(Tmp1.getNode(), 1);
MachineSDNode::mmo_iterator MemRefs1 = MF->allocateMemRefsArray(1);
MemRefs1[0] = cast<MemSDNode>(N)->getMemOperand();
- SDNode *ResNode = CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp1);
+ SDNode *ResNode = CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp1);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs1, MemRefs1 + 1);
- ReplaceUses(SDValue(N.getNode(), 1), Chain);
+ ReplaceUses(SDValue(N, 1), Chain);
return ResNode;
}
-SDNode *Select_ISD_LOAD_f64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode())) {
- if (Predicate_load(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_LOAD_f64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N)) {
+ if (Predicate_load(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -5016,9 +5016,9 @@ SDNode *Select_ISD_LOAD_f64(const SDValue &N) {
return Result;
}
}
- if (Predicate_extload(N.getNode()) &&
- Predicate_extloadf32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extload(N) &&
+ Predicate_extloadf32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -5044,11 +5044,11 @@ SDNode *Select_ISD_LOAD_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_LOAD_v4i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode()) &&
- Predicate_load(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_LOAD_v4i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N) &&
+ Predicate_load(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -5061,27 +5061,27 @@ SDNode *Select_ISD_LOAD_v4i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_59(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain);
-}
-SDNode *Select_ISD_MEMBARRIER(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDValue N4 = N.getOperand(4);
- if (N4.getOpcode() == ISD::Constant) {
- SDValue N5 = N.getOperand(5);
- if (N5.getOpcode() == ISD::Constant &&
+DISABLE_INLINE SDNode *Emit_59(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Chain);
+}
+SDNode *Select_ISD_MEMBARRIER(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N4 = N->getOperand(4);
+ if (N4.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_59(N, PPC::SYNC);
return Result;
@@ -5095,15 +5095,15 @@ SDNode *Select_ISD_MEMBARRIER(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_MUL_i32(const SDValue &N) {
+SDNode *Select_ISD_MUL_i32(SDNode *N) {
// Pattern: (mul:i32 GPRC:i32:$rA, (imm:i32)<<P:Predicate_immSExt16>>:$imm)
// Emits: (MULLI:i32 GPRC:i32:$rA, (imm:i32):$imm)
// Pattern complexity = 7 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_immSExt16(N1.getNode())) {
SDNode *Result = Emit_0(N, PPC::MULLI, MVT::i32);
return Result;
@@ -5117,53 +5117,53 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_MUL_i64(const SDValue &N) {
+SDNode *Select_ISD_MUL_i64(SDNode *N) {
SDNode *Result = Emit_3(N, PPC::MULLD, MVT::i64);
return Result;
}
-SDNode *Select_ISD_MULHS_i32(const SDValue &N) {
+SDNode *Select_ISD_MULHS_i32(SDNode *N) {
SDNode *Result = Emit_3(N, PPC::MULHW, MVT::i32);
return Result;
}
-SDNode *Select_ISD_MULHS_i64(const SDValue &N) {
+SDNode *Select_ISD_MULHS_i64(SDNode *N) {
SDNode *Result = Emit_3(N, PPC::MULHD, MVT::i64);
return Result;
}
-SDNode *Select_ISD_MULHU_i32(const SDValue &N) {
+SDNode *Select_ISD_MULHU_i32(SDNode *N) {
SDNode *Result = Emit_3(N, PPC::MULHWU, MVT::i32);
return Result;
}
-SDNode *Select_ISD_MULHU_i64(const SDValue &N) {
+SDNode *Select_ISD_MULHU_i64(SDNode *N) {
SDNode *Result = Emit_3(N, PPC::MULHDU, MVT::i64);
return Result;
}
-DISABLE_INLINE SDNode *Emit_60(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_60(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_LO16(Tmp1.getNode());
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp2), 0);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
SDValue Tmp4 = Transform_HI16(Tmp1.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp3, Tmp4);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp3, Tmp4);
}
-SDNode *Select_ISD_OR_i32(const SDValue &N) {
+SDNode *Select_ISD_OR_i32(SDNode *N) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (or:i32 GPRC:i32:$rS, (xor:i32 GPRC:i32:$rB, (imm:i32)<<P:Predicate_immAllOnes>>))
// Emits: (ORC:i32 GPRC:i32:$rS, GPRC:i32:$rB)
// Pattern complexity = 10 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N11.getNode())) {
SDNode *Result = Emit_2(N, PPC::ORC, MVT::i32);
return Result;
@@ -5174,17 +5174,17 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Pattern: (or:i32 (xor:i32 GPRC:i32:$rB, (imm:i32)<<P:Predicate_immAllOnes>>), GPRC:i32:$rS)
// Emits: (ORC:i32 GPRC:i32:$rS, GPRC:i32:$rB)
// Pattern complexity = 10 cost = 1 size = 0
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N01.getNode())) {
SDNode *Result = Emit_5(N, PPC::ORC, MVT::i32);
return Result;
}
}
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (or:i32 GPRC:i32:$src1, (imm:i32)<<P:Predicate_immZExt16>><<X:LO16>>:$src2)
// Emits: (ORI:i32 GPRC:i32:$src1, (LO16:i32 (imm:i32):$src2))
@@ -5217,19 +5217,19 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_OR_i64(const SDValue &N) {
+SDNode *Select_ISD_OR_i64(SDNode *N) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (or:i64 G8RC:i64:$rS, (xor:i64 G8RC:i64:$rB, (imm:i64)<<P:Predicate_immAllOnes>>))
// Emits: (ORC8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
// Pattern complexity = 10 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N11.getNode())) {
SDNode *Result = Emit_2(N, PPC::ORC8, MVT::i64);
return Result;
@@ -5240,17 +5240,17 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
// Pattern: (or:i64 (xor:i64 G8RC:i64:$rB, (imm:i64)<<P:Predicate_immAllOnes>>), G8RC:i64:$rS)
// Emits: (ORC8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
// Pattern complexity = 10 cost = 1 size = 0
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N01.getNode())) {
SDNode *Result = Emit_5(N, PPC::ORC8, MVT::i64);
return Result;
}
}
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (or:i64 G8RC:i64:$src1, (imm:i64)<<P:Predicate_immZExt16>><<X:LO16>>:$src2)
// Emits: (ORI8:i64 G8RC:i64:$src1, (LO16:i32 (imm:i64):$src2))
@@ -5277,36 +5277,36 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_OR_v4i32(const SDValue &N) {
+SDNode *Select_ISD_OR_v4i32(SDNode *N) {
SDNode *Result = Emit_3(N, PPC::VOR, MVT::v4i32);
return Result;
}
-DISABLE_INLINE SDNode *Emit_61(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_61(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(0x1FULL, MVT::i32);
SDValue Ops0[] = { N0, N1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_62(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_62(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
SDValue Tmp3 = CurDAG->getTargetConstant(0x1FULL, MVT::i32);
SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-SDNode *Select_ISD_ROTL_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ROTL_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (rotl:i32 GPRC:i32:$in, (imm:i32):$imm)
// Emits: (RLWINM:i32 GPRC:i32:$in, (imm:i32):$imm, 0:i32, 31:i32)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_62(N, PPC::RLWINM, MVT::i32);
return Result;
@@ -5324,27 +5324,27 @@ SDNode *Select_ISD_ROTL_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_63(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_63(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, Tmp2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_64(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_64(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1, Tmp2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1, Tmp2);
}
-SDNode *Select_ISD_ROTL_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ROTL_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (rotl:i64 G8RC:i64:$in, (imm:i32):$imm)
// Emits: (RLDICL:i64 G8RC:i64:$in, (imm:i32):$imm, 0:i32)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_64(N, PPC::RLDICL, MVT::i64);
return Result;
@@ -5362,33 +5362,33 @@ SDNode *Select_ISD_ROTL_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SDIV_i32(const SDValue &N) {
+SDNode *Select_ISD_SDIV_i32(SDNode *N) {
SDNode *Result = Emit_3(N, PPC::DIVW, MVT::i32);
return Result;
}
-SDNode *Select_ISD_SDIV_i64(const SDValue &N) {
+SDNode *Select_ISD_SDIV_i64(SDNode *N) {
SDNode *Result = Emit_3(N, PPC::DIVD, MVT::i64);
return Result;
}
-DISABLE_INLINE SDNode *Emit_65(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_65(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
SDValue Tmp3 = Transform_SHL32(Tmp1.getNode());
SDValue Ops0[] = { N0, Tmp1, Tmp2, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-SDNode *Select_ISD_SHL_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SHL_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (shl:i32 GPRC:i32:$in, (imm:i32):$imm)
// Emits: (RLWINM:i32 GPRC:i32:$in, (imm:i32):$imm, 0:i32, (SHL32:i32 (imm:i32):$imm))
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_65(N, PPC::RLWINM, MVT::i32);
return Result;
@@ -5406,21 +5406,21 @@ SDNode *Select_ISD_SHL_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_66(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_66(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_SHL64(Tmp1.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1, Tmp2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1, Tmp2);
}
-SDNode *Select_ISD_SHL_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SHL_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (shl:i64 G8RC:i64:$in, (imm:i32):$imm)
// Emits: (RLDICR:i64 G8RC:i64:$in, (imm:i32):$imm, (SHL64:i32 (imm:i32):$imm))
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_66(N, PPC::RLDICR, MVT::i64);
return Result;
@@ -5438,9 +5438,9 @@ SDNode *Select_ISD_SHL_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SHL_v16i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SHL_v16i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_3(N, PPC::VSLB, MVT::v16i8);
return Result;
@@ -5450,9 +5450,9 @@ SDNode *Select_ISD_SHL_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SHL_v8i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SHL_v8i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_3(N, PPC::VSLH, MVT::v8i16);
return Result;
@@ -5462,9 +5462,9 @@ SDNode *Select_ISD_SHL_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SHL_v4i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SHL_v4i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_3(N, PPC::VSLW, MVT::v4i32);
return Result;
@@ -5474,8 +5474,8 @@ SDNode *Select_ISD_SHL_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SIGN_EXTEND_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_SIGN_EXTEND_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_29(N, PPC::EXTSW_32_64, MVT::i64);
return Result;
@@ -5485,19 +5485,19 @@ SDNode *Select_ISD_SIGN_EXTEND_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_67(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0);
+DISABLE_INLINE SDNode *Emit_67(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0);
}
-SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (sext_inreg:i32 GPRC:i32:$rS, i8:Other)
// Emits: (EXTSB:i32 GPRC:i32:$rS)
// Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
SDNode *Result = Emit_67(N, PPC::EXTSB, MVT::i32);
return Result;
}
@@ -5505,7 +5505,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
// Pattern: (sext_inreg:i32 GPRC:i32:$rS, i16:Other)
// Emits: (EXTSH:i32 GPRC:i32:$rS)
// Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
SDNode *Result = Emit_67(N, PPC::EXTSH, MVT::i32);
return Result;
}
@@ -5514,14 +5514,14 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SIGN_EXTEND_INREG_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SIGN_EXTEND_INREG_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (sext_inreg:i64 G8RC:i64:$rS, i8:Other)
// Emits: (EXTSB8:i64 G8RC:i64:$rS)
// Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
SDNode *Result = Emit_67(N, PPC::EXTSB8, MVT::i64);
return Result;
}
@@ -5529,7 +5529,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i64(const SDValue &N) {
// Pattern: (sext_inreg:i64 G8RC:i64:$rS, i16:Other)
// Emits: (EXTSH8:i64 G8RC:i64:$rS)
// Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
SDNode *Result = Emit_67(N, PPC::EXTSH8, MVT::i64);
return Result;
}
@@ -5537,7 +5537,7 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i64(const SDValue &N) {
// Pattern: (sext_inreg:i64 G8RC:i64:$rS, i32:Other)
// Emits: (EXTSW:i64 G8RC:i64:$rS)
// Pattern complexity = 3 cost = 1 size = 0
- if (cast<VTSDNode>(N1)->getVT() == MVT::i32) {
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i32) {
SDNode *Result = Emit_67(N, PPC::EXTSW, MVT::i64);
return Result;
}
@@ -5546,14 +5546,14 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SRA_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SRA_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (sra:i32 GPRC:i32:$rS, (imm:i32):$SH)
// Emits: (SRAWI:i32 GPRC:i32:$rS, (imm:i32):$SH)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_0(N, PPC::SRAWI, MVT::i32);
return Result;
@@ -5571,14 +5571,14 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SRA_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SRA_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (sra:i64 G8RC:i64:$rS, (imm:i32):$SH)
// Emits: (SRADI:i64 G8RC:i64:$rS, (imm:i32):$SH)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_0(N, PPC::SRADI, MVT::i64);
return Result;
@@ -5596,9 +5596,9 @@ SDNode *Select_ISD_SRA_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SRA_v16i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SRA_v16i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_3(N, PPC::VSRAB, MVT::v16i8);
return Result;
@@ -5608,9 +5608,9 @@ SDNode *Select_ISD_SRA_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SRA_v8i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SRA_v8i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_3(N, PPC::VSRAH, MVT::v8i16);
return Result;
@@ -5620,9 +5620,9 @@ SDNode *Select_ISD_SRA_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SRA_v4i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SRA_v4i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_3(N, PPC::VSRAW, MVT::v4i32);
return Result;
@@ -5632,23 +5632,23 @@ SDNode *Select_ISD_SRA_v4i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_68(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_68(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_SRL32(Tmp1.getNode());
SDValue Tmp3 = CurDAG->getTargetConstant(0x1FULL, MVT::i32);
SDValue Ops0[] = { N0, Tmp2, Tmp1, Tmp3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-SDNode *Select_ISD_SRL_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SRL_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (srl:i32 GPRC:i32:$in, (imm:i32):$imm)
// Emits: (RLWINM:i32 GPRC:i32:$in, (SRL32:i32 (imm:i32):$imm), (imm:i32):$imm, 31:i32)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_68(N, PPC::RLWINM, MVT::i32);
return Result;
@@ -5666,21 +5666,21 @@ SDNode *Select_ISD_SRL_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_69(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_69(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_SRL64(Tmp1.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2, Tmp1);
}
-SDNode *Select_ISD_SRL_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SRL_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (srl:i64 G8RC:i64:$in, (imm:i32):$imm)
// Emits: (RLDICL:i64 G8RC:i64:$in, (SRL64:i32 (imm:i32):$imm), (imm:i32):$imm)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_69(N, PPC::RLDICL, MVT::i64);
return Result;
@@ -5698,9 +5698,9 @@ SDNode *Select_ISD_SRL_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SRL_v16i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SRL_v16i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_3(N, PPC::VSRB, MVT::v16i8);
return Result;
@@ -5710,9 +5710,9 @@ SDNode *Select_ISD_SRL_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SRL_v8i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SRL_v8i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_3(N, PPC::VSRH, MVT::v8i16);
return Result;
@@ -5722,9 +5722,9 @@ SDNode *Select_ISD_SRL_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SRL_v4i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SRL_v4i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_3(N, PPC::VSRW, MVT::v4i32);
return Result;
@@ -5734,28 +5734,28 @@ SDNode *Select_ISD_SRL_v4i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_70(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_70(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 4);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 4);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-SDNode *Select_ISD_STORE(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode())) {
- if (Predicate_truncstore(N.getNode())) {
+SDNode *Select_ISD_STORE(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N)) {
+ if (Predicate_truncstore(N)) {
// Pattern: (st:isVoid GPRC:i32:$rS, iaddr:iPTR:$src)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
// Emits: (STB:isVoid GPRC:i32:$rS, iaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_truncstorei8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstorei8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
@@ -5768,9 +5768,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid GPRC:i32:$rS, iaddr:iPTR:$src)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
// Emits: (STH:isVoid GPRC:i32:$rS, iaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_truncstorei16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstorei16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
@@ -5780,9 +5780,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1)) {
@@ -5812,14 +5812,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (Predicate_truncstore(N.getNode())) {
+ if (Predicate_truncstore(N)) {
// Pattern: (st:isVoid GPRC:i32:$rS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
// Emits: (STBX:isVoid GPRC:i32:$rS, xaddr:iPTR:$dst)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_truncstorei8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstorei8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1) &&
@@ -5832,9 +5832,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid GPRC:i32:$rS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
// Emits: (STHX:isVoid GPRC:i32:$rS, xaddr:iPTR:$dst)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_truncstorei16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstorei16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1) &&
@@ -5844,9 +5844,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1)) {
@@ -5876,14 +5876,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (Predicate_truncstore(N.getNode())) {
+ if (Predicate_truncstore(N)) {
// Pattern: (st:isVoid G8RC:i64:$rS, iaddr:iPTR:$src)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
// Emits: (STB8:isVoid G8RC:i64:$rS, iaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_truncstorei8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstorei8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
@@ -5896,9 +5896,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid G8RC:i64:$rS, iaddr:iPTR:$src)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
// Emits: (STH8:isVoid G8RC:i64:$rS, iaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_truncstorei16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstorei16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
@@ -5911,9 +5911,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid G8RC:i64:$rS, iaddr:iPTR:$src)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>>
// Emits: (STW8:isVoid G8RC:i64:$rS, iaddr:iPTR:$src)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_truncstorei32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstorei32(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
@@ -5926,9 +5926,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>
// Emits: (STBX8:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_truncstorei8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstorei8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1) &&
@@ -5941,9 +5941,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>
// Emits: (STHX8:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_truncstorei16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstorei16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1) &&
@@ -5956,9 +5956,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>>
// Emits: (STWX8:isVoid G8RC:i64:$rS, xaddr:iPTR:$dst)
// Pattern complexity = 13 cost = 1 size = 0
- if (Predicate_truncstorei32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstorei32(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdx(N, N2, CPTmpN2_0, CPTmpN2_1) &&
@@ -5968,9 +5968,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -6007,30 +6007,30 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_71(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN3_0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_71(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN3_0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { N1, CPTmpN3_0, N2, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 4);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 4);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-SDNode *Select_ISD_STORE_iPTR(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_itruncstore(N.getNode()) &&
- Predicate_pre_truncst(N.getNode())) {
+SDNode *Select_ISD_STORE_iPTR(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_itruncstore(N) &&
+ Predicate_pre_truncst(N)) {
// Pattern: (ist:iPTR GPRC:i32:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti8>>
// Emits: (STBU:iPTR GPRC:i32:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
// Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_pre_truncsti8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_pre_truncsti8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
if (SelectAddrImmOffs(N, N3, CPTmpN3_0) &&
N1.getValueType() == MVT::i32) {
@@ -6042,10 +6042,10 @@ SDNode *Select_ISD_STORE_iPTR(const SDValue &N) {
// Pattern: (ist:iPTR GPRC:i32:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti16>>
// Emits: (STHU:iPTR GPRC:i32:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
// Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_pre_truncsti16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_pre_truncsti16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
if (SelectAddrImmOffs(N, N3, CPTmpN3_0) &&
N1.getValueType() == MVT::i32) {
@@ -6054,11 +6054,11 @@ SDNode *Select_ISD_STORE_iPTR(const SDValue &N) {
}
}
}
- if (Predicate_istore(N.getNode()) &&
- Predicate_pre_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_istore(N) &&
+ Predicate_pre_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
if (SelectAddrImmOffs(N, N3, CPTmpN3_0)) {
@@ -6087,16 +6087,16 @@ SDNode *Select_ISD_STORE_iPTR(const SDValue &N) {
}
}
}
- if (Predicate_itruncstore(N.getNode()) &&
- Predicate_pre_truncst(N.getNode())) {
+ if (Predicate_itruncstore(N) &&
+ Predicate_pre_truncst(N)) {
// Pattern: (ist:iPTR G8RC:i64:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti8>>
// Emits: (STBU8:iPTR G8RC:i64:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
// Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_pre_truncsti8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_pre_truncsti8(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
if (SelectAddrImmOffs(N, N3, CPTmpN3_0) &&
N1.getValueType() == MVT::i64) {
@@ -6108,10 +6108,10 @@ SDNode *Select_ISD_STORE_iPTR(const SDValue &N) {
// Pattern: (ist:iPTR G8RC:i64:$rS, ptr_rc:iPTR:$ptrreg, iaddroff:iPTR:$ptroff)<<P:Predicate_itruncstore>><<P:Predicate_pre_truncst>><<P:Predicate_pre_truncsti16>>
// Emits: (STHU8:iPTR G8RC:i64:$rS, iaddroff:i32:$ptroff, ptr_rc:iPTR:$ptrreg)
// Pattern complexity = 10 cost = 1 size = 0
- if (Predicate_pre_truncsti16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_pre_truncsti16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
if (SelectAddrImmOffs(N, N3, CPTmpN3_0) &&
N1.getValueType() == MVT::i64) {
@@ -6120,11 +6120,11 @@ SDNode *Select_ISD_STORE_iPTR(const SDValue &N) {
}
}
}
- if (Predicate_istore(N.getNode()) &&
- Predicate_pre_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ if (Predicate_istore(N) &&
+ Predicate_pre_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue CPTmpN3_0;
if (SelectAddrImmOffs(N, N3, CPTmpN3_0) &&
N1.getValueType() == MVT::i64) {
@@ -6149,26 +6149,26 @@ SDNode *Select_ISD_STORE_iPTR(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_72(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N0);
+DISABLE_INLINE SDNode *Emit_72(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N0);
}
-DISABLE_INLINE SDNode *Emit_73(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_73(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, Tmp1);
}
-SDNode *Select_ISD_SUB_i32(const SDValue &N) {
+SDNode *Select_ISD_SUB_i32(SDNode *N) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (sub:i32 0:i32, GPRC:i32:$rA)
// Emits: (NEG:i32 GPRC:i32:$rA)
// Pattern complexity = 8 cost = 1 size = 0
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -6181,7 +6181,7 @@ SDNode *Select_ISD_SUB_i32(const SDValue &N) {
// Pattern: (sub:i32 (imm:i32)<<P:Predicate_immSExt16>>:$imm, GPRC:i32:$in)
// Emits: (SUBFIC:i32 GPRC:i32:$in, (imm:i32):$imm)
// Pattern complexity = 7 cost = 1 size = 0
- if (N0.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::Constant &&
Predicate_immSExt16(N0.getNode())) {
SDNode *Result = Emit_73(N, PPC::SUBFIC, MVT::i32);
return Result;
@@ -6195,14 +6195,14 @@ SDNode *Select_ISD_SUB_i32(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_SUB_i64(const SDValue &N) {
+SDNode *Select_ISD_SUB_i64(SDNode *N) {
// Pattern: (sub:i64 0:i64, G8RC:i64:$rA)
// Emits: (NEG8:i64 G8RC:i64:$rA)
// Pattern complexity = 8 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -6219,46 +6219,46 @@ SDNode *Select_ISD_SUB_i64(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_SUB_v16i8(const SDValue &N) {
+SDNode *Select_ISD_SUB_v16i8(SDNode *N) {
SDNode *Result = Emit_3(N, PPC::VSUBUBM, MVT::v16i8);
return Result;
}
-SDNode *Select_ISD_SUB_v8i16(const SDValue &N) {
+SDNode *Select_ISD_SUB_v8i16(SDNode *N) {
SDNode *Result = Emit_3(N, PPC::VSUBUHM, MVT::v8i16);
return Result;
}
-SDNode *Select_ISD_SUB_v4i32(const SDValue &N) {
+SDNode *Select_ISD_SUB_v4i32(SDNode *N) {
SDNode *Result = Emit_3(N, PPC::VSUBUWM, MVT::v4i32);
return Result;
}
-DISABLE_INLINE SDNode *Emit_74(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_74(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N1, Tmp1);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N1, Tmp1);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_75(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N1, N0);
+DISABLE_INLINE SDNode *Emit_75(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N1, N0);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-SDNode *Select_ISD_SUBC_i32(const SDValue &N) {
+SDNode *Select_ISD_SUBC_i32(SDNode *N) {
// Pattern: (subc:i32 (imm:i32)<<P:Predicate_immSExt16>>:$imm, GPRC:i32:$rA)
// Emits: (SUBFIC:i32 GPRC:i32:$rA, (imm:i32):$imm)
// Pattern complexity = 7 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::Constant &&
Predicate_immSExt16(N0.getNode())) {
SDNode *Result = Emit_74(N, PPC::SUBFIC, MVT::i32);
return Result;
@@ -6272,23 +6272,23 @@ SDNode *Select_ISD_SUBC_i32(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_76(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_76(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i64);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N1, Tmp1);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N1, Tmp1);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-SDNode *Select_ISD_SUBC_i64(const SDValue &N) {
+SDNode *Select_ISD_SUBC_i64(SDNode *N) {
// Pattern: (subc:i64 (imm:i64)<<P:Predicate_immSExt16>>:$imm, G8RC:i64:$rA)
// Emits: (SUBFIC8:i64 G8RC:i64:$rA, (imm:i64):$imm)
// Pattern complexity = 7 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::Constant &&
Predicate_immSExt16(N0.getNode())) {
SDNode *Result = Emit_76(N, PPC::SUBFIC8, MVT::i64);
return Result;
@@ -6302,33 +6302,33 @@ SDNode *Select_ISD_SUBC_i64(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_77(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue InFlag = N.getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N1, N0, InFlag);
+DISABLE_INLINE SDNode *Emit_77(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue InFlag = N->getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N1, N0, InFlag);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_78(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue InFlag = N.getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N1, InFlag);
+DISABLE_INLINE SDNode *Emit_78(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue InFlag = N->getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N1, InFlag);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
+SDNode *Select_ISD_SUBE_i32(SDNode *N) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (sube:i32 0:i32, GPRC:i32:$rA)
// Emits: (SUBFZE:i32 GPRC:i32:$rA)
// Pattern complexity = 8 cost = 1 size = 0
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -6341,7 +6341,7 @@ SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
// Pattern: (sube:i32 (imm:i32)<<P:Predicate_immAllOnes>>, GPRC:i32:$rA)
// Emits: (SUBFME:i32 GPRC:i32:$rA)
// Pattern complexity = 7 cost = 1 size = 0
- if (N0.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N0.getNode())) {
SDNode *Result = Emit_78(N, PPC::SUBFME, MVT::i32);
return Result;
@@ -6355,15 +6355,15 @@ SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_SUBE_i64(const SDValue &N) {
+SDNode *Select_ISD_SUBE_i64(SDNode *N) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (sube:i64 0:i64, G8RC:i64:$rA)
// Emits: (SUBFZE8:i64 G8RC:i64:$rA)
// Pattern complexity = 8 cost = 1 size = 0
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -6376,7 +6376,7 @@ SDNode *Select_ISD_SUBE_i64(const SDValue &N) {
// Pattern: (sube:i64 (imm:i64)<<P:Predicate_immAllOnes>>, G8RC:i64:$rA)
// Emits: (SUBFME8:i64 G8RC:i64:$rA)
// Pattern complexity = 7 cost = 1 size = 0
- if (N0.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N0.getNode())) {
SDNode *Result = Emit_78(N, PPC::SUBFME8, MVT::i64);
return Result;
@@ -6390,17 +6390,17 @@ SDNode *Select_ISD_SUBE_i64(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_79(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain);
+DISABLE_INLINE SDNode *Emit_79(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Chain);
}
-SDNode *Select_ISD_TRAP(const SDValue &N) {
+SDNode *Select_ISD_TRAP(SDNode *N) {
SDNode *Result = Emit_79(N, PPC::TRAP);
return Result;
}
-SDNode *Select_ISD_TRUNCATE_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_TRUNCATE_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i64) {
SDNode *Result = Emit_18(N, PPC::OR8To4, MVT::i32);
return Result;
@@ -6410,60 +6410,60 @@ SDNode *Select_ISD_TRUNCATE_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_UDIV_i32(const SDValue &N) {
+SDNode *Select_ISD_UDIV_i32(SDNode *N) {
SDNode *Result = Emit_3(N, PPC::DIVWU, MVT::i32);
return Result;
}
-SDNode *Select_ISD_UDIV_i64(const SDValue &N) {
+SDNode *Select_ISD_UDIV_i64(SDNode *N) {
SDNode *Result = Emit_3(N, PPC::DIVDU, MVT::i64);
return Result;
}
-DISABLE_INLINE SDNode *Emit_80(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp3 = Transform_VSLDOI_get_imm(N.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, Tmp3);
+DISABLE_INLINE SDNode *Emit_80(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp3 = Transform_VSLDOI_get_imm(SDValue(N, 0).getNode());
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_81(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp1 = Transform_VSPLTB_get_imm(N.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1, N0);
+DISABLE_INLINE SDNode *Emit_81(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp1 = Transform_VSPLTB_get_imm(SDValue(N, 0).getNode());
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1, N0);
}
-DISABLE_INLINE SDNode *Emit_82(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp1 = Transform_VSPLTH_get_imm(N.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1, N0);
+DISABLE_INLINE SDNode *Emit_82(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp1 = Transform_VSPLTH_get_imm(SDValue(N, 0).getNode());
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1, N0);
}
-DISABLE_INLINE SDNode *Emit_83(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp1 = Transform_VSPLTW_get_imm(N.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp1, N0);
+DISABLE_INLINE SDNode *Emit_83(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp1 = Transform_VSPLTW_get_imm(SDValue(N, 0).getNode());
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp1, N0);
}
-DISABLE_INLINE SDNode *Emit_84(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp3 = Transform_VSLDOI_unary_get_imm(N.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N0, Tmp3);
+DISABLE_INLINE SDNode *Emit_84(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp3 = Transform_VSLDOI_unary_get_imm(SDValue(N, 0).getNode());
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N0, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_85(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N0);
+DISABLE_INLINE SDNode *Emit_85(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N0);
}
-SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
+SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(SDNode *N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vB, (undef:v16i8))<<P:Predicate_vspltb_shuffle>><<X:VSPLTB_get_imm>>:$UIMM
// Emits: (VSPLTB:v16i8 (VSPLTB_get_imm:i32 (vector_shuffle:v16i8 VRRC:v16i8:$vB, (undef:v16i8)):$UIMM), VRRC:v16i8:$vB)
// Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vspltb_shuffle(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
+ if (Predicate_vspltb_shuffle(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
SDNode *Result = Emit_81(N, PPC::VSPLTB, MVT::v16i8);
return Result;
}
@@ -6472,10 +6472,10 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vB, (undef:v16i8))<<P:Predicate_vsplth_shuffle>><<X:VSPLTH_get_imm>>:$UIMM
// Emits: (VSPLTH:v16i8 (VSPLTH_get_imm:i32 (vector_shuffle:v16i8 VRRC:v16i8:$vB, (undef:v16i8)):$UIMM), VRRC:v16i8:$vB)
// Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vsplth_shuffle(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
+ if (Predicate_vsplth_shuffle(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
SDNode *Result = Emit_82(N, PPC::VSPLTH, MVT::v16i8);
return Result;
}
@@ -6484,10 +6484,10 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vB, (undef:v16i8))<<P:Predicate_vspltw_shuffle>><<X:VSPLTW_get_imm>>:$UIMM
// Emits: (VSPLTW:v16i8 (VSPLTW_get_imm:i32 (vector_shuffle:v16i8 VRRC:v16i8:$vB, (undef:v16i8)):$UIMM), VRRC:v16i8:$vB)
// Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vspltw_shuffle(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
+ if (Predicate_vspltw_shuffle(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
SDNode *Result = Emit_83(N, PPC::VSPLTW, MVT::v16i8);
return Result;
}
@@ -6496,10 +6496,10 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vsldoi_unary_shuffle>><<X:VSLDOI_unary_get_imm>>:$in
// Emits: (VSLDOI:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA, (VSLDOI_unary_get_imm:i32 VRRC:i32:$in))
// Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vsldoi_unary_shuffle(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
+ if (Predicate_vsldoi_unary_shuffle(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
SDNode *Result = Emit_84(N, PPC::VSLDOI, MVT::v16i8);
return Result;
}
@@ -6508,10 +6508,10 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vpkuwum_unary_shuffle>>
// Emits: (VPKUWUM:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
// Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vpkuwum_unary_shuffle(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
+ if (Predicate_vpkuwum_unary_shuffle(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
SDNode *Result = Emit_85(N, PPC::VPKUWUM, MVT::v16i8);
return Result;
}
@@ -6520,10 +6520,10 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vpkuhum_unary_shuffle>>
// Emits: (VPKUHUM:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
// Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vpkuhum_unary_shuffle(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
+ if (Predicate_vpkuhum_unary_shuffle(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
SDNode *Result = Emit_85(N, PPC::VPKUHUM, MVT::v16i8);
return Result;
}
@@ -6532,10 +6532,10 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vmrglb_unary_shuffle>>
// Emits: (VMRGLB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
// Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vmrglb_unary_shuffle(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
+ if (Predicate_vmrglb_unary_shuffle(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
SDNode *Result = Emit_85(N, PPC::VMRGLB, MVT::v16i8);
return Result;
}
@@ -6544,10 +6544,10 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vmrglh_unary_shuffle>>
// Emits: (VMRGLH:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
// Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vmrglh_unary_shuffle(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
+ if (Predicate_vmrglh_unary_shuffle(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
SDNode *Result = Emit_85(N, PPC::VMRGLH, MVT::v16i8);
return Result;
}
@@ -6556,10 +6556,10 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vmrglw_unary_shuffle>>
// Emits: (VMRGLW:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
// Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vmrglw_unary_shuffle(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
+ if (Predicate_vmrglw_unary_shuffle(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
SDNode *Result = Emit_85(N, PPC::VMRGLW, MVT::v16i8);
return Result;
}
@@ -6568,10 +6568,10 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vmrghb_unary_shuffle>>
// Emits: (VMRGHB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
// Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vmrghb_unary_shuffle(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
+ if (Predicate_vmrghb_unary_shuffle(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
SDNode *Result = Emit_85(N, PPC::VMRGHB, MVT::v16i8);
return Result;
}
@@ -6580,10 +6580,10 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vmrghh_unary_shuffle>>
// Emits: (VMRGHH:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
// Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vmrghh_unary_shuffle(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
+ if (Predicate_vmrghh_unary_shuffle(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
SDNode *Result = Emit_85(N, PPC::VMRGHH, MVT::v16i8);
return Result;
}
@@ -6592,10 +6592,10 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, (undef:v16i8))<<P:Predicate_vmrghw_unary_shuffle>>
// Emits: (VMRGHW:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
// Pattern complexity = 7 cost = 1 size = 0
- if (Predicate_vmrghw_unary_shuffle(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
+ if (Predicate_vmrghw_unary_shuffle(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
SDNode *Result = Emit_85(N, PPC::VMRGHW, MVT::v16i8);
return Result;
}
@@ -6604,7 +6604,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vsldoi_shuffle>><<X:VSLDOI_get_imm>>:$SH
// Emits: (VSLDOI:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB, (VSLDOI_get_imm:i32 (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB):$SH))
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_vsldoi_shuffle(N.getNode())) {
+ if (Predicate_vsldoi_shuffle(N)) {
SDNode *Result = Emit_80(N, PPC::VSLDOI, MVT::v16i8);
return Result;
}
@@ -6612,7 +6612,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vmrghb_shuffle>>
// Emits: (VMRGHB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_vmrghb_shuffle(N.getNode())) {
+ if (Predicate_vmrghb_shuffle(N)) {
SDNode *Result = Emit_3(N, PPC::VMRGHB, MVT::v16i8);
return Result;
}
@@ -6620,7 +6620,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vmrghh_shuffle>>
// Emits: (VMRGHH:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_vmrghh_shuffle(N.getNode())) {
+ if (Predicate_vmrghh_shuffle(N)) {
SDNode *Result = Emit_3(N, PPC::VMRGHH, MVT::v16i8);
return Result;
}
@@ -6628,7 +6628,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vmrghw_shuffle>>
// Emits: (VMRGHW:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_vmrghw_shuffle(N.getNode())) {
+ if (Predicate_vmrghw_shuffle(N)) {
SDNode *Result = Emit_3(N, PPC::VMRGHW, MVT::v16i8);
return Result;
}
@@ -6636,7 +6636,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vmrglb_shuffle>>
// Emits: (VMRGLB:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_vmrglb_shuffle(N.getNode())) {
+ if (Predicate_vmrglb_shuffle(N)) {
SDNode *Result = Emit_3(N, PPC::VMRGLB, MVT::v16i8);
return Result;
}
@@ -6644,7 +6644,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vmrglh_shuffle>>
// Emits: (VMRGLH:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_vmrglh_shuffle(N.getNode())) {
+ if (Predicate_vmrglh_shuffle(N)) {
SDNode *Result = Emit_3(N, PPC::VMRGLH, MVT::v16i8);
return Result;
}
@@ -6652,7 +6652,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vmrglw_shuffle>>
// Emits: (VMRGLW:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_vmrglw_shuffle(N.getNode())) {
+ if (Predicate_vmrglw_shuffle(N)) {
SDNode *Result = Emit_3(N, PPC::VMRGLW, MVT::v16i8);
return Result;
}
@@ -6660,7 +6660,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vpkuhum_shuffle>>
// Emits: (VPKUHUM:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_vpkuhum_shuffle(N.getNode())) {
+ if (Predicate_vpkuhum_shuffle(N)) {
SDNode *Result = Emit_3(N, PPC::VPKUHUM, MVT::v16i8);
return Result;
}
@@ -6668,7 +6668,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)<<P:Predicate_vpkuwum_shuffle>>
// Emits: (VPKUWUM:v16i8 VRRC:v16i8:$vA, VRRC:v16i8:$vB)
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_vpkuwum_shuffle(N.getNode())) {
+ if (Predicate_vpkuwum_shuffle(N)) {
SDNode *Result = Emit_3(N, PPC::VPKUWUM, MVT::v16i8);
return Result;
}
@@ -6677,39 +6677,39 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_86(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N01);
-}
-DISABLE_INLINE SDNode *Emit_87(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N1);
-}
-DISABLE_INLINE SDNode *Emit_88(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N0);
-}
-SDNode *Select_ISD_XOR_i32(const SDValue &N) {
+DISABLE_INLINE SDNode *Emit_86(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, N01);
+}
+DISABLE_INLINE SDNode *Emit_87(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, N1);
+}
+DISABLE_INLINE SDNode *Emit_88(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N10, N0);
+}
+SDNode *Select_ISD_XOR_i32(SDNode *N) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (xor:i32 (and:i32 GPRC:i32:$rS, GPRC:i32:$rB), (imm:i32)<<P:Predicate_immAllOnes>>)
// Emits: (NAND:i32 GPRC:i32:$rS, GPRC:i32:$rB)
// Pattern complexity = 10 cost = 1 size = 0
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N1.getNode())) {
SDNode *Result = Emit_86(N, PPC::NAND, MVT::i32);
return Result;
@@ -6719,26 +6719,26 @@ SDNode *Select_ISD_XOR_i32(const SDValue &N) {
// Pattern: (xor:i32 (or:i32 GPRC:i32:$rS, GPRC:i32:$rB), (imm:i32)<<P:Predicate_immAllOnes>>)
// Emits: (NOR:i32 GPRC:i32:$rS, GPRC:i32:$rB)
// Pattern complexity = 10 cost = 1 size = 0
- if (N0.getOpcode() == ISD::OR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N1.getNode())) {
SDNode *Result = Emit_86(N, PPC::NOR, MVT::i32);
return Result;
}
}
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
// Pattern: (xor:i32 (xor:i32 GPRC:i32:$rS, GPRC:i32:$rB), (imm:i32)<<P:Predicate_immAllOnes>>)
// Emits: (EQV:i32 GPRC:i32:$rS, GPRC:i32:$rB)
// Pattern complexity = 10 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N1.getNode())) {
SDNode *Result = Emit_86(N, PPC::EQV, MVT::i32);
return Result;
@@ -6748,27 +6748,27 @@ SDNode *Select_ISD_XOR_i32(const SDValue &N) {
// Pattern: (xor:i32 (xor:i32 GPRC:i32:$rS, (imm:i32)<<P:Predicate_immAllOnes>>), GPRC:i32:$rB)
// Emits: (EQV:i32 GPRC:i32:$rS, GPRC:i32:$rB)
// Pattern complexity = 10 cost = 1 size = 0
- if (N01.getOpcode() == ISD::Constant &&
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N01.getNode())) {
SDNode *Result = Emit_87(N, PPC::EQV, MVT::i32);
return Result;
}
}
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
// Pattern: (xor:i32 GPRC:i32:$rB, (xor:i32 GPRC:i32:$rS, (imm:i32)<<P:Predicate_immAllOnes>>))
// Emits: (EQV:i32 GPRC:i32:$rS, GPRC:i32:$rB)
// Pattern complexity = 10 cost = 1 size = 0
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N11.getNode())) {
SDNode *Result = Emit_88(N, PPC::EQV, MVT::i32);
return Result;
}
}
- if (N1.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (xor:i32 GPRC:i32:$src1, (imm:i32)<<P:Predicate_immZExt16>><<X:LO16>>:$src2)
// Emits: (XORI:i32 GPRC:i32:$src1, (LO16:i32 (imm:i32):$src2))
@@ -6809,18 +6809,18 @@ SDNode *Select_ISD_XOR_i32(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_XOR_i64(const SDValue &N) {
+SDNode *Select_ISD_XOR_i64(SDNode *N) {
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (xor:i64 (and:i64 G8RC:i64:$rS, G8RC:i64:$rB), (imm:i64)<<P:Predicate_immAllOnes>>)
// Emits: (NAND8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
// Pattern complexity = 10 cost = 1 size = 0
- if (N0.getOpcode() == ISD::AND) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::AND) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N1.getNode())) {
SDNode *Result = Emit_86(N, PPC::NAND8, MVT::i64);
return Result;
@@ -6830,26 +6830,26 @@ SDNode *Select_ISD_XOR_i64(const SDValue &N) {
// Pattern: (xor:i64 (or:i64 G8RC:i64:$rS, G8RC:i64:$rB), (imm:i64)<<P:Predicate_immAllOnes>>)
// Emits: (NOR8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
// Pattern complexity = 10 cost = 1 size = 0
- if (N0.getOpcode() == ISD::OR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ if (N0.getNode()->getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N1.getNode())) {
SDNode *Result = Emit_86(N, PPC::NOR8, MVT::i64);
return Result;
}
}
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
// Pattern: (xor:i64 (xor:i64 G8RC:i64:$rS, G8RC:i64:$rB), (imm:i64)<<P:Predicate_immAllOnes>>)
// Emits: (EQV8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
// Pattern complexity = 10 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N1.getNode())) {
SDNode *Result = Emit_86(N, PPC::EQV8, MVT::i64);
return Result;
@@ -6859,27 +6859,27 @@ SDNode *Select_ISD_XOR_i64(const SDValue &N) {
// Pattern: (xor:i64 (xor:i64 G8RC:i64:$rS, (imm:i64)<<P:Predicate_immAllOnes>>), G8RC:i64:$rB)
// Emits: (EQV8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
// Pattern complexity = 10 cost = 1 size = 0
- if (N01.getOpcode() == ISD::Constant &&
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N01.getNode())) {
SDNode *Result = Emit_87(N, PPC::EQV8, MVT::i64);
return Result;
}
}
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
// Pattern: (xor:i64 G8RC:i64:$rB, (xor:i64 G8RC:i64:$rS, (imm:i64)<<P:Predicate_immAllOnes>>))
// Emits: (EQV8:i64 G8RC:i64:$rS, G8RC:i64:$rB)
// Pattern complexity = 10 cost = 1 size = 0
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N11.getNode())) {
SDNode *Result = Emit_88(N, PPC::EQV8, MVT::i64);
return Result;
}
}
- if (N1.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (xor:i64 G8RC:i64:$src1, (imm:i64)<<P:Predicate_immZExt16>><<X:LO16>>:$src2)
// Emits: (XORI8:i64 G8RC:i64:$src1, (LO16:i32 (imm:i64):$src2))
@@ -6906,30 +6906,30 @@ SDNode *Select_ISD_XOR_i64(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_89(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N11);
+DISABLE_INLINE SDNode *Emit_89(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N10, N11);
}
-DISABLE_INLINE SDNode *Emit_90(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N1);
+DISABLE_INLINE SDNode *Emit_90(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N1);
}
-SDNode *Select_ISD_XOR_v4i32(const SDValue &N) {
+SDNode *Select_ISD_XOR_v4i32(SDNode *N) {
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::OR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::OR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
// Pattern: (xor:v4i32 (or:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB), (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)
// Emits: (VNOR:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 10 cost = 1 size = 0
- if (N1.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N1.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N1.getNode())) {
SDNode *Result = Emit_86(N, PPC::VNOR, MVT::v4i32);
return Result;
@@ -6938,7 +6938,7 @@ SDNode *Select_ISD_XOR_v4i32(const SDValue &N) {
// Pattern: (xor:v4i32 (or:v4i32 VRRC:v4i32:$A, VRRC:v4i32:$B), (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>)
// Emits: (VNOR:v4i32 VRRC:v16i8:$A, VRRC:v16i8:$B)
// Pattern complexity = 10 cost = 1 size = 0
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N1.getNode())) {
SDNode *Result = Emit_86(N, PPC::VNOR, MVT::v4i32);
return Result;
@@ -6948,10 +6948,10 @@ SDNode *Select_ISD_XOR_v4i32(const SDValue &N) {
// Pattern: (xor:v4i32 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>, (or:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB))
// Emits: (VNOR:v4i32 VRRC:v4i32:$vA, VRRC:v4i32:$vB)
// Pattern complexity = 10 cost = 1 size = 0
- if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N0.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::OR) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::OR) {
SDNode *Result = Emit_89(N, PPC::VNOR, MVT::v4i32);
return Result;
}
@@ -6960,21 +6960,21 @@ SDNode *Select_ISD_XOR_v4i32(const SDValue &N) {
// Pattern: (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, (or:v4i32 VRRC:v4i32:$A, VRRC:v4i32:$B))
// Emits: (VNOR:v4i32 VRRC:v16i8:$A, VRRC:v16i8:$B)
// Pattern complexity = 10 cost = 1 size = 0
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N0.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::OR) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::OR) {
SDNode *Result = Emit_89(N, PPC::VNOR, MVT::v4i32);
return Result;
}
}
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
// Pattern: (xor:v4i32 VRRC:v4i32:$vA, (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)
// Emits: (VNOR:v4i32 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
// Pattern complexity = 7 cost = 1 size = 0
- if (N1.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N1.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N1.getNode())) {
SDNode *Result = Emit_85(N, PPC::VNOR, MVT::v4i32);
return Result;
@@ -6983,7 +6983,7 @@ SDNode *Select_ISD_XOR_v4i32(const SDValue &N) {
// Pattern: (xor:v4i32 VRRC:v4i32:$vA, (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>)
// Emits: (VNOR:v4i32 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
// Pattern complexity = 7 cost = 1 size = 0
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N1.getNode())) {
SDNode *Result = Emit_85(N, PPC::VNOR, MVT::v4i32);
return Result;
@@ -6993,7 +6993,7 @@ SDNode *Select_ISD_XOR_v4i32(const SDValue &N) {
// Pattern: (xor:v4i32 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>, VRRC:v4i32:$vA)
// Emits: (VNOR:v4i32 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
// Pattern complexity = 7 cost = 1 size = 0
- if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N0.getNode())) {
SDNode *Result = Emit_90(N, PPC::VNOR, MVT::v4i32);
return Result;
@@ -7002,7 +7002,7 @@ SDNode *Select_ISD_XOR_v4i32(const SDValue &N) {
// Pattern: (xor:v4i32 (bitconvert:v4i32)<<P:Predicate_immAllOnesV_bc>>, VRRC:v4i32:$vA)
// Emits: (VNOR:v4i32 VRRC:v16i8:$vA, VRRC:v16i8:$vA)
// Pattern complexity = 7 cost = 1 size = 0
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N0.getNode())) {
SDNode *Result = Emit_90(N, PPC::VNOR, MVT::v4i32);
return Result;
@@ -7016,15 +7016,15 @@ SDNode *Select_ISD_XOR_v4i32(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_91(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, N0), 0);
+DISABLE_INLINE SDNode *Emit_91(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, N0), 0);
SDValue Tmp3 = CurDAG->getTargetConstant(0x0ULL, MVT::i32);
SDValue Tmp4 = CurDAG->getTargetConstant(0x20ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2, Tmp3, Tmp4);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2, Tmp3, Tmp4);
}
-SDNode *Select_ISD_ZERO_EXTEND_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_ZERO_EXTEND_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_91(N, PPC::OR4To8, PPC::RLDICL, MVT::i64, MVT::i64);
return Result;
@@ -7034,26 +7034,26 @@ SDNode *Select_ISD_ZERO_EXTEND_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_92(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N.getOperand(0);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_92(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N->getOperand(0);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SmallVector<SDValue, 8> Ops0;
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
- for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N.getOperand(i));
+ for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N->getOperand(i));
}
Ops0.push_back(Chain);
if (HasInFlag)
Ops0.push_back(InFlag);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -7062,7 +7062,7 @@ DISABLE_INLINE SDNode *Emit_92(const SDValue &N, unsigned Opc0, unsigned NumInpu
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_PPCISD_BCTRL_Darwin(const SDValue &N) {
+SDNode *Select_PPCISD_BCTRL_Darwin(SDNode *N) {
// Pattern: (PPCbctrl_Darwin:isVoid)
// Emits: (BCTRL_Darwin:isVoid)
@@ -7084,7 +7084,7 @@ SDNode *Select_PPCISD_BCTRL_Darwin(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_BCTRL_SVR4(const SDValue &N) {
+SDNode *Select_PPCISD_BCTRL_SVR4(SDNode *N) {
// Pattern: (PPCbctrl_SVR4:isVoid)
// Emits: (BCTRL_SVR4:isVoid)
@@ -7106,29 +7106,29 @@ SDNode *Select_PPCISD_BCTRL_SVR4(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_93(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_93(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SmallVector<SDValue, 8> Ops0;
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
Ops0.push_back(Tmp0);
- for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N.getOperand(i));
+ for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N->getOperand(i));
}
Ops0.push_back(Chain);
if (HasInFlag)
Ops0.push_back(InFlag);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -7137,29 +7137,29 @@ DISABLE_INLINE SDNode *Emit_93(const SDValue &N, unsigned Opc0, unsigned NumInpu
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_94(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_94(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SmallVector<SDValue, 8> Ops0;
SDValue Tmp0 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
Ops0.push_back(Tmp0);
- for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N.getOperand(i));
+ for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N->getOperand(i));
}
Ops0.push_back(Chain);
if (HasInFlag)
Ops0.push_back(InFlag);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -7168,28 +7168,28 @@ DISABLE_INLINE SDNode *Emit_94(const SDValue &N, unsigned Opc0, unsigned NumInpu
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_95(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_95(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SmallVector<SDValue, 8> Ops0;
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
Ops0.push_back(N1);
- for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N.getOperand(i));
+ for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N->getOperand(i));
}
Ops0.push_back(Chain);
if (HasInFlag)
Ops0.push_back(InFlag);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -7198,10 +7198,10 @@ DISABLE_INLINE SDNode *Emit_95(const SDValue &N, unsigned Opc0, unsigned NumInpu
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_PPCISD_CALL_Darwin(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+SDNode *Select_PPCISD_CALL_Darwin(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (PPCcall_Darwin:isVoid (imm:i32):$func)
// Emits: (BLA_Darwin:isVoid (imm:i32):$func)
@@ -7223,7 +7223,7 @@ SDNode *Select_PPCISD_CALL_Darwin(const SDValue &N) {
// Pattern: (PPCcall_Darwin:isVoid (tglobaladdr:i64):$dst)
// Emits: (BL8_Darwin:isVoid (tglobaladdr:iPTR):$dst)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::TargetGlobalAddress &&
+ if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress &&
N1.getValueType() == MVT::i64) {
SDNode *Result = Emit_95(N, PPC::BL8_Darwin, 1);
return Result;
@@ -7232,7 +7232,7 @@ SDNode *Select_PPCISD_CALL_Darwin(const SDValue &N) {
// Pattern: (PPCcall_Darwin:isVoid (texternalsym:i64):$dst)
// Emits: (BL8_Darwin:isVoid (texternalsym:iPTR):$dst)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::TargetExternalSymbol &&
+ if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol &&
N1.getValueType() == MVT::i64) {
SDNode *Result = Emit_95(N, PPC::BL8_Darwin, 1);
return Result;
@@ -7241,7 +7241,7 @@ SDNode *Select_PPCISD_CALL_Darwin(const SDValue &N) {
// Pattern: (PPCcall_Darwin:isVoid (tglobaladdr:i32):$dst)
// Emits: (BL_Darwin:isVoid (tglobaladdr:iPTR):$dst)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::TargetGlobalAddress &&
+ if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_95(N, PPC::BL_Darwin, 1);
return Result;
@@ -7250,7 +7250,7 @@ SDNode *Select_PPCISD_CALL_Darwin(const SDValue &N) {
// Pattern: (PPCcall_Darwin:isVoid (texternalsym:i32):$dst)
// Emits: (BL_Darwin:isVoid (texternalsym:iPTR):$dst)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::TargetExternalSymbol &&
+ if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_95(N, PPC::BL_Darwin, 1);
return Result;
@@ -7260,10 +7260,10 @@ SDNode *Select_PPCISD_CALL_Darwin(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_CALL_SVR4(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+SDNode *Select_PPCISD_CALL_SVR4(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (PPCcall_SVR4:isVoid (imm:i32):$func)
// Emits: (BLA_SVR4:isVoid (imm:i32):$func)
@@ -7285,7 +7285,7 @@ SDNode *Select_PPCISD_CALL_SVR4(const SDValue &N) {
// Pattern: (PPCcall_SVR4:isVoid (tglobaladdr:i64):$dst)
// Emits: (BL8_ELF:isVoid (tglobaladdr:iPTR):$dst)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::TargetGlobalAddress &&
+ if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress &&
N1.getValueType() == MVT::i64) {
SDNode *Result = Emit_95(N, PPC::BL8_ELF, 1);
return Result;
@@ -7294,7 +7294,7 @@ SDNode *Select_PPCISD_CALL_SVR4(const SDValue &N) {
// Pattern: (PPCcall_SVR4:isVoid (texternalsym:i64):$dst)
// Emits: (BL8_ELF:isVoid (texternalsym:iPTR):$dst)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::TargetExternalSymbol &&
+ if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol &&
N1.getValueType() == MVT::i64) {
SDNode *Result = Emit_95(N, PPC::BL8_ELF, 1);
return Result;
@@ -7303,7 +7303,7 @@ SDNode *Select_PPCISD_CALL_SVR4(const SDValue &N) {
// Pattern: (PPCcall_SVR4:isVoid (tglobaladdr:i32):$dst)
// Emits: (BL_SVR4:isVoid (tglobaladdr:iPTR):$dst)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::TargetGlobalAddress &&
+ if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_95(N, PPC::BL_SVR4, 1);
return Result;
@@ -7312,7 +7312,7 @@ SDNode *Select_PPCISD_CALL_SVR4(const SDValue &N) {
// Pattern: (PPCcall_SVR4:isVoid (texternalsym:i32):$dst)
// Emits: (BL_SVR4:isVoid (texternalsym:iPTR):$dst)
// Pattern complexity = 6 cost = 1 size = 0
- if (N1.getOpcode() == ISD::TargetExternalSymbol &&
+ if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_95(N, PPC::BL_SVR4, 1);
return Result;
@@ -7322,17 +7322,17 @@ SDNode *Select_PPCISD_CALL_SVR4(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_96(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_96(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 4);
}
-SDNode *Select_PPCISD_DYNALLOC_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+SDNode *Select_PPCISD_DYNALLOC_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
@@ -7346,10 +7346,10 @@ SDNode *Select_PPCISD_DYNALLOC_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_DYNALLOC_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+SDNode *Select_PPCISD_DYNALLOC_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrImm(N, N2, CPTmpN2_0, CPTmpN2_1) &&
@@ -7363,56 +7363,56 @@ SDNode *Select_PPCISD_DYNALLOC_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_EXTSW_32_i32(const SDValue &N) {
+SDNode *Select_PPCISD_EXTSW_32_i32(SDNode *N) {
SDNode *Result = Emit_29(N, PPC::EXTSW_32, MVT::i32);
return Result;
}
-SDNode *Select_PPCISD_FADDRTZ_f64(const SDValue &N) {
+SDNode *Select_PPCISD_FADDRTZ_f64(SDNode *N) {
SDNode *Result = Emit_11(N, PPC::FADDrtz, MVT::f64);
return Result;
}
-SDNode *Select_PPCISD_FCFID_f64(const SDValue &N) {
+SDNode *Select_PPCISD_FCFID_f64(SDNode *N) {
SDNode *Result = Emit_29(N, PPC::FCFID, MVT::f64);
return Result;
}
-SDNode *Select_PPCISD_FCTIDZ_f64(const SDValue &N) {
+SDNode *Select_PPCISD_FCTIDZ_f64(SDNode *N) {
SDNode *Result = Emit_29(N, PPC::FCTIDZ, MVT::f64);
return Result;
}
-SDNode *Select_PPCISD_FCTIWZ_f64(const SDValue &N) {
+SDNode *Select_PPCISD_FCTIWZ_f64(SDNode *N) {
SDNode *Result = Emit_29(N, PPC::FCTIWZ, MVT::f64);
return Result;
}
-DISABLE_INLINE SDNode *Emit_97(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, N2);
+DISABLE_INLINE SDNode *Emit_97(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, N2);
}
-SDNode *Select_PPCISD_FSEL_f32(const SDValue &N) {
+SDNode *Select_PPCISD_FSEL_f32(SDNode *N) {
SDNode *Result = Emit_97(N, PPC::FSELS, MVT::f32);
return Result;
}
-SDNode *Select_PPCISD_FSEL_f64(const SDValue &N) {
+SDNode *Select_PPCISD_FSEL_f64(SDNode *N) {
SDNode *Result = Emit_97(N, PPC::FSELD, MVT::f64);
return Result;
}
-SDNode *Select_PPCISD_Hi_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_PPCISD_Hi_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (PPChi:i32 (tglobaladdr:i32):$in, 0:i32)
// Emits: (LIS:i32 (tglobaladdr:i32):$in)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -7425,9 +7425,9 @@ SDNode *Select_PPCISD_Hi_i32(const SDValue &N) {
// Pattern: (PPChi:i32 (tconstpool:i32):$in, 0:i32)
// Emits: (LIS:i32 (tconstpool:i32):$in)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::TargetConstantPool) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -7440,9 +7440,9 @@ SDNode *Select_PPCISD_Hi_i32(const SDValue &N) {
// Pattern: (PPChi:i32 (tjumptable:i32):$in, 0:i32)
// Emits: (LIS:i32 (tjumptable:i32):$in)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::TargetJumpTable) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -7455,9 +7455,9 @@ SDNode *Select_PPCISD_Hi_i32(const SDValue &N) {
// Pattern: (PPChi:i32 (tblockaddress:i32):$in, 0:i32)
// Emits: (LIS:i32 (tblockaddress:i32):$in)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::TargetBlockAddress) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::TargetBlockAddress) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -7471,15 +7471,15 @@ SDNode *Select_PPCISD_Hi_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_Hi_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_PPCISD_Hi_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (PPChi:i64 (tglobaladdr:i64):$in, 0:i64)
// Emits: (LIS8:i64 (tglobaladdr:i64):$in)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -7492,9 +7492,9 @@ SDNode *Select_PPCISD_Hi_i64(const SDValue &N) {
// Pattern: (PPChi:i64 (tconstpool:i64):$in, 0:i64)
// Emits: (LIS8:i64 (tconstpool:i64):$in)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::TargetConstantPool) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -7507,9 +7507,9 @@ SDNode *Select_PPCISD_Hi_i64(const SDValue &N) {
// Pattern: (PPChi:i64 (tjumptable:i64):$in, 0:i64)
// Emits: (LIS8:i64 (tjumptable:i64):$in)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::TargetJumpTable) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -7522,9 +7522,9 @@ SDNode *Select_PPCISD_Hi_i64(const SDValue &N) {
// Pattern: (PPChi:i64 (tblockaddress:i64):$in, 0:i64)
// Emits: (LIS8:i64 (tblockaddress:i64):$in)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::TargetBlockAddress) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::TargetBlockAddress) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -7538,14 +7538,14 @@ SDNode *Select_PPCISD_Hi_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_98(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, CPTmpN1_0, CPTmpN1_1, Chain);
+DISABLE_INLINE SDNode *Emit_98(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, CPTmpN1_0, CPTmpN1_1, Chain);
}
-SDNode *Select_PPCISD_LARX_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_PPCISD_LARX_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -7557,9 +7557,9 @@ SDNode *Select_PPCISD_LARX_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_LARX_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_PPCISD_LARX_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
@@ -7571,24 +7571,24 @@ SDNode *Select_PPCISD_LARX_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_99(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, CPTmpN1_0, CPTmpN1_1, Chain);
+DISABLE_INLINE SDNode *Emit_99(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, CPTmpN1_0, CPTmpN1_1, Chain);
}
-SDNode *Select_PPCISD_LBRX_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_PPCISD_LBRX_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectAddrIdxOnly(N, N1, CPTmpN1_0, CPTmpN1_1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
// Pattern: (PPClbrx:i32 xoaddr:iPTR:$src, i16:Other)
// Emits: (LHBRX:i32 xoaddr:iPTR:$src)
// Pattern complexity = 12 cost = 1 size = 0
- if (cast<VTSDNode>(N2)->getVT() == MVT::i16) {
+ if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i16) {
SDNode *Result = Emit_99(N, PPC::LHBRX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
return Result;
}
@@ -7596,7 +7596,7 @@ SDNode *Select_PPCISD_LBRX_i32(const SDValue &N) {
// Pattern: (PPClbrx:i32 xoaddr:iPTR:$src, i32:Other)
// Emits: (LWBRX:i32 xoaddr:iPTR:$src)
// Pattern complexity = 12 cost = 1 size = 0
- if (cast<VTSDNode>(N2)->getVT() == MVT::i32) {
+ if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i32) {
SDNode *Result = Emit_99(N, PPC::LWBRX, MVT::i32, CPTmpN1_0, CPTmpN1_1);
return Result;
}
@@ -7606,21 +7606,21 @@ SDNode *Select_PPCISD_LBRX_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_100(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_100(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, Chain, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 4 : 3);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 4 : 3);
Chain = SDValue(ResNode, 1);
InFlag = SDValue(ResNode, 2);
const SDValue Froms[] = {
- SDValue(N.getNode(), 2),
- SDValue(N.getNode(), 1)
+ SDValue(N, 2),
+ SDValue(N, 1)
};
const SDValue Tos[] = {
InFlag,
@@ -7629,9 +7629,9 @@ DISABLE_INLINE SDNode *Emit_100(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_PPCISD_LOAD_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_PPCISD_LOAD_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
@@ -7657,16 +7657,16 @@ SDNode *Select_PPCISD_LOAD_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_101(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue InFlag = N.getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, N1, Chain, InFlag);
+DISABLE_INLINE SDNode *Emit_101(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue InFlag = N->getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, N1, Chain, InFlag);
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -7675,9 +7675,9 @@ DISABLE_INLINE SDNode *Emit_101(const SDValue &N, unsigned Opc0) {
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_PPCISD_LOAD_TOC(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_PPCISD_LOAD_TOC(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i64) {
SDNode *Result = Emit_101(N, PPC::LDinto_toc);
return Result;
@@ -7687,15 +7687,15 @@ SDNode *Select_PPCISD_LOAD_TOC(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_Lo_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_PPCISD_Lo_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (PPClo:i32 (tglobaladdr:i32):$in, 0:i32)
// Emits: (LI:i32 (tglobaladdr:i32):$in)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -7708,9 +7708,9 @@ SDNode *Select_PPCISD_Lo_i32(const SDValue &N) {
// Pattern: (PPClo:i32 (tconstpool:i32):$in, 0:i32)
// Emits: (LI:i32 (tconstpool:i32):$in)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::TargetConstantPool) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -7723,9 +7723,9 @@ SDNode *Select_PPCISD_Lo_i32(const SDValue &N) {
// Pattern: (PPClo:i32 (tjumptable:i32):$in, 0:i32)
// Emits: (LI:i32 (tjumptable:i32):$in)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::TargetJumpTable) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -7738,9 +7738,9 @@ SDNode *Select_PPCISD_Lo_i32(const SDValue &N) {
// Pattern: (PPClo:i32 (tblockaddress:i32):$in, 0:i32)
// Emits: (LI:i32 (tblockaddress:i32):$in)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::TargetBlockAddress) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::TargetBlockAddress) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -7754,15 +7754,15 @@ SDNode *Select_PPCISD_Lo_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_Lo_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_PPCISD_Lo_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (PPClo:i64 (tglobaladdr:i64):$in, 0:i64)
// Emits: (LI8:i64 (tglobaladdr:i64):$in)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -7775,9 +7775,9 @@ SDNode *Select_PPCISD_Lo_i64(const SDValue &N) {
// Pattern: (PPClo:i64 (tconstpool:i64):$in, 0:i64)
// Emits: (LI8:i64 (tconstpool:i64):$in)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::TargetConstantPool) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -7790,9 +7790,9 @@ SDNode *Select_PPCISD_Lo_i64(const SDValue &N) {
// Pattern: (PPClo:i64 (tjumptable:i64):$in, 0:i64)
// Emits: (LI8:i64 (tjumptable:i64):$in)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::TargetJumpTable) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -7805,9 +7805,9 @@ SDNode *Select_PPCISD_Lo_i64(const SDValue &N) {
// Pattern: (PPClo:i64 (tblockaddress:i64):$in, 0:i64)
// Emits: (LI8:i64 (tblockaddress:i64):$in)
// Pattern complexity = 11 cost = 1 size = 0
- if (N0.getOpcode() == ISD::TargetBlockAddress) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ if (N0.getNode()->getOpcode() == ISD::TargetBlockAddress) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -7821,32 +7821,32 @@ SDNode *Select_PPCISD_Lo_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_102(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag);
+DISABLE_INLINE SDNode *Emit_102(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-SDNode *Select_PPCISD_MFFS_f64(const SDValue &N) {
+SDNode *Select_PPCISD_MFFS_f64(SDNode *N) {
SDNode *Result = Emit_102(N, PPC::MFFS, MVT::f64);
return Result;
}
-DISABLE_INLINE SDNode *Emit_103(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_103(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
SDValue Ops0[] = { N1, Chain, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 3 : 2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 3 : 2);
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -7855,9 +7855,9 @@ DISABLE_INLINE SDNode *Emit_103(const SDValue &N, unsigned Opc0) {
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_PPCISD_MTCTR(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_PPCISD_MTCTR(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (PPCmtctr:isVoid GPRC:i32:$rS)
// Emits: (MTCTR:isVoid GPRC:i32:$rS)
@@ -7879,18 +7879,18 @@ SDNode *Select_PPCISD_MTCTR(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_104(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
+DISABLE_INLINE SDNode *Emit_104(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
- SDValue InFlag = N.getOperand(1);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, Tmp0, InFlag);
+ SDValue InFlag = N->getOperand(1);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, Tmp0, InFlag);
InFlag = SDValue(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ ReplaceUses(SDValue(N, 0), InFlag);
return ResNode;
}
-SDNode *Select_PPCISD_MTFSB0(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::Constant &&
+SDNode *Select_PPCISD_MTFSB0(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_104(N, PPC::MTFSB0);
return Result;
@@ -7900,9 +7900,9 @@ SDNode *Select_PPCISD_MTFSB0(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_MTFSB1(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::Constant &&
+SDNode *Select_PPCISD_MTFSB1(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_104(N, PPC::MTFSB1);
return Result;
@@ -7912,20 +7912,20 @@ SDNode *Select_PPCISD_MTFSB1(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_105(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_105(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N0)->getZExtValue()), MVT::i32);
- SDValue InFlag = N.getOperand(3);
+ SDValue InFlag = N->getOperand(3);
SDValue Ops0[] = { Tmp0, N1, N2, InFlag };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-SDNode *Select_PPCISD_MTFSF_f64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+SDNode *Select_PPCISD_MTFSF_f64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_105(N, PPC::MTFSF, MVT::f64);
return Result;
@@ -7936,38 +7936,38 @@ SDNode *Select_PPCISD_MTFSF_f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_106(const SDValue &N, unsigned Opc0) {
- SDValue InFlag = N.getOperand(0);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Flag, InFlag);
+DISABLE_INLINE SDNode *Emit_106(SDNode *N, unsigned Opc0) {
+ SDValue InFlag = N->getOperand(0);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Flag, InFlag);
InFlag = SDValue(ResNode, 0);
- ReplaceUses(SDValue(N.getNode(), 0), InFlag);
+ ReplaceUses(SDValue(N, 0), InFlag);
return ResNode;
}
-SDNode *Select_PPCISD_NOP(const SDValue &N) {
+SDNode *Select_PPCISD_NOP(SDNode *N) {
SDNode *Result = Emit_106(N, PPC::NOP);
return Result;
}
-DISABLE_INLINE SDNode *Emit_107(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_107(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SDValue Tmp0 = CurDAG->getTargetConstant(0x14ULL, MVT::i32);
SDValue Tmp1 = CurDAG->getRegister(0, MVT::i32);
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
SDValue Ops0[] = { Tmp0, Tmp1, Chain, InFlag };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, HasInFlag ? 4 : 3);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, HasInFlag ? 4 : 3);
}
-SDNode *Select_PPCISD_RET_FLAG(const SDValue &N) {
+SDNode *Select_PPCISD_RET_FLAG(SDNode *N) {
SDNode *Result = Emit_107(N, PPC::BLR);
return Result;
}
-SDNode *Select_PPCISD_SHL_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_PPCISD_SHL_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_3(N, PPC::SLW, MVT::i32);
return Result;
@@ -7977,9 +7977,9 @@ SDNode *Select_PPCISD_SHL_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_SHL_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_PPCISD_SHL_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_3(N, PPC::SLD, MVT::i64);
return Result;
@@ -7989,9 +7989,9 @@ SDNode *Select_PPCISD_SHL_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_SRA_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_PPCISD_SRA_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_3(N, PPC::SRAW, MVT::i32);
return Result;
@@ -8001,9 +8001,9 @@ SDNode *Select_PPCISD_SRA_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_SRA_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_PPCISD_SRA_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_3(N, PPC::SRAD, MVT::i64);
return Result;
@@ -8013,9 +8013,9 @@ SDNode *Select_PPCISD_SRA_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_SRL_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_PPCISD_SRL_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_3(N, PPC::SRW, MVT::i32);
return Result;
@@ -8025,9 +8025,9 @@ SDNode *Select_PPCISD_SRL_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_SRL_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_PPCISD_SRL_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_3(N, PPC::SRD, MVT::i64);
return Result;
@@ -8037,27 +8037,27 @@ SDNode *Select_PPCISD_SRL_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_108(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_108(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 4);
}
-SDNode *Select_PPCISD_STBRX(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+SDNode *Select_PPCISD_STBRX(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
- SDValue N3 = N.getOperand(3);
+ SDValue N3 = N->getOperand(3);
// Pattern: (PPCstbrx:isVoid GPRC:i32:$rS, xoaddr:iPTR:$dst, i16:Other)
// Emits: (STHBRX:isVoid GPRC:i32:$rS, xoaddr:iPTR:$dst)
// Pattern complexity = 12 cost = 1 size = 0
- if (cast<VTSDNode>(N3)->getVT() == MVT::i16) {
+ if (cast<VTSDNode>(N3.getNode())->getVT() == MVT::i16) {
SDNode *Result = Emit_108(N, PPC::STHBRX, CPTmpN2_0, CPTmpN2_1);
return Result;
}
@@ -8065,7 +8065,7 @@ SDNode *Select_PPCISD_STBRX(const SDValue &N) {
// Pattern: (PPCstbrx:isVoid GPRC:i32:$rS, xoaddr:iPTR:$dst, i32:Other)
// Emits: (STWBRX:isVoid GPRC:i32:$rS, xoaddr:iPTR:$dst)
// Pattern complexity = 12 cost = 1 size = 0
- if (cast<VTSDNode>(N3)->getVT() == MVT::i32) {
+ if (cast<VTSDNode>(N3.getNode())->getVT() == MVT::i32) {
SDNode *Result = Emit_108(N, PPC::STWBRX, CPTmpN2_0, CPTmpN2_1);
return Result;
}
@@ -8075,17 +8075,17 @@ SDNode *Select_PPCISD_STBRX(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_109(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_109(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 4);
}
-SDNode *Select_PPCISD_STCX(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+SDNode *Select_PPCISD_STCX(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
@@ -8111,10 +8111,10 @@ SDNode *Select_PPCISD_STCX(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_STD_32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+SDNode *Select_PPCISD_STD_32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
@@ -8140,10 +8140,10 @@ SDNode *Select_PPCISD_STD_32(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_STFIWX(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+SDNode *Select_PPCISD_STFIWX(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
if (SelectAddrIdxOnly(N, N2, CPTmpN2_0, CPTmpN2_1)) {
@@ -8155,77 +8155,77 @@ SDNode *Select_PPCISD_STFIWX(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_110(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_110(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SmallVector<SDValue, 8> Ops0;
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
Ops0.push_back(Tmp0);
Ops0.push_back(Tmp1);
- for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N.getOperand(i));
+ for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N->getOperand(i));
}
Ops0.push_back(Chain);
if (HasInFlag)
Ops0.push_back(InFlag);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, &Ops0[0], Ops0.size());
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, &Ops0[0], Ops0.size());
}
-DISABLE_INLINE SDNode *Emit_111(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_111(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SmallVector<SDValue, 8> Ops0;
SDValue Tmp0 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
Ops0.push_back(Tmp0);
Ops0.push_back(Tmp1);
- for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N.getOperand(i));
+ for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N->getOperand(i));
}
Ops0.push_back(Chain);
if (HasInFlag)
Ops0.push_back(InFlag);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, &Ops0[0], Ops0.size());
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, &Ops0[0], Ops0.size());
}
-DISABLE_INLINE SDNode *Emit_112(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_112(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SmallVector<SDValue, 8> Ops0;
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
Ops0.push_back(N1);
Ops0.push_back(Tmp1);
- for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N.getOperand(i));
+ for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N->getOperand(i));
}
Ops0.push_back(Chain);
if (HasInFlag)
Ops0.push_back(InFlag);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, &Ops0[0], Ops0.size());
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, &Ops0[0], Ops0.size());
}
-SDNode *Select_PPCISD_TC_RETURN(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+SDNode *Select_PPCISD_TC_RETURN(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (PPCtc_return:isVoid (imm:i32):$func, (imm:i32):$offset)
// Emits: (TCRETURNai:isVoid (imm:i32):$func, (imm:i32):$offset)
@@ -8248,9 +8248,9 @@ SDNode *Select_PPCISD_TC_RETURN(const SDValue &N) {
// Pattern: (PPCtc_return:isVoid (tglobaladdr:i64):$dst, (imm:i32):$imm)
// Emits: (TCRETURNdi8:isVoid (tglobaladdr:iPTR):$dst, (imm:i32):$imm)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i64) {
SDNode *Result = Emit_112(N, PPC::TCRETURNdi8, 2);
return Result;
@@ -8260,9 +8260,9 @@ SDNode *Select_PPCISD_TC_RETURN(const SDValue &N) {
// Pattern: (PPCtc_return:isVoid (texternalsym:i64):$dst, (imm:i32):$imm)
// Emits: (TCRETURNdi8:isVoid (texternalsym:iPTR):$dst, (imm:i32):$imm)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ISD::TargetExternalSymbol) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i64) {
SDNode *Result = Emit_112(N, PPC::TCRETURNdi8, 2);
return Result;
@@ -8272,9 +8272,9 @@ SDNode *Select_PPCISD_TC_RETURN(const SDValue &N) {
// Pattern: (PPCtc_return:isVoid (tglobaladdr:i32):$dst, (imm:i32):$imm)
// Emits: (TCRETURNdi:isVoid (tglobaladdr:iPTR):$dst, (imm:i32):$imm)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_112(N, PPC::TCRETURNdi, 2);
return Result;
@@ -8284,16 +8284,16 @@ SDNode *Select_PPCISD_TC_RETURN(const SDValue &N) {
// Pattern: (PPCtc_return:isVoid (texternalsym:i32):$dst, (imm:i32):$imm)
// Emits: (TCRETURNdi:isVoid (texternalsym:iPTR):$dst, (imm:i32):$imm)
// Pattern complexity = 9 cost = 1 size = 0
- if (N1.getOpcode() == ISD::TargetExternalSymbol) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_112(N, PPC::TCRETURNdi, 2);
return Result;
}
}
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (PPCtc_return:isVoid CTRRC8:i64:$dst, (imm:i32):$imm)
// Emits: (TCRETURNri8:isVoid CTRRC8:i64:$dst, (imm:i32):$imm)
@@ -8316,9 +8316,9 @@ SDNode *Select_PPCISD_TC_RETURN(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_TOC_ENTRY_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::TargetGlobalAddress) {
+SDNode *Select_PPCISD_TOC_ENTRY_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
SDNode *Result = Emit_3(N, PPC::LDtoc, MVT::i64);
return Result;
}
@@ -8327,15 +8327,15 @@ SDNode *Select_PPCISD_TOC_ENTRY_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_113(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue InFlag = N.getOperand(1);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Chain, InFlag);
+DISABLE_INLINE SDNode *Emit_113(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue InFlag = N->getOperand(1);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Chain, InFlag);
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -8344,22 +8344,22 @@ DISABLE_INLINE SDNode *Emit_113(const SDValue &N, unsigned Opc0) {
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_PPCISD_TOC_RESTORE(const SDValue &N) {
+SDNode *Select_PPCISD_TOC_RESTORE(SDNode *N) {
SDNode *Result = Emit_113(N, PPC::LDtoc_restore);
return Result;
}
-DISABLE_INLINE SDNode *Emit_114(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1);
+DISABLE_INLINE SDNode *Emit_114(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1);
}
-SDNode *Select_PPCISD_VCMP_v16i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+SDNode *Select_PPCISD_VCMP_v16i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -8392,11 +8392,11 @@ SDNode *Select_PPCISD_VCMP_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_VCMP_v8i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+SDNode *Select_PPCISD_VCMP_v8i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -8429,11 +8429,11 @@ SDNode *Select_PPCISD_VCMP_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_VCMP_v4i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+SDNode *Select_PPCISD_VCMP_v4i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -8466,11 +8466,11 @@ SDNode *Select_PPCISD_VCMP_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_VCMP_v4f32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+SDNode *Select_PPCISD_VCMP_v4f32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -8511,20 +8511,20 @@ SDNode *Select_PPCISD_VCMP_v4f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_115(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, N1);
+DISABLE_INLINE SDNode *Emit_115(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, N1);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-SDNode *Select_PPCISD_VCMPo_v16i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+SDNode *Select_PPCISD_VCMPo_v16i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -8557,11 +8557,11 @@ SDNode *Select_PPCISD_VCMPo_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_VCMPo_v8i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+SDNode *Select_PPCISD_VCMPo_v8i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -8594,11 +8594,11 @@ SDNode *Select_PPCISD_VCMPo_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_VCMPo_v4i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+SDNode *Select_PPCISD_VCMPo_v4i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -8631,11 +8631,11 @@ SDNode *Select_PPCISD_VCMPo_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_VCMPo_v4f32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+SDNode *Select_PPCISD_VCMPo_v4f32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -8676,27 +8676,27 @@ SDNode *Select_PPCISD_VCMPo_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_PPCISD_VMADDFP_v4f32(const SDValue &N) {
+SDNode *Select_PPCISD_VMADDFP_v4f32(SDNode *N) {
SDNode *Result = Emit_97(N, PPC::VMADDFP, MVT::v4f32);
return Result;
}
-SDNode *Select_PPCISD_VNMSUBFP_v4f32(const SDValue &N) {
+SDNode *Select_PPCISD_VNMSUBFP_v4f32(SDNode *N) {
SDNode *Result = Emit_97(N, PPC::VNMSUBFP, MVT::v4f32);
return Result;
}
-SDNode *Select_PPCISD_VPERM_v16i8(const SDValue &N) {
+SDNode *Select_PPCISD_VPERM_v16i8(SDNode *N) {
SDNode *Result = Emit_97(N, PPC::VPERM, MVT::v16i8);
return Result;
}
// The main instruction selector code.
-SDNode *SelectCode(SDValue N) {
- MVT::SimpleValueType NVT = N.getNode()->getValueType(0).getSimpleVT().SimpleTy;
- switch (N.getOpcode()) {
+SDNode *SelectCode(SDNode *N) {
+ MVT::SimpleValueType NVT = N->getValueType(0).getSimpleVT().SimpleTy;
+ switch (N->getOpcode()) {
default:
- assert(!N.isMachineOpcode() && "Node already selected!");
+ assert(!N->isMachineOpcode() && "Node already selected!");
break;
case ISD::EntryToken: // These nodes remain the same.
case ISD::BasicBlock:
@@ -8718,7 +8718,7 @@ SDNode *SelectCode(SDValue N) {
}
case ISD::AssertSext:
case ISD::AssertZext: {
- ReplaceUses(N, N.getOperand(0));
+ ReplaceUses(SDValue(N, 0), N->getOperand(0));
return NULL;
}
case ISD::INLINEASM: return Select_INLINEASM(N);
@@ -9633,9 +9633,9 @@ SDNode *SelectCode(SDValue N) {
}
} // end of big switch.
- if (N.getOpcode() != ISD::INTRINSIC_W_CHAIN &&
- N.getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
- N.getOpcode() != ISD::INTRINSIC_VOID) {
+ if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
+ N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
+ N->getOpcode() != ISD::INTRINSIC_VOID) {
CannotYetSelect(N);
} else {
CannotYetSelectIntrinsic(N);
diff --git a/libclamav/c++/PPCGenInstrInfo.inc b/libclamav/c++/PPCGenInstrInfo.inc
index 80cd4ff..0d5df7d 100644
--- a/libclamav/c++/PPCGenInstrInfo.inc
+++ b/libclamav/c++/PPCGenInstrInfo.inc
@@ -18,8 +18,8 @@ static const TargetRegisterClass* Barriers2[] = { &PPC::CARRYRCRegClass, &PPC::C
static const unsigned ImplicitList6[] = { PPC::X0, PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::LR8, PPC::CTR8, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CARRY, 0 };
static const unsigned ImplicitList7[] = { PPC::CTR, PPC::RM, 0 };
static const TargetRegisterClass* Barriers3[] = { &PPC::CARRYRCRegClass, &PPC::CTRRCRegClass, NULL };
-static const unsigned ImplicitList8[] = { PPC::R0, PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN, PPC::CARRY, 0 };
-static const unsigned ImplicitList9[] = { PPC::R0, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN, PPC::CARRY, 0 };
+static const unsigned ImplicitList8[] = { PPC::R0, PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CARRY, 0 };
+static const unsigned ImplicitList9[] = { PPC::R0, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CARRY, 0 };
static const unsigned ImplicitList10[] = { PPC::RM, 0 };
static const unsigned ImplicitList11[] = { PPC::LR, PPC::RM, 0 };
static const unsigned ImplicitList12[] = { PPC::X1, 0 };
@@ -132,514 +132,515 @@ static const TargetInstrDesc PPCInsts[] = {
{ 8, 1, 1, 52, "IMPLICIT_DEF", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo8 }, // Inst #8 = IMPLICIT_DEF
{ 9, 4, 1, 52, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo24 }, // Inst #9 = SUBREG_TO_REG
{ 10, 3, 1, 52, "COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo20 }, // Inst #10 = COPY_TO_REGCLASS
- { 11, 3, 1, 14, "ADD4", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #11 = ADD4
- { 12, 3, 1, 14, "ADD8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #12 = ADD8
- { 13, 3, 1, 14, "ADDC", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #13 = ADDC
- { 14, 3, 1, 14, "ADDC8", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #14 = ADDC8
- { 15, 3, 1, 14, "ADDE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #15 = ADDE
- { 16, 3, 1, 14, "ADDE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #16 = ADDE8
- { 17, 3, 1, 14, "ADDI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #17 = ADDI
- { 18, 3, 1, 14, "ADDI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #18 = ADDI8
- { 19, 3, 1, 14, "ADDIC", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #19 = ADDIC
- { 20, 3, 1, 14, "ADDIC8", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #20 = ADDIC8
- { 21, 3, 1, 14, "ADDICo", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #21 = ADDICo
- { 22, 3, 1, 14, "ADDIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #22 = ADDIS
- { 23, 3, 1, 14, "ADDIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #23 = ADDIS8
- { 24, 2, 1, 14, "ADDME", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #24 = ADDME
- { 25, 2, 1, 14, "ADDME8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #25 = ADDME8
- { 26, 2, 1, 14, "ADDZE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #26 = ADDZE
- { 27, 2, 1, 14, "ADDZE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #27 = ADDZE8
- { 28, 1, 0, 52, "ADJCALLSTACKDOWN", 0, 0, ImplicitList2, ImplicitList2, NULL, OperandInfo8 }, // Inst #28 = ADJCALLSTACKDOWN
- { 29, 2, 0, 52, "ADJCALLSTACKUP", 0, 0, ImplicitList2, ImplicitList2, NULL, OperandInfo9 }, // Inst #29 = ADJCALLSTACKUP
- { 30, 3, 1, 14, "AND", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #30 = AND
- { 31, 3, 1, 14, "AND8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #31 = AND8
- { 32, 3, 1, 14, "ANDC", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #32 = ANDC
- { 33, 3, 1, 14, "ANDC8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #33 = ANDC8
- { 34, 3, 1, 14, "ANDISo", 0, 0|(1<<3), NULL, ImplicitList3, NULL, OperandInfo4 }, // Inst #34 = ANDISo
- { 35, 3, 1, 14, "ANDISo8", 0, 0|(1<<3), NULL, ImplicitList3, NULL, OperandInfo5 }, // Inst #35 = ANDISo8
- { 36, 3, 1, 14, "ANDIo", 0, 0|(1<<3), NULL, ImplicitList3, NULL, OperandInfo4 }, // Inst #36 = ANDIo
- { 37, 3, 1, 14, "ANDIo8", 0, 0|(1<<3), NULL, ImplicitList3, NULL, OperandInfo5 }, // Inst #37 = ANDIo8
- { 38, 5, 1, 52, "ATOMIC_CMP_SWAP_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo10 }, // Inst #38 = ATOMIC_CMP_SWAP_I16
- { 39, 5, 1, 52, "ATOMIC_CMP_SWAP_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo10 }, // Inst #39 = ATOMIC_CMP_SWAP_I32
- { 40, 5, 1, 52, "ATOMIC_CMP_SWAP_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo11 }, // Inst #40 = ATOMIC_CMP_SWAP_I64
- { 41, 5, 1, 52, "ATOMIC_CMP_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo10 }, // Inst #41 = ATOMIC_CMP_SWAP_I8
- { 42, 4, 1, 52, "ATOMIC_LOAD_ADD_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #42 = ATOMIC_LOAD_ADD_I16
- { 43, 4, 1, 52, "ATOMIC_LOAD_ADD_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #43 = ATOMIC_LOAD_ADD_I32
- { 44, 4, 1, 52, "ATOMIC_LOAD_ADD_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #44 = ATOMIC_LOAD_ADD_I64
- { 45, 4, 1, 52, "ATOMIC_LOAD_ADD_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #45 = ATOMIC_LOAD_ADD_I8
- { 46, 4, 1, 52, "ATOMIC_LOAD_AND_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #46 = ATOMIC_LOAD_AND_I16
- { 47, 4, 1, 52, "ATOMIC_LOAD_AND_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #47 = ATOMIC_LOAD_AND_I32
- { 48, 4, 1, 52, "ATOMIC_LOAD_AND_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #48 = ATOMIC_LOAD_AND_I64
- { 49, 4, 1, 52, "ATOMIC_LOAD_AND_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #49 = ATOMIC_LOAD_AND_I8
- { 50, 4, 1, 52, "ATOMIC_LOAD_NAND_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #50 = ATOMIC_LOAD_NAND_I16
- { 51, 4, 1, 52, "ATOMIC_LOAD_NAND_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #51 = ATOMIC_LOAD_NAND_I32
- { 52, 4, 1, 52, "ATOMIC_LOAD_NAND_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #52 = ATOMIC_LOAD_NAND_I64
- { 53, 4, 1, 52, "ATOMIC_LOAD_NAND_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #53 = ATOMIC_LOAD_NAND_I8
- { 54, 4, 1, 52, "ATOMIC_LOAD_OR_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #54 = ATOMIC_LOAD_OR_I16
- { 55, 4, 1, 52, "ATOMIC_LOAD_OR_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #55 = ATOMIC_LOAD_OR_I32
- { 56, 4, 1, 52, "ATOMIC_LOAD_OR_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #56 = ATOMIC_LOAD_OR_I64
- { 57, 4, 1, 52, "ATOMIC_LOAD_OR_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #57 = ATOMIC_LOAD_OR_I8
- { 58, 4, 1, 52, "ATOMIC_LOAD_SUB_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #58 = ATOMIC_LOAD_SUB_I16
- { 59, 4, 1, 52, "ATOMIC_LOAD_SUB_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #59 = ATOMIC_LOAD_SUB_I32
- { 60, 4, 1, 52, "ATOMIC_LOAD_SUB_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #60 = ATOMIC_LOAD_SUB_I64
- { 61, 4, 1, 52, "ATOMIC_LOAD_SUB_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #61 = ATOMIC_LOAD_SUB_I8
- { 62, 4, 1, 52, "ATOMIC_LOAD_XOR_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #62 = ATOMIC_LOAD_XOR_I16
- { 63, 4, 1, 52, "ATOMIC_LOAD_XOR_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #63 = ATOMIC_LOAD_XOR_I32
- { 64, 4, 1, 52, "ATOMIC_LOAD_XOR_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #64 = ATOMIC_LOAD_XOR_I64
- { 65, 4, 1, 52, "ATOMIC_LOAD_XOR_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #65 = ATOMIC_LOAD_XOR_I8
- { 66, 4, 1, 52, "ATOMIC_SWAP_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #66 = ATOMIC_SWAP_I16
- { 67, 4, 1, 52, "ATOMIC_SWAP_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #67 = ATOMIC_SWAP_I32
- { 68, 4, 1, 52, "ATOMIC_SWAP_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #68 = ATOMIC_SWAP_I64
- { 69, 4, 1, 52, "ATOMIC_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #69 = ATOMIC_SWAP_I8
- { 70, 1, 0, 0, "B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(7<<3), NULL, NULL, NULL, OperandInfo8 }, // Inst #70 = B
- { 71, 3, 0, 0, "BCC", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, NULL, NULL, OperandInfo14 }, // Inst #71 = BCC
- { 72, 0, 0, 0, "BCTR", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList4, NULL, NULL, 0 }, // Inst #72 = BCTR
- { 73, 0, 0, 0, "BCTRL8_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList5, ImplicitList6, Barriers2, 0 }, // Inst #73 = BCTRL8_Darwin
- { 74, 0, 0, 0, "BCTRL8_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList5, ImplicitList6, Barriers2, 0 }, // Inst #74 = BCTRL8_ELF
- { 75, 0, 0, 0, "BCTRL_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList7, ImplicitList8, Barriers3, 0 }, // Inst #75 = BCTRL_Darwin
- { 76, 0, 0, 0, "BCTRL_SVR4", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList7, ImplicitList9, Barriers3, 0 }, // Inst #76 = BCTRL_SVR4
- { 77, 1, 0, 0, "BL8_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, ImplicitList6, Barriers2, OperandInfo8 }, // Inst #77 = BL8_Darwin
- { 78, 1, 0, 0, "BL8_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, ImplicitList6, Barriers2, OperandInfo8 }, // Inst #78 = BL8_ELF
- { 79, 1, 0, 0, "BLA8_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList10, ImplicitList6, Barriers2, OperandInfo8 }, // Inst #79 = BLA8_Darwin
- { 80, 1, 0, 0, "BLA8_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList10, ImplicitList6, Barriers2, OperandInfo8 }, // Inst #80 = BLA8_ELF
- { 81, 1, 0, 0, "BLA_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList10, ImplicitList8, Barriers3, OperandInfo8 }, // Inst #81 = BLA_Darwin
- { 82, 1, 0, 0, "BLA_SVR4", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList10, ImplicitList9, Barriers3, OperandInfo8 }, // Inst #82 = BLA_SVR4
- { 83, 2, 0, 0, "BLR", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(7<<3), ImplicitList11, NULL, NULL, OperandInfo15 }, // Inst #83 = BLR
- { 84, 1, 0, 0, "BL_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, ImplicitList8, Barriers3, OperandInfo8 }, // Inst #84 = BL_Darwin
- { 85, 1, 0, 0, "BL_SVR4", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, ImplicitList9, Barriers3, OperandInfo8 }, // Inst #85 = BL_SVR4
- { 86, 3, 1, 11, "CMPD", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo16 }, // Inst #86 = CMPD
- { 87, 3, 1, 11, "CMPDI", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo17 }, // Inst #87 = CMPDI
- { 88, 3, 1, 11, "CMPLD", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo16 }, // Inst #88 = CMPLD
- { 89, 3, 1, 11, "CMPLDI", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo17 }, // Inst #89 = CMPLDI
- { 90, 3, 1, 11, "CMPLW", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo18 }, // Inst #90 = CMPLW
- { 91, 3, 1, 11, "CMPLWI", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo19 }, // Inst #91 = CMPLWI
- { 92, 3, 1, 11, "CMPW", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo18 }, // Inst #92 = CMPW
- { 93, 3, 1, 11, "CMPWI", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo19 }, // Inst #93 = CMPWI
- { 94, 2, 1, 14, "CNTLZD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #94 = CNTLZD
- { 95, 2, 1, 14, "CNTLZW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #95 = CNTLZW
- { 96, 3, 1, 1, "CREQV", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo21 }, // Inst #96 = CREQV
- { 97, 3, 1, 1, "CROR", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo21 }, // Inst #97 = CROR
- { 98, 1, 1, 1, "CRSET", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo22 }, // Inst #98 = CRSET
- { 99, 2, 0, 30, "DCBA", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #99 = DCBA
- { 100, 2, 0, 30, "DCBF", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #100 = DCBF
- { 101, 2, 0, 30, "DCBI", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #101 = DCBI
- { 102, 2, 0, 30, "DCBST", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #102 = DCBST
- { 103, 2, 0, 30, "DCBT", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #103 = DCBT
- { 104, 2, 0, 30, "DCBTST", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #104 = DCBTST
- { 105, 2, 0, 30, "DCBZ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #105 = DCBZ
- { 106, 2, 0, 30, "DCBZL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #106 = DCBZL
- { 107, 3, 1, 12, "DIVD", 0, 0|1|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #107 = DIVD
- { 108, 3, 1, 12, "DIVDU", 0, 0|1|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #108 = DIVDU
- { 109, 3, 1, 13, "DIVW", 0, 0|1|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #109 = DIVW
- { 110, 3, 1, 13, "DIVWU", 0, 0|1|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #110 = DIVWU
- { 111, 4, 0, 33, "DSS", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo24 }, // Inst #111 = DSS
- { 112, 4, 0, 33, "DSSALL", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo24 }, // Inst #112 = DSSALL
- { 113, 4, 0, 33, "DST", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo25 }, // Inst #113 = DST
- { 114, 4, 0, 33, "DST64", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo26 }, // Inst #114 = DST64
- { 115, 4, 0, 33, "DSTST", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo25 }, // Inst #115 = DSTST
- { 116, 4, 0, 33, "DSTST64", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo26 }, // Inst #116 = DSTST64
- { 117, 4, 0, 33, "DSTSTT", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo25 }, // Inst #117 = DSTSTT
- { 118, 4, 0, 33, "DSTSTT64", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo26 }, // Inst #118 = DSTSTT64
- { 119, 4, 0, 33, "DSTT", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo25 }, // Inst #119 = DSTT
- { 120, 4, 0, 33, "DSTT64", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo26 }, // Inst #120 = DSTT64
- { 121, 4, 1, 52, "DYNALLOC", 0, 0, ImplicitList2, ImplicitList2, NULL, OperandInfo27 }, // Inst #121 = DYNALLOC
- { 122, 4, 1, 52, "DYNALLOC8", 0, 0, ImplicitList12, ImplicitList12, NULL, OperandInfo28 }, // Inst #122 = DYNALLOC8
- { 123, 3, 1, 14, "EQV", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #123 = EQV
- { 124, 3, 1, 14, "EQV8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #124 = EQV8
- { 125, 2, 1, 14, "EXTSB", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #125 = EXTSB
- { 126, 2, 1, 14, "EXTSB8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #126 = EXTSB8
- { 127, 2, 1, 14, "EXTSH", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #127 = EXTSH
- { 128, 2, 1, 14, "EXTSH8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #128 = EXTSH8
- { 129, 2, 1, 14, "EXTSW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #129 = EXTSW
- { 130, 2, 1, 14, "EXTSW_32", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #130 = EXTSW_32
- { 131, 2, 1, 14, "EXTSW_32_64", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo29 }, // Inst #131 = EXTSW_32_64
- { 132, 2, 1, 8, "FABSD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 }, // Inst #132 = FABSD
- { 133, 2, 1, 8, "FABSS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 }, // Inst #133 = FABSS
- { 134, 3, 1, 8, "FADD", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #134 = FADD
- { 135, 3, 1, 8, "FADDS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #135 = FADDS
- { 136, 3, 1, 8, "FADDrtz", 0, 0|(1<<1)|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #136 = FADDrtz
- { 137, 2, 1, 8, "FCFID", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo30 }, // Inst #137 = FCFID
- { 138, 3, 1, 4, "FCMPUD", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<3), NULL, NULL, NULL, OperandInfo34 }, // Inst #138 = FCMPUD
- { 139, 3, 1, 4, "FCMPUS", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<3), NULL, NULL, NULL, OperandInfo35 }, // Inst #139 = FCMPUS
- { 140, 2, 1, 8, "FCTIDZ", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo30 }, // Inst #140 = FCTIDZ
- { 141, 2, 1, 8, "FCTIWZ", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo30 }, // Inst #141 = FCTIWZ
- { 142, 3, 1, 5, "FDIV", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #142 = FDIV
- { 143, 3, 1, 6, "FDIVS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #143 = FDIVS
- { 144, 4, 1, 7, "FMADD", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #144 = FMADD
- { 145, 4, 1, 8, "FMADDS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #145 = FMADDS
- { 146, 2, 1, 8, "FMRD", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo30 }, // Inst #146 = FMRD
- { 147, 2, 1, 8, "FMRS", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo31 }, // Inst #147 = FMRS
- { 148, 2, 1, 8, "FMRSD", 0, 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #148 = FMRSD
- { 149, 4, 1, 7, "FMSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #149 = FMSUB
- { 150, 4, 1, 8, "FMSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #150 = FMSUBS
- { 151, 3, 1, 7, "FMUL", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #151 = FMUL
- { 152, 3, 1, 8, "FMULS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #152 = FMULS
- { 153, 2, 1, 8, "FNABSD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 }, // Inst #153 = FNABSD
- { 154, 2, 1, 8, "FNABSS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 }, // Inst #154 = FNABSS
- { 155, 2, 1, 8, "FNEGD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 }, // Inst #155 = FNEGD
- { 156, 2, 1, 8, "FNEGS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 }, // Inst #156 = FNEGS
- { 157, 4, 1, 7, "FNMADD", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #157 = FNMADD
- { 158, 4, 1, 8, "FNMADDS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #158 = FNMADDS
- { 159, 4, 1, 7, "FNMSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #159 = FNMSUB
- { 160, 4, 1, 8, "FNMSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #160 = FNMSUBS
- { 161, 2, 1, 8, "FRSP", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo39 }, // Inst #161 = FRSP
- { 162, 4, 1, 8, "FSELD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo36 }, // Inst #162 = FSELD
- { 163, 4, 1, 8, "FSELS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo40 }, // Inst #163 = FSELS
- { 164, 2, 1, 10, "FSQRT", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo30 }, // Inst #164 = FSQRT
- { 165, 2, 1, 10, "FSQRTS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo31 }, // Inst #165 = FSQRTS
- { 166, 3, 1, 8, "FSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #166 = FSUB
- { 167, 3, 1, 8, "FSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #167 = FSUBS
- { 168, 3, 1, 14, "LA", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #168 = LA
- { 169, 3, 1, 33, "LBZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #169 = LBZ
- { 170, 3, 1, 33, "LBZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #170 = LBZ8
- { 171, 4, 2, 33, "LBZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #171 = LBZU
- { 172, 4, 2, 33, "LBZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #172 = LBZU8
- { 173, 3, 1, 33, "LBZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #173 = LBZX
- { 174, 3, 1, 33, "LBZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #174 = LBZX8
- { 175, 3, 1, 35, "LD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #175 = LD
- { 176, 3, 1, 36, "LDARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo47 }, // Inst #176 = LDARX
- { 177, 4, 2, 35, "LDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #177 = LDU
- { 178, 3, 1, 35, "LDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #178 = LDX
- { 179, 1, 0, 35, "LDinto_toc", 0|(1<<TID::FoldableAsLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo48 }, // Inst #179 = LDinto_toc
- { 180, 3, 1, 35, "LDtoc", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo49 }, // Inst #180 = LDtoc
- { 181, 0, 0, 35, "LDtoc_restore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, 0 }, // Inst #181 = LDtoc_restore
- { 182, 3, 1, 37, "LFD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 }, // Inst #182 = LFD
- { 183, 4, 2, 37, "LFDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo51 }, // Inst #183 = LFDU
- { 184, 3, 1, 38, "LFDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #184 = LFDX
- { 185, 3, 1, 38, "LFS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo53 }, // Inst #185 = LFS
- { 186, 4, 2, 38, "LFSU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo54 }, // Inst #186 = LFSU
- { 187, 3, 1, 38, "LFSX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #187 = LFSX
- { 188, 3, 1, 39, "LHA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #188 = LHA
- { 189, 3, 1, 39, "LHA8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #189 = LHA8
- { 190, 4, 2, 33, "LHAU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #190 = LHAU
- { 191, 4, 2, 33, "LHAU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #191 = LHAU8
- { 192, 3, 1, 39, "LHAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #192 = LHAX
- { 193, 3, 1, 39, "LHAX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #193 = LHAX8
- { 194, 3, 1, 33, "LHBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #194 = LHBRX
- { 195, 3, 1, 33, "LHZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #195 = LHZ
- { 196, 3, 1, 33, "LHZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #196 = LHZ8
- { 197, 4, 2, 33, "LHZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #197 = LHZU
- { 198, 4, 2, 33, "LHZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #198 = LHZU8
- { 199, 3, 1, 33, "LHZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #199 = LHZX
- { 200, 3, 1, 33, "LHZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #200 = LHZX8
- { 201, 2, 1, 14, "LI", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #201 = LI
- { 202, 2, 1, 14, "LI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #202 = LI8
- { 203, 2, 1, 14, "LIS", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #203 = LIS
- { 204, 2, 1, 14, "LIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #204 = LIS8
- { 205, 3, 1, 33, "LVEBX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #205 = LVEBX
- { 206, 3, 1, 33, "LVEHX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #206 = LVEHX
- { 207, 3, 1, 33, "LVEWX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #207 = LVEWX
- { 208, 3, 1, 33, "LVSL", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #208 = LVSL
- { 209, 3, 1, 33, "LVSR", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #209 = LVSR
- { 210, 3, 1, 33, "LVX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #210 = LVX
- { 211, 3, 1, 33, "LVXL", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #211 = LVXL
- { 212, 3, 1, 42, "LWA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #212 = LWA
- { 213, 3, 1, 43, "LWARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo46 }, // Inst #213 = LWARX
- { 214, 3, 1, 39, "LWAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #214 = LWAX
- { 215, 3, 1, 33, "LWBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #215 = LWBRX
- { 216, 3, 1, 33, "LWZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #216 = LWZ
- { 217, 3, 1, 33, "LWZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #217 = LWZ8
- { 218, 4, 2, 33, "LWZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #218 = LWZU
- { 219, 4, 2, 33, "LWZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #219 = LWZU8
- { 220, 3, 1, 33, "LWZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #220 = LWZX
- { 221, 3, 1, 33, "LWZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #221 = LWZX8
- { 222, 2, 1, 2, "MCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo59 }, // Inst #222 = MCRF
- { 223, 1, 1, 54, "MFCR", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #223 = MFCR
- { 224, 1, 1, 56, "MFCTR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList4, NULL, NULL, OperandInfo60 }, // Inst #224 = MFCTR
- { 225, 1, 1, 56, "MFCTR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList13, NULL, NULL, OperandInfo48 }, // Inst #225 = MFCTR8
- { 226, 1, 1, 15, "MFFS", 0, 0|(1<<1)|(3<<3), ImplicitList10, NULL, NULL, OperandInfo61 }, // Inst #226 = MFFS
- { 227, 1, 1, 56, "MFLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList14, NULL, NULL, OperandInfo60 }, // Inst #227 = MFLR
- { 228, 1, 1, 56, "MFLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList15, NULL, NULL, OperandInfo48 }, // Inst #228 = MFLR8
- { 229, 2, 1, 54, "MFOCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #229 = MFOCRF
- { 230, 1, 1, 14, "MFVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #230 = MFVRSAVE
- { 231, 1, 1, 33, "MFVSCR", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo62 }, // Inst #231 = MFVSCR
- { 232, 2, 0, 3, "MTCRF", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo63 }, // Inst #232 = MTCRF
- { 233, 1, 0, 60, "MTCTR", 0, 0|1|(1<<3), NULL, ImplicitList4, Barriers4, OperandInfo60 }, // Inst #233 = MTCTR
- { 234, 1, 0, 60, "MTCTR8", 0, 0|1|(1<<3), NULL, ImplicitList13, Barriers5, OperandInfo48 }, // Inst #234 = MTCTR8
- { 235, 1, 0, 17, "MTFSB0", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo8 }, // Inst #235 = MTFSB0
- { 236, 1, 0, 17, "MTFSB1", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo8 }, // Inst #236 = MTFSB1
- { 237, 4, 1, 17, "MTFSF", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo64 }, // Inst #237 = MTFSF
- { 238, 1, 0, 60, "MTLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList14, NULL, OperandInfo60 }, // Inst #238 = MTLR
- { 239, 1, 0, 60, "MTLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList15, NULL, OperandInfo48 }, // Inst #239 = MTLR8
- { 240, 1, 0, 14, "MTVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<1)|(1<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #240 = MTVRSAVE
- { 241, 1, 0, 33, "MTVSCR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo62 }, // Inst #241 = MTVSCR
- { 242, 3, 1, 20, "MULHD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #242 = MULHD
- { 243, 3, 1, 21, "MULHDU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #243 = MULHDU
- { 244, 3, 1, 20, "MULHW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #244 = MULHW
- { 245, 3, 1, 21, "MULHWU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #245 = MULHWU
- { 246, 3, 1, 19, "MULLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #246 = MULLD
- { 247, 3, 1, 22, "MULLI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #247 = MULLI
- { 248, 3, 1, 20, "MULLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #248 = MULLW
- { 249, 1, 0, 52, "MovePCtoLR", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList14, NULL, OperandInfo8 }, // Inst #249 = MovePCtoLR
- { 250, 1, 0, 52, "MovePCtoLR8", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList15, NULL, OperandInfo8 }, // Inst #250 = MovePCtoLR8
- { 251, 3, 1, 14, "NAND", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #251 = NAND
- { 252, 3, 1, 14, "NAND8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #252 = NAND8
- { 253, 2, 1, 14, "NEG", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #253 = NEG
- { 254, 2, 1, 14, "NEG8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #254 = NEG8
- { 255, 0, 0, 14, "NOP", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, 0 }, // Inst #255 = NOP
- { 256, 3, 1, 14, "NOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #256 = NOR
- { 257, 3, 1, 14, "NOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #257 = NOR8
- { 258, 3, 1, 14, "OR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #258 = OR
- { 259, 3, 1, 14, "OR4To8", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo65 }, // Inst #259 = OR4To8
- { 260, 3, 1, 14, "OR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #260 = OR8
- { 261, 3, 1, 14, "OR8To4", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo66 }, // Inst #261 = OR8To4
- { 262, 3, 1, 14, "ORC", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #262 = ORC
- { 263, 3, 1, 14, "ORC8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #263 = ORC8
- { 264, 3, 1, 14, "ORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #264 = ORI
- { 265, 3, 1, 14, "ORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #265 = ORI8
- { 266, 3, 1, 14, "ORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #266 = ORIS
- { 267, 3, 1, 14, "ORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #267 = ORIS8
- { 268, 4, 1, 25, "RLDCL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo67 }, // Inst #268 = RLDCL
- { 269, 4, 1, 25, "RLDICL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 }, // Inst #269 = RLDICL
- { 270, 4, 1, 25, "RLDICR", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 }, // Inst #270 = RLDICR
- { 271, 5, 1, 25, "RLDIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo69 }, // Inst #271 = RLDIMI
- { 272, 6, 1, 24, "RLWIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo70 }, // Inst #272 = RLWIMI
- { 273, 5, 1, 14, "RLWINM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo71 }, // Inst #273 = RLWINM
- { 274, 5, 1, 14, "RLWINMo", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, ImplicitList3, NULL, OperandInfo71 }, // Inst #274 = RLWINMo
- { 275, 5, 1, 14, "RLWNM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo72 }, // Inst #275 = RLWNM
- { 276, 5, 1, 52, "SELECT_CC_F4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo73 }, // Inst #276 = SELECT_CC_F4
- { 277, 5, 1, 52, "SELECT_CC_F8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo74 }, // Inst #277 = SELECT_CC_F8
- { 278, 5, 1, 52, "SELECT_CC_I4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo75 }, // Inst #278 = SELECT_CC_I4
- { 279, 5, 1, 52, "SELECT_CC_I8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo76 }, // Inst #279 = SELECT_CC_I8
- { 280, 5, 1, 52, "SELECT_CC_VRRC", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo77 }, // Inst #280 = SELECT_CC_VRRC
- { 281, 3, 1, 25, "SLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo78 }, // Inst #281 = SLD
- { 282, 3, 1, 14, "SLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #282 = SLW
- { 283, 3, 0, 52, "SPILL_CR", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo42 }, // Inst #283 = SPILL_CR
- { 284, 3, 1, 25, "SRAD", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo78 }, // Inst #284 = SRAD
- { 285, 3, 1, 25, "SRADI", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #285 = SRADI
- { 286, 3, 1, 26, "SRAW", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #286 = SRAW
- { 287, 3, 1, 26, "SRAWI", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #287 = SRAWI
- { 288, 3, 1, 25, "SRD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo78 }, // Inst #288 = SRD
- { 289, 3, 1, 14, "SRW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #289 = SRW
- { 290, 3, 0, 33, "STB", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #290 = STB
- { 291, 3, 0, 33, "STB8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #291 = STB8
- { 292, 4, 1, 33, "STBU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #292 = STBU
- { 293, 4, 1, 33, "STBU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #293 = STBU8
- { 294, 3, 0, 33, "STBX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #294 = STBX
- { 295, 3, 0, 33, "STBX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #295 = STBX8
- { 296, 3, 0, 46, "STD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #296 = STD
- { 297, 3, 0, 47, "STDCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList3, NULL, OperandInfo47 }, // Inst #297 = STDCX
- { 298, 4, 1, 46, "STDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #298 = STDU
- { 299, 3, 0, 46, "STDUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #299 = STDUX
- { 300, 3, 0, 46, "STDX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #300 = STDX
- { 301, 3, 0, 46, "STDX_32", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #301 = STDX_32
- { 302, 3, 0, 46, "STD_32", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #302 = STD_32
- { 303, 3, 0, 51, "STFD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 }, // Inst #303 = STFD
- { 304, 4, 1, 33, "STFDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo81 }, // Inst #304 = STFDU
- { 305, 3, 0, 51, "STFDX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #305 = STFDX
- { 306, 3, 0, 51, "STFIWX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #306 = STFIWX
- { 307, 3, 0, 51, "STFS", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo53 }, // Inst #307 = STFS
- { 308, 4, 1, 33, "STFSU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo82 }, // Inst #308 = STFSU
- { 309, 3, 0, 51, "STFSX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #309 = STFSX
- { 310, 3, 0, 33, "STH", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #310 = STH
- { 311, 3, 0, 33, "STH8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #311 = STH8
- { 312, 3, 0, 33, "STHBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #312 = STHBRX
- { 313, 4, 1, 33, "STHU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #313 = STHU
- { 314, 4, 1, 33, "STHU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #314 = STHU8
- { 315, 3, 0, 33, "STHX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #315 = STHX
- { 316, 3, 0, 33, "STHX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #316 = STHX8
- { 317, 3, 0, 33, "STVEBX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #317 = STVEBX
- { 318, 3, 0, 33, "STVEHX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #318 = STVEHX
- { 319, 3, 0, 33, "STVEWX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #319 = STVEWX
- { 320, 3, 0, 33, "STVX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #320 = STVX
- { 321, 3, 0, 33, "STVXL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #321 = STVXL
- { 322, 3, 0, 33, "STW", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #322 = STW
- { 323, 3, 0, 33, "STW8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #323 = STW8
- { 324, 3, 0, 33, "STWBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #324 = STWBRX
- { 325, 3, 0, 49, "STWCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList3, NULL, OperandInfo46 }, // Inst #325 = STWCX
- { 326, 4, 1, 33, "STWU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #326 = STWU
- { 327, 4, 1, 33, "STWU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #327 = STWU8
- { 328, 3, 0, 33, "STWUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #328 = STWUX
- { 329, 3, 0, 33, "STWX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #329 = STWX
- { 330, 3, 0, 33, "STWX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #330 = STWX8
- { 331, 3, 1, 14, "SUBF", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #331 = SUBF
- { 332, 3, 1, 14, "SUBF8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #332 = SUBF8
- { 333, 3, 1, 14, "SUBFC", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #333 = SUBFC
- { 334, 3, 1, 14, "SUBFC8", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #334 = SUBFC8
- { 335, 3, 1, 14, "SUBFE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #335 = SUBFE
- { 336, 3, 1, 14, "SUBFE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #336 = SUBFE8
- { 337, 3, 1, 14, "SUBFIC", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #337 = SUBFIC
- { 338, 3, 1, 14, "SUBFIC8", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #338 = SUBFIC8
- { 339, 2, 1, 14, "SUBFME", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #339 = SUBFME
- { 340, 2, 1, 14, "SUBFME8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #340 = SUBFME8
- { 341, 2, 1, 14, "SUBFZE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #341 = SUBFZE
- { 342, 2, 1, 14, "SUBFZE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #342 = SUBFZE8
- { 343, 0, 0, 50, "SYNC", 0|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #343 = SYNC
- { 344, 1, 0, 0, "TAILB", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #344 = TAILB
- { 345, 1, 0, 0, "TAILB8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #345 = TAILB8
- { 346, 1, 0, 0, "TAILBA", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #346 = TAILBA
- { 347, 1, 0, 0, "TAILBA8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #347 = TAILBA8
- { 348, 0, 0, 0, "TAILBCTR", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList7, NULL, NULL, 0 }, // Inst #348 = TAILBCTR
- { 349, 0, 0, 0, "TAILBCTR8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList7, NULL, NULL, 0 }, // Inst #349 = TAILBCTR8
- { 350, 2, 0, 52, "TCRETURNai", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #350 = TCRETURNai
- { 351, 2, 0, 52, "TCRETURNai8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #351 = TCRETURNai8
- { 352, 2, 0, 52, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #352 = TCRETURNdi
- { 353, 2, 0, 52, "TCRETURNdi8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #353 = TCRETURNdi8
- { 354, 2, 0, 52, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo83 }, // Inst #354 = TCRETURNri
- { 355, 2, 0, 52, "TCRETURNri8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo84 }, // Inst #355 = TCRETURNri8
- { 356, 0, 0, 33, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #356 = TRAP
- { 357, 2, 1, 52, "UPDATE_VRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo6 }, // Inst #357 = UPDATE_VRSAVE
- { 358, 3, 1, 67, "VADDCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #358 = VADDCUW
- { 359, 3, 1, 67, "VADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #359 = VADDFP
- { 360, 3, 1, 67, "VADDSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #360 = VADDSBS
- { 361, 3, 1, 67, "VADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #361 = VADDSHS
- { 362, 3, 1, 67, "VADDSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #362 = VADDSWS
- { 363, 3, 1, 70, "VADDUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #363 = VADDUBM
- { 364, 3, 1, 67, "VADDUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #364 = VADDUBS
- { 365, 3, 1, 70, "VADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #365 = VADDUHM
- { 366, 3, 1, 67, "VADDUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #366 = VADDUHS
- { 367, 3, 1, 70, "VADDUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #367 = VADDUWM
- { 368, 3, 1, 67, "VADDUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #368 = VADDUWS
- { 369, 3, 1, 67, "VAND", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #369 = VAND
- { 370, 3, 1, 67, "VANDC", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #370 = VANDC
- { 371, 3, 1, 67, "VAVGSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #371 = VAVGSB
- { 372, 3, 1, 67, "VAVGSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #372 = VAVGSH
- { 373, 3, 1, 67, "VAVGSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #373 = VAVGSW
- { 374, 3, 1, 67, "VAVGUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #374 = VAVGUB
- { 375, 3, 1, 67, "VAVGUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #375 = VAVGUH
- { 376, 3, 1, 67, "VAVGUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #376 = VAVGUW
- { 377, 3, 1, 67, "VCFSX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #377 = VCFSX
- { 378, 3, 1, 67, "VCFUX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #378 = VCFUX
- { 379, 3, 1, 68, "VCMPBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #379 = VCMPBFP
- { 380, 3, 1, 68, "VCMPBFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #380 = VCMPBFPo
- { 381, 3, 1, 68, "VCMPEQFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #381 = VCMPEQFP
- { 382, 3, 1, 68, "VCMPEQFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #382 = VCMPEQFPo
- { 383, 3, 1, 68, "VCMPEQUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #383 = VCMPEQUB
- { 384, 3, 1, 68, "VCMPEQUBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #384 = VCMPEQUBo
- { 385, 3, 1, 68, "VCMPEQUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #385 = VCMPEQUH
- { 386, 3, 1, 68, "VCMPEQUHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #386 = VCMPEQUHo
- { 387, 3, 1, 68, "VCMPEQUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #387 = VCMPEQUW
- { 388, 3, 1, 68, "VCMPEQUWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #388 = VCMPEQUWo
- { 389, 3, 1, 68, "VCMPGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #389 = VCMPGEFP
- { 390, 3, 1, 68, "VCMPGEFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #390 = VCMPGEFPo
- { 391, 3, 1, 68, "VCMPGTFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #391 = VCMPGTFP
- { 392, 3, 1, 68, "VCMPGTFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #392 = VCMPGTFPo
- { 393, 3, 1, 68, "VCMPGTSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #393 = VCMPGTSB
- { 394, 3, 1, 68, "VCMPGTSBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #394 = VCMPGTSBo
- { 395, 3, 1, 68, "VCMPGTSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #395 = VCMPGTSH
- { 396, 3, 1, 68, "VCMPGTSHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #396 = VCMPGTSHo
- { 397, 3, 1, 68, "VCMPGTSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #397 = VCMPGTSW
- { 398, 3, 1, 68, "VCMPGTSWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #398 = VCMPGTSWo
- { 399, 3, 1, 68, "VCMPGTUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #399 = VCMPGTUB
- { 400, 3, 1, 68, "VCMPGTUBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #400 = VCMPGTUBo
- { 401, 3, 1, 68, "VCMPGTUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #401 = VCMPGTUH
- { 402, 3, 1, 68, "VCMPGTUHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #402 = VCMPGTUHo
- { 403, 3, 1, 68, "VCMPGTUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #403 = VCMPGTUW
- { 404, 3, 1, 68, "VCMPGTUWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #404 = VCMPGTUWo
- { 405, 3, 1, 67, "VCTSXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #405 = VCTSXS
- { 406, 3, 1, 67, "VCTUXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #406 = VCTUXS
- { 407, 2, 1, 67, "VEXPTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #407 = VEXPTEFP
- { 408, 2, 1, 67, "VLOGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #408 = VLOGEFP
- { 409, 4, 1, 67, "VMADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #409 = VMADDFP
- { 410, 3, 1, 67, "VMAXFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #410 = VMAXFP
- { 411, 3, 1, 67, "VMAXSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #411 = VMAXSB
- { 412, 3, 1, 67, "VMAXSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #412 = VMAXSH
- { 413, 3, 1, 67, "VMAXSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #413 = VMAXSW
- { 414, 3, 1, 67, "VMAXUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #414 = VMAXUB
- { 415, 3, 1, 67, "VMAXUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #415 = VMAXUH
- { 416, 3, 1, 67, "VMAXUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #416 = VMAXUW
- { 417, 4, 1, 67, "VMHADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #417 = VMHADDSHS
- { 418, 4, 1, 67, "VMHRADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #418 = VMHRADDSHS
- { 419, 3, 1, 67, "VMINFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #419 = VMINFP
- { 420, 3, 1, 67, "VMINSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #420 = VMINSB
- { 421, 3, 1, 67, "VMINSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #421 = VMINSH
- { 422, 3, 1, 67, "VMINSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #422 = VMINSW
- { 423, 3, 1, 67, "VMINUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #423 = VMINUB
- { 424, 3, 1, 67, "VMINUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #424 = VMINUH
- { 425, 3, 1, 67, "VMINUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #425 = VMINUW
- { 426, 4, 1, 67, "VMLADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #426 = VMLADDUHM
- { 427, 3, 1, 67, "VMRGHB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #427 = VMRGHB
- { 428, 3, 1, 67, "VMRGHH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #428 = VMRGHH
- { 429, 3, 1, 67, "VMRGHW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #429 = VMRGHW
- { 430, 3, 1, 67, "VMRGLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #430 = VMRGLB
- { 431, 3, 1, 67, "VMRGLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #431 = VMRGLH
- { 432, 3, 1, 67, "VMRGLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #432 = VMRGLW
- { 433, 4, 1, 67, "VMSUMMBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #433 = VMSUMMBM
- { 434, 4, 1, 67, "VMSUMSHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #434 = VMSUMSHM
- { 435, 4, 1, 67, "VMSUMSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #435 = VMSUMSHS
- { 436, 4, 1, 67, "VMSUMUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #436 = VMSUMUBM
- { 437, 4, 1, 67, "VMSUMUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #437 = VMSUMUHM
- { 438, 4, 1, 67, "VMSUMUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #438 = VMSUMUHS
- { 439, 3, 1, 67, "VMULESB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #439 = VMULESB
- { 440, 3, 1, 67, "VMULESH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #440 = VMULESH
- { 441, 3, 1, 67, "VMULEUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #441 = VMULEUB
- { 442, 3, 1, 67, "VMULEUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #442 = VMULEUH
- { 443, 3, 1, 67, "VMULOSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #443 = VMULOSB
- { 444, 3, 1, 67, "VMULOSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #444 = VMULOSH
- { 445, 3, 1, 67, "VMULOUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #445 = VMULOUB
- { 446, 3, 1, 67, "VMULOUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #446 = VMULOUH
- { 447, 4, 1, 67, "VNMSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #447 = VNMSUBFP
- { 448, 3, 1, 67, "VNOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #448 = VNOR
- { 449, 3, 1, 67, "VOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #449 = VOR
- { 450, 4, 1, 67, "VPERM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #450 = VPERM
- { 451, 3, 1, 67, "VPKPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #451 = VPKPX
- { 452, 3, 1, 67, "VPKSHSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #452 = VPKSHSS
- { 453, 3, 1, 67, "VPKSHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #453 = VPKSHUS
- { 454, 3, 1, 67, "VPKSWSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #454 = VPKSWSS
- { 455, 3, 1, 67, "VPKSWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #455 = VPKSWUS
- { 456, 3, 1, 67, "VPKUHUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #456 = VPKUHUM
- { 457, 3, 1, 67, "VPKUHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #457 = VPKUHUS
- { 458, 3, 1, 67, "VPKUWUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #458 = VPKUWUM
- { 459, 3, 1, 67, "VPKUWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #459 = VPKUWUS
- { 460, 2, 1, 67, "VREFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #460 = VREFP
- { 461, 2, 1, 67, "VRFIM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #461 = VRFIM
- { 462, 2, 1, 67, "VRFIN", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #462 = VRFIN
- { 463, 2, 1, 67, "VRFIP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #463 = VRFIP
- { 464, 2, 1, 67, "VRFIZ", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #464 = VRFIZ
- { 465, 3, 1, 67, "VRLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #465 = VRLB
- { 466, 3, 1, 67, "VRLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #466 = VRLH
- { 467, 3, 1, 67, "VRLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #467 = VRLW
- { 468, 2, 1, 67, "VRSQRTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #468 = VRSQRTEFP
- { 469, 4, 1, 67, "VSEL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #469 = VSEL
- { 470, 3, 1, 67, "VSL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #470 = VSL
- { 471, 3, 1, 67, "VSLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #471 = VSLB
- { 472, 4, 1, 67, "VSLDOI", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo89 }, // Inst #472 = VSLDOI
- { 473, 3, 1, 67, "VSLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #473 = VSLH
- { 474, 3, 1, 67, "VSLO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #474 = VSLO
- { 475, 3, 1, 67, "VSLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #475 = VSLW
- { 476, 3, 1, 71, "VSPLTB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #476 = VSPLTB
- { 477, 3, 1, 71, "VSPLTH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #477 = VSPLTH
- { 478, 2, 1, 71, "VSPLTISB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #478 = VSPLTISB
- { 479, 2, 1, 71, "VSPLTISH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #479 = VSPLTISH
- { 480, 2, 1, 71, "VSPLTISW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #480 = VSPLTISW
- { 481, 3, 1, 71, "VSPLTW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #481 = VSPLTW
- { 482, 3, 1, 67, "VSR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #482 = VSR
- { 483, 3, 1, 67, "VSRAB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #483 = VSRAB
- { 484, 3, 1, 67, "VSRAH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #484 = VSRAH
- { 485, 3, 1, 67, "VSRAW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #485 = VSRAW
- { 486, 3, 1, 67, "VSRB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #486 = VSRB
- { 487, 3, 1, 67, "VSRH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #487 = VSRH
- { 488, 3, 1, 67, "VSRO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #488 = VSRO
- { 489, 3, 1, 67, "VSRW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #489 = VSRW
- { 490, 3, 1, 67, "VSUBCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #490 = VSUBCUW
- { 491, 3, 1, 70, "VSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #491 = VSUBFP
- { 492, 3, 1, 67, "VSUBSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #492 = VSUBSBS
- { 493, 3, 1, 67, "VSUBSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #493 = VSUBSHS
- { 494, 3, 1, 67, "VSUBSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #494 = VSUBSWS
- { 495, 3, 1, 70, "VSUBUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #495 = VSUBUBM
- { 496, 3, 1, 67, "VSUBUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #496 = VSUBUBS
- { 497, 3, 1, 70, "VSUBUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #497 = VSUBUHM
- { 498, 3, 1, 67, "VSUBUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #498 = VSUBUHS
- { 499, 3, 1, 70, "VSUBUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #499 = VSUBUWM
- { 500, 3, 1, 67, "VSUBUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #500 = VSUBUWS
- { 501, 3, 1, 67, "VSUM2SWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #501 = VSUM2SWS
- { 502, 3, 1, 67, "VSUM4SBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #502 = VSUM4SBS
- { 503, 3, 1, 67, "VSUM4SHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #503 = VSUM4SHS
- { 504, 3, 1, 67, "VSUM4UBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #504 = VSUM4UBS
- { 505, 3, 1, 67, "VSUMSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #505 = VSUMSWS
- { 506, 2, 1, 67, "VUPKHPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #506 = VUPKHPX
- { 507, 2, 1, 67, "VUPKHSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #507 = VUPKHSB
- { 508, 2, 1, 67, "VUPKHSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #508 = VUPKHSH
- { 509, 2, 1, 67, "VUPKLPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #509 = VUPKLPX
- { 510, 2, 1, 67, "VUPKLSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #510 = VUPKLSB
- { 511, 2, 1, 67, "VUPKLSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #511 = VUPKLSH
- { 512, 3, 1, 67, "VXOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #512 = VXOR
- { 513, 1, 1, 67, "V_SET0", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo62 }, // Inst #513 = V_SET0
- { 514, 3, 1, 14, "XOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #514 = XOR
- { 515, 3, 1, 14, "XOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #515 = XOR8
- { 516, 3, 1, 14, "XORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #516 = XORI
- { 517, 3, 1, 14, "XORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #517 = XORI8
- { 518, 3, 1, 14, "XORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #518 = XORIS
- { 519, 3, 1, 14, "XORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #519 = XORIS8
+ { 11, 0, 0, 52, "DEBUG_VALUE", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, 0 }, // Inst #11 = DEBUG_VALUE
+ { 12, 3, 1, 14, "ADD4", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #12 = ADD4
+ { 13, 3, 1, 14, "ADD8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #13 = ADD8
+ { 14, 3, 1, 14, "ADDC", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #14 = ADDC
+ { 15, 3, 1, 14, "ADDC8", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #15 = ADDC8
+ { 16, 3, 1, 14, "ADDE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #16 = ADDE
+ { 17, 3, 1, 14, "ADDE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #17 = ADDE8
+ { 18, 3, 1, 14, "ADDI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #18 = ADDI
+ { 19, 3, 1, 14, "ADDI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #19 = ADDI8
+ { 20, 3, 1, 14, "ADDIC", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #20 = ADDIC
+ { 21, 3, 1, 14, "ADDIC8", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #21 = ADDIC8
+ { 22, 3, 1, 14, "ADDICo", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #22 = ADDICo
+ { 23, 3, 1, 14, "ADDIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #23 = ADDIS
+ { 24, 3, 1, 14, "ADDIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #24 = ADDIS8
+ { 25, 2, 1, 14, "ADDME", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #25 = ADDME
+ { 26, 2, 1, 14, "ADDME8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #26 = ADDME8
+ { 27, 2, 1, 14, "ADDZE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #27 = ADDZE
+ { 28, 2, 1, 14, "ADDZE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #28 = ADDZE8
+ { 29, 1, 0, 52, "ADJCALLSTACKDOWN", 0, 0, ImplicitList2, ImplicitList2, NULL, OperandInfo8 }, // Inst #29 = ADJCALLSTACKDOWN
+ { 30, 2, 0, 52, "ADJCALLSTACKUP", 0, 0, ImplicitList2, ImplicitList2, NULL, OperandInfo9 }, // Inst #30 = ADJCALLSTACKUP
+ { 31, 3, 1, 14, "AND", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #31 = AND
+ { 32, 3, 1, 14, "AND8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #32 = AND8
+ { 33, 3, 1, 14, "ANDC", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #33 = ANDC
+ { 34, 3, 1, 14, "ANDC8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #34 = ANDC8
+ { 35, 3, 1, 14, "ANDISo", 0, 0|(1<<3), NULL, ImplicitList3, NULL, OperandInfo4 }, // Inst #35 = ANDISo
+ { 36, 3, 1, 14, "ANDISo8", 0, 0|(1<<3), NULL, ImplicitList3, NULL, OperandInfo5 }, // Inst #36 = ANDISo8
+ { 37, 3, 1, 14, "ANDIo", 0, 0|(1<<3), NULL, ImplicitList3, NULL, OperandInfo4 }, // Inst #37 = ANDIo
+ { 38, 3, 1, 14, "ANDIo8", 0, 0|(1<<3), NULL, ImplicitList3, NULL, OperandInfo5 }, // Inst #38 = ANDIo8
+ { 39, 5, 1, 52, "ATOMIC_CMP_SWAP_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo10 }, // Inst #39 = ATOMIC_CMP_SWAP_I16
+ { 40, 5, 1, 52, "ATOMIC_CMP_SWAP_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo10 }, // Inst #40 = ATOMIC_CMP_SWAP_I32
+ { 41, 5, 1, 52, "ATOMIC_CMP_SWAP_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo11 }, // Inst #41 = ATOMIC_CMP_SWAP_I64
+ { 42, 5, 1, 52, "ATOMIC_CMP_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo10 }, // Inst #42 = ATOMIC_CMP_SWAP_I8
+ { 43, 4, 1, 52, "ATOMIC_LOAD_ADD_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #43 = ATOMIC_LOAD_ADD_I16
+ { 44, 4, 1, 52, "ATOMIC_LOAD_ADD_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #44 = ATOMIC_LOAD_ADD_I32
+ { 45, 4, 1, 52, "ATOMIC_LOAD_ADD_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #45 = ATOMIC_LOAD_ADD_I64
+ { 46, 4, 1, 52, "ATOMIC_LOAD_ADD_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #46 = ATOMIC_LOAD_ADD_I8
+ { 47, 4, 1, 52, "ATOMIC_LOAD_AND_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #47 = ATOMIC_LOAD_AND_I16
+ { 48, 4, 1, 52, "ATOMIC_LOAD_AND_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #48 = ATOMIC_LOAD_AND_I32
+ { 49, 4, 1, 52, "ATOMIC_LOAD_AND_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #49 = ATOMIC_LOAD_AND_I64
+ { 50, 4, 1, 52, "ATOMIC_LOAD_AND_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #50 = ATOMIC_LOAD_AND_I8
+ { 51, 4, 1, 52, "ATOMIC_LOAD_NAND_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #51 = ATOMIC_LOAD_NAND_I16
+ { 52, 4, 1, 52, "ATOMIC_LOAD_NAND_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #52 = ATOMIC_LOAD_NAND_I32
+ { 53, 4, 1, 52, "ATOMIC_LOAD_NAND_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #53 = ATOMIC_LOAD_NAND_I64
+ { 54, 4, 1, 52, "ATOMIC_LOAD_NAND_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #54 = ATOMIC_LOAD_NAND_I8
+ { 55, 4, 1, 52, "ATOMIC_LOAD_OR_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #55 = ATOMIC_LOAD_OR_I16
+ { 56, 4, 1, 52, "ATOMIC_LOAD_OR_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #56 = ATOMIC_LOAD_OR_I32
+ { 57, 4, 1, 52, "ATOMIC_LOAD_OR_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #57 = ATOMIC_LOAD_OR_I64
+ { 58, 4, 1, 52, "ATOMIC_LOAD_OR_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #58 = ATOMIC_LOAD_OR_I8
+ { 59, 4, 1, 52, "ATOMIC_LOAD_SUB_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #59 = ATOMIC_LOAD_SUB_I16
+ { 60, 4, 1, 52, "ATOMIC_LOAD_SUB_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #60 = ATOMIC_LOAD_SUB_I32
+ { 61, 4, 1, 52, "ATOMIC_LOAD_SUB_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #61 = ATOMIC_LOAD_SUB_I64
+ { 62, 4, 1, 52, "ATOMIC_LOAD_SUB_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #62 = ATOMIC_LOAD_SUB_I8
+ { 63, 4, 1, 52, "ATOMIC_LOAD_XOR_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #63 = ATOMIC_LOAD_XOR_I16
+ { 64, 4, 1, 52, "ATOMIC_LOAD_XOR_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #64 = ATOMIC_LOAD_XOR_I32
+ { 65, 4, 1, 52, "ATOMIC_LOAD_XOR_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #65 = ATOMIC_LOAD_XOR_I64
+ { 66, 4, 1, 52, "ATOMIC_LOAD_XOR_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #66 = ATOMIC_LOAD_XOR_I8
+ { 67, 4, 1, 52, "ATOMIC_SWAP_I16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #67 = ATOMIC_SWAP_I16
+ { 68, 4, 1, 52, "ATOMIC_SWAP_I32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #68 = ATOMIC_SWAP_I32
+ { 69, 4, 1, 52, "ATOMIC_SWAP_I64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo13 }, // Inst #69 = ATOMIC_SWAP_I64
+ { 70, 4, 1, 52, "ATOMIC_SWAP_I8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, ImplicitList3, NULL, NULL, OperandInfo12 }, // Inst #70 = ATOMIC_SWAP_I8
+ { 71, 1, 0, 0, "B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(7<<3), NULL, NULL, NULL, OperandInfo8 }, // Inst #71 = B
+ { 72, 3, 0, 0, "BCC", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, NULL, NULL, OperandInfo14 }, // Inst #72 = BCC
+ { 73, 0, 0, 0, "BCTR", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList4, NULL, NULL, 0 }, // Inst #73 = BCTR
+ { 74, 0, 0, 0, "BCTRL8_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList5, ImplicitList6, Barriers2, 0 }, // Inst #74 = BCTRL8_Darwin
+ { 75, 0, 0, 0, "BCTRL8_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList5, ImplicitList6, Barriers2, 0 }, // Inst #75 = BCTRL8_ELF
+ { 76, 0, 0, 0, "BCTRL_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList7, ImplicitList8, Barriers3, 0 }, // Inst #76 = BCTRL_Darwin
+ { 77, 0, 0, 0, "BCTRL_SVR4", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList7, ImplicitList9, Barriers3, 0 }, // Inst #77 = BCTRL_SVR4
+ { 78, 1, 0, 0, "BL8_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, ImplicitList6, Barriers2, OperandInfo8 }, // Inst #78 = BL8_Darwin
+ { 79, 1, 0, 0, "BL8_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, ImplicitList6, Barriers2, OperandInfo8 }, // Inst #79 = BL8_ELF
+ { 80, 1, 0, 0, "BLA8_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList10, ImplicitList6, Barriers2, OperandInfo8 }, // Inst #80 = BLA8_Darwin
+ { 81, 1, 0, 0, "BLA8_ELF", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList10, ImplicitList6, Barriers2, OperandInfo8 }, // Inst #81 = BLA8_ELF
+ { 82, 1, 0, 0, "BLA_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList10, ImplicitList8, Barriers3, OperandInfo8 }, // Inst #82 = BLA_Darwin
+ { 83, 1, 0, 0, "BLA_SVR4", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(7<<3), ImplicitList10, ImplicitList9, Barriers3, OperandInfo8 }, // Inst #83 = BLA_SVR4
+ { 84, 2, 0, 0, "BLR", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(7<<3), ImplicitList11, NULL, NULL, OperandInfo15 }, // Inst #84 = BLR
+ { 85, 1, 0, 0, "BL_Darwin", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, ImplicitList8, Barriers3, OperandInfo8 }, // Inst #85 = BL_Darwin
+ { 86, 1, 0, 0, "BL_SVR4", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, ImplicitList9, Barriers3, OperandInfo8 }, // Inst #86 = BL_SVR4
+ { 87, 3, 1, 11, "CMPD", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo16 }, // Inst #87 = CMPD
+ { 88, 3, 1, 11, "CMPDI", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo17 }, // Inst #88 = CMPDI
+ { 89, 3, 1, 11, "CMPLD", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo16 }, // Inst #89 = CMPLD
+ { 90, 3, 1, 11, "CMPLDI", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo17 }, // Inst #90 = CMPLDI
+ { 91, 3, 1, 11, "CMPLW", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo18 }, // Inst #91 = CMPLW
+ { 92, 3, 1, 11, "CMPLWI", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo19 }, // Inst #92 = CMPLWI
+ { 93, 3, 1, 11, "CMPW", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo18 }, // Inst #93 = CMPW
+ { 94, 3, 1, 11, "CMPWI", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo19 }, // Inst #94 = CMPWI
+ { 95, 2, 1, 14, "CNTLZD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #95 = CNTLZD
+ { 96, 2, 1, 14, "CNTLZW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #96 = CNTLZW
+ { 97, 3, 1, 1, "CREQV", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo21 }, // Inst #97 = CREQV
+ { 98, 3, 1, 1, "CROR", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo21 }, // Inst #98 = CROR
+ { 99, 1, 1, 1, "CRSET", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo22 }, // Inst #99 = CRSET
+ { 100, 2, 0, 30, "DCBA", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #100 = DCBA
+ { 101, 2, 0, 30, "DCBF", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #101 = DCBF
+ { 102, 2, 0, 30, "DCBI", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #102 = DCBI
+ { 103, 2, 0, 30, "DCBST", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #103 = DCBST
+ { 104, 2, 0, 30, "DCBT", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #104 = DCBT
+ { 105, 2, 0, 30, "DCBTST", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #105 = DCBTST
+ { 106, 2, 0, 30, "DCBZ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #106 = DCBZ
+ { 107, 2, 0, 30, "DCBZL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo23 }, // Inst #107 = DCBZL
+ { 108, 3, 1, 12, "DIVD", 0, 0|1|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #108 = DIVD
+ { 109, 3, 1, 12, "DIVDU", 0, 0|1|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #109 = DIVDU
+ { 110, 3, 1, 13, "DIVW", 0, 0|1|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #110 = DIVW
+ { 111, 3, 1, 13, "DIVWU", 0, 0|1|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #111 = DIVWU
+ { 112, 4, 0, 33, "DSS", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo24 }, // Inst #112 = DSS
+ { 113, 4, 0, 33, "DSSALL", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo24 }, // Inst #113 = DSSALL
+ { 114, 4, 0, 33, "DST", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo25 }, // Inst #114 = DST
+ { 115, 4, 0, 33, "DST64", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo26 }, // Inst #115 = DST64
+ { 116, 4, 0, 33, "DSTST", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo25 }, // Inst #116 = DSTST
+ { 117, 4, 0, 33, "DSTST64", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo26 }, // Inst #117 = DSTST64
+ { 118, 4, 0, 33, "DSTSTT", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo25 }, // Inst #118 = DSTSTT
+ { 119, 4, 0, 33, "DSTSTT64", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo26 }, // Inst #119 = DSTSTT64
+ { 120, 4, 0, 33, "DSTT", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo25 }, // Inst #120 = DSTT
+ { 121, 4, 0, 33, "DSTT64", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo26 }, // Inst #121 = DSTT64
+ { 122, 4, 1, 52, "DYNALLOC", 0, 0, ImplicitList2, ImplicitList2, NULL, OperandInfo27 }, // Inst #122 = DYNALLOC
+ { 123, 4, 1, 52, "DYNALLOC8", 0, 0, ImplicitList12, ImplicitList12, NULL, OperandInfo28 }, // Inst #123 = DYNALLOC8
+ { 124, 3, 1, 14, "EQV", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #124 = EQV
+ { 125, 3, 1, 14, "EQV8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #125 = EQV8
+ { 126, 2, 1, 14, "EXTSB", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #126 = EXTSB
+ { 127, 2, 1, 14, "EXTSB8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #127 = EXTSB8
+ { 128, 2, 1, 14, "EXTSH", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #128 = EXTSH
+ { 129, 2, 1, 14, "EXTSH8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #129 = EXTSH8
+ { 130, 2, 1, 14, "EXTSW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #130 = EXTSW
+ { 131, 2, 1, 14, "EXTSW_32", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #131 = EXTSW_32
+ { 132, 2, 1, 14, "EXTSW_32_64", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo29 }, // Inst #132 = EXTSW_32_64
+ { 133, 2, 1, 8, "FABSD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 }, // Inst #133 = FABSD
+ { 134, 2, 1, 8, "FABSS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 }, // Inst #134 = FABSS
+ { 135, 3, 1, 8, "FADD", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #135 = FADD
+ { 136, 3, 1, 8, "FADDS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #136 = FADDS
+ { 137, 3, 1, 8, "FADDrtz", 0, 0|(1<<1)|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #137 = FADDrtz
+ { 138, 2, 1, 8, "FCFID", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo30 }, // Inst #138 = FCFID
+ { 139, 3, 1, 4, "FCMPUD", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<3), NULL, NULL, NULL, OperandInfo34 }, // Inst #139 = FCMPUD
+ { 140, 3, 1, 4, "FCMPUS", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<3), NULL, NULL, NULL, OperandInfo35 }, // Inst #140 = FCMPUS
+ { 141, 2, 1, 8, "FCTIDZ", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo30 }, // Inst #141 = FCTIDZ
+ { 142, 2, 1, 8, "FCTIWZ", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo30 }, // Inst #142 = FCTIWZ
+ { 143, 3, 1, 5, "FDIV", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #143 = FDIV
+ { 144, 3, 1, 6, "FDIVS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #144 = FDIVS
+ { 145, 4, 1, 7, "FMADD", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #145 = FMADD
+ { 146, 4, 1, 8, "FMADDS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #146 = FMADDS
+ { 147, 2, 1, 8, "FMRD", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo30 }, // Inst #147 = FMRD
+ { 148, 2, 1, 8, "FMRS", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo31 }, // Inst #148 = FMRS
+ { 149, 2, 1, 8, "FMRSD", 0, 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #149 = FMRSD
+ { 150, 4, 1, 7, "FMSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #150 = FMSUB
+ { 151, 4, 1, 8, "FMSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #151 = FMSUBS
+ { 152, 3, 1, 7, "FMUL", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #152 = FMUL
+ { 153, 3, 1, 8, "FMULS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #153 = FMULS
+ { 154, 2, 1, 8, "FNABSD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 }, // Inst #154 = FNABSD
+ { 155, 2, 1, 8, "FNABSS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 }, // Inst #155 = FNABSS
+ { 156, 2, 1, 8, "FNEGD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 }, // Inst #156 = FNEGD
+ { 157, 2, 1, 8, "FNEGS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 }, // Inst #157 = FNEGS
+ { 158, 4, 1, 7, "FNMADD", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #158 = FNMADD
+ { 159, 4, 1, 8, "FNMADDS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #159 = FNMADDS
+ { 160, 4, 1, 7, "FNMSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #160 = FNMSUB
+ { 161, 4, 1, 8, "FNMSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #161 = FNMSUBS
+ { 162, 2, 1, 8, "FRSP", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo39 }, // Inst #162 = FRSP
+ { 163, 4, 1, 8, "FSELD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo36 }, // Inst #163 = FSELD
+ { 164, 4, 1, 8, "FSELS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo40 }, // Inst #164 = FSELS
+ { 165, 2, 1, 10, "FSQRT", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo30 }, // Inst #165 = FSQRT
+ { 166, 2, 1, 10, "FSQRTS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo31 }, // Inst #166 = FSQRTS
+ { 167, 3, 1, 8, "FSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #167 = FSUB
+ { 168, 3, 1, 8, "FSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #168 = FSUBS
+ { 169, 3, 1, 14, "LA", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #169 = LA
+ { 170, 3, 1, 33, "LBZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #170 = LBZ
+ { 171, 3, 1, 33, "LBZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #171 = LBZ8
+ { 172, 4, 2, 33, "LBZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #172 = LBZU
+ { 173, 4, 2, 33, "LBZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #173 = LBZU8
+ { 174, 3, 1, 33, "LBZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #174 = LBZX
+ { 175, 3, 1, 33, "LBZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #175 = LBZX8
+ { 176, 3, 1, 35, "LD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #176 = LD
+ { 177, 3, 1, 36, "LDARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo47 }, // Inst #177 = LDARX
+ { 178, 4, 2, 35, "LDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #178 = LDU
+ { 179, 3, 1, 35, "LDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #179 = LDX
+ { 180, 1, 0, 35, "LDinto_toc", 0|(1<<TID::FoldableAsLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo48 }, // Inst #180 = LDinto_toc
+ { 181, 3, 1, 35, "LDtoc", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo49 }, // Inst #181 = LDtoc
+ { 182, 0, 0, 35, "LDtoc_restore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, 0 }, // Inst #182 = LDtoc_restore
+ { 183, 3, 1, 37, "LFD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 }, // Inst #183 = LFD
+ { 184, 4, 2, 37, "LFDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo51 }, // Inst #184 = LFDU
+ { 185, 3, 1, 38, "LFDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #185 = LFDX
+ { 186, 3, 1, 38, "LFS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo53 }, // Inst #186 = LFS
+ { 187, 4, 2, 38, "LFSU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo54 }, // Inst #187 = LFSU
+ { 188, 3, 1, 38, "LFSX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #188 = LFSX
+ { 189, 3, 1, 39, "LHA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #189 = LHA
+ { 190, 3, 1, 39, "LHA8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #190 = LHA8
+ { 191, 4, 2, 33, "LHAU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #191 = LHAU
+ { 192, 4, 2, 33, "LHAU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #192 = LHAU8
+ { 193, 3, 1, 39, "LHAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #193 = LHAX
+ { 194, 3, 1, 39, "LHAX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #194 = LHAX8
+ { 195, 3, 1, 33, "LHBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #195 = LHBRX
+ { 196, 3, 1, 33, "LHZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #196 = LHZ
+ { 197, 3, 1, 33, "LHZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #197 = LHZ8
+ { 198, 4, 2, 33, "LHZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #198 = LHZU
+ { 199, 4, 2, 33, "LHZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #199 = LHZU8
+ { 200, 3, 1, 33, "LHZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #200 = LHZX
+ { 201, 3, 1, 33, "LHZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #201 = LHZX8
+ { 202, 2, 1, 14, "LI", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #202 = LI
+ { 203, 2, 1, 14, "LI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #203 = LI8
+ { 204, 2, 1, 14, "LIS", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #204 = LIS
+ { 205, 2, 1, 14, "LIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #205 = LIS8
+ { 206, 3, 1, 33, "LVEBX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #206 = LVEBX
+ { 207, 3, 1, 33, "LVEHX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #207 = LVEHX
+ { 208, 3, 1, 33, "LVEWX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #208 = LVEWX
+ { 209, 3, 1, 33, "LVSL", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #209 = LVSL
+ { 210, 3, 1, 33, "LVSR", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #210 = LVSR
+ { 211, 3, 1, 33, "LVX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #211 = LVX
+ { 212, 3, 1, 33, "LVXL", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #212 = LVXL
+ { 213, 3, 1, 42, "LWA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #213 = LWA
+ { 214, 3, 1, 43, "LWARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo46 }, // Inst #214 = LWARX
+ { 215, 3, 1, 39, "LWAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #215 = LWAX
+ { 216, 3, 1, 33, "LWBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #216 = LWBRX
+ { 217, 3, 1, 33, "LWZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #217 = LWZ
+ { 218, 3, 1, 33, "LWZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #218 = LWZ8
+ { 219, 4, 2, 33, "LWZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #219 = LWZU
+ { 220, 4, 2, 33, "LWZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #220 = LWZU8
+ { 221, 3, 1, 33, "LWZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #221 = LWZX
+ { 222, 3, 1, 33, "LWZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #222 = LWZX8
+ { 223, 2, 1, 2, "MCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo59 }, // Inst #223 = MCRF
+ { 224, 1, 1, 54, "MFCR", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #224 = MFCR
+ { 225, 1, 1, 56, "MFCTR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList4, NULL, NULL, OperandInfo60 }, // Inst #225 = MFCTR
+ { 226, 1, 1, 56, "MFCTR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList13, NULL, NULL, OperandInfo48 }, // Inst #226 = MFCTR8
+ { 227, 1, 1, 15, "MFFS", 0, 0|(1<<1)|(3<<3), ImplicitList10, NULL, NULL, OperandInfo61 }, // Inst #227 = MFFS
+ { 228, 1, 1, 56, "MFLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList14, NULL, NULL, OperandInfo60 }, // Inst #228 = MFLR
+ { 229, 1, 1, 56, "MFLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList15, NULL, NULL, OperandInfo48 }, // Inst #229 = MFLR8
+ { 230, 2, 1, 54, "MFOCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #230 = MFOCRF
+ { 231, 1, 1, 14, "MFVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #231 = MFVRSAVE
+ { 232, 1, 1, 33, "MFVSCR", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo62 }, // Inst #232 = MFVSCR
+ { 233, 2, 0, 3, "MTCRF", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo63 }, // Inst #233 = MTCRF
+ { 234, 1, 0, 60, "MTCTR", 0, 0|1|(1<<3), NULL, ImplicitList4, Barriers4, OperandInfo60 }, // Inst #234 = MTCTR
+ { 235, 1, 0, 60, "MTCTR8", 0, 0|1|(1<<3), NULL, ImplicitList13, Barriers5, OperandInfo48 }, // Inst #235 = MTCTR8
+ { 236, 1, 0, 17, "MTFSB0", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo8 }, // Inst #236 = MTFSB0
+ { 237, 1, 0, 17, "MTFSB1", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo8 }, // Inst #237 = MTFSB1
+ { 238, 4, 1, 17, "MTFSF", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo64 }, // Inst #238 = MTFSF
+ { 239, 1, 0, 60, "MTLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList14, NULL, OperandInfo60 }, // Inst #239 = MTLR
+ { 240, 1, 0, 60, "MTLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList15, NULL, OperandInfo48 }, // Inst #240 = MTLR8
+ { 241, 1, 0, 14, "MTVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<1)|(1<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #241 = MTVRSAVE
+ { 242, 1, 0, 33, "MTVSCR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo62 }, // Inst #242 = MTVSCR
+ { 243, 3, 1, 20, "MULHD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #243 = MULHD
+ { 244, 3, 1, 21, "MULHDU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #244 = MULHDU
+ { 245, 3, 1, 20, "MULHW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #245 = MULHW
+ { 246, 3, 1, 21, "MULHWU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #246 = MULHWU
+ { 247, 3, 1, 19, "MULLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #247 = MULLD
+ { 248, 3, 1, 22, "MULLI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #248 = MULLI
+ { 249, 3, 1, 20, "MULLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #249 = MULLW
+ { 250, 1, 0, 52, "MovePCtoLR", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList14, NULL, OperandInfo8 }, // Inst #250 = MovePCtoLR
+ { 251, 1, 0, 52, "MovePCtoLR8", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList15, NULL, OperandInfo8 }, // Inst #251 = MovePCtoLR8
+ { 252, 3, 1, 14, "NAND", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #252 = NAND
+ { 253, 3, 1, 14, "NAND8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #253 = NAND8
+ { 254, 2, 1, 14, "NEG", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #254 = NEG
+ { 255, 2, 1, 14, "NEG8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #255 = NEG8
+ { 256, 0, 0, 14, "NOP", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, 0 }, // Inst #256 = NOP
+ { 257, 3, 1, 14, "NOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #257 = NOR
+ { 258, 3, 1, 14, "NOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #258 = NOR8
+ { 259, 3, 1, 14, "OR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #259 = OR
+ { 260, 3, 1, 14, "OR4To8", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo65 }, // Inst #260 = OR4To8
+ { 261, 3, 1, 14, "OR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #261 = OR8
+ { 262, 3, 1, 14, "OR8To4", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo66 }, // Inst #262 = OR8To4
+ { 263, 3, 1, 14, "ORC", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #263 = ORC
+ { 264, 3, 1, 14, "ORC8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #264 = ORC8
+ { 265, 3, 1, 14, "ORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #265 = ORI
+ { 266, 3, 1, 14, "ORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #266 = ORI8
+ { 267, 3, 1, 14, "ORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #267 = ORIS
+ { 268, 3, 1, 14, "ORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #268 = ORIS8
+ { 269, 4, 1, 25, "RLDCL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo67 }, // Inst #269 = RLDCL
+ { 270, 4, 1, 25, "RLDICL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 }, // Inst #270 = RLDICL
+ { 271, 4, 1, 25, "RLDICR", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 }, // Inst #271 = RLDICR
+ { 272, 5, 1, 25, "RLDIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo69 }, // Inst #272 = RLDIMI
+ { 273, 6, 1, 24, "RLWIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo70 }, // Inst #273 = RLWIMI
+ { 274, 5, 1, 14, "RLWINM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo71 }, // Inst #274 = RLWINM
+ { 275, 5, 1, 14, "RLWINMo", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, ImplicitList3, NULL, OperandInfo71 }, // Inst #275 = RLWINMo
+ { 276, 5, 1, 14, "RLWNM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo72 }, // Inst #276 = RLWNM
+ { 277, 5, 1, 52, "SELECT_CC_F4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo73 }, // Inst #277 = SELECT_CC_F4
+ { 278, 5, 1, 52, "SELECT_CC_F8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo74 }, // Inst #278 = SELECT_CC_F8
+ { 279, 5, 1, 52, "SELECT_CC_I4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo75 }, // Inst #279 = SELECT_CC_I4
+ { 280, 5, 1, 52, "SELECT_CC_I8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo76 }, // Inst #280 = SELECT_CC_I8
+ { 281, 5, 1, 52, "SELECT_CC_VRRC", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo77 }, // Inst #281 = SELECT_CC_VRRC
+ { 282, 3, 1, 25, "SLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo78 }, // Inst #282 = SLD
+ { 283, 3, 1, 14, "SLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #283 = SLW
+ { 284, 3, 0, 52, "SPILL_CR", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo42 }, // Inst #284 = SPILL_CR
+ { 285, 3, 1, 25, "SRAD", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo78 }, // Inst #285 = SRAD
+ { 286, 3, 1, 25, "SRADI", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #286 = SRADI
+ { 287, 3, 1, 26, "SRAW", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #287 = SRAW
+ { 288, 3, 1, 26, "SRAWI", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #288 = SRAWI
+ { 289, 3, 1, 25, "SRD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo78 }, // Inst #289 = SRD
+ { 290, 3, 1, 14, "SRW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #290 = SRW
+ { 291, 3, 0, 33, "STB", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #291 = STB
+ { 292, 3, 0, 33, "STB8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #292 = STB8
+ { 293, 4, 1, 33, "STBU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #293 = STBU
+ { 294, 4, 1, 33, "STBU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #294 = STBU8
+ { 295, 3, 0, 33, "STBX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #295 = STBX
+ { 296, 3, 0, 33, "STBX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #296 = STBX8
+ { 297, 3, 0, 46, "STD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #297 = STD
+ { 298, 3, 0, 47, "STDCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList3, NULL, OperandInfo47 }, // Inst #298 = STDCX
+ { 299, 4, 1, 46, "STDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #299 = STDU
+ { 300, 3, 0, 46, "STDUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #300 = STDUX
+ { 301, 3, 0, 46, "STDX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #301 = STDX
+ { 302, 3, 0, 46, "STDX_32", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #302 = STDX_32
+ { 303, 3, 0, 46, "STD_32", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #303 = STD_32
+ { 304, 3, 0, 51, "STFD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 }, // Inst #304 = STFD
+ { 305, 4, 1, 33, "STFDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo81 }, // Inst #305 = STFDU
+ { 306, 3, 0, 51, "STFDX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #306 = STFDX
+ { 307, 3, 0, 51, "STFIWX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #307 = STFIWX
+ { 308, 3, 0, 51, "STFS", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo53 }, // Inst #308 = STFS
+ { 309, 4, 1, 33, "STFSU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo82 }, // Inst #309 = STFSU
+ { 310, 3, 0, 51, "STFSX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #310 = STFSX
+ { 311, 3, 0, 33, "STH", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #311 = STH
+ { 312, 3, 0, 33, "STH8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #312 = STH8
+ { 313, 3, 0, 33, "STHBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #313 = STHBRX
+ { 314, 4, 1, 33, "STHU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #314 = STHU
+ { 315, 4, 1, 33, "STHU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #315 = STHU8
+ { 316, 3, 0, 33, "STHX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #316 = STHX
+ { 317, 3, 0, 33, "STHX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #317 = STHX8
+ { 318, 3, 0, 33, "STVEBX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #318 = STVEBX
+ { 319, 3, 0, 33, "STVEHX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #319 = STVEHX
+ { 320, 3, 0, 33, "STVEWX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #320 = STVEWX
+ { 321, 3, 0, 33, "STVX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #321 = STVX
+ { 322, 3, 0, 33, "STVXL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #322 = STVXL
+ { 323, 3, 0, 33, "STW", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #323 = STW
+ { 324, 3, 0, 33, "STW8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #324 = STW8
+ { 325, 3, 0, 33, "STWBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #325 = STWBRX
+ { 326, 3, 0, 49, "STWCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList3, NULL, OperandInfo46 }, // Inst #326 = STWCX
+ { 327, 4, 1, 33, "STWU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #327 = STWU
+ { 328, 4, 1, 33, "STWU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #328 = STWU8
+ { 329, 3, 0, 33, "STWUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #329 = STWUX
+ { 330, 3, 0, 33, "STWX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #330 = STWX
+ { 331, 3, 0, 33, "STWX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #331 = STWX8
+ { 332, 3, 1, 14, "SUBF", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #332 = SUBF
+ { 333, 3, 1, 14, "SUBF8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #333 = SUBF8
+ { 334, 3, 1, 14, "SUBFC", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #334 = SUBFC
+ { 335, 3, 1, 14, "SUBFC8", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #335 = SUBFC8
+ { 336, 3, 1, 14, "SUBFE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #336 = SUBFE
+ { 337, 3, 1, 14, "SUBFE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #337 = SUBFE8
+ { 338, 3, 1, 14, "SUBFIC", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #338 = SUBFIC
+ { 339, 3, 1, 14, "SUBFIC8", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #339 = SUBFIC8
+ { 340, 2, 1, 14, "SUBFME", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #340 = SUBFME
+ { 341, 2, 1, 14, "SUBFME8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #341 = SUBFME8
+ { 342, 2, 1, 14, "SUBFZE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #342 = SUBFZE
+ { 343, 2, 1, 14, "SUBFZE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #343 = SUBFZE8
+ { 344, 0, 0, 50, "SYNC", 0|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #344 = SYNC
+ { 345, 1, 0, 0, "TAILB", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #345 = TAILB
+ { 346, 1, 0, 0, "TAILB8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #346 = TAILB8
+ { 347, 1, 0, 0, "TAILBA", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #347 = TAILBA
+ { 348, 1, 0, 0, "TAILBA8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #348 = TAILBA8
+ { 349, 0, 0, 0, "TAILBCTR", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList7, NULL, NULL, 0 }, // Inst #349 = TAILBCTR
+ { 350, 0, 0, 0, "TAILBCTR8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList7, NULL, NULL, 0 }, // Inst #350 = TAILBCTR8
+ { 351, 2, 0, 52, "TCRETURNai", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #351 = TCRETURNai
+ { 352, 2, 0, 52, "TCRETURNai8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #352 = TCRETURNai8
+ { 353, 2, 0, 52, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #353 = TCRETURNdi
+ { 354, 2, 0, 52, "TCRETURNdi8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #354 = TCRETURNdi8
+ { 355, 2, 0, 52, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo83 }, // Inst #355 = TCRETURNri
+ { 356, 2, 0, 52, "TCRETURNri8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo84 }, // Inst #356 = TCRETURNri8
+ { 357, 0, 0, 33, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #357 = TRAP
+ { 358, 2, 1, 52, "UPDATE_VRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo6 }, // Inst #358 = UPDATE_VRSAVE
+ { 359, 3, 1, 67, "VADDCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #359 = VADDCUW
+ { 360, 3, 1, 67, "VADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #360 = VADDFP
+ { 361, 3, 1, 67, "VADDSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #361 = VADDSBS
+ { 362, 3, 1, 67, "VADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #362 = VADDSHS
+ { 363, 3, 1, 67, "VADDSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #363 = VADDSWS
+ { 364, 3, 1, 70, "VADDUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #364 = VADDUBM
+ { 365, 3, 1, 67, "VADDUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #365 = VADDUBS
+ { 366, 3, 1, 70, "VADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #366 = VADDUHM
+ { 367, 3, 1, 67, "VADDUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #367 = VADDUHS
+ { 368, 3, 1, 70, "VADDUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #368 = VADDUWM
+ { 369, 3, 1, 67, "VADDUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #369 = VADDUWS
+ { 370, 3, 1, 67, "VAND", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #370 = VAND
+ { 371, 3, 1, 67, "VANDC", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #371 = VANDC
+ { 372, 3, 1, 67, "VAVGSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #372 = VAVGSB
+ { 373, 3, 1, 67, "VAVGSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #373 = VAVGSH
+ { 374, 3, 1, 67, "VAVGSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #374 = VAVGSW
+ { 375, 3, 1, 67, "VAVGUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #375 = VAVGUB
+ { 376, 3, 1, 67, "VAVGUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #376 = VAVGUH
+ { 377, 3, 1, 67, "VAVGUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #377 = VAVGUW
+ { 378, 3, 1, 67, "VCFSX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #378 = VCFSX
+ { 379, 3, 1, 67, "VCFUX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #379 = VCFUX
+ { 380, 3, 1, 68, "VCMPBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #380 = VCMPBFP
+ { 381, 3, 1, 68, "VCMPBFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #381 = VCMPBFPo
+ { 382, 3, 1, 68, "VCMPEQFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #382 = VCMPEQFP
+ { 383, 3, 1, 68, "VCMPEQFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #383 = VCMPEQFPo
+ { 384, 3, 1, 68, "VCMPEQUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #384 = VCMPEQUB
+ { 385, 3, 1, 68, "VCMPEQUBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #385 = VCMPEQUBo
+ { 386, 3, 1, 68, "VCMPEQUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #386 = VCMPEQUH
+ { 387, 3, 1, 68, "VCMPEQUHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #387 = VCMPEQUHo
+ { 388, 3, 1, 68, "VCMPEQUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #388 = VCMPEQUW
+ { 389, 3, 1, 68, "VCMPEQUWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #389 = VCMPEQUWo
+ { 390, 3, 1, 68, "VCMPGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #390 = VCMPGEFP
+ { 391, 3, 1, 68, "VCMPGEFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #391 = VCMPGEFPo
+ { 392, 3, 1, 68, "VCMPGTFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #392 = VCMPGTFP
+ { 393, 3, 1, 68, "VCMPGTFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #393 = VCMPGTFPo
+ { 394, 3, 1, 68, "VCMPGTSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #394 = VCMPGTSB
+ { 395, 3, 1, 68, "VCMPGTSBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #395 = VCMPGTSBo
+ { 396, 3, 1, 68, "VCMPGTSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #396 = VCMPGTSH
+ { 397, 3, 1, 68, "VCMPGTSHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #397 = VCMPGTSHo
+ { 398, 3, 1, 68, "VCMPGTSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #398 = VCMPGTSW
+ { 399, 3, 1, 68, "VCMPGTSWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #399 = VCMPGTSWo
+ { 400, 3, 1, 68, "VCMPGTUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #400 = VCMPGTUB
+ { 401, 3, 1, 68, "VCMPGTUBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #401 = VCMPGTUBo
+ { 402, 3, 1, 68, "VCMPGTUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #402 = VCMPGTUH
+ { 403, 3, 1, 68, "VCMPGTUHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #403 = VCMPGTUHo
+ { 404, 3, 1, 68, "VCMPGTUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #404 = VCMPGTUW
+ { 405, 3, 1, 68, "VCMPGTUWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #405 = VCMPGTUWo
+ { 406, 3, 1, 67, "VCTSXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #406 = VCTSXS
+ { 407, 3, 1, 67, "VCTUXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #407 = VCTUXS
+ { 408, 2, 1, 67, "VEXPTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #408 = VEXPTEFP
+ { 409, 2, 1, 67, "VLOGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #409 = VLOGEFP
+ { 410, 4, 1, 67, "VMADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #410 = VMADDFP
+ { 411, 3, 1, 67, "VMAXFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #411 = VMAXFP
+ { 412, 3, 1, 67, "VMAXSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #412 = VMAXSB
+ { 413, 3, 1, 67, "VMAXSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #413 = VMAXSH
+ { 414, 3, 1, 67, "VMAXSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #414 = VMAXSW
+ { 415, 3, 1, 67, "VMAXUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #415 = VMAXUB
+ { 416, 3, 1, 67, "VMAXUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #416 = VMAXUH
+ { 417, 3, 1, 67, "VMAXUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #417 = VMAXUW
+ { 418, 4, 1, 67, "VMHADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #418 = VMHADDSHS
+ { 419, 4, 1, 67, "VMHRADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #419 = VMHRADDSHS
+ { 420, 3, 1, 67, "VMINFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #420 = VMINFP
+ { 421, 3, 1, 67, "VMINSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #421 = VMINSB
+ { 422, 3, 1, 67, "VMINSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #422 = VMINSH
+ { 423, 3, 1, 67, "VMINSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #423 = VMINSW
+ { 424, 3, 1, 67, "VMINUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #424 = VMINUB
+ { 425, 3, 1, 67, "VMINUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #425 = VMINUH
+ { 426, 3, 1, 67, "VMINUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #426 = VMINUW
+ { 427, 4, 1, 67, "VMLADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #427 = VMLADDUHM
+ { 428, 3, 1, 67, "VMRGHB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #428 = VMRGHB
+ { 429, 3, 1, 67, "VMRGHH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #429 = VMRGHH
+ { 430, 3, 1, 67, "VMRGHW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #430 = VMRGHW
+ { 431, 3, 1, 67, "VMRGLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #431 = VMRGLB
+ { 432, 3, 1, 67, "VMRGLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #432 = VMRGLH
+ { 433, 3, 1, 67, "VMRGLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #433 = VMRGLW
+ { 434, 4, 1, 67, "VMSUMMBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #434 = VMSUMMBM
+ { 435, 4, 1, 67, "VMSUMSHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #435 = VMSUMSHM
+ { 436, 4, 1, 67, "VMSUMSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #436 = VMSUMSHS
+ { 437, 4, 1, 67, "VMSUMUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #437 = VMSUMUBM
+ { 438, 4, 1, 67, "VMSUMUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #438 = VMSUMUHM
+ { 439, 4, 1, 67, "VMSUMUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #439 = VMSUMUHS
+ { 440, 3, 1, 67, "VMULESB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #440 = VMULESB
+ { 441, 3, 1, 67, "VMULESH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #441 = VMULESH
+ { 442, 3, 1, 67, "VMULEUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #442 = VMULEUB
+ { 443, 3, 1, 67, "VMULEUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #443 = VMULEUH
+ { 444, 3, 1, 67, "VMULOSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #444 = VMULOSB
+ { 445, 3, 1, 67, "VMULOSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #445 = VMULOSH
+ { 446, 3, 1, 67, "VMULOUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #446 = VMULOUB
+ { 447, 3, 1, 67, "VMULOUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #447 = VMULOUH
+ { 448, 4, 1, 67, "VNMSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #448 = VNMSUBFP
+ { 449, 3, 1, 67, "VNOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #449 = VNOR
+ { 450, 3, 1, 67, "VOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #450 = VOR
+ { 451, 4, 1, 67, "VPERM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #451 = VPERM
+ { 452, 3, 1, 67, "VPKPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #452 = VPKPX
+ { 453, 3, 1, 67, "VPKSHSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #453 = VPKSHSS
+ { 454, 3, 1, 67, "VPKSHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #454 = VPKSHUS
+ { 455, 3, 1, 67, "VPKSWSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #455 = VPKSWSS
+ { 456, 3, 1, 67, "VPKSWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #456 = VPKSWUS
+ { 457, 3, 1, 67, "VPKUHUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #457 = VPKUHUM
+ { 458, 3, 1, 67, "VPKUHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #458 = VPKUHUS
+ { 459, 3, 1, 67, "VPKUWUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #459 = VPKUWUM
+ { 460, 3, 1, 67, "VPKUWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #460 = VPKUWUS
+ { 461, 2, 1, 67, "VREFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #461 = VREFP
+ { 462, 2, 1, 67, "VRFIM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #462 = VRFIM
+ { 463, 2, 1, 67, "VRFIN", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #463 = VRFIN
+ { 464, 2, 1, 67, "VRFIP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #464 = VRFIP
+ { 465, 2, 1, 67, "VRFIZ", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #465 = VRFIZ
+ { 466, 3, 1, 67, "VRLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #466 = VRLB
+ { 467, 3, 1, 67, "VRLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #467 = VRLH
+ { 468, 3, 1, 67, "VRLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #468 = VRLW
+ { 469, 2, 1, 67, "VRSQRTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #469 = VRSQRTEFP
+ { 470, 4, 1, 67, "VSEL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #470 = VSEL
+ { 471, 3, 1, 67, "VSL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #471 = VSL
+ { 472, 3, 1, 67, "VSLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #472 = VSLB
+ { 473, 4, 1, 67, "VSLDOI", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo89 }, // Inst #473 = VSLDOI
+ { 474, 3, 1, 67, "VSLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #474 = VSLH
+ { 475, 3, 1, 67, "VSLO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #475 = VSLO
+ { 476, 3, 1, 67, "VSLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #476 = VSLW
+ { 477, 3, 1, 71, "VSPLTB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #477 = VSPLTB
+ { 478, 3, 1, 71, "VSPLTH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #478 = VSPLTH
+ { 479, 2, 1, 71, "VSPLTISB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #479 = VSPLTISB
+ { 480, 2, 1, 71, "VSPLTISH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #480 = VSPLTISH
+ { 481, 2, 1, 71, "VSPLTISW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #481 = VSPLTISW
+ { 482, 3, 1, 71, "VSPLTW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #482 = VSPLTW
+ { 483, 3, 1, 67, "VSR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #483 = VSR
+ { 484, 3, 1, 67, "VSRAB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #484 = VSRAB
+ { 485, 3, 1, 67, "VSRAH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #485 = VSRAH
+ { 486, 3, 1, 67, "VSRAW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #486 = VSRAW
+ { 487, 3, 1, 67, "VSRB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #487 = VSRB
+ { 488, 3, 1, 67, "VSRH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #488 = VSRH
+ { 489, 3, 1, 67, "VSRO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #489 = VSRO
+ { 490, 3, 1, 67, "VSRW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #490 = VSRW
+ { 491, 3, 1, 67, "VSUBCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #491 = VSUBCUW
+ { 492, 3, 1, 70, "VSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #492 = VSUBFP
+ { 493, 3, 1, 67, "VSUBSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #493 = VSUBSBS
+ { 494, 3, 1, 67, "VSUBSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #494 = VSUBSHS
+ { 495, 3, 1, 67, "VSUBSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #495 = VSUBSWS
+ { 496, 3, 1, 70, "VSUBUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #496 = VSUBUBM
+ { 497, 3, 1, 67, "VSUBUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #497 = VSUBUBS
+ { 498, 3, 1, 70, "VSUBUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #498 = VSUBUHM
+ { 499, 3, 1, 67, "VSUBUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #499 = VSUBUHS
+ { 500, 3, 1, 70, "VSUBUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #500 = VSUBUWM
+ { 501, 3, 1, 67, "VSUBUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #501 = VSUBUWS
+ { 502, 3, 1, 67, "VSUM2SWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #502 = VSUM2SWS
+ { 503, 3, 1, 67, "VSUM4SBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #503 = VSUM4SBS
+ { 504, 3, 1, 67, "VSUM4SHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #504 = VSUM4SHS
+ { 505, 3, 1, 67, "VSUM4UBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #505 = VSUM4UBS
+ { 506, 3, 1, 67, "VSUMSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #506 = VSUMSWS
+ { 507, 2, 1, 67, "VUPKHPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #507 = VUPKHPX
+ { 508, 2, 1, 67, "VUPKHSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #508 = VUPKHSB
+ { 509, 2, 1, 67, "VUPKHSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #509 = VUPKHSH
+ { 510, 2, 1, 67, "VUPKLPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #510 = VUPKLPX
+ { 511, 2, 1, 67, "VUPKLSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #511 = VUPKLSB
+ { 512, 2, 1, 67, "VUPKLSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #512 = VUPKLSH
+ { 513, 3, 1, 67, "VXOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #513 = VXOR
+ { 514, 1, 1, 67, "V_SET0", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo62 }, // Inst #514 = V_SET0
+ { 515, 3, 1, 14, "XOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #515 = XOR
+ { 516, 3, 1, 14, "XOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #516 = XOR8
+ { 517, 3, 1, 14, "XORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #517 = XORI
+ { 518, 3, 1, 14, "XORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #518 = XORI8
+ { 519, 3, 1, 14, "XORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #519 = XORIS
+ { 520, 3, 1, 14, "XORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #520 = XORIS8
};
} // End llvm namespace
diff --git a/libclamav/c++/PPCGenInstrNames.inc b/libclamav/c++/PPCGenInstrNames.inc
index eb88431..06e0e36 100644
--- a/libclamav/c++/PPCGenInstrNames.inc
+++ b/libclamav/c++/PPCGenInstrNames.inc
@@ -21,516 +21,517 @@ namespace PPC {
IMPLICIT_DEF = 8,
SUBREG_TO_REG = 9,
COPY_TO_REGCLASS = 10,
- ADD4 = 11,
- ADD8 = 12,
- ADDC = 13,
- ADDC8 = 14,
- ADDE = 15,
- ADDE8 = 16,
- ADDI = 17,
- ADDI8 = 18,
- ADDIC = 19,
- ADDIC8 = 20,
- ADDICo = 21,
- ADDIS = 22,
- ADDIS8 = 23,
- ADDME = 24,
- ADDME8 = 25,
- ADDZE = 26,
- ADDZE8 = 27,
- ADJCALLSTACKDOWN = 28,
- ADJCALLSTACKUP = 29,
- AND = 30,
- AND8 = 31,
- ANDC = 32,
- ANDC8 = 33,
- ANDISo = 34,
- ANDISo8 = 35,
- ANDIo = 36,
- ANDIo8 = 37,
- ATOMIC_CMP_SWAP_I16 = 38,
- ATOMIC_CMP_SWAP_I32 = 39,
- ATOMIC_CMP_SWAP_I64 = 40,
- ATOMIC_CMP_SWAP_I8 = 41,
- ATOMIC_LOAD_ADD_I16 = 42,
- ATOMIC_LOAD_ADD_I32 = 43,
- ATOMIC_LOAD_ADD_I64 = 44,
- ATOMIC_LOAD_ADD_I8 = 45,
- ATOMIC_LOAD_AND_I16 = 46,
- ATOMIC_LOAD_AND_I32 = 47,
- ATOMIC_LOAD_AND_I64 = 48,
- ATOMIC_LOAD_AND_I8 = 49,
- ATOMIC_LOAD_NAND_I16 = 50,
- ATOMIC_LOAD_NAND_I32 = 51,
- ATOMIC_LOAD_NAND_I64 = 52,
- ATOMIC_LOAD_NAND_I8 = 53,
- ATOMIC_LOAD_OR_I16 = 54,
- ATOMIC_LOAD_OR_I32 = 55,
- ATOMIC_LOAD_OR_I64 = 56,
- ATOMIC_LOAD_OR_I8 = 57,
- ATOMIC_LOAD_SUB_I16 = 58,
- ATOMIC_LOAD_SUB_I32 = 59,
- ATOMIC_LOAD_SUB_I64 = 60,
- ATOMIC_LOAD_SUB_I8 = 61,
- ATOMIC_LOAD_XOR_I16 = 62,
- ATOMIC_LOAD_XOR_I32 = 63,
- ATOMIC_LOAD_XOR_I64 = 64,
- ATOMIC_LOAD_XOR_I8 = 65,
- ATOMIC_SWAP_I16 = 66,
- ATOMIC_SWAP_I32 = 67,
- ATOMIC_SWAP_I64 = 68,
- ATOMIC_SWAP_I8 = 69,
- B = 70,
- BCC = 71,
- BCTR = 72,
- BCTRL8_Darwin = 73,
- BCTRL8_ELF = 74,
- BCTRL_Darwin = 75,
- BCTRL_SVR4 = 76,
- BL8_Darwin = 77,
- BL8_ELF = 78,
- BLA8_Darwin = 79,
- BLA8_ELF = 80,
- BLA_Darwin = 81,
- BLA_SVR4 = 82,
- BLR = 83,
- BL_Darwin = 84,
- BL_SVR4 = 85,
- CMPD = 86,
- CMPDI = 87,
- CMPLD = 88,
- CMPLDI = 89,
- CMPLW = 90,
- CMPLWI = 91,
- CMPW = 92,
- CMPWI = 93,
- CNTLZD = 94,
- CNTLZW = 95,
- CREQV = 96,
- CROR = 97,
- CRSET = 98,
- DCBA = 99,
- DCBF = 100,
- DCBI = 101,
- DCBST = 102,
- DCBT = 103,
- DCBTST = 104,
- DCBZ = 105,
- DCBZL = 106,
- DIVD = 107,
- DIVDU = 108,
- DIVW = 109,
- DIVWU = 110,
- DSS = 111,
- DSSALL = 112,
- DST = 113,
- DST64 = 114,
- DSTST = 115,
- DSTST64 = 116,
- DSTSTT = 117,
- DSTSTT64 = 118,
- DSTT = 119,
- DSTT64 = 120,
- DYNALLOC = 121,
- DYNALLOC8 = 122,
- EQV = 123,
- EQV8 = 124,
- EXTSB = 125,
- EXTSB8 = 126,
- EXTSH = 127,
- EXTSH8 = 128,
- EXTSW = 129,
- EXTSW_32 = 130,
- EXTSW_32_64 = 131,
- FABSD = 132,
- FABSS = 133,
- FADD = 134,
- FADDS = 135,
- FADDrtz = 136,
- FCFID = 137,
- FCMPUD = 138,
- FCMPUS = 139,
- FCTIDZ = 140,
- FCTIWZ = 141,
- FDIV = 142,
- FDIVS = 143,
- FMADD = 144,
- FMADDS = 145,
- FMRD = 146,
- FMRS = 147,
- FMRSD = 148,
- FMSUB = 149,
- FMSUBS = 150,
- FMUL = 151,
- FMULS = 152,
- FNABSD = 153,
- FNABSS = 154,
- FNEGD = 155,
- FNEGS = 156,
- FNMADD = 157,
- FNMADDS = 158,
- FNMSUB = 159,
- FNMSUBS = 160,
- FRSP = 161,
- FSELD = 162,
- FSELS = 163,
- FSQRT = 164,
- FSQRTS = 165,
- FSUB = 166,
- FSUBS = 167,
- LA = 168,
- LBZ = 169,
- LBZ8 = 170,
- LBZU = 171,
- LBZU8 = 172,
- LBZX = 173,
- LBZX8 = 174,
- LD = 175,
- LDARX = 176,
- LDU = 177,
- LDX = 178,
- LDinto_toc = 179,
- LDtoc = 180,
- LDtoc_restore = 181,
- LFD = 182,
- LFDU = 183,
- LFDX = 184,
- LFS = 185,
- LFSU = 186,
- LFSX = 187,
- LHA = 188,
- LHA8 = 189,
- LHAU = 190,
- LHAU8 = 191,
- LHAX = 192,
- LHAX8 = 193,
- LHBRX = 194,
- LHZ = 195,
- LHZ8 = 196,
- LHZU = 197,
- LHZU8 = 198,
- LHZX = 199,
- LHZX8 = 200,
- LI = 201,
- LI8 = 202,
- LIS = 203,
- LIS8 = 204,
- LVEBX = 205,
- LVEHX = 206,
- LVEWX = 207,
- LVSL = 208,
- LVSR = 209,
- LVX = 210,
- LVXL = 211,
- LWA = 212,
- LWARX = 213,
- LWAX = 214,
- LWBRX = 215,
- LWZ = 216,
- LWZ8 = 217,
- LWZU = 218,
- LWZU8 = 219,
- LWZX = 220,
- LWZX8 = 221,
- MCRF = 222,
- MFCR = 223,
- MFCTR = 224,
- MFCTR8 = 225,
- MFFS = 226,
- MFLR = 227,
- MFLR8 = 228,
- MFOCRF = 229,
- MFVRSAVE = 230,
- MFVSCR = 231,
- MTCRF = 232,
- MTCTR = 233,
- MTCTR8 = 234,
- MTFSB0 = 235,
- MTFSB1 = 236,
- MTFSF = 237,
- MTLR = 238,
- MTLR8 = 239,
- MTVRSAVE = 240,
- MTVSCR = 241,
- MULHD = 242,
- MULHDU = 243,
- MULHW = 244,
- MULHWU = 245,
- MULLD = 246,
- MULLI = 247,
- MULLW = 248,
- MovePCtoLR = 249,
- MovePCtoLR8 = 250,
- NAND = 251,
- NAND8 = 252,
- NEG = 253,
- NEG8 = 254,
- NOP = 255,
- NOR = 256,
- NOR8 = 257,
- OR = 258,
- OR4To8 = 259,
- OR8 = 260,
- OR8To4 = 261,
- ORC = 262,
- ORC8 = 263,
- ORI = 264,
- ORI8 = 265,
- ORIS = 266,
- ORIS8 = 267,
- RLDCL = 268,
- RLDICL = 269,
- RLDICR = 270,
- RLDIMI = 271,
- RLWIMI = 272,
- RLWINM = 273,
- RLWINMo = 274,
- RLWNM = 275,
- SELECT_CC_F4 = 276,
- SELECT_CC_F8 = 277,
- SELECT_CC_I4 = 278,
- SELECT_CC_I8 = 279,
- SELECT_CC_VRRC = 280,
- SLD = 281,
- SLW = 282,
- SPILL_CR = 283,
- SRAD = 284,
- SRADI = 285,
- SRAW = 286,
- SRAWI = 287,
- SRD = 288,
- SRW = 289,
- STB = 290,
- STB8 = 291,
- STBU = 292,
- STBU8 = 293,
- STBX = 294,
- STBX8 = 295,
- STD = 296,
- STDCX = 297,
- STDU = 298,
- STDUX = 299,
- STDX = 300,
- STDX_32 = 301,
- STD_32 = 302,
- STFD = 303,
- STFDU = 304,
- STFDX = 305,
- STFIWX = 306,
- STFS = 307,
- STFSU = 308,
- STFSX = 309,
- STH = 310,
- STH8 = 311,
- STHBRX = 312,
- STHU = 313,
- STHU8 = 314,
- STHX = 315,
- STHX8 = 316,
- STVEBX = 317,
- STVEHX = 318,
- STVEWX = 319,
- STVX = 320,
- STVXL = 321,
- STW = 322,
- STW8 = 323,
- STWBRX = 324,
- STWCX = 325,
- STWU = 326,
- STWU8 = 327,
- STWUX = 328,
- STWX = 329,
- STWX8 = 330,
- SUBF = 331,
- SUBF8 = 332,
- SUBFC = 333,
- SUBFC8 = 334,
- SUBFE = 335,
- SUBFE8 = 336,
- SUBFIC = 337,
- SUBFIC8 = 338,
- SUBFME = 339,
- SUBFME8 = 340,
- SUBFZE = 341,
- SUBFZE8 = 342,
- SYNC = 343,
- TAILB = 344,
- TAILB8 = 345,
- TAILBA = 346,
- TAILBA8 = 347,
- TAILBCTR = 348,
- TAILBCTR8 = 349,
- TCRETURNai = 350,
- TCRETURNai8 = 351,
- TCRETURNdi = 352,
- TCRETURNdi8 = 353,
- TCRETURNri = 354,
- TCRETURNri8 = 355,
- TRAP = 356,
- UPDATE_VRSAVE = 357,
- VADDCUW = 358,
- VADDFP = 359,
- VADDSBS = 360,
- VADDSHS = 361,
- VADDSWS = 362,
- VADDUBM = 363,
- VADDUBS = 364,
- VADDUHM = 365,
- VADDUHS = 366,
- VADDUWM = 367,
- VADDUWS = 368,
- VAND = 369,
- VANDC = 370,
- VAVGSB = 371,
- VAVGSH = 372,
- VAVGSW = 373,
- VAVGUB = 374,
- VAVGUH = 375,
- VAVGUW = 376,
- VCFSX = 377,
- VCFUX = 378,
- VCMPBFP = 379,
- VCMPBFPo = 380,
- VCMPEQFP = 381,
- VCMPEQFPo = 382,
- VCMPEQUB = 383,
- VCMPEQUBo = 384,
- VCMPEQUH = 385,
- VCMPEQUHo = 386,
- VCMPEQUW = 387,
- VCMPEQUWo = 388,
- VCMPGEFP = 389,
- VCMPGEFPo = 390,
- VCMPGTFP = 391,
- VCMPGTFPo = 392,
- VCMPGTSB = 393,
- VCMPGTSBo = 394,
- VCMPGTSH = 395,
- VCMPGTSHo = 396,
- VCMPGTSW = 397,
- VCMPGTSWo = 398,
- VCMPGTUB = 399,
- VCMPGTUBo = 400,
- VCMPGTUH = 401,
- VCMPGTUHo = 402,
- VCMPGTUW = 403,
- VCMPGTUWo = 404,
- VCTSXS = 405,
- VCTUXS = 406,
- VEXPTEFP = 407,
- VLOGEFP = 408,
- VMADDFP = 409,
- VMAXFP = 410,
- VMAXSB = 411,
- VMAXSH = 412,
- VMAXSW = 413,
- VMAXUB = 414,
- VMAXUH = 415,
- VMAXUW = 416,
- VMHADDSHS = 417,
- VMHRADDSHS = 418,
- VMINFP = 419,
- VMINSB = 420,
- VMINSH = 421,
- VMINSW = 422,
- VMINUB = 423,
- VMINUH = 424,
- VMINUW = 425,
- VMLADDUHM = 426,
- VMRGHB = 427,
- VMRGHH = 428,
- VMRGHW = 429,
- VMRGLB = 430,
- VMRGLH = 431,
- VMRGLW = 432,
- VMSUMMBM = 433,
- VMSUMSHM = 434,
- VMSUMSHS = 435,
- VMSUMUBM = 436,
- VMSUMUHM = 437,
- VMSUMUHS = 438,
- VMULESB = 439,
- VMULESH = 440,
- VMULEUB = 441,
- VMULEUH = 442,
- VMULOSB = 443,
- VMULOSH = 444,
- VMULOUB = 445,
- VMULOUH = 446,
- VNMSUBFP = 447,
- VNOR = 448,
- VOR = 449,
- VPERM = 450,
- VPKPX = 451,
- VPKSHSS = 452,
- VPKSHUS = 453,
- VPKSWSS = 454,
- VPKSWUS = 455,
- VPKUHUM = 456,
- VPKUHUS = 457,
- VPKUWUM = 458,
- VPKUWUS = 459,
- VREFP = 460,
- VRFIM = 461,
- VRFIN = 462,
- VRFIP = 463,
- VRFIZ = 464,
- VRLB = 465,
- VRLH = 466,
- VRLW = 467,
- VRSQRTEFP = 468,
- VSEL = 469,
- VSL = 470,
- VSLB = 471,
- VSLDOI = 472,
- VSLH = 473,
- VSLO = 474,
- VSLW = 475,
- VSPLTB = 476,
- VSPLTH = 477,
- VSPLTISB = 478,
- VSPLTISH = 479,
- VSPLTISW = 480,
- VSPLTW = 481,
- VSR = 482,
- VSRAB = 483,
- VSRAH = 484,
- VSRAW = 485,
- VSRB = 486,
- VSRH = 487,
- VSRO = 488,
- VSRW = 489,
- VSUBCUW = 490,
- VSUBFP = 491,
- VSUBSBS = 492,
- VSUBSHS = 493,
- VSUBSWS = 494,
- VSUBUBM = 495,
- VSUBUBS = 496,
- VSUBUHM = 497,
- VSUBUHS = 498,
- VSUBUWM = 499,
- VSUBUWS = 500,
- VSUM2SWS = 501,
- VSUM4SBS = 502,
- VSUM4SHS = 503,
- VSUM4UBS = 504,
- VSUMSWS = 505,
- VUPKHPX = 506,
- VUPKHSB = 507,
- VUPKHSH = 508,
- VUPKLPX = 509,
- VUPKLSB = 510,
- VUPKLSH = 511,
- VXOR = 512,
- V_SET0 = 513,
- XOR = 514,
- XOR8 = 515,
- XORI = 516,
- XORI8 = 517,
- XORIS = 518,
- XORIS8 = 519,
- INSTRUCTION_LIST_END = 520
+ DEBUG_VALUE = 11,
+ ADD4 = 12,
+ ADD8 = 13,
+ ADDC = 14,
+ ADDC8 = 15,
+ ADDE = 16,
+ ADDE8 = 17,
+ ADDI = 18,
+ ADDI8 = 19,
+ ADDIC = 20,
+ ADDIC8 = 21,
+ ADDICo = 22,
+ ADDIS = 23,
+ ADDIS8 = 24,
+ ADDME = 25,
+ ADDME8 = 26,
+ ADDZE = 27,
+ ADDZE8 = 28,
+ ADJCALLSTACKDOWN = 29,
+ ADJCALLSTACKUP = 30,
+ AND = 31,
+ AND8 = 32,
+ ANDC = 33,
+ ANDC8 = 34,
+ ANDISo = 35,
+ ANDISo8 = 36,
+ ANDIo = 37,
+ ANDIo8 = 38,
+ ATOMIC_CMP_SWAP_I16 = 39,
+ ATOMIC_CMP_SWAP_I32 = 40,
+ ATOMIC_CMP_SWAP_I64 = 41,
+ ATOMIC_CMP_SWAP_I8 = 42,
+ ATOMIC_LOAD_ADD_I16 = 43,
+ ATOMIC_LOAD_ADD_I32 = 44,
+ ATOMIC_LOAD_ADD_I64 = 45,
+ ATOMIC_LOAD_ADD_I8 = 46,
+ ATOMIC_LOAD_AND_I16 = 47,
+ ATOMIC_LOAD_AND_I32 = 48,
+ ATOMIC_LOAD_AND_I64 = 49,
+ ATOMIC_LOAD_AND_I8 = 50,
+ ATOMIC_LOAD_NAND_I16 = 51,
+ ATOMIC_LOAD_NAND_I32 = 52,
+ ATOMIC_LOAD_NAND_I64 = 53,
+ ATOMIC_LOAD_NAND_I8 = 54,
+ ATOMIC_LOAD_OR_I16 = 55,
+ ATOMIC_LOAD_OR_I32 = 56,
+ ATOMIC_LOAD_OR_I64 = 57,
+ ATOMIC_LOAD_OR_I8 = 58,
+ ATOMIC_LOAD_SUB_I16 = 59,
+ ATOMIC_LOAD_SUB_I32 = 60,
+ ATOMIC_LOAD_SUB_I64 = 61,
+ ATOMIC_LOAD_SUB_I8 = 62,
+ ATOMIC_LOAD_XOR_I16 = 63,
+ ATOMIC_LOAD_XOR_I32 = 64,
+ ATOMIC_LOAD_XOR_I64 = 65,
+ ATOMIC_LOAD_XOR_I8 = 66,
+ ATOMIC_SWAP_I16 = 67,
+ ATOMIC_SWAP_I32 = 68,
+ ATOMIC_SWAP_I64 = 69,
+ ATOMIC_SWAP_I8 = 70,
+ B = 71,
+ BCC = 72,
+ BCTR = 73,
+ BCTRL8_Darwin = 74,
+ BCTRL8_ELF = 75,
+ BCTRL_Darwin = 76,
+ BCTRL_SVR4 = 77,
+ BL8_Darwin = 78,
+ BL8_ELF = 79,
+ BLA8_Darwin = 80,
+ BLA8_ELF = 81,
+ BLA_Darwin = 82,
+ BLA_SVR4 = 83,
+ BLR = 84,
+ BL_Darwin = 85,
+ BL_SVR4 = 86,
+ CMPD = 87,
+ CMPDI = 88,
+ CMPLD = 89,
+ CMPLDI = 90,
+ CMPLW = 91,
+ CMPLWI = 92,
+ CMPW = 93,
+ CMPWI = 94,
+ CNTLZD = 95,
+ CNTLZW = 96,
+ CREQV = 97,
+ CROR = 98,
+ CRSET = 99,
+ DCBA = 100,
+ DCBF = 101,
+ DCBI = 102,
+ DCBST = 103,
+ DCBT = 104,
+ DCBTST = 105,
+ DCBZ = 106,
+ DCBZL = 107,
+ DIVD = 108,
+ DIVDU = 109,
+ DIVW = 110,
+ DIVWU = 111,
+ DSS = 112,
+ DSSALL = 113,
+ DST = 114,
+ DST64 = 115,
+ DSTST = 116,
+ DSTST64 = 117,
+ DSTSTT = 118,
+ DSTSTT64 = 119,
+ DSTT = 120,
+ DSTT64 = 121,
+ DYNALLOC = 122,
+ DYNALLOC8 = 123,
+ EQV = 124,
+ EQV8 = 125,
+ EXTSB = 126,
+ EXTSB8 = 127,
+ EXTSH = 128,
+ EXTSH8 = 129,
+ EXTSW = 130,
+ EXTSW_32 = 131,
+ EXTSW_32_64 = 132,
+ FABSD = 133,
+ FABSS = 134,
+ FADD = 135,
+ FADDS = 136,
+ FADDrtz = 137,
+ FCFID = 138,
+ FCMPUD = 139,
+ FCMPUS = 140,
+ FCTIDZ = 141,
+ FCTIWZ = 142,
+ FDIV = 143,
+ FDIVS = 144,
+ FMADD = 145,
+ FMADDS = 146,
+ FMRD = 147,
+ FMRS = 148,
+ FMRSD = 149,
+ FMSUB = 150,
+ FMSUBS = 151,
+ FMUL = 152,
+ FMULS = 153,
+ FNABSD = 154,
+ FNABSS = 155,
+ FNEGD = 156,
+ FNEGS = 157,
+ FNMADD = 158,
+ FNMADDS = 159,
+ FNMSUB = 160,
+ FNMSUBS = 161,
+ FRSP = 162,
+ FSELD = 163,
+ FSELS = 164,
+ FSQRT = 165,
+ FSQRTS = 166,
+ FSUB = 167,
+ FSUBS = 168,
+ LA = 169,
+ LBZ = 170,
+ LBZ8 = 171,
+ LBZU = 172,
+ LBZU8 = 173,
+ LBZX = 174,
+ LBZX8 = 175,
+ LD = 176,
+ LDARX = 177,
+ LDU = 178,
+ LDX = 179,
+ LDinto_toc = 180,
+ LDtoc = 181,
+ LDtoc_restore = 182,
+ LFD = 183,
+ LFDU = 184,
+ LFDX = 185,
+ LFS = 186,
+ LFSU = 187,
+ LFSX = 188,
+ LHA = 189,
+ LHA8 = 190,
+ LHAU = 191,
+ LHAU8 = 192,
+ LHAX = 193,
+ LHAX8 = 194,
+ LHBRX = 195,
+ LHZ = 196,
+ LHZ8 = 197,
+ LHZU = 198,
+ LHZU8 = 199,
+ LHZX = 200,
+ LHZX8 = 201,
+ LI = 202,
+ LI8 = 203,
+ LIS = 204,
+ LIS8 = 205,
+ LVEBX = 206,
+ LVEHX = 207,
+ LVEWX = 208,
+ LVSL = 209,
+ LVSR = 210,
+ LVX = 211,
+ LVXL = 212,
+ LWA = 213,
+ LWARX = 214,
+ LWAX = 215,
+ LWBRX = 216,
+ LWZ = 217,
+ LWZ8 = 218,
+ LWZU = 219,
+ LWZU8 = 220,
+ LWZX = 221,
+ LWZX8 = 222,
+ MCRF = 223,
+ MFCR = 224,
+ MFCTR = 225,
+ MFCTR8 = 226,
+ MFFS = 227,
+ MFLR = 228,
+ MFLR8 = 229,
+ MFOCRF = 230,
+ MFVRSAVE = 231,
+ MFVSCR = 232,
+ MTCRF = 233,
+ MTCTR = 234,
+ MTCTR8 = 235,
+ MTFSB0 = 236,
+ MTFSB1 = 237,
+ MTFSF = 238,
+ MTLR = 239,
+ MTLR8 = 240,
+ MTVRSAVE = 241,
+ MTVSCR = 242,
+ MULHD = 243,
+ MULHDU = 244,
+ MULHW = 245,
+ MULHWU = 246,
+ MULLD = 247,
+ MULLI = 248,
+ MULLW = 249,
+ MovePCtoLR = 250,
+ MovePCtoLR8 = 251,
+ NAND = 252,
+ NAND8 = 253,
+ NEG = 254,
+ NEG8 = 255,
+ NOP = 256,
+ NOR = 257,
+ NOR8 = 258,
+ OR = 259,
+ OR4To8 = 260,
+ OR8 = 261,
+ OR8To4 = 262,
+ ORC = 263,
+ ORC8 = 264,
+ ORI = 265,
+ ORI8 = 266,
+ ORIS = 267,
+ ORIS8 = 268,
+ RLDCL = 269,
+ RLDICL = 270,
+ RLDICR = 271,
+ RLDIMI = 272,
+ RLWIMI = 273,
+ RLWINM = 274,
+ RLWINMo = 275,
+ RLWNM = 276,
+ SELECT_CC_F4 = 277,
+ SELECT_CC_F8 = 278,
+ SELECT_CC_I4 = 279,
+ SELECT_CC_I8 = 280,
+ SELECT_CC_VRRC = 281,
+ SLD = 282,
+ SLW = 283,
+ SPILL_CR = 284,
+ SRAD = 285,
+ SRADI = 286,
+ SRAW = 287,
+ SRAWI = 288,
+ SRD = 289,
+ SRW = 290,
+ STB = 291,
+ STB8 = 292,
+ STBU = 293,
+ STBU8 = 294,
+ STBX = 295,
+ STBX8 = 296,
+ STD = 297,
+ STDCX = 298,
+ STDU = 299,
+ STDUX = 300,
+ STDX = 301,
+ STDX_32 = 302,
+ STD_32 = 303,
+ STFD = 304,
+ STFDU = 305,
+ STFDX = 306,
+ STFIWX = 307,
+ STFS = 308,
+ STFSU = 309,
+ STFSX = 310,
+ STH = 311,
+ STH8 = 312,
+ STHBRX = 313,
+ STHU = 314,
+ STHU8 = 315,
+ STHX = 316,
+ STHX8 = 317,
+ STVEBX = 318,
+ STVEHX = 319,
+ STVEWX = 320,
+ STVX = 321,
+ STVXL = 322,
+ STW = 323,
+ STW8 = 324,
+ STWBRX = 325,
+ STWCX = 326,
+ STWU = 327,
+ STWU8 = 328,
+ STWUX = 329,
+ STWX = 330,
+ STWX8 = 331,
+ SUBF = 332,
+ SUBF8 = 333,
+ SUBFC = 334,
+ SUBFC8 = 335,
+ SUBFE = 336,
+ SUBFE8 = 337,
+ SUBFIC = 338,
+ SUBFIC8 = 339,
+ SUBFME = 340,
+ SUBFME8 = 341,
+ SUBFZE = 342,
+ SUBFZE8 = 343,
+ SYNC = 344,
+ TAILB = 345,
+ TAILB8 = 346,
+ TAILBA = 347,
+ TAILBA8 = 348,
+ TAILBCTR = 349,
+ TAILBCTR8 = 350,
+ TCRETURNai = 351,
+ TCRETURNai8 = 352,
+ TCRETURNdi = 353,
+ TCRETURNdi8 = 354,
+ TCRETURNri = 355,
+ TCRETURNri8 = 356,
+ TRAP = 357,
+ UPDATE_VRSAVE = 358,
+ VADDCUW = 359,
+ VADDFP = 360,
+ VADDSBS = 361,
+ VADDSHS = 362,
+ VADDSWS = 363,
+ VADDUBM = 364,
+ VADDUBS = 365,
+ VADDUHM = 366,
+ VADDUHS = 367,
+ VADDUWM = 368,
+ VADDUWS = 369,
+ VAND = 370,
+ VANDC = 371,
+ VAVGSB = 372,
+ VAVGSH = 373,
+ VAVGSW = 374,
+ VAVGUB = 375,
+ VAVGUH = 376,
+ VAVGUW = 377,
+ VCFSX = 378,
+ VCFUX = 379,
+ VCMPBFP = 380,
+ VCMPBFPo = 381,
+ VCMPEQFP = 382,
+ VCMPEQFPo = 383,
+ VCMPEQUB = 384,
+ VCMPEQUBo = 385,
+ VCMPEQUH = 386,
+ VCMPEQUHo = 387,
+ VCMPEQUW = 388,
+ VCMPEQUWo = 389,
+ VCMPGEFP = 390,
+ VCMPGEFPo = 391,
+ VCMPGTFP = 392,
+ VCMPGTFPo = 393,
+ VCMPGTSB = 394,
+ VCMPGTSBo = 395,
+ VCMPGTSH = 396,
+ VCMPGTSHo = 397,
+ VCMPGTSW = 398,
+ VCMPGTSWo = 399,
+ VCMPGTUB = 400,
+ VCMPGTUBo = 401,
+ VCMPGTUH = 402,
+ VCMPGTUHo = 403,
+ VCMPGTUW = 404,
+ VCMPGTUWo = 405,
+ VCTSXS = 406,
+ VCTUXS = 407,
+ VEXPTEFP = 408,
+ VLOGEFP = 409,
+ VMADDFP = 410,
+ VMAXFP = 411,
+ VMAXSB = 412,
+ VMAXSH = 413,
+ VMAXSW = 414,
+ VMAXUB = 415,
+ VMAXUH = 416,
+ VMAXUW = 417,
+ VMHADDSHS = 418,
+ VMHRADDSHS = 419,
+ VMINFP = 420,
+ VMINSB = 421,
+ VMINSH = 422,
+ VMINSW = 423,
+ VMINUB = 424,
+ VMINUH = 425,
+ VMINUW = 426,
+ VMLADDUHM = 427,
+ VMRGHB = 428,
+ VMRGHH = 429,
+ VMRGHW = 430,
+ VMRGLB = 431,
+ VMRGLH = 432,
+ VMRGLW = 433,
+ VMSUMMBM = 434,
+ VMSUMSHM = 435,
+ VMSUMSHS = 436,
+ VMSUMUBM = 437,
+ VMSUMUHM = 438,
+ VMSUMUHS = 439,
+ VMULESB = 440,
+ VMULESH = 441,
+ VMULEUB = 442,
+ VMULEUH = 443,
+ VMULOSB = 444,
+ VMULOSH = 445,
+ VMULOUB = 446,
+ VMULOUH = 447,
+ VNMSUBFP = 448,
+ VNOR = 449,
+ VOR = 450,
+ VPERM = 451,
+ VPKPX = 452,
+ VPKSHSS = 453,
+ VPKSHUS = 454,
+ VPKSWSS = 455,
+ VPKSWUS = 456,
+ VPKUHUM = 457,
+ VPKUHUS = 458,
+ VPKUWUM = 459,
+ VPKUWUS = 460,
+ VREFP = 461,
+ VRFIM = 462,
+ VRFIN = 463,
+ VRFIP = 464,
+ VRFIZ = 465,
+ VRLB = 466,
+ VRLH = 467,
+ VRLW = 468,
+ VRSQRTEFP = 469,
+ VSEL = 470,
+ VSL = 471,
+ VSLB = 472,
+ VSLDOI = 473,
+ VSLH = 474,
+ VSLO = 475,
+ VSLW = 476,
+ VSPLTB = 477,
+ VSPLTH = 478,
+ VSPLTISB = 479,
+ VSPLTISH = 480,
+ VSPLTISW = 481,
+ VSPLTW = 482,
+ VSR = 483,
+ VSRAB = 484,
+ VSRAH = 485,
+ VSRAW = 486,
+ VSRB = 487,
+ VSRH = 488,
+ VSRO = 489,
+ VSRW = 490,
+ VSUBCUW = 491,
+ VSUBFP = 492,
+ VSUBSBS = 493,
+ VSUBSHS = 494,
+ VSUBSWS = 495,
+ VSUBUBM = 496,
+ VSUBUBS = 497,
+ VSUBUHM = 498,
+ VSUBUHS = 499,
+ VSUBUWM = 500,
+ VSUBUWS = 501,
+ VSUM2SWS = 502,
+ VSUM4SBS = 503,
+ VSUM4SHS = 504,
+ VSUM4UBS = 505,
+ VSUMSWS = 506,
+ VUPKHPX = 507,
+ VUPKHSB = 508,
+ VUPKHSH = 509,
+ VUPKLPX = 510,
+ VUPKLSB = 511,
+ VUPKLSH = 512,
+ VXOR = 513,
+ V_SET0 = 514,
+ XOR = 515,
+ XOR8 = 516,
+ XORI = 517,
+ XORI8 = 518,
+ XORIS = 519,
+ XORIS8 = 520,
+ INSTRUCTION_LIST_END = 521
};
}
} // End llvm namespace
diff --git a/libclamav/c++/PPCGenSubtarget.inc b/libclamav/c++/PPCGenSubtarget.inc
index 74f8ea3..a0be949 100644
--- a/libclamav/c++/PPCGenSubtarget.inc
+++ b/libclamav/c++/PPCGenSubtarget.inc
@@ -519,8 +519,8 @@ enum {
// subtarget options.
std::string llvm::PPCSubtarget::ParseSubtargetFeatures(const std::string &FS,
const std::string &CPU) {
- DEBUG(errs() << "\nFeatures:" << FS);
- DEBUG(errs() << "\nCPU:" << CPU);
+ DEBUG(dbgs() << "\nFeatures:" << FS);
+ DEBUG(dbgs() << "\nCPU:" << CPU);
SubtargetFeatures Features(FS);
Features.setCPUIfNone(CPU);
uint32_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize,
diff --git a/libclamav/c++/X86GenAsmMatcher.inc b/libclamav/c++/X86GenAsmMatcher.inc
index 12be603..da18185 100644
--- a/libclamav/c++/X86GenAsmMatcher.inc
+++ b/libclamav/c++/X86GenAsmMatcher.inc
@@ -6,7 +6,7 @@
//
//===----------------------------------------------------------------------===//
-unsigned X86ATTAsmParser::MatchRegisterName(const StringRef &Name) {
+static unsigned MatchRegisterName(const StringRef &Name) {
switch (Name.size()) {
default: break;
case 2: // 25 strings to match.
@@ -598,11 +598,12 @@ unsigned X86ATTAsmParser::MatchRegisterName(const StringRef &Name) {
return 0;
}
+#ifndef REGISTERS_ONLY
+
// Unified function for converting operants to MCInst instances.
enum ConversionKind {
Convert,
- ConvertImp,
Convert_Reg1_1Imp,
Convert_Imm1_1,
Convert_Mem5_1,
@@ -651,115 +652,112 @@ enum ConversionKind {
};
static bool ConvertToMCInst(ConversionKind Kind, MCInst &Inst, unsigned Opcode,
- SmallVectorImpl<X86Operand> &Operands) {
+ const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
Inst.setOpcode(Opcode);
switch (Kind) {
default:
case Convert:
break;
- case ConvertImp:
- Inst.addOperand(MCOperand::CreateReg(0));
- break;
case Convert_Reg1_1Imp:
- Operands[1].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addRegOperands(Inst, 1);
Inst.addOperand(MCOperand::CreateReg(0));
break;
case Convert_Imm1_1:
- Operands[1].addImmOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
case Convert_Mem5_1:
- Operands[1].addMemOperands(Inst, 5);
+ ((X86Operand*)Operands[1])->addMemOperands(Inst, 5);
break;
case Convert_Reg1_1:
- Operands[1].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addRegOperands(Inst, 1);
break;
case Convert_Reg1_2_ImpReg1_1:
- Operands[2].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
Inst.addOperand(MCOperand::CreateReg(0));
- Operands[1].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addRegOperands(Inst, 1);
break;
case Convert_Mem5_2_Reg1_1:
- Operands[2].addMemOperands(Inst, 5);
- Operands[1].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
+ ((X86Operand*)Operands[1])->addRegOperands(Inst, 1);
break;
case Convert_Reg1_2_ImpImm1_1:
- Operands[2].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
Inst.addOperand(MCOperand::CreateReg(0));
- Operands[1].addImmOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
case Convert_Mem5_2_Imm1_1:
- Operands[2].addMemOperands(Inst, 5);
- Operands[1].addImmOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
+ ((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
case Convert_Reg1_2_ImpMem5_1:
- Operands[2].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
Inst.addOperand(MCOperand::CreateReg(0));
- Operands[1].addMemOperands(Inst, 5);
+ ((X86Operand*)Operands[1])->addMemOperands(Inst, 5);
break;
case Convert_Reg1_2_ImpImmSExt81_1:
- Operands[2].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
Inst.addOperand(MCOperand::CreateReg(0));
- Operands[1].addImmSExt8Operands(Inst, 1);
+ ((X86Operand*)Operands[1])->addImmSExt8Operands(Inst, 1);
break;
case Convert_Mem5_2_ImmSExt81_1:
- Operands[2].addMemOperands(Inst, 5);
- Operands[1].addImmSExt8Operands(Inst, 1);
+ ((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
+ ((X86Operand*)Operands[1])->addImmSExt8Operands(Inst, 1);
break;
case Convert_Reg1_2_Reg1_1:
- Operands[2].addRegOperands(Inst, 1);
- Operands[1].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addRegOperands(Inst, 1);
break;
case Convert_Reg1_2_Mem5_1:
- Operands[2].addRegOperands(Inst, 1);
- Operands[1].addMemOperands(Inst, 5);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addMemOperands(Inst, 5);
break;
case Convert_Reg1_2_ImmSExt81_1:
- Operands[2].addRegOperands(Inst, 1);
- Operands[1].addImmSExt8Operands(Inst, 1);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addImmSExt8Operands(Inst, 1);
break;
case Convert_Reg1_2:
- Operands[2].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
break;
case Convert_Mem5_2:
- Operands[2].addMemOperands(Inst, 5);
+ ((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
break;
case Convert_Reg1_2_Imm1_1:
- Operands[2].addRegOperands(Inst, 1);
- Operands[1].addImmOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
case Convert_ImpReg1_2_Reg1_1:
Inst.addOperand(MCOperand::CreateReg(0));
- Operands[2].addRegOperands(Inst, 1);
- Operands[1].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addRegOperands(Inst, 1);
break;
case Convert_ImpReg1_2_Mem5_1:
Inst.addOperand(MCOperand::CreateReg(0));
- Operands[2].addRegOperands(Inst, 1);
- Operands[1].addMemOperands(Inst, 5);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addMemOperands(Inst, 5);
break;
case Convert_Imm1_1_Imm1_2:
- Operands[1].addImmOperands(Inst, 1);
- Operands[2].addImmOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addImmOperands(Inst, 1);
break;
case Convert_ImmSExt81_1:
- Operands[1].addImmSExt8Operands(Inst, 1);
+ ((X86Operand*)Operands[1])->addImmSExt8Operands(Inst, 1);
break;
case Convert_Reg1_2_Mem4_1:
- Operands[2].addRegOperands(Inst, 1);
- Operands[1].addMemOperands(Inst, 4);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addMemOperands(Inst, 4);
break;
case Convert_Imm1_2:
- Operands[2].addImmOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addImmOperands(Inst, 1);
break;
case Convert_ImmSExt81_2:
- Operands[2].addImmSExt8Operands(Inst, 1);
+ ((X86Operand*)Operands[2])->addImmSExt8Operands(Inst, 1);
break;
case Convert_Reg1_2Imp:
- Operands[2].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
Inst.addOperand(MCOperand::CreateReg(0));
break;
case Convert_Mem5_2ImpImpImpImpImp:
- Operands[2].addMemOperands(Inst, 5);
+ ((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::CreateReg(0));
@@ -767,103 +765,103 @@ static bool ConvertToMCInst(ConversionKind Kind, MCInst &Inst, unsigned Opcode,
Inst.addOperand(MCOperand::CreateReg(0));
break;
case Convert_Mem5_2_ImpImpImpImpImpImm1_1:
- Operands[2].addMemOperands(Inst, 5);
+ ((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::CreateReg(0));
- Operands[1].addImmOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
case Convert_ImpReg1_1_Reg1_2:
Inst.addOperand(MCOperand::CreateReg(0));
- Operands[1].addRegOperands(Inst, 1);
- Operands[2].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
break;
case Convert_ImpReg1_1_Mem5_2:
Inst.addOperand(MCOperand::CreateReg(0));
- Operands[1].addRegOperands(Inst, 1);
- Operands[2].addMemOperands(Inst, 5);
+ ((X86Operand*)Operands[1])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
break;
case Convert_Reg1_3_ImpReg1_2_ImmSExt81_1:
- Operands[3].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
Inst.addOperand(MCOperand::CreateReg(0));
- Operands[2].addRegOperands(Inst, 1);
- Operands[1].addImmSExt8Operands(Inst, 1);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addImmSExt8Operands(Inst, 1);
break;
case Convert_Reg1_3_ImpMem5_2_ImmSExt81_1:
- Operands[3].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
Inst.addOperand(MCOperand::CreateReg(0));
- Operands[2].addMemOperands(Inst, 5);
- Operands[1].addImmSExt8Operands(Inst, 1);
+ ((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
+ ((X86Operand*)Operands[1])->addImmSExt8Operands(Inst, 1);
break;
case Convert_Reg1_3_ImpReg1_2:
- Operands[3].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
Inst.addOperand(MCOperand::CreateReg(0));
- Operands[2].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
break;
case Convert_Reg1_3_ImpMem5_2:
- Operands[3].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
Inst.addOperand(MCOperand::CreateReg(0));
- Operands[2].addMemOperands(Inst, 5);
+ ((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
break;
case Convert_Reg1_3_Reg1_2_ImmSExt81_1:
- Operands[3].addRegOperands(Inst, 1);
- Operands[2].addRegOperands(Inst, 1);
- Operands[1].addImmSExt8Operands(Inst, 1);
+ ((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addImmSExt8Operands(Inst, 1);
break;
case Convert_Mem5_3_Reg1_2_ImmSExt81_1:
- Operands[3].addMemOperands(Inst, 5);
- Operands[2].addRegOperands(Inst, 1);
- Operands[1].addImmSExt8Operands(Inst, 1);
+ ((X86Operand*)Operands[3])->addMemOperands(Inst, 5);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addImmSExt8Operands(Inst, 1);
break;
case Convert_Reg1_3_Mem5_2_ImmSExt81_1:
- Operands[3].addRegOperands(Inst, 1);
- Operands[2].addMemOperands(Inst, 5);
- Operands[1].addImmSExt8Operands(Inst, 1);
+ ((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
+ ((X86Operand*)Operands[1])->addImmSExt8Operands(Inst, 1);
break;
case Convert_Reg1_3_Reg1_2_Imm1_1:
- Operands[3].addRegOperands(Inst, 1);
- Operands[2].addRegOperands(Inst, 1);
- Operands[1].addImmOperands(Inst, 1);
+ ((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
case Convert_Reg1_3_Mem5_2_Imm1_1:
- Operands[3].addRegOperands(Inst, 1);
- Operands[2].addMemOperands(Inst, 5);
- Operands[1].addImmOperands(Inst, 1);
+ ((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
+ ((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
case Convert_Reg1_3_ImpReg1_2_Imm1_1:
- Operands[3].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
Inst.addOperand(MCOperand::CreateReg(0));
- Operands[2].addRegOperands(Inst, 1);
- Operands[1].addImmOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
case Convert_Reg1_3_ImpMem5_2_Imm1_1:
- Operands[3].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
Inst.addOperand(MCOperand::CreateReg(0));
- Operands[2].addMemOperands(Inst, 5);
- Operands[1].addImmOperands(Inst, 1);
+ ((X86Operand*)Operands[2])->addMemOperands(Inst, 5);
+ ((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
case Convert_Mem5_3_Reg1_2:
- Operands[3].addMemOperands(Inst, 5);
- Operands[2].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[3])->addMemOperands(Inst, 5);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
break;
case Convert_Mem5_3_Reg1_2_Imm1_1:
- Operands[3].addMemOperands(Inst, 5);
- Operands[2].addRegOperands(Inst, 1);
- Operands[1].addImmOperands(Inst, 1);
+ ((X86Operand*)Operands[3])->addMemOperands(Inst, 5);
+ ((X86Operand*)Operands[2])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
case Convert_Reg1_4_ImpReg1_3_Imm1_1:
- Operands[4].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[4])->addRegOperands(Inst, 1);
Inst.addOperand(MCOperand::CreateReg(0));
- Operands[3].addRegOperands(Inst, 1);
- Operands[1].addImmOperands(Inst, 1);
+ ((X86Operand*)Operands[3])->addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
case Convert_Reg1_4_ImpMem5_3_Imm1_1:
- Operands[4].addRegOperands(Inst, 1);
+ ((X86Operand*)Operands[4])->addRegOperands(Inst, 1);
Inst.addOperand(MCOperand::CreateReg(0));
- Operands[3].addMemOperands(Inst, 5);
- Operands[1].addImmOperands(Inst, 1);
+ ((X86Operand*)Operands[3])->addMemOperands(Inst, 5);
+ ((X86Operand*)Operands[1])->addImmOperands(Inst, 1);
break;
}
return false;
@@ -5894,7 +5892,8 @@ static MatchClassKind MatchTokenString(const StringRef &Name) {
return InvalidMatchClass;
}
-static MatchClassKind ClassifyOperand(X86Operand &Operand) {
+static MatchClassKind ClassifyOperand(MCParsedAsmOperand *GOp) {
+ X86Operand &Operand = *(X86Operand*)GOp;
if (Operand.isToken())
return MatchTokenString(Operand.getToken());
@@ -6241,12 +6240,14 @@ static bool IsSubclass(MatchClassKind A, MatchClassKind B) {
}
}
-bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MCInst &Inst) {
+bool X86ATTAsmParser::
+MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
+ MCInst &Inst) {
static const struct MatchEntry {
unsigned Opcode;
ConversionKind ConvertFn;
MatchClassKind Classes[5];
- } MatchTable[2041] = {
+ } MatchTable[2040] = {
{ X86::CBW, Convert, { MCK_cbtw } },
{ X86::CLC, Convert, { MCK_clc } },
{ X86::CLD, Convert, { MCK_cld } },
@@ -6309,8 +6310,8 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::IRET64, Convert, { MCK_iretq } },
{ X86::IRET16, Convert, { MCK_iretw } },
{ X86::LAHF, Convert, { MCK_lahf } },
- { X86::LEAVE, Convert, { MCK_leave } },
{ X86::LEAVE64, Convert, { MCK_leave } },
+ { X86::LEAVE, Convert, { MCK_leave } },
{ X86::LFENCE, Convert, { MCK_lfence } },
{ X86::LODSB, Convert, { MCK_lodsb } },
{ X86::LODSD, Convert, { MCK_lodsl } },
@@ -6341,7 +6342,6 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::REP_STOSD, Convert, { MCK_rep_59_stosl } },
{ X86::REP_STOSQ, Convert, { MCK_rep_59_stosq } },
{ X86::REP_STOSW, Convert, { MCK_rep_59_stosw } },
- { X86::EH_RETURN64, ConvertImp, { MCK_ret } },
{ X86::RET, Convert, { MCK_ret } },
{ X86::RSM, Convert, { MCK_rsm } },
{ X86::SAHF, Convert, { MCK_sahf } },
@@ -6356,8 +6356,8 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::SWPGS, Convert, { MCK_swpgs } },
{ X86::SYSCALL, Convert, { MCK_syscall } },
{ X86::SYSENTER, Convert, { MCK_sysenter } },
- { X86::SYSEXIT64, Convert, { MCK_sysexit } },
{ X86::SYSEXIT, Convert, { MCK_sysexit } },
+ { X86::SYSEXIT64, Convert, { MCK_sysexit } },
{ X86::SYSRET, Convert, { MCK_sysret } },
{ X86::TRAP, Convert, { MCK_ud2 } },
{ X86::VMCALL, Convert, { MCK_vmcall } },
@@ -6370,22 +6370,22 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::XLAT, Convert, { MCK_xlatb } },
{ X86::BSWAP32r, Convert_Reg1_1Imp, { MCK_bswapl, MCK_GR32 } },
{ X86::BSWAP64r, Convert_Reg1_1Imp, { MCK_bswapq, MCK_GR64 } },
- { X86::CALLpcrel32, Convert_Imm1_1, { MCK_call, MCK_Imm } },
{ X86::WINCALL64pcrel32, Convert_Imm1_1, { MCK_call, MCK_Imm } },
+ { X86::CALLpcrel32, Convert_Imm1_1, { MCK_call, MCK_Imm } },
{ X86::CALL64pcrel32, Convert_Imm1_1, { MCK_callq, MCK_Imm } },
{ X86::CLFLUSH, Convert_Mem5_1, { MCK_clflush, MCK_Mem } },
{ X86::CMPXCHG16B, Convert_Mem5_1, { MCK_cmpxchg16b, MCK_Mem } },
{ X86::CMPXCHG8B, Convert_Mem5_1, { MCK_cmpxchg8b, MCK_Mem } },
{ X86::DEC8r, Convert_Reg1_1Imp, { MCK_decb, MCK_GR8 } },
{ X86::DEC8m, Convert_Mem5_1, { MCK_decb, MCK_Mem } },
- { X86::DEC32r, Convert_Reg1_1Imp, { MCK_decl, MCK_GR32 } },
{ X86::DEC64_32r, Convert_Reg1_1Imp, { MCK_decl, MCK_GR32 } },
- { X86::DEC32m, Convert_Mem5_1, { MCK_decl, MCK_Mem } },
+ { X86::DEC32r, Convert_Reg1_1Imp, { MCK_decl, MCK_GR32 } },
{ X86::DEC64_32m, Convert_Mem5_1, { MCK_decl, MCK_Mem } },
+ { X86::DEC32m, Convert_Mem5_1, { MCK_decl, MCK_Mem } },
{ X86::DEC64r, Convert_Reg1_1Imp, { MCK_decq, MCK_GR64 } },
{ X86::DEC64m, Convert_Mem5_1, { MCK_decq, MCK_Mem } },
- { X86::DEC16r, Convert_Reg1_1Imp, { MCK_decw, MCK_GR16 } },
{ X86::DEC64_16r, Convert_Reg1_1Imp, { MCK_decw, MCK_GR16 } },
+ { X86::DEC16r, Convert_Reg1_1Imp, { MCK_decw, MCK_GR16 } },
{ X86::DEC64_16m, Convert_Mem5_1, { MCK_decw, MCK_Mem } },
{ X86::DEC16m, Convert_Mem5_1, { MCK_decw, MCK_Mem } },
{ X86::DIV8r, Convert_Reg1_1, { MCK_divb, MCK_GR8 } },
@@ -6437,8 +6437,8 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::IST_FP64m, Convert_Mem5_1, { MCK_fistpll, MCK_Mem } },
{ X86::IST_FP16m, Convert_Mem5_1, { MCK_fistps, MCK_Mem } },
{ X86::IST_F16m, Convert_Mem5_1, { MCK_fists, MCK_Mem } },
- { X86::FISTTP32m, Convert_Mem5_1, { MCK_fisttpl, MCK_Mem } },
{ X86::ISTT_FP32m, Convert_Mem5_1, { MCK_fisttpl, MCK_Mem } },
+ { X86::FISTTP32m, Convert_Mem5_1, { MCK_fisttpl, MCK_Mem } },
{ X86::ISTT_FP64m, Convert_Mem5_1, { MCK_fisttpll, MCK_Mem } },
{ X86::ISTT_FP16m, Convert_Mem5_1, { MCK_fisttps, MCK_Mem } },
{ X86::SUB_FI32m, Convert_Mem5_1, { MCK_fisubl, MCK_Mem } },
@@ -6499,37 +6499,37 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::IMUL16m, Convert_Mem5_1, { MCK_imulw, MCK_Mem } },
{ X86::INC8r, Convert_Reg1_1Imp, { MCK_incb, MCK_GR8 } },
{ X86::INC8m, Convert_Mem5_1, { MCK_incb, MCK_Mem } },
- { X86::INC64_32r, Convert_Reg1_1Imp, { MCK_incl, MCK_GR32 } },
{ X86::INC32r, Convert_Reg1_1Imp, { MCK_incl, MCK_GR32 } },
- { X86::INC64_32m, Convert_Mem5_1, { MCK_incl, MCK_Mem } },
+ { X86::INC64_32r, Convert_Reg1_1Imp, { MCK_incl, MCK_GR32 } },
{ X86::INC32m, Convert_Mem5_1, { MCK_incl, MCK_Mem } },
+ { X86::INC64_32m, Convert_Mem5_1, { MCK_incl, MCK_Mem } },
{ X86::INC64r, Convert_Reg1_1Imp, { MCK_incq, MCK_GR64 } },
{ X86::INC64m, Convert_Mem5_1, { MCK_incq, MCK_Mem } },
- { X86::INC64_16r, Convert_Reg1_1Imp, { MCK_incw, MCK_GR16 } },
{ X86::INC16r, Convert_Reg1_1Imp, { MCK_incw, MCK_GR16 } },
- { X86::INC64_16m, Convert_Mem5_1, { MCK_incw, MCK_Mem } },
+ { X86::INC64_16r, Convert_Reg1_1Imp, { MCK_incw, MCK_GR16 } },
{ X86::INC16m, Convert_Mem5_1, { MCK_incw, MCK_Mem } },
+ { X86::INC64_16m, Convert_Mem5_1, { MCK_incw, MCK_Mem } },
{ X86::INT3, Convert, { MCK_int, MCK_3 } },
{ X86::INT, Convert_Imm1_1, { MCK_int, MCK_Imm } },
- { X86::JA, Convert_Imm1_1, { MCK_ja, MCK_Imm } },
{ X86::JA8, Convert_Imm1_1, { MCK_ja, MCK_Imm } },
+ { X86::JA, Convert_Imm1_1, { MCK_ja, MCK_Imm } },
{ X86::JAE, Convert_Imm1_1, { MCK_jae, MCK_Imm } },
{ X86::JAE8, Convert_Imm1_1, { MCK_jae, MCK_Imm } },
{ X86::JB, Convert_Imm1_1, { MCK_jb, MCK_Imm } },
{ X86::JB8, Convert_Imm1_1, { MCK_jb, MCK_Imm } },
- { X86::JBE8, Convert_Imm1_1, { MCK_jbe, MCK_Imm } },
{ X86::JBE, Convert_Imm1_1, { MCK_jbe, MCK_Imm } },
+ { X86::JBE8, Convert_Imm1_1, { MCK_jbe, MCK_Imm } },
{ X86::JCXZ8, Convert_Imm1_1, { MCK_jcxz, MCK_Imm } },
{ X86::JE, Convert_Imm1_1, { MCK_je, MCK_Imm } },
{ X86::JE8, Convert_Imm1_1, { MCK_je, MCK_Imm } },
{ X86::JG, Convert_Imm1_1, { MCK_jg, MCK_Imm } },
{ X86::JG8, Convert_Imm1_1, { MCK_jg, MCK_Imm } },
- { X86::JGE8, Convert_Imm1_1, { MCK_jge, MCK_Imm } },
{ X86::JGE, Convert_Imm1_1, { MCK_jge, MCK_Imm } },
+ { X86::JGE8, Convert_Imm1_1, { MCK_jge, MCK_Imm } },
{ X86::JL8, Convert_Imm1_1, { MCK_jl, MCK_Imm } },
{ X86::JL, Convert_Imm1_1, { MCK_jl, MCK_Imm } },
- { X86::JLE8, Convert_Imm1_1, { MCK_jle, MCK_Imm } },
{ X86::JLE, Convert_Imm1_1, { MCK_jle, MCK_Imm } },
+ { X86::JLE8, Convert_Imm1_1, { MCK_jle, MCK_Imm } },
{ X86::JMP, Convert_Imm1_1, { MCK_jmp, MCK_Imm } },
{ X86::JMP8, Convert_Imm1_1, { MCK_jmp, MCK_Imm } },
{ X86::TAILJMPd, Convert_Imm1_1, { MCK_jmp, MCK_Imm } },
@@ -6538,14 +6538,14 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::JNE8, Convert_Imm1_1, { MCK_jne, MCK_Imm } },
{ X86::JNO, Convert_Imm1_1, { MCK_jno, MCK_Imm } },
{ X86::JNO8, Convert_Imm1_1, { MCK_jno, MCK_Imm } },
- { X86::JNP8, Convert_Imm1_1, { MCK_jnp, MCK_Imm } },
{ X86::JNP, Convert_Imm1_1, { MCK_jnp, MCK_Imm } },
- { X86::JNS8, Convert_Imm1_1, { MCK_jns, MCK_Imm } },
+ { X86::JNP8, Convert_Imm1_1, { MCK_jnp, MCK_Imm } },
{ X86::JNS, Convert_Imm1_1, { MCK_jns, MCK_Imm } },
- { X86::JO8, Convert_Imm1_1, { MCK_jo, MCK_Imm } },
+ { X86::JNS8, Convert_Imm1_1, { MCK_jns, MCK_Imm } },
{ X86::JO, Convert_Imm1_1, { MCK_jo, MCK_Imm } },
- { X86::JP, Convert_Imm1_1, { MCK_jp, MCK_Imm } },
+ { X86::JO8, Convert_Imm1_1, { MCK_jo, MCK_Imm } },
{ X86::JP8, Convert_Imm1_1, { MCK_jp, MCK_Imm } },
+ { X86::JP, Convert_Imm1_1, { MCK_jp, MCK_Imm } },
{ X86::JS8, Convert_Imm1_1, { MCK_js, MCK_Imm } },
{ X86::JS, Convert_Imm1_1, { MCK_js, MCK_Imm } },
{ X86::LDMXCSR, Convert_Mem5_1, { MCK_ldmxcsr, MCK_Mem } },
@@ -6587,8 +6587,8 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::NOT64m, Convert_Mem5_1, { MCK_notq, MCK_Mem } },
{ X86::NOT16r, Convert_Reg1_1Imp, { MCK_notw, MCK_GR16 } },
{ X86::NOT16m, Convert_Mem5_1, { MCK_notw, MCK_Mem } },
- { X86::POP32r, Convert_Reg1_1, { MCK_popl, MCK_GR32 } },
{ X86::POP32rmr, Convert_Reg1_1, { MCK_popl, MCK_GR32 } },
+ { X86::POP32r, Convert_Reg1_1, { MCK_popl, MCK_GR32 } },
{ X86::POPFS32, Convert, { MCK_popl, MCK_FS } },
{ X86::POPGS32, Convert, { MCK_popl, MCK_GS } },
{ X86::POP32rmm, Convert_Mem5_1, { MCK_popl, MCK_Mem } },
@@ -6611,11 +6611,11 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::PUSHFS32, Convert, { MCK_pushl, MCK_FS } },
{ X86::PUSHGS32, Convert, { MCK_pushl, MCK_GS } },
{ X86::PUSH32i32, Convert_Imm1_1, { MCK_pushl, MCK_Imm } },
- { X86::PUSH32i8, Convert_Imm1_1, { MCK_pushl, MCK_Imm } },
{ X86::PUSH32i16, Convert_Imm1_1, { MCK_pushl, MCK_Imm } },
+ { X86::PUSH32i8, Convert_Imm1_1, { MCK_pushl, MCK_Imm } },
{ X86::PUSH32rmm, Convert_Mem5_1, { MCK_pushl, MCK_Mem } },
- { X86::PUSH64rmr, Convert_Reg1_1, { MCK_pushq, MCK_GR64 } },
{ X86::PUSH64r, Convert_Reg1_1, { MCK_pushq, MCK_GR64 } },
+ { X86::PUSH64rmr, Convert_Reg1_1, { MCK_pushq, MCK_GR64 } },
{ X86::PUSHFS64, Convert, { MCK_pushq, MCK_FS } },
{ X86::PUSHGS64, Convert, { MCK_pushq, MCK_GS } },
{ X86::PUSH64i8, Convert_Imm1_1, { MCK_pushq, MCK_Imm } },
@@ -6721,15 +6721,15 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::VMPTRLDm, Convert_Mem5_1, { MCK_vmptrld, MCK_Mem } },
{ X86::VMPTRSTm, Convert_Mem5_1, { MCK_vmptrst, MCK_Mem } },
{ X86::VMXON, Convert_Mem5_1, { MCK_vmxon, MCK_Mem } },
- { X86::ADC8rr, Convert_Reg1_2_ImpReg1_1, { MCK_adcb, MCK_GR8, MCK_GR8 } },
{ X86::ADC8rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_adcb, MCK_GR8, MCK_GR8 } },
+ { X86::ADC8rr, Convert_Reg1_2_ImpReg1_1, { MCK_adcb, MCK_GR8, MCK_GR8 } },
{ X86::ADC8mr, Convert_Mem5_2_Reg1_1, { MCK_adcb, MCK_GR8, MCK_Mem } },
{ X86::ADC8i8, Convert_Imm1_1, { MCK_adcb, MCK_Imm, MCK_AL } },
{ X86::ADC8ri, Convert_Reg1_2_ImpImm1_1, { MCK_adcb, MCK_Imm, MCK_GR8 } },
{ X86::ADC8mi, Convert_Mem5_2_Imm1_1, { MCK_adcb, MCK_Imm, MCK_Mem } },
{ X86::ADC8rm, Convert_Reg1_2_ImpMem5_1, { MCK_adcb, MCK_Mem, MCK_GR8 } },
- { X86::ADC32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_adcl, MCK_GR32, MCK_GR32 } },
{ X86::ADC32rr, Convert_Reg1_2_ImpReg1_1, { MCK_adcl, MCK_GR32, MCK_GR32 } },
+ { X86::ADC32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_adcl, MCK_GR32, MCK_GR32 } },
{ X86::ADC32mr, Convert_Mem5_2_Reg1_1, { MCK_adcl, MCK_GR32, MCK_Mem } },
{ X86::ADC32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_adcl, MCK_ImmSExt8, MCK_GR32 } },
{ X86::ADC32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_adcl, MCK_ImmSExt8, MCK_Mem } },
@@ -6792,8 +6792,8 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::ADDSUBPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_addsubpd, MCK_Mem, MCK_FR32 } },
{ X86::ADDSUBPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_addsubps, MCK_FR32, MCK_FR32 } },
{ X86::ADDSUBPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_addsubps, MCK_Mem, MCK_FR32 } },
- { X86::ADD16mrmrr, Convert_Reg1_2_ImpReg1_1, { MCK_addw, MCK_GR16, MCK_GR16 } },
{ X86::ADD16rr, Convert_Reg1_2_ImpReg1_1, { MCK_addw, MCK_GR16, MCK_GR16 } },
+ { X86::ADD16mrmrr, Convert_Reg1_2_ImpReg1_1, { MCK_addw, MCK_GR16, MCK_GR16 } },
{ X86::ADD16mr, Convert_Mem5_2_Reg1_1, { MCK_addw, MCK_GR16, MCK_Mem } },
{ X86::ADD16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_addw, MCK_ImmSExt8, MCK_GR16 } },
{ X86::ADD16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_addw, MCK_ImmSExt8, MCK_Mem } },
@@ -6808,8 +6808,8 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::AND8ri, Convert_Reg1_2_ImpImm1_1, { MCK_andb, MCK_Imm, MCK_GR8 } },
{ X86::AND8mi, Convert_Mem5_2_Imm1_1, { MCK_andb, MCK_Imm, MCK_Mem } },
{ X86::AND8rm, Convert_Reg1_2_ImpMem5_1, { MCK_andb, MCK_Mem, MCK_GR8 } },
- { X86::AND32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_andl, MCK_GR32, MCK_GR32 } },
{ X86::AND32rr, Convert_Reg1_2_ImpReg1_1, { MCK_andl, MCK_GR32, MCK_GR32 } },
+ { X86::AND32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_andl, MCK_GR32, MCK_GR32 } },
{ X86::AND32mr, Convert_Mem5_2_Reg1_1, { MCK_andl, MCK_GR32, MCK_Mem } },
{ X86::AND32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_andl, MCK_ImmSExt8, MCK_GR32 } },
{ X86::AND32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_andl, MCK_ImmSExt8, MCK_Mem } },
@@ -6819,16 +6819,16 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::AND32rm, Convert_Reg1_2_ImpMem5_1, { MCK_andl, MCK_Mem, MCK_GR32 } },
{ X86::FsANDNPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_andnpd, MCK_FR32, MCK_FR32 } },
{ X86::ANDNPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_andnpd, MCK_FR32, MCK_FR32 } },
- { X86::FsANDNPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_andnpd, MCK_Mem, MCK_FR32 } },
{ X86::ANDNPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_andnpd, MCK_Mem, MCK_FR32 } },
+ { X86::FsANDNPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_andnpd, MCK_Mem, MCK_FR32 } },
{ X86::ANDNPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_andnps, MCK_FR32, MCK_FR32 } },
{ X86::FsANDNPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_andnps, MCK_FR32, MCK_FR32 } },
- { X86::FsANDNPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_andnps, MCK_Mem, MCK_FR32 } },
{ X86::ANDNPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_andnps, MCK_Mem, MCK_FR32 } },
- { X86::FsANDPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_andpd, MCK_FR32, MCK_FR32 } },
+ { X86::FsANDNPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_andnps, MCK_Mem, MCK_FR32 } },
{ X86::ANDPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_andpd, MCK_FR32, MCK_FR32 } },
- { X86::FsANDPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_andpd, MCK_Mem, MCK_FR32 } },
+ { X86::FsANDPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_andpd, MCK_FR32, MCK_FR32 } },
{ X86::ANDPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_andpd, MCK_Mem, MCK_FR32 } },
+ { X86::FsANDPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_andpd, MCK_Mem, MCK_FR32 } },
{ X86::ANDPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_andps, MCK_FR32, MCK_FR32 } },
{ X86::FsANDPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_andps, MCK_FR32, MCK_FR32 } },
{ X86::ANDPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_andps, MCK_Mem, MCK_FR32 } },
@@ -7020,8 +7020,8 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::CMP8ri, Convert_Reg1_2_Imm1_1, { MCK_cmpb, MCK_Imm, MCK_GR8 } },
{ X86::CMP8mi, Convert_Mem5_2_Imm1_1, { MCK_cmpb, MCK_Imm, MCK_Mem } },
{ X86::CMP8rm, Convert_Reg1_2_Mem5_1, { MCK_cmpb, MCK_Mem, MCK_GR8 } },
- { X86::CMP32rr, Convert_Reg1_2_Reg1_1, { MCK_cmpl, MCK_GR32, MCK_GR32 } },
{ X86::CMP32mrmrr, Convert_Reg1_2_Reg1_1, { MCK_cmpl, MCK_GR32, MCK_GR32 } },
+ { X86::CMP32rr, Convert_Reg1_2_Reg1_1, { MCK_cmpl, MCK_GR32, MCK_GR32 } },
{ X86::CMP32mr, Convert_Mem5_2_Reg1_1, { MCK_cmpl, MCK_GR32, MCK_Mem } },
{ X86::CMP32ri8, Convert_Reg1_2_ImmSExt81_1, { MCK_cmpl, MCK_ImmSExt8, MCK_GR32 } },
{ X86::CMP32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_cmpl, MCK_ImmSExt8, MCK_Mem } },
@@ -7063,9 +7063,9 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::CRC32r16, Convert_ImpReg1_2_Reg1_1, { MCK_crc32, MCK_GR16, MCK_GR32 } },
{ X86::CRC32r32, Convert_ImpReg1_2_Reg1_1, { MCK_crc32, MCK_GR32, MCK_GR32 } },
{ X86::CRC64r64, Convert_ImpReg1_2_Reg1_1, { MCK_crc32, MCK_GR64, MCK_GR64 } },
- { X86::CRC32m16, Convert_ImpReg1_2_Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR32 } },
- { X86::CRC32m32, Convert_ImpReg1_2_Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR32 } },
{ X86::CRC32m8, Convert_ImpReg1_2_Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR32 } },
+ { X86::CRC32m32, Convert_ImpReg1_2_Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR32 } },
+ { X86::CRC32m16, Convert_ImpReg1_2_Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR32 } },
{ X86::CRC64m64, Convert_ImpReg1_2_Mem5_1, { MCK_crc32, MCK_Mem, MCK_GR64 } },
{ X86::CVTDQ2PDrr, Convert_Reg1_2_Reg1_1, { MCK_cvtdq2pd, MCK_FR32, MCK_FR32 } },
{ X86::CVTDQ2PDrm, Convert_Reg1_2_Mem5_1, { MCK_cvtdq2pd, MCK_Mem, MCK_FR32 } },
@@ -7170,8 +7170,8 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::JMP32r, Convert_Reg1_2, { MCK_jmpl, MCK__STAR_, MCK_GR32 } },
{ X86::TAILJMPr, Convert_Reg1_2, { MCK_jmpl, MCK__STAR_, MCK_GR32 } },
{ X86::JMP32m, Convert_Mem5_2, { MCK_jmpl, MCK__STAR_, MCK_Mem } },
- { X86::TAILJMPr64, Convert_Reg1_2, { MCK_jmpq, MCK__STAR_, MCK_GR64 } },
{ X86::JMP64r, Convert_Reg1_2, { MCK_jmpq, MCK__STAR_, MCK_GR64 } },
+ { X86::TAILJMPr64, Convert_Reg1_2, { MCK_jmpq, MCK__STAR_, MCK_GR64 } },
{ X86::JMP64m, Convert_Mem5_2, { MCK_jmpq, MCK__STAR_, MCK_Mem } },
{ X86::LAR32rr, Convert_Reg1_2_Reg1_1, { MCK_larl, MCK_GR32, MCK_GR32 } },
{ X86::LAR32rm, Convert_Reg1_2_Mem5_1, { MCK_larl, MCK_Mem, MCK_GR32 } },
@@ -7187,8 +7187,8 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::LDDQUrm, Convert_Reg1_2_Mem5_1, { MCK_lddqu, MCK_Mem, MCK_FR32 } },
{ X86::LDS32rm, Convert_Reg1_2_Mem5_1, { MCK_ldsl, MCK_Mem, MCK_GR32 } },
{ X86::LDS16rm, Convert_Reg1_2_Mem5_1, { MCK_ldsw, MCK_Mem, MCK_GR16 } },
- { X86::LEA64_32r, Convert_Reg1_2_Mem4_1, { MCK_leal, MCK_Mem, MCK_GR32 } },
{ X86::LEA32r, Convert_Reg1_2_Mem4_1, { MCK_leal, MCK_Mem, MCK_GR32 } },
+ { X86::LEA64_32r, Convert_Reg1_2_Mem4_1, { MCK_leal, MCK_Mem, MCK_GR32 } },
{ X86::LEA64r, Convert_Reg1_2_Mem4_1, { MCK_leaq, MCK_Mem, MCK_GR64 } },
{ X86::LEA16r, Convert_Reg1_2_Mem4_1, { MCK_leaw, MCK_Mem, MCK_GR16 } },
{ X86::LES32rm, Convert_Reg1_2_Mem5_1, { MCK_lesl, MCK_Mem, MCK_GR32 } },
@@ -7213,8 +7213,8 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::LSS32rm, Convert_Reg1_2_Mem5_1, { MCK_lssl, MCK_Mem, MCK_GR32 } },
{ X86::LSS64rm, Convert_Reg1_2_Mem5_1, { MCK_lssq, MCK_Mem, MCK_GR64 } },
{ X86::LSS16rm, Convert_Reg1_2_Mem5_1, { MCK_lssw, MCK_Mem, MCK_GR16 } },
- { X86::MASKMOVDQU64, Convert_Reg1_2_Reg1_1, { MCK_maskmovdqu, MCK_FR32, MCK_FR32 } },
{ X86::MASKMOVDQU, Convert_Reg1_2_Reg1_1, { MCK_maskmovdqu, MCK_FR32, MCK_FR32 } },
+ { X86::MASKMOVDQU64, Convert_Reg1_2_Reg1_1, { MCK_maskmovdqu, MCK_FR32, MCK_FR32 } },
{ X86::MMX_MASKMOVQ, Convert_Reg1_2_Reg1_1, { MCK_maskmovq, MCK_VR64, MCK_VR64 } },
{ X86::MMX_MASKMOVQ64, Convert_Reg1_2_Reg1_1, { MCK_maskmovq, MCK_VR64, MCK_VR64 } },
{ X86::MAXPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_maxpd, MCK_FR32, MCK_FR32 } },
@@ -7234,21 +7234,21 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::MINSSrr, Convert_Reg1_2_ImpReg1_1, { MCK_minss, MCK_FR32, MCK_FR32 } },
{ X86::MINSSrm, Convert_Reg1_2_ImpMem5_1, { MCK_minss, MCK_Mem, MCK_FR32 } },
{ X86::MOV64ri, Convert_Reg1_2_Imm1_1, { MCK_movabsq, MCK_Imm, MCK_GR64 } },
- { X86::MOVAPDrr, Convert_Reg1_2_Reg1_1, { MCK_movapd, MCK_FR32, MCK_FR32 } },
{ X86::FsMOVAPDrr, Convert_Reg1_2_Reg1_1, { MCK_movapd, MCK_FR32, MCK_FR32 } },
+ { X86::MOVAPDrr, Convert_Reg1_2_Reg1_1, { MCK_movapd, MCK_FR32, MCK_FR32 } },
{ X86::MOVAPDmr, Convert_Mem5_2_Reg1_1, { MCK_movapd, MCK_FR32, MCK_Mem } },
{ X86::FsMOVAPDrm, Convert_Reg1_2_Mem5_1, { MCK_movapd, MCK_Mem, MCK_FR32 } },
{ X86::MOVAPDrm, Convert_Reg1_2_Mem5_1, { MCK_movapd, MCK_Mem, MCK_FR32 } },
- { X86::FsMOVAPSrr, Convert_Reg1_2_Reg1_1, { MCK_movaps, MCK_FR32, MCK_FR32 } },
{ X86::MOVAPSrr, Convert_Reg1_2_Reg1_1, { MCK_movaps, MCK_FR32, MCK_FR32 } },
+ { X86::FsMOVAPSrr, Convert_Reg1_2_Reg1_1, { MCK_movaps, MCK_FR32, MCK_FR32 } },
{ X86::MOVAPSmr, Convert_Mem5_2_Reg1_1, { MCK_movaps, MCK_FR32, MCK_Mem } },
{ X86::MOVAPSrm, Convert_Reg1_2_Mem5_1, { MCK_movaps, MCK_Mem, MCK_FR32 } },
{ X86::FsMOVAPSrm, Convert_Reg1_2_Mem5_1, { MCK_movaps, MCK_Mem, MCK_FR32 } },
{ X86::MOV8ao8, Convert_Imm1_2, { MCK_movb, MCK_AL, MCK_Imm } },
{ X86::MOV8rr_NOREX, Convert_Reg1_2_Reg1_1, { MCK_movb, MCK_GR8_NOREX, MCK_GR8_NOREX } },
{ X86::MOV8mr_NOREX, Convert_Mem5_2_Reg1_1, { MCK_movb, MCK_GR8_NOREX, MCK_Mem } },
- { X86::MOV8rr_REV, Convert_Reg1_2_Reg1_1, { MCK_movb, MCK_GR8, MCK_GR8 } },
{ X86::MOV8rr, Convert_Reg1_2_Reg1_1, { MCK_movb, MCK_GR8, MCK_GR8 } },
+ { X86::MOV8rr_REV, Convert_Reg1_2_Reg1_1, { MCK_movb, MCK_GR8, MCK_GR8 } },
{ X86::MOV8mr, Convert_Mem5_2_Reg1_1, { MCK_movb, MCK_GR8, MCK_Mem } },
{ X86::MOV8o8a, Convert_Imm1_1, { MCK_movb, MCK_Imm, MCK_AL } },
{ X86::MOV8ri, Convert_Reg1_2_Imm1_1, { MCK_movb, MCK_Imm, MCK_GR8 } },
@@ -7257,25 +7257,25 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::MOV8rm, Convert_Reg1_2_Mem5_1, { MCK_movb, MCK_Mem, MCK_GR8 } },
{ X86::MMX_MOVZDI2PDIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_VR64 } },
{ X86::MMX_MOVD64rr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_VR64 } },
+ { X86::MOVDI2SSrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_FR32 } },
{ X86::MOVDI2PDIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_FR32 } },
{ X86::MOVZDI2PDIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_FR32 } },
- { X86::MOVDI2SSrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR32, MCK_FR32 } },
- { X86::MMX_MOVD64rrv164, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_VR64 } },
{ X86::MMX_MOVD64to64rr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_VR64 } },
- { X86::MOV64toSDrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_FR32 } },
+ { X86::MMX_MOVD64rrv164, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_VR64 } },
{ X86::MOV64toPQIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_FR32 } },
{ X86::MOVZQI2PQIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_FR32 } },
+ { X86::MOV64toSDrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_GR64, MCK_FR32 } },
{ X86::MMX_MOVD64grr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_VR64, MCK_GR32 } },
{ X86::MMX_MOVD64from64rr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_VR64, MCK_GR64 } },
{ X86::MMX_MOVD64mr, Convert_Mem5_2_Reg1_1, { MCK_movd, MCK_VR64, MCK_Mem } },
{ X86::MOVSS2DIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_GR32 } },
{ X86::MOVPDI2DIrr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_GR32 } },
- { X86::MOVSDto64rr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_GR64 } },
{ X86::MOVPQIto64rr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_GR64 } },
- { X86::MOVPDI2DImr, Convert_Mem5_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_Mem } },
+ { X86::MOVSDto64rr, Convert_Reg1_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_GR64 } },
{ X86::MOVSS2DImr, Convert_Mem5_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_Mem } },
- { X86::MMX_MOVD64rm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_VR64 } },
+ { X86::MOVPDI2DImr, Convert_Mem5_2_Reg1_1, { MCK_movd, MCK_FR32, MCK_Mem } },
{ X86::MMX_MOVZDI2PDIrm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_VR64 } },
+ { X86::MMX_MOVD64rm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_VR64 } },
{ X86::MOVZDI2PDIrm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_FR32 } },
{ X86::MOVDI2PDIrm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_FR32 } },
{ X86::MOVDI2SSrm, Convert_Reg1_2_Mem5_1, { MCK_movd, MCK_Mem, MCK_FR32 } },
@@ -7318,20 +7318,20 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::MOV32cr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_GR32, MCK_CONTROL_REG_32 } },
{ X86::MOV64ao64, Convert_Imm1_2, { MCK_movq, MCK_RAX, MCK_Imm } },
{ X86::MOV64ao8, Convert_Imm1_2, { MCK_movq, MCK_RAX, MCK_Imm } },
- { X86::MOV64rr_REV, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_GR64 } },
{ X86::MOV64rr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_GR64 } },
+ { X86::MOV64rr_REV, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_GR64 } },
{ X86::MOV64sr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_SEGMENT_REG } },
{ X86::MOV64dr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_DEBUG_REG } },
{ X86::MOV64cr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_CONTROL_REG_64 } },
{ X86::MOV64mr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_GR64, MCK_Mem } },
{ X86::MMX_MOVQ64rr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_VR64, MCK_VR64 } },
- { X86::MMX_MOVQ64gmr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_VR64, MCK_Mem } },
{ X86::MMX_MOVQ64mr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_VR64, MCK_Mem } },
- { X86::MOVZPQILo2PQIrr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_FR32 } },
+ { X86::MMX_MOVQ64gmr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_VR64, MCK_Mem } },
{ X86::MOVQxrxr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_FR32 } },
- { X86::MOVLQ128mr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_Mem } },
+ { X86::MOVZPQILo2PQIrr, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_FR32 } },
{ X86::MOVSDto64mr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_Mem } },
{ X86::MOVPQI2QImr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_Mem } },
+ { X86::MOVLQ128mr, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_FR32, MCK_Mem } },
{ X86::MOV64rs, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_SEGMENT_REG, MCK_GR64 } },
{ X86::MOV64ms, Convert_Mem5_2_Reg1_1, { MCK_movq, MCK_SEGMENT_REG, MCK_Mem } },
{ X86::MOV64rd, Convert_Reg1_2_Reg1_1, { MCK_movq, MCK_DEBUG_REG, MCK_GR64 } },
@@ -7344,12 +7344,12 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::MOV64rm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_GR64 } },
{ X86::MMX_MOVQ64rm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_VR64 } },
{ X86::MOVQI2PQIrm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
- { X86::MOV64toSDrm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
{ X86::MOVZPQILo2PQIrm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
{ X86::MOVZQI2PQIrm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
+ { X86::MOV64toSDrm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_FR32 } },
{ X86::MOV64sm, Convert_Reg1_2_Mem5_1, { MCK_movq, MCK_Mem, MCK_SEGMENT_REG } },
- { X86::MMX_MOVQ2FR64rr, Convert_Reg1_2_Reg1_1, { MCK_movq2dq, MCK_VR64, MCK_FR32 } },
{ X86::MMX_MOVQ2DQrr, Convert_Reg1_2_Reg1_1, { MCK_movq2dq, MCK_VR64, MCK_FR32 } },
+ { X86::MMX_MOVQ2FR64rr, Convert_Reg1_2_Reg1_1, { MCK_movq2dq, MCK_VR64, MCK_FR32 } },
{ X86::MOVSX32rr8, Convert_Reg1_2_Reg1_1, { MCK_movsbl, MCK_GR8, MCK_GR32 } },
{ X86::MOVSX32rm8, Convert_Reg1_2_Mem5_1, { MCK_movsbl, MCK_Mem, MCK_GR32 } },
{ X86::MOVSX64rr8, Convert_Reg1_2_Reg1_1, { MCK_movsbq, MCK_GR8, MCK_GR64 } },
@@ -7357,15 +7357,15 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::MOVSX16rr8W, Convert_Reg1_2_Reg1_1, { MCK_movsbw, MCK_GR8, MCK_GR16 } },
{ X86::MOVSX16rm8W, Convert_Reg1_2_Mem5_1, { MCK_movsbw, MCK_Mem, MCK_GR16 } },
{ X86::MOVSDrr, Convert_Reg1_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
- { X86::MOVLPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
{ X86::MOVLSD2PDrr, Convert_Reg1_2_ImpReg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
- { X86::MOVSD2PDrr, Convert_Reg1_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
{ X86::MOVPD2SDrr, Convert_Reg1_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
+ { X86::MOVLPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
+ { X86::MOVSD2PDrr, Convert_Reg1_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
{ X86::MOVSDmr, Convert_Mem5_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_Mem } },
{ X86::MOVPD2SDmr, Convert_Mem5_2_Reg1_1, { MCK_movsd, MCK_FR32, MCK_Mem } },
+ { X86::MOVSD2PDrm, Convert_Reg1_2_Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
{ X86::MOVZSD2PDrm, Convert_Reg1_2_Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
{ X86::MOVSDrm, Convert_Reg1_2_Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
- { X86::MOVSD2PDrm, Convert_Reg1_2_Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
{ X86::MOVSHDUPrr, Convert_Reg1_2_Reg1_1, { MCK_movshdup, MCK_FR32, MCK_FR32 } },
{ X86::MOVSHDUPrm, Convert_Reg1_2_Mem5_1, { MCK_movshdup, MCK_Mem, MCK_FR32 } },
{ X86::MOVSLDUPrr, Convert_Reg1_2_Reg1_1, { MCK_movsldup, MCK_FR32, MCK_FR32 } },
@@ -7374,14 +7374,14 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::MOVSX64rm32, Convert_Reg1_2_Mem5_1, { MCK_movslq, MCK_Mem, MCK_GR64 } },
{ X86::MOVPS2SSrr, Convert_Reg1_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
{ X86::MOVSS2PSrr, Convert_Reg1_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
+ { X86::MOVSSrr, Convert_Reg1_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
{ X86::MOVLSS2PSrr, Convert_Reg1_2_ImpReg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
{ X86::MOVLPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
- { X86::MOVSSrr, Convert_Reg1_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
{ X86::MOVPS2SSmr, Convert_Mem5_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_Mem } },
{ X86::MOVSSmr, Convert_Mem5_2_Reg1_1, { MCK_movss, MCK_FR32, MCK_Mem } },
- { X86::MOVZSS2PSrm, Convert_Reg1_2_Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
- { X86::MOVSSrm, Convert_Reg1_2_Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
{ X86::MOVSS2PSrm, Convert_Reg1_2_Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
+ { X86::MOVSSrm, Convert_Reg1_2_Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
+ { X86::MOVZSS2PSrm, Convert_Reg1_2_Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
{ X86::MOVSX32rr16, Convert_Reg1_2_Reg1_1, { MCK_movswl, MCK_GR16, MCK_GR32 } },
{ X86::MOVSX32rm16, Convert_Reg1_2_Mem5_1, { MCK_movswl, MCK_Mem, MCK_GR32 } },
{ X86::MOVSX64rr16, Convert_Reg1_2_Reg1_1, { MCK_movswq, MCK_GR16, MCK_GR64 } },
@@ -7424,15 +7424,15 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::MULSDrm, Convert_Reg1_2_ImpMem5_1, { MCK_mulsd, MCK_Mem, MCK_FR32 } },
{ X86::MULSSrr, Convert_Reg1_2_ImpReg1_1, { MCK_mulss, MCK_FR32, MCK_FR32 } },
{ X86::MULSSrm, Convert_Reg1_2_ImpMem5_1, { MCK_mulss, MCK_Mem, MCK_FR32 } },
- { X86::OR8rr, Convert_Reg1_2_ImpReg1_1, { MCK_orb, MCK_GR8, MCK_GR8 } },
{ X86::OR8rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_orb, MCK_GR8, MCK_GR8 } },
+ { X86::OR8rr, Convert_Reg1_2_ImpReg1_1, { MCK_orb, MCK_GR8, MCK_GR8 } },
{ X86::OR8mr, Convert_Mem5_2_Reg1_1, { MCK_orb, MCK_GR8, MCK_Mem } },
{ X86::OR8i8, Convert_Imm1_1, { MCK_orb, MCK_Imm, MCK_AL } },
{ X86::OR8ri, Convert_Reg1_2_ImpImm1_1, { MCK_orb, MCK_Imm, MCK_GR8 } },
{ X86::OR8mi, Convert_Mem5_2_Imm1_1, { MCK_orb, MCK_Imm, MCK_Mem } },
{ X86::OR8rm, Convert_Reg1_2_ImpMem5_1, { MCK_orb, MCK_Mem, MCK_GR8 } },
- { X86::OR32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_orl, MCK_GR32, MCK_GR32 } },
{ X86::OR32rr, Convert_Reg1_2_ImpReg1_1, { MCK_orl, MCK_GR32, MCK_GR32 } },
+ { X86::OR32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_orl, MCK_GR32, MCK_GR32 } },
{ X86::OR32mr, Convert_Mem5_2_Reg1_1, { MCK_orl, MCK_GR32, MCK_Mem } },
{ X86::OR32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_orl, MCK_ImmSExt8, MCK_GR32 } },
{ X86::OR32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_orl, MCK_ImmSExt8, MCK_Mem } },
@@ -7440,14 +7440,14 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::OR32ri, Convert_Reg1_2_ImpImm1_1, { MCK_orl, MCK_Imm, MCK_GR32 } },
{ X86::OR32mi, Convert_Mem5_2_Imm1_1, { MCK_orl, MCK_Imm, MCK_Mem } },
{ X86::OR32rm, Convert_Reg1_2_ImpMem5_1, { MCK_orl, MCK_Mem, MCK_GR32 } },
- { X86::FsORPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_orpd, MCK_FR32, MCK_FR32 } },
{ X86::ORPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_orpd, MCK_FR32, MCK_FR32 } },
- { X86::FsORPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_orpd, MCK_Mem, MCK_FR32 } },
+ { X86::FsORPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_orpd, MCK_FR32, MCK_FR32 } },
{ X86::ORPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_orpd, MCK_Mem, MCK_FR32 } },
- { X86::ORPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_orps, MCK_FR32, MCK_FR32 } },
+ { X86::FsORPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_orpd, MCK_Mem, MCK_FR32 } },
{ X86::FsORPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_orps, MCK_FR32, MCK_FR32 } },
- { X86::ORPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_orps, MCK_Mem, MCK_FR32 } },
+ { X86::ORPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_orps, MCK_FR32, MCK_FR32 } },
{ X86::FsORPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_orps, MCK_Mem, MCK_FR32 } },
+ { X86::ORPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_orps, MCK_Mem, MCK_FR32 } },
{ X86::OR64rr, Convert_Reg1_2_ImpReg1_1, { MCK_orq, MCK_GR64, MCK_GR64 } },
{ X86::OR64rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_orq, MCK_GR64, MCK_GR64 } },
{ X86::OR64mr, Convert_Mem5_2_Reg1_1, { MCK_orq, MCK_GR64, MCK_Mem } },
@@ -7949,8 +7949,8 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::SBB8ri, Convert_Reg1_2_ImpImm1_1, { MCK_sbbb, MCK_Imm, MCK_GR8 } },
{ X86::SBB8mi, Convert_Mem5_2_Imm1_1, { MCK_sbbb, MCK_Imm, MCK_Mem } },
{ X86::SBB8rm, Convert_Reg1_2_ImpMem5_1, { MCK_sbbb, MCK_Mem, MCK_GR8 } },
- { X86::SBB32rr, Convert_Reg1_2_ImpReg1_1, { MCK_sbbl, MCK_GR32, MCK_GR32 } },
{ X86::SBB32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_sbbl, MCK_GR32, MCK_GR32 } },
+ { X86::SBB32rr, Convert_Reg1_2_ImpReg1_1, { MCK_sbbl, MCK_GR32, MCK_GR32 } },
{ X86::SBB32mr, Convert_Mem5_2_Reg1_1, { MCK_sbbl, MCK_GR32, MCK_Mem } },
{ X86::SBB32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_sbbl, MCK_ImmSExt8, MCK_GR32 } },
{ X86::SBB32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_sbbl, MCK_ImmSExt8, MCK_Mem } },
@@ -7958,8 +7958,8 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::SBB32ri, Convert_Reg1_2_ImpImm1_1, { MCK_sbbl, MCK_Imm, MCK_GR32 } },
{ X86::SBB32mi, Convert_Mem5_2_Imm1_1, { MCK_sbbl, MCK_Imm, MCK_Mem } },
{ X86::SBB32rm, Convert_Reg1_2_ImpMem5_1, { MCK_sbbl, MCK_Mem, MCK_GR32 } },
- { X86::SBB64rr, Convert_Reg1_2_ImpReg1_1, { MCK_sbbq, MCK_GR64, MCK_GR64 } },
{ X86::SBB64rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_sbbq, MCK_GR64, MCK_GR64 } },
+ { X86::SBB64rr, Convert_Reg1_2_ImpReg1_1, { MCK_sbbq, MCK_GR64, MCK_GR64 } },
{ X86::SBB64mr, Convert_Mem5_2_Reg1_1, { MCK_sbbq, MCK_GR64, MCK_Mem } },
{ X86::SBB64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_sbbq, MCK_ImmSExt8, MCK_GR64 } },
{ X86::SBB64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_sbbq, MCK_ImmSExt8, MCK_Mem } },
@@ -8016,8 +8016,8 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::SQRTSDm, Convert_Reg1_2_Mem5_1, { MCK_sqrtsd, MCK_Mem, MCK_FR32 } },
{ X86::SQRTSSr, Convert_Reg1_2_Reg1_1, { MCK_sqrtss, MCK_FR32, MCK_FR32 } },
{ X86::SQRTSSm, Convert_Reg1_2_Mem5_1, { MCK_sqrtss, MCK_Mem, MCK_FR32 } },
- { X86::SUB8rr, Convert_Reg1_2_ImpReg1_1, { MCK_subb, MCK_GR8, MCK_GR8 } },
{ X86::SUB8rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_subb, MCK_GR8, MCK_GR8 } },
+ { X86::SUB8rr, Convert_Reg1_2_ImpReg1_1, { MCK_subb, MCK_GR8, MCK_GR8 } },
{ X86::SUB8mr, Convert_Mem5_2_Reg1_1, { MCK_subb, MCK_GR8, MCK_Mem } },
{ X86::SUB8i8, Convert_Imm1_1, { MCK_subb, MCK_Imm, MCK_AL } },
{ X86::SUB8ri, Convert_Reg1_2_ImpImm1_1, { MCK_subb, MCK_Imm, MCK_GR8 } },
@@ -8049,8 +8049,8 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::SUBSDrm, Convert_Reg1_2_ImpMem5_1, { MCK_subsd, MCK_Mem, MCK_FR32 } },
{ X86::SUBSSrr, Convert_Reg1_2_ImpReg1_1, { MCK_subss, MCK_FR32, MCK_FR32 } },
{ X86::SUBSSrm, Convert_Reg1_2_ImpMem5_1, { MCK_subss, MCK_Mem, MCK_FR32 } },
- { X86::SUB16rr, Convert_Reg1_2_ImpReg1_1, { MCK_subw, MCK_GR16, MCK_GR16 } },
{ X86::SUB16rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_subw, MCK_GR16, MCK_GR16 } },
+ { X86::SUB16rr, Convert_Reg1_2_ImpReg1_1, { MCK_subw, MCK_GR16, MCK_GR16 } },
{ X86::SUB16mr, Convert_Mem5_2_Reg1_1, { MCK_subw, MCK_GR16, MCK_Mem } },
{ X86::SUB16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_subw, MCK_ImmSExt8, MCK_GR16 } },
{ X86::SUB16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_subw, MCK_ImmSExt8, MCK_Mem } },
@@ -8124,8 +8124,8 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::XOR8ri, Convert_Reg1_2_ImpImm1_1, { MCK_xorb, MCK_Imm, MCK_GR8 } },
{ X86::XOR8mi, Convert_Mem5_2_Imm1_1, { MCK_xorb, MCK_Imm, MCK_Mem } },
{ X86::XOR8rm, Convert_Reg1_2_ImpMem5_1, { MCK_xorb, MCK_Mem, MCK_GR8 } },
- { X86::XOR32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_xorl, MCK_GR32, MCK_GR32 } },
{ X86::XOR32rr, Convert_Reg1_2_ImpReg1_1, { MCK_xorl, MCK_GR32, MCK_GR32 } },
+ { X86::XOR32rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_xorl, MCK_GR32, MCK_GR32 } },
{ X86::XOR32mr, Convert_Mem5_2_Reg1_1, { MCK_xorl, MCK_GR32, MCK_Mem } },
{ X86::XOR32ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_xorl, MCK_ImmSExt8, MCK_GR32 } },
{ X86::XOR32mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_xorl, MCK_ImmSExt8, MCK_Mem } },
@@ -8135,14 +8135,14 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::XOR32rm, Convert_Reg1_2_ImpMem5_1, { MCK_xorl, MCK_Mem, MCK_GR32 } },
{ X86::XORPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_xorpd, MCK_FR32, MCK_FR32 } },
{ X86::FsXORPDrr, Convert_Reg1_2_ImpReg1_1, { MCK_xorpd, MCK_FR32, MCK_FR32 } },
- { X86::XORPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_xorpd, MCK_Mem, MCK_FR32 } },
{ X86::FsXORPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_xorpd, MCK_Mem, MCK_FR32 } },
- { X86::XORPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_xorps, MCK_FR32, MCK_FR32 } },
+ { X86::XORPDrm, Convert_Reg1_2_ImpMem5_1, { MCK_xorpd, MCK_Mem, MCK_FR32 } },
{ X86::FsXORPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_xorps, MCK_FR32, MCK_FR32 } },
- { X86::FsXORPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_xorps, MCK_Mem, MCK_FR32 } },
+ { X86::XORPSrr, Convert_Reg1_2_ImpReg1_1, { MCK_xorps, MCK_FR32, MCK_FR32 } },
{ X86::XORPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_xorps, MCK_Mem, MCK_FR32 } },
- { X86::XOR64rr, Convert_Reg1_2_ImpReg1_1, { MCK_xorq, MCK_GR64, MCK_GR64 } },
+ { X86::FsXORPSrm, Convert_Reg1_2_ImpMem5_1, { MCK_xorps, MCK_Mem, MCK_FR32 } },
{ X86::XOR64rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_xorq, MCK_GR64, MCK_GR64 } },
+ { X86::XOR64rr, Convert_Reg1_2_ImpReg1_1, { MCK_xorq, MCK_GR64, MCK_GR64 } },
{ X86::XOR64mr, Convert_Mem5_2_Reg1_1, { MCK_xorq, MCK_GR64, MCK_Mem } },
{ X86::XOR64ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_xorq, MCK_ImmSExt8, MCK_GR64 } },
{ X86::XOR64mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_xorq, MCK_ImmSExt8, MCK_Mem } },
@@ -8150,8 +8150,8 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::XOR64ri32, Convert_Reg1_2_ImpImm1_1, { MCK_xorq, MCK_Imm, MCK_GR64 } },
{ X86::XOR64mi32, Convert_Mem5_2_Imm1_1, { MCK_xorq, MCK_Imm, MCK_Mem } },
{ X86::XOR64rm, Convert_Reg1_2_ImpMem5_1, { MCK_xorq, MCK_Mem, MCK_GR64 } },
- { X86::XOR16rr, Convert_Reg1_2_ImpReg1_1, { MCK_xorw, MCK_GR16, MCK_GR16 } },
{ X86::XOR16rr_REV, Convert_Reg1_2_ImpReg1_1, { MCK_xorw, MCK_GR16, MCK_GR16 } },
+ { X86::XOR16rr, Convert_Reg1_2_ImpReg1_1, { MCK_xorw, MCK_GR16, MCK_GR16 } },
{ X86::XOR16mr, Convert_Mem5_2_Reg1_1, { MCK_xorw, MCK_GR16, MCK_Mem } },
{ X86::XOR16ri8, Convert_Reg1_2_ImpImmSExt81_1, { MCK_xorw, MCK_ImmSExt8, MCK_GR16 } },
{ X86::XOR16mi8, Convert_Mem5_2_ImmSExt81_1, { MCK_xorw, MCK_ImmSExt8, MCK_Mem } },
@@ -8197,32 +8197,32 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
{ X86::PBLENDVBrm0, Convert_Reg1_3_ImpMem5_2, { MCK_pblendvb, MCK_XMM0, MCK_Mem, MCK_FR32 } },
{ X86::PBLENDWrri, Convert_Reg1_3_ImpReg1_2_ImmSExt81_1, { MCK_pblendw, MCK_ImmSExt8, MCK_FR32, MCK_FR32 } },
{ X86::PBLENDWrmi, Convert_Reg1_3_ImpMem5_2_ImmSExt81_1, { MCK_pblendw, MCK_ImmSExt8, MCK_Mem, MCK_FR32 } },
- { X86::PCMPESTRIrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPESTRIZrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPESTRISrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
{ X86::PCMPESTRIOrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPESTRISrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPESTRIZrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPESTRIrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
{ X86::PCMPESTRICrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
{ X86::PCMPESTRIArr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_FR32, MCK_FR32 } },
{ X86::PCMPESTRIOrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPESTRISrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPESTRICrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPESTRIZrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
{ X86::PCMPESTRIrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPESTRIZrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPESTRISrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
{ X86::PCMPESTRIArm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPESTRICrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestri, MCK_Imm, MCK_Mem, MCK_FR32 } },
{ X86::PCMPESTRM128rr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpestrm, MCK_Imm, MCK_FR32, MCK_FR32 } },
{ X86::PCMPESTRM128rm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpestrm, MCK_Imm, MCK_Mem, MCK_FR32 } },
{ X86::PCMPISTRIArr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
{ X86::PCMPISTRICrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
+ { X86::PCMPISTRIrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
{ X86::PCMPISTRIOrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
{ X86::PCMPISTRISrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
{ X86::PCMPISTRIZrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPISTRIrr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_FR32, MCK_FR32 } },
- { X86::PCMPISTRIZrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPISTRISrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPISTRIOrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPISTRIrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
- { X86::PCMPISTRICrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
{ X86::PCMPISTRIArm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRICrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRIrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRIOrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRISrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
+ { X86::PCMPISTRIZrm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistri, MCK_Imm, MCK_Mem, MCK_FR32 } },
{ X86::PCMPISTRM128rr, Convert_Reg1_3_Reg1_2_Imm1_1, { MCK_pcmpistrm, MCK_Imm, MCK_FR32, MCK_FR32 } },
{ X86::PCMPISTRM128rm, Convert_Reg1_3_Mem5_2_Imm1_1, { MCK_pcmpistrm, MCK_Imm, MCK_Mem, MCK_FR32 } },
{ X86::PEXTRBrr, Convert_Reg1_3_Reg1_2_ImmSExt81_1, { MCK_pextrb, MCK_ImmSExt8, MCK_FR32, MCK_GR32 } },
@@ -8309,7 +8309,7 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
Classes[i] = InvalidMatchClass;
// Search the table.
- for (const MatchEntry *it = MatchTable, *ie = MatchTable + 2041; it != ie; ++it) {
+ for (const MatchEntry *it = MatchTable, *ie = MatchTable + 2040; it != ie; ++it) {
if (!IsSubclass(Classes[0], it->Classes[0]))
continue;
if (!IsSubclass(Classes[1], it->Classes[1]))
@@ -8327,3 +8327,4 @@ bool X86ATTAsmParser::MatchInstruction(SmallVectorImpl<X86Operand> &Operands, MC
return true;
}
+#endif // REGISTERS_ONLY
diff --git a/libclamav/c++/X86GenAsmWriter.inc b/libclamav/c++/X86GenAsmWriter.inc
index 24fdc1d..38d2786 100644
--- a/libclamav/c++/X86GenAsmWriter.inc
+++ b/libclamav/c++/X86GenAsmWriter.inc
@@ -21,100 +21,101 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // IMPLICIT_DEF
0U, // SUBREG_TO_REG
0U, // COPY_TO_REGCLASS
- 1U, // ABS_F
+ 1U, // DEBUG_VALUE
+ 13U, // ABS_F
0U, // ABS_Fp32
0U, // ABS_Fp64
0U, // ABS_Fp80
- 67108870U, // ADC16i16
- 135266310U, // ADC16mi
- 135266310U, // ADC16mi8
- 135266310U, // ADC16mr
- 203456518U, // ADC16ri
- 203456518U, // ADC16ri8
- 270565382U, // ADC16rm
- 203456518U, // ADC16rr
- 203456518U, // ADC16rr_REV
- 70254604U, // ADC32i32
- 135331852U, // ADC32mi
- 135331852U, // ADC32mi8
- 135331852U, // ADC32mr
- 203456524U, // ADC32ri
- 203456524U, // ADC32ri8
- 337674252U, // ADC32rm
- 203456524U, // ADC32rr
- 203456524U, // ADC32rr_REV
- 71303186U, // ADC64i32
- 135364626U, // ADC64mi32
- 135364626U, // ADC64mi8
- 135364626U, // ADC64mr
- 203456530U, // ADC64ri32
- 203456530U, // ADC64ri8
- 404783122U, // ADC64rm
- 203456530U, // ADC64rr
- 203456530U, // ADC64rr_REV
- 72351768U, // ADC8i8
- 135397400U, // ADC8mi
- 135397400U, // ADC8mr
- 203456536U, // ADC8ri
- 471891992U, // ADC8rm
- 203456536U, // ADC8rr
- 203456536U, // ADC8rr_REV
- 67108894U, // ADD16i16
- 135266334U, // ADD16mi
- 135266334U, // ADD16mi8
- 135266334U, // ADD16mr
- 203456542U, // ADD16mrmrr
- 203456542U, // ADD16ri
- 203456542U, // ADD16ri8
- 270565406U, // ADD16rm
- 203456542U, // ADD16rr
- 70254628U, // ADD32i32
- 135331876U, // ADD32mi
- 135331876U, // ADD32mi8
- 135331876U, // ADD32mr
- 203456548U, // ADD32mrmrr
- 203456548U, // ADD32ri
- 203456548U, // ADD32ri8
- 337674276U, // ADD32rm
- 203456548U, // ADD32rr
- 71303210U, // ADD64i32
- 135364650U, // ADD64mi32
- 135364650U, // ADD64mi8
- 135364650U, // ADD64mr
- 203456548U, // ADD64mrmrr
- 203456554U, // ADD64ri32
- 203456554U, // ADD64ri8
- 404783146U, // ADD64rm
- 203456554U, // ADD64rr
- 72351792U, // ADD8i8
- 135397424U, // ADD8mi
- 135397424U, // ADD8mr
- 203456560U, // ADD8mrmrr
- 203456560U, // ADD8ri
- 471892016U, // ADD8rm
- 203456560U, // ADD8rr
- 536870966U, // ADDPDrm
- 203456566U, // ADDPDrr
- 536870973U, // ADDPSrm
- 203456573U, // ADDPSrr
- 603979844U, // ADDSDrm
- 603979844U, // ADDSDrm_Int
- 203456580U, // ADDSDrr
- 203456580U, // ADDSDrr_Int
- 671088715U, // ADDSSrm
- 671088715U, // ADDSSrm_Int
- 203456587U, // ADDSSrr
- 203456587U, // ADDSSrr_Int
- 536870994U, // ADDSUBPDrm
- 203456594U, // ADDSUBPDrr
- 536871004U, // ADDSUBPSrm
- 203456604U, // ADDSUBPSrr
- 738197606U, // ADD_F32m
- 805306477U, // ADD_F64m
- 872415348U, // ADD_FI16m
- 945815676U, // ADD_FI32m
- 73400452U, // ADD_FPrST0
- 73400459U, // ADD_FST0r
+ 67108882U, // ADC16i16
+ 135266322U, // ADC16mi
+ 135266322U, // ADC16mi8
+ 135266322U, // ADC16mr
+ 203456530U, // ADC16ri
+ 203456530U, // ADC16ri8
+ 270565394U, // ADC16rm
+ 203456530U, // ADC16rr
+ 203456530U, // ADC16rr_REV
+ 70254616U, // ADC32i32
+ 135331864U, // ADC32mi
+ 135331864U, // ADC32mi8
+ 135331864U, // ADC32mr
+ 203456536U, // ADC32ri
+ 203456536U, // ADC32ri8
+ 337674264U, // ADC32rm
+ 203456536U, // ADC32rr
+ 203456536U, // ADC32rr_REV
+ 71303198U, // ADC64i32
+ 135364638U, // ADC64mi32
+ 135364638U, // ADC64mi8
+ 135364638U, // ADC64mr
+ 203456542U, // ADC64ri32
+ 203456542U, // ADC64ri8
+ 404783134U, // ADC64rm
+ 203456542U, // ADC64rr
+ 203456542U, // ADC64rr_REV
+ 72351780U, // ADC8i8
+ 135397412U, // ADC8mi
+ 135397412U, // ADC8mr
+ 203456548U, // ADC8ri
+ 471892004U, // ADC8rm
+ 203456548U, // ADC8rr
+ 203456548U, // ADC8rr_REV
+ 67108906U, // ADD16i16
+ 135266346U, // ADD16mi
+ 135266346U, // ADD16mi8
+ 135266346U, // ADD16mr
+ 203456554U, // ADD16mrmrr
+ 203456554U, // ADD16ri
+ 203456554U, // ADD16ri8
+ 270565418U, // ADD16rm
+ 203456554U, // ADD16rr
+ 70254640U, // ADD32i32
+ 135331888U, // ADD32mi
+ 135331888U, // ADD32mi8
+ 135331888U, // ADD32mr
+ 203456560U, // ADD32mrmrr
+ 203456560U, // ADD32ri
+ 203456560U, // ADD32ri8
+ 337674288U, // ADD32rm
+ 203456560U, // ADD32rr
+ 71303222U, // ADD64i32
+ 135364662U, // ADD64mi32
+ 135364662U, // ADD64mi8
+ 135364662U, // ADD64mr
+ 203456560U, // ADD64mrmrr
+ 203456566U, // ADD64ri32
+ 203456566U, // ADD64ri8
+ 404783158U, // ADD64rm
+ 203456566U, // ADD64rr
+ 72351804U, // ADD8i8
+ 135397436U, // ADD8mi
+ 135397436U, // ADD8mr
+ 203456572U, // ADD8mrmrr
+ 203456572U, // ADD8ri
+ 471892028U, // ADD8rm
+ 203456572U, // ADD8rr
+ 536870978U, // ADDPDrm
+ 203456578U, // ADDPDrr
+ 536870985U, // ADDPSrm
+ 203456585U, // ADDPSrr
+ 603979856U, // ADDSDrm
+ 603979856U, // ADDSDrm_Int
+ 203456592U, // ADDSDrr
+ 203456592U, // ADDSDrr_Int
+ 671088727U, // ADDSSrm
+ 671088727U, // ADDSSrm_Int
+ 203456599U, // ADDSSrr
+ 203456599U, // ADDSSrr_Int
+ 536871006U, // ADDSUBPDrm
+ 203456606U, // ADDSUBPDrr
+ 536871016U, // ADDSUBPSrm
+ 203456616U, // ADDSUBPSrr
+ 738197618U, // ADD_F32m
+ 805306489U, // ADD_F64m
+ 872415360U, // ADD_FI16m
+ 945815688U, // ADD_FI32m
+ 73400464U, // ADD_FPrST0
+ 73400471U, // ADD_FST0r
0U, // ADD_Fp32
0U, // ADD_Fp32m
0U, // ADD_Fp64
@@ -129,462 +130,462 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ADD_FpI32m32
0U, // ADD_FpI32m64
0U, // ADD_FpI32m80
- 73400465U, // ADD_FrST0
- 159U, // ADJCALLSTACKDOWN32
- 159U, // ADJCALLSTACKDOWN64
- 177U, // ADJCALLSTACKUP32
- 177U, // ADJCALLSTACKUP64
- 67109057U, // AND16i16
- 135266497U, // AND16mi
- 135266497U, // AND16mi8
- 135266497U, // AND16mr
- 203456705U, // AND16ri
- 203456705U, // AND16ri8
- 270565569U, // AND16rm
- 203456705U, // AND16rr
- 203456705U, // AND16rr_REV
- 70254791U, // AND32i32
- 135332039U, // AND32mi
- 135332039U, // AND32mi8
- 135332039U, // AND32mr
- 203456711U, // AND32ri
- 203456711U, // AND32ri8
- 337674439U, // AND32rm
- 203456711U, // AND32rr
- 203456711U, // AND32rr_REV
- 71303373U, // AND64i32
- 135364813U, // AND64mi32
- 135364813U, // AND64mi8
- 135364813U, // AND64mr
- 203456717U, // AND64ri32
- 203456717U, // AND64ri8
- 404783309U, // AND64rm
- 203456717U, // AND64rr
- 203456717U, // AND64rr_REV
- 72351955U, // AND8i8
- 135397587U, // AND8mi
- 135397587U, // AND8mr
- 203456723U, // AND8ri
- 471892179U, // AND8rm
- 203456723U, // AND8rr
- 203456723U, // AND8rr_REV
- 536871129U, // ANDNPDrm
- 203456729U, // ANDNPDrr
- 536871137U, // ANDNPSrm
- 203456737U, // ANDNPSrr
- 536871145U, // ANDPDrm
- 203456745U, // ANDPDrr
- 536871152U, // ANDPSrm
- 203456752U, // ANDPSrr
- 247U, // ATOMADD6432
- 268U, // ATOMAND16
- 287U, // ATOMAND32
- 306U, // ATOMAND64
- 325U, // ATOMAND6432
- 346U, // ATOMAND8
- 364U, // ATOMMAX16
- 383U, // ATOMMAX32
- 402U, // ATOMMAX64
- 421U, // ATOMMIN16
- 440U, // ATOMMIN32
- 459U, // ATOMMIN64
- 478U, // ATOMNAND16
- 498U, // ATOMNAND32
- 518U, // ATOMNAND64
- 538U, // ATOMNAND6432
- 560U, // ATOMNAND8
- 579U, // ATOMOR16
- 597U, // ATOMOR32
- 615U, // ATOMOR64
- 633U, // ATOMOR6432
- 653U, // ATOMOR8
- 670U, // ATOMSUB6432
- 691U, // ATOMSWAP6432
- 713U, // ATOMUMAX16
- 733U, // ATOMUMAX32
- 753U, // ATOMUMAX64
- 773U, // ATOMUMIN16
- 793U, // ATOMUMIN32
- 813U, // ATOMUMIN64
- 833U, // ATOMXOR16
- 852U, // ATOMXOR32
- 871U, // ATOMXOR64
- 890U, // ATOMXOR6432
- 911U, // ATOMXOR8
- 1013973921U, // BLENDPDrmi
- 1073742753U, // BLENDPDrri
- 1013973930U, // BLENDPSrmi
- 1073742762U, // BLENDPSrri
- 1140851635U, // BLENDVPDrm0
- 203457459U, // BLENDVPDrr0
- 1140851652U, // BLENDVPSrm0
- 203457476U, // BLENDVPSrr0
- 1207960533U, // BSF16rm
- 1277199317U, // BSF16rr
- 1342178267U, // BSF32rm
- 1277199323U, // BSF32rr
- 1409287137U, // BSF64rm
- 1277199329U, // BSF64rr
- 1207960551U, // BSR16rm
- 1277199335U, // BSR16rr
- 1342178285U, // BSR32rm
- 1277199341U, // BSR32rr
- 1409287155U, // BSR64rm
- 1277199347U, // BSR64rr
- 73401337U, // BSWAP32r
- 73401345U, // BSWAP64r
- 135267337U, // BT16mi8
- 135267337U, // BT16mr
- 1277199369U, // BT16ri8
- 1277199369U, // BT16rr
- 135332878U, // BT32mi8
- 135332878U, // BT32mr
- 1277199374U, // BT32ri8
- 1277199374U, // BT32rr
- 135365651U, // BT64mi8
- 135365651U, // BT64mr
- 1277199379U, // BT64ri8
- 1277199379U, // BT64rr
- 135267352U, // BTC16mi8
- 135267352U, // BTC16mr
- 1277199384U, // BTC16ri8
- 1277199384U, // BTC16rr
- 135332894U, // BTC32mi8
- 135332894U, // BTC32mr
- 1277199390U, // BTC32ri8
- 1277199390U, // BTC32rr
- 135365668U, // BTC64mi8
- 135365668U, // BTC64mr
- 1277199396U, // BTC64ri8
- 1277199396U, // BTC64rr
- 135267370U, // BTR16mi8
- 135267370U, // BTR16mr
- 1277199402U, // BTR16ri8
- 1277199402U, // BTR16rr
- 135332912U, // BTR32mi8
- 135332912U, // BTR32mr
- 1277199408U, // BTR32ri8
- 1277199408U, // BTR32rr
- 135365686U, // BTR64mi8
- 135365686U, // BTR64mr
- 1277199414U, // BTR64ri8
- 1277199414U, // BTR64rr
- 135267388U, // BTS16mi8
- 135267388U, // BTS16mr
- 1277199420U, // BTS16ri8
- 1277199420U, // BTS16rr
- 135332930U, // BTS32mi8
- 135332930U, // BTS32mr
- 1277199426U, // BTS32ri8
- 1277199426U, // BTS32rr
- 135365704U, // BTS64mi8
- 135365704U, // BTS64mr
- 1277199432U, // BTS64ri8
- 1277199432U, // BTS64rr
- 945816654U, // CALL32m
- 73401422U, // CALL32r
- 1476396117U, // CALL64m
- 1549796445U, // CALL64pcrel32
- 73401429U, // CALL64r
- 1549796452U, // CALLpcrel32
- 1130U, // CBW
- 1135U, // CDQ
- 1140U, // CDQE
- 1145U, // CHS_F
+ 73400477U, // ADD_FrST0
+ 171U, // ADJCALLSTACKDOWN32
+ 171U, // ADJCALLSTACKDOWN64
+ 189U, // ADJCALLSTACKUP32
+ 189U, // ADJCALLSTACKUP64
+ 67109069U, // AND16i16
+ 135266509U, // AND16mi
+ 135266509U, // AND16mi8
+ 135266509U, // AND16mr
+ 203456717U, // AND16ri
+ 203456717U, // AND16ri8
+ 270565581U, // AND16rm
+ 203456717U, // AND16rr
+ 203456717U, // AND16rr_REV
+ 70254803U, // AND32i32
+ 135332051U, // AND32mi
+ 135332051U, // AND32mi8
+ 135332051U, // AND32mr
+ 203456723U, // AND32ri
+ 203456723U, // AND32ri8
+ 337674451U, // AND32rm
+ 203456723U, // AND32rr
+ 203456723U, // AND32rr_REV
+ 71303385U, // AND64i32
+ 135364825U, // AND64mi32
+ 135364825U, // AND64mi8
+ 135364825U, // AND64mr
+ 203456729U, // AND64ri32
+ 203456729U, // AND64ri8
+ 404783321U, // AND64rm
+ 203456729U, // AND64rr
+ 203456729U, // AND64rr_REV
+ 72351967U, // AND8i8
+ 135397599U, // AND8mi
+ 135397599U, // AND8mr
+ 203456735U, // AND8ri
+ 471892191U, // AND8rm
+ 203456735U, // AND8rr
+ 203456735U, // AND8rr_REV
+ 536871141U, // ANDNPDrm
+ 203456741U, // ANDNPDrr
+ 536871149U, // ANDNPSrm
+ 203456749U, // ANDNPSrr
+ 536871157U, // ANDPDrm
+ 203456757U, // ANDPDrr
+ 536871164U, // ANDPSrm
+ 203456764U, // ANDPSrr
+ 259U, // ATOMADD6432
+ 280U, // ATOMAND16
+ 299U, // ATOMAND32
+ 318U, // ATOMAND64
+ 337U, // ATOMAND6432
+ 358U, // ATOMAND8
+ 376U, // ATOMMAX16
+ 395U, // ATOMMAX32
+ 414U, // ATOMMAX64
+ 433U, // ATOMMIN16
+ 452U, // ATOMMIN32
+ 471U, // ATOMMIN64
+ 490U, // ATOMNAND16
+ 510U, // ATOMNAND32
+ 530U, // ATOMNAND64
+ 550U, // ATOMNAND6432
+ 572U, // ATOMNAND8
+ 591U, // ATOMOR16
+ 609U, // ATOMOR32
+ 627U, // ATOMOR64
+ 645U, // ATOMOR6432
+ 665U, // ATOMOR8
+ 682U, // ATOMSUB6432
+ 703U, // ATOMSWAP6432
+ 725U, // ATOMUMAX16
+ 745U, // ATOMUMAX32
+ 765U, // ATOMUMAX64
+ 785U, // ATOMUMIN16
+ 805U, // ATOMUMIN32
+ 825U, // ATOMUMIN64
+ 845U, // ATOMXOR16
+ 864U, // ATOMXOR32
+ 883U, // ATOMXOR64
+ 902U, // ATOMXOR6432
+ 923U, // ATOMXOR8
+ 1013973933U, // BLENDPDrmi
+ 1073742765U, // BLENDPDrri
+ 1013973942U, // BLENDPSrmi
+ 1073742774U, // BLENDPSrri
+ 1140851647U, // BLENDVPDrm0
+ 203457471U, // BLENDVPDrr0
+ 1140851664U, // BLENDVPSrm0
+ 203457488U, // BLENDVPSrr0
+ 1207960545U, // BSF16rm
+ 1277199329U, // BSF16rr
+ 1342178279U, // BSF32rm
+ 1277199335U, // BSF32rr
+ 1409287149U, // BSF64rm
+ 1277199341U, // BSF64rr
+ 1207960563U, // BSR16rm
+ 1277199347U, // BSR16rr
+ 1342178297U, // BSR32rm
+ 1277199353U, // BSR32rr
+ 1409287167U, // BSR64rm
+ 1277199359U, // BSR64rr
+ 73401349U, // BSWAP32r
+ 73401357U, // BSWAP64r
+ 135267349U, // BT16mi8
+ 135267349U, // BT16mr
+ 1277199381U, // BT16ri8
+ 1277199381U, // BT16rr
+ 135332890U, // BT32mi8
+ 135332890U, // BT32mr
+ 1277199386U, // BT32ri8
+ 1277199386U, // BT32rr
+ 135365663U, // BT64mi8
+ 135365663U, // BT64mr
+ 1277199391U, // BT64ri8
+ 1277199391U, // BT64rr
+ 135267364U, // BTC16mi8
+ 135267364U, // BTC16mr
+ 1277199396U, // BTC16ri8
+ 1277199396U, // BTC16rr
+ 135332906U, // BTC32mi8
+ 135332906U, // BTC32mr
+ 1277199402U, // BTC32ri8
+ 1277199402U, // BTC32rr
+ 135365680U, // BTC64mi8
+ 135365680U, // BTC64mr
+ 1277199408U, // BTC64ri8
+ 1277199408U, // BTC64rr
+ 135267382U, // BTR16mi8
+ 135267382U, // BTR16mr
+ 1277199414U, // BTR16ri8
+ 1277199414U, // BTR16rr
+ 135332924U, // BTR32mi8
+ 135332924U, // BTR32mr
+ 1277199420U, // BTR32ri8
+ 1277199420U, // BTR32rr
+ 135365698U, // BTR64mi8
+ 135365698U, // BTR64mr
+ 1277199426U, // BTR64ri8
+ 1277199426U, // BTR64rr
+ 135267400U, // BTS16mi8
+ 135267400U, // BTS16mr
+ 1277199432U, // BTS16ri8
+ 1277199432U, // BTS16rr
+ 135332942U, // BTS32mi8
+ 135332942U, // BTS32mr
+ 1277199438U, // BTS32ri8
+ 1277199438U, // BTS32rr
+ 135365716U, // BTS64mi8
+ 135365716U, // BTS64mr
+ 1277199444U, // BTS64ri8
+ 1277199444U, // BTS64rr
+ 945816666U, // CALL32m
+ 73401434U, // CALL32r
+ 1476396129U, // CALL64m
+ 1549796457U, // CALL64pcrel32
+ 73401441U, // CALL64r
+ 1549796464U, // CALLpcrel32
+ 1142U, // CBW
+ 1147U, // CDQ
+ 1152U, // CDQE
+ 1157U, // CHS_F
0U, // CHS_Fp32
0U, // CHS_Fp64
0U, // CHS_Fp80
- 1150U, // CLC
- 1154U, // CLD
- 1610613894U, // CLFLUSH
- 1167U, // CLI
- 1171U, // CLTS
- 1176U, // CMC
- 270566556U, // CMOVA16rm
- 203457692U, // CMOVA16rr
- 337675428U, // CMOVA32rm
- 203457700U, // CMOVA32rr
- 404784300U, // CMOVA64rm
- 203457708U, // CMOVA64rr
- 270566580U, // CMOVAE16rm
- 203457716U, // CMOVAE16rr
- 337675453U, // CMOVAE32rm
- 203457725U, // CMOVAE32rr
- 404784326U, // CMOVAE64rm
- 203457734U, // CMOVAE64rr
- 270566607U, // CMOVB16rm
- 203457743U, // CMOVB16rr
- 337675479U, // CMOVB32rm
- 203457751U, // CMOVB32rr
- 404784351U, // CMOVB64rm
- 203457759U, // CMOVB64rr
- 270566631U, // CMOVBE16rm
- 203457767U, // CMOVBE16rr
- 337675504U, // CMOVBE32rm
- 203457776U, // CMOVBE32rr
- 404784377U, // CMOVBE64rm
- 203457785U, // CMOVBE64rr
- 75498754U, // CMOVBE_F
+ 1162U, // CLC
+ 1166U, // CLD
+ 1610613906U, // CLFLUSH
+ 1179U, // CLI
+ 1183U, // CLTS
+ 1188U, // CMC
+ 270566568U, // CMOVA16rm
+ 203457704U, // CMOVA16rr
+ 337675440U, // CMOVA32rm
+ 203457712U, // CMOVA32rr
+ 404784312U, // CMOVA64rm
+ 203457720U, // CMOVA64rr
+ 270566592U, // CMOVAE16rm
+ 203457728U, // CMOVAE16rr
+ 337675465U, // CMOVAE32rm
+ 203457737U, // CMOVAE32rr
+ 404784338U, // CMOVAE64rm
+ 203457746U, // CMOVAE64rr
+ 270566619U, // CMOVB16rm
+ 203457755U, // CMOVB16rr
+ 337675491U, // CMOVB32rm
+ 203457763U, // CMOVB32rr
+ 404784363U, // CMOVB64rm
+ 203457771U, // CMOVB64rr
+ 270566643U, // CMOVBE16rm
+ 203457779U, // CMOVBE16rr
+ 337675516U, // CMOVBE32rm
+ 203457788U, // CMOVBE32rr
+ 404784389U, // CMOVBE64rm
+ 203457797U, // CMOVBE64rr
+ 75498766U, // CMOVBE_F
0U, // CMOVBE_Fp32
0U, // CMOVBE_Fp64
0U, // CMOVBE_Fp80
- 75498763U, // CMOVB_F
+ 75498775U, // CMOVB_F
0U, // CMOVB_Fp32
0U, // CMOVB_Fp64
0U, // CMOVB_Fp80
- 270566675U, // CMOVE16rm
- 203457811U, // CMOVE16rr
- 337675547U, // CMOVE32rm
- 203457819U, // CMOVE32rr
- 404784419U, // CMOVE64rm
- 203457827U, // CMOVE64rr
- 75498795U, // CMOVE_F
+ 270566687U, // CMOVE16rm
+ 203457823U, // CMOVE16rr
+ 337675559U, // CMOVE32rm
+ 203457831U, // CMOVE32rr
+ 404784431U, // CMOVE64rm
+ 203457839U, // CMOVE64rr
+ 75498807U, // CMOVE_F
0U, // CMOVE_Fp32
0U, // CMOVE_Fp64
0U, // CMOVE_Fp80
- 270566707U, // CMOVG16rm
- 203457843U, // CMOVG16rr
- 337675579U, // CMOVG32rm
- 203457851U, // CMOVG32rr
- 404784451U, // CMOVG64rm
- 203457859U, // CMOVG64rr
- 270566731U, // CMOVGE16rm
- 203457867U, // CMOVGE16rr
- 337675604U, // CMOVGE32rm
- 203457876U, // CMOVGE32rr
- 404784477U, // CMOVGE64rm
- 203457885U, // CMOVGE64rr
- 270566758U, // CMOVL16rm
- 203457894U, // CMOVL16rr
- 337675630U, // CMOVL32rm
- 203457902U, // CMOVL32rr
- 404784502U, // CMOVL64rm
- 203457910U, // CMOVL64rr
- 270566782U, // CMOVLE16rm
- 203457918U, // CMOVLE16rr
- 337675655U, // CMOVLE32rm
- 203457927U, // CMOVLE32rr
- 404784528U, // CMOVLE64rm
- 203457936U, // CMOVLE64rr
- 75498905U, // CMOVNBE_F
+ 270566719U, // CMOVG16rm
+ 203457855U, // CMOVG16rr
+ 337675591U, // CMOVG32rm
+ 203457863U, // CMOVG32rr
+ 404784463U, // CMOVG64rm
+ 203457871U, // CMOVG64rr
+ 270566743U, // CMOVGE16rm
+ 203457879U, // CMOVGE16rr
+ 337675616U, // CMOVGE32rm
+ 203457888U, // CMOVGE32rr
+ 404784489U, // CMOVGE64rm
+ 203457897U, // CMOVGE64rr
+ 270566770U, // CMOVL16rm
+ 203457906U, // CMOVL16rr
+ 337675642U, // CMOVL32rm
+ 203457914U, // CMOVL32rr
+ 404784514U, // CMOVL64rm
+ 203457922U, // CMOVL64rr
+ 270566794U, // CMOVLE16rm
+ 203457930U, // CMOVLE16rr
+ 337675667U, // CMOVLE32rm
+ 203457939U, // CMOVLE32rr
+ 404784540U, // CMOVLE64rm
+ 203457948U, // CMOVLE64rr
+ 75498917U, // CMOVNBE_F
0U, // CMOVNBE_Fp32
0U, // CMOVNBE_Fp64
0U, // CMOVNBE_Fp80
- 75498915U, // CMOVNB_F
+ 75498927U, // CMOVNB_F
0U, // CMOVNB_Fp32
0U, // CMOVNB_Fp64
0U, // CMOVNB_Fp80
- 270566828U, // CMOVNE16rm
- 203457964U, // CMOVNE16rr
- 337675701U, // CMOVNE32rm
- 203457973U, // CMOVNE32rr
- 404784574U, // CMOVNE64rm
- 203457982U, // CMOVNE64rr
- 75498951U, // CMOVNE_F
+ 270566840U, // CMOVNE16rm
+ 203457976U, // CMOVNE16rr
+ 337675713U, // CMOVNE32rm
+ 203457985U, // CMOVNE32rr
+ 404784586U, // CMOVNE64rm
+ 203457994U, // CMOVNE64rr
+ 75498963U, // CMOVNE_F
0U, // CMOVNE_Fp32
0U, // CMOVNE_Fp64
0U, // CMOVNE_Fp80
- 270566864U, // CMOVNO16rm
- 203458000U, // CMOVNO16rr
- 337675737U, // CMOVNO32rm
- 203458009U, // CMOVNO32rr
- 404784610U, // CMOVNO64rm
- 203458018U, // CMOVNO64rr
- 270566891U, // CMOVNP16rm
- 203458027U, // CMOVNP16rr
- 337675764U, // CMOVNP32rm
- 203458036U, // CMOVNP32rr
- 404784637U, // CMOVNP64rm
- 203458045U, // CMOVNP64rr
- 75499014U, // CMOVNP_F
+ 270566876U, // CMOVNO16rm
+ 203458012U, // CMOVNO16rr
+ 337675749U, // CMOVNO32rm
+ 203458021U, // CMOVNO32rr
+ 404784622U, // CMOVNO64rm
+ 203458030U, // CMOVNO64rr
+ 270566903U, // CMOVNP16rm
+ 203458039U, // CMOVNP16rr
+ 337675776U, // CMOVNP32rm
+ 203458048U, // CMOVNP32rr
+ 404784649U, // CMOVNP64rm
+ 203458057U, // CMOVNP64rr
+ 75499026U, // CMOVNP_F
0U, // CMOVNP_Fp32
0U, // CMOVNP_Fp64
0U, // CMOVNP_Fp80
- 270566927U, // CMOVNS16rm
- 203458063U, // CMOVNS16rr
- 337675800U, // CMOVNS32rm
- 203458072U, // CMOVNS32rr
- 404784673U, // CMOVNS64rm
- 203458081U, // CMOVNS64rr
- 270566954U, // CMOVO16rm
- 203458090U, // CMOVO16rr
- 337675826U, // CMOVO32rm
- 203458098U, // CMOVO32rr
- 404784698U, // CMOVO64rm
- 203458106U, // CMOVO64rr
- 270566978U, // CMOVP16rm
- 203458114U, // CMOVP16rr
- 337675850U, // CMOVP32rm
- 203458122U, // CMOVP32rr
- 404784722U, // CMOVP64rm
- 203458130U, // CMOVP64rr
- 75499098U, // CMOVP_F
+ 270566939U, // CMOVNS16rm
+ 203458075U, // CMOVNS16rr
+ 337675812U, // CMOVNS32rm
+ 203458084U, // CMOVNS32rr
+ 404784685U, // CMOVNS64rm
+ 203458093U, // CMOVNS64rr
+ 270566966U, // CMOVO16rm
+ 203458102U, // CMOVO16rr
+ 337675838U, // CMOVO32rm
+ 203458110U, // CMOVO32rr
+ 404784710U, // CMOVO64rm
+ 203458118U, // CMOVO64rr
+ 270566990U, // CMOVP16rm
+ 203458126U, // CMOVP16rr
+ 337675862U, // CMOVP32rm
+ 203458134U, // CMOVP32rr
+ 404784734U, // CMOVP64rm
+ 203458142U, // CMOVP64rr
+ 75499110U, // CMOVP_F
0U, // CMOVP_Fp32
0U, // CMOVP_Fp64
0U, // CMOVP_Fp80
- 270567011U, // CMOVS16rm
- 203458147U, // CMOVS16rr
- 337675883U, // CMOVS32rm
- 203458155U, // CMOVS32rr
- 404784755U, // CMOVS64rm
- 203458163U, // CMOVS64rr
- 1659U, // CMOV_FR32
- 1678U, // CMOV_FR64
- 1697U, // CMOV_GR8
- 1715U, // CMOV_V1I64
- 1735U, // CMOV_V2F64
- 1755U, // CMOV_V2I64
- 1775U, // CMOV_V4F32
- 67110659U, // CMP16i16
- 135268099U, // CMP16mi
- 135268099U, // CMP16mi8
- 135268099U, // CMP16mr
- 1277200131U, // CMP16mrmrr
- 1277200131U, // CMP16ri
- 1277200131U, // CMP16ri8
- 1207961347U, // CMP16rm
- 1277200131U, // CMP16rr
- 70256393U, // CMP32i32
- 135333641U, // CMP32mi
- 135333641U, // CMP32mi8
- 135333641U, // CMP32mr
- 1277200137U, // CMP32mrmrr
- 1277200137U, // CMP32ri
- 1277200137U, // CMP32ri8
- 1342179081U, // CMP32rm
- 1277200137U, // CMP32rr
- 71304975U, // CMP64i32
- 135366415U, // CMP64mi32
- 135366415U, // CMP64mi8
- 135366415U, // CMP64mr
- 1277200143U, // CMP64mrmrr
- 1277200143U, // CMP64ri32
- 1277200143U, // CMP64ri8
- 1409287951U, // CMP64rm
- 1277200143U, // CMP64rr
- 72353557U, // CMP8i8
- 135399189U, // CMP8mi
- 135399189U, // CMP8mr
- 1277200149U, // CMP8mrmrr
- 1277200149U, // CMP8ri
- 1684014869U, // CMP8rm
- 1277200149U, // CMP8rr
- 1754433307U, // CMPPDrmi
- 1821574939U, // CMPPDrri
- 1755481883U, // CMPPSrmi
- 1822623515U, // CMPPSrri
- 1823U, // CMPS16
- 1829U, // CMPS32
- 1835U, // CMPS64
- 1841U, // CMPS8
- 1756595995U, // CMPSDrm
- 1823672091U, // CMPSDrr
- 1757677339U, // CMPSSrm
- 1824720667U, // CMPSSrr
- 1879050039U, // CMPXCHG16B
- 135268163U, // CMPXCHG16rm
- 1277200195U, // CMPXCHG16rr
- 135333709U, // CMPXCHG32rm
- 1277200205U, // CMPXCHG32rr
- 135366487U, // CMPXCHG64rm
- 1277200215U, // CMPXCHG64rr
- 1476396897U, // CMPXCHG8B
- 135399276U, // CMPXCHG8rm
- 1277200236U, // CMPXCHG8rr
- 1946158966U, // COMISDrm
- 1277200246U, // COMISDrr
- 1946158974U, // COMISSrm
- 1277200254U, // COMISSrr
- 73402246U, // COMP_FST0r
- 75499405U, // COM_FIPr
- 75499413U, // COM_FIr
- 73402268U, // COM_FST0r
- 1954U, // COS_F
+ 270567023U, // CMOVS16rm
+ 203458159U, // CMOVS16rr
+ 337675895U, // CMOVS32rm
+ 203458167U, // CMOVS32rr
+ 404784767U, // CMOVS64rm
+ 203458175U, // CMOVS64rr
+ 1671U, // CMOV_FR32
+ 1690U, // CMOV_FR64
+ 1709U, // CMOV_GR8
+ 1727U, // CMOV_V1I64
+ 1747U, // CMOV_V2F64
+ 1767U, // CMOV_V2I64
+ 1787U, // CMOV_V4F32
+ 67110671U, // CMP16i16
+ 135268111U, // CMP16mi
+ 135268111U, // CMP16mi8
+ 135268111U, // CMP16mr
+ 1277200143U, // CMP16mrmrr
+ 1277200143U, // CMP16ri
+ 1277200143U, // CMP16ri8
+ 1207961359U, // CMP16rm
+ 1277200143U, // CMP16rr
+ 70256405U, // CMP32i32
+ 135333653U, // CMP32mi
+ 135333653U, // CMP32mi8
+ 135333653U, // CMP32mr
+ 1277200149U, // CMP32mrmrr
+ 1277200149U, // CMP32ri
+ 1277200149U, // CMP32ri8
+ 1342179093U, // CMP32rm
+ 1277200149U, // CMP32rr
+ 71304987U, // CMP64i32
+ 135366427U, // CMP64mi32
+ 135366427U, // CMP64mi8
+ 135366427U, // CMP64mr
+ 1277200155U, // CMP64mrmrr
+ 1277200155U, // CMP64ri32
+ 1277200155U, // CMP64ri8
+ 1409287963U, // CMP64rm
+ 1277200155U, // CMP64rr
+ 72353569U, // CMP8i8
+ 135399201U, // CMP8mi
+ 135399201U, // CMP8mr
+ 1277200161U, // CMP8mrmrr
+ 1277200161U, // CMP8ri
+ 1684014881U, // CMP8rm
+ 1277200161U, // CMP8rr
+ 1754433319U, // CMPPDrmi
+ 1821574951U, // CMPPDrri
+ 1755481895U, // CMPPSrmi
+ 1822623527U, // CMPPSrri
+ 1835U, // CMPS16
+ 1841U, // CMPS32
+ 1847U, // CMPS64
+ 1853U, // CMPS8
+ 1756596007U, // CMPSDrm
+ 1823672103U, // CMPSDrr
+ 1757677351U, // CMPSSrm
+ 1824720679U, // CMPSSrr
+ 1879050051U, // CMPXCHG16B
+ 135268175U, // CMPXCHG16rm
+ 1277200207U, // CMPXCHG16rr
+ 135333721U, // CMPXCHG32rm
+ 1277200217U, // CMPXCHG32rr
+ 135366499U, // CMPXCHG64rm
+ 1277200227U, // CMPXCHG64rr
+ 1476396909U, // CMPXCHG8B
+ 135399288U, // CMPXCHG8rm
+ 1277200248U, // CMPXCHG8rr
+ 1946158978U, // COMISDrm
+ 1277200258U, // COMISDrr
+ 1946158986U, // COMISSrm
+ 1277200266U, // COMISSrr
+ 73402258U, // COMP_FST0r
+ 75499417U, // COM_FIPr
+ 75499425U, // COM_FIr
+ 73402280U, // COM_FST0r
+ 1966U, // COS_F
0U, // COS_Fp32
0U, // COS_Fp64
0U, // COS_Fp80
- 1959U, // CPUID
- 1965U, // CQO
- 282101682U, // CRC32m16
- 349210546U, // CRC32m32
- 483428274U, // CRC32m8
- 214992818U, // CRC32r16
- 214992818U, // CRC32r32
- 214992818U, // CRC32r8
- 416319410U, // CRC64m64
- 214992818U, // CRC64r64
- 1946159034U, // CVTDQ2PDrm
- 1277200314U, // CVTDQ2PDrr
- 1946159044U, // CVTDQ2PSrm
- 1277200324U, // CVTDQ2PSrr
- 1946159054U, // CVTPD2DQrm
- 1277200334U, // CVTPD2DQrr
- 1946159064U, // CVTPD2PSrm
- 1277200344U, // CVTPD2PSrr
- 1946159074U, // CVTPS2DQrm
- 1277200354U, // CVTPS2DQrr
- 2013267948U, // CVTPS2PDrm
- 1277200364U, // CVTPS2PDrr
- 2013267958U, // CVTSD2SI64rm
- 1277200374U, // CVTSD2SI64rr
- 2013267969U, // CVTSD2SSrm
- 1277200385U, // CVTSD2SSrr
- 1409288203U, // CVTSI2SD64rm
- 1277200395U, // CVTSI2SD64rr
- 1342179350U, // CVTSI2SDrm
- 1277200406U, // CVTSI2SDrr
- 1409288224U, // CVTSI2SS64rm
- 1277200416U, // CVTSI2SS64rr
- 1342179371U, // CVTSI2SSrm
- 1277200427U, // CVTSI2SSrr
- 2080376885U, // CVTSS2SDrm
- 1277200437U, // CVTSS2SDrr
- 2080376895U, // CVTSS2SI64rm
- 1277200447U, // CVTSS2SI64rr
- 2080376906U, // CVTSS2SIrm
- 1277200458U, // CVTSS2SIrr
- 1946159189U, // CVTTPS2DQrm
- 1277200469U, // CVTTPS2DQrr
- 2013268064U, // CVTTSD2SI64rm
- 1277200480U, // CVTTSD2SI64rr
- 2013268076U, // CVTTSD2SIrm
- 1277200492U, // CVTTSD2SIrr
- 2080376951U, // CVTTSS2SI64rm
- 1277200503U, // CVTTSS2SI64rr
- 2080376963U, // CVTTSS2SIrm
- 1277200515U, // CVTTSS2SIrr
- 2190U, // CWD
- 2195U, // CWDE
- 872417432U, // DEC16m
- 73402520U, // DEC16r
- 945817758U, // DEC32m
- 73402526U, // DEC32r
- 872417432U, // DEC64_16m
- 73402520U, // DEC64_16r
- 945817758U, // DEC64_32m
- 73402526U, // DEC64_32r
- 1476397220U, // DEC64m
- 73402532U, // DEC64r
- 1610614954U, // DEC8m
- 73402538U, // DEC8r
- 872417456U, // DIV16m
- 73402544U, // DIV16r
- 945817782U, // DIV32m
- 73402550U, // DIV32r
- 1476397244U, // DIV64m
- 73402556U, // DIV64r
- 1610614978U, // DIV8m
- 73402562U, // DIV8r
- 536873160U, // DIVPDrm
- 203458760U, // DIVPDrr
- 536873167U, // DIVPSrm
- 203458767U, // DIVPSrr
- 738199766U, // DIVR_F32m
- 805308638U, // DIVR_F64m
- 872417510U, // DIVR_FI16m
- 945817839U, // DIVR_FI32m
- 73402616U, // DIVR_FPrST0
- 73402623U, // DIVR_FST0r
+ 1971U, // CPUID
+ 1977U, // CQO
+ 282101694U, // CRC32m16
+ 349210558U, // CRC32m32
+ 483428286U, // CRC32m8
+ 214992830U, // CRC32r16
+ 214992830U, // CRC32r32
+ 214992830U, // CRC32r8
+ 416319422U, // CRC64m64
+ 214992830U, // CRC64r64
+ 1946159046U, // CVTDQ2PDrm
+ 1277200326U, // CVTDQ2PDrr
+ 1946159056U, // CVTDQ2PSrm
+ 1277200336U, // CVTDQ2PSrr
+ 1946159066U, // CVTPD2DQrm
+ 1277200346U, // CVTPD2DQrr
+ 1946159076U, // CVTPD2PSrm
+ 1277200356U, // CVTPD2PSrr
+ 1946159086U, // CVTPS2DQrm
+ 1277200366U, // CVTPS2DQrr
+ 2013267960U, // CVTPS2PDrm
+ 1277200376U, // CVTPS2PDrr
+ 2013267970U, // CVTSD2SI64rm
+ 1277200386U, // CVTSD2SI64rr
+ 2013267981U, // CVTSD2SSrm
+ 1277200397U, // CVTSD2SSrr
+ 1409288215U, // CVTSI2SD64rm
+ 1277200407U, // CVTSI2SD64rr
+ 1342179362U, // CVTSI2SDrm
+ 1277200418U, // CVTSI2SDrr
+ 1409288236U, // CVTSI2SS64rm
+ 1277200428U, // CVTSI2SS64rr
+ 1342179383U, // CVTSI2SSrm
+ 1277200439U, // CVTSI2SSrr
+ 2080376897U, // CVTSS2SDrm
+ 1277200449U, // CVTSS2SDrr
+ 2080376907U, // CVTSS2SI64rm
+ 1277200459U, // CVTSS2SI64rr
+ 2080376918U, // CVTSS2SIrm
+ 1277200470U, // CVTSS2SIrr
+ 1946159201U, // CVTTPS2DQrm
+ 1277200481U, // CVTTPS2DQrr
+ 2013268076U, // CVTTSD2SI64rm
+ 1277200492U, // CVTTSD2SI64rr
+ 2013268088U, // CVTTSD2SIrm
+ 1277200504U, // CVTTSD2SIrr
+ 2080376963U, // CVTTSS2SI64rm
+ 1277200515U, // CVTTSS2SI64rr
+ 2080376975U, // CVTTSS2SIrm
+ 1277200527U, // CVTTSS2SIrr
+ 2202U, // CWD
+ 2207U, // CWDE
+ 872417444U, // DEC16m
+ 73402532U, // DEC16r
+ 945817770U, // DEC32m
+ 73402538U, // DEC32r
+ 872417444U, // DEC64_16m
+ 73402532U, // DEC64_16r
+ 945817770U, // DEC64_32m
+ 73402538U, // DEC64_32r
+ 1476397232U, // DEC64m
+ 73402544U, // DEC64r
+ 1610614966U, // DEC8m
+ 73402550U, // DEC8r
+ 872417468U, // DIV16m
+ 73402556U, // DIV16r
+ 945817794U, // DIV32m
+ 73402562U, // DIV32r
+ 1476397256U, // DIV64m
+ 73402568U, // DIV64r
+ 1610614990U, // DIV8m
+ 73402574U, // DIV8r
+ 536873172U, // DIVPDrm
+ 203458772U, // DIVPDrr
+ 536873179U, // DIVPSrm
+ 203458779U, // DIVPSrr
+ 738199778U, // DIVR_F32m
+ 805308650U, // DIVR_F64m
+ 872417522U, // DIVR_FI16m
+ 945817851U, // DIVR_FI32m
+ 73402628U, // DIVR_FPrST0
+ 73402635U, // DIVR_FST0r
0U, // DIVR_Fp32m
0U, // DIVR_Fp64m
0U, // DIVR_Fp64m32
@@ -596,21 +597,21 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // DIVR_FpI32m32
0U, // DIVR_FpI32m64
0U, // DIVR_FpI32m80
- 73402630U, // DIVR_FrST0
- 603982100U, // DIVSDrm
- 603982100U, // DIVSDrm_Int
- 203458836U, // DIVSDrr
- 203458836U, // DIVSDrr_Int
- 671090971U, // DIVSSrm
- 671090971U, // DIVSSrm_Int
- 203458843U, // DIVSSrr
- 203458843U, // DIVSSrr_Int
- 738199842U, // DIV_F32m
- 805308713U, // DIV_F64m
- 872417584U, // DIV_FI16m
- 945817912U, // DIV_FI32m
- 73402688U, // DIV_FPrST0
- 73402696U, // DIV_FST0r
+ 73402642U, // DIVR_FrST0
+ 603982112U, // DIVSDrm
+ 603982112U, // DIVSDrm_Int
+ 203458848U, // DIVSDrr
+ 203458848U, // DIVSDrr_Int
+ 671090983U, // DIVSSrm
+ 671090983U, // DIVSSrm_Int
+ 203458855U, // DIVSSrr
+ 203458855U, // DIVSSrr_Int
+ 738199854U, // DIV_F32m
+ 805308725U, // DIV_F64m
+ 872417596U, // DIV_FI16m
+ 945817924U, // DIV_FI32m
+ 73402700U, // DIV_FPrST0
+ 73402708U, // DIV_FST0r
0U, // DIV_Fp32
0U, // DIV_Fp32m
0U, // DIV_Fp64
@@ -625,82 +626,82 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // DIV_FpI32m32
0U, // DIV_FpI32m64
0U, // DIV_FpI32m80
- 73402702U, // DIV_FrST0
- 1013975389U, // DPPDrmi
- 1073744221U, // DPPDrri
- 1013975395U, // DPPSrmi
- 1073744227U, // DPPSrri
- 73402729U, // EH_RETURN
- 73402729U, // EH_RETURN64
- 68454784U, // ENTER
- 2162493831U, // EXTRACTPSmr
- 215320967U, // EXTRACTPSrr
- 2450U, // F2XM1
- 68454808U, // FARCALL16i
- 2214594976U, // FARCALL16m
- 68454825U, // FARCALL32i
- 2214594993U, // FARCALL32m
- 2214595002U, // FARCALL64
- 68454851U, // FARJMP16i
- 2214595018U, // FARJMP16m
- 68454866U, // FARJMP32i
- 2214595033U, // FARJMP32m
- 2214595041U, // FARJMP64
- 738200041U, // FBLDm
- 738200047U, // FBSTPm
- 738200054U, // FCOM32m
- 805308925U, // FCOM64m
- 738200069U, // FCOMP32m
- 805308941U, // FCOMP64m
- 2582U, // FCOMPP
- 2589U, // FDECSTP
- 73402917U, // FFREE
- 872417836U, // FICOM16m
- 945818164U, // FICOM32m
- 872417852U, // FICOMP16m
- 945818181U, // FICOMP32m
- 2638U, // FINCSTP
- 945818198U, // FISTTP32m
- 872417887U, // FLDCW16m
- 738200166U, // FLDENVm
- 2670U, // FLDL2E
- 2677U, // FLDL2T
- 2684U, // FLDLG2
- 2691U, // FLDLN2
- 2698U, // FLDPI
- 2704U, // FNCLEX
- 2711U, // FNINIT
- 2718U, // FNOP
- 872417955U, // FNSTCW16m
- 2731U, // FNSTSW8r
- 738200246U, // FNSTSWm
- 2750U, // FP32_TO_INT16_IN_MEM
- 2781U, // FP32_TO_INT32_IN_MEM
- 2812U, // FP32_TO_INT64_IN_MEM
- 2843U, // FP64_TO_INT16_IN_MEM
- 2874U, // FP64_TO_INT32_IN_MEM
- 2905U, // FP64_TO_INT64_IN_MEM
- 2936U, // FP80_TO_INT16_IN_MEM
- 2967U, // FP80_TO_INT32_IN_MEM
- 2998U, // FP80_TO_INT64_IN_MEM
- 3029U, // FPATAN
- 3036U, // FPREM
- 3042U, // FPREM1
- 3049U, // FPTAN
- 3055U, // FP_REG_KILL
- 3069U, // FRNDINT
- 738200581U, // FRSTORm
- 738200589U, // FSAVEm
- 3093U, // FSCALE
- 3100U, // FSINCOS
- 738200612U, // FSTENVm
- 1342180397U, // FS_MOV32rm
- 3127U, // FXAM
- 2214595644U, // FXRSTOR
- 2214595653U, // FXSAVE
- 3149U, // FXTRACT
- 3157U, // FYL2X
- 3163U, // FYL2XP1
+ 73402714U, // DIV_FrST0
+ 1013975401U, // DPPDrmi
+ 1073744233U, // DPPDrri
+ 1013975407U, // DPPSrmi
+ 1073744239U, // DPPSrri
+ 73402741U, // EH_RETURN
+ 73402741U, // EH_RETURN64
+ 68454796U, // ENTER
+ 2162493843U, // EXTRACTPSmr
+ 215320979U, // EXTRACTPSrr
+ 2462U, // F2XM1
+ 68454820U, // FARCALL16i
+ 2214594988U, // FARCALL16m
+ 68454837U, // FARCALL32i
+ 2214595005U, // FARCALL32m
+ 2214595014U, // FARCALL64
+ 68454863U, // FARJMP16i
+ 2214595030U, // FARJMP16m
+ 68454878U, // FARJMP32i
+ 2214595045U, // FARJMP32m
+ 2214595053U, // FARJMP64
+ 738200053U, // FBLDm
+ 738200059U, // FBSTPm
+ 738200066U, // FCOM32m
+ 805308937U, // FCOM64m
+ 738200081U, // FCOMP32m
+ 805308953U, // FCOMP64m
+ 2594U, // FCOMPP
+ 2601U, // FDECSTP
+ 73402929U, // FFREE
+ 872417848U, // FICOM16m
+ 945818176U, // FICOM32m
+ 872417864U, // FICOMP16m
+ 945818193U, // FICOMP32m
+ 2650U, // FINCSTP
+ 945818210U, // FISTTP32m
+ 872417899U, // FLDCW16m
+ 738200178U, // FLDENVm
+ 2682U, // FLDL2E
+ 2689U, // FLDL2T
+ 2696U, // FLDLG2
+ 2703U, // FLDLN2
+ 2710U, // FLDPI
+ 2716U, // FNCLEX
+ 2723U, // FNINIT
+ 2730U, // FNOP
+ 872417967U, // FNSTCW16m
+ 2743U, // FNSTSW8r
+ 738200258U, // FNSTSWm
+ 2762U, // FP32_TO_INT16_IN_MEM
+ 2793U, // FP32_TO_INT32_IN_MEM
+ 2824U, // FP32_TO_INT64_IN_MEM
+ 2855U, // FP64_TO_INT16_IN_MEM
+ 2886U, // FP64_TO_INT32_IN_MEM
+ 2917U, // FP64_TO_INT64_IN_MEM
+ 2948U, // FP80_TO_INT16_IN_MEM
+ 2979U, // FP80_TO_INT32_IN_MEM
+ 3010U, // FP80_TO_INT64_IN_MEM
+ 3041U, // FPATAN
+ 3048U, // FPREM
+ 3054U, // FPREM1
+ 3061U, // FPTAN
+ 3067U, // FP_REG_KILL
+ 3081U, // FRNDINT
+ 738200593U, // FRSTORm
+ 738200601U, // FSAVEm
+ 3105U, // FSCALE
+ 3112U, // FSINCOS
+ 738200624U, // FSTENVm
+ 1342180409U, // FS_MOV32rm
+ 3139U, // FXAM
+ 2214595656U, // FXRSTOR
+ 2214595665U, // FXSAVE
+ 3161U, // FXTRACT
+ 3169U, // FYL2X
+ 3175U, // FYL2XP1
0U, // FpGET_ST0_32
0U, // FpGET_ST0_64
0U, // FpGET_ST0_80
@@ -713,49 +714,49 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // FpSET_ST1_32
0U, // FpSET_ST1_64
0U, // FpSET_ST1_80
- 536871129U, // FsANDNPDrm
- 203456729U, // FsANDNPDrr
- 536871137U, // FsANDNPSrm
- 203456737U, // FsANDNPSrr
- 536871145U, // FsANDPDrm
- 203456745U, // FsANDPDrr
- 536871152U, // FsANDPSrm
- 203456752U, // FsANDPSrr
- 68553827U, // FsFLD0SD
- 68553827U, // FsFLD0SS
- 1946160233U, // FsMOVAPDrm
- 1277201513U, // FsMOVAPDrr
- 1946160241U, // FsMOVAPSrm
- 1277201521U, // FsMOVAPSrr
- 536874105U, // FsORPDrm
- 203459705U, // FsORPDrr
- 536874111U, // FsORPSrm
- 203459711U, // FsORPSrr
- 536874117U, // FsXORPDrm
- 203459717U, // FsXORPDrr
- 536874124U, // FsXORPSrm
- 203459724U, // FsXORPSrr
- 1342180499U, // GS_MOV32rm
- 536874141U, // HADDPDrm
- 203459741U, // HADDPDrr
- 536874149U, // HADDPSrm
- 203459749U, // HADDPSrr
- 3245U, // HLT
- 536874161U, // HSUBPDrm
- 203459761U, // HSUBPDrr
- 536874169U, // HSUBPSrm
- 203459769U, // HSUBPSrr
- 872418497U, // IDIV16m
- 73403585U, // IDIV16r
- 945818824U, // IDIV32m
- 73403592U, // IDIV32r
- 1476398287U, // IDIV64m
- 73403599U, // IDIV64r
- 1610616022U, // IDIV8m
- 73403606U, // IDIV8r
- 872418525U, // ILD_F16m
- 945818852U, // ILD_F32m
- 1476398315U, // ILD_F64m
+ 536871141U, // FsANDNPDrm
+ 203456741U, // FsANDNPDrr
+ 536871149U, // FsANDNPSrm
+ 203456749U, // FsANDNPSrr
+ 536871157U, // FsANDPDrm
+ 203456757U, // FsANDPDrr
+ 536871164U, // FsANDPSrm
+ 203456764U, // FsANDPSrr
+ 68553839U, // FsFLD0SD
+ 68553839U, // FsFLD0SS
+ 1946160245U, // FsMOVAPDrm
+ 1277201525U, // FsMOVAPDrr
+ 1946160253U, // FsMOVAPSrm
+ 1277201533U, // FsMOVAPSrr
+ 536874117U, // FsORPDrm
+ 203459717U, // FsORPDrr
+ 536874123U, // FsORPSrm
+ 203459723U, // FsORPSrr
+ 536874129U, // FsXORPDrm
+ 203459729U, // FsXORPDrr
+ 536874136U, // FsXORPSrm
+ 203459736U, // FsXORPSrr
+ 1342180511U, // GS_MOV32rm
+ 536874153U, // HADDPDrm
+ 203459753U, // HADDPDrr
+ 536874161U, // HADDPSrm
+ 203459761U, // HADDPSrr
+ 3257U, // HLT
+ 536874173U, // HSUBPDrm
+ 203459773U, // HSUBPDrr
+ 536874181U, // HSUBPSrm
+ 203459781U, // HSUBPSrr
+ 872418509U, // IDIV16m
+ 73403597U, // IDIV16r
+ 945818836U, // IDIV32m
+ 73403604U, // IDIV32r
+ 1476398299U, // IDIV64m
+ 73403611U, // IDIV64r
+ 1610616034U, // IDIV8m
+ 73403618U, // IDIV8r
+ 872418537U, // ILD_F16m
+ 945818864U, // ILD_F32m
+ 1476398327U, // ILD_F64m
0U, // ILD_Fp16m32
0U, // ILD_Fp16m64
0U, // ILD_Fp16m80
@@ -765,67 +766,67 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ILD_Fp64m32
0U, // ILD_Fp64m64
0U, // ILD_Fp64m80
- 872418547U, // IMUL16m
- 73403635U, // IMUL16r
- 270568691U, // IMUL16rm
- 2163215603U, // IMUL16rmi
- 2163215603U, // IMUL16rmi8
- 203459827U, // IMUL16rr
- 215321843U, // IMUL16rri
- 215321843U, // IMUL16rri8
- 945818874U, // IMUL32m
- 73403642U, // IMUL32r
- 337677562U, // IMUL32rm
- 2164264186U, // IMUL32rmi
- 2164264186U, // IMUL32rmi8
- 203459834U, // IMUL32rr
- 215321850U, // IMUL32rri
- 215321850U, // IMUL32rri8
- 1476398337U, // IMUL64m
- 73403649U, // IMUL64r
- 404786433U, // IMUL64rm
- 2165312769U, // IMUL64rmi32
- 2165312769U, // IMUL64rmi8
- 203459841U, // IMUL64rr
- 215321857U, // IMUL64rri32
- 215321857U, // IMUL64rri8
- 1610616072U, // IMUL8m
- 73403656U, // IMUL8r
- 3343U, // IN16
- 67112212U, // IN16ri
- 3353U, // IN16rr
- 3366U, // IN32
- 70257963U, // IN32ri
- 3376U, // IN32rr
- 3390U, // IN8
- 72355139U, // IN8ri
- 3400U, // IN8rr
- 872418645U, // INC16m
- 73403733U, // INC16r
- 945818971U, // INC32m
- 73403739U, // INC32r
- 872418645U, // INC64_16m
- 73403733U, // INC64_16r
- 945818971U, // INC64_32m
- 73403739U, // INC64_32r
- 1476398433U, // INC64m
- 73403745U, // INC64r
- 1610616167U, // INC8m
- 73403751U, // INC8r
- 1025510765U, // INSERTPSrm
- 1073745261U, // INSERTPSrr
- 73403767U, // INT
- 3452U, // INT3
- 3458U, // INVD
- 3463U, // INVEPT
- 3470U, // INVLPG
- 3477U, // INVVPID
- 3485U, // IRET16
- 3491U, // IRET32
- 3497U, // IRET64
- 872418735U, // ISTT_FP16m
- 945818198U, // ISTT_FP32m
- 1476398520U, // ISTT_FP64m
+ 872418559U, // IMUL16m
+ 73403647U, // IMUL16r
+ 270568703U, // IMUL16rm
+ 2163215615U, // IMUL16rmi
+ 2163215615U, // IMUL16rmi8
+ 203459839U, // IMUL16rr
+ 215321855U, // IMUL16rri
+ 215321855U, // IMUL16rri8
+ 945818886U, // IMUL32m
+ 73403654U, // IMUL32r
+ 337677574U, // IMUL32rm
+ 2164264198U, // IMUL32rmi
+ 2164264198U, // IMUL32rmi8
+ 203459846U, // IMUL32rr
+ 215321862U, // IMUL32rri
+ 215321862U, // IMUL32rri8
+ 1476398349U, // IMUL64m
+ 73403661U, // IMUL64r
+ 404786445U, // IMUL64rm
+ 2165312781U, // IMUL64rmi32
+ 2165312781U, // IMUL64rmi8
+ 203459853U, // IMUL64rr
+ 215321869U, // IMUL64rri32
+ 215321869U, // IMUL64rri8
+ 1610616084U, // IMUL8m
+ 73403668U, // IMUL8r
+ 3355U, // IN16
+ 67112224U, // IN16ri
+ 3365U, // IN16rr
+ 3378U, // IN32
+ 70257975U, // IN32ri
+ 3388U, // IN32rr
+ 3402U, // IN8
+ 72355151U, // IN8ri
+ 3412U, // IN8rr
+ 872418657U, // INC16m
+ 73403745U, // INC16r
+ 945818983U, // INC32m
+ 73403751U, // INC32r
+ 872418657U, // INC64_16m
+ 73403745U, // INC64_16r
+ 945818983U, // INC64_32m
+ 73403751U, // INC64_32r
+ 1476398445U, // INC64m
+ 73403757U, // INC64r
+ 1610616179U, // INC8m
+ 73403763U, // INC8r
+ 1025510777U, // INSERTPSrm
+ 1073745273U, // INSERTPSrr
+ 73403779U, // INT
+ 3464U, // INT3
+ 3470U, // INVD
+ 3475U, // INVEPT
+ 3482U, // INVLPG
+ 3489U, // INVVPID
+ 3497U, // IRET16
+ 3503U, // IRET32
+ 3509U, // IRET64
+ 872418747U, // ISTT_FP16m
+ 945818210U, // ISTT_FP32m
+ 1476398532U, // ISTT_FP64m
0U, // ISTT_Fp16m32
0U, // ISTT_Fp16m64
0U, // ISTT_Fp16m80
@@ -835,11 +836,11 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ISTT_Fp64m32
0U, // ISTT_Fp64m64
0U, // ISTT_Fp64m80
- 872418754U, // IST_F16m
- 945819081U, // IST_F32m
- 872418768U, // IST_FP16m
- 945819096U, // IST_FP32m
- 1476398560U, // IST_FP64m
+ 872418766U, // IST_F16m
+ 945819093U, // IST_F32m
+ 872418780U, // IST_FP16m
+ 945819108U, // IST_FP32m
+ 1476398572U, // IST_FP64m
0U, // IST_Fp16m32
0U, // IST_Fp16m64
0U, // IST_Fp16m80
@@ -849,135 +850,135 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // IST_Fp64m32
0U, // IST_Fp64m64
0U, // IST_Fp64m80
- 1756595995U, // Int_CMPSDrm
- 1823672091U, // Int_CMPSDrr
- 1757677339U, // Int_CMPSSrm
- 1824720667U, // Int_CMPSSrr
- 1946158966U, // Int_COMISDrm
- 1277200246U, // Int_COMISDrr
- 1946158974U, // Int_COMISSrm
- 1277200254U, // Int_COMISSrr
- 1409288122U, // Int_CVTDQ2PDrm
- 1277200314U, // Int_CVTDQ2PDrr
- 2281703364U, // Int_CVTDQ2PSrm
- 1277200324U, // Int_CVTDQ2PSrr
- 1946159054U, // Int_CVTPD2DQrm
- 1277200334U, // Int_CVTPD2DQrr
- 1946160617U, // Int_CVTPD2PIrm
- 1277201897U, // Int_CVTPD2PIrr
- 1946159064U, // Int_CVTPD2PSrm
- 1277200344U, // Int_CVTPD2PSrr
- 1409289715U, // Int_CVTPI2PDrm
- 1277201907U, // Int_CVTPI2PDrr
- 404786685U, // Int_CVTPI2PSrm
- 203460093U, // Int_CVTPI2PSrr
- 1946159074U, // Int_CVTPS2DQrm
- 1277200354U, // Int_CVTPS2DQrr
- 2013267948U, // Int_CVTPS2PDrm
- 1277200364U, // Int_CVTPS2PDrr
- 2013269511U, // Int_CVTPS2PIrm
- 1277201927U, // Int_CVTPS2PIrr
- 1946159094U, // Int_CVTSD2SI64rm
- 1277200374U, // Int_CVTSD2SI64rr
- 1946160657U, // Int_CVTSD2SIrm
- 1277201937U, // Int_CVTSD2SIrr
- 603981825U, // Int_CVTSD2SSrm
- 203458561U, // Int_CVTSD2SSrr
- 404785163U, // Int_CVTSI2SD64rm
- 203458571U, // Int_CVTSI2SD64rr
- 337676310U, // Int_CVTSI2SDrm
- 203458582U, // Int_CVTSI2SDrr
- 404785184U, // Int_CVTSI2SS64rm
- 203458592U, // Int_CVTSI2SS64rr
- 337676331U, // Int_CVTSI2SSrm
- 203458603U, // Int_CVTSI2SSrr
- 671090741U, // Int_CVTSS2SDrm
- 203458613U, // Int_CVTSS2SDrr
- 2080376895U, // Int_CVTSS2SI64rm
- 1277200447U, // Int_CVTSS2SI64rr
- 2080378395U, // Int_CVTSS2SIrm
- 1277201947U, // Int_CVTSS2SIrr
- 1946160677U, // Int_CVTTPD2DQrm
- 1277201957U, // Int_CVTTPD2DQrr
- 1946160688U, // Int_CVTTPD2PIrm
- 1277201968U, // Int_CVTTPD2PIrr
- 1946159189U, // Int_CVTTPS2DQrm
- 1277200469U, // Int_CVTTPS2DQrr
- 2013269563U, // Int_CVTTPS2PIrm
- 1277201979U, // Int_CVTTPS2PIrr
- 1946159200U, // Int_CVTTSD2SI64rm
- 1277200480U, // Int_CVTTSD2SI64rr
- 1946159212U, // Int_CVTTSD2SIrm
- 1277200492U, // Int_CVTTSD2SIrr
- 2080376951U, // Int_CVTTSS2SI64rm
- 1277200503U, // Int_CVTTSS2SI64rr
- 2080376963U, // Int_CVTTSS2SIrm
- 1277200515U, // Int_CVTTSS2SIrr
- 1946160710U, // Int_UCOMISDrm
- 1277201990U, // Int_UCOMISDrr
- 1946160719U, // Int_UCOMISSrm
- 1277201999U, // Int_UCOMISSrr
- 1549799000U, // JA
- 1549799000U, // JA8
- 1549799004U, // JAE
- 1549799004U, // JAE8
- 1549799009U, // JB
- 1549799009U, // JB8
- 1549799013U, // JBE
- 1549799013U, // JBE8
- 1549799018U, // JCXZ8
- 1549799024U, // JE
- 1549799024U, // JE8
- 1549799028U, // JG
- 1549799028U, // JG8
- 1549799032U, // JGE
- 1549799032U, // JGE8
- 1549799037U, // JL
- 1549799037U, // JL8
- 1549799041U, // JLE
- 1549799041U, // JLE8
- 1549799046U, // JMP
- 945819275U, // JMP32m
- 73404043U, // JMP32r
- 1476398738U, // JMP64m
- 1549799065U, // JMP64pcrel32
- 73404050U, // JMP64r
- 1549799046U, // JMP8
- 1549799071U, // JNE
- 1549799071U, // JNE8
- 1549799076U, // JNO
- 1549799076U, // JNO8
- 1549799081U, // JNP
- 1549799081U, // JNP8
- 1549799086U, // JNS
- 1549799086U, // JNS8
- 1549799091U, // JO
- 1549799091U, // JO8
- 1549799095U, // JP
- 1549799095U, // JP8
- 1549799099U, // JS
- 1549799099U, // JS8
- 3775U, // LAHF
- 1207963332U, // LAR16rm
- 1277202116U, // LAR16rr
- 1207963338U, // LAR32rm
- 1277202122U, // LAR32rr
- 1207963344U, // LAR64rm
- 1277202128U, // LAR64rr
- 135270102U, // LCMPXCHG16
- 135335654U, // LCMPXCHG32
- 154144502U, // LCMPXCHG64
- 135401222U, // LCMPXCHG8
- 945819414U, // LCMPXCHG8B
- 2281705255U, // LDDQUrm
- 945819438U, // LDMXCSR
- 2348814135U, // LDS16rm
- 2348814141U, // LDS32rm
- 3907U, // LD_F0
- 3912U, // LD_F1
- 738201421U, // LD_F32m
- 805310291U, // LD_F64m
- 2415923033U, // LD_F80m
+ 1756596007U, // Int_CMPSDrm
+ 1823672103U, // Int_CMPSDrr
+ 1757677351U, // Int_CMPSSrm
+ 1824720679U, // Int_CMPSSrr
+ 1946158978U, // Int_COMISDrm
+ 1277200258U, // Int_COMISDrr
+ 1946158986U, // Int_COMISSrm
+ 1277200266U, // Int_COMISSrr
+ 1409288134U, // Int_CVTDQ2PDrm
+ 1277200326U, // Int_CVTDQ2PDrr
+ 2281703376U, // Int_CVTDQ2PSrm
+ 1277200336U, // Int_CVTDQ2PSrr
+ 1946159066U, // Int_CVTPD2DQrm
+ 1277200346U, // Int_CVTPD2DQrr
+ 1946160629U, // Int_CVTPD2PIrm
+ 1277201909U, // Int_CVTPD2PIrr
+ 1946159076U, // Int_CVTPD2PSrm
+ 1277200356U, // Int_CVTPD2PSrr
+ 1409289727U, // Int_CVTPI2PDrm
+ 1277201919U, // Int_CVTPI2PDrr
+ 404786697U, // Int_CVTPI2PSrm
+ 203460105U, // Int_CVTPI2PSrr
+ 1946159086U, // Int_CVTPS2DQrm
+ 1277200366U, // Int_CVTPS2DQrr
+ 2013267960U, // Int_CVTPS2PDrm
+ 1277200376U, // Int_CVTPS2PDrr
+ 2013269523U, // Int_CVTPS2PIrm
+ 1277201939U, // Int_CVTPS2PIrr
+ 1946159106U, // Int_CVTSD2SI64rm
+ 1277200386U, // Int_CVTSD2SI64rr
+ 1946160669U, // Int_CVTSD2SIrm
+ 1277201949U, // Int_CVTSD2SIrr
+ 603981837U, // Int_CVTSD2SSrm
+ 203458573U, // Int_CVTSD2SSrr
+ 404785175U, // Int_CVTSI2SD64rm
+ 203458583U, // Int_CVTSI2SD64rr
+ 337676322U, // Int_CVTSI2SDrm
+ 203458594U, // Int_CVTSI2SDrr
+ 404785196U, // Int_CVTSI2SS64rm
+ 203458604U, // Int_CVTSI2SS64rr
+ 337676343U, // Int_CVTSI2SSrm
+ 203458615U, // Int_CVTSI2SSrr
+ 671090753U, // Int_CVTSS2SDrm
+ 203458625U, // Int_CVTSS2SDrr
+ 2080376907U, // Int_CVTSS2SI64rm
+ 1277200459U, // Int_CVTSS2SI64rr
+ 2080378407U, // Int_CVTSS2SIrm
+ 1277201959U, // Int_CVTSS2SIrr
+ 1946160689U, // Int_CVTTPD2DQrm
+ 1277201969U, // Int_CVTTPD2DQrr
+ 1946160700U, // Int_CVTTPD2PIrm
+ 1277201980U, // Int_CVTTPD2PIrr
+ 1946159201U, // Int_CVTTPS2DQrm
+ 1277200481U, // Int_CVTTPS2DQrr
+ 2013269575U, // Int_CVTTPS2PIrm
+ 1277201991U, // Int_CVTTPS2PIrr
+ 1946159212U, // Int_CVTTSD2SI64rm
+ 1277200492U, // Int_CVTTSD2SI64rr
+ 1946159224U, // Int_CVTTSD2SIrm
+ 1277200504U, // Int_CVTTSD2SIrr
+ 2080376963U, // Int_CVTTSS2SI64rm
+ 1277200515U, // Int_CVTTSS2SI64rr
+ 2080376975U, // Int_CVTTSS2SIrm
+ 1277200527U, // Int_CVTTSS2SIrr
+ 1946160722U, // Int_UCOMISDrm
+ 1277202002U, // Int_UCOMISDrr
+ 1946160731U, // Int_UCOMISSrm
+ 1277202011U, // Int_UCOMISSrr
+ 1549799012U, // JA
+ 1549799012U, // JA8
+ 1549799016U, // JAE
+ 1549799016U, // JAE8
+ 1549799021U, // JB
+ 1549799021U, // JB8
+ 1549799025U, // JBE
+ 1549799025U, // JBE8
+ 1549799030U, // JCXZ8
+ 1549799036U, // JE
+ 1549799036U, // JE8
+ 1549799040U, // JG
+ 1549799040U, // JG8
+ 1549799044U, // JGE
+ 1549799044U, // JGE8
+ 1549799049U, // JL
+ 1549799049U, // JL8
+ 1549799053U, // JLE
+ 1549799053U, // JLE8
+ 1549799058U, // JMP
+ 945819287U, // JMP32m
+ 73404055U, // JMP32r
+ 1476398750U, // JMP64m
+ 1549799077U, // JMP64pcrel32
+ 73404062U, // JMP64r
+ 1549799058U, // JMP8
+ 1549799083U, // JNE
+ 1549799083U, // JNE8
+ 1549799088U, // JNO
+ 1549799088U, // JNO8
+ 1549799093U, // JNP
+ 1549799093U, // JNP8
+ 1549799098U, // JNS
+ 1549799098U, // JNS8
+ 1549799103U, // JO
+ 1549799103U, // JO8
+ 1549799107U, // JP
+ 1549799107U, // JP8
+ 1549799111U, // JS
+ 1549799111U, // JS8
+ 3787U, // LAHF
+ 1207963344U, // LAR16rm
+ 1277202128U, // LAR16rr
+ 1207963350U, // LAR32rm
+ 1277202134U, // LAR32rr
+ 1207963356U, // LAR64rm
+ 1277202140U, // LAR64rr
+ 135270114U, // LCMPXCHG16
+ 135335666U, // LCMPXCHG32
+ 154144514U, // LCMPXCHG64
+ 135401234U, // LCMPXCHG8
+ 1476398882U, // LCMPXCHG8B
+ 2281705267U, // LDDQUrm
+ 945819450U, // LDMXCSR
+ 2348814147U, // LDS16rm
+ 2348814153U, // LDS32rm
+ 3919U, // LD_F0
+ 3924U, // LD_F1
+ 738201433U, // LD_F32m
+ 805310303U, // LD_F64m
+ 2415923045U, // LD_F80m
0U, // LD_Fp032
0U, // LD_Fp064
0U, // LD_Fp080
@@ -990,461 +991,463 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // LD_Fp64m
0U, // LD_Fp64m80
0U, // LD_Fp80m
- 73404255U, // LD_Frr
- 2483031908U, // LEA16r
- 2483031914U, // LEA32r
- 2550140778U, // LEA64_32r
- 2617249648U, // LEA64r
- 3958U, // LEAVE
- 3958U, // LEAVE64
- 2348814204U, // LES16rm
- 2348814210U, // LES32rm
- 3976U, // LFENCE
- 2348814223U, // LFS16rm
- 2348814229U, // LFS32rm
- 2348814235U, // LFS64rm
- 2214596513U, // LGDTm
- 2348814247U, // LGS16rm
- 2348814253U, // LGS32rm
- 2348814259U, // LGS64rm
- 2214596537U, // LIDTm
- 872419263U, // LLDT16m
- 73404351U, // LLDT16r
- 872419270U, // LMSW16m
- 73404358U, // LMSW16r
- 135270349U, // LOCK_ADD16mi
- 135270349U, // LOCK_ADD16mi8
- 135270349U, // LOCK_ADD16mr
- 135335897U, // LOCK_ADD32mi
- 135335897U, // LOCK_ADD32mi8
- 135335897U, // LOCK_ADD32mr
- 135368677U, // LOCK_ADD64mi32
- 135368677U, // LOCK_ADD64mi8
- 135368677U, // LOCK_ADD64mr
- 135401457U, // LOCK_ADD8mi
- 135401457U, // LOCK_ADD8mr
- 872419325U, // LOCK_DEC16m
- 945819657U, // LOCK_DEC32m
- 1476399125U, // LOCK_DEC64m
- 1610616865U, // LOCK_DEC8m
- 872419373U, // LOCK_INC16m
- 945819705U, // LOCK_INC32m
- 1476399173U, // LOCK_INC64m
- 1610616913U, // LOCK_INC8m
- 135270493U, // LOCK_SUB16mi
- 135270493U, // LOCK_SUB16mi8
- 135270493U, // LOCK_SUB16mr
- 135336041U, // LOCK_SUB32mi
- 135336041U, // LOCK_SUB32mi8
- 135336041U, // LOCK_SUB32mr
- 135368821U, // LOCK_SUB64mi32
- 135368821U, // LOCK_SUB64mi8
- 135368821U, // LOCK_SUB64mr
- 135401601U, // LOCK_SUB8mi
- 135401601U, // LOCK_SUB8mr
- 4237U, // LODSB
- 4243U, // LODSD
- 4249U, // LODSQ
- 4255U, // LODSW
- 1549799589U, // LOOP
- 1549799595U, // LOOPE
- 1549799602U, // LOOPNE
- 4282U, // LRET
- 73404607U, // LRETI
- 1207963845U, // LSL16rm
- 1277202629U, // LSL16rr
- 1342181579U, // LSL32rm
- 1277202635U, // LSL32rr
- 1409290449U, // LSL64rm
- 1277202641U, // LSL64rr
- 2348814551U, // LSS16rm
- 2348814557U, // LSS32rm
- 2348814563U, // LSS64rm
- 872419561U, // LTRm
- 73404649U, // LTRr
- 1296077039U, // LXADD16
- 1297125628U, // LXADD32
- 1298174217U, // LXADD64
- 1299222805U, // LXADD8
- 1277202722U, // MASKMOVDQU
- 1277202722U, // MASKMOVDQU64
- 536875310U, // MAXPDrm
- 536875310U, // MAXPDrm_Int
- 203460910U, // MAXPDrr
- 203460910U, // MAXPDrr_Int
- 536875317U, // MAXPSrm
- 536875317U, // MAXPSrm_Int
- 203460917U, // MAXPSrr
- 203460917U, // MAXPSrr_Int
- 603984188U, // MAXSDrm
- 603984188U, // MAXSDrm_Int
- 203460924U, // MAXSDrr
- 203460924U, // MAXSDrr_Int
- 671093059U, // MAXSSrm
- 671093059U, // MAXSSrm_Int
- 203460931U, // MAXSSrr
- 203460931U, // MAXSSrr_Int
- 4426U, // MFENCE
- 536875345U, // MINPDrm
- 536875345U, // MINPDrm_Int
- 203460945U, // MINPDrr
- 203460945U, // MINPDrr_Int
- 536875352U, // MINPSrm
- 536875352U, // MINPSrm_Int
- 203460952U, // MINPSrr
- 203460952U, // MINPSrr_Int
- 603984223U, // MINSDrm
- 603984223U, // MINSDrm_Int
- 203460959U, // MINSDrr
- 203460959U, // MINSDrr_Int
- 671093094U, // MINSSrm
- 671093094U, // MINSSrm_Int
- 203460966U, // MINSSrr
- 203460966U, // MINSSrr_Int
- 1946160617U, // MMX_CVTPD2PIrm
- 1277201897U, // MMX_CVTPD2PIrr
- 1409289715U, // MMX_CVTPI2PDrm
- 1277201907U, // MMX_CVTPI2PDrr
- 1409289725U, // MMX_CVTPI2PSrm
- 1277201917U, // MMX_CVTPI2PSrr
- 2013269511U, // MMX_CVTPS2PIrm
- 1277201927U, // MMX_CVTPS2PIrr
- 1946160688U, // MMX_CVTTPD2PIrm
- 1277201968U, // MMX_CVTTPD2PIrr
- 2013269563U, // MMX_CVTTPS2PIrm
- 1277201979U, // MMX_CVTTPS2PIrr
- 4461U, // MMX_EMMS
- 4466U, // MMX_FEMMS
- 1277202808U, // MMX_MASKMOVQ
- 1277202808U, // MMX_MASKMOVQ64
- 1277202818U, // MMX_MOVD64from64rr
- 1277202818U, // MMX_MOVD64grr
- 135336322U, // MMX_MOVD64mr
- 1342181762U, // MMX_MOVD64rm
- 1277202818U, // MMX_MOVD64rr
- 1277202818U, // MMX_MOVD64rrv164
- 1277202818U, // MMX_MOVD64to64rr
- 1277202824U, // MMX_MOVDQ2Qrr
- 135369105U, // MMX_MOVNTQmr
- 1277202841U, // MMX_MOVQ2DQrr
- 1277202841U, // MMX_MOVQ2FR64rr
- 135369122U, // MMX_MOVQ64gmr
- 135369122U, // MMX_MOVQ64mr
- 1409290658U, // MMX_MOVQ64rm
- 1277202850U, // MMX_MOVQ64rr
- 1342181762U, // MMX_MOVZDI2PDIrm
- 1277202818U, // MMX_MOVZDI2PDIrr
- 404787624U, // MMX_PACKSSDWrm
- 203461032U, // MMX_PACKSSDWrr
- 404787634U, // MMX_PACKSSWBrm
- 203461042U, // MMX_PACKSSWBrr
- 404787644U, // MMX_PACKUSWBrm
- 203461052U, // MMX_PACKUSWBrr
- 404787654U, // MMX_PADDBrm
- 203461062U, // MMX_PADDBrr
- 404787661U, // MMX_PADDDrm
- 203461069U, // MMX_PADDDrr
- 404787668U, // MMX_PADDQrm
- 203461076U, // MMX_PADDQrr
- 404787675U, // MMX_PADDSBrm
- 203461083U, // MMX_PADDSBrr
- 404787683U, // MMX_PADDSWrm
- 203461091U, // MMX_PADDSWrr
- 404787691U, // MMX_PADDUSBrm
- 203461099U, // MMX_PADDUSBrr
- 404787700U, // MMX_PADDUSWrm
- 203461108U, // MMX_PADDUSWrr
- 404787709U, // MMX_PADDWrm
- 203461117U, // MMX_PADDWrr
- 404787716U, // MMX_PANDNrm
- 203461124U, // MMX_PANDNrr
- 404787723U, // MMX_PANDrm
- 203461131U, // MMX_PANDrr
- 404787729U, // MMX_PAVGBrm
- 203461137U, // MMX_PAVGBrr
- 404787736U, // MMX_PAVGWrm
- 203461144U, // MMX_PAVGWrr
- 404787743U, // MMX_PCMPEQBrm
- 203461151U, // MMX_PCMPEQBrr
- 404787752U, // MMX_PCMPEQDrm
- 203461160U, // MMX_PCMPEQDrr
- 404787761U, // MMX_PCMPEQWrm
- 203461169U, // MMX_PCMPEQWrr
- 404787770U, // MMX_PCMPGTBrm
- 203461178U, // MMX_PCMPGTBrr
- 404787779U, // MMX_PCMPGTDrm
- 203461187U, // MMX_PCMPGTDrr
- 404787788U, // MMX_PCMPGTWrm
- 203461196U, // MMX_PCMPGTWrr
- 215323221U, // MMX_PEXTRWri
- 1027969629U, // MMX_PINSRWrmi
- 1073746525U, // MMX_PINSRWrri
- 404787813U, // MMX_PMADDWDrm
- 203461221U, // MMX_PMADDWDrr
- 404787822U, // MMX_PMAXSWrm
- 203461230U, // MMX_PMAXSWrr
- 404787830U, // MMX_PMAXUBrm
- 203461238U, // MMX_PMAXUBrr
- 404787838U, // MMX_PMINSWrm
- 203461246U, // MMX_PMINSWrr
- 404787846U, // MMX_PMINUBrm
- 203461254U, // MMX_PMINUBrr
- 1277203086U, // MMX_PMOVMSKBrr
- 404787864U, // MMX_PMULHUWrm
- 203461272U, // MMX_PMULHUWrr
- 404787873U, // MMX_PMULHWrm
- 203461281U, // MMX_PMULHWrr
- 404787881U, // MMX_PMULLWrm
- 203461289U, // MMX_PMULLWrr
- 404787889U, // MMX_PMULUDQrm
- 203461297U, // MMX_PMULUDQrr
- 404787898U, // MMX_PORrm
- 203461306U, // MMX_PORrr
- 404787903U, // MMX_PSADBWrm
- 203461311U, // MMX_PSADBWrr
- 2165314247U, // MMX_PSHUFWmi
- 215323335U, // MMX_PSHUFWri
- 203461327U, // MMX_PSLLDri
- 404787919U, // MMX_PSLLDrm
- 203461327U, // MMX_PSLLDrr
- 203461334U, // MMX_PSLLQri
- 404787926U, // MMX_PSLLQrm
- 203461334U, // MMX_PSLLQrr
- 203461341U, // MMX_PSLLWri
- 404787933U, // MMX_PSLLWrm
- 203461341U, // MMX_PSLLWrr
- 203461348U, // MMX_PSRADri
- 404787940U, // MMX_PSRADrm
- 203461348U, // MMX_PSRADrr
- 203461355U, // MMX_PSRAWri
- 404787947U, // MMX_PSRAWrm
- 203461355U, // MMX_PSRAWrr
- 203461362U, // MMX_PSRLDri
- 404787954U, // MMX_PSRLDrm
- 203461362U, // MMX_PSRLDrr
- 203461369U, // MMX_PSRLQri
- 404787961U, // MMX_PSRLQrm
- 203461369U, // MMX_PSRLQrr
- 203461376U, // MMX_PSRLWri
- 404787968U, // MMX_PSRLWrm
- 203461376U, // MMX_PSRLWrr
- 404787975U, // MMX_PSUBBrm
- 203461383U, // MMX_PSUBBrr
- 404787982U, // MMX_PSUBDrm
- 203461390U, // MMX_PSUBDrr
- 404787989U, // MMX_PSUBQrm
- 203461397U, // MMX_PSUBQrr
- 404787996U, // MMX_PSUBSBrm
- 203461404U, // MMX_PSUBSBrr
- 404788004U, // MMX_PSUBSWrm
- 203461412U, // MMX_PSUBSWrr
- 404788012U, // MMX_PSUBUSBrm
- 203461420U, // MMX_PSUBUSBrr
- 404788021U, // MMX_PSUBUSWrm
- 203461429U, // MMX_PSUBUSWrr
- 404788030U, // MMX_PSUBWrm
- 203461438U, // MMX_PSUBWrr
- 404788037U, // MMX_PUNPCKHBWrm
- 203461445U, // MMX_PUNPCKHBWrr
- 404788048U, // MMX_PUNPCKHDQrm
- 203461456U, // MMX_PUNPCKHDQrr
- 404788059U, // MMX_PUNPCKHWDrm
- 203461467U, // MMX_PUNPCKHWDrr
- 404788070U, // MMX_PUNPCKLBWrm
- 203461478U, // MMX_PUNPCKLBWrr
- 404788081U, // MMX_PUNPCKLDQrm
- 203461489U, // MMX_PUNPCKLDQrr
- 404788092U, // MMX_PUNPCKLWDrm
- 203461500U, // MMX_PUNPCKLWDrr
- 404786275U, // MMX_PXORrm
- 203459683U, // MMX_PXORrr
- 68553827U, // MMX_V_SET0
- 68555304U, // MMX_V_SETALLONES
- 4999U, // MONITOR
- 1549800335U, // MOV16ao16
- 135271322U, // MOV16mi
- 135271322U, // MOV16mr
- 135271322U, // MOV16ms
- 1543508890U, // MOV16o16a
- 1277203354U, // MOV16ri
- 1207964570U, // MOV16rm
- 1277203354U, // MOV16rr
- 1277203354U, // MOV16rr_REV
- 1277203354U, // MOV16rs
- 1207964570U, // MOV16sm
- 1277203354U, // MOV16sr
- 1549800352U, // MOV32ao32
- 1277202850U, // MOV32cr
- 1277203372U, // MOV32dr
- 135336876U, // MOV32mi
- 135336876U, // MOV32mr
- 1546654636U, // MOV32o32a
- 68555698U, // MOV32r0
- 1277202850U, // MOV32rc
- 1277203372U, // MOV32rd
- 1277203372U, // MOV32ri
- 1342182316U, // MOV32rm
- 1277203372U, // MOV32rr
- 1277203372U, // MOV32rr_REV
- 1409291192U, // MOV64FSrm
- 1409291202U, // MOV64GSrm
- 1549800396U, // MOV64ao64
- 1549800396U, // MOV64ao8
- 1277202850U, // MOV64cr
- 1277202850U, // MOV64dr
- 135369122U, // MOV64mi32
- 135369122U, // MOV64mr
- 135369122U, // MOV64ms
- 1547702690U, // MOV64o64a
- 1547702690U, // MOV64o8a
- 1277202850U, // MOV64rc
- 1277202850U, // MOV64rd
- 1277203416U, // MOV64ri
- 1277202850U, // MOV64ri32
+ 73404267U, // LD_Frr
+ 2483031920U, // LEA16r
+ 2483031926U, // LEA32r
+ 2550140790U, // LEA64_32r
+ 2617249660U, // LEA64r
+ 3970U, // LEAVE
+ 3970U, // LEAVE64
+ 2348814216U, // LES16rm
+ 2348814222U, // LES32rm
+ 3988U, // LFENCE
+ 2348814235U, // LFS16rm
+ 2348814241U, // LFS32rm
+ 2348814247U, // LFS64rm
+ 2214596525U, // LGDTm
+ 2348814259U, // LGS16rm
+ 2348814265U, // LGS32rm
+ 2348814271U, // LGS64rm
+ 2214596549U, // LIDTm
+ 872419275U, // LLDT16m
+ 73404363U, // LLDT16r
+ 872419282U, // LMSW16m
+ 73404370U, // LMSW16r
+ 135270361U, // LOCK_ADD16mi
+ 135270361U, // LOCK_ADD16mi8
+ 135270361U, // LOCK_ADD16mr
+ 135335909U, // LOCK_ADD32mi
+ 135335909U, // LOCK_ADD32mi8
+ 135335909U, // LOCK_ADD32mr
+ 135368689U, // LOCK_ADD64mi32
+ 135368689U, // LOCK_ADD64mi8
+ 135368689U, // LOCK_ADD64mr
+ 135401469U, // LOCK_ADD8mi
+ 135401469U, // LOCK_ADD8mr
+ 872419337U, // LOCK_DEC16m
+ 945819669U, // LOCK_DEC32m
+ 1476399137U, // LOCK_DEC64m
+ 1610616877U, // LOCK_DEC8m
+ 872419385U, // LOCK_INC16m
+ 945819717U, // LOCK_INC32m
+ 1476399185U, // LOCK_INC64m
+ 1610616925U, // LOCK_INC8m
+ 135270505U, // LOCK_SUB16mi
+ 135270505U, // LOCK_SUB16mi8
+ 135270505U, // LOCK_SUB16mr
+ 135336053U, // LOCK_SUB32mi
+ 135336053U, // LOCK_SUB32mi8
+ 135336053U, // LOCK_SUB32mr
+ 135368833U, // LOCK_SUB64mi32
+ 135368833U, // LOCK_SUB64mi8
+ 135368833U, // LOCK_SUB64mr
+ 135401613U, // LOCK_SUB8mi
+ 135401613U, // LOCK_SUB8mr
+ 4249U, // LODSB
+ 4255U, // LODSD
+ 4261U, // LODSQ
+ 4267U, // LODSW
+ 1549799601U, // LOOP
+ 1549799607U, // LOOPE
+ 1549799614U, // LOOPNE
+ 4294U, // LRET
+ 73404619U, // LRETI
+ 1207963857U, // LSL16rm
+ 1277202641U, // LSL16rr
+ 1342181591U, // LSL32rm
+ 1277202647U, // LSL32rr
+ 1409290461U, // LSL64rm
+ 1277202653U, // LSL64rr
+ 2348814563U, // LSS16rm
+ 2348814569U, // LSS32rm
+ 2348814575U, // LSS64rm
+ 872419573U, // LTRm
+ 73404661U, // LTRr
+ 1296077051U, // LXADD16
+ 1297125640U, // LXADD32
+ 1298174229U, // LXADD64
+ 1299222817U, // LXADD8
+ 1277202734U, // MASKMOVDQU
+ 1277202734U, // MASKMOVDQU64
+ 536875322U, // MAXPDrm
+ 536875322U, // MAXPDrm_Int
+ 203460922U, // MAXPDrr
+ 203460922U, // MAXPDrr_Int
+ 536875329U, // MAXPSrm
+ 536875329U, // MAXPSrm_Int
+ 203460929U, // MAXPSrr
+ 203460929U, // MAXPSrr_Int
+ 603984200U, // MAXSDrm
+ 603984200U, // MAXSDrm_Int
+ 203460936U, // MAXSDrr
+ 203460936U, // MAXSDrr_Int
+ 671093071U, // MAXSSrm
+ 671093071U, // MAXSSrm_Int
+ 203460943U, // MAXSSrr
+ 203460943U, // MAXSSrr_Int
+ 4438U, // MFENCE
+ 536875357U, // MINPDrm
+ 536875357U, // MINPDrm_Int
+ 203460957U, // MINPDrr
+ 203460957U, // MINPDrr_Int
+ 536875364U, // MINPSrm
+ 536875364U, // MINPSrm_Int
+ 203460964U, // MINPSrr
+ 203460964U, // MINPSrr_Int
+ 603984235U, // MINSDrm
+ 603984235U, // MINSDrm_Int
+ 203460971U, // MINSDrr
+ 203460971U, // MINSDrr_Int
+ 671093106U, // MINSSrm
+ 671093106U, // MINSSrm_Int
+ 203460978U, // MINSSrr
+ 203460978U, // MINSSrr_Int
+ 1946160629U, // MMX_CVTPD2PIrm
+ 1277201909U, // MMX_CVTPD2PIrr
+ 1409289727U, // MMX_CVTPI2PDrm
+ 1277201919U, // MMX_CVTPI2PDrr
+ 1409289737U, // MMX_CVTPI2PSrm
+ 1277201929U, // MMX_CVTPI2PSrr
+ 2013269523U, // MMX_CVTPS2PIrm
+ 1277201939U, // MMX_CVTPS2PIrr
+ 1946160700U, // MMX_CVTTPD2PIrm
+ 1277201980U, // MMX_CVTTPD2PIrr
+ 2013269575U, // MMX_CVTTPS2PIrm
+ 1277201991U, // MMX_CVTTPS2PIrr
+ 4473U, // MMX_EMMS
+ 4478U, // MMX_FEMMS
+ 1277202820U, // MMX_MASKMOVQ
+ 1277202820U, // MMX_MASKMOVQ64
+ 1277202830U, // MMX_MOVD64from64rr
+ 1277202830U, // MMX_MOVD64grr
+ 135336334U, // MMX_MOVD64mr
+ 1342181774U, // MMX_MOVD64rm
+ 1277202830U, // MMX_MOVD64rr
+ 1277202830U, // MMX_MOVD64rrv164
+ 1277202830U, // MMX_MOVD64to64rr
+ 1277202836U, // MMX_MOVDQ2Qrr
+ 135369117U, // MMX_MOVNTQmr
+ 1277202853U, // MMX_MOVQ2DQrr
+ 1277202853U, // MMX_MOVQ2FR64rr
+ 135369134U, // MMX_MOVQ64gmr
+ 135369134U, // MMX_MOVQ64mr
+ 1409290670U, // MMX_MOVQ64rm
+ 1277202862U, // MMX_MOVQ64rr
+ 1342181774U, // MMX_MOVZDI2PDIrm
+ 1277202830U, // MMX_MOVZDI2PDIrr
+ 404787636U, // MMX_PACKSSDWrm
+ 203461044U, // MMX_PACKSSDWrr
+ 404787646U, // MMX_PACKSSWBrm
+ 203461054U, // MMX_PACKSSWBrr
+ 404787656U, // MMX_PACKUSWBrm
+ 203461064U, // MMX_PACKUSWBrr
+ 404787666U, // MMX_PADDBrm
+ 203461074U, // MMX_PADDBrr
+ 404787673U, // MMX_PADDDrm
+ 203461081U, // MMX_PADDDrr
+ 404787680U, // MMX_PADDQrm
+ 203461088U, // MMX_PADDQrr
+ 404787687U, // MMX_PADDSBrm
+ 203461095U, // MMX_PADDSBrr
+ 404787695U, // MMX_PADDSWrm
+ 203461103U, // MMX_PADDSWrr
+ 404787703U, // MMX_PADDUSBrm
+ 203461111U, // MMX_PADDUSBrr
+ 404787712U, // MMX_PADDUSWrm
+ 203461120U, // MMX_PADDUSWrr
+ 404787721U, // MMX_PADDWrm
+ 203461129U, // MMX_PADDWrr
+ 404787728U, // MMX_PANDNrm
+ 203461136U, // MMX_PANDNrr
+ 404787735U, // MMX_PANDrm
+ 203461143U, // MMX_PANDrr
+ 404787741U, // MMX_PAVGBrm
+ 203461149U, // MMX_PAVGBrr
+ 404787748U, // MMX_PAVGWrm
+ 203461156U, // MMX_PAVGWrr
+ 404787755U, // MMX_PCMPEQBrm
+ 203461163U, // MMX_PCMPEQBrr
+ 404787764U, // MMX_PCMPEQDrm
+ 203461172U, // MMX_PCMPEQDrr
+ 404787773U, // MMX_PCMPEQWrm
+ 203461181U, // MMX_PCMPEQWrr
+ 404787782U, // MMX_PCMPGTBrm
+ 203461190U, // MMX_PCMPGTBrr
+ 404787791U, // MMX_PCMPGTDrm
+ 203461199U, // MMX_PCMPGTDrr
+ 404787800U, // MMX_PCMPGTWrm
+ 203461208U, // MMX_PCMPGTWrr
+ 215323233U, // MMX_PEXTRWri
+ 1027969641U, // MMX_PINSRWrmi
+ 1073746537U, // MMX_PINSRWrri
+ 404787825U, // MMX_PMADDWDrm
+ 203461233U, // MMX_PMADDWDrr
+ 404787834U, // MMX_PMAXSWrm
+ 203461242U, // MMX_PMAXSWrr
+ 404787842U, // MMX_PMAXUBrm
+ 203461250U, // MMX_PMAXUBrr
+ 404787850U, // MMX_PMINSWrm
+ 203461258U, // MMX_PMINSWrr
+ 404787858U, // MMX_PMINUBrm
+ 203461266U, // MMX_PMINUBrr
+ 1277203098U, // MMX_PMOVMSKBrr
+ 404787876U, // MMX_PMULHUWrm
+ 203461284U, // MMX_PMULHUWrr
+ 404787885U, // MMX_PMULHWrm
+ 203461293U, // MMX_PMULHWrr
+ 404787893U, // MMX_PMULLWrm
+ 203461301U, // MMX_PMULLWrr
+ 404787901U, // MMX_PMULUDQrm
+ 203461309U, // MMX_PMULUDQrr
+ 404787910U, // MMX_PORrm
+ 203461318U, // MMX_PORrr
+ 404787915U, // MMX_PSADBWrm
+ 203461323U, // MMX_PSADBWrr
+ 2165314259U, // MMX_PSHUFWmi
+ 215323347U, // MMX_PSHUFWri
+ 203461339U, // MMX_PSLLDri
+ 404787931U, // MMX_PSLLDrm
+ 203461339U, // MMX_PSLLDrr
+ 203461346U, // MMX_PSLLQri
+ 404787938U, // MMX_PSLLQrm
+ 203461346U, // MMX_PSLLQrr
+ 203461353U, // MMX_PSLLWri
+ 404787945U, // MMX_PSLLWrm
+ 203461353U, // MMX_PSLLWrr
+ 203461360U, // MMX_PSRADri
+ 404787952U, // MMX_PSRADrm
+ 203461360U, // MMX_PSRADrr
+ 203461367U, // MMX_PSRAWri
+ 404787959U, // MMX_PSRAWrm
+ 203461367U, // MMX_PSRAWrr
+ 203461374U, // MMX_PSRLDri
+ 404787966U, // MMX_PSRLDrm
+ 203461374U, // MMX_PSRLDrr
+ 203461381U, // MMX_PSRLQri
+ 404787973U, // MMX_PSRLQrm
+ 203461381U, // MMX_PSRLQrr
+ 203461388U, // MMX_PSRLWri
+ 404787980U, // MMX_PSRLWrm
+ 203461388U, // MMX_PSRLWrr
+ 404787987U, // MMX_PSUBBrm
+ 203461395U, // MMX_PSUBBrr
+ 404787994U, // MMX_PSUBDrm
+ 203461402U, // MMX_PSUBDrr
+ 404788001U, // MMX_PSUBQrm
+ 203461409U, // MMX_PSUBQrr
+ 404788008U, // MMX_PSUBSBrm
+ 203461416U, // MMX_PSUBSBrr
+ 404788016U, // MMX_PSUBSWrm
+ 203461424U, // MMX_PSUBSWrr
+ 404788024U, // MMX_PSUBUSBrm
+ 203461432U, // MMX_PSUBUSBrr
+ 404788033U, // MMX_PSUBUSWrm
+ 203461441U, // MMX_PSUBUSWrr
+ 404788042U, // MMX_PSUBWrm
+ 203461450U, // MMX_PSUBWrr
+ 404788049U, // MMX_PUNPCKHBWrm
+ 203461457U, // MMX_PUNPCKHBWrr
+ 404788060U, // MMX_PUNPCKHDQrm
+ 203461468U, // MMX_PUNPCKHDQrr
+ 404788071U, // MMX_PUNPCKHWDrm
+ 203461479U, // MMX_PUNPCKHWDrr
+ 404788082U, // MMX_PUNPCKLBWrm
+ 203461490U, // MMX_PUNPCKLBWrr
+ 404788093U, // MMX_PUNPCKLDQrm
+ 203461501U, // MMX_PUNPCKLDQrr
+ 404788104U, // MMX_PUNPCKLWDrm
+ 203461512U, // MMX_PUNPCKLWDrr
+ 404786287U, // MMX_PXORrm
+ 203459695U, // MMX_PXORrr
+ 68553839U, // MMX_V_SET0
+ 68555316U, // MMX_V_SETALLONES
+ 5011U, // MONITOR
+ 1549800347U, // MOV16ao16
+ 135271334U, // MOV16mi
+ 135271334U, // MOV16mr
+ 135271334U, // MOV16ms
+ 1543508902U, // MOV16o16a
+ 0U, // MOV16r0
+ 1277203366U, // MOV16ri
+ 1207964582U, // MOV16rm
+ 1277203366U, // MOV16rr
+ 1277203366U, // MOV16rr_REV
+ 1277203366U, // MOV16rs
+ 1207964582U, // MOV16sm
+ 1277203366U, // MOV16sr
+ 1549800364U, // MOV32ao32
+ 1277202862U, // MOV32cr
+ 1277203384U, // MOV32dr
+ 135336888U, // MOV32mi
+ 135336888U, // MOV32mr
+ 1546654648U, // MOV32o32a
+ 68555710U, // MOV32r0
+ 1277202862U, // MOV32rc
+ 1277203384U, // MOV32rd
+ 1277203384U, // MOV32ri
+ 1342182328U, // MOV32rm
+ 1277203384U, // MOV32rr
+ 1277203384U, // MOV32rr_REV
+ 1409291204U, // MOV64FSrm
+ 1409291214U, // MOV64GSrm
+ 1549800408U, // MOV64ao64
+ 1549800408U, // MOV64ao8
+ 1277202862U, // MOV64cr
+ 1277202862U, // MOV64dr
+ 135369134U, // MOV64mi32
+ 135369134U, // MOV64mr
+ 135369134U, // MOV64ms
+ 1547702702U, // MOV64o64a
+ 1547702702U, // MOV64o8a
+ 0U, // MOV64r0
+ 1277202862U, // MOV64rc
+ 1277202862U, // MOV64rd
+ 1277203428U, // MOV64ri
+ 1277202862U, // MOV64ri32
0U, // MOV64ri64i32
- 1409290658U, // MOV64rm
- 1277202850U, // MOV64rr
- 1277202850U, // MOV64rr_REV
- 1277202850U, // MOV64rs
- 1409290658U, // MOV64sm
- 1277202850U, // MOV64sr
- 1277202818U, // MOV64toPQIrr
- 1409290658U, // MOV64toSDrm
- 1277202818U, // MOV64toSDrr
- 1549800417U, // MOV8ao8
- 135402476U, // MOV8mi
- 135402476U, // MOV8mr
- 135402476U, // MOV8mr_NOREX
- 1548751852U, // MOV8o8a
- 68555762U, // MOV8r0
- 1277203436U, // MOV8ri
- 1684018156U, // MOV8rm
- 1702892524U, // MOV8rm_NOREX
- 1277203436U, // MOV8rr
- 1277596652U, // MOV8rr_NOREX
- 1277203436U, // MOV8rr_REV
- 135728233U, // MOVAPDmr
- 1946160233U, // MOVAPDrm
- 1277201513U, // MOVAPDrr
- 135728241U, // MOVAPSmr
- 1946160241U, // MOVAPSrm
- 1277201521U, // MOVAPSrr
- 2013271032U, // MOVDDUPrm
- 1277203448U, // MOVDDUPrr
- 1342181762U, // MOVDI2PDIrm
- 1277202818U, // MOVDI2PDIrr
- 1342181762U, // MOVDI2SSrm
- 1277202818U, // MOVDI2SSrr
- 135762945U, // MOVDQAmr
- 2281706497U, // MOVDQArm
- 1277203457U, // MOVDQArr
- 135762953U, // MOVDQUmr
- 135762953U, // MOVDQUmr_Int
- 2281706505U, // MOVDQUrm
- 2281706505U, // MOVDQUrm_Int
- 203461649U, // MOVHLPSrr
- 135795738U, // MOVHPDmr
- 603984922U, // MOVHPDrm
- 135795746U, // MOVHPSmr
- 603984930U, // MOVHPSrm
- 203461674U, // MOVLHPSrr
- 135795763U, // MOVLPDmr
- 603984947U, // MOVLPDrm
- 203461691U, // MOVLPDrr
- 135795778U, // MOVLPSmr
- 603984962U, // MOVLPSrm
- 203461706U, // MOVLPSrr
- 135369122U, // MOVLQ128mr
- 203461691U, // MOVLSD2PDrr
- 203461706U, // MOVLSS2PSrr
- 1277203537U, // MOVMSKPDrr
- 1277203547U, // MOVMSKPSrr
- 2281706597U, // MOVNTDQArm
- 135730287U, // MOVNTDQmr
- 135337080U, // MOVNTImr
- 135763072U, // MOVNTPDmr
- 135763081U, // MOVNTPSmr
+ 1409290670U, // MOV64rm
+ 1277202862U, // MOV64rr
+ 1277202862U, // MOV64rr_REV
+ 1277202862U, // MOV64rs
+ 1409290670U, // MOV64sm
+ 1277202862U, // MOV64sr
+ 1277202830U, // MOV64toPQIrr
+ 1409290670U, // MOV64toSDrm
+ 1277202830U, // MOV64toSDrr
+ 1549800429U, // MOV8ao8
+ 135402488U, // MOV8mi
+ 135402488U, // MOV8mr
+ 135402488U, // MOV8mr_NOREX
+ 1548751864U, // MOV8o8a
+ 68555774U, // MOV8r0
+ 1277203448U, // MOV8ri
+ 1684018168U, // MOV8rm
+ 1702892536U, // MOV8rm_NOREX
+ 1277203448U, // MOV8rr
+ 1277596664U, // MOV8rr_NOREX
+ 1277203448U, // MOV8rr_REV
+ 135728245U, // MOVAPDmr
+ 1946160245U, // MOVAPDrm
+ 1277201525U, // MOVAPDrr
+ 135728253U, // MOVAPSmr
+ 1946160253U, // MOVAPSrm
+ 1277201533U, // MOVAPSrr
+ 2013271044U, // MOVDDUPrm
+ 1277203460U, // MOVDDUPrr
+ 1342181774U, // MOVDI2PDIrm
+ 1277202830U, // MOVDI2PDIrr
+ 1342181774U, // MOVDI2SSrm
+ 1277202830U, // MOVDI2SSrr
+ 135762957U, // MOVDQAmr
+ 2281706509U, // MOVDQArm
+ 1277203469U, // MOVDQArr
+ 135762965U, // MOVDQUmr
+ 135762965U, // MOVDQUmr_Int
+ 2281706517U, // MOVDQUrm
+ 2281706517U, // MOVDQUrm_Int
+ 203461661U, // MOVHLPSrr
+ 135795750U, // MOVHPDmr
+ 603984934U, // MOVHPDrm
+ 135795758U, // MOVHPSmr
+ 603984942U, // MOVHPSrm
+ 203461686U, // MOVLHPSrr
+ 135795775U, // MOVLPDmr
+ 603984959U, // MOVLPDrm
+ 203461703U, // MOVLPDrr
+ 135795790U, // MOVLPSmr
+ 603984974U, // MOVLPSrm
+ 203461718U, // MOVLPSrr
+ 135369134U, // MOVLQ128mr
+ 203461703U, // MOVLSD2PDrr
+ 203461718U, // MOVLSS2PSrr
+ 1277203549U, // MOVMSKPDrr
+ 1277203559U, // MOVMSKPSrr
+ 2281706609U, // MOVNTDQArm
+ 135730299U, // MOVNTDQmr
+ 135337092U, // MOVNTImr
+ 135763084U, // MOVNTPDmr
+ 135763093U, // MOVNTPSmr
0U, // MOVPC32r
- 135795771U, // MOVPD2SDmr
- 1277203515U, // MOVPD2SDrr
- 135336322U, // MOVPDI2DImr
- 1277202818U, // MOVPDI2DIrr
- 135369122U, // MOVPQI2QImr
- 1277202818U, // MOVPQIto64rr
- 135599178U, // MOVPS2SSmr
- 1277203530U, // MOVPS2SSrr
- 1409290658U, // MOVQI2PQIrm
- 1277202850U, // MOVQxrxr
- 2013271099U, // MOVSD2PDrm
- 1277203515U, // MOVSD2PDrr
- 135795771U, // MOVSDmr
- 2013271099U, // MOVSDrm
- 1277203515U, // MOVSDrr
- 135369122U, // MOVSDto64mr
- 1277202818U, // MOVSDto64rr
- 1946162322U, // MOVSHDUPrm
- 1277203602U, // MOVSHDUPrr
- 1946162332U, // MOVSLDUPrm
- 1277203612U, // MOVSLDUPrr
- 135336322U, // MOVSS2DImr
- 1277202818U, // MOVSS2DIrr
- 2080379978U, // MOVSS2PSrm
- 1277203530U, // MOVSS2PSrr
- 135599178U, // MOVSSmr
- 2080379978U, // MOVSSrm
- 1277203530U, // MOVSSrr
+ 135795783U, // MOVPD2SDmr
+ 1277203527U, // MOVPD2SDrr
+ 135336334U, // MOVPDI2DImr
+ 1277202830U, // MOVPDI2DIrr
+ 135369134U, // MOVPQI2QImr
+ 1277202830U, // MOVPQIto64rr
+ 135599190U, // MOVPS2SSmr
+ 1277203542U, // MOVPS2SSrr
+ 1409290670U, // MOVQI2PQIrm
+ 1277202862U, // MOVQxrxr
+ 2013271111U, // MOVSD2PDrm
+ 1277203527U, // MOVSD2PDrr
+ 135795783U, // MOVSDmr
+ 2013271111U, // MOVSDrm
+ 1277203527U, // MOVSDrr
+ 135369134U, // MOVSDto64mr
+ 1277202830U, // MOVSDto64rr
+ 1946162334U, // MOVSHDUPrm
+ 1277203614U, // MOVSHDUPrr
+ 1946162344U, // MOVSLDUPrm
+ 1277203624U, // MOVSLDUPrr
+ 135336334U, // MOVSS2DImr
+ 1277202830U, // MOVSS2DIrr
+ 2080379990U, // MOVSS2PSrm
+ 1277203542U, // MOVSS2PSrr
+ 135599190U, // MOVSSmr
+ 2080379990U, // MOVSSrm
+ 1277203542U, // MOVSSrr
0U, // MOVSX16rm8
- 1684018342U, // MOVSX16rm8W
+ 1684018354U, // MOVSX16rm8W
0U, // MOVSX16rr8
- 1277203622U, // MOVSX16rr8W
- 1207964846U, // MOVSX32rm16
- 1684018358U, // MOVSX32rm8
- 1277203630U, // MOVSX32rr16
- 1277203638U, // MOVSX32rr8
- 1207964862U, // MOVSX64rm16
- 1342182598U, // MOVSX64rm32
- 1684018382U, // MOVSX64rm8
- 1277203646U, // MOVSX64rr16
- 1277203654U, // MOVSX64rr32
- 1277203662U, // MOVSX64rr8
- 135730390U, // MOVUPDmr
- 135730390U, // MOVUPDmr_Int
- 1946162390U, // MOVUPDrm
- 1946162390U, // MOVUPDrm_Int
- 1277203670U, // MOVUPDrr
- 135730398U, // MOVUPSmr
- 135730398U, // MOVUPSmr_Int
- 1946162398U, // MOVUPSrm
- 1946162398U, // MOVUPSrm_Int
- 1277203678U, // MOVUPSrr
- 1342181762U, // MOVZDI2PDIrm
- 1277202818U, // MOVZDI2PDIrr
- 2281705890U, // MOVZPQILo2PQIrm
- 1277202850U, // MOVZPQILo2PQIrr
- 1409290658U, // MOVZQI2PQIrm
- 1277202818U, // MOVZQI2PQIrr
- 2013271099U, // MOVZSD2PDrm
- 2080379978U, // MOVZSS2PSrm
+ 1277203634U, // MOVSX16rr8W
+ 1207964858U, // MOVSX32rm16
+ 1684018370U, // MOVSX32rm8
+ 1277203642U, // MOVSX32rr16
+ 1277203650U, // MOVSX32rr8
+ 1207964874U, // MOVSX64rm16
+ 1342182610U, // MOVSX64rm32
+ 1684018394U, // MOVSX64rm8
+ 1277203658U, // MOVSX64rr16
+ 1277203666U, // MOVSX64rr32
+ 1277203674U, // MOVSX64rr8
+ 135730402U, // MOVUPDmr
+ 135730402U, // MOVUPDmr_Int
+ 1946162402U, // MOVUPDrm
+ 1946162402U, // MOVUPDrm_Int
+ 1277203682U, // MOVUPDrr
+ 135730410U, // MOVUPSmr
+ 135730410U, // MOVUPSmr_Int
+ 1946162410U, // MOVUPSrm
+ 1946162410U, // MOVUPSrm_Int
+ 1277203690U, // MOVUPSrr
+ 1342181774U, // MOVZDI2PDIrm
+ 1277202830U, // MOVZDI2PDIrr
+ 2281705902U, // MOVZPQILo2PQIrm
+ 1277202862U, // MOVZPQILo2PQIrr
+ 1409290670U, // MOVZQI2PQIrm
+ 1277202830U, // MOVZQI2PQIrr
+ 2013271111U, // MOVZSD2PDrm
+ 2080379990U, // MOVZSS2PSrm
0U, // MOVZX16rm8
- 1684018406U, // MOVZX16rm8W
+ 1684018418U, // MOVZX16rm8W
0U, // MOVZX16rr8
- 1277203686U, // MOVZX16rr8W
- 1702892782U, // MOVZX32_NOREXrm8
- 1277596910U, // MOVZX32_NOREXrr8
- 1207964918U, // MOVZX32rm16
- 1684018414U, // MOVZX32rm8
- 1277203702U, // MOVZX32rr16
- 1277203694U, // MOVZX32rr8
+ 1277203698U, // MOVZX16rr8W
+ 1702892794U, // MOVZX32_NOREXrm8
+ 1277596922U, // MOVZX32_NOREXrr8
+ 1207964930U, // MOVZX32rm16
+ 1684018426U, // MOVZX32rm8
+ 1277203714U, // MOVZX32rr16
+ 1277203706U, // MOVZX32rr8
0U, // MOVZX64rm16
- 1207964926U, // MOVZX64rm16_Q
+ 1207964938U, // MOVZX64rm16_Q
0U, // MOVZX64rm32
0U, // MOVZX64rm8
- 1684018438U, // MOVZX64rm8_Q
+ 1684018450U, // MOVZX64rm8_Q
0U, // MOVZX64rr16
- 1277203710U, // MOVZX64rr16_Q
+ 1277203722U, // MOVZX64rr16_Q
0U, // MOVZX64rr32
0U, // MOVZX64rr8
- 1277203718U, // MOVZX64rr8_Q
+ 1277203730U, // MOVZX64rr8_Q
0U, // MOV_Fp3232
0U, // MOV_Fp3264
0U, // MOV_Fp3280
@@ -1454,34 +1457,34 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // MOV_Fp8032
0U, // MOV_Fp8064
0U, // MOV_Fp8080
- 1013978382U, // MPSADBWrmi
- 1073747214U, // MPSADBWrri
- 872420631U, // MUL16m
- 73405719U, // MUL16r
- 945820957U, // MUL32m
- 73405725U, // MUL32r
- 1476400419U, // MUL64m
- 73405731U, // MUL64r
- 1610618153U, // MUL8m
- 73405737U, // MUL8r
- 536876335U, // MULPDrm
- 203461935U, // MULPDrr
- 536876342U, // MULPSrm
- 203461942U, // MULPSrr
- 603985213U, // MULSDrm
- 603985213U, // MULSDrm_Int
- 203461949U, // MULSDrr
- 203461949U, // MULSDrr_Int
- 671094084U, // MULSSrm
- 671094084U, // MULSSrm_Int
- 203461956U, // MULSSrr
- 203461956U, // MULSSrr_Int
- 738202955U, // MUL_F32m
- 805311826U, // MUL_F64m
- 872420697U, // MUL_FI16m
- 945821025U, // MUL_FI32m
- 73405801U, // MUL_FPrST0
- 73405808U, // MUL_FST0r
+ 1013978394U, // MPSADBWrmi
+ 1073747226U, // MPSADBWrri
+ 872420643U, // MUL16m
+ 73405731U, // MUL16r
+ 945820969U, // MUL32m
+ 73405737U, // MUL32r
+ 1476400431U, // MUL64m
+ 73405743U, // MUL64r
+ 1610618165U, // MUL8m
+ 73405749U, // MUL8r
+ 536876347U, // MULPDrm
+ 203461947U, // MULPDrr
+ 536876354U, // MULPSrm
+ 203461954U, // MULPSrr
+ 603985225U, // MULSDrm
+ 603985225U, // MULSDrm_Int
+ 203461961U, // MULSDrr
+ 203461961U, // MULSDrr_Int
+ 671094096U, // MULSSrm
+ 671094096U, // MULSSrm_Int
+ 203461968U, // MULSSrr
+ 203461968U, // MULSSrr_Int
+ 738202967U, // MUL_F32m
+ 805311838U, // MUL_F64m
+ 872420709U, // MUL_FI16m
+ 945821037U, // MUL_FI32m
+ 73405813U, // MUL_FPrST0
+ 73405820U, // MUL_FST0r
0U, // MUL_Fp32
0U, // MUL_Fp32m
0U, // MUL_Fp64
@@ -1496,785 +1499,785 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // MUL_FpI32m32
0U, // MUL_FpI32m64
0U, // MUL_FpI32m80
- 73405814U, // MUL_FrST0
- 5508U, // MWAIT
- 872420746U, // NEG16m
- 73405834U, // NEG16r
- 945821072U, // NEG32m
- 73405840U, // NEG32r
- 1476400534U, // NEG64m
- 73405846U, // NEG64r
- 1610618268U, // NEG8m
- 73405852U, // NEG8r
- 5538U, // NOOP
- 945821094U, // NOOPL
- 872420780U, // NOOPW
- 872420786U, // NOT16m
- 73405874U, // NOT16r
- 945821112U, // NOT32m
- 73405880U, // NOT32r
- 1476400574U, // NOT64m
- 73405886U, // NOT64r
- 1610618308U, // NOT8m
- 73405892U, // NOT8r
- 67114442U, // OR16i16
- 135271882U, // OR16mi
- 135271882U, // OR16mi8
- 135271882U, // OR16mr
- 203462090U, // OR16ri
- 203462090U, // OR16ri8
- 270570954U, // OR16rm
- 203462090U, // OR16rr
- 203462090U, // OR16rr_REV
- 70260175U, // OR32i32
- 135337423U, // OR32mi
- 135337423U, // OR32mi8
- 135337423U, // OR32mr
- 203462095U, // OR32ri
- 203462095U, // OR32ri8
- 337679823U, // OR32rm
- 203462095U, // OR32rr
- 203462095U, // OR32rr_REV
- 71308756U, // OR64i32
- 135370196U, // OR64mi32
- 135370196U, // OR64mi8
- 135370196U, // OR64mr
- 203462100U, // OR64ri32
- 203462100U, // OR64ri8
- 404788692U, // OR64rm
- 203462100U, // OR64rr
- 203462100U, // OR64rr_REV
- 72357337U, // OR8i8
- 135402969U, // OR8mi
- 135402969U, // OR8mr
- 203462105U, // OR8ri
- 471897561U, // OR8rm
- 203462105U, // OR8rr
- 203462105U, // OR8rr_REV
- 536874105U, // ORPDrm
- 203459705U, // ORPDrr
- 536874111U, // ORPSrm
- 203459711U, // ORPSrr
- 73405918U, // OUT16ir
- 5609U, // OUT16rr
- 73405943U, // OUT32ir
- 5635U, // OUT32rr
- 73405970U, // OUT8ir
- 5661U, // OUT8rr
- 5675U, // OUTSB
- 5681U, // OUTSD
- 5687U, // OUTSW
- 2281707069U, // PABSBrm128
- 1409291837U, // PABSBrm64
- 1277204029U, // PABSBrr128
- 1277204029U, // PABSBrr64
- 2281707076U, // PABSDrm128
- 1409291844U, // PABSDrm64
- 1277204036U, // PABSDrr128
- 1277204036U, // PABSDrr64
- 2281707083U, // PABSWrm128
- 1409291851U, // PABSWrm64
- 1277204043U, // PABSWrr128
- 1277204043U, // PABSWrr64
- 1140855208U, // PACKSSDWrm
- 203461032U, // PACKSSDWrr
- 1140855218U, // PACKSSWBrm
- 203461042U, // PACKSSWBrr
- 1140856402U, // PACKUSDWrm
- 203462226U, // PACKUSDWrr
- 1140855228U, // PACKUSWBrm
- 203461052U, // PACKUSWBrr
- 1140855238U, // PADDBrm
- 203461062U, // PADDBrr
- 1140855245U, // PADDDrm
- 203461069U, // PADDDrr
- 1140855252U, // PADDQrm
- 203461076U, // PADDQrr
- 1140855259U, // PADDSBrm
- 203461083U, // PADDSBrr
- 1140855267U, // PADDSWrm
- 203461091U, // PADDSWrr
- 1140855275U, // PADDUSBrm
- 203461099U, // PADDUSBrr
- 1140855284U, // PADDUSWrm
- 203461108U, // PADDUSWrr
- 1140855293U, // PADDWrm
- 203461117U, // PADDWrr
- 1013978716U, // PALIGNR128rm
- 1073747548U, // PALIGNR128rr
- 1030067804U, // PALIGNR64rm
- 1073747548U, // PALIGNR64rr
- 1140855300U, // PANDNrm
- 203461124U, // PANDNrr
- 1140855307U, // PANDrm
- 203461131U, // PANDrr
- 1140855313U, // PAVGBrm
- 203461137U, // PAVGBrr
- 1140855320U, // PAVGWrm
- 203461144U, // PAVGWrr
- 1140856421U, // PBLENDVBrm0
- 203462245U, // PBLENDVBrr0
- 1013978742U, // PBLENDWrmi
- 1073747574U, // PBLENDWrri
- 1140855327U, // PCMPEQBrm
- 203461151U, // PCMPEQBrr
- 1140855336U, // PCMPEQDrm
- 203461160U, // PCMPEQDrr
- 1140856447U, // PCMPEQQrm
- 203462271U, // PCMPEQQrr
- 1140855345U, // PCMPEQWrm
- 203461169U, // PCMPEQWrr
- 2173703816U, // PCMPESTRIArm
- 215324296U, // PCMPESTRIArr
- 2173703816U, // PCMPESTRICrm
- 215324296U, // PCMPESTRICrr
- 2173703816U, // PCMPESTRIOrm
- 215324296U, // PCMPESTRIOrr
- 2173703816U, // PCMPESTRISrm
- 215324296U, // PCMPESTRISrr
- 2173703816U, // PCMPESTRIZrm
- 215324296U, // PCMPESTRIZrr
- 2173703816U, // PCMPESTRIrm
- 215324296U, // PCMPESTRIrr
- 5779U, // PCMPESTRM128MEM
- 5803U, // PCMPESTRM128REG
- 2173703875U, // PCMPESTRM128rm
- 215324355U, // PCMPESTRM128rr
- 1140855354U, // PCMPGTBrm
- 203461178U, // PCMPGTBrr
- 1140855363U, // PCMPGTDrm
- 203461187U, // PCMPGTDrr
- 1140856526U, // PCMPGTQrm
- 203462350U, // PCMPGTQrr
- 1140855372U, // PCMPGTWrm
- 203461196U, // PCMPGTWrr
- 2173703895U, // PCMPISTRIArm
- 215324375U, // PCMPISTRIArr
- 2173703895U, // PCMPISTRICrm
- 215324375U, // PCMPISTRICrr
- 2173703895U, // PCMPISTRIOrm
- 215324375U, // PCMPISTRIOrr
- 2173703895U, // PCMPISTRISrm
- 215324375U, // PCMPISTRISrr
- 2173703895U, // PCMPISTRIZrm
- 215324375U, // PCMPISTRIZrr
- 2173703895U, // PCMPISTRIrm
- 215324375U, // PCMPISTRIrr
- 5858U, // PCMPISTRM128MEM
- 5882U, // PCMPISTRM128REG
- 2173703954U, // PCMPISTRM128rm
- 215324434U, // PCMPISTRM128rr
- 2162300701U, // PEXTRBmr
- 215324445U, // PEXTRBrr
- 2162235173U, // PEXTRDmr
- 215324453U, // PEXTRDrr
- 2162267949U, // PEXTRQmr
- 215324461U, // PEXTRQrr
- 2162168405U, // PEXTRWmr
- 215323221U, // PEXTRWri
- 1140856629U, // PHADDDrm128
- 404789045U, // PHADDDrm64
- 203462453U, // PHADDDrr128
- 203462453U, // PHADDDrr64
- 1140856637U, // PHADDSWrm128
- 404789053U, // PHADDSWrm64
- 203462461U, // PHADDSWrr128
- 203462461U, // PHADDSWrr64
- 1140856646U, // PHADDWrm128
- 404789062U, // PHADDWrm64
- 203462470U, // PHADDWrr128
- 203462470U, // PHADDWrr64
- 2281707342U, // PHMINPOSUWrm128
- 1277204302U, // PHMINPOSUWrr128
- 1140856666U, // PHSUBDrm128
- 404789082U, // PHSUBDrm64
- 203462490U, // PHSUBDrr128
- 203462490U, // PHSUBDrr64
- 1140856674U, // PHSUBSWrm128
- 404789090U, // PHSUBSWrm64
- 203462498U, // PHSUBSWrr128
- 203462498U, // PHSUBSWrr64
- 1140856683U, // PHSUBWrm128
- 404789099U, // PHSUBWrm64
- 203462507U, // PHSUBWrr128
- 203462507U, // PHSUBWrr64
- 1031116659U, // PINSRBrm
- 1073747827U, // PINSRBrr
- 1029019515U, // PINSRDrm
- 1073747835U, // PINSRDrr
- 1030068099U, // PINSRQrm
- 1073747843U, // PINSRQrr
- 1027969629U, // PINSRWrmi
- 1073746525U, // PINSRWrri
- 1140856715U, // PMADDUBSWrm128
- 404789131U, // PMADDUBSWrm64
- 203462539U, // PMADDUBSWrr128
- 203462539U, // PMADDUBSWrr64
- 1140855397U, // PMADDWDrm
- 203461221U, // PMADDWDrr
- 1140856726U, // PMAXSBrm
- 203462550U, // PMAXSBrr
- 1140856734U, // PMAXSDrm
- 203462558U, // PMAXSDrr
- 1140855406U, // PMAXSWrm
- 203461230U, // PMAXSWrr
- 1140855414U, // PMAXUBrm
- 203461238U, // PMAXUBrr
- 1140856742U, // PMAXUDrm
- 203462566U, // PMAXUDrr
- 1140856750U, // PMAXUWrm
- 203462574U, // PMAXUWrr
- 1140856758U, // PMINSBrm
- 203462582U, // PMINSBrr
- 1140856766U, // PMINSDrm
- 203462590U, // PMINSDrr
- 1140855422U, // PMINSWrm
- 203461246U, // PMINSWrr
- 1140855430U, // PMINUBrm
- 203461254U, // PMINUBrr
- 1140856774U, // PMINUDrm
- 203462598U, // PMINUDrr
- 1140856782U, // PMINUWrm
- 203462606U, // PMINUWrr
- 1277203086U, // PMOVMSKBrr
- 1342183382U, // PMOVSXBDrm
- 1277204438U, // PMOVSXBDrr
- 1207965664U, // PMOVSXBQrm
- 1277204448U, // PMOVSXBQrr
- 1409292266U, // PMOVSXBWrm
- 1277204458U, // PMOVSXBWrr
- 1409292276U, // PMOVSXDQrm
- 1277204468U, // PMOVSXDQrr
- 1409292286U, // PMOVSXWDrm
- 1277204478U, // PMOVSXWDrr
- 1342183432U, // PMOVSXWQrm
- 1277204488U, // PMOVSXWQrr
- 1342183442U, // PMOVZXBDrm
- 1277204498U, // PMOVZXBDrr
- 1207965724U, // PMOVZXBQrm
- 1277204508U, // PMOVZXBQrr
- 1409292326U, // PMOVZXBWrm
- 1277204518U, // PMOVZXBWrr
- 1409292336U, // PMOVZXDQrm
- 1277204528U, // PMOVZXDQrr
- 1409292346U, // PMOVZXWDrm
- 1277204538U, // PMOVZXWDrr
- 1342183492U, // PMOVZXWQrm
- 1277204548U, // PMOVZXWQrr
- 1140856910U, // PMULDQrm
- 203462734U, // PMULDQrr
- 1140856918U, // PMULHRSWrm128
- 404789334U, // PMULHRSWrm64
- 203462742U, // PMULHRSWrr128
- 203462742U, // PMULHRSWrr64
- 1140855448U, // PMULHUWrm
- 203461272U, // PMULHUWrr
- 1140855457U, // PMULHWrm
- 203461281U, // PMULHWrr
- 1140856928U, // PMULLDrm
- 1140856928U, // PMULLDrm_int
- 203462752U, // PMULLDrr
- 203462752U, // PMULLDrr_int
- 1140855465U, // PMULLWrm
- 203461289U, // PMULLWrr
- 1140855473U, // PMULUDQrm
- 203461297U, // PMULUDQrr
- 73406568U, // POP16r
- 872421480U, // POP16rmm
- 73406568U, // POP16rmr
- 73406574U, // POP32r
- 945821806U, // POP32rmm
- 73406574U, // POP32rmr
- 73406580U, // POP64r
- 1476401268U, // POP64rmm
- 73406580U, // POP64rmr
- 1207965818U, // POPCNT16rm
- 1277204602U, // POPCNT16rr
- 1342183555U, // POPCNT32rm
- 1277204611U, // POPCNT32rr
- 1409292428U, // POPCNT64rm
- 1277204620U, // POPCNT64rr
- 6293U, // POPF
- 6299U, // POPFD
- 6305U, // POPFQ
- 6311U, // POPFS16
- 6320U, // POPFS32
- 6329U, // POPFS64
- 6338U, // POPGS16
- 6347U, // POPGS32
- 6356U, // POPGS64
- 1140855482U, // PORrm
- 203461306U, // PORrr
- 1610619101U, // PREFETCHNTA
- 1610619114U, // PREFETCHT0
- 1610619126U, // PREFETCHT1
- 1610619138U, // PREFETCHT2
- 1140855487U, // PSADBWrm
- 203461311U, // PSADBWrr
- 1140857102U, // PSHUFBrm128
- 404789518U, // PSHUFBrm64
- 203462926U, // PSHUFBrr128
- 203462926U, // PSHUFBrr64
- 2173704470U, // PSHUFDmi
- 215324950U, // PSHUFDri
- 2173704478U, // PSHUFHWmi
- 215324958U, // PSHUFHWri
- 2173704487U, // PSHUFLWmi
- 215324967U, // PSHUFLWri
- 1140857136U, // PSIGNBrm128
- 404789552U, // PSIGNBrm64
- 203462960U, // PSIGNBrr128
- 203462960U, // PSIGNBrr64
- 1140857144U, // PSIGNDrm128
- 404789560U, // PSIGNDrm64
- 203462968U, // PSIGNDrr128
- 203462968U, // PSIGNDrr64
- 1140857152U, // PSIGNWrm128
- 404789568U, // PSIGNWrm64
- 203462976U, // PSIGNWrr128
- 203462976U, // PSIGNWrr64
- 203462984U, // PSLLDQri
- 203461327U, // PSLLDri
- 1140855503U, // PSLLDrm
- 203461327U, // PSLLDrr
- 203461334U, // PSLLQri
- 1140855510U, // PSLLQrm
- 203461334U, // PSLLQrr
- 203461341U, // PSLLWri
- 1140855517U, // PSLLWrm
- 203461341U, // PSLLWrr
- 203461348U, // PSRADri
- 1140855524U, // PSRADrm
- 203461348U, // PSRADrr
- 203461355U, // PSRAWri
- 1140855531U, // PSRAWrm
- 203461355U, // PSRAWrr
- 203462992U, // PSRLDQri
- 203461362U, // PSRLDri
- 1140855538U, // PSRLDrm
- 203461362U, // PSRLDrr
- 203461369U, // PSRLQri
- 1140855545U, // PSRLQrm
- 203461369U, // PSRLQrr
- 203461376U, // PSRLWri
- 1140855552U, // PSRLWrm
- 203461376U, // PSRLWrr
- 1140855559U, // PSUBBrm
- 203461383U, // PSUBBrr
- 1140855566U, // PSUBDrm
- 203461390U, // PSUBDrr
- 1140855573U, // PSUBQrm
- 203461397U, // PSUBQrr
- 1140855580U, // PSUBSBrm
- 203461404U, // PSUBSBrr
- 1140855588U, // PSUBSWrm
- 203461412U, // PSUBSWrr
- 1140855596U, // PSUBUSBrm
- 203461420U, // PSUBUSBrr
- 1140855605U, // PSUBUSWrm
- 203461429U, // PSUBUSWrr
- 1140855614U, // PSUBWrm
- 203461438U, // PSUBWrr
- 2281707864U, // PTESTrm
- 1277204824U, // PTESTrr
- 1140855621U, // PUNPCKHBWrm
- 203461445U, // PUNPCKHBWrr
- 1140855632U, // PUNPCKHDQrm
- 203461456U, // PUNPCKHDQrr
- 1140857184U, // PUNPCKHQDQrm
- 203463008U, // PUNPCKHQDQrr
- 1140855643U, // PUNPCKHWDrm
- 203461467U, // PUNPCKHWDrr
- 1140855654U, // PUNPCKLBWrm
- 203461478U, // PUNPCKLBWrr
- 1140855665U, // PUNPCKLDQrm
- 203461489U, // PUNPCKLDQrr
- 1140857196U, // PUNPCKLQDQrm
- 203463020U, // PUNPCKLQDQrr
- 1140855676U, // PUNPCKLWDrm
- 203461500U, // PUNPCKLWDrr
- 73406840U, // PUSH16r
- 872421752U, // PUSH16rmm
- 73406840U, // PUSH16rmr
- 73406847U, // PUSH32i16
- 73406847U, // PUSH32i32
- 73406847U, // PUSH32i8
- 73406847U, // PUSH32r
- 945822079U, // PUSH32rmm
- 73406847U, // PUSH32rmr
- 73406854U, // PUSH64i16
- 73406854U, // PUSH64i32
- 73406854U, // PUSH64i8
- 73406854U, // PUSH64r
- 1476401542U, // PUSH64rmm
- 73406854U, // PUSH64rmr
- 6541U, // PUSHF
- 6548U, // PUSHFD
- 6555U, // PUSHFQ64
- 6562U, // PUSHFS16
- 6572U, // PUSHFS32
- 6582U, // PUSHFS64
- 6592U, // PUSHGS16
- 6602U, // PUSHGS32
- 6612U, // PUSHGS64
- 1140853859U, // PXORrm
- 203459683U, // PXORrr
- 872421854U, // RCL16m1
- 872421863U, // RCL16mCL
- 2711624178U, // RCL16mi
- 73406942U, // RCL16r1
- 73406951U, // RCL16rCL
- 203463154U, // RCL16ri
- 945822200U, // RCL32m1
- 945822209U, // RCL32mCL
- 2712672780U, // RCL32mi
- 73406968U, // RCL32r1
- 73406977U, // RCL32rCL
- 203463180U, // RCL32ri
- 1476401682U, // RCL64m1
- 1476401691U, // RCL64mCL
- 2713721382U, // RCL64mi
- 73406994U, // RCL64r1
- 73407003U, // RCL64rCL
- 203463206U, // RCL64ri
- 1610619436U, // RCL8m1
- 1610619445U, // RCL8mCL
- 2714769984U, // RCL8mi
- 73407020U, // RCL8r1
- 73407029U, // RCL8rCL
- 203463232U, // RCL8ri
- 1946163782U, // RCPPSm
- 1946163782U, // RCPPSm_Int
- 1277205062U, // RCPPSr
- 1277205062U, // RCPPSr_Int
- 2080381517U, // RCPSSm
- 2080381517U, // RCPSSm_Int
- 1277205069U, // RCPSSr
- 1277205069U, // RCPSSr_Int
- 872421972U, // RCR16m1
- 872421981U, // RCR16mCL
- 2711624296U, // RCR16mi
- 73407060U, // RCR16r1
- 73407069U, // RCR16rCL
- 203463272U, // RCR16ri
- 945822318U, // RCR32m1
- 945822327U, // RCR32mCL
- 2712672898U, // RCR32mi
- 73407086U, // RCR32r1
- 73407095U, // RCR32rCL
- 203463298U, // RCR32ri
- 1476401800U, // RCR64m1
- 1476401809U, // RCR64mCL
- 2713721500U, // RCR64mi
- 73407112U, // RCR64r1
- 73407121U, // RCR64rCL
- 203463324U, // RCR64ri
- 1610619554U, // RCR8m1
- 1610619563U, // RCR8mCL
- 2714770102U, // RCR8mi
- 73407138U, // RCR8r1
- 73407147U, // RCR8rCL
- 203463350U, // RCR8ri
- 6844U, // RDMSR
- 6850U, // RDPMC
- 6856U, // RDTSC
- 6862U, // REP_MOVSB
- 6872U, // REP_MOVSD
- 6882U, // REP_MOVSQ
- 6892U, // REP_MOVSW
- 6902U, // REP_STOSB
- 6912U, // REP_STOSD
- 6922U, // REP_STOSQ
- 6932U, // REP_STOSW
- 6942U, // RET
- 73407266U, // RETI
- 872422183U, // ROL16m1
- 872422189U, // ROL16mCL
- 135273255U, // ROL16mi
- 73407271U, // ROL16r1
- 73407277U, // ROL16rCL
- 203463463U, // ROL16ri
- 945822520U, // ROL32m1
- 945822526U, // ROL32mCL
- 135338808U, // ROL32mi
- 73407288U, // ROL32r1
- 73407294U, // ROL32rCL
- 203463480U, // ROL32ri
- 1476401993U, // ROL64m1
- 1476401999U, // ROL64mCL
- 135371593U, // ROL64mi
- 73407305U, // ROL64r1
- 73407311U, // ROL64rCL
- 203463497U, // ROL64ri
- 1610619738U, // ROL8m1
- 1610619744U, // ROL8mCL
- 135404378U, // ROL8mi
- 73407322U, // ROL8r1
- 73407328U, // ROL8rCL
- 203463514U, // ROL8ri
- 872422251U, // ROR16m1
- 872422257U, // ROR16mCL
- 135273323U, // ROR16mi
- 73407339U, // ROR16r1
- 73407345U, // ROR16rCL
- 203463531U, // ROR16ri
- 945822588U, // ROR32m1
- 945822594U, // ROR32mCL
- 135338876U, // ROR32mi
- 73407356U, // ROR32r1
- 73407362U, // ROR32rCL
- 203463548U, // ROR32ri
- 1476402061U, // ROR64m1
- 1476402067U, // ROR64mCL
- 135371661U, // ROR64mi
- 73407373U, // ROR64r1
- 73407379U, // ROR64rCL
- 203463565U, // ROR64ri
- 1610619806U, // ROR8m1
- 1610619812U, // ROR8mCL
- 135404446U, // ROR8mi
- 73407390U, // ROR8r1
- 73407396U, // ROR8rCL
- 203463582U, // ROR8ri
- 2178948015U, // ROUNDPDm_Int
- 215325615U, // ROUNDPDr_Int
- 2178948024U, // ROUNDPSm_Int
- 215325624U, // ROUNDPSr_Int
- 1039145921U, // ROUNDSDm_Int
- 1073748929U, // ROUNDSDr_Int
- 1025514442U, // ROUNDSSm_Int
- 1073748938U, // ROUNDSSr_Int
- 7123U, // RSM
- 1946164183U, // RSQRTPSm
- 1946164183U, // RSQRTPSm_Int
- 1277205463U, // RSQRTPSr
- 1277205463U, // RSQRTPSr_Int
- 2080381920U, // RSQRTSSm
- 2080381920U, // RSQRTSSm_Int
- 1277205472U, // RSQRTSSr
- 1277205472U, // RSQRTSSr_Int
- 7145U, // SAHF
- 872422382U, // SAR16m1
- 872422388U, // SAR16mCL
- 135273454U, // SAR16mi
- 73407470U, // SAR16r1
- 73407476U, // SAR16rCL
- 203463662U, // SAR16ri
- 945822719U, // SAR32m1
- 945822725U, // SAR32mCL
- 135339007U, // SAR32mi
- 73407487U, // SAR32r1
- 73407493U, // SAR32rCL
- 203463679U, // SAR32ri
- 1476402192U, // SAR64m1
- 1476402198U, // SAR64mCL
- 135371792U, // SAR64mi
- 73407504U, // SAR64r1
- 73407510U, // SAR64rCL
- 203463696U, // SAR64ri
- 1610619937U, // SAR8m1
- 1610619943U, // SAR8mCL
- 135404577U, // SAR8mi
- 73407521U, // SAR8r1
- 73407527U, // SAR8rCL
- 203463713U, // SAR8ri
- 67116082U, // SBB16i16
- 135273522U, // SBB16mi
- 135273522U, // SBB16mi8
- 135273522U, // SBB16mr
- 203463730U, // SBB16ri
- 203463730U, // SBB16ri8
- 270572594U, // SBB16rm
- 203463730U, // SBB16rr
- 203463730U, // SBB16rr_REV
- 70261816U, // SBB32i32
- 135339064U, // SBB32mi
- 135339064U, // SBB32mi8
- 135339064U, // SBB32mr
- 203463736U, // SBB32ri
- 203463736U, // SBB32ri8
- 337681464U, // SBB32rm
- 203463736U, // SBB32rr
- 203463736U, // SBB32rr_REV
- 71310398U, // SBB64i32
- 135371838U, // SBB64mi32
- 135371838U, // SBB64mi8
- 135371838U, // SBB64mr
- 203463742U, // SBB64ri32
- 203463742U, // SBB64ri8
- 404790334U, // SBB64rm
- 203463742U, // SBB64rr
- 203463742U, // SBB64rr_REV
- 72358980U, // SBB8i8
- 135404612U, // SBB8mi
- 135404612U, // SBB8mr
- 203463748U, // SBB8ri
- 471899204U, // SBB8rm
- 203463748U, // SBB8rr
- 203463748U, // SBB8rr_REV
- 7242U, // SCAS16
- 7248U, // SCAS32
- 7254U, // SCAS64
- 7260U, // SCAS8
- 1610620002U, // SETAEm
- 73407586U, // SETAEr
- 1610620009U, // SETAm
- 73407593U, // SETAr
- 1610620015U, // SETBEm
- 73407599U, // SETBEr
- 68557874U, // SETB_C16r
- 68557880U, // SETB_C32r
- 68557886U, // SETB_C64r
- 68557892U, // SETB_C8r
- 1610620022U, // SETBm
- 73407606U, // SETBr
- 1610620028U, // SETEm
- 73407612U, // SETEr
- 1610620034U, // SETGEm
- 73407618U, // SETGEr
- 1610620041U, // SETGm
- 73407625U, // SETGr
- 1610620047U, // SETLEm
- 73407631U, // SETLEr
- 1610620054U, // SETLm
- 73407638U, // SETLr
- 1610620060U, // SETNEm
- 73407644U, // SETNEr
- 1610620067U, // SETNOm
- 73407651U, // SETNOr
- 1610620074U, // SETNPm
- 73407658U, // SETNPr
- 1610620081U, // SETNSm
- 73407665U, // SETNSr
- 1610620088U, // SETOm
- 73407672U, // SETOr
- 1610620094U, // SETPm
- 73407678U, // SETPr
- 1610620100U, // SETSm
- 73407684U, // SETSr
- 7370U, // SFENCE
- 2214599889U, // SGDTm
- 872422615U, // SHL16m1
- 872422621U, // SHL16mCL
- 135273687U, // SHL16mi
- 73407703U, // SHL16r1
- 73407709U, // SHL16rCL
- 203463895U, // SHL16ri
- 945822952U, // SHL32m1
- 945822958U, // SHL32mCL
- 135339240U, // SHL32mi
- 73407720U, // SHL32r1
- 73407726U, // SHL32rCL
- 203463912U, // SHL32ri
- 1476402425U, // SHL64m1
- 1476402431U, // SHL64mCL
- 135372025U, // SHL64mi
- 73407737U, // SHL64r1
- 73407743U, // SHL64rCL
- 203463929U, // SHL64ri
- 1610620170U, // SHL8m1
- 1610620176U, // SHL8mCL
- 135404810U, // SHL8mi
- 73407754U, // SHL8r1
- 73407760U, // SHL8rCL
- 203463946U, // SHL8ri
- 135273755U, // SHLD16mrCL
- 2162171175U, // SHLD16mri8
- 203463963U, // SHLD16rrCL
- 1073749287U, // SHLD16rri8
- 135339310U, // SHLD32mrCL
- 2162236730U, // SHLD32mri8
- 203463982U, // SHLD32rrCL
- 1073749306U, // SHLD32rri8
- 135372097U, // SHLD64mrCL
- 2162269517U, // SHLD64mri8
- 203464001U, // SHLD64rrCL
- 1073749325U, // SHLD64rri8
- 872422740U, // SHR16m1
- 872422746U, // SHR16mCL
- 135273812U, // SHR16mi
- 73407828U, // SHR16r1
- 73407834U, // SHR16rCL
- 203464020U, // SHR16ri
- 945823077U, // SHR32m1
- 945823083U, // SHR32mCL
- 135339365U, // SHR32mi
- 73407845U, // SHR32r1
- 73407851U, // SHR32rCL
- 203464037U, // SHR32ri
- 1476402550U, // SHR64m1
- 1476402556U, // SHR64mCL
- 135372150U, // SHR64mi
- 73407862U, // SHR64r1
- 73407868U, // SHR64rCL
- 203464054U, // SHR64ri
- 1610620295U, // SHR8m1
- 1610620301U, // SHR8mCL
- 135404935U, // SHR8mi
- 73407879U, // SHR8r1
- 73407885U, // SHR8rCL
- 203464071U, // SHR8ri
- 135273880U, // SHRD16mrCL
- 2162171300U, // SHRD16mri8
- 203464088U, // SHRD16rrCL
- 1073749412U, // SHRD16rri8
- 135339435U, // SHRD32mrCL
- 2162236855U, // SHRD32mri8
- 203464107U, // SHRD32rrCL
- 1073749431U, // SHRD32rri8
- 135372222U, // SHRD64mrCL
- 2162269642U, // SHRD64mri8
- 203464126U, // SHRD64rrCL
- 1073749450U, // SHRD64rri8
- 1040195025U, // SHUFPDrmi
- 1073749457U, // SHUFPDrri
- 1040195033U, // SHUFPSrmi
- 1073749465U, // SHUFPSrri
- 2214600161U, // SIDTm
- 7655U, // SIN_F
+ 73405826U, // MUL_FrST0
+ 5520U, // MWAIT
+ 872420758U, // NEG16m
+ 73405846U, // NEG16r
+ 945821084U, // NEG32m
+ 73405852U, // NEG32r
+ 1476400546U, // NEG64m
+ 73405858U, // NEG64r
+ 1610618280U, // NEG8m
+ 73405864U, // NEG8r
+ 5550U, // NOOP
+ 945821106U, // NOOPL
+ 872420792U, // NOOPW
+ 872420798U, // NOT16m
+ 73405886U, // NOT16r
+ 945821124U, // NOT32m
+ 73405892U, // NOT32r
+ 1476400586U, // NOT64m
+ 73405898U, // NOT64r
+ 1610618320U, // NOT8m
+ 73405904U, // NOT8r
+ 67114454U, // OR16i16
+ 135271894U, // OR16mi
+ 135271894U, // OR16mi8
+ 135271894U, // OR16mr
+ 203462102U, // OR16ri
+ 203462102U, // OR16ri8
+ 270570966U, // OR16rm
+ 203462102U, // OR16rr
+ 203462102U, // OR16rr_REV
+ 70260187U, // OR32i32
+ 135337435U, // OR32mi
+ 135337435U, // OR32mi8
+ 135337435U, // OR32mr
+ 203462107U, // OR32ri
+ 203462107U, // OR32ri8
+ 337679835U, // OR32rm
+ 203462107U, // OR32rr
+ 203462107U, // OR32rr_REV
+ 71308768U, // OR64i32
+ 135370208U, // OR64mi32
+ 135370208U, // OR64mi8
+ 135370208U, // OR64mr
+ 203462112U, // OR64ri32
+ 203462112U, // OR64ri8
+ 404788704U, // OR64rm
+ 203462112U, // OR64rr
+ 203462112U, // OR64rr_REV
+ 72357349U, // OR8i8
+ 135402981U, // OR8mi
+ 135402981U, // OR8mr
+ 203462117U, // OR8ri
+ 471897573U, // OR8rm
+ 203462117U, // OR8rr
+ 203462117U, // OR8rr_REV
+ 536874117U, // ORPDrm
+ 203459717U, // ORPDrr
+ 536874123U, // ORPSrm
+ 203459723U, // ORPSrr
+ 73405930U, // OUT16ir
+ 5621U, // OUT16rr
+ 73405955U, // OUT32ir
+ 5647U, // OUT32rr
+ 73405982U, // OUT8ir
+ 5673U, // OUT8rr
+ 5687U, // OUTSB
+ 5693U, // OUTSD
+ 5699U, // OUTSW
+ 2281707081U, // PABSBrm128
+ 1409291849U, // PABSBrm64
+ 1277204041U, // PABSBrr128
+ 1277204041U, // PABSBrr64
+ 2281707088U, // PABSDrm128
+ 1409291856U, // PABSDrm64
+ 1277204048U, // PABSDrr128
+ 1277204048U, // PABSDrr64
+ 2281707095U, // PABSWrm128
+ 1409291863U, // PABSWrm64
+ 1277204055U, // PABSWrr128
+ 1277204055U, // PABSWrr64
+ 1140855220U, // PACKSSDWrm
+ 203461044U, // PACKSSDWrr
+ 1140855230U, // PACKSSWBrm
+ 203461054U, // PACKSSWBrr
+ 1140856414U, // PACKUSDWrm
+ 203462238U, // PACKUSDWrr
+ 1140855240U, // PACKUSWBrm
+ 203461064U, // PACKUSWBrr
+ 1140855250U, // PADDBrm
+ 203461074U, // PADDBrr
+ 1140855257U, // PADDDrm
+ 203461081U, // PADDDrr
+ 1140855264U, // PADDQrm
+ 203461088U, // PADDQrr
+ 1140855271U, // PADDSBrm
+ 203461095U, // PADDSBrr
+ 1140855279U, // PADDSWrm
+ 203461103U, // PADDSWrr
+ 1140855287U, // PADDUSBrm
+ 203461111U, // PADDUSBrr
+ 1140855296U, // PADDUSWrm
+ 203461120U, // PADDUSWrr
+ 1140855305U, // PADDWrm
+ 203461129U, // PADDWrr
+ 1013978728U, // PALIGNR128rm
+ 1073747560U, // PALIGNR128rr
+ 1030067816U, // PALIGNR64rm
+ 1073747560U, // PALIGNR64rr
+ 1140855312U, // PANDNrm
+ 203461136U, // PANDNrr
+ 1140855319U, // PANDrm
+ 203461143U, // PANDrr
+ 1140855325U, // PAVGBrm
+ 203461149U, // PAVGBrr
+ 1140855332U, // PAVGWrm
+ 203461156U, // PAVGWrr
+ 1140856433U, // PBLENDVBrm0
+ 203462257U, // PBLENDVBrr0
+ 1013978754U, // PBLENDWrmi
+ 1073747586U, // PBLENDWrri
+ 1140855339U, // PCMPEQBrm
+ 203461163U, // PCMPEQBrr
+ 1140855348U, // PCMPEQDrm
+ 203461172U, // PCMPEQDrr
+ 1140856459U, // PCMPEQQrm
+ 203462283U, // PCMPEQQrr
+ 1140855357U, // PCMPEQWrm
+ 203461181U, // PCMPEQWrr
+ 2173703828U, // PCMPESTRIArm
+ 215324308U, // PCMPESTRIArr
+ 2173703828U, // PCMPESTRICrm
+ 215324308U, // PCMPESTRICrr
+ 2173703828U, // PCMPESTRIOrm
+ 215324308U, // PCMPESTRIOrr
+ 2173703828U, // PCMPESTRISrm
+ 215324308U, // PCMPESTRISrr
+ 2173703828U, // PCMPESTRIZrm
+ 215324308U, // PCMPESTRIZrr
+ 2173703828U, // PCMPESTRIrm
+ 215324308U, // PCMPESTRIrr
+ 5791U, // PCMPESTRM128MEM
+ 5815U, // PCMPESTRM128REG
+ 2173703887U, // PCMPESTRM128rm
+ 215324367U, // PCMPESTRM128rr
+ 1140855366U, // PCMPGTBrm
+ 203461190U, // PCMPGTBrr
+ 1140855375U, // PCMPGTDrm
+ 203461199U, // PCMPGTDrr
+ 1140856538U, // PCMPGTQrm
+ 203462362U, // PCMPGTQrr
+ 1140855384U, // PCMPGTWrm
+ 203461208U, // PCMPGTWrr
+ 2173703907U, // PCMPISTRIArm
+ 215324387U, // PCMPISTRIArr
+ 2173703907U, // PCMPISTRICrm
+ 215324387U, // PCMPISTRICrr
+ 2173703907U, // PCMPISTRIOrm
+ 215324387U, // PCMPISTRIOrr
+ 2173703907U, // PCMPISTRISrm
+ 215324387U, // PCMPISTRISrr
+ 2173703907U, // PCMPISTRIZrm
+ 215324387U, // PCMPISTRIZrr
+ 2173703907U, // PCMPISTRIrm
+ 215324387U, // PCMPISTRIrr
+ 5870U, // PCMPISTRM128MEM
+ 5894U, // PCMPISTRM128REG
+ 2173703966U, // PCMPISTRM128rm
+ 215324446U, // PCMPISTRM128rr
+ 2162300713U, // PEXTRBmr
+ 215324457U, // PEXTRBrr
+ 2162235185U, // PEXTRDmr
+ 215324465U, // PEXTRDrr
+ 2162267961U, // PEXTRQmr
+ 215324473U, // PEXTRQrr
+ 2162168417U, // PEXTRWmr
+ 215323233U, // PEXTRWri
+ 1140856641U, // PHADDDrm128
+ 404789057U, // PHADDDrm64
+ 203462465U, // PHADDDrr128
+ 203462465U, // PHADDDrr64
+ 1140856649U, // PHADDSWrm128
+ 404789065U, // PHADDSWrm64
+ 203462473U, // PHADDSWrr128
+ 203462473U, // PHADDSWrr64
+ 1140856658U, // PHADDWrm128
+ 404789074U, // PHADDWrm64
+ 203462482U, // PHADDWrr128
+ 203462482U, // PHADDWrr64
+ 2281707354U, // PHMINPOSUWrm128
+ 1277204314U, // PHMINPOSUWrr128
+ 1140856678U, // PHSUBDrm128
+ 404789094U, // PHSUBDrm64
+ 203462502U, // PHSUBDrr128
+ 203462502U, // PHSUBDrr64
+ 1140856686U, // PHSUBSWrm128
+ 404789102U, // PHSUBSWrm64
+ 203462510U, // PHSUBSWrr128
+ 203462510U, // PHSUBSWrr64
+ 1140856695U, // PHSUBWrm128
+ 404789111U, // PHSUBWrm64
+ 203462519U, // PHSUBWrr128
+ 203462519U, // PHSUBWrr64
+ 1031116671U, // PINSRBrm
+ 1073747839U, // PINSRBrr
+ 1029019527U, // PINSRDrm
+ 1073747847U, // PINSRDrr
+ 1030068111U, // PINSRQrm
+ 1073747855U, // PINSRQrr
+ 1027969641U, // PINSRWrmi
+ 1073746537U, // PINSRWrri
+ 1140856727U, // PMADDUBSWrm128
+ 404789143U, // PMADDUBSWrm64
+ 203462551U, // PMADDUBSWrr128
+ 203462551U, // PMADDUBSWrr64
+ 1140855409U, // PMADDWDrm
+ 203461233U, // PMADDWDrr
+ 1140856738U, // PMAXSBrm
+ 203462562U, // PMAXSBrr
+ 1140856746U, // PMAXSDrm
+ 203462570U, // PMAXSDrr
+ 1140855418U, // PMAXSWrm
+ 203461242U, // PMAXSWrr
+ 1140855426U, // PMAXUBrm
+ 203461250U, // PMAXUBrr
+ 1140856754U, // PMAXUDrm
+ 203462578U, // PMAXUDrr
+ 1140856762U, // PMAXUWrm
+ 203462586U, // PMAXUWrr
+ 1140856770U, // PMINSBrm
+ 203462594U, // PMINSBrr
+ 1140856778U, // PMINSDrm
+ 203462602U, // PMINSDrr
+ 1140855434U, // PMINSWrm
+ 203461258U, // PMINSWrr
+ 1140855442U, // PMINUBrm
+ 203461266U, // PMINUBrr
+ 1140856786U, // PMINUDrm
+ 203462610U, // PMINUDrr
+ 1140856794U, // PMINUWrm
+ 203462618U, // PMINUWrr
+ 1277203098U, // PMOVMSKBrr
+ 1342183394U, // PMOVSXBDrm
+ 1277204450U, // PMOVSXBDrr
+ 1207965676U, // PMOVSXBQrm
+ 1277204460U, // PMOVSXBQrr
+ 1409292278U, // PMOVSXBWrm
+ 1277204470U, // PMOVSXBWrr
+ 1409292288U, // PMOVSXDQrm
+ 1277204480U, // PMOVSXDQrr
+ 1409292298U, // PMOVSXWDrm
+ 1277204490U, // PMOVSXWDrr
+ 1342183444U, // PMOVSXWQrm
+ 1277204500U, // PMOVSXWQrr
+ 1342183454U, // PMOVZXBDrm
+ 1277204510U, // PMOVZXBDrr
+ 1207965736U, // PMOVZXBQrm
+ 1277204520U, // PMOVZXBQrr
+ 1409292338U, // PMOVZXBWrm
+ 1277204530U, // PMOVZXBWrr
+ 1409292348U, // PMOVZXDQrm
+ 1277204540U, // PMOVZXDQrr
+ 1409292358U, // PMOVZXWDrm
+ 1277204550U, // PMOVZXWDrr
+ 1342183504U, // PMOVZXWQrm
+ 1277204560U, // PMOVZXWQrr
+ 1140856922U, // PMULDQrm
+ 203462746U, // PMULDQrr
+ 1140856930U, // PMULHRSWrm128
+ 404789346U, // PMULHRSWrm64
+ 203462754U, // PMULHRSWrr128
+ 203462754U, // PMULHRSWrr64
+ 1140855460U, // PMULHUWrm
+ 203461284U, // PMULHUWrr
+ 1140855469U, // PMULHWrm
+ 203461293U, // PMULHWrr
+ 1140856940U, // PMULLDrm
+ 1140856940U, // PMULLDrm_int
+ 203462764U, // PMULLDrr
+ 203462764U, // PMULLDrr_int
+ 1140855477U, // PMULLWrm
+ 203461301U, // PMULLWrr
+ 1140855485U, // PMULUDQrm
+ 203461309U, // PMULUDQrr
+ 73406580U, // POP16r
+ 872421492U, // POP16rmm
+ 73406580U, // POP16rmr
+ 73406586U, // POP32r
+ 945821818U, // POP32rmm
+ 73406586U, // POP32rmr
+ 73406592U, // POP64r
+ 1476401280U, // POP64rmm
+ 73406592U, // POP64rmr
+ 1207965830U, // POPCNT16rm
+ 1277204614U, // POPCNT16rr
+ 1342183567U, // POPCNT32rm
+ 1277204623U, // POPCNT32rr
+ 1409292440U, // POPCNT64rm
+ 1277204632U, // POPCNT64rr
+ 6305U, // POPF
+ 6311U, // POPFD
+ 6317U, // POPFQ
+ 6323U, // POPFS16
+ 6332U, // POPFS32
+ 6341U, // POPFS64
+ 6350U, // POPGS16
+ 6359U, // POPGS32
+ 6368U, // POPGS64
+ 1140855494U, // PORrm
+ 203461318U, // PORrr
+ 1610619113U, // PREFETCHNTA
+ 1610619126U, // PREFETCHT0
+ 1610619138U, // PREFETCHT1
+ 1610619150U, // PREFETCHT2
+ 1140855499U, // PSADBWrm
+ 203461323U, // PSADBWrr
+ 1140857114U, // PSHUFBrm128
+ 404789530U, // PSHUFBrm64
+ 203462938U, // PSHUFBrr128
+ 203462938U, // PSHUFBrr64
+ 2173704482U, // PSHUFDmi
+ 215324962U, // PSHUFDri
+ 2173704490U, // PSHUFHWmi
+ 215324970U, // PSHUFHWri
+ 2173704499U, // PSHUFLWmi
+ 215324979U, // PSHUFLWri
+ 1140857148U, // PSIGNBrm128
+ 404789564U, // PSIGNBrm64
+ 203462972U, // PSIGNBrr128
+ 203462972U, // PSIGNBrr64
+ 1140857156U, // PSIGNDrm128
+ 404789572U, // PSIGNDrm64
+ 203462980U, // PSIGNDrr128
+ 203462980U, // PSIGNDrr64
+ 1140857164U, // PSIGNWrm128
+ 404789580U, // PSIGNWrm64
+ 203462988U, // PSIGNWrr128
+ 203462988U, // PSIGNWrr64
+ 203462996U, // PSLLDQri
+ 203461339U, // PSLLDri
+ 1140855515U, // PSLLDrm
+ 203461339U, // PSLLDrr
+ 203461346U, // PSLLQri
+ 1140855522U, // PSLLQrm
+ 203461346U, // PSLLQrr
+ 203461353U, // PSLLWri
+ 1140855529U, // PSLLWrm
+ 203461353U, // PSLLWrr
+ 203461360U, // PSRADri
+ 1140855536U, // PSRADrm
+ 203461360U, // PSRADrr
+ 203461367U, // PSRAWri
+ 1140855543U, // PSRAWrm
+ 203461367U, // PSRAWrr
+ 203463004U, // PSRLDQri
+ 203461374U, // PSRLDri
+ 1140855550U, // PSRLDrm
+ 203461374U, // PSRLDrr
+ 203461381U, // PSRLQri
+ 1140855557U, // PSRLQrm
+ 203461381U, // PSRLQrr
+ 203461388U, // PSRLWri
+ 1140855564U, // PSRLWrm
+ 203461388U, // PSRLWrr
+ 1140855571U, // PSUBBrm
+ 203461395U, // PSUBBrr
+ 1140855578U, // PSUBDrm
+ 203461402U, // PSUBDrr
+ 1140855585U, // PSUBQrm
+ 203461409U, // PSUBQrr
+ 1140855592U, // PSUBSBrm
+ 203461416U, // PSUBSBrr
+ 1140855600U, // PSUBSWrm
+ 203461424U, // PSUBSWrr
+ 1140855608U, // PSUBUSBrm
+ 203461432U, // PSUBUSBrr
+ 1140855617U, // PSUBUSWrm
+ 203461441U, // PSUBUSWrr
+ 1140855626U, // PSUBWrm
+ 203461450U, // PSUBWrr
+ 2281707876U, // PTESTrm
+ 1277204836U, // PTESTrr
+ 1140855633U, // PUNPCKHBWrm
+ 203461457U, // PUNPCKHBWrr
+ 1140855644U, // PUNPCKHDQrm
+ 203461468U, // PUNPCKHDQrr
+ 1140857196U, // PUNPCKHQDQrm
+ 203463020U, // PUNPCKHQDQrr
+ 1140855655U, // PUNPCKHWDrm
+ 203461479U, // PUNPCKHWDrr
+ 1140855666U, // PUNPCKLBWrm
+ 203461490U, // PUNPCKLBWrr
+ 1140855677U, // PUNPCKLDQrm
+ 203461501U, // PUNPCKLDQrr
+ 1140857208U, // PUNPCKLQDQrm
+ 203463032U, // PUNPCKLQDQrr
+ 1140855688U, // PUNPCKLWDrm
+ 203461512U, // PUNPCKLWDrr
+ 73406852U, // PUSH16r
+ 872421764U, // PUSH16rmm
+ 73406852U, // PUSH16rmr
+ 73406859U, // PUSH32i16
+ 73406859U, // PUSH32i32
+ 73406859U, // PUSH32i8
+ 73406859U, // PUSH32r
+ 945822091U, // PUSH32rmm
+ 73406859U, // PUSH32rmr
+ 73406866U, // PUSH64i16
+ 73406866U, // PUSH64i32
+ 73406866U, // PUSH64i8
+ 73406866U, // PUSH64r
+ 1476401554U, // PUSH64rmm
+ 73406866U, // PUSH64rmr
+ 6553U, // PUSHF
+ 6560U, // PUSHFD
+ 6567U, // PUSHFQ64
+ 6574U, // PUSHFS16
+ 6584U, // PUSHFS32
+ 6594U, // PUSHFS64
+ 6604U, // PUSHGS16
+ 6614U, // PUSHGS32
+ 6624U, // PUSHGS64
+ 1140853871U, // PXORrm
+ 203459695U, // PXORrr
+ 872421866U, // RCL16m1
+ 872421875U, // RCL16mCL
+ 2711624190U, // RCL16mi
+ 73406954U, // RCL16r1
+ 73406963U, // RCL16rCL
+ 203463166U, // RCL16ri
+ 945822212U, // RCL32m1
+ 945822221U, // RCL32mCL
+ 2712672792U, // RCL32mi
+ 73406980U, // RCL32r1
+ 73406989U, // RCL32rCL
+ 203463192U, // RCL32ri
+ 1476401694U, // RCL64m1
+ 1476401703U, // RCL64mCL
+ 2713721394U, // RCL64mi
+ 73407006U, // RCL64r1
+ 73407015U, // RCL64rCL
+ 203463218U, // RCL64ri
+ 1610619448U, // RCL8m1
+ 1610619457U, // RCL8mCL
+ 2714769996U, // RCL8mi
+ 73407032U, // RCL8r1
+ 73407041U, // RCL8rCL
+ 203463244U, // RCL8ri
+ 1946163794U, // RCPPSm
+ 1946163794U, // RCPPSm_Int
+ 1277205074U, // RCPPSr
+ 1277205074U, // RCPPSr_Int
+ 2080381529U, // RCPSSm
+ 2080381529U, // RCPSSm_Int
+ 1277205081U, // RCPSSr
+ 1277205081U, // RCPSSr_Int
+ 872421984U, // RCR16m1
+ 872421993U, // RCR16mCL
+ 2711624308U, // RCR16mi
+ 73407072U, // RCR16r1
+ 73407081U, // RCR16rCL
+ 203463284U, // RCR16ri
+ 945822330U, // RCR32m1
+ 945822339U, // RCR32mCL
+ 2712672910U, // RCR32mi
+ 73407098U, // RCR32r1
+ 73407107U, // RCR32rCL
+ 203463310U, // RCR32ri
+ 1476401812U, // RCR64m1
+ 1476401821U, // RCR64mCL
+ 2713721512U, // RCR64mi
+ 73407124U, // RCR64r1
+ 73407133U, // RCR64rCL
+ 203463336U, // RCR64ri
+ 1610619566U, // RCR8m1
+ 1610619575U, // RCR8mCL
+ 2714770114U, // RCR8mi
+ 73407150U, // RCR8r1
+ 73407159U, // RCR8rCL
+ 203463362U, // RCR8ri
+ 6856U, // RDMSR
+ 6862U, // RDPMC
+ 6868U, // RDTSC
+ 6874U, // REP_MOVSB
+ 6884U, // REP_MOVSD
+ 6894U, // REP_MOVSQ
+ 6904U, // REP_MOVSW
+ 6914U, // REP_STOSB
+ 6924U, // REP_STOSD
+ 6934U, // REP_STOSQ
+ 6944U, // REP_STOSW
+ 6954U, // RET
+ 73407278U, // RETI
+ 872422195U, // ROL16m1
+ 872422201U, // ROL16mCL
+ 135273267U, // ROL16mi
+ 73407283U, // ROL16r1
+ 73407289U, // ROL16rCL
+ 203463475U, // ROL16ri
+ 945822532U, // ROL32m1
+ 945822538U, // ROL32mCL
+ 135338820U, // ROL32mi
+ 73407300U, // ROL32r1
+ 73407306U, // ROL32rCL
+ 203463492U, // ROL32ri
+ 1476402005U, // ROL64m1
+ 1476402011U, // ROL64mCL
+ 135371605U, // ROL64mi
+ 73407317U, // ROL64r1
+ 73407323U, // ROL64rCL
+ 203463509U, // ROL64ri
+ 1610619750U, // ROL8m1
+ 1610619756U, // ROL8mCL
+ 135404390U, // ROL8mi
+ 73407334U, // ROL8r1
+ 73407340U, // ROL8rCL
+ 203463526U, // ROL8ri
+ 872422263U, // ROR16m1
+ 872422269U, // ROR16mCL
+ 135273335U, // ROR16mi
+ 73407351U, // ROR16r1
+ 73407357U, // ROR16rCL
+ 203463543U, // ROR16ri
+ 945822600U, // ROR32m1
+ 945822606U, // ROR32mCL
+ 135338888U, // ROR32mi
+ 73407368U, // ROR32r1
+ 73407374U, // ROR32rCL
+ 203463560U, // ROR32ri
+ 1476402073U, // ROR64m1
+ 1476402079U, // ROR64mCL
+ 135371673U, // ROR64mi
+ 73407385U, // ROR64r1
+ 73407391U, // ROR64rCL
+ 203463577U, // ROR64ri
+ 1610619818U, // ROR8m1
+ 1610619824U, // ROR8mCL
+ 135404458U, // ROR8mi
+ 73407402U, // ROR8r1
+ 73407408U, // ROR8rCL
+ 203463594U, // ROR8ri
+ 2178948027U, // ROUNDPDm_Int
+ 215325627U, // ROUNDPDr_Int
+ 2178948036U, // ROUNDPSm_Int
+ 215325636U, // ROUNDPSr_Int
+ 1039145933U, // ROUNDSDm_Int
+ 1073748941U, // ROUNDSDr_Int
+ 1025514454U, // ROUNDSSm_Int
+ 1073748950U, // ROUNDSSr_Int
+ 7135U, // RSM
+ 1946164195U, // RSQRTPSm
+ 1946164195U, // RSQRTPSm_Int
+ 1277205475U, // RSQRTPSr
+ 1277205475U, // RSQRTPSr_Int
+ 2080381932U, // RSQRTSSm
+ 2080381932U, // RSQRTSSm_Int
+ 1277205484U, // RSQRTSSr
+ 1277205484U, // RSQRTSSr_Int
+ 7157U, // SAHF
+ 872422394U, // SAR16m1
+ 872422400U, // SAR16mCL
+ 135273466U, // SAR16mi
+ 73407482U, // SAR16r1
+ 73407488U, // SAR16rCL
+ 203463674U, // SAR16ri
+ 945822731U, // SAR32m1
+ 945822737U, // SAR32mCL
+ 135339019U, // SAR32mi
+ 73407499U, // SAR32r1
+ 73407505U, // SAR32rCL
+ 203463691U, // SAR32ri
+ 1476402204U, // SAR64m1
+ 1476402210U, // SAR64mCL
+ 135371804U, // SAR64mi
+ 73407516U, // SAR64r1
+ 73407522U, // SAR64rCL
+ 203463708U, // SAR64ri
+ 1610619949U, // SAR8m1
+ 1610619955U, // SAR8mCL
+ 135404589U, // SAR8mi
+ 73407533U, // SAR8r1
+ 73407539U, // SAR8rCL
+ 203463725U, // SAR8ri
+ 67116094U, // SBB16i16
+ 135273534U, // SBB16mi
+ 135273534U, // SBB16mi8
+ 135273534U, // SBB16mr
+ 203463742U, // SBB16ri
+ 203463742U, // SBB16ri8
+ 270572606U, // SBB16rm
+ 203463742U, // SBB16rr
+ 203463742U, // SBB16rr_REV
+ 70261828U, // SBB32i32
+ 135339076U, // SBB32mi
+ 135339076U, // SBB32mi8
+ 135339076U, // SBB32mr
+ 203463748U, // SBB32ri
+ 203463748U, // SBB32ri8
+ 337681476U, // SBB32rm
+ 203463748U, // SBB32rr
+ 203463748U, // SBB32rr_REV
+ 71310410U, // SBB64i32
+ 135371850U, // SBB64mi32
+ 135371850U, // SBB64mi8
+ 135371850U, // SBB64mr
+ 203463754U, // SBB64ri32
+ 203463754U, // SBB64ri8
+ 404790346U, // SBB64rm
+ 203463754U, // SBB64rr
+ 203463754U, // SBB64rr_REV
+ 72358992U, // SBB8i8
+ 135404624U, // SBB8mi
+ 135404624U, // SBB8mr
+ 203463760U, // SBB8ri
+ 471899216U, // SBB8rm
+ 203463760U, // SBB8rr
+ 203463760U, // SBB8rr_REV
+ 7254U, // SCAS16
+ 7260U, // SCAS32
+ 7266U, // SCAS64
+ 7272U, // SCAS8
+ 1610620014U, // SETAEm
+ 73407598U, // SETAEr
+ 1610620021U, // SETAm
+ 73407605U, // SETAr
+ 1610620027U, // SETBEm
+ 73407611U, // SETBEr
+ 68557886U, // SETB_C16r
+ 68557892U, // SETB_C32r
+ 68557898U, // SETB_C64r
+ 68557904U, // SETB_C8r
+ 1610620034U, // SETBm
+ 73407618U, // SETBr
+ 1610620040U, // SETEm
+ 73407624U, // SETEr
+ 1610620046U, // SETGEm
+ 73407630U, // SETGEr
+ 1610620053U, // SETGm
+ 73407637U, // SETGr
+ 1610620059U, // SETLEm
+ 73407643U, // SETLEr
+ 1610620066U, // SETLm
+ 73407650U, // SETLr
+ 1610620072U, // SETNEm
+ 73407656U, // SETNEr
+ 1610620079U, // SETNOm
+ 73407663U, // SETNOr
+ 1610620086U, // SETNPm
+ 73407670U, // SETNPr
+ 1610620093U, // SETNSm
+ 73407677U, // SETNSr
+ 1610620100U, // SETOm
+ 73407684U, // SETOr
+ 1610620106U, // SETPm
+ 73407690U, // SETPr
+ 1610620112U, // SETSm
+ 73407696U, // SETSr
+ 7382U, // SFENCE
+ 2214599901U, // SGDTm
+ 872422627U, // SHL16m1
+ 872422633U, // SHL16mCL
+ 135273699U, // SHL16mi
+ 73407715U, // SHL16r1
+ 73407721U, // SHL16rCL
+ 203463907U, // SHL16ri
+ 945822964U, // SHL32m1
+ 945822970U, // SHL32mCL
+ 135339252U, // SHL32mi
+ 73407732U, // SHL32r1
+ 73407738U, // SHL32rCL
+ 203463924U, // SHL32ri
+ 1476402437U, // SHL64m1
+ 1476402443U, // SHL64mCL
+ 135372037U, // SHL64mi
+ 73407749U, // SHL64r1
+ 73407755U, // SHL64rCL
+ 203463941U, // SHL64ri
+ 1610620182U, // SHL8m1
+ 1610620188U, // SHL8mCL
+ 135404822U, // SHL8mi
+ 73407766U, // SHL8r1
+ 73407772U, // SHL8rCL
+ 203463958U, // SHL8ri
+ 135273767U, // SHLD16mrCL
+ 2162171187U, // SHLD16mri8
+ 203463975U, // SHLD16rrCL
+ 1073749299U, // SHLD16rri8
+ 135339322U, // SHLD32mrCL
+ 2162236742U, // SHLD32mri8
+ 203463994U, // SHLD32rrCL
+ 1073749318U, // SHLD32rri8
+ 135372109U, // SHLD64mrCL
+ 2162269529U, // SHLD64mri8
+ 203464013U, // SHLD64rrCL
+ 1073749337U, // SHLD64rri8
+ 872422752U, // SHR16m1
+ 872422758U, // SHR16mCL
+ 135273824U, // SHR16mi
+ 73407840U, // SHR16r1
+ 73407846U, // SHR16rCL
+ 203464032U, // SHR16ri
+ 945823089U, // SHR32m1
+ 945823095U, // SHR32mCL
+ 135339377U, // SHR32mi
+ 73407857U, // SHR32r1
+ 73407863U, // SHR32rCL
+ 203464049U, // SHR32ri
+ 1476402562U, // SHR64m1
+ 1476402568U, // SHR64mCL
+ 135372162U, // SHR64mi
+ 73407874U, // SHR64r1
+ 73407880U, // SHR64rCL
+ 203464066U, // SHR64ri
+ 1610620307U, // SHR8m1
+ 1610620313U, // SHR8mCL
+ 135404947U, // SHR8mi
+ 73407891U, // SHR8r1
+ 73407897U, // SHR8rCL
+ 203464083U, // SHR8ri
+ 135273892U, // SHRD16mrCL
+ 2162171312U, // SHRD16mri8
+ 203464100U, // SHRD16rrCL
+ 1073749424U, // SHRD16rri8
+ 135339447U, // SHRD32mrCL
+ 2162236867U, // SHRD32mri8
+ 203464119U, // SHRD32rrCL
+ 1073749443U, // SHRD32rri8
+ 135372234U, // SHRD64mrCL
+ 2162269654U, // SHRD64mri8
+ 203464138U, // SHRD64rrCL
+ 1073749462U, // SHRD64rri8
+ 1040195037U, // SHUFPDrmi
+ 1073749469U, // SHUFPDrri
+ 1040195045U, // SHUFPSrmi
+ 1073749477U, // SHUFPSrri
+ 2214600173U, // SIDTm
+ 7667U, // SIN_F
0U, // SIN_Fp32
0U, // SIN_Fp64
0U, // SIN_Fp80
- 872422892U, // SLDT16m
- 73407980U, // SLDT16r
- 872422899U, // SLDT64m
- 73407987U, // SLDT64r
- 872422906U, // SMSW16m
- 73407994U, // SMSW16r
- 73408001U, // SMSW32r
- 73408008U, // SMSW64r
- 1946164751U, // SQRTPDm
- 1946164751U, // SQRTPDm_Int
- 1277206031U, // SQRTPDr
- 1277206031U, // SQRTPDr_Int
- 1946164759U, // SQRTPSm
- 1946164759U, // SQRTPSm_Int
- 1277206039U, // SQRTPSr
- 1277206039U, // SQRTPSr_Int
- 2013273631U, // SQRTSDm
- 2013273631U, // SQRTSDm_Int
- 1277206047U, // SQRTSDr
- 1277206047U, // SQRTSDr_Int
- 2080382503U, // SQRTSSm
- 2080382503U, // SQRTSSm_Int
- 1277206055U, // SQRTSSr
- 1277206055U, // SQRTSSr_Int
- 7727U, // SQRT_F
+ 872422904U, // SLDT16m
+ 73407992U, // SLDT16r
+ 872422911U, // SLDT64m
+ 73407999U, // SLDT64r
+ 872422918U, // SMSW16m
+ 73408006U, // SMSW16r
+ 73408013U, // SMSW32r
+ 73408020U, // SMSW64r
+ 1946164763U, // SQRTPDm
+ 1946164763U, // SQRTPDm_Int
+ 1277206043U, // SQRTPDr
+ 1277206043U, // SQRTPDr_Int
+ 1946164771U, // SQRTPSm
+ 1946164771U, // SQRTPSm_Int
+ 1277206051U, // SQRTPSr
+ 1277206051U, // SQRTPSr_Int
+ 2013273643U, // SQRTSDm
+ 2013273643U, // SQRTSDm_Int
+ 1277206059U, // SQRTSDr
+ 1277206059U, // SQRTSDr_Int
+ 2080382515U, // SQRTSSm
+ 2080382515U, // SQRTSSm_Int
+ 1277206067U, // SQRTSSr
+ 1277206067U, // SQRTSSr_Int
+ 7739U, // SQRT_F
0U, // SQRT_Fp32
0U, // SQRT_Fp64
0U, // SQRT_Fp80
- 7733U, // STC
- 7737U, // STD
- 7741U, // STI
- 945823297U, // STMXCSR
- 872422986U, // STRm
- 73408074U, // STRr
- 738205264U, // ST_F32m
- 805314134U, // ST_F64m
- 738205276U, // ST_FP32m
- 805314147U, // ST_FP64m
- 2415926890U, // ST_FP80m
- 73408113U, // ST_FPrr
+ 7745U, // STC
+ 7749U, // STD
+ 7753U, // STI
+ 945823309U, // STMXCSR
+ 872422998U, // STRm
+ 73408086U, // STRr
+ 738205276U, // ST_F32m
+ 805314146U, // ST_F64m
+ 738205288U, // ST_FP32m
+ 805314159U, // ST_FP64m
+ 2415926902U, // ST_FP80m
+ 73408125U, // ST_FPrr
0U, // ST_Fp32m
0U, // ST_Fp64m
0U, // ST_Fp64m32
@@ -2286,51 +2289,51 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ST_FpP80m
0U, // ST_FpP80m32
0U, // ST_FpP80m64
- 73408119U, // ST_Frr
- 67116668U, // SUB16i16
- 135274108U, // SUB16mi
- 135274108U, // SUB16mi8
- 135274108U, // SUB16mr
- 203464316U, // SUB16ri
- 203464316U, // SUB16ri8
- 270573180U, // SUB16rm
- 203464316U, // SUB16rr
- 203464316U, // SUB16rr_REV
- 70262402U, // SUB32i32
- 135339650U, // SUB32mi
- 135339650U, // SUB32mi8
- 135339650U, // SUB32mr
- 203464322U, // SUB32ri
- 203464322U, // SUB32ri8
- 337682050U, // SUB32rm
- 203464322U, // SUB32rr
- 203464322U, // SUB32rr_REV
- 71310984U, // SUB64i32
- 135372424U, // SUB64mi32
- 135372424U, // SUB64mi8
- 135372424U, // SUB64mr
- 203464328U, // SUB64ri32
- 203464328U, // SUB64ri8
- 404790920U, // SUB64rm
- 203464328U, // SUB64rr
- 203464328U, // SUB64rr_REV
- 72359566U, // SUB8i8
- 135405198U, // SUB8mi
- 135405198U, // SUB8mr
- 203464334U, // SUB8ri
- 471899790U, // SUB8rm
- 203464334U, // SUB8rr
- 203464334U, // SUB8rr_REV
- 536878740U, // SUBPDrm
- 203464340U, // SUBPDrr
- 536878747U, // SUBPSrm
- 203464347U, // SUBPSrr
- 738205346U, // SUBR_F32m
- 805314218U, // SUBR_F64m
- 872423090U, // SUBR_FI16m
- 945823419U, // SUBR_FI32m
- 73408196U, // SUBR_FPrST0
- 73408203U, // SUBR_FST0r
+ 73408131U, // ST_Frr
+ 67116680U, // SUB16i16
+ 135274120U, // SUB16mi
+ 135274120U, // SUB16mi8
+ 135274120U, // SUB16mr
+ 203464328U, // SUB16ri
+ 203464328U, // SUB16ri8
+ 270573192U, // SUB16rm
+ 203464328U, // SUB16rr
+ 203464328U, // SUB16rr_REV
+ 70262414U, // SUB32i32
+ 135339662U, // SUB32mi
+ 135339662U, // SUB32mi8
+ 135339662U, // SUB32mr
+ 203464334U, // SUB32ri
+ 203464334U, // SUB32ri8
+ 337682062U, // SUB32rm
+ 203464334U, // SUB32rr
+ 203464334U, // SUB32rr_REV
+ 71310996U, // SUB64i32
+ 135372436U, // SUB64mi32
+ 135372436U, // SUB64mi8
+ 135372436U, // SUB64mr
+ 203464340U, // SUB64ri32
+ 203464340U, // SUB64ri8
+ 404790932U, // SUB64rm
+ 203464340U, // SUB64rr
+ 203464340U, // SUB64rr_REV
+ 72359578U, // SUB8i8
+ 135405210U, // SUB8mi
+ 135405210U, // SUB8mr
+ 203464346U, // SUB8ri
+ 471899802U, // SUB8rm
+ 203464346U, // SUB8rr
+ 203464346U, // SUB8rr_REV
+ 536878752U, // SUBPDrm
+ 203464352U, // SUBPDrr
+ 536878759U, // SUBPSrm
+ 203464359U, // SUBPSrr
+ 738205358U, // SUBR_F32m
+ 805314230U, // SUBR_F64m
+ 872423102U, // SUBR_FI16m
+ 945823431U, // SUBR_FI32m
+ 73408208U, // SUBR_FPrST0
+ 73408215U, // SUBR_FST0r
0U, // SUBR_Fp32m
0U, // SUBR_Fp64m
0U, // SUBR_Fp64m32
@@ -2342,21 +2345,21 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // SUBR_FpI32m32
0U, // SUBR_FpI32m64
0U, // SUBR_FpI32m80
- 73408210U, // SUBR_FrST0
- 603987680U, // SUBSDrm
- 603987680U, // SUBSDrm_Int
- 203464416U, // SUBSDrr
- 203464416U, // SUBSDrr_Int
- 671096551U, // SUBSSrm
- 671096551U, // SUBSSrm_Int
- 203464423U, // SUBSSrr
- 203464423U, // SUBSSrr_Int
- 738205422U, // SUB_F32m
- 805314293U, // SUB_F64m
- 872423164U, // SUB_FI16m
- 945823492U, // SUB_FI32m
- 73408268U, // SUB_FPrST0
- 73408276U, // SUB_FST0r
+ 73408222U, // SUBR_FrST0
+ 603987692U, // SUBSDrm
+ 603987692U, // SUBSDrm_Int
+ 203464428U, // SUBSDrr
+ 203464428U, // SUBSDrr_Int
+ 671096563U, // SUBSSrm
+ 671096563U, // SUBSSrm_Int
+ 203464435U, // SUBSSrr
+ 203464435U, // SUBSSrr_Int
+ 738205434U, // SUB_F32m
+ 805314305U, // SUB_F64m
+ 872423176U, // SUB_FI16m
+ 945823504U, // SUB_FI32m
+ 73408280U, // SUB_FPrST0
+ 73408288U, // SUB_FST0r
0U, // SUB_Fp32
0U, // SUB_Fp32m
0U, // SUB_Fp64
@@ -2371,304 +2374,304 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // SUB_FpI32m32
0U, // SUB_FpI32m64
0U, // SUB_FpI32m80
- 73408282U, // SUB_FrST0
- 7977U, // SWPGS
- 7983U, // SYSCALL
- 7991U, // SYSENTER
- 8000U, // SYSEXIT
- 8000U, // SYSEXIT64
- 8008U, // SYSRET
- 1578110598U, // TAILJMPd
- 974135119U, // TAILJMPm
- 101715595U, // TAILJMPr
- 101715602U, // TAILJMPr64
- 102768469U, // TCRETURNdi
- 102768469U, // TCRETURNdi64
- 102768469U, // TCRETURNri
- 102768469U, // TCRETURNri64
- 67116897U, // TEST16i16
- 135274337U, // TEST16mi
- 1277206369U, // TEST16ri
- 1207967585U, // TEST16rm
- 1277206369U, // TEST16rr
- 70262632U, // TEST32i32
- 135339880U, // TEST32mi
- 1277206376U, // TEST32ri
- 1342185320U, // TEST32rm
- 1277206376U, // TEST32rr
- 71311215U, // TEST64i32
- 135372655U, // TEST64mi32
- 1277206383U, // TEST64ri32
- 1409294191U, // TEST64rm
- 1277206383U, // TEST64rr
- 72359798U, // TEST8i8
- 135405430U, // TEST8mi
- 1277206390U, // TEST8ri
- 1684021110U, // TEST8rm
- 1277206390U, // TEST8rr
- 2751467370U, // TLS_addr32
- 2818580349U, // TLS_addr64
- 8079U, // TRAP
- 8083U, // TST_F
+ 73408294U, // SUB_FrST0
+ 7989U, // SWPGS
+ 7995U, // SYSCALL
+ 8003U, // SYSENTER
+ 8012U, // SYSEXIT
+ 8012U, // SYSEXIT64
+ 8020U, // SYSRET
+ 1578110610U, // TAILJMPd
+ 974135131U, // TAILJMPm
+ 101715607U, // TAILJMPr
+ 101715614U, // TAILJMPr64
+ 102768481U, // TCRETURNdi
+ 102768481U, // TCRETURNdi64
+ 102768481U, // TCRETURNri
+ 102768481U, // TCRETURNri64
+ 67116909U, // TEST16i16
+ 135274349U, // TEST16mi
+ 1277206381U, // TEST16ri
+ 1207967597U, // TEST16rm
+ 1277206381U, // TEST16rr
+ 70262644U, // TEST32i32
+ 135339892U, // TEST32mi
+ 1277206388U, // TEST32ri
+ 1342185332U, // TEST32rm
+ 1277206388U, // TEST32rr
+ 71311227U, // TEST64i32
+ 135372667U, // TEST64mi32
+ 1277206395U, // TEST64ri32
+ 1409294203U, // TEST64rm
+ 1277206395U, // TEST64rr
+ 72359810U, // TEST8i8
+ 135405442U, // TEST8mi
+ 1277206402U, // TEST8ri
+ 1684021122U, // TEST8rm
+ 1277206402U, // TEST8rr
+ 2751467382U, // TLS_addr32
+ 2818580361U, // TLS_addr64
+ 8091U, // TRAP
+ 8095U, // TST_F
0U, // TST_Fp32
0U, // TST_Fp64
0U, // TST_Fp80
- 2013269574U, // UCOMISDrm
- 1277201990U, // UCOMISDrr
- 2080378447U, // UCOMISSrm
- 1277201999U, // UCOMISSrr
- 75505560U, // UCOM_FIPr
- 75505569U, // UCOM_FIr
- 8105U, // UCOM_FPPr
- 73408433U, // UCOM_FPr
+ 2013269586U, // UCOMISDrm
+ 1277202002U, // UCOMISDrr
+ 2080378459U, // UCOMISSrm
+ 1277202011U, // UCOMISSrr
+ 75505572U, // UCOM_FIPr
+ 75505581U, // UCOM_FIr
+ 8117U, // UCOM_FPPr
+ 73408445U, // UCOM_FPr
0U, // UCOM_FpIr32
0U, // UCOM_FpIr64
0U, // UCOM_FpIr80
0U, // UCOM_Fpr32
0U, // UCOM_Fpr64
0U, // UCOM_Fpr80
- 73408441U, // UCOM_Fr
- 536879040U, // UNPCKHPDrm
- 203464640U, // UNPCKHPDrr
- 536879050U, // UNPCKHPSrm
- 203464650U, // UNPCKHPSrr
- 536879060U, // UNPCKLPDrm
- 203464660U, // UNPCKLPDrr
- 536879070U, // UNPCKLPSrm
- 203464670U, // UNPCKLPSrr
- 68460520U, // VASTART_SAVE_XMM_REGS
- 872423424U, // VERRm
- 73408512U, // VERRr
- 872423430U, // VERWm
- 73408518U, // VERWr
- 8204U, // VMCALL
- 1476403219U, // VMCLEARm
- 8220U, // VMLAUNCH
- 1476403237U, // VMPTRLDm
- 1476403246U, // VMPTRSTm
- 135340087U, // VMREAD32rm
- 1277206583U, // VMREAD32rr
- 135372864U, // VMREAD64rm
- 1277206592U, // VMREAD64rr
- 8265U, // VMRESUME
- 1342185554U, // VMWRITE32rm
- 1277206610U, // VMWRITE32rr
- 1409294428U, // VMWRITE64rm
- 1277206620U, // VMWRITE64rr
- 8294U, // VMXOFF
- 1476403309U, // VMXON
- 68553868U, // V_SET0
- 68555304U, // V_SETALLONES
- 8308U, // WAIT
- 8313U, // WBINVD
- 1476396110U, // WINCALL64m
- 1549796452U, // WINCALL64pcrel32
- 73401422U, // WINCALL64r
- 8320U, // WRMSR
- 135274630U, // XADD16rm
- 1277206662U, // XADD16rr
- 135340173U, // XADD32rm
- 1277206669U, // XADD32rr
- 135372948U, // XADD64rm
- 1277206676U, // XADD64rr
- 135405723U, // XADD8rm
- 1277206683U, // XADD8rr
- 67117218U, // XCHG16ar
- 1296081058U, // XCHG16rm
- 1311776930U, // XCHG16rr
- 70262953U, // XCHG32ar
- 1297129641U, // XCHG32rm
- 1311776937U, // XCHG32rr
- 71311536U, // XCHG64ar
- 1298178224U, // XCHG64rm
- 1311776944U, // XCHG64rr
- 1299226807U, // XCHG8rm
- 1311776951U, // XCHG8rr
- 73408702U, // XCH_F
- 8388U, // XLAT
- 67117258U, // XOR16i16
- 135274698U, // XOR16mi
- 135274698U, // XOR16mi8
- 135274698U, // XOR16mr
- 203464906U, // XOR16ri
- 203464906U, // XOR16ri8
- 270573770U, // XOR16rm
- 203464906U, // XOR16rr
- 203464906U, // XOR16rr_REV
- 70259634U, // XOR32i32
- 135336882U, // XOR32mi
- 135336882U, // XOR32mi8
- 135336882U, // XOR32mr
- 203461554U, // XOR32ri
- 203461554U, // XOR32ri8
- 337679282U, // XOR32rm
- 203461554U, // XOR32rr
- 203461554U, // XOR32rr_REV
- 71311568U, // XOR64i32
- 135373008U, // XOR64mi32
- 135373008U, // XOR64mi8
- 135373008U, // XOR64mr
- 203464912U, // XOR64ri32
- 203464912U, // XOR64ri8
- 404791504U, // XOR64rm
- 203464912U, // XOR64rr
- 203464912U, // XOR64rr_REV
- 72356850U, // XOR8i8
- 135402482U, // XOR8mi
- 135402482U, // XOR8mr
- 203461618U, // XOR8ri
- 471897074U, // XOR8rm
- 203461618U, // XOR8rr
- 203461618U, // XOR8rr_REV
- 536874117U, // XORPDrm
- 203459717U, // XORPDrr
- 536874124U, // XORPSrm
- 203459724U, // XORPSrr
+ 73408453U, // UCOM_Fr
+ 536879052U, // UNPCKHPDrm
+ 203464652U, // UNPCKHPDrr
+ 536879062U, // UNPCKHPSrm
+ 203464662U, // UNPCKHPSrr
+ 536879072U, // UNPCKLPDrm
+ 203464672U, // UNPCKLPDrr
+ 536879082U, // UNPCKLPSrm
+ 203464682U, // UNPCKLPSrr
+ 68460532U, // VASTART_SAVE_XMM_REGS
+ 872423436U, // VERRm
+ 73408524U, // VERRr
+ 872423442U, // VERWm
+ 73408530U, // VERWr
+ 8216U, // VMCALL
+ 1476403231U, // VMCLEARm
+ 8232U, // VMLAUNCH
+ 1476403249U, // VMPTRLDm
+ 1476403258U, // VMPTRSTm
+ 135340099U, // VMREAD32rm
+ 1277206595U, // VMREAD32rr
+ 135372876U, // VMREAD64rm
+ 1277206604U, // VMREAD64rr
+ 8277U, // VMRESUME
+ 1342185566U, // VMWRITE32rm
+ 1277206622U, // VMWRITE32rr
+ 1409294440U, // VMWRITE64rm
+ 1277206632U, // VMWRITE64rr
+ 8306U, // VMXOFF
+ 1476403321U, // VMXON
+ 68553880U, // V_SET0
+ 68555316U, // V_SETALLONES
+ 8320U, // WAIT
+ 8325U, // WBINVD
+ 1476396122U, // WINCALL64m
+ 1549796464U, // WINCALL64pcrel32
+ 73401434U, // WINCALL64r
+ 8332U, // WRMSR
+ 135274642U, // XADD16rm
+ 1277206674U, // XADD16rr
+ 135340185U, // XADD32rm
+ 1277206681U, // XADD32rr
+ 135372960U, // XADD64rm
+ 1277206688U, // XADD64rr
+ 135405735U, // XADD8rm
+ 1277206695U, // XADD8rr
+ 67117230U, // XCHG16ar
+ 1296081070U, // XCHG16rm
+ 1311776942U, // XCHG16rr
+ 70262965U, // XCHG32ar
+ 1297129653U, // XCHG32rm
+ 1311776949U, // XCHG32rr
+ 71311548U, // XCHG64ar
+ 1298178236U, // XCHG64rm
+ 1311776956U, // XCHG64rr
+ 1299226819U, // XCHG8rm
+ 1311776963U, // XCHG8rr
+ 73408714U, // XCH_F
+ 8400U, // XLAT
+ 67117270U, // XOR16i16
+ 135274710U, // XOR16mi
+ 135274710U, // XOR16mi8
+ 135274710U, // XOR16mr
+ 203464918U, // XOR16ri
+ 203464918U, // XOR16ri8
+ 270573782U, // XOR16rm
+ 203464918U, // XOR16rr
+ 203464918U, // XOR16rr_REV
+ 70259646U, // XOR32i32
+ 135336894U, // XOR32mi
+ 135336894U, // XOR32mi8
+ 135336894U, // XOR32mr
+ 203461566U, // XOR32ri
+ 203461566U, // XOR32ri8
+ 337679294U, // XOR32rm
+ 203461566U, // XOR32rr
+ 203461566U, // XOR32rr_REV
+ 71311580U, // XOR64i32
+ 135373020U, // XOR64mi32
+ 135373020U, // XOR64mi8
+ 135373020U, // XOR64mr
+ 203464924U, // XOR64ri32
+ 203464924U, // XOR64ri8
+ 404791516U, // XOR64rm
+ 203464924U, // XOR64rr
+ 203464924U, // XOR64rr_REV
+ 72356862U, // XOR8i8
+ 135402494U, // XOR8mi
+ 135402494U, // XOR8mr
+ 203461630U, // XOR8ri
+ 471897086U, // XOR8rm
+ 203461630U, // XOR8rr
+ 203461630U, // XOR8rr_REV
+ 536874129U, // XORPDrm
+ 203459729U, // XORPDrr
+ 536874136U, // XORPSrm
+ 203459736U, // XORPSrr
0U
};
const char *AsmStrs =
- "fabs\000adcw\t\000adcl\t\000adcq\t\000adcb\t\000addw\t\000addl\t\000add"
- "q\t\000addb\t\000addpd\t\000addps\t\000addsd\t\000addss\t\000addsubpd\t"
- "\000addsubps\t\000fadds\t\000faddl\t\000fiadds\t\000fiaddl\t\000faddp\t"
- "\000fadd\t\000fadd\t%st(0), \000#ADJCALLSTACKDOWN\000#ADJCALLSTACKUP\000"
- "andw\t\000andl\t\000andq\t\000andb\t\000andnpd\t\000andnps\t\000andpd\t"
- "\000andps\t\000#ATOMADD6432 PSEUDO!\000#ATOMAND16 PSEUDO!\000#ATOMAND32"
- " PSEUDO!\000#ATOMAND64 PSEUDO!\000#ATOMAND6432 PSEUDO!\000#ATOMAND8 PSE"
- "UDO!\000#ATOMMAX16 PSEUDO!\000#ATOMMAX32 PSEUDO!\000#ATOMMAX64 PSEUDO!\000"
- "#ATOMMIN16 PSEUDO!\000#ATOMMIN32 PSEUDO!\000#ATOMMIN64 PSEUDO!\000#ATOM"
- "NAND16 PSEUDO!\000#ATOMNAND32 PSEUDO!\000#ATOMNAND64 PSEUDO!\000#ATOMNA"
- "ND6432 PSEUDO!\000#ATOMNAND8 PSEUDO!\000#ATOMOR16 PSEUDO!\000#ATOMOR32 "
- "PSEUDO!\000#ATOMOR64 PSEUDO!\000#ATOMOR6432 PSEUDO!\000#ATOMOR8 PSEUDO!"
- "\000#ATOMSUB6432 PSEUDO!\000#ATOMSWAP6432 PSEUDO!\000#ATOMUMAX16 PSEUDO"
- "!\000#ATOMUMAX32 PSEUDO!\000#ATOMUMAX64 PSEUDO!\000#ATOMUMIN16 PSEUDO!\000"
- "#ATOMUMIN32 PSEUDO!\000#ATOMUMIN64 PSEUDO!\000#ATOMXOR16 PSEUDO!\000#AT"
- "OMXOR32 PSEUDO!\000#ATOMXOR64 PSEUDO!\000#ATOMXOR6432 PSEUDO!\000#ATOMX"
- "OR8 PSEUDO!\000blendpd\t\000blendps\t\000blendvpd\t%xmm0, \000blendvps\t"
- "%xmm0, \000bsfw\t\000bsfl\t\000bsfq\t\000bsrw\t\000bsrl\t\000bsrq\t\000"
- "bswapl\t\000bswapq\t\000btw\t\000btl\t\000btq\t\000btcw\t\000btcl\t\000"
- "btcq\t\000btrw\t\000btrl\t\000btrq\t\000btsw\t\000btsl\t\000btsq\t\000c"
- "all\t*\000callq\t*\000callq\t\000call\t\000cbtw\000cltd\000cltq\000fchs"
- "\000clc\000cld\000clflush\t\000cli\000clts\000cmc\000cmovaw\t\000cmoval"
- "\t\000cmovaq\t\000cmovaew\t\000cmovael\t\000cmovaeq\t\000cmovbw\t\000cm"
- "ovbl\t\000cmovbq\t\000cmovbew\t\000cmovbel\t\000cmovbeq\t\000fcmovbe\t\000"
- "fcmovb\t\000cmovew\t\000cmovel\t\000cmoveq\t\000fcmove\t\000cmovgw\t\000"
- "cmovgl\t\000cmovgq\t\000cmovgew\t\000cmovgel\t\000cmovgeq\t\000cmovlw\t"
- "\000cmovll\t\000cmovlq\t\000cmovlew\t\000cmovlel\t\000cmovleq\t\000fcmo"
- "vnbe\t\000fcmovnb\t\000cmovnew\t\000cmovnel\t\000cmovneq\t\000fcmovne\t"
- "\000cmovnow\t\000cmovnol\t\000cmovnoq\t\000cmovnpw\t\000cmovnpl\t\000cm"
- "ovnpq\t\000fcmovnu\t\000cmovnsw\t\000cmovnsl\t\000cmovnsq\t\000cmovow\t"
- "\000cmovol\t\000cmovoq\t\000cmovpw\t\000cmovpl\t\000cmovpq\t\000fcmovu\t"
- " \000cmovsw\t\000cmovsl\t\000cmovsq\t\000#CMOV_FR32 PSEUDO!\000#CMOV_FR"
- "64 PSEUDO!\000#CMOV_GR8 PSEUDO!\000#CMOV_V1I64 PSEUDO!\000#CMOV_V2F64 P"
- "SEUDO!\000#CMOV_V2I64 PSEUDO!\000#CMOV_V4F32 PSEUDO!\000cmpw\t\000cmpl\t"
- "\000cmpq\t\000cmpb\t\000cmp\000cmpsw\000cmpsl\000cmpsq\000cmpsb\000cmpx"
- "chg16b\t\000cmpxchgw\t\000cmpxchgl\t\000cmpxchgq\t\000cmpxchg8b\t\000cm"
- "pxchgb\t\000comisd\t\000comiss\t\000fcomp\t\000fcomip\t\000fcomi\t\000f"
- "com\t\000fcos\000cpuid\000cqto\000crc32 \t\000cvtdq2pd\t\000cvtdq2ps\t\000"
- "cvtpd2dq\t\000cvtpd2ps\t\000cvtps2dq\t\000cvtps2pd\t\000cvtsd2siq\t\000"
- "cvtsd2ss\t\000cvtsi2sdq\t\000cvtsi2sd\t\000cvtsi2ssq\t\000cvtsi2ss\t\000"
- "cvtss2sd\t\000cvtss2siq\t\000cvtss2sil\t\000cvttps2dq\t\000cvttsd2siq\t"
- "\000cvttsd2si\t\000cvttss2siq\t\000cvttss2si\t\000cwtd\000cwtl\000decw\t"
- "\000decl\t\000decq\t\000decb\t\000divw\t\000divl\t\000divq\t\000divb\t\000"
- "divpd\t\000divps\t\000fdivrs\t\000fdivrl\t\000fidivrs\t\000fidivrl\t\000"
- "fdivp\t\000fdivr\t\000fdiv\t%st(0), \000divsd\t\000divss\t\000fdivs\t\000"
- "fdivl\t\000fidivs\t\000fidivl\t\000fdivrp\t\000fdiv\t\000fdivr\t%st(0),"
- " \000dppd\t\000dpps\t\000ret\t#eh_return, addr: \000enter\t\000extractp"
- "s\t\000f2xm1\000lcallw\t\000lcallw\t*\000lcalll\t\000lcalll\t*\000lcall"
- "q\t*\000ljmpw\t\000ljmpw\t*\000ljmpl\t\000ljmpl\t*\000ljmpq\t*\000fbld\t"
- "\000fbstp\t\000fcoml\t\000fcomll\t\000fcompl\t\000fcompll\t\000fcompp\000"
- "fdecstp\000ffree\t\000ficomw\t\000ficoml\t\000ficompw\t\000ficompl\t\000"
- "fincstp\000fisttpl\t\000fldcw\t\000fldenv\t\000fldl2e\000fldl2t\000fldl"
- "g2\000fldln2\000fldpi\000fnclex\000fninit\000fnop\000fnstcw\t\000fnstsw"
- " %ax\000fnstsw\t\000##FP32_TO_INT16_IN_MEM PSEUDO!\000##FP32_TO_INT32_I"
- "N_MEM PSEUDO!\000##FP32_TO_INT64_IN_MEM PSEUDO!\000##FP64_TO_INT16_IN_M"
- "EM PSEUDO!\000##FP64_TO_INT32_IN_MEM PSEUDO!\000##FP64_TO_INT64_IN_MEM "
- "PSEUDO!\000##FP80_TO_INT16_IN_MEM PSEUDO!\000##FP80_TO_INT32_IN_MEM PSE"
- "UDO!\000##FP80_TO_INT64_IN_MEM PSEUDO!\000fpatan\000fprem\000fprem1\000"
- "fptan\000##FP_REG_KILL\000frndint\000frstor\t\000fnsave\t\000fscale\000"
- "fsincos\000fnstenv\t\000movl\t%fs:\000fxam\000fxrstor\t\000fxsave\t\000"
- "fxtract\000fyl2x\000fyl2xp1\000pxor\t\000movapd\t\000movaps\t\000orpd\t"
- "\000orps\t\000xorpd\t\000xorps\t\000movl\t%gs:\000haddpd\t\000haddps\t\000"
- "hlt\000hsubpd\t\000hsubps\t\000idivw\t\000idivl\t\000idivq\t\000idivb\t"
- "\000filds\t\000fildl\t\000fildll\t\000imulw\t\000imull\t\000imulq\t\000"
- "imulb\t\000insw\000inw\t\000inw\t%dx, %ax\000insl\000inl\t\000inl\t%dx,"
- " %eax\000insb\000inb\t\000inb\t%dx, %al\000incw\t\000incl\t\000incq\t\000"
- "incb\t\000insertps\t\000int\t\000int\t3\000invd\000invept\000invlpg\000"
- "invvpid\000iretw\000iretl\000iretq\000fisttps\t\000fisttpll\t\000fists\t"
- "\000fistl\t\000fistps\t\000fistpl\t\000fistpll\t\000cvtpd2pi\t\000cvtpi"
- "2pd\t\000cvtpi2ps\t\000cvtps2pi\t\000cvtsd2si\t\000cvtss2si\t\000cvttpd"
- "2dq\t\000cvttpd2pi\t\000cvttps2pi\t\000ucomisd\t\000ucomiss\t\000ja\t\000"
- "jae\t\000jb\t\000jbe\t\000jcxz\t\000je\t\000jg\t\000jge\t\000jl\t\000jl"
- "e\t\000jmp\t\000jmpl\t*\000jmpq\t*\000jmpq\t\000jne\t\000jno\t\000jnp\t"
- "\000jns\t\000jo\t\000jp\t\000js\t\000lahf\000larw\t\000larl\t\000larq\t"
- "\000lock\n\tcmpxchgw\t\000lock\n\tcmpxchgl\t\000lock\n\tcmpxchgq\t\000l"
- "ock\n\tcmpxchgb\t\000lock\n\tcmpxchg8b\t\000lddqu\t\000ldmxcsr\t\000lds"
- "w\t\000ldsl\t\000fldz\000fld1\000flds\t\000fldl\t\000fldt\t\000fld\t\000"
- "leaw\t\000leal\t\000leaq\t\000leave\000lesw\t\000lesl\t\000lfence\000lf"
- "sw\t\000lfsl\t\000lfsq\t\000lgdt\t\000lgsw\t\000lgsl\t\000lgsq\t\000lid"
- "t\t\000lldtw\t\000lmsww\t\000lock\n\taddw\t\000lock\n\taddl\t\000lock\n"
- "\taddq\t\000lock\n\taddb\t\000lock\n\tdecw\t\000lock\n\tdecl\t\000lock\n"
- "\tdecq\t\000lock\n\tdecb\t\000lock\n\tincw\t\000lock\n\tincl\t\000lock\n"
- "\tincq\t\000lock\n\tincb\t\000lock\n\tsubw\t\000lock\n\tsubl\t\000lock\n"
- "\tsubq\t\000lock\n\tsubb\t\000lodsb\000lodsl\000lodsq\000lodsw\000loop\t"
- "\000loope\t\000loopne\t\000lret\000lret\t\000lslw\t\000lsll\t\000lslq\t"
- "\000lssw\t\000lssl\t\000lssq\t\000ltrw\t\000lock\n\txaddw\t\000lock\n\t"
- "xaddl\t\000lock\n\txadd\t\000lock\n\txaddb\t\000maskmovdqu\t\000maxpd\t"
- "\000maxps\t\000maxsd\t\000maxss\t\000mfence\000minpd\t\000minps\t\000mi"
- "nsd\t\000minss\t\000emms\000femms\000maskmovq\t\000movd\t\000movdq2q\t\000"
- "movntq\t\000movq2dq\t\000movq\t\000packssdw\t\000packsswb\t\000packuswb"
- "\t\000paddb\t\000paddd\t\000paddq\t\000paddsb\t\000paddsw\t\000paddusb\t"
- "\000paddusw\t\000paddw\t\000pandn\t\000pand\t\000pavgb\t\000pavgw\t\000"
- "pcmpeqb\t\000pcmpeqd\t\000pcmpeqw\t\000pcmpgtb\t\000pcmpgtd\t\000pcmpgt"
- "w\t\000pextrw\t\000pinsrw\t\000pmaddwd\t\000pmaxsw\t\000pmaxub\t\000pmi"
- "nsw\t\000pminub\t\000pmovmskb\t\000pmulhuw\t\000pmulhw\t\000pmullw\t\000"
- "pmuludq\t\000por\t\000psadbw\t\000pshufw\t\000pslld\t\000psllq\t\000psl"
- "lw\t\000psrad\t\000psraw\t\000psrld\t\000psrlq\t\000psrlw\t\000psubb\t\000"
- "psubd\t\000psubq\t\000psubsb\t\000psubsw\t\000psubusb\t\000psubusw\t\000"
- "psubw\t\000punpckhbw\t\000punpckhdq\t\000punpckhwd\t\000punpcklbw\t\000"
- "punpckldq\t\000punpcklwd\t\000monitor\000movw\t%ax, \000movw\t\000movl\t"
- "%eax, \000movl\t\000xorl\t\000movq\t%fs:\000movq\t%gs:\000movq\t%rax, \000"
- "movabsq\t\000movb\t%al, \000movb\t\000xorb\t\000movddup\t\000movdqa\t\000"
- "movdqu\t\000movhlps\t\000movhpd\t\000movhps\t\000movlhps\t\000movlpd\t\000"
- "movsd\t\000movlps\t\000movss\t\000movmskpd\t\000movmskps\t\000movntdqa\t"
- "\000movntdq\t\000movnti\t\000movntpd\t\000movntps\t\000movshdup\t\000mo"
- "vsldup\t\000movsbw\t\000movswl\t\000movsbl\t\000movswq\t\000movslq\t\000"
- "movsbq\t\000movupd\t\000movups\t\000movzbw\t\000movzbl\t\000movzwl\t\000"
- "movzwq\t\000movzbq\t\000mpsadbw\t\000mulw\t\000mull\t\000mulq\t\000mulb"
- "\t\000mulpd\t\000mulps\t\000mulsd\t\000mulss\t\000fmuls\t\000fmull\t\000"
- "fimuls\t\000fimull\t\000fmulp\t\000fmul\t\000fmul\t%st(0), \000mwait\000"
- "negw\t\000negl\t\000negq\t\000negb\t\000nop\000nopl\t\000nopw\t\000notw"
- "\t\000notl\t\000notq\t\000notb\t\000orw\t\000orl\t\000orq\t\000orb\t\000"
- "outw\t%ax, \000outw\t%ax, %dx\000outl\t%eax, \000outl\t%eax, %dx\000out"
- "b\t%al, \000outb\t%al, %dx\000outsb\000outsl\000outsw\000pabsb\t\000pab"
- "sd\t\000pabsw\t\000packusdw\t\000palignr\t\000pblendvb\t%xmm0, \000pble"
- "ndw\t\000pcmpeqq\t\000pcmpestri\t\000#PCMPESTRM128rm PSEUDO!\000#PCMPES"
- "TRM128rr PSEUDO!\000pcmpestrm\t\000pcmpgtq\t\000pcmpistri\t\000#PCMPIST"
- "RM128rm PSEUDO!\000#PCMPISTRM128rr PSEUDO!\000pcmpistrm\t\000pextrb\t\000"
- "pextrd\t\000pextrq\t\000phaddd\t\000phaddsw\t\000phaddw\t\000phminposuw"
- "\t\000phsubd\t\000phsubsw\t\000phsubw\t\000pinsrb\t\000pinsrd\t\000pins"
- "rq\t\000pmaddubsw\t\000pmaxsb\t\000pmaxsd\t\000pmaxud\t\000pmaxuw\t\000"
- "pminsb\t\000pminsd\t\000pminud\t\000pminuw\t\000pmovsxbd\t\000pmovsxbq\t"
- "\000pmovsxbw\t\000pmovsxdq\t\000pmovsxwd\t\000pmovsxwq\t\000pmovzxbd\t\000"
- "pmovzxbq\t\000pmovzxbw\t\000pmovzxdq\t\000pmovzxwd\t\000pmovzxwq\t\000p"
- "muldq\t\000pmulhrsw\t\000pmulld\t\000popw\t\000popl\t\000popq\t\000popc"
- "ntw\t\000popcntl\t\000popcntq\t\000popfw\000popfl\000popfq\000popw\t%fs"
- "\000popl\t%fs\000popq\t%fs\000popw\t%gs\000popl\t%gs\000popq\t%gs\000pr"
- "efetchnta\t\000prefetcht0\t\000prefetcht1\t\000prefetcht2\t\000pshufb\t"
- "\000pshufd\t\000pshufhw\t\000pshuflw\t\000psignb\t\000psignd\t\000psign"
- "w\t\000pslldq\t\000psrldq\t\000ptest \t\000punpckhqdq\t\000punpcklqdq\t"
- "\000pushw\t\000pushl\t\000pushq\t\000pushfw\000pushfl\000pushfq\000push"
- "w\t%fs\000pushl\t%fs\000pushq\t%fs\000pushw\t%gs\000pushl\t%gs\000pushq"
- "\t%gs\000rclw\t1, \000rclw\t%cl, \000rclw\t\000rcll\t1, \000rcll\t%cl, "
- "\000rcll\t\000rclq\t1, \000rclq\t%cl, \000rclq\t\000rclb\t1, \000rclb\t"
- "%cl, \000rclb\t\000rcpps\t\000rcpss\t\000rcrw\t1, \000rcrw\t%cl, \000rc"
- "rw\t\000rcrl\t1, \000rcrl\t%cl, \000rcrl\t\000rcrq\t1, \000rcrq\t%cl, \000"
- "rcrq\t\000rcrb\t1, \000rcrb\t%cl, \000rcrb\t\000rdmsr\000rdpmc\000rdtsc"
- "\000rep;movsb\000rep;movsl\000rep;movsq\000rep;movsw\000rep;stosb\000re"
- "p;stosl\000rep;stosq\000rep;stosw\000ret\000ret\t\000rolw\t\000rolw\t%c"
- "l, \000roll\t\000roll\t%cl, \000rolq\t\000rolq\t%cl, \000rolb\t\000rolb"
- "\t%cl, \000rorw\t\000rorw\t%cl, \000rorl\t\000rorl\t%cl, \000rorq\t\000"
+ "DEBUG_VALUE\000fabs\000adcw\t\000adcl\t\000adcq\t\000adcb\t\000addw\t\000"
+ "addl\t\000addq\t\000addb\t\000addpd\t\000addps\t\000addsd\t\000addss\t\000"
+ "addsubpd\t\000addsubps\t\000fadds\t\000faddl\t\000fiadds\t\000fiaddl\t\000"
+ "faddp\t\000fadd\t\000fadd\t%st(0), \000#ADJCALLSTACKDOWN\000#ADJCALLSTA"
+ "CKUP\000andw\t\000andl\t\000andq\t\000andb\t\000andnpd\t\000andnps\t\000"
+ "andpd\t\000andps\t\000#ATOMADD6432 PSEUDO!\000#ATOMAND16 PSEUDO!\000#AT"
+ "OMAND32 PSEUDO!\000#ATOMAND64 PSEUDO!\000#ATOMAND6432 PSEUDO!\000#ATOMA"
+ "ND8 PSEUDO!\000#ATOMMAX16 PSEUDO!\000#ATOMMAX32 PSEUDO!\000#ATOMMAX64 P"
+ "SEUDO!\000#ATOMMIN16 PSEUDO!\000#ATOMMIN32 PSEUDO!\000#ATOMMIN64 PSEUDO"
+ "!\000#ATOMNAND16 PSEUDO!\000#ATOMNAND32 PSEUDO!\000#ATOMNAND64 PSEUDO!\000"
+ "#ATOMNAND6432 PSEUDO!\000#ATOMNAND8 PSEUDO!\000#ATOMOR16 PSEUDO!\000#AT"
+ "OMOR32 PSEUDO!\000#ATOMOR64 PSEUDO!\000#ATOMOR6432 PSEUDO!\000#ATOMOR8 "
+ "PSEUDO!\000#ATOMSUB6432 PSEUDO!\000#ATOMSWAP6432 PSEUDO!\000#ATOMUMAX16"
+ " PSEUDO!\000#ATOMUMAX32 PSEUDO!\000#ATOMUMAX64 PSEUDO!\000#ATOMUMIN16 P"
+ "SEUDO!\000#ATOMUMIN32 PSEUDO!\000#ATOMUMIN64 PSEUDO!\000#ATOMXOR16 PSEU"
+ "DO!\000#ATOMXOR32 PSEUDO!\000#ATOMXOR64 PSEUDO!\000#ATOMXOR6432 PSEUDO!"
+ "\000#ATOMXOR8 PSEUDO!\000blendpd\t\000blendps\t\000blendvpd\t%xmm0, \000"
+ "blendvps\t%xmm0, \000bsfw\t\000bsfl\t\000bsfq\t\000bsrw\t\000bsrl\t\000"
+ "bsrq\t\000bswapl\t\000bswapq\t\000btw\t\000btl\t\000btq\t\000btcw\t\000"
+ "btcl\t\000btcq\t\000btrw\t\000btrl\t\000btrq\t\000btsw\t\000btsl\t\000b"
+ "tsq\t\000call\t*\000callq\t*\000callq\t\000call\t\000cbtw\000cltd\000cl"
+ "tq\000fchs\000clc\000cld\000clflush\t\000cli\000clts\000cmc\000cmovaw\t"
+ "\000cmoval\t\000cmovaq\t\000cmovaew\t\000cmovael\t\000cmovaeq\t\000cmov"
+ "bw\t\000cmovbl\t\000cmovbq\t\000cmovbew\t\000cmovbel\t\000cmovbeq\t\000"
+ "fcmovbe\t\000fcmovb\t\000cmovew\t\000cmovel\t\000cmoveq\t\000fcmove\t\000"
+ "cmovgw\t\000cmovgl\t\000cmovgq\t\000cmovgew\t\000cmovgel\t\000cmovgeq\t"
+ "\000cmovlw\t\000cmovll\t\000cmovlq\t\000cmovlew\t\000cmovlel\t\000cmovl"
+ "eq\t\000fcmovnbe\t\000fcmovnb\t\000cmovnew\t\000cmovnel\t\000cmovneq\t\000"
+ "fcmovne\t\000cmovnow\t\000cmovnol\t\000cmovnoq\t\000cmovnpw\t\000cmovnp"
+ "l\t\000cmovnpq\t\000fcmovnu\t\000cmovnsw\t\000cmovnsl\t\000cmovnsq\t\000"
+ "cmovow\t\000cmovol\t\000cmovoq\t\000cmovpw\t\000cmovpl\t\000cmovpq\t\000"
+ "fcmovu\t \000cmovsw\t\000cmovsl\t\000cmovsq\t\000#CMOV_FR32 PSEUDO!\000"
+ "#CMOV_FR64 PSEUDO!\000#CMOV_GR8 PSEUDO!\000#CMOV_V1I64 PSEUDO!\000#CMOV"
+ "_V2F64 PSEUDO!\000#CMOV_V2I64 PSEUDO!\000#CMOV_V4F32 PSEUDO!\000cmpw\t\000"
+ "cmpl\t\000cmpq\t\000cmpb\t\000cmp\000cmpsw\000cmpsl\000cmpsq\000cmpsb\000"
+ "cmpxchg16b\t\000cmpxchgw\t\000cmpxchgl\t\000cmpxchgq\t\000cmpxchg8b\t\000"
+ "cmpxchgb\t\000comisd\t\000comiss\t\000fcomp\t\000fcomip\t\000fcomi\t\000"
+ "fcom\t\000fcos\000cpuid\000cqto\000crc32 \t\000cvtdq2pd\t\000cvtdq2ps\t"
+ "\000cvtpd2dq\t\000cvtpd2ps\t\000cvtps2dq\t\000cvtps2pd\t\000cvtsd2siq\t"
+ "\000cvtsd2ss\t\000cvtsi2sdq\t\000cvtsi2sd\t\000cvtsi2ssq\t\000cvtsi2ss\t"
+ "\000cvtss2sd\t\000cvtss2siq\t\000cvtss2sil\t\000cvttps2dq\t\000cvttsd2s"
+ "iq\t\000cvttsd2si\t\000cvttss2siq\t\000cvttss2si\t\000cwtd\000cwtl\000d"
+ "ecw\t\000decl\t\000decq\t\000decb\t\000divw\t\000divl\t\000divq\t\000di"
+ "vb\t\000divpd\t\000divps\t\000fdivrs\t\000fdivrl\t\000fidivrs\t\000fidi"
+ "vrl\t\000fdivp\t\000fdivr\t\000fdiv\t%st(0), \000divsd\t\000divss\t\000"
+ "fdivs\t\000fdivl\t\000fidivs\t\000fidivl\t\000fdivrp\t\000fdiv\t\000fdi"
+ "vr\t%st(0), \000dppd\t\000dpps\t\000ret\t#eh_return, addr: \000enter\t\000"
+ "extractps\t\000f2xm1\000lcallw\t\000lcallw\t*\000lcalll\t\000lcalll\t*\000"
+ "lcallq\t*\000ljmpw\t\000ljmpw\t*\000ljmpl\t\000ljmpl\t*\000ljmpq\t*\000"
+ "fbld\t\000fbstp\t\000fcoml\t\000fcomll\t\000fcompl\t\000fcompll\t\000fc"
+ "ompp\000fdecstp\000ffree\t\000ficomw\t\000ficoml\t\000ficompw\t\000fico"
+ "mpl\t\000fincstp\000fisttpl\t\000fldcw\t\000fldenv\t\000fldl2e\000fldl2"
+ "t\000fldlg2\000fldln2\000fldpi\000fnclex\000fninit\000fnop\000fnstcw\t\000"
+ "fnstsw %ax\000fnstsw\t\000##FP32_TO_INT16_IN_MEM PSEUDO!\000##FP32_TO_I"
+ "NT32_IN_MEM PSEUDO!\000##FP32_TO_INT64_IN_MEM PSEUDO!\000##FP64_TO_INT1"
+ "6_IN_MEM PSEUDO!\000##FP64_TO_INT32_IN_MEM PSEUDO!\000##FP64_TO_INT64_I"
+ "N_MEM PSEUDO!\000##FP80_TO_INT16_IN_MEM PSEUDO!\000##FP80_TO_INT32_IN_M"
+ "EM PSEUDO!\000##FP80_TO_INT64_IN_MEM PSEUDO!\000fpatan\000fprem\000fpre"
+ "m1\000fptan\000##FP_REG_KILL\000frndint\000frstor\t\000fnsave\t\000fsca"
+ "le\000fsincos\000fnstenv\t\000movl\t%fs:\000fxam\000fxrstor\t\000fxsave"
+ "\t\000fxtract\000fyl2x\000fyl2xp1\000pxor\t\000movapd\t\000movaps\t\000"
+ "orpd\t\000orps\t\000xorpd\t\000xorps\t\000movl\t%gs:\000haddpd\t\000had"
+ "dps\t\000hlt\000hsubpd\t\000hsubps\t\000idivw\t\000idivl\t\000idivq\t\000"
+ "idivb\t\000filds\t\000fildl\t\000fildll\t\000imulw\t\000imull\t\000imul"
+ "q\t\000imulb\t\000insw\000inw\t\000inw\t%dx, %ax\000insl\000inl\t\000in"
+ "l\t%dx, %eax\000insb\000inb\t\000inb\t%dx, %al\000incw\t\000incl\t\000i"
+ "ncq\t\000incb\t\000insertps\t\000int\t\000int\t3\000invd\000invept\000i"
+ "nvlpg\000invvpid\000iretw\000iretl\000iretq\000fisttps\t\000fisttpll\t\000"
+ "fists\t\000fistl\t\000fistps\t\000fistpl\t\000fistpll\t\000cvtpd2pi\t\000"
+ "cvtpi2pd\t\000cvtpi2ps\t\000cvtps2pi\t\000cvtsd2si\t\000cvtss2si\t\000c"
+ "vttpd2dq\t\000cvttpd2pi\t\000cvttps2pi\t\000ucomisd\t\000ucomiss\t\000j"
+ "a\t\000jae\t\000jb\t\000jbe\t\000jcxz\t\000je\t\000jg\t\000jge\t\000jl\t"
+ "\000jle\t\000jmp\t\000jmpl\t*\000jmpq\t*\000jmpq\t\000jne\t\000jno\t\000"
+ "jnp\t\000jns\t\000jo\t\000jp\t\000js\t\000lahf\000larw\t\000larl\t\000l"
+ "arq\t\000lock\n\tcmpxchgw\t\000lock\n\tcmpxchgl\t\000lock\n\tcmpxchgq\t"
+ "\000lock\n\tcmpxchgb\t\000lock\n\tcmpxchg8b\t\000lddqu\t\000ldmxcsr\t\000"
+ "ldsw\t\000ldsl\t\000fldz\000fld1\000flds\t\000fldl\t\000fldt\t\000fld\t"
+ "\000leaw\t\000leal\t\000leaq\t\000leave\000lesw\t\000lesl\t\000lfence\000"
+ "lfsw\t\000lfsl\t\000lfsq\t\000lgdt\t\000lgsw\t\000lgsl\t\000lgsq\t\000l"
+ "idt\t\000lldtw\t\000lmsww\t\000lock\n\taddw\t\000lock\n\taddl\t\000lock"
+ "\n\taddq\t\000lock\n\taddb\t\000lock\n\tdecw\t\000lock\n\tdecl\t\000loc"
+ "k\n\tdecq\t\000lock\n\tdecb\t\000lock\n\tincw\t\000lock\n\tincl\t\000lo"
+ "ck\n\tincq\t\000lock\n\tincb\t\000lock\n\tsubw\t\000lock\n\tsubl\t\000l"
+ "ock\n\tsubq\t\000lock\n\tsubb\t\000lodsb\000lodsl\000lodsq\000lodsw\000"
+ "loop\t\000loope\t\000loopne\t\000lret\000lret\t\000lslw\t\000lsll\t\000"
+ "lslq\t\000lssw\t\000lssl\t\000lssq\t\000ltrw\t\000lock\n\txaddw\t\000lo"
+ "ck\n\txaddl\t\000lock\n\txadd\t\000lock\n\txaddb\t\000maskmovdqu\t\000m"
+ "axpd\t\000maxps\t\000maxsd\t\000maxss\t\000mfence\000minpd\t\000minps\t"
+ "\000minsd\t\000minss\t\000emms\000femms\000maskmovq\t\000movd\t\000movd"
+ "q2q\t\000movntq\t\000movq2dq\t\000movq\t\000packssdw\t\000packsswb\t\000"
+ "packuswb\t\000paddb\t\000paddd\t\000paddq\t\000paddsb\t\000paddsw\t\000"
+ "paddusb\t\000paddusw\t\000paddw\t\000pandn\t\000pand\t\000pavgb\t\000pa"
+ "vgw\t\000pcmpeqb\t\000pcmpeqd\t\000pcmpeqw\t\000pcmpgtb\t\000pcmpgtd\t\000"
+ "pcmpgtw\t\000pextrw\t\000pinsrw\t\000pmaddwd\t\000pmaxsw\t\000pmaxub\t\000"
+ "pminsw\t\000pminub\t\000pmovmskb\t\000pmulhuw\t\000pmulhw\t\000pmullw\t"
+ "\000pmuludq\t\000por\t\000psadbw\t\000pshufw\t\000pslld\t\000psllq\t\000"
+ "psllw\t\000psrad\t\000psraw\t\000psrld\t\000psrlq\t\000psrlw\t\000psubb"
+ "\t\000psubd\t\000psubq\t\000psubsb\t\000psubsw\t\000psubusb\t\000psubus"
+ "w\t\000psubw\t\000punpckhbw\t\000punpckhdq\t\000punpckhwd\t\000punpcklb"
+ "w\t\000punpckldq\t\000punpcklwd\t\000monitor\000movw\t%ax, \000movw\t\000"
+ "movl\t%eax, \000movl\t\000xorl\t\000movq\t%fs:\000movq\t%gs:\000movq\t%"
+ "rax, \000movabsq\t\000movb\t%al, \000movb\t\000xorb\t\000movddup\t\000m"
+ "ovdqa\t\000movdqu\t\000movhlps\t\000movhpd\t\000movhps\t\000movlhps\t\000"
+ "movlpd\t\000movsd\t\000movlps\t\000movss\t\000movmskpd\t\000movmskps\t\000"
+ "movntdqa\t\000movntdq\t\000movnti\t\000movntpd\t\000movntps\t\000movshd"
+ "up\t\000movsldup\t\000movsbw\t\000movswl\t\000movsbl\t\000movswq\t\000m"
+ "ovslq\t\000movsbq\t\000movupd\t\000movups\t\000movzbw\t\000movzbl\t\000"
+ "movzwl\t\000movzwq\t\000movzbq\t\000mpsadbw\t\000mulw\t\000mull\t\000mu"
+ "lq\t\000mulb\t\000mulpd\t\000mulps\t\000mulsd\t\000mulss\t\000fmuls\t\000"
+ "fmull\t\000fimuls\t\000fimull\t\000fmulp\t\000fmul\t\000fmul\t%st(0), \000"
+ "mwait\000negw\t\000negl\t\000negq\t\000negb\t\000nop\000nopl\t\000nopw\t"
+ "\000notw\t\000notl\t\000notq\t\000notb\t\000orw\t\000orl\t\000orq\t\000"
+ "orb\t\000outw\t%ax, \000outw\t%ax, %dx\000outl\t%eax, \000outl\t%eax, %"
+ "dx\000outb\t%al, \000outb\t%al, %dx\000outsb\000outsl\000outsw\000pabsb"
+ "\t\000pabsd\t\000pabsw\t\000packusdw\t\000palignr\t\000pblendvb\t%xmm0,"
+ " \000pblendw\t\000pcmpeqq\t\000pcmpestri\t\000#PCMPESTRM128rm PSEUDO!\000"
+ "#PCMPESTRM128rr PSEUDO!\000pcmpestrm\t\000pcmpgtq\t\000pcmpistri\t\000#"
+ "PCMPISTRM128rm PSEUDO!\000#PCMPISTRM128rr PSEUDO!\000pcmpistrm\t\000pex"
+ "trb\t\000pextrd\t\000pextrq\t\000phaddd\t\000phaddsw\t\000phaddw\t\000p"
+ "hminposuw\t\000phsubd\t\000phsubsw\t\000phsubw\t\000pinsrb\t\000pinsrd\t"
+ "\000pinsrq\t\000pmaddubsw\t\000pmaxsb\t\000pmaxsd\t\000pmaxud\t\000pmax"
+ "uw\t\000pminsb\t\000pminsd\t\000pminud\t\000pminuw\t\000pmovsxbd\t\000p"
+ "movsxbq\t\000pmovsxbw\t\000pmovsxdq\t\000pmovsxwd\t\000pmovsxwq\t\000pm"
+ "ovzxbd\t\000pmovzxbq\t\000pmovzxbw\t\000pmovzxdq\t\000pmovzxwd\t\000pmo"
+ "vzxwq\t\000pmuldq\t\000pmulhrsw\t\000pmulld\t\000popw\t\000popl\t\000po"
+ "pq\t\000popcntw\t\000popcntl\t\000popcntq\t\000popfw\000popfl\000popfq\000"
+ "popw\t%fs\000popl\t%fs\000popq\t%fs\000popw\t%gs\000popl\t%gs\000popq\t"
+ "%gs\000prefetchnta\t\000prefetcht0\t\000prefetcht1\t\000prefetcht2\t\000"
+ "pshufb\t\000pshufd\t\000pshufhw\t\000pshuflw\t\000psignb\t\000psignd\t\000"
+ "psignw\t\000pslldq\t\000psrldq\t\000ptest \t\000punpckhqdq\t\000punpckl"
+ "qdq\t\000pushw\t\000pushl\t\000pushq\t\000pushfw\000pushfl\000pushfq\000"
+ "pushw\t%fs\000pushl\t%fs\000pushq\t%fs\000pushw\t%gs\000pushl\t%gs\000p"
+ "ushq\t%gs\000rclw\t1, \000rclw\t%cl, \000rclw\t\000rcll\t1, \000rcll\t%"
+ "cl, \000rcll\t\000rclq\t1, \000rclq\t%cl, \000rclq\t\000rclb\t1, \000rc"
+ "lb\t%cl, \000rclb\t\000rcpps\t\000rcpss\t\000rcrw\t1, \000rcrw\t%cl, \000"
+ "rcrw\t\000rcrl\t1, \000rcrl\t%cl, \000rcrl\t\000rcrq\t1, \000rcrq\t%cl,"
+ " \000rcrq\t\000rcrb\t1, \000rcrb\t%cl, \000rcrb\t\000rdmsr\000rdpmc\000"
+ "rdtsc\000rep;movsb\000rep;movsl\000rep;movsq\000rep;movsw\000rep;stosb\000"
+ "rep;stosl\000rep;stosq\000rep;stosw\000ret\000ret\t\000rolw\t\000rolw\t"
+ "%cl, \000roll\t\000roll\t%cl, \000rolq\t\000rolq\t%cl, \000rolb\t\000ro"
+ "lb\t%cl, \000rorw\t\000rorw\t%cl, \000rorl\t\000rorl\t%cl, \000rorq\t\000"
"rorq\t%cl, \000rorb\t\000rorb\t%cl, \000roundpd\t\000roundps\t\000round"
"sd\t\000roundss\t\000rsm\000rsqrtps\t\000rsqrtss\t\000sahf\000sarw\t\000"
"sarw\t%cl, \000sarl\t\000sarl\t%cl, \000sarq\t\000sarq\t%cl, \000sarb\t"
@@ -2729,7 +2732,7 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
switch ((Bits >> 26) & 63) {
default: // unreachable.
case 0:
- // ABS_F, ADJCALLSTACKDOWN32, ADJCALLSTACKDOWN64, ADJCALLSTACKUP32, ADJCA...
+ // DEBUG_VALUE, ABS_F, ADJCALLSTACKDOWN32, ADJCALLSTACKDOWN64, ADJCALLSTA...
return;
break;
case 1:
diff --git a/libclamav/c++/X86GenAsmWriter1.inc b/libclamav/c++/X86GenAsmWriter1.inc
index 6c71a8e..56b4f90 100644
--- a/libclamav/c++/X86GenAsmWriter1.inc
+++ b/libclamav/c++/X86GenAsmWriter1.inc
@@ -21,100 +21,101 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // IMPLICIT_DEF
0U, // SUBREG_TO_REG
0U, // COPY_TO_REGCLASS
- 1U, // ABS_F
+ 1U, // DEBUG_VALUE
+ 13U, // ABS_F
0U, // ABS_Fp32
0U, // ABS_Fp64
0U, // ABS_Fp80
- 134217734U, // ADC16i16
- 272629776U, // ADC16mi
- 272629776U, // ADC16mi8
- 272629776U, // ADC16mr
- 138543120U, // ADC16ri
- 138543120U, // ADC16ri8
- 138674192U, // ADC16rm
- 138543120U, // ADC16rr
- 138543120U, // ADC16rr_REV
- 134217749U, // ADC32i32
- 406847504U, // ADC32mi
- 406847504U, // ADC32mi8
- 406847504U, // ADC32mr
- 138543120U, // ADC32ri
- 138543120U, // ADC32ri8
- 138805264U, // ADC32rm
- 138543120U, // ADC32rr
- 138543120U, // ADC32rr_REV
- 134217760U, // ADC64i32
- 541065232U, // ADC64mi32
- 541065232U, // ADC64mi8
- 541065232U, // ADC64mr
- 138543120U, // ADC64ri32
- 138543120U, // ADC64ri8
- 138936336U, // ADC64rm
- 138543120U, // ADC64rr
- 138543120U, // ADC64rr_REV
- 134217771U, // ADC8i8
- 675282960U, // ADC8mi
- 675282960U, // ADC8mr
- 138543120U, // ADC8ri
- 139067408U, // ADC8rm
- 138543120U, // ADC8rr
- 138543120U, // ADC8rr_REV
- 134217781U, // ADD16i16
- 272629823U, // ADD16mi
- 272629823U, // ADD16mi8
- 272629823U, // ADD16mr
- 138543167U, // ADD16mrmrr
- 138543167U, // ADD16ri
- 138543167U, // ADD16ri8
- 138674239U, // ADD16rm
- 138543167U, // ADD16rr
- 134217796U, // ADD32i32
- 406847551U, // ADD32mi
- 406847551U, // ADD32mi8
- 406847551U, // ADD32mr
- 138543167U, // ADD32mrmrr
- 138543167U, // ADD32ri
- 138543167U, // ADD32ri8
- 138805311U, // ADD32rm
- 138543167U, // ADD32rr
- 134217807U, // ADD64i32
- 541065279U, // ADD64mi32
- 541065279U, // ADD64mi8
- 541065279U, // ADD64mr
- 138543167U, // ADD64mrmrr
- 138543167U, // ADD64ri32
- 138543167U, // ADD64ri8
- 138936383U, // ADD64rm
- 138543167U, // ADD64rr
- 134217818U, // ADD8i8
- 675283007U, // ADD8mi
- 675283007U, // ADD8mr
- 138543167U, // ADD8mrmrr
- 138543167U, // ADD8ri
- 139067455U, // ADD8rm
- 138543167U, // ADD8rr
- 139198564U, // ADDPDrm
- 138543204U, // ADDPDrr
- 139198571U, // ADDPSrm
- 138543211U, // ADDPSrr
- 139329650U, // ADDSDrm
- 139329650U, // ADDSDrm_Int
- 138543218U, // ADDSDrr
- 138543218U, // ADDSDrr_Int
- 139460729U, // ADDSSrm
- 139460729U, // ADDSSrm_Int
- 138543225U, // ADDSSrr
- 138543225U, // ADDSSrr_Int
- 139198592U, // ADDSUBPDrm
- 138543232U, // ADDSUBPDrr
- 139198602U, // ADDSUBPSrm
- 138543242U, // ADDSUBPSrr
- 805306516U, // ADD_F32m
- 939524244U, // ADD_F64m
- 268435610U, // ADD_FI16m
- 402653338U, // ADD_FI32m
- 134217889U, // ADD_FPrST0
- 134217876U, // ADD_FST0r
+ 134217746U, // ADC16i16
+ 272629788U, // ADC16mi
+ 272629788U, // ADC16mi8
+ 272629788U, // ADC16mr
+ 138543132U, // ADC16ri
+ 138543132U, // ADC16ri8
+ 138674204U, // ADC16rm
+ 138543132U, // ADC16rr
+ 138543132U, // ADC16rr_REV
+ 134217761U, // ADC32i32
+ 406847516U, // ADC32mi
+ 406847516U, // ADC32mi8
+ 406847516U, // ADC32mr
+ 138543132U, // ADC32ri
+ 138543132U, // ADC32ri8
+ 138805276U, // ADC32rm
+ 138543132U, // ADC32rr
+ 138543132U, // ADC32rr_REV
+ 134217772U, // ADC64i32
+ 541065244U, // ADC64mi32
+ 541065244U, // ADC64mi8
+ 541065244U, // ADC64mr
+ 138543132U, // ADC64ri32
+ 138543132U, // ADC64ri8
+ 138936348U, // ADC64rm
+ 138543132U, // ADC64rr
+ 138543132U, // ADC64rr_REV
+ 134217783U, // ADC8i8
+ 675282972U, // ADC8mi
+ 675282972U, // ADC8mr
+ 138543132U, // ADC8ri
+ 139067420U, // ADC8rm
+ 138543132U, // ADC8rr
+ 138543132U, // ADC8rr_REV
+ 134217793U, // ADD16i16
+ 272629835U, // ADD16mi
+ 272629835U, // ADD16mi8
+ 272629835U, // ADD16mr
+ 138543179U, // ADD16mrmrr
+ 138543179U, // ADD16ri
+ 138543179U, // ADD16ri8
+ 138674251U, // ADD16rm
+ 138543179U, // ADD16rr
+ 134217808U, // ADD32i32
+ 406847563U, // ADD32mi
+ 406847563U, // ADD32mi8
+ 406847563U, // ADD32mr
+ 138543179U, // ADD32mrmrr
+ 138543179U, // ADD32ri
+ 138543179U, // ADD32ri8
+ 138805323U, // ADD32rm
+ 138543179U, // ADD32rr
+ 134217819U, // ADD64i32
+ 541065291U, // ADD64mi32
+ 541065291U, // ADD64mi8
+ 541065291U, // ADD64mr
+ 138543179U, // ADD64mrmrr
+ 138543179U, // ADD64ri32
+ 138543179U, // ADD64ri8
+ 138936395U, // ADD64rm
+ 138543179U, // ADD64rr
+ 134217830U, // ADD8i8
+ 675283019U, // ADD8mi
+ 675283019U, // ADD8mr
+ 138543179U, // ADD8mrmrr
+ 138543179U, // ADD8ri
+ 139067467U, // ADD8rm
+ 138543179U, // ADD8rr
+ 139198576U, // ADDPDrm
+ 138543216U, // ADDPDrr
+ 139198583U, // ADDPSrm
+ 138543223U, // ADDPSrr
+ 139329662U, // ADDSDrm
+ 139329662U, // ADDSDrm_Int
+ 138543230U, // ADDSDrr
+ 138543230U, // ADDSDrr_Int
+ 139460741U, // ADDSSrm
+ 139460741U, // ADDSSrm_Int
+ 138543237U, // ADDSSrr
+ 138543237U, // ADDSSrr_Int
+ 139198604U, // ADDSUBPDrm
+ 138543244U, // ADDSUBPDrr
+ 139198614U, // ADDSUBPSrm
+ 138543254U, // ADDSUBPSrr
+ 805306528U, // ADD_F32m
+ 939524256U, // ADD_F64m
+ 268435622U, // ADD_FI16m
+ 402653350U, // ADD_FI32m
+ 134217901U, // ADD_FPrST0
+ 134217888U, // ADD_FST0r
0U, // ADD_Fp32
0U, // ADD_Fp32m
0U, // ADD_Fp64
@@ -129,462 +130,462 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ADD_FpI32m32
0U, // ADD_FpI32m64
0U, // ADD_FpI32m80
- 142606484U, // ADD_FrST0
- 168U, // ADJCALLSTACKDOWN32
- 168U, // ADJCALLSTACKDOWN64
- 186U, // ADJCALLSTACKUP32
- 186U, // ADJCALLSTACKUP64
- 134217930U, // AND16i16
- 272629972U, // AND16mi
- 272629972U, // AND16mi8
- 272629972U, // AND16mr
- 138543316U, // AND16ri
- 138543316U, // AND16ri8
- 138674388U, // AND16rm
- 138543316U, // AND16rr
- 138543316U, // AND16rr_REV
- 134217945U, // AND32i32
- 406847700U, // AND32mi
- 406847700U, // AND32mi8
- 406847700U, // AND32mr
- 138543316U, // AND32ri
- 138543316U, // AND32ri8
- 138805460U, // AND32rm
- 138543316U, // AND32rr
- 138543316U, // AND32rr_REV
- 134217956U, // AND64i32
- 541065428U, // AND64mi32
- 541065428U, // AND64mi8
- 541065428U, // AND64mr
- 138543316U, // AND64ri32
- 138543316U, // AND64ri8
- 138936532U, // AND64rm
- 138543316U, // AND64rr
- 138543316U, // AND64rr_REV
- 134217967U, // AND8i8
- 675283156U, // AND8mi
- 675283156U, // AND8mr
- 138543316U, // AND8ri
- 139067604U, // AND8rm
- 138543316U, // AND8rr
- 138543316U, // AND8rr_REV
- 139198713U, // ANDNPDrm
- 138543353U, // ANDNPDrr
- 139198721U, // ANDNPSrm
- 138543361U, // ANDNPSrr
- 139198729U, // ANDPDrm
- 138543369U, // ANDPDrr
- 139198736U, // ANDPSrm
- 138543376U, // ANDPSrr
- 279U, // ATOMADD6432
- 300U, // ATOMAND16
- 319U, // ATOMAND32
- 338U, // ATOMAND64
- 357U, // ATOMAND6432
- 378U, // ATOMAND8
- 396U, // ATOMMAX16
- 415U, // ATOMMAX32
- 434U, // ATOMMAX64
- 453U, // ATOMMIN16
- 472U, // ATOMMIN32
- 491U, // ATOMMIN64
- 510U, // ATOMNAND16
- 530U, // ATOMNAND32
- 550U, // ATOMNAND64
- 570U, // ATOMNAND6432
- 592U, // ATOMNAND8
- 611U, // ATOMOR16
- 629U, // ATOMOR32
- 647U, // ATOMOR64
- 665U, // ATOMOR6432
- 685U, // ATOMOR8
- 702U, // ATOMSUB6432
- 723U, // ATOMSWAP6432
- 745U, // ATOMUMAX16
- 765U, // ATOMUMAX32
- 785U, // ATOMUMAX64
- 805U, // ATOMUMIN16
- 825U, // ATOMUMIN32
- 845U, // ATOMUMIN64
- 865U, // ATOMXOR16
- 884U, // ATOMXOR32
- 903U, // ATOMXOR64
- 922U, // ATOMXOR6432
- 943U, // ATOMXOR8
- 139609025U, // BLENDPDrmi
- 138560449U, // BLENDPDrri
- 139609034U, // BLENDPSrmi
- 138560458U, // BLENDPSrri
- 139625427U, // BLENDVPDrm0
- 138576851U, // BLENDVPDrr0
- 139625437U, // BLENDVPSrm0
- 138576861U, // BLENDVPSrr0
- 139723751U, // BSF16rm
- 139854823U, // BSF16rr
- 139985895U, // BSF32rm
- 139854823U, // BSF32rr
- 140116967U, // BSF64rm
- 139854823U, // BSF64rr
- 139723756U, // BSR16rm
- 139854828U, // BSR16rr
- 139985900U, // BSR32rm
- 139854828U, // BSR32rr
- 140116972U, // BSR64rm
- 139854828U, // BSR64rr
- 134218737U, // BSWAP32r
- 134218737U, // BSWAP64r
- 272630776U, // BT16mi8
- 272630776U, // BT16mr
- 139854840U, // BT16ri8
- 139854840U, // BT16rr
- 406848504U, // BT32mi8
- 406848504U, // BT32mr
- 139854840U, // BT32ri8
- 139854840U, // BT32rr
- 541066232U, // BT64mi8
- 541066232U, // BT64mr
- 139854840U, // BT64ri8
- 139854840U, // BT64rr
- 272630780U, // BTC16mi8
- 272630780U, // BTC16mr
- 139854844U, // BTC16ri8
- 139854844U, // BTC16rr
- 406848508U, // BTC32mi8
- 406848508U, // BTC32mr
- 139854844U, // BTC32ri8
- 139854844U, // BTC32rr
- 541066236U, // BTC64mi8
- 541066236U, // BTC64mr
- 139854844U, // BTC64ri8
- 139854844U, // BTC64rr
- 272630785U, // BTR16mi8
- 272630785U, // BTR16mr
- 139854849U, // BTR16ri8
- 139854849U, // BTR16rr
- 406848513U, // BTR32mi8
- 406848513U, // BTR32mr
- 139854849U, // BTR32ri8
- 139854849U, // BTR32rr
- 541066241U, // BTR64mi8
- 541066241U, // BTR64mr
- 139854849U, // BTR64ri8
- 139854849U, // BTR64rr
- 272630790U, // BTS16mi8
- 272630790U, // BTS16mr
- 139854854U, // BTS16ri8
- 139854854U, // BTS16rr
- 406848518U, // BTS32mi8
- 406848518U, // BTS32mr
- 139854854U, // BTS32ri8
- 139854854U, // BTS32rr
- 541066246U, // BTS64mi8
- 541066246U, // BTS64mr
- 139854854U, // BTS64ri8
- 139854854U, // BTS64rr
- 402654219U, // CALL32m
- 134218763U, // CALL32r
- 536871947U, // CALL64m
- 1073742859U, // CALL64pcrel32
- 134218763U, // CALL64r
- 1073742859U, // CALLpcrel32
- 1041U, // CBW
- 1045U, // CDQ
- 1049U, // CDQE
- 1054U, // CHS_F
+ 142606496U, // ADD_FrST0
+ 180U, // ADJCALLSTACKDOWN32
+ 180U, // ADJCALLSTACKDOWN64
+ 198U, // ADJCALLSTACKUP32
+ 198U, // ADJCALLSTACKUP64
+ 134217942U, // AND16i16
+ 272629984U, // AND16mi
+ 272629984U, // AND16mi8
+ 272629984U, // AND16mr
+ 138543328U, // AND16ri
+ 138543328U, // AND16ri8
+ 138674400U, // AND16rm
+ 138543328U, // AND16rr
+ 138543328U, // AND16rr_REV
+ 134217957U, // AND32i32
+ 406847712U, // AND32mi
+ 406847712U, // AND32mi8
+ 406847712U, // AND32mr
+ 138543328U, // AND32ri
+ 138543328U, // AND32ri8
+ 138805472U, // AND32rm
+ 138543328U, // AND32rr
+ 138543328U, // AND32rr_REV
+ 134217968U, // AND64i32
+ 541065440U, // AND64mi32
+ 541065440U, // AND64mi8
+ 541065440U, // AND64mr
+ 138543328U, // AND64ri32
+ 138543328U, // AND64ri8
+ 138936544U, // AND64rm
+ 138543328U, // AND64rr
+ 138543328U, // AND64rr_REV
+ 134217979U, // AND8i8
+ 675283168U, // AND8mi
+ 675283168U, // AND8mr
+ 138543328U, // AND8ri
+ 139067616U, // AND8rm
+ 138543328U, // AND8rr
+ 138543328U, // AND8rr_REV
+ 139198725U, // ANDNPDrm
+ 138543365U, // ANDNPDrr
+ 139198733U, // ANDNPSrm
+ 138543373U, // ANDNPSrr
+ 139198741U, // ANDPDrm
+ 138543381U, // ANDPDrr
+ 139198748U, // ANDPSrm
+ 138543388U, // ANDPSrr
+ 291U, // ATOMADD6432
+ 312U, // ATOMAND16
+ 331U, // ATOMAND32
+ 350U, // ATOMAND64
+ 369U, // ATOMAND6432
+ 390U, // ATOMAND8
+ 408U, // ATOMMAX16
+ 427U, // ATOMMAX32
+ 446U, // ATOMMAX64
+ 465U, // ATOMMIN16
+ 484U, // ATOMMIN32
+ 503U, // ATOMMIN64
+ 522U, // ATOMNAND16
+ 542U, // ATOMNAND32
+ 562U, // ATOMNAND64
+ 582U, // ATOMNAND6432
+ 604U, // ATOMNAND8
+ 623U, // ATOMOR16
+ 641U, // ATOMOR32
+ 659U, // ATOMOR64
+ 677U, // ATOMOR6432
+ 697U, // ATOMOR8
+ 714U, // ATOMSUB6432
+ 735U, // ATOMSWAP6432
+ 757U, // ATOMUMAX16
+ 777U, // ATOMUMAX32
+ 797U, // ATOMUMAX64
+ 817U, // ATOMUMIN16
+ 837U, // ATOMUMIN32
+ 857U, // ATOMUMIN64
+ 877U, // ATOMXOR16
+ 896U, // ATOMXOR32
+ 915U, // ATOMXOR64
+ 934U, // ATOMXOR6432
+ 955U, // ATOMXOR8
+ 139609037U, // BLENDPDrmi
+ 138560461U, // BLENDPDrri
+ 139609046U, // BLENDPSrmi
+ 138560470U, // BLENDPSrri
+ 139625439U, // BLENDVPDrm0
+ 138576863U, // BLENDVPDrr0
+ 139625449U, // BLENDVPSrm0
+ 138576873U, // BLENDVPSrr0
+ 139723763U, // BSF16rm
+ 139854835U, // BSF16rr
+ 139985907U, // BSF32rm
+ 139854835U, // BSF32rr
+ 140116979U, // BSF64rm
+ 139854835U, // BSF64rr
+ 139723768U, // BSR16rm
+ 139854840U, // BSR16rr
+ 139985912U, // BSR32rm
+ 139854840U, // BSR32rr
+ 140116984U, // BSR64rm
+ 139854840U, // BSR64rr
+ 134218749U, // BSWAP32r
+ 134218749U, // BSWAP64r
+ 272630788U, // BT16mi8
+ 272630788U, // BT16mr
+ 139854852U, // BT16ri8
+ 139854852U, // BT16rr
+ 406848516U, // BT32mi8
+ 406848516U, // BT32mr
+ 139854852U, // BT32ri8
+ 139854852U, // BT32rr
+ 541066244U, // BT64mi8
+ 541066244U, // BT64mr
+ 139854852U, // BT64ri8
+ 139854852U, // BT64rr
+ 272630792U, // BTC16mi8
+ 272630792U, // BTC16mr
+ 139854856U, // BTC16ri8
+ 139854856U, // BTC16rr
+ 406848520U, // BTC32mi8
+ 406848520U, // BTC32mr
+ 139854856U, // BTC32ri8
+ 139854856U, // BTC32rr
+ 541066248U, // BTC64mi8
+ 541066248U, // BTC64mr
+ 139854856U, // BTC64ri8
+ 139854856U, // BTC64rr
+ 272630797U, // BTR16mi8
+ 272630797U, // BTR16mr
+ 139854861U, // BTR16ri8
+ 139854861U, // BTR16rr
+ 406848525U, // BTR32mi8
+ 406848525U, // BTR32mr
+ 139854861U, // BTR32ri8
+ 139854861U, // BTR32rr
+ 541066253U, // BTR64mi8
+ 541066253U, // BTR64mr
+ 139854861U, // BTR64ri8
+ 139854861U, // BTR64rr
+ 272630802U, // BTS16mi8
+ 272630802U, // BTS16mr
+ 139854866U, // BTS16ri8
+ 139854866U, // BTS16rr
+ 406848530U, // BTS32mi8
+ 406848530U, // BTS32mr
+ 139854866U, // BTS32ri8
+ 139854866U, // BTS32rr
+ 541066258U, // BTS64mi8
+ 541066258U, // BTS64mr
+ 139854866U, // BTS64ri8
+ 139854866U, // BTS64rr
+ 402654231U, // CALL32m
+ 134218775U, // CALL32r
+ 536871959U, // CALL64m
+ 1073742871U, // CALL64pcrel32
+ 134218775U, // CALL64r
+ 1073742871U, // CALLpcrel32
+ 1053U, // CBW
+ 1057U, // CDQ
+ 1061U, // CDQE
+ 1066U, // CHS_F
0U, // CHS_Fp32
0U, // CHS_Fp64
0U, // CHS_Fp80
- 1059U, // CLC
- 1063U, // CLD
- 671089707U, // CLFLUSH
- 1076U, // CLI
- 1080U, // CLTS
- 1085U, // CMC
- 138675265U, // CMOVA16rm
- 138544193U, // CMOVA16rr
- 138806337U, // CMOVA32rm
- 138544193U, // CMOVA32rr
- 138937409U, // CMOVA64rm
- 138544193U, // CMOVA64rr
- 138675272U, // CMOVAE16rm
- 138544200U, // CMOVAE16rr
- 138806344U, // CMOVAE32rm
- 138544200U, // CMOVAE32rr
- 138937416U, // CMOVAE64rm
- 138544200U, // CMOVAE64rr
- 138675280U, // CMOVB16rm
- 138544208U, // CMOVB16rr
- 138806352U, // CMOVB32rm
- 138544208U, // CMOVB32rr
- 138937424U, // CMOVB64rm
- 138544208U, // CMOVB64rr
- 138675287U, // CMOVBE16rm
- 138544215U, // CMOVBE16rr
- 138806359U, // CMOVBE32rm
- 138544215U, // CMOVBE32rr
- 138937431U, // CMOVBE64rm
- 138544215U, // CMOVBE64rr
- 134218847U, // CMOVBE_F
+ 1071U, // CLC
+ 1075U, // CLD
+ 671089719U, // CLFLUSH
+ 1088U, // CLI
+ 1092U, // CLTS
+ 1097U, // CMC
+ 138675277U, // CMOVA16rm
+ 138544205U, // CMOVA16rr
+ 138806349U, // CMOVA32rm
+ 138544205U, // CMOVA32rr
+ 138937421U, // CMOVA64rm
+ 138544205U, // CMOVA64rr
+ 138675284U, // CMOVAE16rm
+ 138544212U, // CMOVAE16rr
+ 138806356U, // CMOVAE32rm
+ 138544212U, // CMOVAE32rr
+ 138937428U, // CMOVAE64rm
+ 138544212U, // CMOVAE64rr
+ 138675292U, // CMOVB16rm
+ 138544220U, // CMOVB16rr
+ 138806364U, // CMOVB32rm
+ 138544220U, // CMOVB32rr
+ 138937436U, // CMOVB64rm
+ 138544220U, // CMOVB64rr
+ 138675299U, // CMOVBE16rm
+ 138544227U, // CMOVBE16rr
+ 138806371U, // CMOVBE32rm
+ 138544227U, // CMOVBE32rr
+ 138937443U, // CMOVBE64rm
+ 138544227U, // CMOVBE64rr
+ 134218859U, // CMOVBE_F
0U, // CMOVBE_Fp32
0U, // CMOVBE_Fp64
0U, // CMOVBE_Fp80
- 134218864U, // CMOVB_F
+ 134218876U, // CMOVB_F
0U, // CMOVB_Fp32
0U, // CMOVB_Fp64
0U, // CMOVB_Fp80
- 138675328U, // CMOVE16rm
- 138544256U, // CMOVE16rr
- 138806400U, // CMOVE32rm
- 138544256U, // CMOVE32rr
- 138937472U, // CMOVE64rm
- 138544256U, // CMOVE64rr
- 134218887U, // CMOVE_F
+ 138675340U, // CMOVE16rm
+ 138544268U, // CMOVE16rr
+ 138806412U, // CMOVE32rm
+ 138544268U, // CMOVE32rr
+ 138937484U, // CMOVE64rm
+ 138544268U, // CMOVE64rr
+ 134218899U, // CMOVE_F
0U, // CMOVE_Fp32
0U, // CMOVE_Fp64
0U, // CMOVE_Fp80
- 138675351U, // CMOVG16rm
- 138544279U, // CMOVG16rr
- 138806423U, // CMOVG32rm
- 138544279U, // CMOVG32rr
- 138937495U, // CMOVG64rm
- 138544279U, // CMOVG64rr
- 138675358U, // CMOVGE16rm
- 138544286U, // CMOVGE16rr
- 138806430U, // CMOVGE32rm
- 138544286U, // CMOVGE32rr
- 138937502U, // CMOVGE64rm
- 138544286U, // CMOVGE64rr
- 138675366U, // CMOVL16rm
- 138544294U, // CMOVL16rr
- 138806438U, // CMOVL32rm
- 138544294U, // CMOVL32rr
- 138937510U, // CMOVL64rm
- 138544294U, // CMOVL64rr
- 138675373U, // CMOVLE16rm
- 138544301U, // CMOVLE16rr
- 138806445U, // CMOVLE32rm
- 138544301U, // CMOVLE32rr
- 138937517U, // CMOVLE64rm
- 138544301U, // CMOVLE64rr
- 134218933U, // CMOVNBE_F
+ 138675363U, // CMOVG16rm
+ 138544291U, // CMOVG16rr
+ 138806435U, // CMOVG32rm
+ 138544291U, // CMOVG32rr
+ 138937507U, // CMOVG64rm
+ 138544291U, // CMOVG64rr
+ 138675370U, // CMOVGE16rm
+ 138544298U, // CMOVGE16rr
+ 138806442U, // CMOVGE32rm
+ 138544298U, // CMOVGE32rr
+ 138937514U, // CMOVGE64rm
+ 138544298U, // CMOVGE64rr
+ 138675378U, // CMOVL16rm
+ 138544306U, // CMOVL16rr
+ 138806450U, // CMOVL32rm
+ 138544306U, // CMOVL32rr
+ 138937522U, // CMOVL64rm
+ 138544306U, // CMOVL64rr
+ 138675385U, // CMOVLE16rm
+ 138544313U, // CMOVLE16rr
+ 138806457U, // CMOVLE32rm
+ 138544313U, // CMOVLE32rr
+ 138937529U, // CMOVLE64rm
+ 138544313U, // CMOVLE64rr
+ 134218945U, // CMOVNBE_F
0U, // CMOVNBE_Fp32
0U, // CMOVNBE_Fp64
0U, // CMOVNBE_Fp80
- 134218951U, // CMOVNB_F
+ 134218963U, // CMOVNB_F
0U, // CMOVNB_Fp32
0U, // CMOVNB_Fp64
0U, // CMOVNB_Fp80
- 138675416U, // CMOVNE16rm
- 138544344U, // CMOVNE16rr
- 138806488U, // CMOVNE32rm
- 138544344U, // CMOVNE32rr
- 138937560U, // CMOVNE64rm
- 138544344U, // CMOVNE64rr
- 134218976U, // CMOVNE_F
+ 138675428U, // CMOVNE16rm
+ 138544356U, // CMOVNE16rr
+ 138806500U, // CMOVNE32rm
+ 138544356U, // CMOVNE32rr
+ 138937572U, // CMOVNE64rm
+ 138544356U, // CMOVNE64rr
+ 134218988U, // CMOVNE_F
0U, // CMOVNE_Fp32
0U, // CMOVNE_Fp64
0U, // CMOVNE_Fp80
- 138675441U, // CMOVNO16rm
- 138544369U, // CMOVNO16rr
- 138806513U, // CMOVNO32rm
- 138544369U, // CMOVNO32rr
- 138937585U, // CMOVNO64rm
- 138544369U, // CMOVNO64rr
- 138675449U, // CMOVNP16rm
- 138544377U, // CMOVNP16rr
- 138806521U, // CMOVNP32rm
- 138544377U, // CMOVNP32rr
- 138937593U, // CMOVNP64rm
- 138544377U, // CMOVNP64rr
- 134219009U, // CMOVNP_F
+ 138675453U, // CMOVNO16rm
+ 138544381U, // CMOVNO16rr
+ 138806525U, // CMOVNO32rm
+ 138544381U, // CMOVNO32rr
+ 138937597U, // CMOVNO64rm
+ 138544381U, // CMOVNO64rr
+ 138675461U, // CMOVNP16rm
+ 138544389U, // CMOVNP16rr
+ 138806533U, // CMOVNP32rm
+ 138544389U, // CMOVNP32rr
+ 138937605U, // CMOVNP64rm
+ 138544389U, // CMOVNP64rr
+ 134219021U, // CMOVNP_F
0U, // CMOVNP_Fp32
0U, // CMOVNP_Fp64
0U, // CMOVNP_Fp80
- 138675474U, // CMOVNS16rm
- 138544402U, // CMOVNS16rr
- 138806546U, // CMOVNS32rm
- 138544402U, // CMOVNS32rr
- 138937618U, // CMOVNS64rm
- 138544402U, // CMOVNS64rr
- 138675482U, // CMOVO16rm
- 138544410U, // CMOVO16rr
- 138806554U, // CMOVO32rm
- 138544410U, // CMOVO32rr
- 138937626U, // CMOVO64rm
- 138544410U, // CMOVO64rr
- 138675489U, // CMOVP16rm
- 138544417U, // CMOVP16rr
- 138806561U, // CMOVP32rm
- 138544417U, // CMOVP32rr
- 138937633U, // CMOVP64rm
- 138544417U, // CMOVP64rr
- 134219048U, // CMOVP_F
+ 138675486U, // CMOVNS16rm
+ 138544414U, // CMOVNS16rr
+ 138806558U, // CMOVNS32rm
+ 138544414U, // CMOVNS32rr
+ 138937630U, // CMOVNS64rm
+ 138544414U, // CMOVNS64rr
+ 138675494U, // CMOVO16rm
+ 138544422U, // CMOVO16rr
+ 138806566U, // CMOVO32rm
+ 138544422U, // CMOVO32rr
+ 138937638U, // CMOVO64rm
+ 138544422U, // CMOVO64rr
+ 138675501U, // CMOVP16rm
+ 138544429U, // CMOVP16rr
+ 138806573U, // CMOVP32rm
+ 138544429U, // CMOVP32rr
+ 138937645U, // CMOVP64rm
+ 138544429U, // CMOVP64rr
+ 134219060U, // CMOVP_F
0U, // CMOVP_Fp32
0U, // CMOVP_Fp64
0U, // CMOVP_Fp80
- 138675513U, // CMOVS16rm
- 138544441U, // CMOVS16rr
- 138806585U, // CMOVS32rm
- 138544441U, // CMOVS32rr
- 138937657U, // CMOVS64rm
- 138544441U, // CMOVS64rr
- 1344U, // CMOV_FR32
- 1363U, // CMOV_FR64
- 1382U, // CMOV_GR8
- 1400U, // CMOV_V1I64
- 1420U, // CMOV_V2F64
- 1440U, // CMOV_V2I64
- 1460U, // CMOV_V4F32
- 134219208U, // CMP16i16
- 272631250U, // CMP16mi
- 272631250U, // CMP16mi8
- 272631250U, // CMP16mr
- 139855314U, // CMP16mrmrr
- 139855314U, // CMP16ri
- 139855314U, // CMP16ri8
- 139724242U, // CMP16rm
- 139855314U, // CMP16rr
- 134219223U, // CMP32i32
- 406848978U, // CMP32mi
- 406848978U, // CMP32mi8
- 406848978U, // CMP32mr
- 139855314U, // CMP32mrmrr
- 139855314U, // CMP32ri
- 139855314U, // CMP32ri8
- 139986386U, // CMP32rm
- 139855314U, // CMP32rr
- 134219234U, // CMP64i32
- 541066706U, // CMP64mi32
- 541066706U, // CMP64mi8
- 541066706U, // CMP64mr
- 139855314U, // CMP64mrmrr
- 139855314U, // CMP64ri32
- 139855314U, // CMP64ri8
- 140117458U, // CMP64rm
- 139855314U, // CMP64rr
- 134219245U, // CMP8i8
- 675284434U, // CMP8mi
- 675284434U, // CMP8mr
- 139855314U, // CMP8mrmrr
- 139855314U, // CMP8ri
- 140248530U, // CMP8rm
- 139855314U, // CMP8rr
- 1221330423U, // CMPPDrmi
- 1354892791U, // CMPPDrri
- 1225524727U, // CMPPSrmi
- 1359087095U, // CMPPSrri
- 1531U, // CMPS16
- 1531U, // CMPS32
- 1531U, // CMPS64
- 1531U, // CMPS8
- 1229850103U, // CMPSDrm
- 1363281399U, // CMPSDrr
- 1234175479U, // CMPSSrm
- 1367475703U, // CMPSSrr
- 1476396544U, // CMPXCHG16B
- 272631308U, // CMPXCHG16rm
- 139855372U, // CMPXCHG16rr
- 406849036U, // CMPXCHG32rm
- 139855372U, // CMPXCHG32rr
- 541066764U, // CMPXCHG64rm
- 139855372U, // CMPXCHG64rr
- 536872469U, // CMPXCHG8B
- 675284492U, // CMPXCHG8rm
- 139855372U, // CMPXCHG8rr
- 140379680U, // COMISDrm
- 139855392U, // COMISDrr
- 140379688U, // COMISSrm
- 139855400U, // COMISSrr
- 134219312U, // COMP_FST0r
- 134219319U, // COM_FIPr
- 134219335U, // COM_FIr
- 134219350U, // COM_FST0r
- 1628U, // COS_F
+ 138675525U, // CMOVS16rm
+ 138544453U, // CMOVS16rr
+ 138806597U, // CMOVS32rm
+ 138544453U, // CMOVS32rr
+ 138937669U, // CMOVS64rm
+ 138544453U, // CMOVS64rr
+ 1356U, // CMOV_FR32
+ 1375U, // CMOV_FR64
+ 1394U, // CMOV_GR8
+ 1412U, // CMOV_V1I64
+ 1432U, // CMOV_V2F64
+ 1452U, // CMOV_V2I64
+ 1472U, // CMOV_V4F32
+ 134219220U, // CMP16i16
+ 272631262U, // CMP16mi
+ 272631262U, // CMP16mi8
+ 272631262U, // CMP16mr
+ 139855326U, // CMP16mrmrr
+ 139855326U, // CMP16ri
+ 139855326U, // CMP16ri8
+ 139724254U, // CMP16rm
+ 139855326U, // CMP16rr
+ 134219235U, // CMP32i32
+ 406848990U, // CMP32mi
+ 406848990U, // CMP32mi8
+ 406848990U, // CMP32mr
+ 139855326U, // CMP32mrmrr
+ 139855326U, // CMP32ri
+ 139855326U, // CMP32ri8
+ 139986398U, // CMP32rm
+ 139855326U, // CMP32rr
+ 134219246U, // CMP64i32
+ 541066718U, // CMP64mi32
+ 541066718U, // CMP64mi8
+ 541066718U, // CMP64mr
+ 139855326U, // CMP64mrmrr
+ 139855326U, // CMP64ri32
+ 139855326U, // CMP64ri8
+ 140117470U, // CMP64rm
+ 139855326U, // CMP64rr
+ 134219257U, // CMP8i8
+ 675284446U, // CMP8mi
+ 675284446U, // CMP8mr
+ 139855326U, // CMP8mrmrr
+ 139855326U, // CMP8ri
+ 140248542U, // CMP8rm
+ 139855326U, // CMP8rr
+ 1221330435U, // CMPPDrmi
+ 1354892803U, // CMPPDrri
+ 1225524739U, // CMPPSrmi
+ 1359087107U, // CMPPSrri
+ 1543U, // CMPS16
+ 1543U, // CMPS32
+ 1543U, // CMPS64
+ 1543U, // CMPS8
+ 1229850115U, // CMPSDrm
+ 1363281411U, // CMPSDrr
+ 1234175491U, // CMPSSrm
+ 1367475715U, // CMPSSrr
+ 1476396556U, // CMPXCHG16B
+ 272631320U, // CMPXCHG16rm
+ 139855384U, // CMPXCHG16rr
+ 406849048U, // CMPXCHG32rm
+ 139855384U, // CMPXCHG32rr
+ 541066776U, // CMPXCHG64rm
+ 139855384U, // CMPXCHG64rr
+ 536872481U, // CMPXCHG8B
+ 675284504U, // CMPXCHG8rm
+ 139855384U, // CMPXCHG8rr
+ 140379692U, // COMISDrm
+ 139855404U, // COMISDrr
+ 140379700U, // COMISSrm
+ 139855412U, // COMISSrr
+ 134219324U, // COMP_FST0r
+ 134219331U, // COM_FIPr
+ 134219347U, // COM_FIr
+ 134219362U, // COM_FST0r
+ 1640U, // COS_F
0U, // COS_Fp32
0U, // COS_Fp64
0U, // COS_Fp80
- 1633U, // CPUID
- 1639U, // CQO
- 1639974507U, // CRC32m16
- 1644168811U, // CRC32m32
- 1648363115U, // CRC32m8
- 1652557419U, // CRC32r16
- 1652557419U, // CRC32r32
- 1652557419U, // CRC32r8
- 1656751723U, // CRC64m64
- 1652557419U, // CRC64r64
- 140379763U, // CVTDQ2PDrm
- 139855475U, // CVTDQ2PDrr
- 140379773U, // CVTDQ2PSrm
- 139855485U, // CVTDQ2PSrr
- 140379783U, // CVTPD2DQrm
- 139855495U, // CVTPD2DQrr
- 140379793U, // CVTPD2PSrm
- 139855505U, // CVTPD2PSrr
- 140379803U, // CVTPS2DQrm
- 139855515U, // CVTPS2DQrr
- 140510885U, // CVTPS2PDrm
- 139855525U, // CVTPS2PDrr
- 140510895U, // CVTSD2SI64rm
- 139855535U, // CVTSD2SI64rr
- 140510905U, // CVTSD2SSrm
- 139855545U, // CVTSD2SSrr
- 140117699U, // CVTSI2SD64rm
- 139855555U, // CVTSI2SD64rr
- 139986627U, // CVTSI2SDrm
- 139855555U, // CVTSI2SDrr
- 140117709U, // CVTSI2SS64rm
- 139855565U, // CVTSI2SS64rr
- 139986637U, // CVTSI2SSrm
- 139855565U, // CVTSI2SSrr
- 140642007U, // CVTSS2SDrm
- 139855575U, // CVTSS2SDrr
- 140642017U, // CVTSS2SI64rm
- 139855585U, // CVTSS2SI64rr
- 140642017U, // CVTSS2SIrm
- 139855585U, // CVTSS2SIrr
- 140379883U, // CVTTPS2DQrm
- 139855595U, // CVTTPS2DQrr
- 140510966U, // CVTTSD2SI64rm
- 139855606U, // CVTTSD2SI64rr
- 140510966U, // CVTTSD2SIrm
- 139855606U, // CVTTSD2SIrr
- 140642049U, // CVTTSS2SI64rm
- 139855617U, // CVTTSS2SI64rr
- 140642049U, // CVTTSS2SIrm
- 139855617U, // CVTTSS2SIrr
- 1804U, // CWD
- 1808U, // CWDE
- 268437269U, // DEC16m
- 134219541U, // DEC16r
- 402654997U, // DEC32m
- 134219541U, // DEC32r
- 268437269U, // DEC64_16m
- 134219541U, // DEC64_16r
- 402654997U, // DEC64_32m
- 134219541U, // DEC64_32r
- 536872725U, // DEC64m
- 134219541U, // DEC64r
- 671090453U, // DEC8m
- 134219541U, // DEC8r
- 268437274U, // DIV16m
- 134219546U, // DIV16r
- 402655002U, // DIV32m
- 134219546U, // DIV32r
- 536872730U, // DIV64m
- 134219546U, // DIV64r
- 671090458U, // DIV8m
- 134219546U, // DIV8r
- 139200287U, // DIVPDrm
- 138544927U, // DIVPDrr
- 139200294U, // DIVPSrm
- 138544934U, // DIVPSrr
- 805308205U, // DIVR_F32m
- 939525933U, // DIVR_F64m
- 268437300U, // DIVR_FI16m
- 402655028U, // DIVR_FI32m
- 134219580U, // DIVR_FPrST0
- 134219565U, // DIVR_FST0r
+ 1645U, // CPUID
+ 1651U, // CQO
+ 1639974519U, // CRC32m16
+ 1644168823U, // CRC32m32
+ 1648363127U, // CRC32m8
+ 1652557431U, // CRC32r16
+ 1652557431U, // CRC32r32
+ 1652557431U, // CRC32r8
+ 1656751735U, // CRC64m64
+ 1652557431U, // CRC64r64
+ 140379775U, // CVTDQ2PDrm
+ 139855487U, // CVTDQ2PDrr
+ 140379785U, // CVTDQ2PSrm
+ 139855497U, // CVTDQ2PSrr
+ 140379795U, // CVTPD2DQrm
+ 139855507U, // CVTPD2DQrr
+ 140379805U, // CVTPD2PSrm
+ 139855517U, // CVTPD2PSrr
+ 140379815U, // CVTPS2DQrm
+ 139855527U, // CVTPS2DQrr
+ 140510897U, // CVTPS2PDrm
+ 139855537U, // CVTPS2PDrr
+ 140510907U, // CVTSD2SI64rm
+ 139855547U, // CVTSD2SI64rr
+ 140510917U, // CVTSD2SSrm
+ 139855557U, // CVTSD2SSrr
+ 140117711U, // CVTSI2SD64rm
+ 139855567U, // CVTSI2SD64rr
+ 139986639U, // CVTSI2SDrm
+ 139855567U, // CVTSI2SDrr
+ 140117721U, // CVTSI2SS64rm
+ 139855577U, // CVTSI2SS64rr
+ 139986649U, // CVTSI2SSrm
+ 139855577U, // CVTSI2SSrr
+ 140642019U, // CVTSS2SDrm
+ 139855587U, // CVTSS2SDrr
+ 140642029U, // CVTSS2SI64rm
+ 139855597U, // CVTSS2SI64rr
+ 140642029U, // CVTSS2SIrm
+ 139855597U, // CVTSS2SIrr
+ 140379895U, // CVTTPS2DQrm
+ 139855607U, // CVTTPS2DQrr
+ 140510978U, // CVTTSD2SI64rm
+ 139855618U, // CVTTSD2SI64rr
+ 140510978U, // CVTTSD2SIrm
+ 139855618U, // CVTTSD2SIrr
+ 140642061U, // CVTTSS2SI64rm
+ 139855629U, // CVTTSS2SI64rr
+ 140642061U, // CVTTSS2SIrm
+ 139855629U, // CVTTSS2SIrr
+ 1816U, // CWD
+ 1820U, // CWDE
+ 268437281U, // DEC16m
+ 134219553U, // DEC16r
+ 402655009U, // DEC32m
+ 134219553U, // DEC32r
+ 268437281U, // DEC64_16m
+ 134219553U, // DEC64_16r
+ 402655009U, // DEC64_32m
+ 134219553U, // DEC64_32r
+ 536872737U, // DEC64m
+ 134219553U, // DEC64r
+ 671090465U, // DEC8m
+ 134219553U, // DEC8r
+ 268437286U, // DIV16m
+ 134219558U, // DIV16r
+ 402655014U, // DIV32m
+ 134219558U, // DIV32r
+ 536872742U, // DIV64m
+ 134219558U, // DIV64r
+ 671090470U, // DIV8m
+ 134219558U, // DIV8r
+ 139200299U, // DIVPDrm
+ 138544939U, // DIVPDrr
+ 139200306U, // DIVPSrm
+ 138544946U, // DIVPSrr
+ 805308217U, // DIVR_F32m
+ 939525945U, // DIVR_F64m
+ 268437312U, // DIVR_FI16m
+ 402655040U, // DIVR_FI32m
+ 134219592U, // DIVR_FPrST0
+ 134219577U, // DIVR_FST0r
0U, // DIVR_Fp32m
0U, // DIVR_Fp64m
0U, // DIVR_Fp64m32
@@ -596,21 +597,21 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // DIVR_FpI32m32
0U, // DIVR_FpI32m64
0U, // DIVR_FpI32m80
- 142608173U, // DIVR_FrST0
- 139331396U, // DIVSDrm
- 139331396U, // DIVSDrm_Int
- 138544964U, // DIVSDrr
- 138544964U, // DIVSDrr_Int
- 139462475U, // DIVSSrm
- 139462475U, // DIVSSrm_Int
- 138544971U, // DIVSSrr
- 138544971U, // DIVSSrr_Int
- 805308242U, // DIV_F32m
- 939525970U, // DIV_F64m
- 268437336U, // DIV_FI16m
- 402655064U, // DIV_FI32m
- 134219615U, // DIV_FPrST0
- 134219602U, // DIV_FST0r
+ 142608185U, // DIVR_FrST0
+ 139331408U, // DIVSDrm
+ 139331408U, // DIVSDrm_Int
+ 138544976U, // DIVSDrr
+ 138544976U, // DIVSDrr_Int
+ 139462487U, // DIVSSrm
+ 139462487U, // DIVSSrm_Int
+ 138544983U, // DIVSSrr
+ 138544983U, // DIVSSrr_Int
+ 805308254U, // DIV_F32m
+ 939525982U, // DIV_F64m
+ 268437348U, // DIV_FI16m
+ 402655076U, // DIV_FI32m
+ 134219627U, // DIV_FPrST0
+ 134219614U, // DIV_FST0r
0U, // DIV_Fp32
0U, // DIV_Fp32m
0U, // DIV_Fp64
@@ -625,82 +626,82 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // DIV_FpI32m32
0U, // DIV_FpI32m64
0U, // DIV_FpI32m80
- 142608210U, // DIV_FrST0
- 139609958U, // DPPDrmi
- 138561382U, // DPPDrri
- 139609964U, // DPPSrmi
- 138561388U, // DPPSrri
- 134219634U, // EH_RETURN
- 134219634U, // EH_RETURN64
- 139855753U, // ENTER
- 809518992U, // EXTRACTPSmr
- 139872144U, // EXTRACTPSrr
- 1947U, // F2XM1
- 139855777U, // FARCALL16i
- 1744832417U, // FARCALL16m
- 139855777U, // FARCALL32i
- 1744832417U, // FARCALL32m
- 1744832417U, // FARCALL64
- 139855784U, // FARJMP16i
- 1744832424U, // FARJMP16m
- 139855784U, // FARJMP32i
- 1744832424U, // FARJMP32m
- 1744832424U, // FARJMP64
- 805308334U, // FBLDm
- 805308340U, // FBSTPm
- 805307990U, // FCOM32m
- 939525718U, // FCOM64m
- 805307952U, // FCOMP32m
- 939525680U, // FCOMP64m
- 1979U, // FCOMPP
- 1986U, // FDECSTP
- 134219722U, // FFREE
- 268437457U, // FICOM16m
- 402655185U, // FICOM32m
- 268437464U, // FICOMP16m
- 402655192U, // FICOMP32m
- 2016U, // FINCSTP
- 402655208U, // FISTTP32m
- 268437488U, // FLDCW16m
- 805308407U, // FLDENVm
- 2047U, // FLDL2E
- 2054U, // FLDL2T
- 2061U, // FLDLG2
- 2068U, // FLDLN2
- 2075U, // FLDPI
- 2081U, // FNCLEX
- 2088U, // FNINIT
- 2095U, // FNOP
- 268437556U, // FNSTCW16m
- 2108U, // FNSTSW8r
- 805308487U, // FNSTSWm
- 2127U, // FP32_TO_INT16_IN_MEM
- 2158U, // FP32_TO_INT32_IN_MEM
- 2189U, // FP32_TO_INT64_IN_MEM
- 2220U, // FP64_TO_INT16_IN_MEM
- 2251U, // FP64_TO_INT32_IN_MEM
- 2282U, // FP64_TO_INT64_IN_MEM
- 2313U, // FP80_TO_INT16_IN_MEM
- 2344U, // FP80_TO_INT32_IN_MEM
- 2375U, // FP80_TO_INT64_IN_MEM
- 2406U, // FPATAN
- 2413U, // FPREM
- 2419U, // FPREM1
- 2426U, // FPTAN
- 2432U, // FP_REG_KILL
- 2446U, // FRNDINT
- 805308822U, // FRSTORm
- 805308830U, // FSAVEm
- 2470U, // FSCALE
- 2477U, // FSINCOS
- 805308853U, // FSTENVm
- 1879050686U, // FS_MOV32rm
- 2504U, // FXAM
- 1744832973U, // FXRSTOR
- 1744832982U, // FXSAVE
- 2526U, // FXTRACT
- 2534U, // FYL2X
- 2540U, // FYL2XP1
+ 142608222U, // DIV_FrST0
+ 139609970U, // DPPDrmi
+ 138561394U, // DPPDrri
+ 139609976U, // DPPSrmi
+ 138561400U, // DPPSrri
+ 134219646U, // EH_RETURN
+ 134219646U, // EH_RETURN64
+ 139855765U, // ENTER
+ 809519004U, // EXTRACTPSmr
+ 139872156U, // EXTRACTPSrr
+ 1959U, // F2XM1
+ 139855789U, // FARCALL16i
+ 1744832429U, // FARCALL16m
+ 139855789U, // FARCALL32i
+ 1744832429U, // FARCALL32m
+ 1744832429U, // FARCALL64
+ 139855796U, // FARJMP16i
+ 1744832436U, // FARJMP16m
+ 139855796U, // FARJMP32i
+ 1744832436U, // FARJMP32m
+ 1744832436U, // FARJMP64
+ 805308346U, // FBLDm
+ 805308352U, // FBSTPm
+ 805308002U, // FCOM32m
+ 939525730U, // FCOM64m
+ 805307964U, // FCOMP32m
+ 939525692U, // FCOMP64m
+ 1991U, // FCOMPP
+ 1998U, // FDECSTP
+ 134219734U, // FFREE
+ 268437469U, // FICOM16m
+ 402655197U, // FICOM32m
+ 268437476U, // FICOMP16m
+ 402655204U, // FICOMP32m
+ 2028U, // FINCSTP
+ 402655220U, // FISTTP32m
+ 268437500U, // FLDCW16m
+ 805308419U, // FLDENVm
+ 2059U, // FLDL2E
+ 2066U, // FLDL2T
+ 2073U, // FLDLG2
+ 2080U, // FLDLN2
+ 2087U, // FLDPI
+ 2093U, // FNCLEX
+ 2100U, // FNINIT
+ 2107U, // FNOP
+ 268437568U, // FNSTCW16m
+ 2120U, // FNSTSW8r
+ 805308499U, // FNSTSWm
+ 2139U, // FP32_TO_INT16_IN_MEM
+ 2170U, // FP32_TO_INT32_IN_MEM
+ 2201U, // FP32_TO_INT64_IN_MEM
+ 2232U, // FP64_TO_INT16_IN_MEM
+ 2263U, // FP64_TO_INT32_IN_MEM
+ 2294U, // FP64_TO_INT64_IN_MEM
+ 2325U, // FP80_TO_INT16_IN_MEM
+ 2356U, // FP80_TO_INT32_IN_MEM
+ 2387U, // FP80_TO_INT64_IN_MEM
+ 2418U, // FPATAN
+ 2425U, // FPREM
+ 2431U, // FPREM1
+ 2438U, // FPTAN
+ 2444U, // FP_REG_KILL
+ 2458U, // FRNDINT
+ 805308834U, // FRSTORm
+ 805308842U, // FSAVEm
+ 2482U, // FSCALE
+ 2489U, // FSINCOS
+ 805308865U, // FSTENVm
+ 1879050698U, // FS_MOV32rm
+ 2516U, // FXAM
+ 1744832985U, // FXRSTOR
+ 1744832994U, // FXSAVE
+ 2538U, // FXTRACT
+ 2546U, // FYL2X
+ 2552U, // FYL2XP1
0U, // FpGET_ST0_32
0U, // FpGET_ST0_64
0U, // FpGET_ST0_80
@@ -713,49 +714,49 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // FpSET_ST1_32
0U, // FpSET_ST1_64
0U, // FpSET_ST1_80
- 139198713U, // FsANDNPDrm
- 138543353U, // FsANDNPDrr
- 139198721U, // FsANDNPSrm
- 138543361U, // FsANDNPSrr
- 139198729U, // FsANDPDrm
- 138543369U, // FsANDPDrr
- 139198736U, // FsANDPSrm
- 138543376U, // FsANDPSrr
- 140773876U, // FsFLD0SD
- 140773876U, // FsFLD0SS
- 140380666U, // FsMOVAPDrm
- 139856378U, // FsMOVAPDrr
- 140380674U, // FsMOVAPSrm
- 139856386U, // FsMOVAPSrr
- 139201034U, // FsORPDrm
- 138545674U, // FsORPDrr
- 139201040U, // FsORPSrm
- 138545680U, // FsORPSrr
- 139201046U, // FsXORPDrm
- 138545686U, // FsXORPDrr
- 139201053U, // FsXORPSrm
- 138545693U, // FsXORPSrr
- 1879050788U, // GS_MOV32rm
- 139201070U, // HADDPDrm
- 138545710U, // HADDPDrr
- 139201078U, // HADDPSrm
- 138545718U, // HADDPSrr
- 2622U, // HLT
- 139201090U, // HSUBPDrm
- 138545730U, // HSUBPDrr
- 139201098U, // HSUBPSrm
- 138545738U, // HSUBPSrr
- 268438098U, // IDIV16m
- 134220370U, // IDIV16r
- 402655826U, // IDIV32m
- 134220370U, // IDIV32r
- 536873554U, // IDIV64m
- 134220370U, // IDIV64r
- 671091282U, // IDIV8m
- 134220370U, // IDIV8r
- 268438104U, // ILD_F16m
- 402655832U, // ILD_F32m
- 536873560U, // ILD_F64m
+ 139198725U, // FsANDNPDrm
+ 138543365U, // FsANDNPDrr
+ 139198733U, // FsANDNPSrm
+ 138543373U, // FsANDNPSrr
+ 139198741U, // FsANDPDrm
+ 138543381U, // FsANDPDrr
+ 139198748U, // FsANDPSrm
+ 138543388U, // FsANDPSrr
+ 140773888U, // FsFLD0SD
+ 140773888U, // FsFLD0SS
+ 140380678U, // FsMOVAPDrm
+ 139856390U, // FsMOVAPDrr
+ 140380686U, // FsMOVAPSrm
+ 139856398U, // FsMOVAPSrr
+ 139201046U, // FsORPDrm
+ 138545686U, // FsORPDrr
+ 139201052U, // FsORPSrm
+ 138545692U, // FsORPSrr
+ 139201058U, // FsXORPDrm
+ 138545698U, // FsXORPDrr
+ 139201065U, // FsXORPSrm
+ 138545705U, // FsXORPSrr
+ 1879050800U, // GS_MOV32rm
+ 139201082U, // HADDPDrm
+ 138545722U, // HADDPDrr
+ 139201090U, // HADDPSrm
+ 138545730U, // HADDPSrr
+ 2634U, // HLT
+ 139201102U, // HSUBPDrm
+ 138545742U, // HSUBPDrr
+ 139201110U, // HSUBPSrm
+ 138545750U, // HSUBPSrr
+ 268438110U, // IDIV16m
+ 134220382U, // IDIV16r
+ 402655838U, // IDIV32m
+ 134220382U, // IDIV32r
+ 536873566U, // IDIV64m
+ 134220382U, // IDIV64r
+ 671091294U, // IDIV8m
+ 134220382U, // IDIV8r
+ 268438116U, // ILD_F16m
+ 402655844U, // ILD_F32m
+ 536873572U, // ILD_F64m
0U, // ILD_Fp16m32
0U, // ILD_Fp16m64
0U, // ILD_Fp16m80
@@ -765,67 +766,67 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ILD_Fp64m32
0U, // ILD_Fp64m64
0U, // ILD_Fp64m80
- 268438110U, // IMUL16m
- 134220382U, // IMUL16r
- 138676830U, // IMUL16rm
- 139741790U, // IMUL16rmi
- 139741790U, // IMUL16rmi8
- 138545758U, // IMUL16rr
- 139872862U, // IMUL16rri
- 139872862U, // IMUL16rri8
- 402655838U, // IMUL32m
- 134220382U, // IMUL32r
- 138807902U, // IMUL32rm
- 140003934U, // IMUL32rmi
- 140003934U, // IMUL32rmi8
- 138545758U, // IMUL32rr
- 139872862U, // IMUL32rri
- 139872862U, // IMUL32rri8
- 536873566U, // IMUL64m
- 134220382U, // IMUL64r
- 138938974U, // IMUL64rm
- 140135006U, // IMUL64rmi32
- 140135006U, // IMUL64rmi8
- 138545758U, // IMUL64rr
- 139872862U, // IMUL64rri32
- 139872862U, // IMUL64rri8
- 671091294U, // IMUL8m
- 134220382U, // IMUL8r
- 2660U, // IN16
- 134220392U, // IN16ri
- 2673U, // IN16rr
- 2660U, // IN32
- 134220413U, // IN32ri
- 2695U, // IN32rr
- 2660U, // IN8
- 134220436U, // IN8ri
- 2717U, // IN8rr
- 268438185U, // INC16m
- 134220457U, // INC16r
- 402655913U, // INC32m
- 134220457U, // INC32r
- 268438185U, // INC64_16m
- 134220457U, // INC64_16r
- 402655913U, // INC64_32m
- 134220457U, // INC64_32r
- 536873641U, // INC64m
- 134220457U, // INC64r
- 671091369U, // INC8m
- 134220457U, // INC8r
- 139479726U, // INSERTPSrm
- 138562222U, // INSERTPSrr
- 134220472U, // INT
- 2749U, // INT3
- 2755U, // INVD
- 2760U, // INVEPT
- 2767U, // INVLPG
- 2774U, // INVVPID
- 2782U, // IRET16
- 2782U, // IRET32
- 2782U, // IRET64
- 268437480U, // ISTT_FP16m
- 402655208U, // ISTT_FP32m
- 536872936U, // ISTT_FP64m
+ 268438122U, // IMUL16m
+ 134220394U, // IMUL16r
+ 138676842U, // IMUL16rm
+ 139741802U, // IMUL16rmi
+ 139741802U, // IMUL16rmi8
+ 138545770U, // IMUL16rr
+ 139872874U, // IMUL16rri
+ 139872874U, // IMUL16rri8
+ 402655850U, // IMUL32m
+ 134220394U, // IMUL32r
+ 138807914U, // IMUL32rm
+ 140003946U, // IMUL32rmi
+ 140003946U, // IMUL32rmi8
+ 138545770U, // IMUL32rr
+ 139872874U, // IMUL32rri
+ 139872874U, // IMUL32rri8
+ 536873578U, // IMUL64m
+ 134220394U, // IMUL64r
+ 138938986U, // IMUL64rm
+ 140135018U, // IMUL64rmi32
+ 140135018U, // IMUL64rmi8
+ 138545770U, // IMUL64rr
+ 139872874U, // IMUL64rri32
+ 139872874U, // IMUL64rri8
+ 671091306U, // IMUL8m
+ 134220394U, // IMUL8r
+ 2672U, // IN16
+ 134220404U, // IN16ri
+ 2685U, // IN16rr
+ 2672U, // IN32
+ 134220425U, // IN32ri
+ 2707U, // IN32rr
+ 2672U, // IN8
+ 134220448U, // IN8ri
+ 2729U, // IN8rr
+ 268438197U, // INC16m
+ 134220469U, // INC16r
+ 402655925U, // INC32m
+ 134220469U, // INC32r
+ 268438197U, // INC64_16m
+ 134220469U, // INC64_16r
+ 402655925U, // INC64_32m
+ 134220469U, // INC64_32r
+ 536873653U, // INC64m
+ 134220469U, // INC64r
+ 671091381U, // INC8m
+ 134220469U, // INC8r
+ 139479738U, // INSERTPSrm
+ 138562234U, // INSERTPSrr
+ 134220484U, // INT
+ 2761U, // INT3
+ 2767U, // INVD
+ 2772U, // INVEPT
+ 2779U, // INVLPG
+ 2786U, // INVVPID
+ 2794U, // IRET16
+ 2794U, // IRET32
+ 2794U, // IRET64
+ 268437492U, // ISTT_FP16m
+ 402655220U, // ISTT_FP32m
+ 536872948U, // ISTT_FP64m
0U, // ISTT_Fp16m32
0U, // ISTT_Fp16m64
0U, // ISTT_Fp16m80
@@ -835,11 +836,11 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ISTT_Fp64m32
0U, // ISTT_Fp64m64
0U, // ISTT_Fp64m80
- 268438243U, // IST_F16m
- 402655971U, // IST_F32m
- 268438249U, // IST_FP16m
- 402655977U, // IST_FP32m
- 536873705U, // IST_FP64m
+ 268438255U, // IST_F16m
+ 402655983U, // IST_F32m
+ 268438261U, // IST_FP16m
+ 402655989U, // IST_FP32m
+ 536873717U, // IST_FP64m
0U, // IST_Fp16m32
0U, // IST_Fp16m64
0U, // IST_Fp16m80
@@ -849,135 +850,135 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // IST_Fp64m32
0U, // IST_Fp64m64
0U, // IST_Fp64m80
- 1229850103U, // Int_CMPSDrm
- 1363281399U, // Int_CMPSDrr
- 1234175479U, // Int_CMPSSrm
- 1367475703U, // Int_CMPSSrr
- 140379680U, // Int_COMISDrm
- 139855392U, // Int_COMISDrr
- 140379688U, // Int_COMISSrm
- 139855400U, // Int_COMISSrr
- 140117619U, // Int_CVTDQ2PDrm
- 139855475U, // Int_CVTDQ2PDrr
- 140904061U, // Int_CVTDQ2PSrm
- 139855485U, // Int_CVTDQ2PSrr
- 140379783U, // Int_CVTPD2DQrm
- 139855495U, // Int_CVTPD2DQrr
- 140380912U, // Int_CVTPD2PIrm
- 139856624U, // Int_CVTPD2PIrr
- 140379793U, // Int_CVTPD2PSrm
- 139855505U, // Int_CVTPD2PSrr
- 140118778U, // Int_CVTPI2PDrm
- 139856634U, // Int_CVTPI2PDrr
- 138939140U, // Int_CVTPI2PSrm
- 138545924U, // Int_CVTPI2PSrr
- 140379803U, // Int_CVTPS2DQrm
- 139855515U, // Int_CVTPS2DQrr
- 140510885U, // Int_CVTPS2PDrm
- 139855525U, // Int_CVTPS2PDrr
- 140512014U, // Int_CVTPS2PIrm
- 139856654U, // Int_CVTPS2PIrr
- 140379823U, // Int_CVTSD2SI64rm
- 139855535U, // Int_CVTSD2SI64rr
- 140379823U, // Int_CVTSD2SIrm
- 139855535U, // Int_CVTSD2SIrr
- 139331257U, // Int_CVTSD2SSrm
- 138544825U, // Int_CVTSD2SSrr
- 138938051U, // Int_CVTSI2SD64rm
- 138544835U, // Int_CVTSI2SD64rr
- 138806979U, // Int_CVTSI2SDrm
- 138544835U, // Int_CVTSI2SDrr
- 138938061U, // Int_CVTSI2SS64rm
- 138544845U, // Int_CVTSI2SS64rr
- 138806989U, // Int_CVTSI2SSrm
- 138544845U, // Int_CVTSI2SSrr
- 139462359U, // Int_CVTSS2SDrm
- 138544855U, // Int_CVTSS2SDrr
- 140642017U, // Int_CVTSS2SI64rm
- 139855585U, // Int_CVTSS2SI64rr
- 140642017U, // Int_CVTSS2SIrm
- 139855585U, // Int_CVTSS2SIrr
- 140380952U, // Int_CVTTPD2DQrm
- 139856664U, // Int_CVTTPD2DQrr
- 140380963U, // Int_CVTTPD2PIrm
- 139856675U, // Int_CVTTPD2PIrr
- 140379883U, // Int_CVTTPS2DQrm
- 139855595U, // Int_CVTTPS2DQrr
- 140512046U, // Int_CVTTPS2PIrm
- 139856686U, // Int_CVTTPS2PIrr
- 140379894U, // Int_CVTTSD2SI64rm
- 139855606U, // Int_CVTTSD2SI64rr
- 140379894U, // Int_CVTTSD2SIrm
- 139855606U, // Int_CVTTSD2SIrr
- 140642049U, // Int_CVTTSS2SI64rm
- 139855617U, // Int_CVTTSS2SI64rr
- 140642049U, // Int_CVTTSS2SIrm
- 139855617U, // Int_CVTTSS2SIrr
- 140380985U, // Int_UCOMISDrm
- 139856697U, // Int_UCOMISDrr
- 140380994U, // Int_UCOMISSrm
- 139856706U, // Int_UCOMISSrr
- 1073744715U, // JA
- 1073744715U, // JA8
- 1073744719U, // JAE
- 1073744719U, // JAE8
- 1073744724U, // JB
- 1073744724U, // JB8
- 1073744728U, // JBE
- 1073744728U, // JBE8
- 1073744733U, // JCXZ8
- 1073744739U, // JE
- 1073744739U, // JE8
- 1073744743U, // JG
- 1073744743U, // JG8
- 1073744747U, // JGE
- 1073744747U, // JGE8
- 1073744752U, // JL
- 1073744752U, // JL8
- 1073744756U, // JLE
- 1073744756U, // JLE8
- 1073744761U, // JMP
- 402656121U, // JMP32m
- 134220665U, // JMP32r
- 536873849U, // JMP64m
- 1073744761U, // JMP64pcrel32
- 134220665U, // JMP64r
- 1073744761U, // JMP8
- 1073744766U, // JNE
- 1073744766U, // JNE8
- 1073744771U, // JNO
- 1073744771U, // JNO8
- 1073744776U, // JNP
- 1073744776U, // JNP8
- 1073744781U, // JNS
- 1073744781U, // JNS8
- 1073744786U, // JO
- 1073744786U, // JO8
- 1073744790U, // JP
- 1073744790U, // JP8
- 1073744794U, // JS
- 1073744794U, // JS8
- 2974U, // LAHF
- 139725731U, // LAR16rm
- 139856803U, // LAR16rr
- 139725731U, // LAR32rm
- 139856803U, // LAR32rr
- 139725731U, // LAR64rm
- 139856803U, // LAR64rr
- 272632744U, // LCMPXCHG16
- 406850472U, // LCMPXCHG32
- 2013268919U, // LCMPXCHG64
- 675285928U, // LCMPXCHG8
- 402656199U, // LCMPXCHG8B
- 140905432U, // LDDQUrm
- 402656223U, // LDMXCSR
- 141036520U, // LDS16rm
- 141036520U, // LDS32rm
- 3053U, // LD_F0
- 3058U, // LD_F1
- 805309431U, // LD_F32m
- 939527159U, // LD_F64m
- 2147486711U, // LD_F80m
+ 1229850115U, // Int_CMPSDrm
+ 1363281411U, // Int_CMPSDrr
+ 1234175491U, // Int_CMPSSrm
+ 1367475715U, // Int_CMPSSrr
+ 140379692U, // Int_COMISDrm
+ 139855404U, // Int_COMISDrr
+ 140379700U, // Int_COMISSrm
+ 139855412U, // Int_COMISSrr
+ 140117631U, // Int_CVTDQ2PDrm
+ 139855487U, // Int_CVTDQ2PDrr
+ 140904073U, // Int_CVTDQ2PSrm
+ 139855497U, // Int_CVTDQ2PSrr
+ 140379795U, // Int_CVTPD2DQrm
+ 139855507U, // Int_CVTPD2DQrr
+ 140380924U, // Int_CVTPD2PIrm
+ 139856636U, // Int_CVTPD2PIrr
+ 140379805U, // Int_CVTPD2PSrm
+ 139855517U, // Int_CVTPD2PSrr
+ 140118790U, // Int_CVTPI2PDrm
+ 139856646U, // Int_CVTPI2PDrr
+ 138939152U, // Int_CVTPI2PSrm
+ 138545936U, // Int_CVTPI2PSrr
+ 140379815U, // Int_CVTPS2DQrm
+ 139855527U, // Int_CVTPS2DQrr
+ 140510897U, // Int_CVTPS2PDrm
+ 139855537U, // Int_CVTPS2PDrr
+ 140512026U, // Int_CVTPS2PIrm
+ 139856666U, // Int_CVTPS2PIrr
+ 140379835U, // Int_CVTSD2SI64rm
+ 139855547U, // Int_CVTSD2SI64rr
+ 140379835U, // Int_CVTSD2SIrm
+ 139855547U, // Int_CVTSD2SIrr
+ 139331269U, // Int_CVTSD2SSrm
+ 138544837U, // Int_CVTSD2SSrr
+ 138938063U, // Int_CVTSI2SD64rm
+ 138544847U, // Int_CVTSI2SD64rr
+ 138806991U, // Int_CVTSI2SDrm
+ 138544847U, // Int_CVTSI2SDrr
+ 138938073U, // Int_CVTSI2SS64rm
+ 138544857U, // Int_CVTSI2SS64rr
+ 138807001U, // Int_CVTSI2SSrm
+ 138544857U, // Int_CVTSI2SSrr
+ 139462371U, // Int_CVTSS2SDrm
+ 138544867U, // Int_CVTSS2SDrr
+ 140642029U, // Int_CVTSS2SI64rm
+ 139855597U, // Int_CVTSS2SI64rr
+ 140642029U, // Int_CVTSS2SIrm
+ 139855597U, // Int_CVTSS2SIrr
+ 140380964U, // Int_CVTTPD2DQrm
+ 139856676U, // Int_CVTTPD2DQrr
+ 140380975U, // Int_CVTTPD2PIrm
+ 139856687U, // Int_CVTTPD2PIrr
+ 140379895U, // Int_CVTTPS2DQrm
+ 139855607U, // Int_CVTTPS2DQrr
+ 140512058U, // Int_CVTTPS2PIrm
+ 139856698U, // Int_CVTTPS2PIrr
+ 140379906U, // Int_CVTTSD2SI64rm
+ 139855618U, // Int_CVTTSD2SI64rr
+ 140379906U, // Int_CVTTSD2SIrm
+ 139855618U, // Int_CVTTSD2SIrr
+ 140642061U, // Int_CVTTSS2SI64rm
+ 139855629U, // Int_CVTTSS2SI64rr
+ 140642061U, // Int_CVTTSS2SIrm
+ 139855629U, // Int_CVTTSS2SIrr
+ 140380997U, // Int_UCOMISDrm
+ 139856709U, // Int_UCOMISDrr
+ 140381006U, // Int_UCOMISSrm
+ 139856718U, // Int_UCOMISSrr
+ 1073744727U, // JA
+ 1073744727U, // JA8
+ 1073744731U, // JAE
+ 1073744731U, // JAE8
+ 1073744736U, // JB
+ 1073744736U, // JB8
+ 1073744740U, // JBE
+ 1073744740U, // JBE8
+ 1073744745U, // JCXZ8
+ 1073744751U, // JE
+ 1073744751U, // JE8
+ 1073744755U, // JG
+ 1073744755U, // JG8
+ 1073744759U, // JGE
+ 1073744759U, // JGE8
+ 1073744764U, // JL
+ 1073744764U, // JL8
+ 1073744768U, // JLE
+ 1073744768U, // JLE8
+ 1073744773U, // JMP
+ 402656133U, // JMP32m
+ 134220677U, // JMP32r
+ 536873861U, // JMP64m
+ 1073744773U, // JMP64pcrel32
+ 134220677U, // JMP64r
+ 1073744773U, // JMP8
+ 1073744778U, // JNE
+ 1073744778U, // JNE8
+ 1073744783U, // JNO
+ 1073744783U, // JNO8
+ 1073744788U, // JNP
+ 1073744788U, // JNP8
+ 1073744793U, // JNS
+ 1073744793U, // JNS8
+ 1073744798U, // JO
+ 1073744798U, // JO8
+ 1073744802U, // JP
+ 1073744802U, // JP8
+ 1073744806U, // JS
+ 1073744806U, // JS8
+ 2986U, // LAHF
+ 139725743U, // LAR16rm
+ 139856815U, // LAR16rr
+ 139725743U, // LAR32rm
+ 139856815U, // LAR32rr
+ 139725743U, // LAR64rm
+ 139856815U, // LAR64rr
+ 272632756U, // LCMPXCHG16
+ 406850484U, // LCMPXCHG32
+ 2013268931U, // LCMPXCHG64
+ 675285940U, // LCMPXCHG8
+ 536873939U, // LCMPXCHG8B
+ 140905444U, // LDDQUrm
+ 402656235U, // LDMXCSR
+ 141036532U, // LDS16rm
+ 141036532U, // LDS32rm
+ 3065U, // LD_F0
+ 3070U, // LD_F1
+ 805309443U, // LD_F32m
+ 939527171U, // LD_F64m
+ 2147486723U, // LD_F80m
0U, // LD_Fp032
0U, // LD_Fp064
0U, // LD_Fp080
@@ -990,461 +991,463 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // LD_Fp64m
0U, // LD_Fp64m80
0U, // LD_Fp80m
- 134220791U, // LD_Frr
- 141167612U, // LEA16r
- 141167612U, // LEA32r
- 141298684U, // LEA64_32r
- 141429756U, // LEA64r
- 3073U, // LEAVE
- 3073U, // LEAVE64
- 141036551U, // LES16rm
- 141036551U, // LES32rm
- 3084U, // LFENCE
- 141036563U, // LFS16rm
- 141036563U, // LFS32rm
- 141036563U, // LFS64rm
- 1744833560U, // LGDTm
- 141036574U, // LGS16rm
- 141036574U, // LGS32rm
- 141036574U, // LGS64rm
- 1744833571U, // LIDTm
- 268438569U, // LLDT16m
- 134220841U, // LLDT16r
- 268438575U, // LMSW16m
- 134220847U, // LMSW16r
- 272632885U, // LOCK_ADD16mi
- 272632885U, // LOCK_ADD16mi8
- 272632885U, // LOCK_ADD16mr
- 406850613U, // LOCK_ADD32mi
- 406850613U, // LOCK_ADD32mi8
- 406850613U, // LOCK_ADD32mr
- 541068341U, // LOCK_ADD64mi32
- 541068341U, // LOCK_ADD64mi8
- 541068341U, // LOCK_ADD64mr
- 675286069U, // LOCK_ADD8mi
- 675286069U, // LOCK_ADD8mr
- 268438592U, // LOCK_DEC16m
- 402656320U, // LOCK_DEC32m
- 536874048U, // LOCK_DEC64m
- 671091776U, // LOCK_DEC8m
- 268438603U, // LOCK_INC16m
- 402656331U, // LOCK_INC32m
- 536874059U, // LOCK_INC64m
- 671091787U, // LOCK_INC8m
- 272632918U, // LOCK_SUB16mi
- 272632918U, // LOCK_SUB16mi8
- 272632918U, // LOCK_SUB16mr
- 406850646U, // LOCK_SUB32mi
- 406850646U, // LOCK_SUB32mi8
- 406850646U, // LOCK_SUB32mr
- 541068374U, // LOCK_SUB64mi32
- 541068374U, // LOCK_SUB64mi8
- 541068374U, // LOCK_SUB64mr
- 675286102U, // LOCK_SUB8mi
- 675286102U, // LOCK_SUB8mr
- 3169U, // LODSB
- 3175U, // LODSD
- 3181U, // LODSQ
- 3187U, // LODSW
- 1073745017U, // LOOP
- 1073745023U, // LOOPE
- 1073745030U, // LOOPNE
- 3214U, // LRET
- 134220947U, // LRETI
- 139725977U, // LSL16rm
- 139857049U, // LSL16rr
- 139988121U, // LSL32rm
- 139857049U, // LSL32rr
- 140119193U, // LSL64rm
- 139857049U, // LSL64rr
- 141036702U, // LSS16rm
- 141036702U, // LSS32rm
- 141036702U, // LSS64rm
- 3235U, // LTRm
- 3235U, // LTRr
- 2281704616U, // LXADD16
- 2415922344U, // LXADD32
- 1656753320U, // LXADD64
- 2550140072U, // LXADD8
- 139857076U, // MASKMOVDQU
- 139857076U, // MASKMOVDQU64
- 139201728U, // MAXPDrm
- 139201728U, // MAXPDrm_Int
- 138546368U, // MAXPDrr
- 138546368U, // MAXPDrr_Int
- 139201735U, // MAXPSrm
- 139201735U, // MAXPSrm_Int
- 138546375U, // MAXPSrr
- 138546375U, // MAXPSrr_Int
- 139332814U, // MAXSDrm
- 139332814U, // MAXSDrm_Int
- 138546382U, // MAXSDrr
- 138546382U, // MAXSDrr_Int
- 139463893U, // MAXSSrm
- 139463893U, // MAXSSrm_Int
- 138546389U, // MAXSSrr
- 138546389U, // MAXSSrr_Int
- 3292U, // MFENCE
- 139201763U, // MINPDrm
- 139201763U, // MINPDrm_Int
- 138546403U, // MINPDrr
- 138546403U, // MINPDrr_Int
- 139201770U, // MINPSrm
- 139201770U, // MINPSrm_Int
- 138546410U, // MINPSrr
- 138546410U, // MINPSrr_Int
- 139332849U, // MINSDrm
- 139332849U, // MINSDrm_Int
- 138546417U, // MINSDrr
- 138546417U, // MINSDrr_Int
- 139463928U, // MINSSrm
- 139463928U, // MINSSrm_Int
- 138546424U, // MINSSrr
- 138546424U, // MINSSrr_Int
- 140380912U, // MMX_CVTPD2PIrm
- 139856624U, // MMX_CVTPD2PIrr
- 140118778U, // MMX_CVTPI2PDrm
- 139856634U, // MMX_CVTPI2PDrr
- 140118788U, // MMX_CVTPI2PSrm
- 139856644U, // MMX_CVTPI2PSrr
- 140512014U, // MMX_CVTPS2PIrm
- 139856654U, // MMX_CVTPS2PIrr
- 140380963U, // MMX_CVTTPD2PIrm
- 139856675U, // MMX_CVTTPD2PIrr
- 140512046U, // MMX_CVTTPS2PIrm
- 139856686U, // MMX_CVTTPS2PIrr
- 3327U, // MMX_EMMS
- 3332U, // MMX_FEMMS
- 139857162U, // MMX_MASKMOVQ
- 139857162U, // MMX_MASKMOVQ64
- 139857172U, // MMX_MOVD64from64rr
- 139857172U, // MMX_MOVD64grr
- 406850836U, // MMX_MOVD64mr
- 139988244U, // MMX_MOVD64rm
- 139857172U, // MMX_MOVD64rr
- 139857172U, // MMX_MOVD64rrv164
- 139857172U, // MMX_MOVD64to64rr
- 139857178U, // MMX_MOVDQ2Qrr
- 541068579U, // MMX_MOVNTQmr
- 139857195U, // MMX_MOVQ2DQrr
- 139857195U, // MMX_MOVQ2FR64rr
- 541068596U, // MMX_MOVQ64gmr
- 541068596U, // MMX_MOVQ64mr
- 140119348U, // MMX_MOVQ64rm
- 139857204U, // MMX_MOVQ64rr
- 139988244U, // MMX_MOVZDI2PDIrm
- 139857172U, // MMX_MOVZDI2PDIrr
- 138939706U, // MMX_PACKSSDWrm
- 138546490U, // MMX_PACKSSDWrr
- 138939716U, // MMX_PACKSSWBrm
- 138546500U, // MMX_PACKSSWBrr
- 138939726U, // MMX_PACKUSWBrm
- 138546510U, // MMX_PACKUSWBrr
- 138939736U, // MMX_PADDBrm
- 138546520U, // MMX_PADDBrr
- 138939743U, // MMX_PADDDrm
- 138546527U, // MMX_PADDDrr
- 138939750U, // MMX_PADDQrm
- 138546534U, // MMX_PADDQrr
- 138939757U, // MMX_PADDSBrm
- 138546541U, // MMX_PADDSBrr
- 138939765U, // MMX_PADDSWrm
- 138546549U, // MMX_PADDSWrr
- 138939773U, // MMX_PADDUSBrm
- 138546557U, // MMX_PADDUSBrr
- 138939782U, // MMX_PADDUSWrm
- 138546566U, // MMX_PADDUSWrr
- 138939791U, // MMX_PADDWrm
- 138546575U, // MMX_PADDWrr
- 138939798U, // MMX_PANDNrm
- 138546582U, // MMX_PANDNrr
- 138939805U, // MMX_PANDrm
- 138546589U, // MMX_PANDrr
- 138939811U, // MMX_PAVGBrm
- 138546595U, // MMX_PAVGBrr
- 138939818U, // MMX_PAVGWrm
- 138546602U, // MMX_PAVGWrr
- 138939825U, // MMX_PCMPEQBrm
- 138546609U, // MMX_PCMPEQBrr
- 138939834U, // MMX_PCMPEQDrm
- 138546618U, // MMX_PCMPEQDrr
- 138939843U, // MMX_PCMPEQWrm
- 138546627U, // MMX_PCMPEQWrr
- 138939852U, // MMX_PCMPGTBrm
- 138546636U, // MMX_PCMPGTBrr
- 138939861U, // MMX_PCMPGTDrm
- 138546645U, // MMX_PCMPGTDrr
- 138939870U, // MMX_PCMPGTWrm
- 138546654U, // MMX_PCMPGTWrr
- 139873767U, // MMX_PEXTRWri
- 138694127U, // MMX_PINSRWrmi
- 138563055U, // MMX_PINSRWrri
- 138939895U, // MMX_PMADDWDrm
- 138546679U, // MMX_PMADDWDrr
- 138939904U, // MMX_PMAXSWrm
- 138546688U, // MMX_PMAXSWrr
- 138939912U, // MMX_PMAXUBrm
- 138546696U, // MMX_PMAXUBrr
- 138939920U, // MMX_PMINSWrm
- 138546704U, // MMX_PMINSWrr
- 138939928U, // MMX_PMINUBrm
- 138546712U, // MMX_PMINUBrr
- 139857440U, // MMX_PMOVMSKBrr
- 138939946U, // MMX_PMULHUWrm
- 138546730U, // MMX_PMULHUWrr
- 138939955U, // MMX_PMULHWrm
- 138546739U, // MMX_PMULHWrr
- 138939963U, // MMX_PMULLWrm
- 138546747U, // MMX_PMULLWrr
- 138939971U, // MMX_PMULUDQrm
- 138546755U, // MMX_PMULUDQrr
- 138939980U, // MMX_PORrm
- 138546764U, // MMX_PORrr
- 138939985U, // MMX_PSADBWrm
- 138546769U, // MMX_PSADBWrr
- 140136025U, // MMX_PSHUFWmi
- 139873881U, // MMX_PSHUFWri
- 138546785U, // MMX_PSLLDri
- 138940001U, // MMX_PSLLDrm
- 138546785U, // MMX_PSLLDrr
- 138546792U, // MMX_PSLLQri
- 138940008U, // MMX_PSLLQrm
- 138546792U, // MMX_PSLLQrr
- 138546799U, // MMX_PSLLWri
- 138940015U, // MMX_PSLLWrm
- 138546799U, // MMX_PSLLWrr
- 138546806U, // MMX_PSRADri
- 138940022U, // MMX_PSRADrm
- 138546806U, // MMX_PSRADrr
- 138546813U, // MMX_PSRAWri
- 138940029U, // MMX_PSRAWrm
- 138546813U, // MMX_PSRAWrr
- 138546820U, // MMX_PSRLDri
- 138940036U, // MMX_PSRLDrm
- 138546820U, // MMX_PSRLDrr
- 138546827U, // MMX_PSRLQri
- 138940043U, // MMX_PSRLQrm
- 138546827U, // MMX_PSRLQrr
- 138546834U, // MMX_PSRLWri
- 138940050U, // MMX_PSRLWrm
- 138546834U, // MMX_PSRLWrr
- 138940057U, // MMX_PSUBBrm
- 138546841U, // MMX_PSUBBrr
- 138940064U, // MMX_PSUBDrm
- 138546848U, // MMX_PSUBDrr
- 138940071U, // MMX_PSUBQrm
- 138546855U, // MMX_PSUBQrr
- 138940078U, // MMX_PSUBSBrm
- 138546862U, // MMX_PSUBSBrr
- 138940086U, // MMX_PSUBSWrm
- 138546870U, // MMX_PSUBSWrr
- 138940094U, // MMX_PSUBUSBrm
- 138546878U, // MMX_PSUBUSBrr
- 138940103U, // MMX_PSUBUSWrm
- 138546887U, // MMX_PSUBUSWrr
- 138940112U, // MMX_PSUBWrm
- 138546896U, // MMX_PSUBWrr
- 138940119U, // MMX_PUNPCKHBWrm
- 138546903U, // MMX_PUNPCKHBWrr
- 138940130U, // MMX_PUNPCKHDQrm
- 138546914U, // MMX_PUNPCKHDQrr
- 138940141U, // MMX_PUNPCKHWDrm
- 138546925U, // MMX_PUNPCKHWDrr
- 138940152U, // MMX_PUNPCKLBWrm
- 138546936U, // MMX_PUNPCKLBWrr
- 138940163U, // MMX_PUNPCKLDQrm
- 138546947U, // MMX_PUNPCKLDQrr
- 138940174U, // MMX_PUNPCKLWDrm
- 138546958U, // MMX_PUNPCKLWDrr
- 138938868U, // MMX_PXORrm
- 138545652U, // MMX_PXORrr
- 140773876U, // MMX_V_SET0
- 140774842U, // MMX_V_SETALLONES
- 3865U, // MONITOR
- 1124077345U, // MOV16ao16
- 272633633U, // MOV16mi
- 272633633U, // MOV16mr
- 272633633U, // MOV16ms
- 1073745702U, // MOV16o16a
- 139857697U, // MOV16ri
- 139726625U, // MOV16rm
- 139857697U, // MOV16rr
- 139857697U, // MOV16rr_REV
- 139857697U, // MOV16rs
- 139726625U, // MOV16sm
- 139857697U, // MOV16sr
- 1128271649U, // MOV32ao32
- 139857697U, // MOV32cr
- 139857697U, // MOV32dr
- 406851361U, // MOV32mi
- 406851361U, // MOV32mr
- 1073745712U, // MOV32o32a
- 140775227U, // MOV32r0
- 139857697U, // MOV32rc
- 139857697U, // MOV32rd
- 139857697U, // MOV32ri
- 139988769U, // MOV32rm
- 139857697U, // MOV32rr
- 139857697U, // MOV32rr_REV
- 2684358464U, // MOV64FSrm
- 2684358474U, // MOV64GSrm
- 1132465953U, // MOV64ao64
- 1132465953U, // MOV64ao8
- 139857697U, // MOV64cr
- 139857697U, // MOV64dr
- 541069089U, // MOV64mi32
- 541069089U, // MOV64mr
- 541069089U, // MOV64ms
- 1073745748U, // MOV64o64a
- 1073745748U, // MOV64o8a
- 139857697U, // MOV64rc
- 139857697U, // MOV64rd
- 139857759U, // MOV64ri
- 139857697U, // MOV64ri32
+ 134220803U, // LD_Frr
+ 141167624U, // LEA16r
+ 141167624U, // LEA32r
+ 141298696U, // LEA64_32r
+ 141429768U, // LEA64r
+ 3085U, // LEAVE
+ 3085U, // LEAVE64
+ 141036563U, // LES16rm
+ 141036563U, // LES32rm
+ 3096U, // LFENCE
+ 141036575U, // LFS16rm
+ 141036575U, // LFS32rm
+ 141036575U, // LFS64rm
+ 1744833572U, // LGDTm
+ 141036586U, // LGS16rm
+ 141036586U, // LGS32rm
+ 141036586U, // LGS64rm
+ 1744833583U, // LIDTm
+ 268438581U, // LLDT16m
+ 134220853U, // LLDT16r
+ 268438587U, // LMSW16m
+ 134220859U, // LMSW16r
+ 272632897U, // LOCK_ADD16mi
+ 272632897U, // LOCK_ADD16mi8
+ 272632897U, // LOCK_ADD16mr
+ 406850625U, // LOCK_ADD32mi
+ 406850625U, // LOCK_ADD32mi8
+ 406850625U, // LOCK_ADD32mr
+ 541068353U, // LOCK_ADD64mi32
+ 541068353U, // LOCK_ADD64mi8
+ 541068353U, // LOCK_ADD64mr
+ 675286081U, // LOCK_ADD8mi
+ 675286081U, // LOCK_ADD8mr
+ 268438604U, // LOCK_DEC16m
+ 402656332U, // LOCK_DEC32m
+ 536874060U, // LOCK_DEC64m
+ 671091788U, // LOCK_DEC8m
+ 268438615U, // LOCK_INC16m
+ 402656343U, // LOCK_INC32m
+ 536874071U, // LOCK_INC64m
+ 671091799U, // LOCK_INC8m
+ 272632930U, // LOCK_SUB16mi
+ 272632930U, // LOCK_SUB16mi8
+ 272632930U, // LOCK_SUB16mr
+ 406850658U, // LOCK_SUB32mi
+ 406850658U, // LOCK_SUB32mi8
+ 406850658U, // LOCK_SUB32mr
+ 541068386U, // LOCK_SUB64mi32
+ 541068386U, // LOCK_SUB64mi8
+ 541068386U, // LOCK_SUB64mr
+ 675286114U, // LOCK_SUB8mi
+ 675286114U, // LOCK_SUB8mr
+ 3181U, // LODSB
+ 3187U, // LODSD
+ 3193U, // LODSQ
+ 3199U, // LODSW
+ 1073745029U, // LOOP
+ 1073745035U, // LOOPE
+ 1073745042U, // LOOPNE
+ 3226U, // LRET
+ 134220959U, // LRETI
+ 139725989U, // LSL16rm
+ 139857061U, // LSL16rr
+ 139988133U, // LSL32rm
+ 139857061U, // LSL32rr
+ 140119205U, // LSL64rm
+ 139857061U, // LSL64rr
+ 141036714U, // LSS16rm
+ 141036714U, // LSS32rm
+ 141036714U, // LSS64rm
+ 3247U, // LTRm
+ 3247U, // LTRr
+ 2281704628U, // LXADD16
+ 2415922356U, // LXADD32
+ 1656753332U, // LXADD64
+ 2550140084U, // LXADD8
+ 139857088U, // MASKMOVDQU
+ 139857088U, // MASKMOVDQU64
+ 139201740U, // MAXPDrm
+ 139201740U, // MAXPDrm_Int
+ 138546380U, // MAXPDrr
+ 138546380U, // MAXPDrr_Int
+ 139201747U, // MAXPSrm
+ 139201747U, // MAXPSrm_Int
+ 138546387U, // MAXPSrr
+ 138546387U, // MAXPSrr_Int
+ 139332826U, // MAXSDrm
+ 139332826U, // MAXSDrm_Int
+ 138546394U, // MAXSDrr
+ 138546394U, // MAXSDrr_Int
+ 139463905U, // MAXSSrm
+ 139463905U, // MAXSSrm_Int
+ 138546401U, // MAXSSrr
+ 138546401U, // MAXSSrr_Int
+ 3304U, // MFENCE
+ 139201775U, // MINPDrm
+ 139201775U, // MINPDrm_Int
+ 138546415U, // MINPDrr
+ 138546415U, // MINPDrr_Int
+ 139201782U, // MINPSrm
+ 139201782U, // MINPSrm_Int
+ 138546422U, // MINPSrr
+ 138546422U, // MINPSrr_Int
+ 139332861U, // MINSDrm
+ 139332861U, // MINSDrm_Int
+ 138546429U, // MINSDrr
+ 138546429U, // MINSDrr_Int
+ 139463940U, // MINSSrm
+ 139463940U, // MINSSrm_Int
+ 138546436U, // MINSSrr
+ 138546436U, // MINSSrr_Int
+ 140380924U, // MMX_CVTPD2PIrm
+ 139856636U, // MMX_CVTPD2PIrr
+ 140118790U, // MMX_CVTPI2PDrm
+ 139856646U, // MMX_CVTPI2PDrr
+ 140118800U, // MMX_CVTPI2PSrm
+ 139856656U, // MMX_CVTPI2PSrr
+ 140512026U, // MMX_CVTPS2PIrm
+ 139856666U, // MMX_CVTPS2PIrr
+ 140380975U, // MMX_CVTTPD2PIrm
+ 139856687U, // MMX_CVTTPD2PIrr
+ 140512058U, // MMX_CVTTPS2PIrm
+ 139856698U, // MMX_CVTTPS2PIrr
+ 3339U, // MMX_EMMS
+ 3344U, // MMX_FEMMS
+ 139857174U, // MMX_MASKMOVQ
+ 139857174U, // MMX_MASKMOVQ64
+ 139857184U, // MMX_MOVD64from64rr
+ 139857184U, // MMX_MOVD64grr
+ 406850848U, // MMX_MOVD64mr
+ 139988256U, // MMX_MOVD64rm
+ 139857184U, // MMX_MOVD64rr
+ 139857184U, // MMX_MOVD64rrv164
+ 139857184U, // MMX_MOVD64to64rr
+ 139857190U, // MMX_MOVDQ2Qrr
+ 541068591U, // MMX_MOVNTQmr
+ 139857207U, // MMX_MOVQ2DQrr
+ 139857207U, // MMX_MOVQ2FR64rr
+ 541068608U, // MMX_MOVQ64gmr
+ 541068608U, // MMX_MOVQ64mr
+ 140119360U, // MMX_MOVQ64rm
+ 139857216U, // MMX_MOVQ64rr
+ 139988256U, // MMX_MOVZDI2PDIrm
+ 139857184U, // MMX_MOVZDI2PDIrr
+ 138939718U, // MMX_PACKSSDWrm
+ 138546502U, // MMX_PACKSSDWrr
+ 138939728U, // MMX_PACKSSWBrm
+ 138546512U, // MMX_PACKSSWBrr
+ 138939738U, // MMX_PACKUSWBrm
+ 138546522U, // MMX_PACKUSWBrr
+ 138939748U, // MMX_PADDBrm
+ 138546532U, // MMX_PADDBrr
+ 138939755U, // MMX_PADDDrm
+ 138546539U, // MMX_PADDDrr
+ 138939762U, // MMX_PADDQrm
+ 138546546U, // MMX_PADDQrr
+ 138939769U, // MMX_PADDSBrm
+ 138546553U, // MMX_PADDSBrr
+ 138939777U, // MMX_PADDSWrm
+ 138546561U, // MMX_PADDSWrr
+ 138939785U, // MMX_PADDUSBrm
+ 138546569U, // MMX_PADDUSBrr
+ 138939794U, // MMX_PADDUSWrm
+ 138546578U, // MMX_PADDUSWrr
+ 138939803U, // MMX_PADDWrm
+ 138546587U, // MMX_PADDWrr
+ 138939810U, // MMX_PANDNrm
+ 138546594U, // MMX_PANDNrr
+ 138939817U, // MMX_PANDrm
+ 138546601U, // MMX_PANDrr
+ 138939823U, // MMX_PAVGBrm
+ 138546607U, // MMX_PAVGBrr
+ 138939830U, // MMX_PAVGWrm
+ 138546614U, // MMX_PAVGWrr
+ 138939837U, // MMX_PCMPEQBrm
+ 138546621U, // MMX_PCMPEQBrr
+ 138939846U, // MMX_PCMPEQDrm
+ 138546630U, // MMX_PCMPEQDrr
+ 138939855U, // MMX_PCMPEQWrm
+ 138546639U, // MMX_PCMPEQWrr
+ 138939864U, // MMX_PCMPGTBrm
+ 138546648U, // MMX_PCMPGTBrr
+ 138939873U, // MMX_PCMPGTDrm
+ 138546657U, // MMX_PCMPGTDrr
+ 138939882U, // MMX_PCMPGTWrm
+ 138546666U, // MMX_PCMPGTWrr
+ 139873779U, // MMX_PEXTRWri
+ 138694139U, // MMX_PINSRWrmi
+ 138563067U, // MMX_PINSRWrri
+ 138939907U, // MMX_PMADDWDrm
+ 138546691U, // MMX_PMADDWDrr
+ 138939916U, // MMX_PMAXSWrm
+ 138546700U, // MMX_PMAXSWrr
+ 138939924U, // MMX_PMAXUBrm
+ 138546708U, // MMX_PMAXUBrr
+ 138939932U, // MMX_PMINSWrm
+ 138546716U, // MMX_PMINSWrr
+ 138939940U, // MMX_PMINUBrm
+ 138546724U, // MMX_PMINUBrr
+ 139857452U, // MMX_PMOVMSKBrr
+ 138939958U, // MMX_PMULHUWrm
+ 138546742U, // MMX_PMULHUWrr
+ 138939967U, // MMX_PMULHWrm
+ 138546751U, // MMX_PMULHWrr
+ 138939975U, // MMX_PMULLWrm
+ 138546759U, // MMX_PMULLWrr
+ 138939983U, // MMX_PMULUDQrm
+ 138546767U, // MMX_PMULUDQrr
+ 138939992U, // MMX_PORrm
+ 138546776U, // MMX_PORrr
+ 138939997U, // MMX_PSADBWrm
+ 138546781U, // MMX_PSADBWrr
+ 140136037U, // MMX_PSHUFWmi
+ 139873893U, // MMX_PSHUFWri
+ 138546797U, // MMX_PSLLDri
+ 138940013U, // MMX_PSLLDrm
+ 138546797U, // MMX_PSLLDrr
+ 138546804U, // MMX_PSLLQri
+ 138940020U, // MMX_PSLLQrm
+ 138546804U, // MMX_PSLLQrr
+ 138546811U, // MMX_PSLLWri
+ 138940027U, // MMX_PSLLWrm
+ 138546811U, // MMX_PSLLWrr
+ 138546818U, // MMX_PSRADri
+ 138940034U, // MMX_PSRADrm
+ 138546818U, // MMX_PSRADrr
+ 138546825U, // MMX_PSRAWri
+ 138940041U, // MMX_PSRAWrm
+ 138546825U, // MMX_PSRAWrr
+ 138546832U, // MMX_PSRLDri
+ 138940048U, // MMX_PSRLDrm
+ 138546832U, // MMX_PSRLDrr
+ 138546839U, // MMX_PSRLQri
+ 138940055U, // MMX_PSRLQrm
+ 138546839U, // MMX_PSRLQrr
+ 138546846U, // MMX_PSRLWri
+ 138940062U, // MMX_PSRLWrm
+ 138546846U, // MMX_PSRLWrr
+ 138940069U, // MMX_PSUBBrm
+ 138546853U, // MMX_PSUBBrr
+ 138940076U, // MMX_PSUBDrm
+ 138546860U, // MMX_PSUBDrr
+ 138940083U, // MMX_PSUBQrm
+ 138546867U, // MMX_PSUBQrr
+ 138940090U, // MMX_PSUBSBrm
+ 138546874U, // MMX_PSUBSBrr
+ 138940098U, // MMX_PSUBSWrm
+ 138546882U, // MMX_PSUBSWrr
+ 138940106U, // MMX_PSUBUSBrm
+ 138546890U, // MMX_PSUBUSBrr
+ 138940115U, // MMX_PSUBUSWrm
+ 138546899U, // MMX_PSUBUSWrr
+ 138940124U, // MMX_PSUBWrm
+ 138546908U, // MMX_PSUBWrr
+ 138940131U, // MMX_PUNPCKHBWrm
+ 138546915U, // MMX_PUNPCKHBWrr
+ 138940142U, // MMX_PUNPCKHDQrm
+ 138546926U, // MMX_PUNPCKHDQrr
+ 138940153U, // MMX_PUNPCKHWDrm
+ 138546937U, // MMX_PUNPCKHWDrr
+ 138940164U, // MMX_PUNPCKLBWrm
+ 138546948U, // MMX_PUNPCKLBWrr
+ 138940175U, // MMX_PUNPCKLDQrm
+ 138546959U, // MMX_PUNPCKLDQrr
+ 138940186U, // MMX_PUNPCKLWDrm
+ 138546970U, // MMX_PUNPCKLWDrr
+ 138938880U, // MMX_PXORrm
+ 138545664U, // MMX_PXORrr
+ 140773888U, // MMX_V_SET0
+ 140774854U, // MMX_V_SETALLONES
+ 3877U, // MONITOR
+ 1124077357U, // MOV16ao16
+ 272633645U, // MOV16mi
+ 272633645U, // MOV16mr
+ 272633645U, // MOV16ms
+ 1073745714U, // MOV16o16a
+ 0U, // MOV16r0
+ 139857709U, // MOV16ri
+ 139726637U, // MOV16rm
+ 139857709U, // MOV16rr
+ 139857709U, // MOV16rr_REV
+ 139857709U, // MOV16rs
+ 139726637U, // MOV16sm
+ 139857709U, // MOV16sr
+ 1128271661U, // MOV32ao32
+ 139857709U, // MOV32cr
+ 139857709U, // MOV32dr
+ 406851373U, // MOV32mi
+ 406851373U, // MOV32mr
+ 1073745724U, // MOV32o32a
+ 140775239U, // MOV32r0
+ 139857709U, // MOV32rc
+ 139857709U, // MOV32rd
+ 139857709U, // MOV32ri
+ 139988781U, // MOV32rm
+ 139857709U, // MOV32rr
+ 139857709U, // MOV32rr_REV
+ 2684358476U, // MOV64FSrm
+ 2684358486U, // MOV64GSrm
+ 1132465965U, // MOV64ao64
+ 1132465965U, // MOV64ao8
+ 139857709U, // MOV64cr
+ 139857709U, // MOV64dr
+ 541069101U, // MOV64mi32
+ 541069101U, // MOV64mr
+ 541069101U, // MOV64ms
+ 1073745760U, // MOV64o64a
+ 1073745760U, // MOV64o8a
+ 0U, // MOV64r0
+ 139857709U, // MOV64rc
+ 139857709U, // MOV64rd
+ 139857771U, // MOV64ri
+ 139857709U, // MOV64ri32
0U, // MOV64ri64i32
- 140119841U, // MOV64rm
- 139857697U, // MOV64rr
- 139857697U, // MOV64rr_REV
- 139857697U, // MOV64rs
- 140119841U, // MOV64sm
- 139857697U, // MOV64sr
- 139857204U, // MOV64toPQIrr
- 140119348U, // MOV64toSDrm
- 139857204U, // MOV64toSDrr
- 1136660257U, // MOV8ao8
- 675286817U, // MOV8mi
- 675286817U, // MOV8mr
- 675335969U, // MOV8mr_NOREX
- 1073745767U, // MOV8o8a
- 140775227U, // MOV8r0
- 139857697U, // MOV8ri
- 140250913U, // MOV8rm
- 140300065U, // MOV8rm_NOREX
- 139857697U, // MOV8rr
- 139906849U, // MOV8rr_NOREX
- 139857697U, // MOV8rr_REV
- 2818574842U, // MOVAPDmr
- 140380666U, // MOVAPDrm
- 139856378U, // MOVAPDrr
- 2818574850U, // MOVAPSmr
- 140380674U, // MOVAPSrm
- 139856386U, // MOVAPSrr
- 140513137U, // MOVDDUPrm
- 139857777U, // MOVDDUPrr
- 139988244U, // MOVDI2PDIrm
- 139857172U, // MOVDI2PDIrr
- 139988244U, // MOVDI2SSrm
- 139857172U, // MOVDI2SSrr
- 1480593274U, // MOVDQAmr
- 140906362U, // MOVDQArm
- 139857786U, // MOVDQArr
- 1480593282U, // MOVDQUmr
- 1480593282U, // MOVDQUmr_Int
- 140906370U, // MOVDQUrm
- 140906370U, // MOVDQUrm_Int
- 138547082U, // MOVHLPSrr
- 943722387U, // MOVHPDmr
- 139333523U, // MOVHPDrm
- 943722395U, // MOVHPSmr
- 139333531U, // MOVHPSrm
- 138547107U, // MOVLHPSrr
- 943722412U, // MOVLPDmr
- 139333548U, // MOVLPDrm
- 138547124U, // MOVLPDrr
- 943722427U, // MOVLPSmr
- 139333563U, // MOVLPSrm
- 138547139U, // MOVLPSrr
- 541068596U, // MOVLQ128mr
- 138547124U, // MOVLSD2PDrr
- 138547139U, // MOVLSS2PSrr
- 139857866U, // MOVMSKPDrr
- 139857876U, // MOVMSKPSrr
- 140906462U, // MOVNTDQArm
- 2818576360U, // MOVNTDQmr
- 406851569U, // MOVNTImr
- 1480593401U, // MOVNTPDmr
- 1480593410U, // MOVNTPSmr
+ 140119853U, // MOV64rm
+ 139857709U, // MOV64rr
+ 139857709U, // MOV64rr_REV
+ 139857709U, // MOV64rs
+ 140119853U, // MOV64sm
+ 139857709U, // MOV64sr
+ 139857216U, // MOV64toPQIrr
+ 140119360U, // MOV64toSDrm
+ 139857216U, // MOV64toSDrr
+ 1136660269U, // MOV8ao8
+ 675286829U, // MOV8mi
+ 675286829U, // MOV8mr
+ 675335981U, // MOV8mr_NOREX
+ 1073745779U, // MOV8o8a
+ 140775239U, // MOV8r0
+ 139857709U, // MOV8ri
+ 140250925U, // MOV8rm
+ 140300077U, // MOV8rm_NOREX
+ 139857709U, // MOV8rr
+ 139906861U, // MOV8rr_NOREX
+ 139857709U, // MOV8rr_REV
+ 2818574854U, // MOVAPDmr
+ 140380678U, // MOVAPDrm
+ 139856390U, // MOVAPDrr
+ 2818574862U, // MOVAPSmr
+ 140380686U, // MOVAPSrm
+ 139856398U, // MOVAPSrr
+ 140513149U, // MOVDDUPrm
+ 139857789U, // MOVDDUPrr
+ 139988256U, // MOVDI2PDIrm
+ 139857184U, // MOVDI2PDIrr
+ 139988256U, // MOVDI2SSrm
+ 139857184U, // MOVDI2SSrr
+ 1480593286U, // MOVDQAmr
+ 140906374U, // MOVDQArm
+ 139857798U, // MOVDQArr
+ 1480593294U, // MOVDQUmr
+ 1480593294U, // MOVDQUmr_Int
+ 140906382U, // MOVDQUrm
+ 140906382U, // MOVDQUrm_Int
+ 138547094U, // MOVHLPSrr
+ 943722399U, // MOVHPDmr
+ 139333535U, // MOVHPDrm
+ 943722407U, // MOVHPSmr
+ 139333543U, // MOVHPSrm
+ 138547119U, // MOVLHPSrr
+ 943722424U, // MOVLPDmr
+ 139333560U, // MOVLPDrm
+ 138547136U, // MOVLPDrr
+ 943722439U, // MOVLPSmr
+ 139333575U, // MOVLPSrm
+ 138547151U, // MOVLPSrr
+ 541068608U, // MOVLQ128mr
+ 138547136U, // MOVLSD2PDrr
+ 138547151U, // MOVLSS2PSrr
+ 139857878U, // MOVMSKPDrr
+ 139857888U, // MOVMSKPSrr
+ 140906474U, // MOVNTDQArm
+ 2818576372U, // MOVNTDQmr
+ 406851581U, // MOVNTImr
+ 1480593413U, // MOVNTPDmr
+ 1480593422U, // MOVNTPSmr
0U, // MOVPC32r
- 943722420U, // MOVPD2SDmr
- 139857844U, // MOVPD2SDrr
- 406850836U, // MOVPDI2DImr
- 139857172U, // MOVPDI2DIrr
- 541068596U, // MOVPQI2QImr
- 139857204U, // MOVPQIto64rr
- 809504707U, // MOVPS2SSmr
- 139857859U, // MOVPS2SSrr
- 140119348U, // MOVQI2PQIrm
- 139857204U, // MOVQxrxr
- 140513204U, // MOVSD2PDrm
- 139857844U, // MOVSD2PDrr
- 943722420U, // MOVSDmr
- 140513204U, // MOVSDrm
- 139857844U, // MOVSDrr
- 541068596U, // MOVSDto64mr
- 139857204U, // MOVSDto64rr
- 140382219U, // MOVSHDUPrm
- 139857931U, // MOVSHDUPrr
- 140382229U, // MOVSLDUPrm
- 139857941U, // MOVSLDUPrr
- 406850836U, // MOVSS2DImr
- 139857172U, // MOVSS2DIrr
- 140644291U, // MOVSS2PSrm
- 139857859U, // MOVSS2PSrr
- 809504707U, // MOVSSmr
- 140644291U, // MOVSSrm
- 139857859U, // MOVSSrr
+ 943722432U, // MOVPD2SDmr
+ 139857856U, // MOVPD2SDrr
+ 406850848U, // MOVPDI2DImr
+ 139857184U, // MOVPDI2DIrr
+ 541068608U, // MOVPQI2QImr
+ 139857216U, // MOVPQIto64rr
+ 809504719U, // MOVPS2SSmr
+ 139857871U, // MOVPS2SSrr
+ 140119360U, // MOVQI2PQIrm
+ 139857216U, // MOVQxrxr
+ 140513216U, // MOVSD2PDrm
+ 139857856U, // MOVSD2PDrr
+ 943722432U, // MOVSDmr
+ 140513216U, // MOVSDrm
+ 139857856U, // MOVSDrr
+ 541068608U, // MOVSDto64mr
+ 139857216U, // MOVSDto64rr
+ 140382231U, // MOVSHDUPrm
+ 139857943U, // MOVSHDUPrr
+ 140382241U, // MOVSLDUPrm
+ 139857953U, // MOVSLDUPrr
+ 406850848U, // MOVSS2DImr
+ 139857184U, // MOVSS2DIrr
+ 140644303U, // MOVSS2PSrm
+ 139857871U, // MOVSS2PSrr
+ 809504719U, // MOVSSmr
+ 140644303U, // MOVSSrm
+ 139857871U, // MOVSSrr
0U, // MOVSX16rm8
- 140251167U, // MOVSX16rm8W
+ 140251179U, // MOVSX16rm8W
0U, // MOVSX16rr8
- 139857951U, // MOVSX16rr8W
- 139726879U, // MOVSX32rm16
- 140251167U, // MOVSX32rm8
- 139857951U, // MOVSX32rr16
- 139857951U, // MOVSX32rr8
- 139726879U, // MOVSX64rm16
- 139989030U, // MOVSX64rm32
- 140251167U, // MOVSX64rm8
- 139857951U, // MOVSX64rr16
- 139857958U, // MOVSX64rr32
- 139857951U, // MOVSX64rr8
- 2818576430U, // MOVUPDmr
- 2818576430U, // MOVUPDmr_Int
- 140382254U, // MOVUPDrm
- 140382254U, // MOVUPDrm_Int
- 139857966U, // MOVUPDrr
- 2818576438U, // MOVUPSmr
- 2818576438U, // MOVUPSmr_Int
- 140382262U, // MOVUPSrm
- 140382262U, // MOVUPSrm_Int
- 139857974U, // MOVUPSrr
- 139988244U, // MOVZDI2PDIrm
- 139857172U, // MOVZDI2PDIrr
- 140905780U, // MOVZPQILo2PQIrm
- 139857204U, // MOVZPQILo2PQIrr
- 140119348U, // MOVZQI2PQIrm
- 139857204U, // MOVZQI2PQIrr
- 140513204U, // MOVZSD2PDrm
- 140644291U, // MOVZSS2PSrm
+ 139857963U, // MOVSX16rr8W
+ 139726891U, // MOVSX32rm16
+ 140251179U, // MOVSX32rm8
+ 139857963U, // MOVSX32rr16
+ 139857963U, // MOVSX32rr8
+ 139726891U, // MOVSX64rm16
+ 139989042U, // MOVSX64rm32
+ 140251179U, // MOVSX64rm8
+ 139857963U, // MOVSX64rr16
+ 139857970U, // MOVSX64rr32
+ 139857963U, // MOVSX64rr8
+ 2818576442U, // MOVUPDmr
+ 2818576442U, // MOVUPDmr_Int
+ 140382266U, // MOVUPDrm
+ 140382266U, // MOVUPDrm_Int
+ 139857978U, // MOVUPDrr
+ 2818576450U, // MOVUPSmr
+ 2818576450U, // MOVUPSmr_Int
+ 140382274U, // MOVUPSrm
+ 140382274U, // MOVUPSrm_Int
+ 139857986U, // MOVUPSrr
+ 139988256U, // MOVZDI2PDIrm
+ 139857184U, // MOVZDI2PDIrr
+ 140905792U, // MOVZPQILo2PQIrm
+ 139857216U, // MOVZPQILo2PQIrr
+ 140119360U, // MOVZQI2PQIrm
+ 139857216U, // MOVZQI2PQIrr
+ 140513216U, // MOVZSD2PDrm
+ 140644303U, // MOVZSS2PSrm
0U, // MOVZX16rm8
- 140251198U, // MOVZX16rm8W
+ 140251210U, // MOVZX16rm8W
0U, // MOVZX16rr8
- 139857982U, // MOVZX16rr8W
- 140300350U, // MOVZX32_NOREXrm8
- 139907134U, // MOVZX32_NOREXrr8
- 139726910U, // MOVZX32rm16
- 140251198U, // MOVZX32rm8
- 139857982U, // MOVZX32rr16
- 139857982U, // MOVZX32rr8
+ 139857994U, // MOVZX16rr8W
+ 140300362U, // MOVZX32_NOREXrm8
+ 139907146U, // MOVZX32_NOREXrr8
+ 139726922U, // MOVZX32rm16
+ 140251210U, // MOVZX32rm8
+ 139857994U, // MOVZX32rr16
+ 139857994U, // MOVZX32rr8
0U, // MOVZX64rm16
- 139726910U, // MOVZX64rm16_Q
+ 139726922U, // MOVZX64rm16_Q
0U, // MOVZX64rm32
0U, // MOVZX64rm8
- 140251198U, // MOVZX64rm8_Q
+ 140251210U, // MOVZX64rm8_Q
0U, // MOVZX64rr16
- 139857982U, // MOVZX64rr16_Q
+ 139857994U, // MOVZX64rr16_Q
0U, // MOVZX64rr32
0U, // MOVZX64rr8
- 139857982U, // MOVZX64rr8_Q
+ 139857994U, // MOVZX64rr8_Q
0U, // MOV_Fp3232
0U, // MOV_Fp3264
0U, // MOV_Fp3280
@@ -1454,34 +1457,34 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // MOV_Fp8032
0U, // MOV_Fp8064
0U, // MOV_Fp8080
- 139612229U, // MPSADBWrmi
- 138563653U, // MPSADBWrri
- 268439630U, // MUL16m
- 134221902U, // MUL16r
- 402657358U, // MUL32m
- 134221902U, // MUL32r
- 536875086U, // MUL64m
- 134221902U, // MUL64r
- 671092814U, // MUL8m
- 134221902U, // MUL8r
- 139202643U, // MULPDrm
- 138547283U, // MULPDrr
- 139202650U, // MULPSrm
- 138547290U, // MULPSrr
- 139333729U, // MULSDrm
- 139333729U, // MULSDrm_Int
- 138547297U, // MULSDrr
- 138547297U, // MULSDrr_Int
- 139464808U, // MULSSrm
- 139464808U, // MULSSrm_Int
- 138547304U, // MULSSrr
- 138547304U, // MULSSrr_Int
- 805310575U, // MUL_F32m
- 939528303U, // MUL_F64m
- 268439669U, // MUL_FI16m
- 402657397U, // MUL_FI32m
- 134221948U, // MUL_FPrST0
- 134221935U, // MUL_FST0r
+ 139612241U, // MPSADBWrmi
+ 138563665U, // MPSADBWrri
+ 268439642U, // MUL16m
+ 134221914U, // MUL16r
+ 402657370U, // MUL32m
+ 134221914U, // MUL32r
+ 536875098U, // MUL64m
+ 134221914U, // MUL64r
+ 671092826U, // MUL8m
+ 134221914U, // MUL8r
+ 139202655U, // MULPDrm
+ 138547295U, // MULPDrr
+ 139202662U, // MULPSrm
+ 138547302U, // MULPSrr
+ 139333741U, // MULSDrm
+ 139333741U, // MULSDrm_Int
+ 138547309U, // MULSDrr
+ 138547309U, // MULSDrr_Int
+ 139464820U, // MULSSrm
+ 139464820U, // MULSSrm_Int
+ 138547316U, // MULSSrr
+ 138547316U, // MULSSrr_Int
+ 805310587U, // MUL_F32m
+ 939528315U, // MUL_F64m
+ 268439681U, // MUL_FI16m
+ 402657409U, // MUL_FI32m
+ 134221960U, // MUL_FPrST0
+ 134221947U, // MUL_FST0r
0U, // MUL_Fp32
0U, // MUL_Fp32m
0U, // MUL_Fp64
@@ -1496,785 +1499,785 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // MUL_FpI32m32
0U, // MUL_FpI32m64
0U, // MUL_FpI32m80
- 142610543U, // MUL_FrST0
- 4227U, // MWAIT
- 268439689U, // NEG16m
- 134221961U, // NEG16r
- 402657417U, // NEG32m
- 134221961U, // NEG32r
- 536875145U, // NEG64m
- 134221961U, // NEG64r
- 671092873U, // NEG8m
- 134221961U, // NEG8r
- 4238U, // NOOP
- 402657426U, // NOOPL
- 268439698U, // NOOPW
- 268439703U, // NOT16m
- 134221975U, // NOT16r
- 402657431U, // NOT32m
- 134221975U, // NOT32r
- 536875159U, // NOT64m
- 134221975U, // NOT64r
- 671092887U, // NOT8m
- 134221975U, // NOT8r
- 134221980U, // OR16i16
- 272634021U, // OR16mi
- 272634021U, // OR16mi8
- 272634021U, // OR16mr
- 138547365U, // OR16ri
- 138547365U, // OR16ri8
- 138678437U, // OR16rm
- 138547365U, // OR16rr
- 138547365U, // OR16rr_REV
- 134221993U, // OR32i32
- 406851749U, // OR32mi
- 406851749U, // OR32mi8
- 406851749U, // OR32mr
- 138547365U, // OR32ri
- 138547365U, // OR32ri8
- 138809509U, // OR32rm
- 138547365U, // OR32rr
- 138547365U, // OR32rr_REV
- 134222003U, // OR64i32
- 541069477U, // OR64mi32
- 541069477U, // OR64mi8
- 541069477U, // OR64mr
- 138547365U, // OR64ri32
- 138547365U, // OR64ri8
- 138940581U, // OR64rm
- 138547365U, // OR64rr
- 138547365U, // OR64rr_REV
- 134222013U, // OR8i8
- 675287205U, // OR8mi
- 675287205U, // OR8mr
- 138547365U, // OR8ri
- 139071653U, // OR8rm
- 138547365U, // OR8rr
- 138547365U, // OR8rr_REV
- 139201034U, // ORPDrm
- 138545674U, // ORPDrr
- 139201040U, // ORPSrm
- 138545680U, // ORPSrr
- 201330886U, // OUT16ir
- 4299U, // OUT16rr
- 205525190U, // OUT32ir
- 4312U, // OUT32rr
- 209719494U, // OUT8ir
- 4326U, // OUT8rr
- 4339U, // OUTSB
- 4345U, // OUTSD
- 4351U, // OUTSW
- 140906757U, // PABSBrm128
- 140120325U, // PABSBrm64
- 139858181U, // PABSBrr128
- 139858181U, // PABSBrr64
- 140906764U, // PABSDrm128
- 140120332U, // PABSDrm64
- 139858188U, // PABSDrr128
- 139858188U, // PABSDrr64
- 140906771U, // PABSWrm128
- 140120339U, // PABSWrm64
- 139858195U, // PABSWrr128
- 139858195U, // PABSWrr64
- 139595066U, // PACKSSDWrm
- 138546490U, // PACKSSDWrr
- 139595076U, // PACKSSWBrm
- 138546500U, // PACKSSWBrr
- 139596058U, // PACKUSDWrm
- 138547482U, // PACKUSDWrr
- 139595086U, // PACKUSWBrm
- 138546510U, // PACKUSWBrr
- 139595096U, // PADDBrm
- 138546520U, // PADDBrr
- 139595103U, // PADDDrm
- 138546527U, // PADDDrr
- 139595110U, // PADDQrm
- 138546534U, // PADDQrr
- 139595117U, // PADDSBrm
- 138546541U, // PADDSBrr
- 139595125U, // PADDSWrm
- 138546549U, // PADDSWrr
- 139595133U, // PADDUSBrm
- 138546557U, // PADDUSBrr
- 139595142U, // PADDUSWrm
- 138546566U, // PADDUSWrr
- 139595151U, // PADDWrm
- 138546575U, // PADDWrr
- 139612452U, // PALIGNR128rm
- 138563876U, // PALIGNR128rr
- 138957092U, // PALIGNR64rm
- 138563876U, // PALIGNR64rr
- 139595158U, // PANDNrm
- 138546582U, // PANDNrr
- 139595165U, // PANDrm
- 138546589U, // PANDrr
- 139595171U, // PAVGBrm
- 138546595U, // PAVGBrr
- 139595178U, // PAVGWrm
- 138546602U, // PAVGWrr
- 139628845U, // PBLENDVBrm0
- 138580269U, // PBLENDVBrr0
- 139612471U, // PBLENDWrmi
- 138563895U, // PBLENDWrri
- 139595185U, // PCMPEQBrm
- 138546609U, // PCMPEQBrr
- 139595194U, // PCMPEQDrm
- 138546618U, // PCMPEQDrr
- 139596096U, // PCMPEQQrm
- 138547520U, // PCMPEQQrr
- 139595203U, // PCMPEQWrm
- 138546627U, // PCMPEQWrr
- 140923209U, // PCMPESTRIArm
- 139874633U, // PCMPESTRIArr
- 140923209U, // PCMPESTRICrm
- 139874633U, // PCMPESTRICrr
- 140923209U, // PCMPESTRIOrm
- 139874633U, // PCMPESTRIOrr
- 140923209U, // PCMPESTRISrm
- 139874633U, // PCMPESTRISrr
- 140923209U, // PCMPESTRIZrm
- 139874633U, // PCMPESTRIZrr
- 140923209U, // PCMPESTRIrm
- 139874633U, // PCMPESTRIrr
- 4436U, // PCMPESTRM128MEM
- 4460U, // PCMPESTRM128REG
- 140923268U, // PCMPESTRM128rm
- 139874692U, // PCMPESTRM128rr
- 139595212U, // PCMPGTBrm
- 138546636U, // PCMPGTBrr
- 139595221U, // PCMPGTDrm
- 138546645U, // PCMPGTDrr
- 139596175U, // PCMPGTQrm
- 138547599U, // PCMPGTQrr
- 139595230U, // PCMPGTWrm
- 138546654U, // PCMPGTWrr
- 140923288U, // PCMPISTRIArm
- 139874712U, // PCMPISTRIArr
- 140923288U, // PCMPISTRICrm
- 139874712U, // PCMPISTRICrr
- 140923288U, // PCMPISTRIOrm
- 139874712U, // PCMPISTRIOrr
- 140923288U, // PCMPISTRISrm
- 139874712U, // PCMPISTRISrr
- 140923288U, // PCMPISTRIZrm
- 139874712U, // PCMPISTRIZrr
- 140923288U, // PCMPISTRIrm
- 139874712U, // PCMPISTRIrr
- 4515U, // PCMPISTRM128MEM
- 4539U, // PCMPISTRM128REG
- 140923347U, // PCMPISTRM128rm
- 139874771U, // PCMPISTRM128rr
- 675303902U, // PEXTRBmr
- 139874782U, // PEXTRBrr
- 406868454U, // PEXTRDmr
- 139874790U, // PEXTRDrr
- 541086190U, // PEXTRQmr
- 139874798U, // PEXTRQrr
- 272649703U, // PEXTRWmr
- 139873767U, // PEXTRWri
- 139596278U, // PHADDDrm128
- 138940918U, // PHADDDrm64
- 138547702U, // PHADDDrr128
- 138547702U, // PHADDDrr64
- 139596286U, // PHADDSWrm128
- 138940926U, // PHADDSWrm64
- 138547710U, // PHADDSWrr128
- 138547710U, // PHADDSWrr64
- 139596295U, // PHADDWrm128
- 138940935U, // PHADDWrm64
- 138547719U, // PHADDWrr128
- 138547719U, // PHADDWrr64
- 140907023U, // PHMINPOSUWrm128
- 139858447U, // PHMINPOSUWrr128
- 139596315U, // PHSUBDrm128
- 138940955U, // PHSUBDrm64
- 138547739U, // PHSUBDrr128
- 138547739U, // PHSUBDrr64
- 139596323U, // PHSUBSWrm128
- 138940963U, // PHSUBSWrm64
- 138547747U, // PHSUBSWrr128
- 138547747U, // PHSUBSWrr64
- 139596332U, // PHSUBWrm128
- 138940972U, // PHSUBWrm64
- 138547756U, // PHSUBWrr128
- 138547756U, // PHSUBWrr64
- 139088436U, // PINSRBrm
- 138564148U, // PINSRBrr
- 138826300U, // PINSRDrm
- 138564156U, // PINSRDrr
- 138957380U, // PINSRQrm
- 138564164U, // PINSRQrr
- 138694127U, // PINSRWrmi
- 138563055U, // PINSRWrri
- 139596364U, // PMADDUBSWrm128
- 138941004U, // PMADDUBSWrm64
- 138547788U, // PMADDUBSWrr128
- 138547788U, // PMADDUBSWrr64
- 139595255U, // PMADDWDrm
- 138546679U, // PMADDWDrr
- 139596375U, // PMAXSBrm
- 138547799U, // PMAXSBrr
- 139596383U, // PMAXSDrm
- 138547807U, // PMAXSDrr
- 139595264U, // PMAXSWrm
- 138546688U, // PMAXSWrr
- 139595272U, // PMAXUBrm
- 138546696U, // PMAXUBrr
- 139596391U, // PMAXUDrm
- 138547815U, // PMAXUDrr
- 139596399U, // PMAXUWrm
- 138547823U, // PMAXUWrr
- 139596407U, // PMINSBrm
- 138547831U, // PMINSBrr
- 139596415U, // PMINSDrm
- 138547839U, // PMINSDrr
- 139595280U, // PMINSWrm
- 138546704U, // PMINSWrr
- 139595288U, // PMINUBrm
- 138546712U, // PMINUBrr
- 139596423U, // PMINUDrm
- 138547847U, // PMINUDrr
- 139596431U, // PMINUWrm
- 138547855U, // PMINUWrr
- 139857440U, // PMOVMSKBrr
- 139989655U, // PMOVSXBDrm
- 139858583U, // PMOVSXBDrr
- 139727521U, // PMOVSXBQrm
- 139858593U, // PMOVSXBQrr
- 140120747U, // PMOVSXBWrm
- 139858603U, // PMOVSXBWrr
- 140120757U, // PMOVSXDQrm
- 139858613U, // PMOVSXDQrr
- 140120767U, // PMOVSXWDrm
- 139858623U, // PMOVSXWDrr
- 139989705U, // PMOVSXWQrm
- 139858633U, // PMOVSXWQrr
- 139989715U, // PMOVZXBDrm
- 139858643U, // PMOVZXBDrr
- 139727581U, // PMOVZXBQrm
- 139858653U, // PMOVZXBQrr
- 140120807U, // PMOVZXBWrm
- 139858663U, // PMOVZXBWrr
- 140120817U, // PMOVZXDQrm
- 139858673U, // PMOVZXDQrr
- 140120827U, // PMOVZXWDrm
- 139858683U, // PMOVZXWDrr
- 139989765U, // PMOVZXWQrm
- 139858693U, // PMOVZXWQrr
- 139596559U, // PMULDQrm
- 138547983U, // PMULDQrr
- 139596567U, // PMULHRSWrm128
- 138941207U, // PMULHRSWrm64
- 138547991U, // PMULHRSWrr128
- 138547991U, // PMULHRSWrr64
- 139595306U, // PMULHUWrm
- 138546730U, // PMULHUWrr
- 139595315U, // PMULHWrm
- 138546739U, // PMULHWrr
- 139596577U, // PMULLDrm
- 139596577U, // PMULLDrm_int
- 138548001U, // PMULLDrr
- 138548001U, // PMULLDrr_int
- 139595323U, // PMULLWrm
- 138546747U, // PMULLWrr
- 139595331U, // PMULUDQrm
- 138546755U, // PMULUDQrr
- 134222633U, // POP16r
- 268440361U, // POP16rmm
- 134222633U, // POP16rmr
- 134222633U, // POP32r
- 402658089U, // POP32rmm
- 134222633U, // POP32rmr
- 134222633U, // POP64r
- 536875817U, // POP64rmm
- 134222633U, // POP64rmr
- 139727662U, // POPCNT16rm
- 139858734U, // POPCNT16rr
- 139989806U, // POPCNT32rm
- 139858734U, // POPCNT32rr
- 140120878U, // POPCNT64rm
- 139858734U, // POPCNT64rr
- 4918U, // POPF
- 4918U, // POPFD
- 4918U, // POPFQ
- 4923U, // POPFS16
- 4923U, // POPFS32
- 4923U, // POPFS64
- 4931U, // POPGS16
- 4931U, // POPGS32
- 4931U, // POPGS64
- 139595340U, // PORrm
- 138546764U, // PORrr
- 671093579U, // PREFETCHNTA
- 671093592U, // PREFETCHT0
- 671093604U, // PREFETCHT1
- 671093616U, // PREFETCHT2
- 139595345U, // PSADBWrm
- 138546769U, // PSADBWrr
- 139596668U, // PSHUFBrm128
- 138941308U, // PSHUFBrm64
- 138548092U, // PSHUFBrr128
- 138548092U, // PSHUFBrr64
- 140923780U, // PSHUFDmi
- 139875204U, // PSHUFDri
- 140923788U, // PSHUFHWmi
- 139875212U, // PSHUFHWri
- 140923797U, // PSHUFLWmi
- 139875221U, // PSHUFLWri
- 139596702U, // PSIGNBrm128
- 138941342U, // PSIGNBrm64
- 138548126U, // PSIGNBrr128
- 138548126U, // PSIGNBrr64
- 139596710U, // PSIGNDrm128
- 138941350U, // PSIGNDrm64
- 138548134U, // PSIGNDrr128
- 138548134U, // PSIGNDrr64
- 139596718U, // PSIGNWrm128
- 138941358U, // PSIGNWrm64
- 138548142U, // PSIGNWrr128
- 138548142U, // PSIGNWrr64
- 138548150U, // PSLLDQri
- 138546785U, // PSLLDri
- 139595361U, // PSLLDrm
- 138546785U, // PSLLDrr
- 138546792U, // PSLLQri
- 139595368U, // PSLLQrm
- 138546792U, // PSLLQrr
- 138546799U, // PSLLWri
- 139595375U, // PSLLWrm
- 138546799U, // PSLLWrr
- 138546806U, // PSRADri
- 139595382U, // PSRADrm
- 138546806U, // PSRADrr
- 138546813U, // PSRAWri
- 139595389U, // PSRAWrm
- 138546813U, // PSRAWrr
- 138548158U, // PSRLDQri
- 138546820U, // PSRLDri
- 139595396U, // PSRLDrm
- 138546820U, // PSRLDrr
- 138546827U, // PSRLQri
- 139595403U, // PSRLQrm
- 138546827U, // PSRLQrr
- 138546834U, // PSRLWri
- 139595410U, // PSRLWrm
- 138546834U, // PSRLWrr
- 139595417U, // PSUBBrm
- 138546841U, // PSUBBrr
- 139595424U, // PSUBDrm
- 138546848U, // PSUBDrr
- 139595431U, // PSUBQrm
- 138546855U, // PSUBQrr
- 139595438U, // PSUBSBrm
- 138546862U, // PSUBSBrr
- 139595446U, // PSUBSWrm
- 138546870U, // PSUBSWrr
- 139595454U, // PSUBUSBrm
- 138546878U, // PSUBUSBrr
- 139595463U, // PSUBUSWrm
- 138546887U, // PSUBUSWrr
- 139595472U, // PSUBWrm
- 138546896U, // PSUBWrr
- 140907462U, // PTESTrm
- 139858886U, // PTESTrr
- 139595479U, // PUNPCKHBWrm
- 138546903U, // PUNPCKHBWrr
- 139595490U, // PUNPCKHDQrm
- 138546914U, // PUNPCKHDQrr
- 139596750U, // PUNPCKHQDQrm
- 138548174U, // PUNPCKHQDQrr
- 139595501U, // PUNPCKHWDrm
- 138546925U, // PUNPCKHWDrr
- 139595512U, // PUNPCKLBWrm
- 138546936U, // PUNPCKLBWrr
- 139595523U, // PUNPCKLDQrm
- 138546947U, // PUNPCKLDQrr
- 139596762U, // PUNPCKLQDQrm
- 138548186U, // PUNPCKLQDQrr
- 139595534U, // PUNPCKLWDrm
- 138546958U, // PUNPCKLWDrr
- 134222822U, // PUSH16r
- 268440550U, // PUSH16rmm
- 134222822U, // PUSH16rmr
- 134222822U, // PUSH32i16
- 134222822U, // PUSH32i32
- 134222822U, // PUSH32i8
- 134222822U, // PUSH32r
- 402658278U, // PUSH32rmm
- 134222822U, // PUSH32rmr
- 134222822U, // PUSH64i16
- 134222822U, // PUSH64i32
- 134222822U, // PUSH64i8
- 134222822U, // PUSH64r
- 536876006U, // PUSH64rmm
- 134222822U, // PUSH64rmr
- 5100U, // PUSHF
- 5100U, // PUSHFD
- 5100U, // PUSHFQ64
- 5106U, // PUSHFS16
- 5106U, // PUSHFS32
- 5106U, // PUSHFS64
- 5115U, // PUSHGS16
- 5115U, // PUSHGS32
- 5115U, // PUSHGS64
- 139594228U, // PXORrm
- 138545652U, // PXORrr
- 348132356U, // RCL16m1
- 352326660U, // RCL16mCL
- 275780612U, // RCL16mi
- 213914628U, // RCL16r1
- 218108932U, // RCL16rCL
- 138548228U, // RCL16ri
- 482350084U, // RCL32m1
- 486544388U, // RCL32mCL
- 409998340U, // RCL32mi
- 213914628U, // RCL32r1
- 218108932U, // RCL32rCL
- 138548228U, // RCL32ri
- 616567812U, // RCL64m1
- 620762116U, // RCL64mCL
- 544216068U, // RCL64mi
- 213914628U, // RCL64r1
- 218108932U, // RCL64rCL
- 138548228U, // RCL64ri
- 750785540U, // RCL8m1
- 754979844U, // RCL8mCL
- 678433796U, // RCL8mi
- 213914628U, // RCL8r1
- 218108932U, // RCL8rCL
- 138548228U, // RCL8ri
- 140383241U, // RCPPSm
- 140383241U, // RCPPSm_Int
- 139858953U, // RCPPSr
- 139858953U, // RCPPSr_Int
- 140645392U, // RCPSSm
- 140645392U, // RCPSSm_Int
- 139858960U, // RCPSSr
- 139858960U, // RCPSSr_Int
- 348132375U, // RCR16m1
- 352326679U, // RCR16mCL
- 275780631U, // RCR16mi
- 213914647U, // RCR16r1
- 218108951U, // RCR16rCL
- 138548247U, // RCR16ri
- 482350103U, // RCR32m1
- 486544407U, // RCR32mCL
- 409998359U, // RCR32mi
- 213914647U, // RCR32r1
- 218108951U, // RCR32rCL
- 138548247U, // RCR32ri
- 616567831U, // RCR64m1
- 620762135U, // RCR64mCL
- 544216087U, // RCR64mi
- 213914647U, // RCR64r1
- 218108951U, // RCR64rCL
- 138548247U, // RCR64ri
- 750785559U, // RCR8m1
- 754979863U, // RCR8mCL
- 678433815U, // RCR8mi
- 213914647U, // RCR8r1
- 218108951U, // RCR8rCL
- 138548247U, // RCR8ri
- 5148U, // RDMSR
- 5154U, // RDPMC
- 5160U, // RDTSC
- 5166U, // REP_MOVSB
- 5176U, // REP_MOVSD
- 5186U, // REP_MOVSQ
- 5196U, // REP_MOVSW
- 5206U, // REP_STOSB
- 5216U, // REP_STOSD
- 5226U, // REP_STOSQ
- 5236U, // REP_STOSW
- 5246U, // RET
- 134222978U, // RETI
- 268440711U, // ROL16m1
- 352326791U, // ROL16mCL
- 272635015U, // ROL16mi
- 134222983U, // ROL16r1
- 218109063U, // ROL16rCL
- 138548359U, // ROL16ri
- 402658439U, // ROL32m1
- 486544519U, // ROL32mCL
- 406852743U, // ROL32mi
- 134222983U, // ROL32r1
- 218109063U, // ROL32rCL
- 138548359U, // ROL32ri
- 536876167U, // ROL64m1
- 624956551U, // ROL64mCL
- 541070471U, // ROL64mi
- 134222983U, // ROL64r1
- 222303367U, // ROL64rCL
- 138548359U, // ROL64ri
- 671093895U, // ROL8m1
- 754979975U, // ROL8mCL
- 675288199U, // ROL8mi
- 134222983U, // ROL8r1
- 218109063U, // ROL8rCL
- 138548359U, // ROL8ri
- 268440716U, // ROR16m1
- 352326796U, // ROR16mCL
- 272635020U, // ROR16mi
- 134222988U, // ROR16r1
- 218109068U, // ROR16rCL
- 138548364U, // ROR16ri
- 402658444U, // ROR32m1
- 486544524U, // ROR32mCL
- 406852748U, // ROR32mi
- 134222988U, // ROR32r1
- 218109068U, // ROR32rCL
- 138548364U, // ROR32ri
- 536876172U, // ROR64m1
- 624956556U, // ROR64mCL
- 541070476U, // ROR64mi
- 134222988U, // ROR64r1
- 222303372U, // ROR64rCL
- 138548364U, // ROR64ri
- 671093900U, // ROR8m1
- 754979980U, // ROR8mCL
- 675288204U, // ROR8mi
- 134222988U, // ROR8r1
- 218109068U, // ROR8rCL
- 138548364U, // ROR8ri
- 140399761U, // ROUNDPDm_Int
- 139875473U, // ROUNDPDr_Int
- 140399770U, // ROUNDPSm_Int
- 139875482U, // ROUNDPSr_Int
- 139351203U, // ROUNDSDm_Int
- 138564771U, // ROUNDSDr_Int
- 139482284U, // ROUNDSSm_Int
- 138564780U, // ROUNDSSr_Int
- 5301U, // RSM
- 140383417U, // RSQRTPSm
- 140383417U, // RSQRTPSm_Int
- 139859129U, // RSQRTPSr
- 139859129U, // RSQRTPSr_Int
- 140645570U, // RSQRTSSm
- 140645570U, // RSQRTSSm_Int
- 139859138U, // RSQRTSSr
- 139859138U, // RSQRTSSr_Int
- 5323U, // SAHF
- 268440784U, // SAR16m1
- 352326864U, // SAR16mCL
- 272635088U, // SAR16mi
- 134223056U, // SAR16r1
- 218109136U, // SAR16rCL
- 138548432U, // SAR16ri
- 402658512U, // SAR32m1
- 486544592U, // SAR32mCL
- 406852816U, // SAR32mi
- 134223056U, // SAR32r1
- 218109136U, // SAR32rCL
- 138548432U, // SAR32ri
- 536876240U, // SAR64m1
- 624956624U, // SAR64mCL
- 541070544U, // SAR64mi
- 134223056U, // SAR64r1
- 222303440U, // SAR64rCL
- 138548432U, // SAR64ri
- 671093968U, // SAR8m1
- 754980048U, // SAR8mCL
- 675288272U, // SAR8mi
- 134223056U, // SAR8r1
- 218109136U, // SAR8rCL
- 138548432U, // SAR8ri
- 134223061U, // SBB16i16
- 272635103U, // SBB16mi
- 272635103U, // SBB16mi8
- 272635103U, // SBB16mr
- 138548447U, // SBB16ri
- 138548447U, // SBB16ri8
- 138679519U, // SBB16rm
- 138548447U, // SBB16rr
- 138548447U, // SBB16rr_REV
- 134223076U, // SBB32i32
- 406852831U, // SBB32mi
- 406852831U, // SBB32mi8
- 406852831U, // SBB32mr
- 138548447U, // SBB32ri
- 138548447U, // SBB32ri8
- 138810591U, // SBB32rm
- 138548447U, // SBB32rr
- 138548447U, // SBB32rr_REV
- 134223087U, // SBB64i32
- 541070559U, // SBB64mi32
- 541070559U, // SBB64mi8
- 541070559U, // SBB64mr
- 138548447U, // SBB64ri32
- 138548447U, // SBB64ri8
- 138941663U, // SBB64rm
- 138548447U, // SBB64rr
- 138548447U, // SBB64rr_REV
- 134223098U, // SBB8i8
- 675288287U, // SBB8mi
- 675288287U, // SBB8mr
- 138548447U, // SBB8ri
- 139072735U, // SBB8rm
- 138548447U, // SBB8rr
- 138548447U, // SBB8rr_REV
- 5380U, // SCAS16
- 5380U, // SCAS32
- 5380U, // SCAS64
- 5380U, // SCAS8
- 671094025U, // SETAEm
- 134223113U, // SETAEr
- 671094032U, // SETAm
- 134223120U, // SETAr
- 671094038U, // SETBEm
- 134223126U, // SETBEr
- 140776671U, // SETB_C16r
- 140776671U, // SETB_C32r
- 140776671U, // SETB_C64r
- 140776671U, // SETB_C8r
- 671094045U, // SETBm
- 134223133U, // SETBr
- 671094051U, // SETEm
- 134223139U, // SETEr
- 671094057U, // SETGEm
- 134223145U, // SETGEr
- 671094064U, // SETGm
- 134223152U, // SETGr
- 671094070U, // SETLEm
- 134223158U, // SETLEr
- 671094077U, // SETLm
- 134223165U, // SETLr
- 671094083U, // SETNEm
- 134223171U, // SETNEr
- 671094090U, // SETNOm
- 134223178U, // SETNOr
- 671094097U, // SETNPm
- 134223185U, // SETNPr
- 671094104U, // SETNSm
- 134223192U, // SETNSr
- 671094111U, // SETOm
- 134223199U, // SETOr
- 671094117U, // SETPm
- 134223205U, // SETPr
- 671094123U, // SETSm
- 134223211U, // SETSr
- 5489U, // SFENCE
- 1744835960U, // SGDTm
- 268440958U, // SHL16m1
- 352327038U, // SHL16mCL
- 272635262U, // SHL16mi
- 134223230U, // SHL16r1
- 218109310U, // SHL16rCL
- 138548606U, // SHL16ri
- 402658686U, // SHL32m1
- 486544766U, // SHL32mCL
- 406852990U, // SHL32mi
- 134223230U, // SHL32r1
- 218109310U, // SHL32rCL
- 138548606U, // SHL32ri
- 536876414U, // SHL64m1
- 624956798U, // SHL64mCL
- 541070718U, // SHL64mi
- 134223230U, // SHL64r1
- 222303614U, // SHL64rCL
- 138548606U, // SHL64ri
- 671094142U, // SHL8m1
- 754980222U, // SHL8mCL
- 675288446U, // SHL8mi
- 134223230U, // SHL8r1
- 218109310U, // SHL8rCL
- 138548606U, // SHL8ri
- 272700803U, // SHLD16mrCL
- 272651651U, // SHLD16mri8
- 138614147U, // SHLD16rrCL
- 138564995U, // SHLD16rri8
- 406918531U, // SHLD32mrCL
- 406869379U, // SHLD32mri8
- 138614147U, // SHLD32rrCL
- 138564995U, // SHLD32rri8
- 541152643U, // SHLD64mrCL
- 541087107U, // SHLD64mri8
- 138630531U, // SHLD64rrCL
- 138564995U, // SHLD64rri8
- 268440969U, // SHR16m1
- 352327049U, // SHR16mCL
- 272635273U, // SHR16mi
- 134223241U, // SHR16r1
- 218109321U, // SHR16rCL
- 138548617U, // SHR16ri
- 402658697U, // SHR32m1
- 486544777U, // SHR32mCL
- 406853001U, // SHR32mi
- 134223241U, // SHR32r1
- 218109321U, // SHR32rCL
- 138548617U, // SHR32ri
- 536876425U, // SHR64m1
- 624956809U, // SHR64mCL
- 541070729U, // SHR64mi
- 134223241U, // SHR64r1
- 222303625U, // SHR64rCL
- 138548617U, // SHR64ri
- 671094153U, // SHR8m1
- 754980233U, // SHR8mCL
- 675288457U, // SHR8mi
- 134223241U, // SHR8r1
- 218109321U, // SHR8rCL
- 138548617U, // SHR8ri
- 272700814U, // SHRD16mrCL
- 272651662U, // SHRD16mri8
- 138614158U, // SHRD16rrCL
- 138565006U, // SHRD16rri8
- 406918542U, // SHRD32mrCL
- 406869390U, // SHRD32mri8
- 138614158U, // SHRD32rrCL
- 138565006U, // SHRD32rri8
- 541152654U, // SHRD64mrCL
- 541087118U, // SHRD64mri8
- 138630542U, // SHRD64rrCL
- 138565006U, // SHRD64rri8
- 139220372U, // SHUFPDrmi
- 138565012U, // SHUFPDrri
- 139220380U, // SHUFPSrmi
- 138565020U, // SHUFPSrri
- 1744836004U, // SIDTm
- 5546U, // SIN_F
+ 142610555U, // MUL_FrST0
+ 4239U, // MWAIT
+ 268439701U, // NEG16m
+ 134221973U, // NEG16r
+ 402657429U, // NEG32m
+ 134221973U, // NEG32r
+ 536875157U, // NEG64m
+ 134221973U, // NEG64r
+ 671092885U, // NEG8m
+ 134221973U, // NEG8r
+ 4250U, // NOOP
+ 402657438U, // NOOPL
+ 268439710U, // NOOPW
+ 268439715U, // NOT16m
+ 134221987U, // NOT16r
+ 402657443U, // NOT32m
+ 134221987U, // NOT32r
+ 536875171U, // NOT64m
+ 134221987U, // NOT64r
+ 671092899U, // NOT8m
+ 134221987U, // NOT8r
+ 134221992U, // OR16i16
+ 272634033U, // OR16mi
+ 272634033U, // OR16mi8
+ 272634033U, // OR16mr
+ 138547377U, // OR16ri
+ 138547377U, // OR16ri8
+ 138678449U, // OR16rm
+ 138547377U, // OR16rr
+ 138547377U, // OR16rr_REV
+ 134222005U, // OR32i32
+ 406851761U, // OR32mi
+ 406851761U, // OR32mi8
+ 406851761U, // OR32mr
+ 138547377U, // OR32ri
+ 138547377U, // OR32ri8
+ 138809521U, // OR32rm
+ 138547377U, // OR32rr
+ 138547377U, // OR32rr_REV
+ 134222015U, // OR64i32
+ 541069489U, // OR64mi32
+ 541069489U, // OR64mi8
+ 541069489U, // OR64mr
+ 138547377U, // OR64ri32
+ 138547377U, // OR64ri8
+ 138940593U, // OR64rm
+ 138547377U, // OR64rr
+ 138547377U, // OR64rr_REV
+ 134222025U, // OR8i8
+ 675287217U, // OR8mi
+ 675287217U, // OR8mr
+ 138547377U, // OR8ri
+ 139071665U, // OR8rm
+ 138547377U, // OR8rr
+ 138547377U, // OR8rr_REV
+ 139201046U, // ORPDrm
+ 138545686U, // ORPDrr
+ 139201052U, // ORPSrm
+ 138545692U, // ORPSrr
+ 201330898U, // OUT16ir
+ 4311U, // OUT16rr
+ 205525202U, // OUT32ir
+ 4324U, // OUT32rr
+ 209719506U, // OUT8ir
+ 4338U, // OUT8rr
+ 4351U, // OUTSB
+ 4357U, // OUTSD
+ 4363U, // OUTSW
+ 140906769U, // PABSBrm128
+ 140120337U, // PABSBrm64
+ 139858193U, // PABSBrr128
+ 139858193U, // PABSBrr64
+ 140906776U, // PABSDrm128
+ 140120344U, // PABSDrm64
+ 139858200U, // PABSDrr128
+ 139858200U, // PABSDrr64
+ 140906783U, // PABSWrm128
+ 140120351U, // PABSWrm64
+ 139858207U, // PABSWrr128
+ 139858207U, // PABSWrr64
+ 139595078U, // PACKSSDWrm
+ 138546502U, // PACKSSDWrr
+ 139595088U, // PACKSSWBrm
+ 138546512U, // PACKSSWBrr
+ 139596070U, // PACKUSDWrm
+ 138547494U, // PACKUSDWrr
+ 139595098U, // PACKUSWBrm
+ 138546522U, // PACKUSWBrr
+ 139595108U, // PADDBrm
+ 138546532U, // PADDBrr
+ 139595115U, // PADDDrm
+ 138546539U, // PADDDrr
+ 139595122U, // PADDQrm
+ 138546546U, // PADDQrr
+ 139595129U, // PADDSBrm
+ 138546553U, // PADDSBrr
+ 139595137U, // PADDSWrm
+ 138546561U, // PADDSWrr
+ 139595145U, // PADDUSBrm
+ 138546569U, // PADDUSBrr
+ 139595154U, // PADDUSWrm
+ 138546578U, // PADDUSWrr
+ 139595163U, // PADDWrm
+ 138546587U, // PADDWrr
+ 139612464U, // PALIGNR128rm
+ 138563888U, // PALIGNR128rr
+ 138957104U, // PALIGNR64rm
+ 138563888U, // PALIGNR64rr
+ 139595170U, // PANDNrm
+ 138546594U, // PANDNrr
+ 139595177U, // PANDrm
+ 138546601U, // PANDrr
+ 139595183U, // PAVGBrm
+ 138546607U, // PAVGBrr
+ 139595190U, // PAVGWrm
+ 138546614U, // PAVGWrr
+ 139628857U, // PBLENDVBrm0
+ 138580281U, // PBLENDVBrr0
+ 139612483U, // PBLENDWrmi
+ 138563907U, // PBLENDWrri
+ 139595197U, // PCMPEQBrm
+ 138546621U, // PCMPEQBrr
+ 139595206U, // PCMPEQDrm
+ 138546630U, // PCMPEQDrr
+ 139596108U, // PCMPEQQrm
+ 138547532U, // PCMPEQQrr
+ 139595215U, // PCMPEQWrm
+ 138546639U, // PCMPEQWrr
+ 140923221U, // PCMPESTRIArm
+ 139874645U, // PCMPESTRIArr
+ 140923221U, // PCMPESTRICrm
+ 139874645U, // PCMPESTRICrr
+ 140923221U, // PCMPESTRIOrm
+ 139874645U, // PCMPESTRIOrr
+ 140923221U, // PCMPESTRISrm
+ 139874645U, // PCMPESTRISrr
+ 140923221U, // PCMPESTRIZrm
+ 139874645U, // PCMPESTRIZrr
+ 140923221U, // PCMPESTRIrm
+ 139874645U, // PCMPESTRIrr
+ 4448U, // PCMPESTRM128MEM
+ 4472U, // PCMPESTRM128REG
+ 140923280U, // PCMPESTRM128rm
+ 139874704U, // PCMPESTRM128rr
+ 139595224U, // PCMPGTBrm
+ 138546648U, // PCMPGTBrr
+ 139595233U, // PCMPGTDrm
+ 138546657U, // PCMPGTDrr
+ 139596187U, // PCMPGTQrm
+ 138547611U, // PCMPGTQrr
+ 139595242U, // PCMPGTWrm
+ 138546666U, // PCMPGTWrr
+ 140923300U, // PCMPISTRIArm
+ 139874724U, // PCMPISTRIArr
+ 140923300U, // PCMPISTRICrm
+ 139874724U, // PCMPISTRICrr
+ 140923300U, // PCMPISTRIOrm
+ 139874724U, // PCMPISTRIOrr
+ 140923300U, // PCMPISTRISrm
+ 139874724U, // PCMPISTRISrr
+ 140923300U, // PCMPISTRIZrm
+ 139874724U, // PCMPISTRIZrr
+ 140923300U, // PCMPISTRIrm
+ 139874724U, // PCMPISTRIrr
+ 4527U, // PCMPISTRM128MEM
+ 4551U, // PCMPISTRM128REG
+ 140923359U, // PCMPISTRM128rm
+ 139874783U, // PCMPISTRM128rr
+ 675303914U, // PEXTRBmr
+ 139874794U, // PEXTRBrr
+ 406868466U, // PEXTRDmr
+ 139874802U, // PEXTRDrr
+ 541086202U, // PEXTRQmr
+ 139874810U, // PEXTRQrr
+ 272649715U, // PEXTRWmr
+ 139873779U, // PEXTRWri
+ 139596290U, // PHADDDrm128
+ 138940930U, // PHADDDrm64
+ 138547714U, // PHADDDrr128
+ 138547714U, // PHADDDrr64
+ 139596298U, // PHADDSWrm128
+ 138940938U, // PHADDSWrm64
+ 138547722U, // PHADDSWrr128
+ 138547722U, // PHADDSWrr64
+ 139596307U, // PHADDWrm128
+ 138940947U, // PHADDWrm64
+ 138547731U, // PHADDWrr128
+ 138547731U, // PHADDWrr64
+ 140907035U, // PHMINPOSUWrm128
+ 139858459U, // PHMINPOSUWrr128
+ 139596327U, // PHSUBDrm128
+ 138940967U, // PHSUBDrm64
+ 138547751U, // PHSUBDrr128
+ 138547751U, // PHSUBDrr64
+ 139596335U, // PHSUBSWrm128
+ 138940975U, // PHSUBSWrm64
+ 138547759U, // PHSUBSWrr128
+ 138547759U, // PHSUBSWrr64
+ 139596344U, // PHSUBWrm128
+ 138940984U, // PHSUBWrm64
+ 138547768U, // PHSUBWrr128
+ 138547768U, // PHSUBWrr64
+ 139088448U, // PINSRBrm
+ 138564160U, // PINSRBrr
+ 138826312U, // PINSRDrm
+ 138564168U, // PINSRDrr
+ 138957392U, // PINSRQrm
+ 138564176U, // PINSRQrr
+ 138694139U, // PINSRWrmi
+ 138563067U, // PINSRWrri
+ 139596376U, // PMADDUBSWrm128
+ 138941016U, // PMADDUBSWrm64
+ 138547800U, // PMADDUBSWrr128
+ 138547800U, // PMADDUBSWrr64
+ 139595267U, // PMADDWDrm
+ 138546691U, // PMADDWDrr
+ 139596387U, // PMAXSBrm
+ 138547811U, // PMAXSBrr
+ 139596395U, // PMAXSDrm
+ 138547819U, // PMAXSDrr
+ 139595276U, // PMAXSWrm
+ 138546700U, // PMAXSWrr
+ 139595284U, // PMAXUBrm
+ 138546708U, // PMAXUBrr
+ 139596403U, // PMAXUDrm
+ 138547827U, // PMAXUDrr
+ 139596411U, // PMAXUWrm
+ 138547835U, // PMAXUWrr
+ 139596419U, // PMINSBrm
+ 138547843U, // PMINSBrr
+ 139596427U, // PMINSDrm
+ 138547851U, // PMINSDrr
+ 139595292U, // PMINSWrm
+ 138546716U, // PMINSWrr
+ 139595300U, // PMINUBrm
+ 138546724U, // PMINUBrr
+ 139596435U, // PMINUDrm
+ 138547859U, // PMINUDrr
+ 139596443U, // PMINUWrm
+ 138547867U, // PMINUWrr
+ 139857452U, // PMOVMSKBrr
+ 139989667U, // PMOVSXBDrm
+ 139858595U, // PMOVSXBDrr
+ 139727533U, // PMOVSXBQrm
+ 139858605U, // PMOVSXBQrr
+ 140120759U, // PMOVSXBWrm
+ 139858615U, // PMOVSXBWrr
+ 140120769U, // PMOVSXDQrm
+ 139858625U, // PMOVSXDQrr
+ 140120779U, // PMOVSXWDrm
+ 139858635U, // PMOVSXWDrr
+ 139989717U, // PMOVSXWQrm
+ 139858645U, // PMOVSXWQrr
+ 139989727U, // PMOVZXBDrm
+ 139858655U, // PMOVZXBDrr
+ 139727593U, // PMOVZXBQrm
+ 139858665U, // PMOVZXBQrr
+ 140120819U, // PMOVZXBWrm
+ 139858675U, // PMOVZXBWrr
+ 140120829U, // PMOVZXDQrm
+ 139858685U, // PMOVZXDQrr
+ 140120839U, // PMOVZXWDrm
+ 139858695U, // PMOVZXWDrr
+ 139989777U, // PMOVZXWQrm
+ 139858705U, // PMOVZXWQrr
+ 139596571U, // PMULDQrm
+ 138547995U, // PMULDQrr
+ 139596579U, // PMULHRSWrm128
+ 138941219U, // PMULHRSWrm64
+ 138548003U, // PMULHRSWrr128
+ 138548003U, // PMULHRSWrr64
+ 139595318U, // PMULHUWrm
+ 138546742U, // PMULHUWrr
+ 139595327U, // PMULHWrm
+ 138546751U, // PMULHWrr
+ 139596589U, // PMULLDrm
+ 139596589U, // PMULLDrm_int
+ 138548013U, // PMULLDrr
+ 138548013U, // PMULLDrr_int
+ 139595335U, // PMULLWrm
+ 138546759U, // PMULLWrr
+ 139595343U, // PMULUDQrm
+ 138546767U, // PMULUDQrr
+ 134222645U, // POP16r
+ 268440373U, // POP16rmm
+ 134222645U, // POP16rmr
+ 134222645U, // POP32r
+ 402658101U, // POP32rmm
+ 134222645U, // POP32rmr
+ 134222645U, // POP64r
+ 536875829U, // POP64rmm
+ 134222645U, // POP64rmr
+ 139727674U, // POPCNT16rm
+ 139858746U, // POPCNT16rr
+ 139989818U, // POPCNT32rm
+ 139858746U, // POPCNT32rr
+ 140120890U, // POPCNT64rm
+ 139858746U, // POPCNT64rr
+ 4930U, // POPF
+ 4930U, // POPFD
+ 4930U, // POPFQ
+ 4935U, // POPFS16
+ 4935U, // POPFS32
+ 4935U, // POPFS64
+ 4943U, // POPGS16
+ 4943U, // POPGS32
+ 4943U, // POPGS64
+ 139595352U, // PORrm
+ 138546776U, // PORrr
+ 671093591U, // PREFETCHNTA
+ 671093604U, // PREFETCHT0
+ 671093616U, // PREFETCHT1
+ 671093628U, // PREFETCHT2
+ 139595357U, // PSADBWrm
+ 138546781U, // PSADBWrr
+ 139596680U, // PSHUFBrm128
+ 138941320U, // PSHUFBrm64
+ 138548104U, // PSHUFBrr128
+ 138548104U, // PSHUFBrr64
+ 140923792U, // PSHUFDmi
+ 139875216U, // PSHUFDri
+ 140923800U, // PSHUFHWmi
+ 139875224U, // PSHUFHWri
+ 140923809U, // PSHUFLWmi
+ 139875233U, // PSHUFLWri
+ 139596714U, // PSIGNBrm128
+ 138941354U, // PSIGNBrm64
+ 138548138U, // PSIGNBrr128
+ 138548138U, // PSIGNBrr64
+ 139596722U, // PSIGNDrm128
+ 138941362U, // PSIGNDrm64
+ 138548146U, // PSIGNDrr128
+ 138548146U, // PSIGNDrr64
+ 139596730U, // PSIGNWrm128
+ 138941370U, // PSIGNWrm64
+ 138548154U, // PSIGNWrr128
+ 138548154U, // PSIGNWrr64
+ 138548162U, // PSLLDQri
+ 138546797U, // PSLLDri
+ 139595373U, // PSLLDrm
+ 138546797U, // PSLLDrr
+ 138546804U, // PSLLQri
+ 139595380U, // PSLLQrm
+ 138546804U, // PSLLQrr
+ 138546811U, // PSLLWri
+ 139595387U, // PSLLWrm
+ 138546811U, // PSLLWrr
+ 138546818U, // PSRADri
+ 139595394U, // PSRADrm
+ 138546818U, // PSRADrr
+ 138546825U, // PSRAWri
+ 139595401U, // PSRAWrm
+ 138546825U, // PSRAWrr
+ 138548170U, // PSRLDQri
+ 138546832U, // PSRLDri
+ 139595408U, // PSRLDrm
+ 138546832U, // PSRLDrr
+ 138546839U, // PSRLQri
+ 139595415U, // PSRLQrm
+ 138546839U, // PSRLQrr
+ 138546846U, // PSRLWri
+ 139595422U, // PSRLWrm
+ 138546846U, // PSRLWrr
+ 139595429U, // PSUBBrm
+ 138546853U, // PSUBBrr
+ 139595436U, // PSUBDrm
+ 138546860U, // PSUBDrr
+ 139595443U, // PSUBQrm
+ 138546867U, // PSUBQrr
+ 139595450U, // PSUBSBrm
+ 138546874U, // PSUBSBrr
+ 139595458U, // PSUBSWrm
+ 138546882U, // PSUBSWrr
+ 139595466U, // PSUBUSBrm
+ 138546890U, // PSUBUSBrr
+ 139595475U, // PSUBUSWrm
+ 138546899U, // PSUBUSWrr
+ 139595484U, // PSUBWrm
+ 138546908U, // PSUBWrr
+ 140907474U, // PTESTrm
+ 139858898U, // PTESTrr
+ 139595491U, // PUNPCKHBWrm
+ 138546915U, // PUNPCKHBWrr
+ 139595502U, // PUNPCKHDQrm
+ 138546926U, // PUNPCKHDQrr
+ 139596762U, // PUNPCKHQDQrm
+ 138548186U, // PUNPCKHQDQrr
+ 139595513U, // PUNPCKHWDrm
+ 138546937U, // PUNPCKHWDrr
+ 139595524U, // PUNPCKLBWrm
+ 138546948U, // PUNPCKLBWrr
+ 139595535U, // PUNPCKLDQrm
+ 138546959U, // PUNPCKLDQrr
+ 139596774U, // PUNPCKLQDQrm
+ 138548198U, // PUNPCKLQDQrr
+ 139595546U, // PUNPCKLWDrm
+ 138546970U, // PUNPCKLWDrr
+ 134222834U, // PUSH16r
+ 268440562U, // PUSH16rmm
+ 134222834U, // PUSH16rmr
+ 134222834U, // PUSH32i16
+ 134222834U, // PUSH32i32
+ 134222834U, // PUSH32i8
+ 134222834U, // PUSH32r
+ 402658290U, // PUSH32rmm
+ 134222834U, // PUSH32rmr
+ 134222834U, // PUSH64i16
+ 134222834U, // PUSH64i32
+ 134222834U, // PUSH64i8
+ 134222834U, // PUSH64r
+ 536876018U, // PUSH64rmm
+ 134222834U, // PUSH64rmr
+ 5112U, // PUSHF
+ 5112U, // PUSHFD
+ 5112U, // PUSHFQ64
+ 5118U, // PUSHFS16
+ 5118U, // PUSHFS32
+ 5118U, // PUSHFS64
+ 5127U, // PUSHGS16
+ 5127U, // PUSHGS32
+ 5127U, // PUSHGS64
+ 139594240U, // PXORrm
+ 138545664U, // PXORrr
+ 348132368U, // RCL16m1
+ 352326672U, // RCL16mCL
+ 275780624U, // RCL16mi
+ 213914640U, // RCL16r1
+ 218108944U, // RCL16rCL
+ 138548240U, // RCL16ri
+ 482350096U, // RCL32m1
+ 486544400U, // RCL32mCL
+ 409998352U, // RCL32mi
+ 213914640U, // RCL32r1
+ 218108944U, // RCL32rCL
+ 138548240U, // RCL32ri
+ 616567824U, // RCL64m1
+ 620762128U, // RCL64mCL
+ 544216080U, // RCL64mi
+ 213914640U, // RCL64r1
+ 218108944U, // RCL64rCL
+ 138548240U, // RCL64ri
+ 750785552U, // RCL8m1
+ 754979856U, // RCL8mCL
+ 678433808U, // RCL8mi
+ 213914640U, // RCL8r1
+ 218108944U, // RCL8rCL
+ 138548240U, // RCL8ri
+ 140383253U, // RCPPSm
+ 140383253U, // RCPPSm_Int
+ 139858965U, // RCPPSr
+ 139858965U, // RCPPSr_Int
+ 140645404U, // RCPSSm
+ 140645404U, // RCPSSm_Int
+ 139858972U, // RCPSSr
+ 139858972U, // RCPSSr_Int
+ 348132387U, // RCR16m1
+ 352326691U, // RCR16mCL
+ 275780643U, // RCR16mi
+ 213914659U, // RCR16r1
+ 218108963U, // RCR16rCL
+ 138548259U, // RCR16ri
+ 482350115U, // RCR32m1
+ 486544419U, // RCR32mCL
+ 409998371U, // RCR32mi
+ 213914659U, // RCR32r1
+ 218108963U, // RCR32rCL
+ 138548259U, // RCR32ri
+ 616567843U, // RCR64m1
+ 620762147U, // RCR64mCL
+ 544216099U, // RCR64mi
+ 213914659U, // RCR64r1
+ 218108963U, // RCR64rCL
+ 138548259U, // RCR64ri
+ 750785571U, // RCR8m1
+ 754979875U, // RCR8mCL
+ 678433827U, // RCR8mi
+ 213914659U, // RCR8r1
+ 218108963U, // RCR8rCL
+ 138548259U, // RCR8ri
+ 5160U, // RDMSR
+ 5166U, // RDPMC
+ 5172U, // RDTSC
+ 5178U, // REP_MOVSB
+ 5188U, // REP_MOVSD
+ 5198U, // REP_MOVSQ
+ 5208U, // REP_MOVSW
+ 5218U, // REP_STOSB
+ 5228U, // REP_STOSD
+ 5238U, // REP_STOSQ
+ 5248U, // REP_STOSW
+ 5258U, // RET
+ 134222990U, // RETI
+ 268440723U, // ROL16m1
+ 352326803U, // ROL16mCL
+ 272635027U, // ROL16mi
+ 134222995U, // ROL16r1
+ 218109075U, // ROL16rCL
+ 138548371U, // ROL16ri
+ 402658451U, // ROL32m1
+ 486544531U, // ROL32mCL
+ 406852755U, // ROL32mi
+ 134222995U, // ROL32r1
+ 218109075U, // ROL32rCL
+ 138548371U, // ROL32ri
+ 536876179U, // ROL64m1
+ 624956563U, // ROL64mCL
+ 541070483U, // ROL64mi
+ 134222995U, // ROL64r1
+ 222303379U, // ROL64rCL
+ 138548371U, // ROL64ri
+ 671093907U, // ROL8m1
+ 754979987U, // ROL8mCL
+ 675288211U, // ROL8mi
+ 134222995U, // ROL8r1
+ 218109075U, // ROL8rCL
+ 138548371U, // ROL8ri
+ 268440728U, // ROR16m1
+ 352326808U, // ROR16mCL
+ 272635032U, // ROR16mi
+ 134223000U, // ROR16r1
+ 218109080U, // ROR16rCL
+ 138548376U, // ROR16ri
+ 402658456U, // ROR32m1
+ 486544536U, // ROR32mCL
+ 406852760U, // ROR32mi
+ 134223000U, // ROR32r1
+ 218109080U, // ROR32rCL
+ 138548376U, // ROR32ri
+ 536876184U, // ROR64m1
+ 624956568U, // ROR64mCL
+ 541070488U, // ROR64mi
+ 134223000U, // ROR64r1
+ 222303384U, // ROR64rCL
+ 138548376U, // ROR64ri
+ 671093912U, // ROR8m1
+ 754979992U, // ROR8mCL
+ 675288216U, // ROR8mi
+ 134223000U, // ROR8r1
+ 218109080U, // ROR8rCL
+ 138548376U, // ROR8ri
+ 140399773U, // ROUNDPDm_Int
+ 139875485U, // ROUNDPDr_Int
+ 140399782U, // ROUNDPSm_Int
+ 139875494U, // ROUNDPSr_Int
+ 139351215U, // ROUNDSDm_Int
+ 138564783U, // ROUNDSDr_Int
+ 139482296U, // ROUNDSSm_Int
+ 138564792U, // ROUNDSSr_Int
+ 5313U, // RSM
+ 140383429U, // RSQRTPSm
+ 140383429U, // RSQRTPSm_Int
+ 139859141U, // RSQRTPSr
+ 139859141U, // RSQRTPSr_Int
+ 140645582U, // RSQRTSSm
+ 140645582U, // RSQRTSSm_Int
+ 139859150U, // RSQRTSSr
+ 139859150U, // RSQRTSSr_Int
+ 5335U, // SAHF
+ 268440796U, // SAR16m1
+ 352326876U, // SAR16mCL
+ 272635100U, // SAR16mi
+ 134223068U, // SAR16r1
+ 218109148U, // SAR16rCL
+ 138548444U, // SAR16ri
+ 402658524U, // SAR32m1
+ 486544604U, // SAR32mCL
+ 406852828U, // SAR32mi
+ 134223068U, // SAR32r1
+ 218109148U, // SAR32rCL
+ 138548444U, // SAR32ri
+ 536876252U, // SAR64m1
+ 624956636U, // SAR64mCL
+ 541070556U, // SAR64mi
+ 134223068U, // SAR64r1
+ 222303452U, // SAR64rCL
+ 138548444U, // SAR64ri
+ 671093980U, // SAR8m1
+ 754980060U, // SAR8mCL
+ 675288284U, // SAR8mi
+ 134223068U, // SAR8r1
+ 218109148U, // SAR8rCL
+ 138548444U, // SAR8ri
+ 134223073U, // SBB16i16
+ 272635115U, // SBB16mi
+ 272635115U, // SBB16mi8
+ 272635115U, // SBB16mr
+ 138548459U, // SBB16ri
+ 138548459U, // SBB16ri8
+ 138679531U, // SBB16rm
+ 138548459U, // SBB16rr
+ 138548459U, // SBB16rr_REV
+ 134223088U, // SBB32i32
+ 406852843U, // SBB32mi
+ 406852843U, // SBB32mi8
+ 406852843U, // SBB32mr
+ 138548459U, // SBB32ri
+ 138548459U, // SBB32ri8
+ 138810603U, // SBB32rm
+ 138548459U, // SBB32rr
+ 138548459U, // SBB32rr_REV
+ 134223099U, // SBB64i32
+ 541070571U, // SBB64mi32
+ 541070571U, // SBB64mi8
+ 541070571U, // SBB64mr
+ 138548459U, // SBB64ri32
+ 138548459U, // SBB64ri8
+ 138941675U, // SBB64rm
+ 138548459U, // SBB64rr
+ 138548459U, // SBB64rr_REV
+ 134223110U, // SBB8i8
+ 675288299U, // SBB8mi
+ 675288299U, // SBB8mr
+ 138548459U, // SBB8ri
+ 139072747U, // SBB8rm
+ 138548459U, // SBB8rr
+ 138548459U, // SBB8rr_REV
+ 5392U, // SCAS16
+ 5392U, // SCAS32
+ 5392U, // SCAS64
+ 5392U, // SCAS8
+ 671094037U, // SETAEm
+ 134223125U, // SETAEr
+ 671094044U, // SETAm
+ 134223132U, // SETAr
+ 671094050U, // SETBEm
+ 134223138U, // SETBEr
+ 140776683U, // SETB_C16r
+ 140776683U, // SETB_C32r
+ 140776683U, // SETB_C64r
+ 140776683U, // SETB_C8r
+ 671094057U, // SETBm
+ 134223145U, // SETBr
+ 671094063U, // SETEm
+ 134223151U, // SETEr
+ 671094069U, // SETGEm
+ 134223157U, // SETGEr
+ 671094076U, // SETGm
+ 134223164U, // SETGr
+ 671094082U, // SETLEm
+ 134223170U, // SETLEr
+ 671094089U, // SETLm
+ 134223177U, // SETLr
+ 671094095U, // SETNEm
+ 134223183U, // SETNEr
+ 671094102U, // SETNOm
+ 134223190U, // SETNOr
+ 671094109U, // SETNPm
+ 134223197U, // SETNPr
+ 671094116U, // SETNSm
+ 134223204U, // SETNSr
+ 671094123U, // SETOm
+ 134223211U, // SETOr
+ 671094129U, // SETPm
+ 134223217U, // SETPr
+ 671094135U, // SETSm
+ 134223223U, // SETSr
+ 5501U, // SFENCE
+ 1744835972U, // SGDTm
+ 268440970U, // SHL16m1
+ 352327050U, // SHL16mCL
+ 272635274U, // SHL16mi
+ 134223242U, // SHL16r1
+ 218109322U, // SHL16rCL
+ 138548618U, // SHL16ri
+ 402658698U, // SHL32m1
+ 486544778U, // SHL32mCL
+ 406853002U, // SHL32mi
+ 134223242U, // SHL32r1
+ 218109322U, // SHL32rCL
+ 138548618U, // SHL32ri
+ 536876426U, // SHL64m1
+ 624956810U, // SHL64mCL
+ 541070730U, // SHL64mi
+ 134223242U, // SHL64r1
+ 222303626U, // SHL64rCL
+ 138548618U, // SHL64ri
+ 671094154U, // SHL8m1
+ 754980234U, // SHL8mCL
+ 675288458U, // SHL8mi
+ 134223242U, // SHL8r1
+ 218109322U, // SHL8rCL
+ 138548618U, // SHL8ri
+ 272700815U, // SHLD16mrCL
+ 272651663U, // SHLD16mri8
+ 138614159U, // SHLD16rrCL
+ 138565007U, // SHLD16rri8
+ 406918543U, // SHLD32mrCL
+ 406869391U, // SHLD32mri8
+ 138614159U, // SHLD32rrCL
+ 138565007U, // SHLD32rri8
+ 541152655U, // SHLD64mrCL
+ 541087119U, // SHLD64mri8
+ 138630543U, // SHLD64rrCL
+ 138565007U, // SHLD64rri8
+ 268440981U, // SHR16m1
+ 352327061U, // SHR16mCL
+ 272635285U, // SHR16mi
+ 134223253U, // SHR16r1
+ 218109333U, // SHR16rCL
+ 138548629U, // SHR16ri
+ 402658709U, // SHR32m1
+ 486544789U, // SHR32mCL
+ 406853013U, // SHR32mi
+ 134223253U, // SHR32r1
+ 218109333U, // SHR32rCL
+ 138548629U, // SHR32ri
+ 536876437U, // SHR64m1
+ 624956821U, // SHR64mCL
+ 541070741U, // SHR64mi
+ 134223253U, // SHR64r1
+ 222303637U, // SHR64rCL
+ 138548629U, // SHR64ri
+ 671094165U, // SHR8m1
+ 754980245U, // SHR8mCL
+ 675288469U, // SHR8mi
+ 134223253U, // SHR8r1
+ 218109333U, // SHR8rCL
+ 138548629U, // SHR8ri
+ 272700826U, // SHRD16mrCL
+ 272651674U, // SHRD16mri8
+ 138614170U, // SHRD16rrCL
+ 138565018U, // SHRD16rri8
+ 406918554U, // SHRD32mrCL
+ 406869402U, // SHRD32mri8
+ 138614170U, // SHRD32rrCL
+ 138565018U, // SHRD32rri8
+ 541152666U, // SHRD64mrCL
+ 541087130U, // SHRD64mri8
+ 138630554U, // SHRD64rrCL
+ 138565018U, // SHRD64rri8
+ 139220384U, // SHUFPDrmi
+ 138565024U, // SHUFPDrri
+ 139220392U, // SHUFPSrmi
+ 138565032U, // SHUFPSrri
+ 1744836016U, // SIDTm
+ 5558U, // SIN_F
0U, // SIN_Fp32
0U, // SIN_Fp64
0U, // SIN_Fp80
- 268441007U, // SLDT16m
- 134223279U, // SLDT16r
- 268441007U, // SLDT64m
- 134223279U, // SLDT64r
- 268441013U, // SMSW16m
- 134223285U, // SMSW16r
- 134223285U, // SMSW32r
- 134223285U, // SMSW64r
- 140383675U, // SQRTPDm
- 140383675U, // SQRTPDm_Int
- 139859387U, // SQRTPDr
- 139859387U, // SQRTPDr_Int
- 140383683U, // SQRTPSm
- 140383683U, // SQRTPSm_Int
- 139859395U, // SQRTPSr
- 139859395U, // SQRTPSr_Int
- 140514763U, // SQRTSDm
- 140514763U, // SQRTSDm_Int
- 139859403U, // SQRTSDr
- 139859403U, // SQRTSDr_Int
- 140645843U, // SQRTSSm
- 140645843U, // SQRTSSm_Int
- 139859411U, // SQRTSSr
- 139859411U, // SQRTSSr_Int
- 5595U, // SQRT_F
+ 268441019U, // SLDT16m
+ 134223291U, // SLDT16r
+ 268441019U, // SLDT64m
+ 134223291U, // SLDT64r
+ 268441025U, // SMSW16m
+ 134223297U, // SMSW16r
+ 134223297U, // SMSW32r
+ 134223297U, // SMSW64r
+ 140383687U, // SQRTPDm
+ 140383687U, // SQRTPDm_Int
+ 139859399U, // SQRTPDr
+ 139859399U, // SQRTPDr_Int
+ 140383695U, // SQRTPSm
+ 140383695U, // SQRTPSm_Int
+ 139859407U, // SQRTPSr
+ 139859407U, // SQRTPSr_Int
+ 140514775U, // SQRTSDm
+ 140514775U, // SQRTSDm_Int
+ 139859415U, // SQRTSDr
+ 139859415U, // SQRTSDr_Int
+ 140645855U, // SQRTSSm
+ 140645855U, // SQRTSSm_Int
+ 139859423U, // SQRTSSr
+ 139859423U, // SQRTSSr_Int
+ 5607U, // SQRT_F
0U, // SQRT_Fp32
0U, // SQRT_Fp64
0U, // SQRT_Fp80
- 5601U, // STC
- 5605U, // STD
- 5609U, // STI
- 402658797U, // STMXCSR
- 5622U, // STRm
- 5622U, // STRr
- 805311995U, // ST_F32m
- 939529723U, // ST_F64m
- 805312000U, // ST_FP32m
- 939529728U, // ST_FP64m
- 2147489280U, // ST_FP80m
- 134223360U, // ST_FPrr
+ 5613U, // STC
+ 5617U, // STD
+ 5621U, // STI
+ 402658809U, // STMXCSR
+ 5634U, // STRm
+ 5634U, // STRr
+ 805312007U, // ST_F32m
+ 939529735U, // ST_F64m
+ 805312012U, // ST_FP32m
+ 939529740U, // ST_FP64m
+ 2147489292U, // ST_FP80m
+ 134223372U, // ST_FPrr
0U, // ST_Fp32m
0U, // ST_Fp64m
0U, // ST_Fp64m32
@@ -2286,51 +2289,51 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ST_FpP80m
0U, // ST_FpP80m32
0U, // ST_FpP80m64
- 134223355U, // ST_Frr
- 134223366U, // SUB16i16
- 272635408U, // SUB16mi
- 272635408U, // SUB16mi8
- 272635408U, // SUB16mr
- 138548752U, // SUB16ri
- 138548752U, // SUB16ri8
- 138679824U, // SUB16rm
- 138548752U, // SUB16rr
- 138548752U, // SUB16rr_REV
- 134223381U, // SUB32i32
- 406853136U, // SUB32mi
- 406853136U, // SUB32mi8
- 406853136U, // SUB32mr
- 138548752U, // SUB32ri
- 138548752U, // SUB32ri8
- 138810896U, // SUB32rm
- 138548752U, // SUB32rr
- 138548752U, // SUB32rr_REV
- 134223392U, // SUB64i32
- 541070864U, // SUB64mi32
- 541070864U, // SUB64mi8
- 541070864U, // SUB64mr
- 138548752U, // SUB64ri32
- 138548752U, // SUB64ri8
- 138941968U, // SUB64rm
- 138548752U, // SUB64rr
- 138548752U, // SUB64rr_REV
- 134223403U, // SUB8i8
- 675288592U, // SUB8mi
- 675288592U, // SUB8mr
- 138548752U, // SUB8ri
- 139073040U, // SUB8rm
- 138548752U, // SUB8rr
- 138548752U, // SUB8rr_REV
- 139204149U, // SUBPDrm
- 138548789U, // SUBPDrr
- 139204156U, // SUBPSrm
- 138548796U, // SUBPSrr
- 805312067U, // SUBR_F32m
- 939529795U, // SUBR_F64m
- 268441162U, // SUBR_FI16m
- 402658890U, // SUBR_FI32m
- 134223442U, // SUBR_FPrST0
- 134223427U, // SUBR_FST0r
+ 134223367U, // ST_Frr
+ 134223378U, // SUB16i16
+ 272635420U, // SUB16mi
+ 272635420U, // SUB16mi8
+ 272635420U, // SUB16mr
+ 138548764U, // SUB16ri
+ 138548764U, // SUB16ri8
+ 138679836U, // SUB16rm
+ 138548764U, // SUB16rr
+ 138548764U, // SUB16rr_REV
+ 134223393U, // SUB32i32
+ 406853148U, // SUB32mi
+ 406853148U, // SUB32mi8
+ 406853148U, // SUB32mr
+ 138548764U, // SUB32ri
+ 138548764U, // SUB32ri8
+ 138810908U, // SUB32rm
+ 138548764U, // SUB32rr
+ 138548764U, // SUB32rr_REV
+ 134223404U, // SUB64i32
+ 541070876U, // SUB64mi32
+ 541070876U, // SUB64mi8
+ 541070876U, // SUB64mr
+ 138548764U, // SUB64ri32
+ 138548764U, // SUB64ri8
+ 138941980U, // SUB64rm
+ 138548764U, // SUB64rr
+ 138548764U, // SUB64rr_REV
+ 134223415U, // SUB8i8
+ 675288604U, // SUB8mi
+ 675288604U, // SUB8mr
+ 138548764U, // SUB8ri
+ 139073052U, // SUB8rm
+ 138548764U, // SUB8rr
+ 138548764U, // SUB8rr_REV
+ 139204161U, // SUBPDrm
+ 138548801U, // SUBPDrr
+ 139204168U, // SUBPSrm
+ 138548808U, // SUBPSrr
+ 805312079U, // SUBR_F32m
+ 939529807U, // SUBR_F64m
+ 268441174U, // SUBR_FI16m
+ 402658902U, // SUBR_FI32m
+ 134223454U, // SUBR_FPrST0
+ 134223439U, // SUBR_FST0r
0U, // SUBR_Fp32m
0U, // SUBR_Fp64m
0U, // SUBR_Fp64m32
@@ -2342,21 +2345,21 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // SUBR_FpI32m32
0U, // SUBR_FpI32m64
0U, // SUBR_FpI32m80
- 142612035U, // SUBR_FrST0
- 139335258U, // SUBSDrm
- 139335258U, // SUBSDrm_Int
- 138548826U, // SUBSDrr
- 138548826U, // SUBSDrr_Int
- 139466337U, // SUBSSrm
- 139466337U, // SUBSSrm_Int
- 138548833U, // SUBSSrr
- 138548833U, // SUBSSrr_Int
- 805312104U, // SUB_F32m
- 939529832U, // SUB_F64m
- 268441198U, // SUB_FI16m
- 402658926U, // SUB_FI32m
- 134223477U, // SUB_FPrST0
- 134223464U, // SUB_FST0r
+ 142612047U, // SUBR_FrST0
+ 139335270U, // SUBSDrm
+ 139335270U, // SUBSDrm_Int
+ 138548838U, // SUBSDrr
+ 138548838U, // SUBSDrr_Int
+ 139466349U, // SUBSSrm
+ 139466349U, // SUBSSrm_Int
+ 138548845U, // SUBSSrr
+ 138548845U, // SUBSSrr_Int
+ 805312116U, // SUB_F32m
+ 939529844U, // SUB_F64m
+ 268441210U, // SUB_FI16m
+ 402658938U, // SUB_FI32m
+ 134223489U, // SUB_FPrST0
+ 134223476U, // SUB_FST0r
0U, // SUB_Fp32
0U, // SUB_Fp32m
0U, // SUB_Fp64
@@ -2371,286 +2374,287 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // SUB_FpI32m32
0U, // SUB_FpI32m64
0U, // SUB_FpI32m80
- 142612072U, // SUB_FrST0
- 5756U, // SWPGS
- 5762U, // SYSCALL
- 5770U, // SYSENTER
- 5779U, // SYSEXIT
- 5779U, // SYSEXIT64
- 5787U, // SYSRET
- 1166019449U, // TAILJMPd
- 494930809U, // TAILJMPm
- 226495353U, // TAILJMPr
- 226495353U, // TAILJMPr64
- 230692514U, // TCRETURNdi
- 230692514U, // TCRETURNdi64
- 230692514U, // TCRETURNri
- 230692514U, // TCRETURNri64
- 134223534U, // TEST16i16
- 272635577U, // TEST16mi
- 139859641U, // TEST16ri
- 139728569U, // TEST16rm
- 139859641U, // TEST16rr
- 134223551U, // TEST32i32
- 406853305U, // TEST32mi
- 139859641U, // TEST32ri
- 139990713U, // TEST32rm
- 139859641U, // TEST32rr
- 134223563U, // TEST64i32
- 541071033U, // TEST64mi32
- 139859641U, // TEST64ri32
- 140121785U, // TEST64rm
- 139859641U, // TEST64rr
- 134223575U, // TEST8i8
- 675288761U, // TEST8mi
- 139859641U, // TEST8ri
- 140252857U, // TEST8rm
- 139859641U, // TEST8rr
- 2952795874U, // TLS_addr32
- 3087013608U, // TLS_addr64
- 5882U, // TRAP
- 5886U, // TST_F
+ 142612084U, // SUB_FrST0
+ 5768U, // SWPGS
+ 5774U, // SYSCALL
+ 5782U, // SYSENTER
+ 5791U, // SYSEXIT
+ 5791U, // SYSEXIT64
+ 5799U, // SYSRET
+ 1166019461U, // TAILJMPd
+ 494930821U, // TAILJMPm
+ 226495365U, // TAILJMPr
+ 226495365U, // TAILJMPr64
+ 230692526U, // TCRETURNdi
+ 230692526U, // TCRETURNdi64
+ 230692526U, // TCRETURNri
+ 230692526U, // TCRETURNri64
+ 134223546U, // TEST16i16
+ 272635589U, // TEST16mi
+ 139859653U, // TEST16ri
+ 139728581U, // TEST16rm
+ 139859653U, // TEST16rr
+ 134223563U, // TEST32i32
+ 406853317U, // TEST32mi
+ 139859653U, // TEST32ri
+ 139990725U, // TEST32rm
+ 139859653U, // TEST32rr
+ 134223575U, // TEST64i32
+ 541071045U, // TEST64mi32
+ 139859653U, // TEST64ri32
+ 140121797U, // TEST64rm
+ 139859653U, // TEST64rr
+ 134223587U, // TEST8i8
+ 675288773U, // TEST8mi
+ 139859653U, // TEST8ri
+ 140252869U, // TEST8rm
+ 139859653U, // TEST8rr
+ 2952795886U, // TLS_addr32
+ 3087013620U, // TLS_addr64
+ 5894U, // TRAP
+ 5898U, // TST_F
0U, // TST_Fp32
0U, // TST_Fp64
0U, // TST_Fp80
- 140512057U, // UCOMISDrm
- 139856697U, // UCOMISDrr
- 140643138U, // UCOMISSrm
- 139856706U, // UCOMISSrr
- 134223619U, // UCOM_FIPr
- 134223636U, // UCOM_FIr
- 5924U, // UCOM_FPPr
- 134223660U, // UCOM_FPr
+ 140512069U, // UCOMISDrm
+ 139856709U, // UCOMISDrr
+ 140643150U, // UCOMISSrm
+ 139856718U, // UCOMISSrr
+ 134223631U, // UCOM_FIPr
+ 134223648U, // UCOM_FIr
+ 5936U, // UCOM_FPPr
+ 134223672U, // UCOM_FPr
0U, // UCOM_FpIr32
0U, // UCOM_FpIr64
0U, // UCOM_FpIr80
0U, // UCOM_Fpr32
0U, // UCOM_Fpr64
0U, // UCOM_Fpr80
- 134223668U, // UCOM_Fr
- 139204411U, // UNPCKHPDrm
- 138549051U, // UNPCKHPDrr
- 139204421U, // UNPCKHPSrm
- 138549061U, // UNPCKHPSrr
- 139204431U, // UNPCKLPDrm
- 138549071U, // UNPCKLPDrr
- 139204441U, // UNPCKLPSrm
- 138549081U, // UNPCKLPSrr
- 139876195U, // VASTART_SAVE_XMM_REGS
- 268441467U, // VERRm
- 134223739U, // VERRr
- 268441473U, // VERWm
- 134223745U, // VERWr
- 6023U, // VMCALL
- 536876942U, // VMCLEARm
- 6039U, // VMLAUNCH
- 536876960U, // VMPTRLDm
- 536876969U, // VMPTRSTm
- 406853554U, // VMREAD32rm
- 139859890U, // VMREAD32rr
- 541071282U, // VMREAD64rm
- 139859890U, // VMREAD64rr
- 6074U, // VMRESUME
- 139990979U, // VMWRITE32rm
- 139859907U, // VMWRITE32rr
- 140122051U, // VMWRITE64rm
- 139859907U, // VMWRITE64rr
- 6092U, // VMXOFF
- 6099U, // VMXON
- 140773917U, // V_SET0
- 140774842U, // V_SETALLONES
- 6106U, // WAIT
- 6111U, // WBINVD
- 536871947U, // WINCALL64m
- 1073742859U, // WINCALL64pcrel32
- 134218763U, // WINCALL64r
- 6118U, // WRMSR
- 272635884U, // XADD16rm
- 139859948U, // XADD16rr
- 406853612U, // XADD32rm
- 139859948U, // XADD32rr
- 541071340U, // XADD64rm
- 139859948U, // XADD64rr
- 675289068U, // XADD8rm
- 139859948U, // XADD8rr
- 134223858U, // XCHG16ar
- 2281707517U, // XCHG16rm
- 3221231613U, // XCHG16rr
- 134223875U, // XCHG32ar
- 2415925245U, // XCHG32rm
- 3221231613U, // XCHG32rr
- 134223887U, // XCHG64ar
- 3355449341U, // XCHG64rm
- 3221231613U, // XCHG64rr
- 2550142973U, // XCHG8rm
- 3221231613U, // XCHG8rr
- 134223899U, // XCH_F
- 6177U, // XLAT
- 134223911U, // XOR16i16
- 272633659U, // XOR16mi
- 272633659U, // XOR16mi8
- 272633659U, // XOR16mr
- 138547003U, // XOR16ri
- 138547003U, // XOR16ri8
- 138678075U, // XOR16rm
- 138547003U, // XOR16rr
- 138547003U, // XOR16rr_REV
- 134223921U, // XOR32i32
- 406851387U, // XOR32mi
- 406851387U, // XOR32mi8
- 406851387U, // XOR32mr
- 138547003U, // XOR32ri
- 138547003U, // XOR32ri8
- 138809147U, // XOR32rm
- 138547003U, // XOR32rr
- 138547003U, // XOR32rr_REV
- 134223932U, // XOR64i32
- 541069115U, // XOR64mi32
- 541069115U, // XOR64mi8
- 541069115U, // XOR64mr
- 138547003U, // XOR64ri32
- 138547003U, // XOR64ri8
- 138940219U, // XOR64rm
- 138547003U, // XOR64rr
- 138547003U, // XOR64rr_REV
- 134223943U, // XOR8i8
- 675286843U, // XOR8mi
- 675286843U, // XOR8mr
- 138547003U, // XOR8ri
- 139071291U, // XOR8rm
- 138547003U, // XOR8rr
- 138547003U, // XOR8rr_REV
- 139201046U, // XORPDrm
- 138545686U, // XORPDrr
- 139201053U, // XORPSrm
- 138545693U, // XORPSrr
+ 134223680U, // UCOM_Fr
+ 139204423U, // UNPCKHPDrm
+ 138549063U, // UNPCKHPDrr
+ 139204433U, // UNPCKHPSrm
+ 138549073U, // UNPCKHPSrr
+ 139204443U, // UNPCKLPDrm
+ 138549083U, // UNPCKLPDrr
+ 139204453U, // UNPCKLPSrm
+ 138549093U, // UNPCKLPSrr
+ 139876207U, // VASTART_SAVE_XMM_REGS
+ 268441479U, // VERRm
+ 134223751U, // VERRr
+ 268441485U, // VERWm
+ 134223757U, // VERWr
+ 6035U, // VMCALL
+ 536876954U, // VMCLEARm
+ 6051U, // VMLAUNCH
+ 536876972U, // VMPTRLDm
+ 536876981U, // VMPTRSTm
+ 406853566U, // VMREAD32rm
+ 139859902U, // VMREAD32rr
+ 541071294U, // VMREAD64rm
+ 139859902U, // VMREAD64rr
+ 6086U, // VMRESUME
+ 139990991U, // VMWRITE32rm
+ 139859919U, // VMWRITE32rr
+ 140122063U, // VMWRITE64rm
+ 139859919U, // VMWRITE64rr
+ 6104U, // VMXOFF
+ 6111U, // VMXON
+ 140773929U, // V_SET0
+ 140774854U, // V_SETALLONES
+ 6118U, // WAIT
+ 6123U, // WBINVD
+ 536871959U, // WINCALL64m
+ 1073742871U, // WINCALL64pcrel32
+ 134218775U, // WINCALL64r
+ 6130U, // WRMSR
+ 272635896U, // XADD16rm
+ 139859960U, // XADD16rr
+ 406853624U, // XADD32rm
+ 139859960U, // XADD32rr
+ 541071352U, // XADD64rm
+ 139859960U, // XADD64rr
+ 675289080U, // XADD8rm
+ 139859960U, // XADD8rr
+ 134223870U, // XCHG16ar
+ 2281707529U, // XCHG16rm
+ 3221231625U, // XCHG16rr
+ 134223887U, // XCHG32ar
+ 2415925257U, // XCHG32rm
+ 3221231625U, // XCHG32rr
+ 134223899U, // XCHG64ar
+ 3355449353U, // XCHG64rm
+ 3221231625U, // XCHG64rr
+ 2550142985U, // XCHG8rm
+ 3221231625U, // XCHG8rr
+ 134223911U, // XCH_F
+ 6189U, // XLAT
+ 134223923U, // XOR16i16
+ 272633671U, // XOR16mi
+ 272633671U, // XOR16mi8
+ 272633671U, // XOR16mr
+ 138547015U, // XOR16ri
+ 138547015U, // XOR16ri8
+ 138678087U, // XOR16rm
+ 138547015U, // XOR16rr
+ 138547015U, // XOR16rr_REV
+ 134223933U, // XOR32i32
+ 406851399U, // XOR32mi
+ 406851399U, // XOR32mi8
+ 406851399U, // XOR32mr
+ 138547015U, // XOR32ri
+ 138547015U, // XOR32ri8
+ 138809159U, // XOR32rm
+ 138547015U, // XOR32rr
+ 138547015U, // XOR32rr_REV
+ 134223944U, // XOR64i32
+ 541069127U, // XOR64mi32
+ 541069127U, // XOR64mi8
+ 541069127U, // XOR64mr
+ 138547015U, // XOR64ri32
+ 138547015U, // XOR64ri8
+ 138940231U, // XOR64rm
+ 138547015U, // XOR64rr
+ 138547015U, // XOR64rr_REV
+ 134223955U, // XOR8i8
+ 675286855U, // XOR8mi
+ 675286855U, // XOR8mr
+ 138547015U, // XOR8ri
+ 139071303U, // XOR8rm
+ 138547015U, // XOR8rr
+ 138547015U, // XOR8rr_REV
+ 139201058U, // XORPDrm
+ 138545698U, // XORPDrr
+ 139201065U, // XORPSrm
+ 138545705U, // XORPSrr
0U
};
const char *AsmStrs =
- "fabs\000adc\t%ax, \000adc\t\000adc\t%eax, \000adc\t%rax, \000adc\t%al, "
- "\000add\t%ax, \000add\t\000add\t%eax, \000add\t%rax, \000add\t%al, \000"
- "addpd\t\000addps\t\000addsd\t\000addss\t\000addsubpd\t\000addsubps\t\000"
- "fadd\t\000fiadd\t\000faddp\t\000#ADJCALLSTACKDOWN\000#ADJCALLSTACKUP\000"
- "and\t%ax, \000and\t\000and\t%eax, \000and\t%rax, \000and\t%al, \000andn"
- "pd\t\000andnps\t\000andpd\t\000andps\t\000#ATOMADD6432 PSEUDO!\000#ATOM"
- "AND16 PSEUDO!\000#ATOMAND32 PSEUDO!\000#ATOMAND64 PSEUDO!\000#ATOMAND64"
- "32 PSEUDO!\000#ATOMAND8 PSEUDO!\000#ATOMMAX16 PSEUDO!\000#ATOMMAX32 PSE"
- "UDO!\000#ATOMMAX64 PSEUDO!\000#ATOMMIN16 PSEUDO!\000#ATOMMIN32 PSEUDO!\000"
- "#ATOMMIN64 PSEUDO!\000#ATOMNAND16 PSEUDO!\000#ATOMNAND32 PSEUDO!\000#AT"
- "OMNAND64 PSEUDO!\000#ATOMNAND6432 PSEUDO!\000#ATOMNAND8 PSEUDO!\000#ATO"
- "MOR16 PSEUDO!\000#ATOMOR32 PSEUDO!\000#ATOMOR64 PSEUDO!\000#ATOMOR6432 "
- "PSEUDO!\000#ATOMOR8 PSEUDO!\000#ATOMSUB6432 PSEUDO!\000#ATOMSWAP6432 PS"
- "EUDO!\000#ATOMUMAX16 PSEUDO!\000#ATOMUMAX32 PSEUDO!\000#ATOMUMAX64 PSEU"
- "DO!\000#ATOMUMIN16 PSEUDO!\000#ATOMUMIN32 PSEUDO!\000#ATOMUMIN64 PSEUDO"
- "!\000#ATOMXOR16 PSEUDO!\000#ATOMXOR32 PSEUDO!\000#ATOMXOR64 PSEUDO!\000"
- "#ATOMXOR6432 PSEUDO!\000#ATOMXOR8 PSEUDO!\000blendpd\t\000blendps\t\000"
- "blendvpd\t\000blendvps\t\000bsf\t\000bsr\t\000bswap\t\000bt\t\000btc\t\000"
- "btr\t\000bts\t\000call\t\000cbw\000cdq\000cdqe\000fchs\000clc\000cld\000"
- "clflush\t\000cli\000clts\000cmc\000cmova\t\000cmovae\t\000cmovb\t\000cm"
- "ovbe\t\000fcmovbe\t%ST(0), \000fcmovb\t%ST(0), \000cmove\t\000fcmove\t%"
- "ST(0), \000cmovg\t\000cmovge\t\000cmovl\t\000cmovle\t\000fcmovnbe\t%ST("
- "0), \000fcmovnb\t%ST(0), \000cmovne\t\000fcmovne\t%ST(0), \000cmovno\t\000"
- "cmovnp\t\000fcmovnu\t%ST(0), \000cmovns\t\000cmovo\t\000cmovp\t\000fcmo"
- "vu\t %ST(0), \000cmovs\t\000#CMOV_FR32 PSEUDO!\000#CMOV_FR64 PSEUDO!\000"
- "#CMOV_GR8 PSEUDO!\000#CMOV_V1I64 PSEUDO!\000#CMOV_V2F64 PSEUDO!\000#CMO"
- "V_V2I64 PSEUDO!\000#CMOV_V4F32 PSEUDO!\000cmp\t%ax, \000cmp\t\000cmp\t%"
- "eax, \000cmp\t%rax, \000cmp\t%al, \000cmp\000cmps\000cmpxchg16b\t\000cm"
- "pxchg\t\000cmpxchg8b\t\000comisd\t\000comiss\t\000fcomp\t\000fcomip\t%S"
- "T(0), \000fcomi\t%ST(0), \000fcom\t\000fcos\000cpuid\000cqo\000crc32 \t"
- "\000cvtdq2pd\t\000cvtdq2ps\t\000cvtpd2dq\t\000cvtpd2ps\t\000cvtps2dq\t\000"
- "cvtps2pd\t\000cvtsd2si\t\000cvtsd2ss\t\000cvtsi2sd\t\000cvtsi2ss\t\000c"
- "vtss2sd\t\000cvtss2si\t\000cvttps2dq\t\000cvttsd2si\t\000cvttss2si\t\000"
- "cwd\000cwde\000dec\t\000div\t\000divpd\t\000divps\t\000fdivr\t\000fidiv"
- "r\t\000fdivrp\t\000divsd\t\000divss\t\000fdiv\t\000fidiv\t\000fdivp\t\000"
- "dppd\t\000dpps\t\000ret\t#eh_return, addr: \000enter\t\000extractps\t\000"
- "f2xm1\000lcall\t\000ljmp\t\000fbld\t\000fbstp\t\000fcompp\000fdecstp\000"
- "ffree\t\000ficom\t\000ficomp\t\000fincstp\000fisttp\t\000fldcw\t\000fld"
- "env\t\000fldl2e\000fldl2t\000fldlg2\000fldln2\000fldpi\000fnclex\000fni"
- "nit\000fnop\000fnstcw\t\000fnstsw %ax\000fnstsw\t\000##FP32_TO_INT16_IN"
- "_MEM PSEUDO!\000##FP32_TO_INT32_IN_MEM PSEUDO!\000##FP32_TO_INT64_IN_ME"
- "M PSEUDO!\000##FP64_TO_INT16_IN_MEM PSEUDO!\000##FP64_TO_INT32_IN_MEM P"
- "SEUDO!\000##FP64_TO_INT64_IN_MEM PSEUDO!\000##FP80_TO_INT16_IN_MEM PSEU"
- "DO!\000##FP80_TO_INT32_IN_MEM PSEUDO!\000##FP80_TO_INT64_IN_MEM PSEUDO!"
- "\000fpatan\000fprem\000fprem1\000fptan\000##FP_REG_KILL\000frndint\000f"
- "rstor\t\000fnsave\t\000fscale\000fsincos\000fnstenv\t\000movl\t%fs:\000"
- "fxam\000fxrstor\t\000fxsave\t\000fxtract\000fyl2x\000fyl2xp1\000pxor\t\000"
- "movapd\t\000movaps\t\000orpd\t\000orps\t\000xorpd\t\000xorps\t\000movl\t"
- "%gs:\000haddpd\t\000haddps\t\000hlt\000hsubpd\t\000hsubps\t\000idiv\t\000"
- "fild\t\000imul\t\000ins\000in\t%AX, \000in\t%AX, %DX\000in\t%EAX, \000i"
- "n\t%EAX, %DX\000in\t%AL, \000in\t%AL, %DX\000inc\t\000insertps\t\000int"
- "\t\000int\t3\000invd\000invept\000invlpg\000invvpid\000iret\000fist\t\000"
- "fistp\t\000cvtpd2pi\t\000cvtpi2pd\t\000cvtpi2ps\t\000cvtps2pi\t\000cvtt"
- "pd2dq\t\000cvttpd2pi\t\000cvttps2pi\t\000ucomisd\t\000ucomiss\t\000ja\t"
- "\000jae\t\000jb\t\000jbe\t\000jcxz\t\000je\t\000jg\t\000jge\t\000jl\t\000"
- "jle\t\000jmp\t\000jne\t\000jno\t\000jnp\t\000jns\t\000jo\t\000jp\t\000j"
- "s\t\000lahf\000lar\t\000lock\n\tcmpxchg\t\000lock\n\tcmpxchgq\t\000lock"
- "\n\tcmpxchg8b\t\000lddqu\t\000ldmxcsr\t\000lds\t\000fldz\000fld1\000fld"
- "\t\000lea\t\000leave\000les\t\000lfence\000lfs\t\000lgdt\t\000lgs\t\000"
- "lidt\t\000lldt\t\000lmsw\t\000lock\n\tadd\t\000lock\n\tdec\t\000lock\n\t"
- "inc\t\000lock\n\tsub\t\000lodsb\000lodsd\000lodsq\000lodsw\000loop\t\000"
- "loope\t\000loopne\t\000lret\000lret\t\000lsl\t\000lss\t\000ltr\t\000loc"
- "k\n\txadd\t\000maskmovdqu\t\000maxpd\t\000maxps\t\000maxsd\t\000maxss\t"
- "\000mfence\000minpd\t\000minps\t\000minsd\t\000minss\t\000emms\000femms"
- "\000maskmovq\t\000movd\t\000movdq2q\t\000movntq\t\000movq2dq\t\000movq\t"
- "\000packssdw\t\000packsswb\t\000packuswb\t\000paddb\t\000paddd\t\000pad"
- "dq\t\000paddsb\t\000paddsw\t\000paddusb\t\000paddusw\t\000paddw\t\000pa"
- "ndn\t\000pand\t\000pavgb\t\000pavgw\t\000pcmpeqb\t\000pcmpeqd\t\000pcmp"
- "eqw\t\000pcmpgtb\t\000pcmpgtd\t\000pcmpgtw\t\000pextrw\t\000pinsrw\t\000"
- "pmaddwd\t\000pmaxsw\t\000pmaxub\t\000pminsw\t\000pminub\t\000pmovmskb\t"
- "\000pmulhuw\t\000pmulhw\t\000pmullw\t\000pmuludq\t\000por\t\000psadbw\t"
- "\000pshufw\t\000pslld\t\000psllq\t\000psllw\t\000psrad\t\000psraw\t\000"
- "psrld\t\000psrlq\t\000psrlw\t\000psubb\t\000psubd\t\000psubq\t\000psubs"
- "b\t\000psubsw\t\000psubusb\t\000psubusw\t\000psubw\t\000punpckhbw\t\000"
- "punpckhdq\t\000punpckhwd\t\000punpcklbw\t\000punpckldq\t\000punpcklwd\t"
- "\000monitor\000mov\t\000mov\t%ax, \000mov\t%eax, \000xor\t\000movq\t%fs"
- ":\000movq\t%gs:\000mov\t%rax, \000movabs\t\000mov\t%al, \000movddup\t\000"
- "movdqa\t\000movdqu\t\000movhlps\t\000movhpd\t\000movhps\t\000movlhps\t\000"
- "movlpd\t\000movsd\t\000movlps\t\000movss\t\000movmskpd\t\000movmskps\t\000"
- "movntdqa\t\000movntdq\t\000movnti\t\000movntpd\t\000movntps\t\000movshd"
- "up\t\000movsldup\t\000movsx\t\000movsxd\t\000movupd\t\000movups\t\000mo"
- "vzx\t\000mpsadbw\t\000mul\t\000mulpd\t\000mulps\t\000mulsd\t\000mulss\t"
- "\000fmul\t\000fimul\t\000fmulp\t\000mwait\000neg\t\000nop\000nop\t\000n"
- "ot\t\000or\t%ax, \000or\t\000or\t%eax, \000or\t%rax, \000or\t%al, \000o"
- "ut\t\000out\t%DX, %AX\000out\t%DX, %EAX\000out\t%DX, %AL\000outsb\000ou"
- "tsd\000outsw\000pabsb\t\000pabsd\t\000pabsw\t\000packusdw\t\000palignr\t"
- "\000pblendvb\t\000pblendw\t\000pcmpeqq\t\000pcmpestri\t\000#PCMPESTRM12"
- "8rm PSEUDO!\000#PCMPESTRM128rr PSEUDO!\000pcmpestrm\t\000pcmpgtq\t\000p"
- "cmpistri\t\000#PCMPISTRM128rm PSEUDO!\000#PCMPISTRM128rr PSEUDO!\000pcm"
- "pistrm\t\000pextrb\t\000pextrd\t\000pextrq\t\000phaddd\t\000phaddsw\t\000"
- "phaddw\t\000phminposuw\t\000phsubd\t\000phsubsw\t\000phsubw\t\000pinsrb"
- "\t\000pinsrd\t\000pinsrq\t\000pmaddubsw\t\000pmaxsb\t\000pmaxsd\t\000pm"
- "axud\t\000pmaxuw\t\000pminsb\t\000pminsd\t\000pminud\t\000pminuw\t\000p"
- "movsxbd\t\000pmovsxbq\t\000pmovsxbw\t\000pmovsxdq\t\000pmovsxwd\t\000pm"
- "ovsxwq\t\000pmovzxbd\t\000pmovzxbq\t\000pmovzxbw\t\000pmovzxdq\t\000pmo"
- "vzxwd\t\000pmovzxwq\t\000pmuldq\t\000pmulhrsw\t\000pmulld\t\000pop\t\000"
- "popcnt\t\000popf\000pop\t%fs\000pop\t%gs\000prefetchnta\t\000prefetcht0"
- "\t\000prefetcht1\t\000prefetcht2\t\000pshufb\t\000pshufd\t\000pshufhw\t"
- "\000pshuflw\t\000psignb\t\000psignd\t\000psignw\t\000pslldq\t\000psrldq"
- "\t\000ptest \t\000punpckhqdq\t\000punpcklqdq\t\000push\t\000pushf\000pu"
- "sh\t%fs\000push\t%gs\000rcl\t\000rcpps\t\000rcpss\t\000rcr\t\000rdmsr\000"
- "rdpmc\000rdtsc\000rep movsb\000rep movsd\000rep movsq\000rep movsw\000r"
- "ep stosb\000rep stosd\000rep stosq\000rep stosw\000ret\000ret\t\000rol\t"
- "\000ror\t\000roundpd\t\000roundps\t\000roundsd\t\000roundss\t\000rsm\000"
- "rsqrtps\t\000rsqrtss\t\000sahf\000sar\t\000sbb\t%ax, \000sbb\t\000sbb\t"
- "%eax, \000sbb\t%rax, \000sbb\t%al, \000scas\000setae\t\000seta\t\000set"
- "be\t\000setb\t\000sete\t\000setge\t\000setg\t\000setle\t\000setl\t\000s"
- "etne\t\000setno\t\000setnp\t\000setns\t\000seto\t\000setp\t\000sets\t\000"
- "sfence\000sgdt\t\000shl\t\000shld\t\000shr\t\000shrd\t\000shufpd\t\000s"
- "hufps\t\000sidt\t\000fsin\000sldt\t\000smsw\t\000sqrtpd\t\000sqrtps\t\000"
- "sqrtsd\t\000sqrtss\t\000fsqrt\000stc\000std\000sti\000stmxcsr\t\000str\t"
- "\000fst\t\000fstp\t\000sub\t%ax, \000sub\t\000sub\t%eax, \000sub\t%rax,"
- " \000sub\t%al, \000subpd\t\000subps\t\000fsubr\t\000fisubr\t\000fsubrp\t"
- "\000subsd\t\000subss\t\000fsub\t\000fisub\t\000fsubp\t\000swpgs\000sysc"
- "all\000sysenter\000sysexit\000sysret\000#TC_RETURN \000test\t%ax, \000t"
- "est\t\000test\t%eax, \000test\t%rax, \000test\t%al, \000leal\t\000.byte"
- "\t0x66; leaq\t\000ud2\000ftst\000fucomip\t%ST(0), \000fucomi\t%ST(0), \000"
- "fucompp\000fucomp\t\000fucom\t\000unpckhpd\t\000unpckhps\t\000unpcklpd\t"
- "\000unpcklps\t\000#VASTART_SAVE_XMM_REGS \000verr\t\000verw\t\000vmcall"
- "\000vmclear\t\000vmlaunch\000vmptrld\t\000vmptrst\t\000vmread\t\000vmre"
- "sume\000vmwrite\t\000vmxoff\000vmxon\t\000wait\000wbinvd\000wrmsr\000xa"
- "dd\t\000xchg\t%ax, \000xchg\t\000xchg\t%eax, \000xchg\t%rax, \000fxch\t"
- "\000xlatb\000xor\t%ax, \000xor\t%eax, \000xor\t%rax, \000xor\t%al, \000";
+ "DEBUG_VALUE\000fabs\000adc\t%ax, \000adc\t\000adc\t%eax, \000adc\t%rax,"
+ " \000adc\t%al, \000add\t%ax, \000add\t\000add\t%eax, \000add\t%rax, \000"
+ "add\t%al, \000addpd\t\000addps\t\000addsd\t\000addss\t\000addsubpd\t\000"
+ "addsubps\t\000fadd\t\000fiadd\t\000faddp\t\000#ADJCALLSTACKDOWN\000#ADJ"
+ "CALLSTACKUP\000and\t%ax, \000and\t\000and\t%eax, \000and\t%rax, \000and"
+ "\t%al, \000andnpd\t\000andnps\t\000andpd\t\000andps\t\000#ATOMADD6432 P"
+ "SEUDO!\000#ATOMAND16 PSEUDO!\000#ATOMAND32 PSEUDO!\000#ATOMAND64 PSEUDO"
+ "!\000#ATOMAND6432 PSEUDO!\000#ATOMAND8 PSEUDO!\000#ATOMMAX16 PSEUDO!\000"
+ "#ATOMMAX32 PSEUDO!\000#ATOMMAX64 PSEUDO!\000#ATOMMIN16 PSEUDO!\000#ATOM"
+ "MIN32 PSEUDO!\000#ATOMMIN64 PSEUDO!\000#ATOMNAND16 PSEUDO!\000#ATOMNAND"
+ "32 PSEUDO!\000#ATOMNAND64 PSEUDO!\000#ATOMNAND6432 PSEUDO!\000#ATOMNAND"
+ "8 PSEUDO!\000#ATOMOR16 PSEUDO!\000#ATOMOR32 PSEUDO!\000#ATOMOR64 PSEUDO"
+ "!\000#ATOMOR6432 PSEUDO!\000#ATOMOR8 PSEUDO!\000#ATOMSUB6432 PSEUDO!\000"
+ "#ATOMSWAP6432 PSEUDO!\000#ATOMUMAX16 PSEUDO!\000#ATOMUMAX32 PSEUDO!\000"
+ "#ATOMUMAX64 PSEUDO!\000#ATOMUMIN16 PSEUDO!\000#ATOMUMIN32 PSEUDO!\000#A"
+ "TOMUMIN64 PSEUDO!\000#ATOMXOR16 PSEUDO!\000#ATOMXOR32 PSEUDO!\000#ATOMX"
+ "OR64 PSEUDO!\000#ATOMXOR6432 PSEUDO!\000#ATOMXOR8 PSEUDO!\000blendpd\t\000"
+ "blendps\t\000blendvpd\t\000blendvps\t\000bsf\t\000bsr\t\000bswap\t\000b"
+ "t\t\000btc\t\000btr\t\000bts\t\000call\t\000cbw\000cdq\000cdqe\000fchs\000"
+ "clc\000cld\000clflush\t\000cli\000clts\000cmc\000cmova\t\000cmovae\t\000"
+ "cmovb\t\000cmovbe\t\000fcmovbe\t%ST(0), \000fcmovb\t%ST(0), \000cmove\t"
+ "\000fcmove\t%ST(0), \000cmovg\t\000cmovge\t\000cmovl\t\000cmovle\t\000f"
+ "cmovnbe\t%ST(0), \000fcmovnb\t%ST(0), \000cmovne\t\000fcmovne\t%ST(0), "
+ "\000cmovno\t\000cmovnp\t\000fcmovnu\t%ST(0), \000cmovns\t\000cmovo\t\000"
+ "cmovp\t\000fcmovu\t %ST(0), \000cmovs\t\000#CMOV_FR32 PSEUDO!\000#CMOV_"
+ "FR64 PSEUDO!\000#CMOV_GR8 PSEUDO!\000#CMOV_V1I64 PSEUDO!\000#CMOV_V2F64"
+ " PSEUDO!\000#CMOV_V2I64 PSEUDO!\000#CMOV_V4F32 PSEUDO!\000cmp\t%ax, \000"
+ "cmp\t\000cmp\t%eax, \000cmp\t%rax, \000cmp\t%al, \000cmp\000cmps\000cmp"
+ "xchg16b\t\000cmpxchg\t\000cmpxchg8b\t\000comisd\t\000comiss\t\000fcomp\t"
+ "\000fcomip\t%ST(0), \000fcomi\t%ST(0), \000fcom\t\000fcos\000cpuid\000c"
+ "qo\000crc32 \t\000cvtdq2pd\t\000cvtdq2ps\t\000cvtpd2dq\t\000cvtpd2ps\t\000"
+ "cvtps2dq\t\000cvtps2pd\t\000cvtsd2si\t\000cvtsd2ss\t\000cvtsi2sd\t\000c"
+ "vtsi2ss\t\000cvtss2sd\t\000cvtss2si\t\000cvttps2dq\t\000cvttsd2si\t\000"
+ "cvttss2si\t\000cwd\000cwde\000dec\t\000div\t\000divpd\t\000divps\t\000f"
+ "divr\t\000fidivr\t\000fdivrp\t\000divsd\t\000divss\t\000fdiv\t\000fidiv"
+ "\t\000fdivp\t\000dppd\t\000dpps\t\000ret\t#eh_return, addr: \000enter\t"
+ "\000extractps\t\000f2xm1\000lcall\t\000ljmp\t\000fbld\t\000fbstp\t\000f"
+ "compp\000fdecstp\000ffree\t\000ficom\t\000ficomp\t\000fincstp\000fisttp"
+ "\t\000fldcw\t\000fldenv\t\000fldl2e\000fldl2t\000fldlg2\000fldln2\000fl"
+ "dpi\000fnclex\000fninit\000fnop\000fnstcw\t\000fnstsw %ax\000fnstsw\t\000"
+ "##FP32_TO_INT16_IN_MEM PSEUDO!\000##FP32_TO_INT32_IN_MEM PSEUDO!\000##F"
+ "P32_TO_INT64_IN_MEM PSEUDO!\000##FP64_TO_INT16_IN_MEM PSEUDO!\000##FP64"
+ "_TO_INT32_IN_MEM PSEUDO!\000##FP64_TO_INT64_IN_MEM PSEUDO!\000##FP80_TO"
+ "_INT16_IN_MEM PSEUDO!\000##FP80_TO_INT32_IN_MEM PSEUDO!\000##FP80_TO_IN"
+ "T64_IN_MEM PSEUDO!\000fpatan\000fprem\000fprem1\000fptan\000##FP_REG_KI"
+ "LL\000frndint\000frstor\t\000fnsave\t\000fscale\000fsincos\000fnstenv\t"
+ "\000movl\t%fs:\000fxam\000fxrstor\t\000fxsave\t\000fxtract\000fyl2x\000"
+ "fyl2xp1\000pxor\t\000movapd\t\000movaps\t\000orpd\t\000orps\t\000xorpd\t"
+ "\000xorps\t\000movl\t%gs:\000haddpd\t\000haddps\t\000hlt\000hsubpd\t\000"
+ "hsubps\t\000idiv\t\000fild\t\000imul\t\000ins\000in\t%AX, \000in\t%AX, "
+ "%DX\000in\t%EAX, \000in\t%EAX, %DX\000in\t%AL, \000in\t%AL, %DX\000inc\t"
+ "\000insertps\t\000int\t\000int\t3\000invd\000invept\000invlpg\000invvpi"
+ "d\000iret\000fist\t\000fistp\t\000cvtpd2pi\t\000cvtpi2pd\t\000cvtpi2ps\t"
+ "\000cvtps2pi\t\000cvttpd2dq\t\000cvttpd2pi\t\000cvttps2pi\t\000ucomisd\t"
+ "\000ucomiss\t\000ja\t\000jae\t\000jb\t\000jbe\t\000jcxz\t\000je\t\000jg"
+ "\t\000jge\t\000jl\t\000jle\t\000jmp\t\000jne\t\000jno\t\000jnp\t\000jns"
+ "\t\000jo\t\000jp\t\000js\t\000lahf\000lar\t\000lock\n\tcmpxchg\t\000loc"
+ "k\n\tcmpxchgq\t\000lock\n\tcmpxchg8b\t\000lddqu\t\000ldmxcsr\t\000lds\t"
+ "\000fldz\000fld1\000fld\t\000lea\t\000leave\000les\t\000lfence\000lfs\t"
+ "\000lgdt\t\000lgs\t\000lidt\t\000lldt\t\000lmsw\t\000lock\n\tadd\t\000l"
+ "ock\n\tdec\t\000lock\n\tinc\t\000lock\n\tsub\t\000lodsb\000lodsd\000lod"
+ "sq\000lodsw\000loop\t\000loope\t\000loopne\t\000lret\000lret\t\000lsl\t"
+ "\000lss\t\000ltr\t\000lock\n\txadd\t\000maskmovdqu\t\000maxpd\t\000maxp"
+ "s\t\000maxsd\t\000maxss\t\000mfence\000minpd\t\000minps\t\000minsd\t\000"
+ "minss\t\000emms\000femms\000maskmovq\t\000movd\t\000movdq2q\t\000movntq"
+ "\t\000movq2dq\t\000movq\t\000packssdw\t\000packsswb\t\000packuswb\t\000"
+ "paddb\t\000paddd\t\000paddq\t\000paddsb\t\000paddsw\t\000paddusb\t\000p"
+ "addusw\t\000paddw\t\000pandn\t\000pand\t\000pavgb\t\000pavgw\t\000pcmpe"
+ "qb\t\000pcmpeqd\t\000pcmpeqw\t\000pcmpgtb\t\000pcmpgtd\t\000pcmpgtw\t\000"
+ "pextrw\t\000pinsrw\t\000pmaddwd\t\000pmaxsw\t\000pmaxub\t\000pminsw\t\000"
+ "pminub\t\000pmovmskb\t\000pmulhuw\t\000pmulhw\t\000pmullw\t\000pmuludq\t"
+ "\000por\t\000psadbw\t\000pshufw\t\000pslld\t\000psllq\t\000psllw\t\000p"
+ "srad\t\000psraw\t\000psrld\t\000psrlq\t\000psrlw\t\000psubb\t\000psubd\t"
+ "\000psubq\t\000psubsb\t\000psubsw\t\000psubusb\t\000psubusw\t\000psubw\t"
+ "\000punpckhbw\t\000punpckhdq\t\000punpckhwd\t\000punpcklbw\t\000punpckl"
+ "dq\t\000punpcklwd\t\000monitor\000mov\t\000mov\t%ax, \000mov\t%eax, \000"
+ "xor\t\000movq\t%fs:\000movq\t%gs:\000mov\t%rax, \000movabs\t\000mov\t%a"
+ "l, \000movddup\t\000movdqa\t\000movdqu\t\000movhlps\t\000movhpd\t\000mo"
+ "vhps\t\000movlhps\t\000movlpd\t\000movsd\t\000movlps\t\000movss\t\000mo"
+ "vmskpd\t\000movmskps\t\000movntdqa\t\000movntdq\t\000movnti\t\000movntp"
+ "d\t\000movntps\t\000movshdup\t\000movsldup\t\000movsx\t\000movsxd\t\000"
+ "movupd\t\000movups\t\000movzx\t\000mpsadbw\t\000mul\t\000mulpd\t\000mul"
+ "ps\t\000mulsd\t\000mulss\t\000fmul\t\000fimul\t\000fmulp\t\000mwait\000"
+ "neg\t\000nop\000nop\t\000not\t\000or\t%ax, \000or\t\000or\t%eax, \000or"
+ "\t%rax, \000or\t%al, \000out\t\000out\t%DX, %AX\000out\t%DX, %EAX\000ou"
+ "t\t%DX, %AL\000outsb\000outsd\000outsw\000pabsb\t\000pabsd\t\000pabsw\t"
+ "\000packusdw\t\000palignr\t\000pblendvb\t\000pblendw\t\000pcmpeqq\t\000"
+ "pcmpestri\t\000#PCMPESTRM128rm PSEUDO!\000#PCMPESTRM128rr PSEUDO!\000pc"
+ "mpestrm\t\000pcmpgtq\t\000pcmpistri\t\000#PCMPISTRM128rm PSEUDO!\000#PC"
+ "MPISTRM128rr PSEUDO!\000pcmpistrm\t\000pextrb\t\000pextrd\t\000pextrq\t"
+ "\000phaddd\t\000phaddsw\t\000phaddw\t\000phminposuw\t\000phsubd\t\000ph"
+ "subsw\t\000phsubw\t\000pinsrb\t\000pinsrd\t\000pinsrq\t\000pmaddubsw\t\000"
+ "pmaxsb\t\000pmaxsd\t\000pmaxud\t\000pmaxuw\t\000pminsb\t\000pminsd\t\000"
+ "pminud\t\000pminuw\t\000pmovsxbd\t\000pmovsxbq\t\000pmovsxbw\t\000pmovs"
+ "xdq\t\000pmovsxwd\t\000pmovsxwq\t\000pmovzxbd\t\000pmovzxbq\t\000pmovzx"
+ "bw\t\000pmovzxdq\t\000pmovzxwd\t\000pmovzxwq\t\000pmuldq\t\000pmulhrsw\t"
+ "\000pmulld\t\000pop\t\000popcnt\t\000popf\000pop\t%fs\000pop\t%gs\000pr"
+ "efetchnta\t\000prefetcht0\t\000prefetcht1\t\000prefetcht2\t\000pshufb\t"
+ "\000pshufd\t\000pshufhw\t\000pshuflw\t\000psignb\t\000psignd\t\000psign"
+ "w\t\000pslldq\t\000psrldq\t\000ptest \t\000punpckhqdq\t\000punpcklqdq\t"
+ "\000push\t\000pushf\000push\t%fs\000push\t%gs\000rcl\t\000rcpps\t\000rc"
+ "pss\t\000rcr\t\000rdmsr\000rdpmc\000rdtsc\000rep movsb\000rep movsd\000"
+ "rep movsq\000rep movsw\000rep stosb\000rep stosd\000rep stosq\000rep st"
+ "osw\000ret\000ret\t\000rol\t\000ror\t\000roundpd\t\000roundps\t\000roun"
+ "dsd\t\000roundss\t\000rsm\000rsqrtps\t\000rsqrtss\t\000sahf\000sar\t\000"
+ "sbb\t%ax, \000sbb\t\000sbb\t%eax, \000sbb\t%rax, \000sbb\t%al, \000scas"
+ "\000setae\t\000seta\t\000setbe\t\000setb\t\000sete\t\000setge\t\000setg"
+ "\t\000setle\t\000setl\t\000setne\t\000setno\t\000setnp\t\000setns\t\000"
+ "seto\t\000setp\t\000sets\t\000sfence\000sgdt\t\000shl\t\000shld\t\000sh"
+ "r\t\000shrd\t\000shufpd\t\000shufps\t\000sidt\t\000fsin\000sldt\t\000sm"
+ "sw\t\000sqrtpd\t\000sqrtps\t\000sqrtsd\t\000sqrtss\t\000fsqrt\000stc\000"
+ "std\000sti\000stmxcsr\t\000str\t\000fst\t\000fstp\t\000sub\t%ax, \000su"
+ "b\t\000sub\t%eax, \000sub\t%rax, \000sub\t%al, \000subpd\t\000subps\t\000"
+ "fsubr\t\000fisubr\t\000fsubrp\t\000subsd\t\000subss\t\000fsub\t\000fisu"
+ "b\t\000fsubp\t\000swpgs\000syscall\000sysenter\000sysexit\000sysret\000"
+ "#TC_RETURN \000test\t%ax, \000test\t\000test\t%eax, \000test\t%rax, \000"
+ "test\t%al, \000leal\t\000.byte\t0x66; leaq\t\000ud2\000ftst\000fucomip\t"
+ "%ST(0), \000fucomi\t%ST(0), \000fucompp\000fucomp\t\000fucom\t\000unpck"
+ "hpd\t\000unpckhps\t\000unpcklpd\t\000unpcklps\t\000#VASTART_SAVE_XMM_RE"
+ "GS \000verr\t\000verw\t\000vmcall\000vmclear\t\000vmlaunch\000vmptrld\t"
+ "\000vmptrst\t\000vmread\t\000vmresume\000vmwrite\t\000vmxoff\000vmxon\t"
+ "\000wait\000wbinvd\000wrmsr\000xadd\t\000xchg\t%ax, \000xchg\t\000xchg\t"
+ "%eax, \000xchg\t%rax, \000fxch\t\000xlatb\000xor\t%ax, \000xor\t%eax, \000"
+ "xor\t%rax, \000xor\t%al, \000";
#ifndef NO_ASM_WRITER_BOILERPLATE
@@ -2682,7 +2686,7 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
switch ((Bits >> 27) & 31) {
default: // unreachable.
case 0:
- // ABS_F, ADJCALLSTACKDOWN32, ADJCALLSTACKDOWN64, ADJCALLSTACKUP32, ADJCA...
+ // DEBUG_VALUE, ABS_F, ADJCALLSTACKDOWN32, ADJCALLSTACKDOWN64, ADJCALLSTA...
return;
break;
case 1:
diff --git a/libclamav/c++/X86GenDAGISel.inc b/libclamav/c++/X86GenDAGISel.inc
index 541f420..36bd51a 100644
--- a/libclamav/c++/X86GenDAGISel.inc
+++ b/libclamav/c++/X86GenDAGISel.inc
@@ -607,7 +607,8 @@ inline bool Predicate_loadi8(SDNode *N) {
}
inline bool Predicate_memop(SDNode *N) {
- return cast<LoadSDNode>(N)->getAlignment() >= 16;
+ return Subtarget->hasVectorUAMem()
+ || cast<LoadSDNode>(N)->getAlignment() >= 16;
}
inline bool Predicate_memop64(SDNode *N) {
@@ -697,6 +698,21 @@ inline bool Predicate_nvloadi32(SDNode *N) {
return false;
}
+inline bool Predicate_or_is_add(SDNode *N) {
+
+ if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
+ return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
+ else {
+ unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
+ APInt Mask = APInt::getAllOnesValue(BitWidth);
+ APInt KnownZero0, KnownOne0;
+ CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
+ APInt KnownZero1, KnownOne1;
+ CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
+ return (~KnownZero0 & ~KnownZero1) == 0;
+ }
+
+}
inline bool Predicate_palign(SDNode *N) {
return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
@@ -959,64 +975,64 @@ inline bool Predicate_zextloadi8(SDNode *N) {
}
-DISABLE_INLINE SDNode *Emit_0(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N0);
+DISABLE_INLINE SDNode *Emit_0(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N0);
}
-DISABLE_INLINE SDNode *Emit_1(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N0, N1);
+DISABLE_INLINE SDNode *Emit_1(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N0, N1);
}
-DISABLE_INLINE SDNode *Emit_2(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_2(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 2));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_3(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_3(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N0, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_4(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_4(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 2));
return ResNode;
}
-SDNode *Select_ISD_ADD_i8(const SDValue &N) {
+SDNode *Select_ISD_ADD_i8(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (add:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (ADD8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -1033,13 +1049,13 @@ SDNode *Select_ISD_ADD_i8(const SDValue &N) {
// Pattern: (add:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src1)
// Emits: (ADD8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -1053,10 +1069,10 @@ SDNode *Select_ISD_ADD_i8(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -1081,7 +1097,7 @@ SDNode *Select_ISD_ADD_i8(const SDValue &N) {
// Pattern: (add:i8 GR8:i8:$src1, (imm:i8):$src2)
// Emits: (ADD8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_3(N, X86::ADD8ri, MVT::i8);
return Result;
}
@@ -1094,34 +1110,34 @@ SDNode *Select_ISD_ADD_i8(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_5(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_5(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N0, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_6(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_6(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFFFFFFFF80ULL, MVT::i16);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp3);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp3);
}
-SDNode *Select_ISD_ADD_i16(const SDValue &N) {
+SDNode *Select_ISD_ADD_i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (add:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (ADD16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -1138,13 +1154,13 @@ SDNode *Select_ISD_ADD_i16(const SDValue &N) {
// Pattern: (add:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src1)
// Emits: (ADD16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -1158,9 +1174,9 @@ SDNode *Select_ISD_ADD_i16(const SDValue &N) {
}
}
if ((!Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -1182,9 +1198,9 @@ SDNode *Select_ISD_ADD_i16(const SDValue &N) {
}
}
if ((Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -1206,14 +1222,14 @@ SDNode *Select_ISD_ADD_i16(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (add:i16 GR16:i16:$src1, 128:i16)
// Emits: (SUB16ri8:i16 GR16:i16:$src1, -128:i16)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(128)) {
@@ -1222,7 +1238,7 @@ SDNode *Select_ISD_ADD_i16(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (add:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Emits: (ADD16ri8:i16 GR16:i16:$src1, (imm:i16):$src2)
@@ -1247,50 +1263,50 @@ SDNode *Select_ISD_ADD_i16(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_7(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN_0, SDValue &CPTmpN_1, SDValue &CPTmpN_2, SDValue &CPTmpN_3) {
+DISABLE_INLINE SDNode *Emit_7(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN_0, SDValue &CPTmpN_1, SDValue &CPTmpN_2, SDValue &CPTmpN_3) {
SDValue Ops0[] = { CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3 };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-DISABLE_INLINE SDNode *Emit_8(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_8(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N0, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_9(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_9(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFFFFFFFF80ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp3);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_10(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N10);
+DISABLE_INLINE SDNode *Emit_10(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N10);
}
-DISABLE_INLINE SDNode *Emit_11(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N00);
+DISABLE_INLINE SDNode *Emit_11(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N00);
}
-SDNode *Select_ISD_ADD_i32(const SDValue &N) {
+SDNode *Select_ISD_ADD_i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (add:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (ADD32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -1307,13 +1323,13 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src1)
// Emits: (ADD32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -1335,7 +1351,7 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
@@ -1349,22 +1365,22 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
}
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == X86ISD::Wrapper) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == X86ISD::Wrapper) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (add:i32 GR32:i32:$src1, (X86Wrapper:i32 (tconstpool:i32):$src2))
// Emits: (ADD32ri:i32 GR32:i32:$src1, (tconstpool:i32):$src2)
// Pattern complexity = 9 cost = 1 size = 3
- if (N10.getOpcode() == ISD::TargetConstantPool) {
+ if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
SDNode *Result = Emit_10(N, X86::ADD32ri, MVT::i32);
return Result;
}
@@ -1372,7 +1388,7 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GR32:i32:$src1, (X86Wrapper:i32 (tjumptable:i32):$src2))
// Emits: (ADD32ri:i32 GR32:i32:$src1, (tjumptable:i32):$src2)
// Pattern complexity = 9 cost = 1 size = 3
- if (N10.getOpcode() == ISD::TargetJumpTable) {
+ if (N10.getNode()->getOpcode() == ISD::TargetJumpTable) {
SDNode *Result = Emit_10(N, X86::ADD32ri, MVT::i32);
return Result;
}
@@ -1380,7 +1396,7 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GR32:i32:$src1, (X86Wrapper:i32 (tglobaladdr:i32):$src2))
// Emits: (ADD32ri:i32 GR32:i32:$src1, (tglobaladdr:i32):$src2)
// Pattern complexity = 9 cost = 1 size = 3
- if (N10.getOpcode() == ISD::TargetGlobalAddress) {
+ if (N10.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
SDNode *Result = Emit_10(N, X86::ADD32ri, MVT::i32);
return Result;
}
@@ -1388,7 +1404,7 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GR32:i32:$src1, (X86Wrapper:i32 (texternalsym:i32):$src2))
// Emits: (ADD32ri:i32 GR32:i32:$src1, (texternalsym:i32):$src2)
// Pattern complexity = 9 cost = 1 size = 3
- if (N10.getOpcode() == ISD::TargetExternalSymbol) {
+ if (N10.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
SDNode *Result = Emit_10(N, X86::ADD32ri, MVT::i32);
return Result;
}
@@ -1396,19 +1412,19 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 GR32:i32:$src1, (X86Wrapper:i32 (tblockaddress:i32):$src2))
// Emits: (ADD32ri:i32 GR32:i32:$src1, (tblockaddress:i32):$src2)
// Pattern complexity = 9 cost = 1 size = 3
- if (N10.getOpcode() == ISD::TargetBlockAddress) {
+ if (N10.getNode()->getOpcode() == ISD::TargetBlockAddress) {
SDNode *Result = Emit_10(N, X86::ADD32ri, MVT::i32);
return Result;
}
}
}
- if (N0.getOpcode() == X86ISD::Wrapper) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == X86ISD::Wrapper) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (add:i32 (X86Wrapper:i32 (tconstpool:i32):$src2), GR32:i32:$src1)
// Emits: (ADD32ri:i32 GR32:i32:$src1, (tconstpool:i32):$src2)
// Pattern complexity = 9 cost = 1 size = 3
- if (N00.getOpcode() == ISD::TargetConstantPool) {
+ if (N00.getNode()->getOpcode() == ISD::TargetConstantPool) {
SDNode *Result = Emit_11(N, X86::ADD32ri, MVT::i32);
return Result;
}
@@ -1416,7 +1432,7 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (X86Wrapper:i32 (tjumptable:i32):$src2), GR32:i32:$src1)
// Emits: (ADD32ri:i32 GR32:i32:$src1, (tjumptable:i32):$src2)
// Pattern complexity = 9 cost = 1 size = 3
- if (N00.getOpcode() == ISD::TargetJumpTable) {
+ if (N00.getNode()->getOpcode() == ISD::TargetJumpTable) {
SDNode *Result = Emit_11(N, X86::ADD32ri, MVT::i32);
return Result;
}
@@ -1424,7 +1440,7 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (X86Wrapper:i32 (tglobaladdr:i32):$src2), GR32:i32:$src1)
// Emits: (ADD32ri:i32 GR32:i32:$src1, (tglobaladdr:i32):$src2)
// Pattern complexity = 9 cost = 1 size = 3
- if (N00.getOpcode() == ISD::TargetGlobalAddress) {
+ if (N00.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
SDNode *Result = Emit_11(N, X86::ADD32ri, MVT::i32);
return Result;
}
@@ -1432,7 +1448,7 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (X86Wrapper:i32 (texternalsym:i32):$src2), GR32:i32:$src1)
// Emits: (ADD32ri:i32 GR32:i32:$src1, (texternalsym:i32):$src2)
// Pattern complexity = 9 cost = 1 size = 3
- if (N00.getOpcode() == ISD::TargetExternalSymbol) {
+ if (N00.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
SDNode *Result = Emit_11(N, X86::ADD32ri, MVT::i32);
return Result;
}
@@ -1440,16 +1456,16 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
// Pattern: (add:i32 (X86Wrapper:i32 (tblockaddress:i32):$src2), GR32:i32:$src1)
// Emits: (ADD32ri:i32 GR32:i32:$src1, (tblockaddress:i32):$src2)
// Pattern complexity = 9 cost = 1 size = 3
- if (N00.getOpcode() == ISD::TargetBlockAddress) {
+ if (N00.getNode()->getOpcode() == ISD::TargetBlockAddress) {
SDNode *Result = Emit_11(N, X86::ADD32ri, MVT::i32);
return Result;
}
}
}
if ((!Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -1471,9 +1487,9 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
if ((Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -1495,14 +1511,14 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (add:i32 GR32:i32:$src1, 128:i32)
// Emits: (SUB32ri8:i32 GR32:i32:$src1, -128:i32)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(128)) {
@@ -1511,7 +1527,7 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (add:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Emits: (ADD32ri8:i32 GR32:i32:$src1, (imm:i32):$src2)
@@ -1536,40 +1552,40 @@ SDNode *Select_ISD_ADD_i32(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_12(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_12(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N0, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_13(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_13(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFFFFFFFF80ULL, MVT::i64);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp3);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_14(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_14(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFF80000000ULL, MVT::i64);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp3);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp3);
}
-SDNode *Select_ISD_ADD_i64(const SDValue &N) {
+SDNode *Select_ISD_ADD_i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (add:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (ADD64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -1586,13 +1602,13 @@ SDNode *Select_ISD_ADD_i64(const SDValue &N) {
// Pattern: (add:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
// Emits: (ADD64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -1614,16 +1630,16 @@ SDNode *Select_ISD_ADD_i64(const SDValue &N) {
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -1660,7 +1676,7 @@ SDNode *Select_ISD_ADD_i64(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (add:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Emits: (ADD64ri8:i64 GR64:i64:$src1, (imm:i64):$src2)
@@ -1687,59 +1703,59 @@ SDNode *Select_ISD_ADD_i64(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_15(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1);
+DISABLE_INLINE SDNode *Emit_15(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1);
}
-DISABLE_INLINE SDNode *Emit_16(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
+DISABLE_INLINE SDNode *Emit_16(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { N0, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_17(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue Chain00 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_17(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
SDValue Ops0[] = { N1, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_ISD_ADD_v8i8(const SDValue &N) {
+SDNode *Select_ISD_ADD_v8i8(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (add:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PADDBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -1758,23 +1774,23 @@ SDNode *Select_ISD_ADD_v8i8(const SDValue &N) {
// Pattern: (add:v8i8 (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
// Emits: (MMX_PADDBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v1i64) {
SDNode *Result = Emit_17(N, X86::MMX_PADDBrm, MVT::v8i8, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
@@ -1797,27 +1813,27 @@ SDNode *Select_ISD_ADD_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ADD_v16i8(const SDValue &N) {
+SDNode *Select_ISD_ADD_v16i8(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (add:v16i8 VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PADDBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -1836,24 +1852,24 @@ SDNode *Select_ISD_ADD_v16i8(const SDValue &N) {
// Pattern: (add:v16i8 (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
// Emits: (PADDBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode()) &&
Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_17(N, X86::PADDBrm, MVT::v16i8, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
@@ -1876,26 +1892,26 @@ SDNode *Select_ISD_ADD_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ADD_v4i16(const SDValue &N) {
+SDNode *Select_ISD_ADD_v4i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (add:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PADDWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -1914,23 +1930,23 @@ SDNode *Select_ISD_ADD_v4i16(const SDValue &N) {
// Pattern: (add:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
// Emits: (MMX_PADDWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v1i64) {
SDNode *Result = Emit_17(N, X86::MMX_PADDWrm, MVT::v4i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
@@ -1953,27 +1969,27 @@ SDNode *Select_ISD_ADD_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
+SDNode *Select_ISD_ADD_v8i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (add:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PADDWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -1992,24 +2008,24 @@ SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
// Pattern: (add:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
// Emits: (PADDWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode()) &&
Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_17(N, X86::PADDWrm, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
@@ -2032,26 +2048,26 @@ SDNode *Select_ISD_ADD_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ADD_v2i32(const SDValue &N) {
+SDNode *Select_ISD_ADD_v2i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (add:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PADDDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -2070,23 +2086,23 @@ SDNode *Select_ISD_ADD_v2i32(const SDValue &N) {
// Pattern: (add:v2i32 (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v2i32:$src1)
// Emits: (MMX_PADDDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v1i64) {
SDNode *Result = Emit_17(N, X86::MMX_PADDDrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
@@ -2109,27 +2125,27 @@ SDNode *Select_ISD_ADD_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
+SDNode *Select_ISD_ADD_v4i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (add:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PADDDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -2148,24 +2164,24 @@ SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
// Pattern: (add:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
// Emits: (PADDDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode()) &&
Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_17(N, X86::PADDDrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
@@ -2188,26 +2204,26 @@ SDNode *Select_ISD_ADD_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ADD_v1i64(const SDValue &N) {
+SDNode *Select_ISD_ADD_v1i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (add:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PADDQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -2226,23 +2242,23 @@ SDNode *Select_ISD_ADD_v1i64(const SDValue &N) {
// Pattern: (add:v1i64 (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v1i64:$src1)
// Emits: (MMX_PADDQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v1i64) {
SDNode *Result = Emit_17(N, X86::MMX_PADDQrm, MVT::v1i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
@@ -2265,50 +2281,50 @@ SDNode *Select_ISD_ADD_v1i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_18(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_18(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_19(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_19(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_ISD_ADD_v2i64(const SDValue &N) {
+SDNode *Select_ISD_ADD_v2i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (add:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PADDQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -2325,14 +2341,14 @@ SDNode *Select_ISD_ADD_v2i64(const SDValue &N) {
// Pattern: (add:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
// Emits: (PADDQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -2358,28 +2374,28 @@ SDNode *Select_ISD_ADD_v2i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_20(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, N1);
+DISABLE_INLINE SDNode *Emit_20(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, N1);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_21(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_21(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, MVT::Flag, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, MVT::Flag, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
SDValue InFlag(ResNode, 2);
const SDValue Froms[] = {
SDValue(N1.getNode(), 1),
- SDValue(N.getNode(), 1)
+ SDValue(N, 1)
};
const SDValue Tos[] = {
SDValue(ResNode, 1),
@@ -2388,29 +2404,29 @@ DISABLE_INLINE SDNode *Emit_21(const SDValue &N, unsigned Opc0, MVT::SimpleValue
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_22(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_22(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, Tmp1);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, Tmp1);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_23(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_23(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, MVT::Flag, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, MVT::Flag, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
SDValue InFlag(ResNode, 2);
const SDValue Froms[] = {
SDValue(N0.getNode(), 1),
- SDValue(N.getNode(), 1)
+ SDValue(N, 1)
};
const SDValue Tos[] = {
SDValue(ResNode, 1),
@@ -2419,22 +2435,22 @@ DISABLE_INLINE SDNode *Emit_23(const SDValue &N, unsigned Opc0, MVT::SimpleValue
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_ISD_ADDC_i32(const SDValue &N) {
+SDNode *Select_ISD_ADDC_i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (addc:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (ADD32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -2451,13 +2467,13 @@ SDNode *Select_ISD_ADDC_i32(const SDValue &N) {
// Pattern: (addc:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src1)
// Emits: (ADD32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -2471,9 +2487,9 @@ SDNode *Select_ISD_ADDC_i32(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (addc:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Emits: (ADD32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
@@ -2498,31 +2514,31 @@ SDNode *Select_ISD_ADDC_i32(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_24(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_24(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, Tmp1);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, Tmp1);
SDValue InFlag(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-SDNode *Select_ISD_ADDC_i64(const SDValue &N) {
+SDNode *Select_ISD_ADDC_i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (addc:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (ADD64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -2539,13 +2555,13 @@ SDNode *Select_ISD_ADDC_i64(const SDValue &N) {
// Pattern: (addc:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
// Emits: (ADD64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -2559,9 +2575,9 @@ SDNode *Select_ISD_ADDC_i64(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (addc:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Emits: (ADD64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
@@ -2588,30 +2604,30 @@ SDNode *Select_ISD_ADDC_i64(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_25(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue InFlag = N.getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, N1, InFlag);
+DISABLE_INLINE SDNode *Emit_25(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue InFlag = N->getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, N1, InFlag);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_26(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue InFlag = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_26(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue InFlag = N->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, MVT::Flag, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, MVT::Flag, Ops0, 8);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
InFlag = SDValue(ResNode, 2);
const SDValue Froms[] = {
SDValue(N1.getNode(), 1),
- SDValue(N.getNode(), 1)
+ SDValue(N, 1)
};
const SDValue Tos[] = {
SDValue(ResNode, 1),
@@ -2620,31 +2636,31 @@ DISABLE_INLINE SDNode *Emit_26(const SDValue &N, unsigned Opc0, MVT::SimpleValue
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_27(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_27(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
- SDValue InFlag = N.getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, Tmp1, InFlag);
+ SDValue InFlag = N->getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, Tmp1, InFlag);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_28(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue InFlag = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_28(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue InFlag = N->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, MVT::Flag, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, MVT::Flag, Ops0, 8);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
InFlag = SDValue(ResNode, 2);
const SDValue Froms[] = {
SDValue(N0.getNode(), 1),
- SDValue(N.getNode(), 1)
+ SDValue(N, 1)
};
const SDValue Tos[] = {
SDValue(ResNode, 1),
@@ -2653,22 +2669,22 @@ DISABLE_INLINE SDNode *Emit_28(const SDValue &N, unsigned Opc0, MVT::SimpleValue
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_ISD_ADDE_i8(const SDValue &N) {
+SDNode *Select_ISD_ADDE_i8(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (adde:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (ADC8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -2685,13 +2701,13 @@ SDNode *Select_ISD_ADDE_i8(const SDValue &N) {
// Pattern: (adde:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src1)
// Emits: (ADC8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -2709,9 +2725,9 @@ SDNode *Select_ISD_ADDE_i8(const SDValue &N) {
// Emits: (ADC8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_27(N, X86::ADC8ri, MVT::i8);
return Result;
}
@@ -2724,32 +2740,32 @@ SDNode *Select_ISD_ADDE_i8(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_29(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_29(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
- SDValue InFlag = N.getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, Tmp1, InFlag);
+ SDValue InFlag = N->getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, Tmp1, InFlag);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-SDNode *Select_ISD_ADDE_i16(const SDValue &N) {
+SDNode *Select_ISD_ADDE_i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (adde:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (ADC16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -2766,13 +2782,13 @@ SDNode *Select_ISD_ADDE_i16(const SDValue &N) {
// Pattern: (adde:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src1)
// Emits: (ADC16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -2786,9 +2802,9 @@ SDNode *Select_ISD_ADDE_i16(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (adde:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Emits: (ADC16ri8:i16 GR16:i16:$src1, (imm:i16):$src2)
@@ -2813,32 +2829,32 @@ SDNode *Select_ISD_ADDE_i16(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_30(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_30(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- SDValue InFlag = N.getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, Tmp1, InFlag);
+ SDValue InFlag = N->getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, Tmp1, InFlag);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
+SDNode *Select_ISD_ADDE_i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (adde:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (ADC32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -2855,13 +2871,13 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
// Pattern: (adde:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src1)
// Emits: (ADC32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -2875,9 +2891,9 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (adde:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Emits: (ADC32ri8:i32 GR32:i32:$src1, (imm:i32):$src2)
@@ -2902,32 +2918,32 @@ SDNode *Select_ISD_ADDE_i32(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_31(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_31(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
- SDValue InFlag = N.getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Flag, N0, Tmp1, InFlag);
+ SDValue InFlag = N->getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Flag, N0, Tmp1, InFlag);
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(N.getNode(), 1), InFlag);
+ ReplaceUses(SDValue(N, 1), InFlag);
return ResNode;
}
-SDNode *Select_ISD_ADDE_i64(const SDValue &N) {
+SDNode *Select_ISD_ADDE_i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (adde:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (ADC64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -2944,13 +2960,13 @@ SDNode *Select_ISD_ADDE_i64(const SDValue &N) {
// Pattern: (adde:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
// Emits: (ADC64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -2964,9 +2980,9 @@ SDNode *Select_ISD_ADDE_i64(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (adde:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Emits: (ADC64ri8:i64 GR64:i64:$src1, (imm:i64):$src2)
@@ -2993,23 +3009,23 @@ SDNode *Select_ISD_ADDE_i64(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_AND_i8(const SDValue &N) {
+SDNode *Select_ISD_AND_i8(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (and:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
// Emits: (AND8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_loadi8(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -3026,14 +3042,14 @@ SDNode *Select_ISD_AND_i8(const SDValue &N) {
// Pattern: (and:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src1)
// Emits: (AND8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_loadi8(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -3051,9 +3067,9 @@ SDNode *Select_ISD_AND_i8(const SDValue &N) {
// Emits: (AND8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_3(N, X86::AND8ri, MVT::i8);
return Result;
}
@@ -3066,38 +3082,38 @@ SDNode *Select_ISD_AND_i8(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_32(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_32(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp2), 0);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
SDValue Tmp4 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- SDValue Tmp5(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp3, Tmp4), 0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc2, VT2, Tmp5);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp3, Tmp4), 0);
+ return CurDAG->SelectNodeTo(N, Opc2, VT2, Tmp5);
}
-DISABLE_INLINE SDNode *Emit_33(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_33(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp2), 0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp3);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp3);
}
-SDNode *Select_ISD_AND_i16(const SDValue &N) {
+SDNode *Select_ISD_AND_i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (and:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
// Emits: (AND16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_loadi16(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -3114,13 +3130,13 @@ SDNode *Select_ISD_AND_i16(const SDValue &N) {
// Pattern: (and:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src1)
// Emits: (AND16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -3138,9 +3154,9 @@ SDNode *Select_ISD_AND_i16(const SDValue &N) {
// Emits: (MOVZX16rr8:i16 (EXTRACT_SUBREG:i8 GR16:i16:$src1, 1:i32))
// Pattern complexity = 8 cost = 2 size = 3
if ((Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0 &&
CheckAndMask(N0, Tmp0, INT64_C(255))) {
SDNode *Result = Emit_33(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX16rr8, MVT::i8, MVT::i16);
@@ -3152,9 +3168,9 @@ SDNode *Select_ISD_AND_i16(const SDValue &N) {
// Emits: (MOVZX16rr8:i16 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src1, GR16_ABCD:i16), 1:i32))
// Pattern complexity = 8 cost = 3 size = 3
if ((!Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0 &&
CheckAndMask(N0, Tmp0, INT64_C(255))) {
SDNode *Result = Emit_32(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX16rr8, MVT::i16, MVT::i8, MVT::i16);
@@ -3162,9 +3178,9 @@ SDNode *Select_ISD_AND_i16(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (and:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Emits: (AND16ri8:i16 GR16:i16:$src1, (imm:i16):$src2)
@@ -3189,66 +3205,66 @@ SDNode *Select_ISD_AND_i16(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_34(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+DISABLE_INLINE SDNode *Emit_34(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_35(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_35(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0x3ULL, MVT::i32);
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp2), 0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp3);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_36(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_36(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(X86::GR32_ABCDRegClassID, MVT::i32);
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp2), 0);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
SDValue Tmp4 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- SDValue Tmp5(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp3, Tmp4), 0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc2, VT2, Tmp5);
-}
-DISABLE_INLINE SDNode *Emit_37(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp3, Tmp4), 0);
+ return CurDAG->SelectNodeTo(N, Opc2, VT2, Tmp5);
+}
+DISABLE_INLINE SDNode *Emit_37(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue Tmp4 = CurDAG->getTargetConstant(X86::GR32_ABCDRegClassID, MVT::i32);
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N00, Tmp4), 0);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N00, Tmp4), 0);
SDValue Tmp6 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
- SDValue Tmp7(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp5, Tmp6), 0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc2, VT2, Tmp7);
+ SDValue Tmp7(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp5, Tmp6), 0);
+ return CurDAG->SelectNodeTo(N, Opc2, VT2, Tmp7);
}
-SDNode *Select_ISD_AND_i32(const SDValue &N) {
+SDNode *Select_ISD_AND_i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
// Pattern: (and:i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_nvloadi32>>, 255:i32)
// Emits: (MOVZX32rm8:i32 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
if (CheckAndMask(N0, Tmp0, INT64_C(255)) &&
- N0.getOpcode() == ISD::LOAD &&
+ N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_nvloadi32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -3265,13 +3281,13 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (MOVZX32rm16:i32 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
if (CheckAndMask(N0, Tmp0, INT64_C(65535)) &&
- N0.getOpcode() == ISD::LOAD &&
+ N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_nvloadi32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -3289,13 +3305,13 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Pattern: (and:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
// Emits: (AND32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N1.getOpcode() == ISD::LOAD &&
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -3312,13 +3328,13 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Pattern: (and:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src1)
// Emits: (AND32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -3336,16 +3352,16 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (MOVZX32rr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR32:i32:$src, GR32_ABCD:i32), 2:i32))
// Pattern complexity = 17 cost = 3 size = 3
if ((!Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0 &&
CheckAndMask(N0, Tmp0, INT64_C(255)) &&
- N0.getOpcode() == ISD::SRL &&
+ N0.getNode()->getOpcode() == ISD::SRL &&
Predicate_srl_su(N0.getNode())) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8) &&
@@ -3361,16 +3377,16 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR32:i32:$src, GR32_ABCD:i32), 2:i32))
// Pattern complexity = 17 cost = 3 size = 3
if ((Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0 &&
CheckAndMask(N0, Tmp0, INT64_C(255)) &&
- N0.getOpcode() == ISD::SRL &&
+ N0.getNode()->getOpcode() == ISD::SRL &&
Predicate_srl_su(N0.getNode())) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8) &&
@@ -3386,9 +3402,9 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (MOVZX32rr16:i32 (EXTRACT_SUBREG:i16 GR32:i32:$src1, 3:i32))
// Pattern complexity = 8 cost = 2 size = 3
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0 &&
CheckAndMask(N0, Tmp0, INT64_C(65535))) {
SDNode *Result = Emit_35(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr16, MVT::i16, MVT::i32);
@@ -3400,9 +3416,9 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (MOVZX32rr8:i32 (EXTRACT_SUBREG:i8 GR32:i32:$src1, 1:i32))
// Pattern complexity = 8 cost = 2 size = 3
if ((Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0 &&
CheckAndMask(N0, Tmp0, INT64_C(255))) {
SDNode *Result = Emit_33(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i8, MVT::i32);
@@ -3414,9 +3430,9 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
// Emits: (MOVZX32rr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR32:i32:$src1, GR32_ABCD:i32), 1:i32))
// Pattern complexity = 8 cost = 3 size = 3
if ((!Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0 &&
CheckAndMask(N0, Tmp0, INT64_C(255))) {
SDNode *Result = Emit_36(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i32, MVT::i8, MVT::i32);
@@ -3424,9 +3440,9 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (and:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Emits: (AND32ri8:i32 GR32:i32:$src1, (imm:i32):$src2)
@@ -3451,43 +3467,54 @@ SDNode *Select_ISD_AND_i32(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_38(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_38(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp0 = CurDAG->getTargetConstant(0x0ULL, MVT::i64);
SDValue Tmp2 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp2), 0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp3);
-}
-DISABLE_INLINE SDNode *Emit_39(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
+ SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp3, Tmp4), 0);
+ SDValue Tmp6 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
+ return CurDAG->SelectNodeTo(N, Opc2, VT2, Tmp0, Tmp5, Tmp6);
+}
+DISABLE_INLINE SDNode *Emit_39(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp2 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp2), 0);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp3);
+}
+DISABLE_INLINE SDNode *Emit_40(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(0x0ULL, MVT::i64);
SDValue Tmp5 = CurDAG->getTargetConstant(X86::GR64_ABCDRegClassID, MVT::i32);
- SDValue Tmp6(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N00, Tmp5), 0);
+ SDValue Tmp6(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N00, Tmp5), 0);
SDValue Tmp7 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
- SDValue Tmp8(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp6, Tmp7), 0);
- SDValue Tmp9(CurDAG->getMachineNode(Opc2, N.getDebugLoc(), VT2, Tmp8), 0);
+ SDValue Tmp8(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp6, Tmp7), 0);
+ SDValue Tmp9(CurDAG->getMachineNode(Opc2, N->getDebugLoc(), VT2, Tmp8), 0);
SDValue Tmp10 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc3, VT3, Tmp3, Tmp9, Tmp10);
+ return CurDAG->SelectNodeTo(N, Opc3, VT3, Tmp3, Tmp9, Tmp10);
}
-SDNode *Select_ISD_AND_i64(const SDValue &N) {
+SDNode *Select_ISD_AND_i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (and:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (AND64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -3504,13 +3531,13 @@ SDNode *Select_ISD_AND_i64(const SDValue &N) {
// Pattern: (and:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
// Emits: (AND64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -3524,26 +3551,26 @@ SDNode *Select_ISD_AND_i64(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
// Pattern: (and:i64 (srl:i64 GR64:i64:$src, 8:i8)<<P:Predicate_srl_su>>, 255:i64)
// Emits: (SUBREG_TO_REG:i64 0:i64, (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i64 GR64:i64:$src, GR64_ABCD:i64), 2:i32)), 4:i32)
// Pattern complexity = 17 cost = 4 size = 3
if (CheckAndMask(N0, Tmp0, INT64_C(255)) &&
- N0.getOpcode() == ISD::SRL &&
+ N0.getNode()->getOpcode() == ISD::SRL &&
Predicate_srl_su(N0.getNode())) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp1 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp1) {
int64_t CN2 = Tmp1->getSExtValue();
if (CN2 == INT64_C(8) &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_39(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetInstrInfo::SUBREG_TO_REG, MVT::i64, MVT::i8, MVT::i32, MVT::i64);
+ SDNode *Result = Emit_40(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetInstrInfo::SUBREG_TO_REG, MVT::i64, MVT::i8, MVT::i32, MVT::i64);
return Result;
}
}
@@ -3553,7 +3580,7 @@ SDNode *Select_ISD_AND_i64(const SDValue &N) {
// Emits: (MOVZX64rr32:i64 (EXTRACT_SUBREG:i32 GR64:i64:$src, 4:i32))
// Pattern complexity = 8 cost = 2 size = 3
if (CheckAndMask(N0, Tmp0, INT64_C(4294967295))) {
- SDNode *Result = Emit_38(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX64rr32, MVT::i32, MVT::i64);
+ SDNode *Result = Emit_39(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX64rr32, MVT::i32, MVT::i64);
return Result;
}
@@ -3574,7 +3601,7 @@ SDNode *Select_ISD_AND_i64(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (and:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Emits: (AND64ri8:i64 GR64:i64:$src1, (imm:i64):$src2)
@@ -3591,6 +3618,14 @@ SDNode *Select_ISD_AND_i64(const SDValue &N) {
SDNode *Result = Emit_12(N, X86::AND64ri32, MVT::i64);
return Result;
}
+
+ // Pattern: (and:i64 GR64:i64:$src, (imm:i64)<<P:Predicate_i64immZExt32>>:$imm)
+ // Emits: (SUBREG_TO_REG:i64 0:i64, (AND32ri:i32 (EXTRACT_SUBREG:i32 GR64:i64:$src, 4:i32), (imm:i32):$imm), 4:i32)
+ // Pattern complexity = 7 cost = 3 size = 3
+ if (Predicate_i64immZExt32(N1.getNode())) {
+ SDNode *Result = Emit_38(N, TargetInstrInfo::EXTRACT_SUBREG, X86::AND32ri, TargetInstrInfo::SUBREG_TO_REG, MVT::i32, MVT::i32, MVT::i64);
+ return Result;
+ }
}
}
@@ -3601,214 +3636,214 @@ SDNode *Select_ISD_AND_i64(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_40(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N1);
-}
-DISABLE_INLINE SDNode *Emit_41(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_41(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, N1);
+}
+DISABLE_INLINE SDNode *Emit_42(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { N00, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_42(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N1);
-}
-DISABLE_INLINE SDNode *Emit_43(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_43(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, N1);
+}
+DISABLE_INLINE SDNode *Emit_44(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { N00, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_44(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N01, N1);
-}
-DISABLE_INLINE SDNode *Emit_45(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N0);
-}
-DISABLE_INLINE SDNode *Emit_46(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N11, N0);
-}
-DISABLE_INLINE SDNode *Emit_47(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_45(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N01, N1);
+}
+DISABLE_INLINE SDNode *Emit_46(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N10, N0);
+}
+DISABLE_INLINE SDNode *Emit_47(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N11, N0);
+}
+DISABLE_INLINE SDNode *Emit_48(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { N01, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_48(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_49(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { N10, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_49(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_50(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { N11, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_50(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N01, N1);
-}
-DISABLE_INLINE SDNode *Emit_51(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N0);
-}
-DISABLE_INLINE SDNode *Emit_52(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N11, N0);
-}
-DISABLE_INLINE SDNode *Emit_53(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_51(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N01, N1);
+}
+DISABLE_INLINE SDNode *Emit_52(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N10, N0);
+}
+DISABLE_INLINE SDNode *Emit_53(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N11, N0);
+}
+DISABLE_INLINE SDNode *Emit_54(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { N01, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_54(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
+DISABLE_INLINE SDNode *Emit_55(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { N10, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_55(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_56(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { N11, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
+SDNode *Select_ISD_AND_v1i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getNode()->getOperand(0);
// Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>)), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
- if (N010.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N010.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N010.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -3816,22 +3851,22 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N010.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_43(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_44(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- if (N010.getOpcode() == ISD::BIT_CONVERT &&
+ if (N010.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N010.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -3843,7 +3878,7 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
if (N010.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_43(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_44(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -3851,7 +3886,7 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
if (N010.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_43(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_44(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -3864,19 +3899,19 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>), VR64:v1i64:$src1), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
- if (N00.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -3884,7 +3919,7 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N000.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_53(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_54(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -3892,34 +3927,34 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>)))
// Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N110.getNode()) &&
N110.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_54(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_55(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -3928,13 +3963,13 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>), VR64:v1i64:$src1))
// Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_55(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_56(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -3947,21 +3982,21 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::BIT_CONVERT &&
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N000.getNode())) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -3969,7 +4004,7 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N000.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_53(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_54(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -3977,34 +4012,34 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>)))
// Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N110.getNode()) &&
N110.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_54(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_55(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -4013,13 +4048,13 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1))
// Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::BIT_CONVERT &&
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N100.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_55(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_56(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -4032,21 +4067,21 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::BIT_CONVERT &&
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N000.getNode())) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -4054,7 +4089,7 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N000.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_53(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_54(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -4062,34 +4097,34 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>)))
// Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N110.getNode()) &&
N110.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_54(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_55(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -4098,13 +4133,13 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1))
// Emits: (MMX_PANDNrm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::BIT_CONVERT &&
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N100.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_55(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_56(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -4115,32 +4150,32 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
}
}
if ((Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (build_vector:v1i64)<<P:Predicate_immAllOnesV>>), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (MMX_PANDNrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 32 cost = 1 size = 3
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N01.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_41(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_42(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -4151,55 +4186,55 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Pattern: (and:v1i64 (xor:v1i64 (build_vector:v1i64)<<P:Predicate_immAllOnesV>>, VR64:v1i64:$src1), (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (MMX_PANDNrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 32 cost = 1 size = 3
- if (N00.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N00.getNode())) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_47(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_48(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
}
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 VR64:v1i64:$src1, (build_vector:v1i64)<<P:Predicate_immAllOnesV>>))
// Emits: (MMX_PANDNrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 32 cost = 1 size = 3
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N11.getNode())) {
- SDNode *Result = Emit_48(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_49(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -4207,9 +4242,9 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (xor:v1i64 (build_vector:v1i64)<<P:Predicate_immAllOnesV>>, VR64:v1i64:$src1))
// Emits: (MMX_PANDNrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 32 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N10.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N10.getNode())) {
- SDNode *Result = Emit_49(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_50(N, X86::MMX_PANDNrm, MVT::v1i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -4221,14 +4256,14 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Emits: (MMX_PANDrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -4245,13 +4280,13 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Pattern: (and:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR64:v1i64:$src1)
// Emits: (MMX_PANDrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -4266,34 +4301,34 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getNode()->getOperand(0);
// Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>)), VR64:v1i64:$src2)
// Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
- if (N010.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N010.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N010.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N010.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_42(N, X86::MMX_PANDNrr, MVT::v1i64);
+ SDNode *Result = Emit_43(N, X86::MMX_PANDNrr, MVT::v1i64);
return Result;
}
}
- if (N010.getOpcode() == ISD::BIT_CONVERT &&
+ if (N010.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N010.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
// Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>)), VR64:v1i64:$src2)
// Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
if (N010.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_42(N, X86::MMX_PANDNrr, MVT::v1i64);
+ SDNode *Result = Emit_43(N, X86::MMX_PANDNrr, MVT::v1i64);
return Result;
}
@@ -4301,7 +4336,7 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
if (N010.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_42(N, X86::MMX_PANDNrr, MVT::v1i64);
+ SDNode *Result = Emit_43(N, X86::MMX_PANDNrr, MVT::v1i64);
return Result;
}
}
@@ -4311,35 +4346,35 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>), VR64:v1i64:$src1), VR64:v1i64:$src2)
// Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
- if (N00.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_50(N, X86::MMX_PANDNrr, MVT::v1i64);
+ SDNode *Result = Emit_51(N, X86::MMX_PANDNrr, MVT::v1i64);
return Result;
}
}
}
}
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>)))
// Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N110.getNode()) &&
N110.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_51(N, X86::MMX_PANDNrr, MVT::v1i64);
+ SDNode *Result = Emit_52(N, X86::MMX_PANDNrr, MVT::v1i64);
return Result;
}
}
@@ -4348,13 +4383,13 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 (bitconvert:v1i64 (build_vector:v2i32)<<P:Predicate_immAllOnesV>>), VR64:v1i64:$src1))
// Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_52(N, X86::MMX_PANDNrr, MVT::v1i64);
+ SDNode *Result = Emit_53(N, X86::MMX_PANDNrr, MVT::v1i64);
return Result;
}
}
@@ -4365,37 +4400,37 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1), VR64:v1i64:$src2)
// Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::BIT_CONVERT &&
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N000.getNode())) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_50(N, X86::MMX_PANDNrr, MVT::v1i64);
+ SDNode *Result = Emit_51(N, X86::MMX_PANDNrr, MVT::v1i64);
return Result;
}
}
}
}
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>)))
// Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N110.getNode()) &&
N110.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_51(N, X86::MMX_PANDNrr, MVT::v1i64);
+ SDNode *Result = Emit_52(N, X86::MMX_PANDNrr, MVT::v1i64);
return Result;
}
}
@@ -4404,13 +4439,13 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 (bitconvert:v1i64 (bitconvert:v4i16)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1))
// Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::BIT_CONVERT &&
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N100.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_52(N, X86::MMX_PANDNrr, MVT::v1i64);
+ SDNode *Result = Emit_53(N, X86::MMX_PANDNrr, MVT::v1i64);
return Result;
}
}
@@ -4421,36 +4456,36 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Pattern: (and:v1i64 (xor:v1i64 (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1), VR64:v1i64:$src2)
// Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::BIT_CONVERT &&
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N000.getNode())) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_50(N, X86::MMX_PANDNrr, MVT::v1i64);
+ SDNode *Result = Emit_51(N, X86::MMX_PANDNrr, MVT::v1i64);
return Result;
}
}
}
}
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>)))
// Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N110.getNode()) &&
N110.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_51(N, X86::MMX_PANDNrr, MVT::v1i64);
+ SDNode *Result = Emit_52(N, X86::MMX_PANDNrr, MVT::v1i64);
return Result;
}
}
@@ -4459,13 +4494,13 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 (bitconvert:v1i64 (bitconvert:v8i8)<<P:Predicate_immAllOnesV_bc>>), VR64:v1i64:$src1))
// Emits: (MMX_PANDNrr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::BIT_CONVERT &&
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllOnesV_bc(N100.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_52(N, X86::MMX_PANDNrr, MVT::v1i64);
+ SDNode *Result = Emit_53(N, X86::MMX_PANDNrr, MVT::v1i64);
return Result;
}
}
@@ -4474,18 +4509,18 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
}
if ((Subtarget->hasMMX())) {
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (and:v1i64 (xor:v1i64 VR64:v1i64:$src1, (build_vector:v1i64)<<P:Predicate_immAllOnesV>>), VR64:v1i64:$src2)
// Emits: (MMX_PANDNrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
// Pattern complexity = 10 cost = 1 size = 3
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N01.getNode())) {
- SDNode *Result = Emit_40(N, X86::MMX_PANDNrr, MVT::v1i64);
+ SDNode *Result = Emit_41(N, X86::MMX_PANDNrr, MVT::v1i64);
return Result;
}
}
@@ -4493,24 +4528,24 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Pattern: (and:v1i64 (xor:v1i64 (build_vector:v1i64)<<P:Predicate_immAllOnesV>>, VR64:v1i64:$src1), VR64:v1i64:$src2)
// Emits: (MMX_PANDNrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
// Pattern complexity = 10 cost = 1 size = 3
- if (N00.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N00.getNode())) {
- SDNode *Result = Emit_44(N, X86::MMX_PANDNrr, MVT::v1i64);
+ SDNode *Result = Emit_45(N, X86::MMX_PANDNrr, MVT::v1i64);
return Result;
}
}
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 VR64:v1i64:$src1, (build_vector:v1i64)<<P:Predicate_immAllOnesV>>))
// Emits: (MMX_PANDNrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
// Pattern complexity = 10 cost = 1 size = 3
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N11.getNode())) {
- SDNode *Result = Emit_45(N, X86::MMX_PANDNrr, MVT::v1i64);
+ SDNode *Result = Emit_46(N, X86::MMX_PANDNrr, MVT::v1i64);
return Result;
}
}
@@ -4518,9 +4553,9 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
// Pattern: (and:v1i64 VR64:v1i64:$src2, (xor:v1i64 (build_vector:v1i64)<<P:Predicate_immAllOnesV>>, VR64:v1i64:$src1))
// Emits: (MMX_PANDNrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
// Pattern complexity = 10 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N10.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N10.getNode())) {
- SDNode *Result = Emit_46(N, X86::MMX_PANDNrr, MVT::v1i64);
+ SDNode *Result = Emit_47(N, X86::MMX_PANDNrr, MVT::v1i64);
return Result;
}
}
@@ -4537,236 +4572,236 @@ SDNode *Select_ISD_AND_v1i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_56(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_57(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { N00, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_57(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_58(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { N000, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_58(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N10);
-}
-DISABLE_INLINE SDNode *Emit_59(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N000, N10);
-}
-DISABLE_INLINE SDNode *Emit_60(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_59(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, N10);
+}
+DISABLE_INLINE SDNode *Emit_60(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N000, N10);
+}
+DISABLE_INLINE SDNode *Emit_61(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { N000, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_61(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
+DISABLE_INLINE SDNode *Emit_62(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { N10, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_62(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_63(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { N010, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_63(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
+DISABLE_INLINE SDNode *Emit_64(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { N100, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_64(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
+DISABLE_INLINE SDNode *Emit_65(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { N110, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_65(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N010, N10);
-}
-DISABLE_INLINE SDNode *Emit_66(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N100, N00);
-}
-DISABLE_INLINE SDNode *Emit_67(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N110, N00);
-}
-DISABLE_INLINE SDNode *Emit_68(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_66(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N010, N10);
+}
+DISABLE_INLINE SDNode *Emit_67(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N100, N00);
+}
+DISABLE_INLINE SDNode *Emit_68(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N110, N00);
+}
+DISABLE_INLINE SDNode *Emit_69(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { N010, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_69(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_70(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { N100, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_70(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
+DISABLE_INLINE SDNode *Emit_71(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { N110, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
+SDNode *Select_ISD_AND_v2i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
// Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (ANDNPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 38 cost = 1 size = 3
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N010.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -4775,7 +4810,7 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N000.getValueType() == MVT::v4f32 &&
N010.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_57(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_58(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -4787,20 +4822,20 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), (bitconvert:v2i64 VR128:v4f32:$src1)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (ANDNPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 38 cost = 1 size = 3
- if (N000.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -4809,7 +4844,7 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N000.getValueType() == MVT::v4i32 &&
N010.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_62(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_63(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -4818,38 +4853,38 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
// Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)))
// Emits: (ANDNPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 38 cost = 1 size = 3
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N110.getNode()) &&
N100.getValueType() == MVT::v4f32 &&
N110.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_63(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_64(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -4858,14 +4893,14 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), (bitconvert:v2i64 VR128:v4f32:$src1)))
// Emits: (ANDNPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 38 cost = 1 size = 3
- if (N100.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
if (N100.getValueType() == MVT::v4i32 &&
N110.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_64(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_65(N, X86::ANDNPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -4877,27 +4912,27 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (build_vector:v2i64)<<P:Predicate_immAllOnesV>>), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (ANDNPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
- if (N00.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N01.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -4905,7 +4940,7 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N000.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_60(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_61(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -4913,20 +4948,20 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
}
}
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N010.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -4938,7 +4973,7 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
if (N010.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_43(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_44(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -4946,7 +4981,7 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
if (N010.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_43(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_44(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -4954,7 +4989,7 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
if (N010.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_43(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_44(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -4967,20 +5002,20 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, (bitconvert:v2i64 VR128:v2f64:$src1)), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (ANDNPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
- if (N00.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N00.getNode())) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -4988,7 +5023,7 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N010.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_68(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_69(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -4996,34 +5031,34 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (build_vector:v2i64)<<P:Predicate_immAllOnesV>>))
// Emits: (ANDNPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N11.getNode()) &&
N100.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_69(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_70(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -5031,13 +5066,13 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, (bitconvert:v2i64 VR128:v2f64:$src1)))
// Emits: (ANDNPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N10.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N10.getNode())) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
if (N110.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_70(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_71(N, X86::ANDNPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -5050,22 +5085,22 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -5073,7 +5108,7 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N000.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_53(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_54(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -5081,35 +5116,35 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)))
// Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N110.getNode()) &&
N110.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_54(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_55(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -5118,13 +5153,13 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
// Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_55(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_56(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -5137,22 +5172,22 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -5160,7 +5195,7 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N000.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_53(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_54(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -5168,35 +5203,35 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>)))
// Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N110.getNode()) &&
N110.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_54(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_55(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -5205,13 +5240,13 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
// Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_55(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_56(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -5224,22 +5259,22 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -5247,7 +5282,7 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N000.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_53(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_54(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -5255,35 +5290,35 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>)))
// Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N110.getNode()) &&
N110.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_54(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_55(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -5292,13 +5327,13 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
// Emits: (PANDNrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 35 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_55(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_56(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -5307,32 +5342,32 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (build_vector:v2i64)<<P:Predicate_immAllOnesV>>), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PANDNrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 32 cost = 1 size = 3
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N01.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_41(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_42(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -5343,57 +5378,57 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, VR128:v2i64:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PANDNrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 32 cost = 1 size = 3
- if (N00.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N00.getNode())) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_47(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_48(N, X86::PANDNrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
}
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 VR128:v2i64:$src1, (build_vector:v2i64)<<P:Predicate_immAllOnesV>>))
// Emits: (PANDNrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 32 cost = 1 size = 3
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N11.getNode())) {
- SDNode *Result = Emit_48(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_49(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -5401,9 +5436,9 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, VR128:v2i64:$src1))
// Emits: (PANDNrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 32 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N10.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N10.getNode())) {
- SDNode *Result = Emit_49(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_50(N, X86::PANDNrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -5416,18 +5451,18 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Emits: (ANDPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -5435,7 +5470,7 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_56(N, X86::ANDPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_57(N, X86::ANDPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -5447,18 +5482,18 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Emits: (ANDPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -5466,7 +5501,7 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N00.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_56(N, X86::ANDPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_57(N, X86::ANDPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -5478,26 +5513,26 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Emits: (ANDPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
if (N10.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_61(N, X86::ANDPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_62(N, X86::ANDPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -5506,30 +5541,30 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v2f64:$src1))
// Emits: (ANDPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
if (N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_61(N, X86::ANDPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_62(N, X86::ANDPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -5541,15 +5576,15 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Emits: (PANDrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -5566,14 +5601,14 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
// Emits: (PANDrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -5588,24 +5623,24 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (build_vector:v2i64)<<P:Predicate_immAllOnesV>>), (bitconvert:v2i64 VR128:v2f64:$src2))
// Emits: (ANDNPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 16 cost = 1 size = 3
- if (N00.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N01.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
if (N000.getValueType() == MVT::v2f64 &&
N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_59(N, X86::ANDNPDrr, MVT::v2i64);
+ SDNode *Result = Emit_60(N, X86::ANDNPDrr, MVT::v2i64);
return Result;
}
}
@@ -5615,40 +5650,40 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, (bitconvert:v2i64 VR128:v2f64:$src1)), (bitconvert:v2i64 VR128:v2f64:$src2))
// Emits: (ANDNPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 16 cost = 1 size = 3
- if (N00.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N00.getNode())) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
if (N010.getValueType() == MVT::v2f64 &&
N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_65(N, X86::ANDNPDrr, MVT::v2i64);
+ SDNode *Result = Emit_66(N, X86::ANDNPDrr, MVT::v2i64);
return Result;
}
}
}
}
}
- if (N0.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v2i64 (bitconvert:v2i64 VR128:v2f64:$src2), (xor:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (build_vector:v2i64)<<P:Predicate_immAllOnesV>>))
// Emits: (ANDNPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 16 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N11.getNode()) &&
N00.getValueType() == MVT::v2f64 &&
N100.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_66(N, X86::ANDNPDrr, MVT::v2i64);
+ SDNode *Result = Emit_67(N, X86::ANDNPDrr, MVT::v2i64);
return Result;
}
}
@@ -5656,14 +5691,14 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 (bitconvert:v2i64 VR128:v2f64:$src2), (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, (bitconvert:v2i64 VR128:v2f64:$src1)))
// Emits: (ANDNPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 16 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N10.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N10.getNode())) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
if (N00.getValueType() == MVT::v2f64 &&
N110.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_67(N, X86::ANDNPDrr, MVT::v2i64);
+ SDNode *Result = Emit_68(N, X86::ANDNPDrr, MVT::v2i64);
return Result;
}
}
@@ -5676,17 +5711,17 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Emits: (ANDNPSrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 13 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N010.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N010.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_42(N, X86::ANDNPSrr, MVT::v2i64);
+ SDNode *Result = Emit_43(N, X86::ANDNPSrr, MVT::v2i64);
return Result;
}
}
@@ -5694,21 +5729,21 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N010.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
// Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)), VR128:v2i64:$src2)
// Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
if (N010.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_42(N, X86::PANDNrr, MVT::v2i64);
+ SDNode *Result = Emit_43(N, X86::PANDNrr, MVT::v2i64);
return Result;
}
@@ -5716,7 +5751,7 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
if (N010.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_42(N, X86::PANDNrr, MVT::v2i64);
+ SDNode *Result = Emit_43(N, X86::PANDNrr, MVT::v2i64);
return Result;
}
@@ -5724,7 +5759,7 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
if (N010.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_42(N, X86::PANDNrr, MVT::v2i64);
+ SDNode *Result = Emit_43(N, X86::PANDNrr, MVT::v2i64);
return Result;
}
}
@@ -5732,41 +5767,41 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), VR128:v2i64:$src2)
// Emits: (ANDNPSrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 13 cost = 1 size = 3
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_50(N, X86::ANDNPSrr, MVT::v2i64);
+ SDNode *Result = Emit_51(N, X86::ANDNPSrr, MVT::v2i64);
return Result;
}
}
}
}
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)))
// Emits: (ANDNPSrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 13 cost = 1 size = 3
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N110.getNode()) &&
N110.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_51(N, X86::ANDNPSrr, MVT::v2i64);
+ SDNode *Result = Emit_52(N, X86::ANDNPSrr, MVT::v2i64);
return Result;
}
}
@@ -5775,13 +5810,13 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
// Emits: (ANDNPSrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 13 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_52(N, X86::ANDNPSrr, MVT::v2i64);
+ SDNode *Result = Emit_53(N, X86::ANDNPSrr, MVT::v2i64);
return Result;
}
}
@@ -5789,42 +5824,42 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), VR128:v2i64:$src2)
// Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_50(N, X86::PANDNrr, MVT::v2i64);
+ SDNode *Result = Emit_51(N, X86::PANDNrr, MVT::v2i64);
return Result;
}
}
}
}
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>)))
// Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N110.getNode()) &&
N110.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_51(N, X86::PANDNrr, MVT::v2i64);
+ SDNode *Result = Emit_52(N, X86::PANDNrr, MVT::v2i64);
return Result;
}
}
@@ -5833,13 +5868,13 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 (bitconvert:v2i64 (build_vector:v4i32)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
// Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_52(N, X86::PANDNrr, MVT::v2i64);
+ SDNode *Result = Emit_53(N, X86::PANDNrr, MVT::v2i64);
return Result;
}
}
@@ -5850,37 +5885,37 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), VR128:v2i64:$src2)
// Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_50(N, X86::PANDNrr, MVT::v2i64);
+ SDNode *Result = Emit_51(N, X86::PANDNrr, MVT::v2i64);
return Result;
}
}
}
}
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>)))
// Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N110.getNode()) &&
N110.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_51(N, X86::PANDNrr, MVT::v2i64);
+ SDNode *Result = Emit_52(N, X86::PANDNrr, MVT::v2i64);
return Result;
}
}
@@ -5889,13 +5924,13 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 (bitconvert:v2i64 (build_vector:v8i16)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
// Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_52(N, X86::PANDNrr, MVT::v2i64);
+ SDNode *Result = Emit_53(N, X86::PANDNrr, MVT::v2i64);
return Result;
}
}
@@ -5906,37 +5941,37 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 (xor:v2i64 (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1), VR128:v2i64:$src2)
// Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N000.getNode())) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_50(N, X86::PANDNrr, MVT::v2i64);
+ SDNode *Result = Emit_51(N, X86::PANDNrr, MVT::v2i64);
return Result;
}
}
}
}
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 VR128:v2i64:$src1, (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>)))
// Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N110.getNode()) &&
N110.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_51(N, X86::PANDNrr, MVT::v2i64);
+ SDNode *Result = Emit_52(N, X86::PANDNrr, MVT::v2i64);
return Result;
}
}
@@ -5945,30 +5980,30 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 (bitconvert:v2i64 (build_vector:v16i8)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src1))
// Emits: (PANDNrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 13 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N100.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_52(N, X86::PANDNrr, MVT::v2i64);
+ SDNode *Result = Emit_53(N, X86::PANDNrr, MVT::v2i64);
return Result;
}
}
}
}
}
- if (N0.getOpcode() == ISD::XOR) {
- SDValue N00 = N0.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
// Pattern: (and:v2i64 (xor:v2i64 VR128:v2i64:$src1, (build_vector:v2i64)<<P:Predicate_immAllOnesV>>), VR128:v2i64:$src2)
// Emits: (PANDNrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 10 cost = 1 size = 3
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N01.getNode())) {
- SDNode *Result = Emit_40(N, X86::PANDNrr, MVT::v2i64);
+ SDNode *Result = Emit_41(N, X86::PANDNrr, MVT::v2i64);
return Result;
}
}
@@ -5976,25 +6011,25 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, VR128:v2i64:$src1), VR128:v2i64:$src2)
// Emits: (PANDNrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 10 cost = 1 size = 3
- if (N00.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N00.getNode())) {
- SDNode *Result = Emit_44(N, X86::PANDNrr, MVT::v2i64);
+ SDNode *Result = Emit_45(N, X86::PANDNrr, MVT::v2i64);
return Result;
}
}
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::XOR) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::XOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 VR128:v2i64:$src1, (build_vector:v2i64)<<P:Predicate_immAllOnesV>>))
// Emits: (PANDNrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 10 cost = 1 size = 3
{
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N11.getNode())) {
- SDNode *Result = Emit_45(N, X86::PANDNrr, MVT::v2i64);
+ SDNode *Result = Emit_46(N, X86::PANDNrr, MVT::v2i64);
return Result;
}
}
@@ -6002,9 +6037,9 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 VR128:v2i64:$src2, (xor:v2i64 (build_vector:v2i64)<<P:Predicate_immAllOnesV>>, VR128:v2i64:$src1))
// Emits: (PANDNrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 10 cost = 1 size = 3
- if (N10.getOpcode() == ISD::BUILD_VECTOR &&
+ if (N10.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllOnesV(N10.getNode())) {
- SDNode *Result = Emit_46(N, X86::PANDNrr, MVT::v2i64);
+ SDNode *Result = Emit_47(N, X86::PANDNrr, MVT::v2i64);
return Result;
}
}
@@ -6013,14 +6048,14 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
// Pattern: (and:v2i64 (bitconvert:v2i64 VR128:v2f64:$src1), (bitconvert:v2i64 VR128:v2f64:$src2))
// Emits: (ANDPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 9 cost = 1 size = 3
- if (N0.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
if (N00.getValueType() == MVT::v2f64 &&
N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_58(N, X86::ANDPDrr, MVT::v2i64);
+ SDNode *Result = Emit_59(N, X86::ANDPDrr, MVT::v2i64);
return Result;
}
}
@@ -6047,36 +6082,36 @@ SDNode *Select_ISD_AND_v2i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_71(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0);
+DISABLE_INLINE SDNode *Emit_72(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0);
}
-DISABLE_INLINE SDNode *Emit_72(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+DISABLE_INLINE SDNode *Emit_73(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue Chain = CurDAG->getEntryNode();
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N0.getDebugLoc(), X86::EFLAGS, N01, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N0.getNode()->getDebugLoc(), X86::EFLAGS, N01, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, InFlag);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, InFlag);
}
-SDNode *Select_ISD_ANY_EXTEND_i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_ANY_EXTEND_i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (anyext:i16 (X86setcc_c:i8 2:i8, EFLAGS:i32))
// Emits: (SETB_C16r:i16)
// Pattern complexity = 11 cost = 1 size = 3
- if (N0.getOpcode() == X86ISD::SETCC_CARRY) {
- SDValue N00 = N0.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ if (N0.getNode()->getOpcode() == X86ISD::SETCC_CARRY) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_72(N, X86::SETB_C16r, MVT::i16);
+ SDNode *Result = Emit_73(N, X86::SETB_C16r, MVT::i16);
return Result;
}
}
@@ -6087,7 +6122,7 @@ SDNode *Select_ISD_ANY_EXTEND_i16(const SDValue &N) {
// Emits: (MOVZX16rr8:i16 GR8:i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_71(N, X86::MOVZX16rr8, MVT::i16);
+ SDNode *Result = Emit_72(N, X86::MOVZX16rr8, MVT::i16);
return Result;
}
@@ -6095,34 +6130,34 @@ SDNode *Select_ISD_ANY_EXTEND_i16(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_73(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+DISABLE_INLINE SDNode *Emit_74(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N00, Tmp3), 0);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N00, Tmp3), 0);
SDValue Tmp5 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
- SDValue Tmp6(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp4, Tmp5), 0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc2, VT2, Tmp6);
+ SDValue Tmp6(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp4, Tmp5), 0);
+ return CurDAG->SelectNodeTo(N, Opc2, VT2, Tmp6);
}
-SDNode *Select_ISD_ANY_EXTEND_i32(const SDValue &N) {
+SDNode *Select_ISD_ANY_EXTEND_i32(SDNode *N) {
// Pattern: (anyext:i32 (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>)
// Emits: (MOVZX32rr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32))
// Pattern complexity = 12 cost = 3 size = 3
if ((!Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SRL &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRL &&
Predicate_srl_su(N0.getNode())) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(8) &&
N0.getValueType() == MVT::i16 &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_73(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i16, MVT::i8, MVT::i32);
+ SDNode *Result = Emit_74(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i16, MVT::i8, MVT::i32);
return Result;
}
}
@@ -6133,37 +6168,37 @@ SDNode *Select_ISD_ANY_EXTEND_i32(const SDValue &N) {
// Emits: (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32))
// Pattern complexity = 12 cost = 3 size = 3
if ((Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SRL &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRL &&
Predicate_srl_su(N0.getNode())) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(8) &&
N0.getValueType() == MVT::i16 &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_73(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, MVT::i16, MVT::i8, MVT::i32);
+ SDNode *Result = Emit_74(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, MVT::i16, MVT::i8, MVT::i32);
return Result;
}
}
}
}
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (anyext:i32 (X86setcc_c:i8 2:i8, EFLAGS:i32))
// Emits: (SETB_C32r:i32)
// Pattern complexity = 11 cost = 1 size = 3
- if (N0.getOpcode() == X86ISD::SETCC_CARRY) {
- SDValue N00 = N0.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ if (N0.getNode()->getOpcode() == X86ISD::SETCC_CARRY) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_72(N, X86::SETB_C32r, MVT::i32);
+ SDNode *Result = Emit_73(N, X86::SETB_C32r, MVT::i32);
return Result;
}
}
@@ -6174,7 +6209,7 @@ SDNode *Select_ISD_ANY_EXTEND_i32(const SDValue &N) {
// Emits: (MOVZX32rr8:i32 GR8:i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_71(N, X86::MOVZX32rr8, MVT::i32);
+ SDNode *Result = Emit_72(N, X86::MOVZX32rr8, MVT::i32);
return Result;
}
@@ -6182,7 +6217,7 @@ SDNode *Select_ISD_ANY_EXTEND_i32(const SDValue &N) {
// Emits: (MOVZX32rr16:i32 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_71(N, X86::MOVZX32rr16, MVT::i32);
+ SDNode *Result = Emit_72(N, X86::MOVZX32rr16, MVT::i32);
return Result;
}
@@ -6190,42 +6225,42 @@ SDNode *Select_ISD_ANY_EXTEND_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_74(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
+DISABLE_INLINE SDNode *Emit_75(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
SDValue Tmp0 = CurDAG->getTargetConstant(0x0ULL, MVT::i64);
SDValue Tmp2 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0, N0, Tmp2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp0, N0, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_75(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+DISABLE_INLINE SDNode *Emit_76(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(0x0ULL, MVT::i64);
SDValue Tmp4 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N00, Tmp4), 0);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N00, Tmp4), 0);
SDValue Tmp6 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
- SDValue Tmp7(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp5, Tmp6), 0);
- SDValue Tmp8(CurDAG->getMachineNode(Opc2, N.getDebugLoc(), VT2, Tmp7), 0);
+ SDValue Tmp7(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp5, Tmp6), 0);
+ SDValue Tmp8(CurDAG->getMachineNode(Opc2, N->getDebugLoc(), VT2, Tmp7), 0);
SDValue Tmp9 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc3, VT3, Tmp2, Tmp8, Tmp9);
+ return CurDAG->SelectNodeTo(N, Opc3, VT3, Tmp2, Tmp8, Tmp9);
}
-SDNode *Select_ISD_ANY_EXTEND_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_ANY_EXTEND_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (anyext:i64 (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>)
// Emits: (SUBREG_TO_REG:i64 0:i64, (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32)), 4:i32)
// Pattern complexity = 12 cost = 4 size = 3
- if (N0.getOpcode() == ISD::SRL &&
+ if (N0.getNode()->getOpcode() == ISD::SRL &&
Predicate_srl_su(N0.getNode())) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(8) &&
N0.getValueType() == MVT::i16 &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_75(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetInstrInfo::SUBREG_TO_REG, MVT::i16, MVT::i8, MVT::i32, MVT::i64);
+ SDNode *Result = Emit_76(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetInstrInfo::SUBREG_TO_REG, MVT::i16, MVT::i8, MVT::i32, MVT::i64);
return Result;
}
}
@@ -6234,15 +6269,15 @@ SDNode *Select_ISD_ANY_EXTEND_i64(const SDValue &N) {
// Pattern: (anyext:i64 (X86setcc_c:i8 2:i8, EFLAGS:i32))
// Emits: (SETB_C64r:i64)
// Pattern complexity = 11 cost = 1 size = 3
- if (N0.getOpcode() == X86ISD::SETCC_CARRY) {
- SDValue N00 = N0.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00);
+ if (N0.getNode()->getOpcode() == X86ISD::SETCC_CARRY) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N00.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_72(N, X86::SETB_C64r, MVT::i64);
+ SDNode *Result = Emit_73(N, X86::SETB_C64r, MVT::i64);
return Result;
}
}
@@ -6253,7 +6288,7 @@ SDNode *Select_ISD_ANY_EXTEND_i64(const SDValue &N) {
// Emits: (SUBREG_TO_REG:i64 0:i64, GR32:i32:$src, 4:i32)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_74(N, TargetInstrInfo::SUBREG_TO_REG, MVT::i64);
+ SDNode *Result = Emit_75(N, TargetInstrInfo::SUBREG_TO_REG, MVT::i64);
return Result;
}
@@ -6261,7 +6296,7 @@ SDNode *Select_ISD_ANY_EXTEND_i64(const SDValue &N) {
// Emits: (MOVZX64rr8:i64 GR8:i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_71(N, X86::MOVZX64rr8, MVT::i64);
+ SDNode *Result = Emit_72(N, X86::MOVZX64rr8, MVT::i64);
return Result;
}
@@ -6269,7 +6304,7 @@ SDNode *Select_ISD_ANY_EXTEND_i64(const SDValue &N) {
// Emits: (MOVZX64rr16:i64 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_71(N, X86::MOVZX64rr16, MVT::i64);
+ SDNode *Result = Emit_72(N, X86::MOVZX64rr16, MVT::i64);
return Result;
}
@@ -6277,28 +6312,28 @@ SDNode *Select_ISD_ANY_EXTEND_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_76(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_77(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { N2, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-SDNode *Select_ISD_ATOMIC_LOAD_ADD_i8(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_add_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_ADD_i8(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_add_8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::LXADD8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::LXADD8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6307,17 +6342,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_ADD_i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_ADD_i16(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_add_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_ADD_i16(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_add_16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::LXADD16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::LXADD16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6326,17 +6361,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_ADD_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_ADD_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_add_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_ADD_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_add_32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::LXADD32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::LXADD32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6345,17 +6380,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_ADD_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_ADD_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_add_64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_ADD_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_add_64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::LXADD64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::LXADD64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6364,28 +6399,28 @@ SDNode *Select_ISD_ATOMIC_LOAD_ADD_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_77(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_78(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, N2, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-SDNode *Select_ISD_ATOMIC_LOAD_AND_i8(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_and_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_AND_i8(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_and_8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMAND8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMAND8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6394,17 +6429,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_AND_i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_AND_i16(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_and_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_AND_i16(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_and_16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMAND16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMAND16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6413,17 +6448,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_AND_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_AND_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_and_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_AND_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_and_32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMAND32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMAND32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6432,17 +6467,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_AND_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_AND_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_and_64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_AND_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_and_64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMAND64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMAND64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6451,17 +6486,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_AND_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_MAX_i16(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_max_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_MAX_i16(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_max_16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMMAX16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMMAX16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6470,17 +6505,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_MAX_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_MAX_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_max_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_MAX_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_max_32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMMAX32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMMAX32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6489,17 +6524,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_MAX_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_MAX_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_max_64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_MAX_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_max_64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMMAX64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMMAX64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6508,17 +6543,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_MAX_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_MIN_i16(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_min_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_MIN_i16(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_min_16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMMIN16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMMIN16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6527,17 +6562,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_MIN_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_MIN_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_min_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_MIN_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_min_32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMMIN32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMMIN32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6546,17 +6581,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_MIN_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_MIN_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_min_64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_MIN_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_min_64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMMIN64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMMIN64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6565,17 +6600,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_MIN_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_NAND_i8(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_nand_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_NAND_i8(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_nand_8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMNAND8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMNAND8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6584,17 +6619,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_NAND_i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_NAND_i16(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_nand_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_NAND_i16(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_nand_16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMNAND16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMNAND16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6603,17 +6638,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_NAND_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_NAND_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_nand_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_NAND_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_nand_32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMNAND32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMNAND32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6622,17 +6657,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_NAND_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_NAND_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_nand_64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_NAND_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_nand_64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMNAND64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMNAND64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6641,17 +6676,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_NAND_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_OR_i8(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_or_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_OR_i8(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_or_8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMOR8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMOR8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6660,17 +6695,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_OR_i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_OR_i16(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_or_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_OR_i16(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_or_16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMOR16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMOR16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6679,17 +6714,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_OR_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_OR_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_or_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_OR_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_or_32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMOR32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMOR32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6698,17 +6733,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_OR_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_OR_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_or_64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_OR_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_or_64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMOR64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMOR64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6717,17 +6752,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_OR_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_UMAX_i16(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_umax_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_UMAX_i16(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_umax_16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMUMAX16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMUMAX16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6736,17 +6771,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_UMAX_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_UMAX_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_umax_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_UMAX_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_umax_32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMUMAX32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMUMAX32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6755,17 +6790,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_UMAX_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_UMAX_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_umax_64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_UMAX_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_umax_64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMUMAX64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMUMAX64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6774,17 +6809,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_UMAX_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_UMIN_i16(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_umin_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_UMIN_i16(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_umin_16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMUMIN16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMUMIN16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6793,17 +6828,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_UMIN_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_UMIN_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_umin_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_UMIN_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_umin_32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMUMIN32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMUMIN32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6812,17 +6847,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_UMIN_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_UMIN_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_umin_64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_UMIN_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_umin_64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMUMIN64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMUMIN64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6831,17 +6866,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_UMIN_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_XOR_i8(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_xor_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_XOR_i8(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_xor_8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMXOR8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMXOR8, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6850,17 +6885,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_XOR_i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_XOR_i16(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_xor_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_XOR_i16(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_xor_16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMXOR16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMXOR16, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6869,17 +6904,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_XOR_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_XOR_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_xor_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_XOR_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_xor_32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMXOR32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMXOR32, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6888,17 +6923,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_XOR_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_LOAD_XOR_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_load_xor_64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_LOAD_XOR_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_load_xor_64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_77(N, X86::ATOMXOR64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_78(N, X86::ATOMXOR64, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6907,17 +6942,17 @@ SDNode *Select_ISD_ATOMIC_LOAD_XOR_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_SWAP_i8(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_swap_8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_SWAP_i8(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_swap_8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::XCHG8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::XCHG8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6926,17 +6961,17 @@ SDNode *Select_ISD_ATOMIC_SWAP_i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_SWAP_i16(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_swap_16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_SWAP_i16(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_swap_16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::XCHG16rm, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::XCHG16rm, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6945,17 +6980,17 @@ SDNode *Select_ISD_ATOMIC_SWAP_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_SWAP_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_swap_32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_SWAP_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_swap_32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::XCHG32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::XCHG32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6964,17 +6999,17 @@ SDNode *Select_ISD_ATOMIC_SWAP_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ATOMIC_SWAP_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_atomic_swap_64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ATOMIC_SWAP_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_atomic_swap_64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_76(N, X86::XCHG64rm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_77(N, X86::XCHG64rm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -6983,11 +7018,11 @@ SDNode *Select_ISD_ATOMIC_SWAP_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_i32(const SDValue &N) {
+SDNode *Select_ISD_BIT_CONVERT_i32(SDNode *N) {
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_71(N, X86::MOVSS2DIrr, MVT::i32);
+ SDNode *Result = Emit_72(N, X86::MOVSS2DIrr, MVT::i32);
return Result;
}
}
@@ -6996,25 +7031,25 @@ SDNode *Select_ISD_BIT_CONVERT_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_i64(const SDValue &N) {
+SDNode *Select_ISD_BIT_CONVERT_i64(SDNode *N) {
// Pattern: (bitconvert:i64 FR64:f64:$src)
// Emits: (MOVSDto64rr:i64 FR64:f64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_71(N, X86::MOVSDto64rr, MVT::i64);
+ SDNode *Result = Emit_72(N, X86::MOVSDto64rr, MVT::i64);
return Result;
}
}
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:i64 VR64:v1i64:$src)
// Emits: (MMX_MOVD64from64rr:i64 VR64:v8i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_71(N, X86::MMX_MOVD64from64rr, MVT::i64);
+ SDNode *Result = Emit_72(N, X86::MMX_MOVD64from64rr, MVT::i64);
return Result;
}
@@ -7022,7 +7057,7 @@ SDNode *Select_ISD_BIT_CONVERT_i64(const SDValue &N) {
// Emits: (MMX_MOVD64from64rr:i64 VR64:v8i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_71(N, X86::MMX_MOVD64from64rr, MVT::i64);
+ SDNode *Result = Emit_72(N, X86::MMX_MOVD64from64rr, MVT::i64);
return Result;
}
@@ -7030,7 +7065,7 @@ SDNode *Select_ISD_BIT_CONVERT_i64(const SDValue &N) {
// Emits: (MMX_MOVD64from64rr:i64 VR64:v8i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_71(N, X86::MMX_MOVD64from64rr, MVT::i64);
+ SDNode *Result = Emit_72(N, X86::MMX_MOVD64from64rr, MVT::i64);
return Result;
}
@@ -7038,7 +7073,7 @@ SDNode *Select_ISD_BIT_CONVERT_i64(const SDValue &N) {
// Emits: (MMX_MOVD64from64rr:i64 VR64:v8i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_71(N, X86::MMX_MOVD64from64rr, MVT::i64);
+ SDNode *Result = Emit_72(N, X86::MMX_MOVD64from64rr, MVT::i64);
return Result;
}
@@ -7046,7 +7081,7 @@ SDNode *Select_ISD_BIT_CONVERT_i64(const SDValue &N) {
// Emits: (MMX_MOVD64from64rr:i64 VR64:v8i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_71(N, X86::MMX_MOVD64from64rr, MVT::i64);
+ SDNode *Result = Emit_72(N, X86::MMX_MOVD64from64rr, MVT::i64);
return Result;
}
@@ -7054,32 +7089,32 @@ SDNode *Select_ISD_BIT_CONVERT_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_78(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+DISABLE_INLINE SDNode *Emit_79(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_ISD_BIT_CONVERT_f32(const SDValue &N) {
+SDNode *Select_ISD_BIT_CONVERT_f32(SDNode *N) {
// Pattern: (bitconvert:f32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
// Emits: (MOVDI2SSrm:f32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -7087,7 +7122,7 @@ SDNode *Select_ISD_BIT_CONVERT_f32(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_78(N, X86::MOVDI2SSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::MOVDI2SSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -7098,9 +7133,9 @@ SDNode *Select_ISD_BIT_CONVERT_f32(const SDValue &N) {
// Emits: (MOVDI2SSrr:f32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_71(N, X86::MOVDI2SSrr, MVT::f32);
+ SDNode *Result = Emit_72(N, X86::MOVDI2SSrr, MVT::f32);
return Result;
}
}
@@ -7109,21 +7144,21 @@ SDNode *Select_ISD_BIT_CONVERT_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_f64(const SDValue &N) {
+SDNode *Select_ISD_BIT_CONVERT_f64(SDNode *N) {
// Pattern: (bitconvert:f64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
// Emits: (MOV64toSDrm:f64 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -7131,7 +7166,7 @@ SDNode *Select_ISD_BIT_CONVERT_f64(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_78(N, X86::MOV64toSDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::MOV64toSDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -7142,19 +7177,19 @@ SDNode *Select_ISD_BIT_CONVERT_f64(const SDValue &N) {
// Emits: (MOV64toSDrr:f64 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_71(N, X86::MOV64toSDrr, MVT::f64);
+ SDNode *Result = Emit_72(N, X86::MOV64toSDrr, MVT::f64);
return Result;
}
}
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:f64 VR64:v1i64:$src)
// Emits: (MMX_MOVQ2FR64rr:f64 VR64:v8i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_71(N, X86::MMX_MOVQ2FR64rr, MVT::f64);
+ SDNode *Result = Emit_72(N, X86::MMX_MOVQ2FR64rr, MVT::f64);
return Result;
}
@@ -7162,7 +7197,7 @@ SDNode *Select_ISD_BIT_CONVERT_f64(const SDValue &N) {
// Emits: (MMX_MOVQ2FR64rr:f64 VR64:v8i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_71(N, X86::MMX_MOVQ2FR64rr, MVT::f64);
+ SDNode *Result = Emit_72(N, X86::MMX_MOVQ2FR64rr, MVT::f64);
return Result;
}
@@ -7170,7 +7205,7 @@ SDNode *Select_ISD_BIT_CONVERT_f64(const SDValue &N) {
// Emits: (MMX_MOVQ2FR64rr:f64 VR64:v8i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_71(N, X86::MMX_MOVQ2FR64rr, MVT::f64);
+ SDNode *Result = Emit_72(N, X86::MMX_MOVQ2FR64rr, MVT::f64);
return Result;
}
@@ -7178,7 +7213,7 @@ SDNode *Select_ISD_BIT_CONVERT_f64(const SDValue &N) {
// Emits: (MMX_MOVQ2FR64rr:f64 VR64:v8i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_71(N, X86::MMX_MOVQ2FR64rr, MVT::f64);
+ SDNode *Result = Emit_72(N, X86::MMX_MOVQ2FR64rr, MVT::f64);
return Result;
}
@@ -7186,33 +7221,33 @@ SDNode *Select_ISD_BIT_CONVERT_f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_79(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- ReplaceUses(N, N0);
+DISABLE_INLINE SDNode *Emit_80(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ ReplaceUses(SDValue(N, 0), N0);
return NULL;
}
-DISABLE_INLINE SDNode *Emit_80(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00);
+DISABLE_INLINE SDNode *Emit_81(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N00);
}
-SDNode *Select_ISD_BIT_CONVERT_v8i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_BIT_CONVERT_v8i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v8i8 (vector_extract:i64 VR128:v2i64:$src, 0:iPTR))
// Emits: (MMX_MOVDQ2Qrr:v8i8 VR128:v16i8:$src)
// Pattern complexity = 11 cost = 1 size = 3
- if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N0.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64 &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_80(N, X86::MMX_MOVDQ2Qrr, MVT::v8i8);
+ SDNode *Result = Emit_81(N, X86::MMX_MOVDQ2Qrr, MVT::v8i8);
return Result;
}
}
@@ -7222,7 +7257,7 @@ SDNode *Select_ISD_BIT_CONVERT_v8i8(const SDValue &N) {
// Emits: VR64:v8i8:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7230,7 +7265,7 @@ SDNode *Select_ISD_BIT_CONVERT_v8i8(const SDValue &N) {
// Emits: VR64:v8i8:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7238,7 +7273,7 @@ SDNode *Select_ISD_BIT_CONVERT_v8i8(const SDValue &N) {
// Emits: VR64:v8i8:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7246,7 +7281,7 @@ SDNode *Select_ISD_BIT_CONVERT_v8i8(const SDValue &N) {
// Emits: VR64:v8i8:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7254,7 +7289,7 @@ SDNode *Select_ISD_BIT_CONVERT_v8i8(const SDValue &N) {
// Emits: (MMX_MOVD64to64rr:v8i8 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_71(N, X86::MMX_MOVD64to64rr, MVT::v8i8);
+ SDNode *Result = Emit_72(N, X86::MMX_MOVD64to64rr, MVT::v8i8);
return Result;
}
@@ -7262,15 +7297,15 @@ SDNode *Select_ISD_BIT_CONVERT_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v16i8(const SDValue &N) {
+SDNode *Select_ISD_BIT_CONVERT_v16i8(SDNode *N) {
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v16i8 VR128:v2i64:$src)
// Emits: VR128:v16i8:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7278,7 +7313,7 @@ SDNode *Select_ISD_BIT_CONVERT_v16i8(const SDValue &N) {
// Emits: VR128:v16i8:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7286,7 +7321,7 @@ SDNode *Select_ISD_BIT_CONVERT_v16i8(const SDValue &N) {
// Emits: VR128:v16i8:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7294,7 +7329,7 @@ SDNode *Select_ISD_BIT_CONVERT_v16i8(const SDValue &N) {
// Emits: VR128:v16i8:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7302,7 +7337,7 @@ SDNode *Select_ISD_BIT_CONVERT_v16i8(const SDValue &N) {
// Emits: VR128:v16i8:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
}
@@ -7311,22 +7346,22 @@ SDNode *Select_ISD_BIT_CONVERT_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v4i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_BIT_CONVERT_v4i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v4i16 (vector_extract:i64 VR128:v2i64:$src, 0:iPTR))
// Emits: (MMX_MOVDQ2Qrr:v4i16 VR128:v16i8:$src)
// Pattern complexity = 11 cost = 1 size = 3
- if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N0.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64 &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_80(N, X86::MMX_MOVDQ2Qrr, MVT::v4i16);
+ SDNode *Result = Emit_81(N, X86::MMX_MOVDQ2Qrr, MVT::v4i16);
return Result;
}
}
@@ -7336,7 +7371,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4i16(const SDValue &N) {
// Emits: VR64:v4i16:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7344,7 +7379,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4i16(const SDValue &N) {
// Emits: VR64:v4i16:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7352,7 +7387,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4i16(const SDValue &N) {
// Emits: VR64:v4i16:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7360,7 +7395,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4i16(const SDValue &N) {
// Emits: VR64:v4i16:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7368,7 +7403,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4i16(const SDValue &N) {
// Emits: (MMX_MOVD64to64rr:v4i16 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_71(N, X86::MMX_MOVD64to64rr, MVT::v4i16);
+ SDNode *Result = Emit_72(N, X86::MMX_MOVD64to64rr, MVT::v4i16);
return Result;
}
@@ -7376,15 +7411,15 @@ SDNode *Select_ISD_BIT_CONVERT_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v8i16(const SDValue &N) {
+SDNode *Select_ISD_BIT_CONVERT_v8i16(SDNode *N) {
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v8i16 VR128:v2i64:$src)
// Emits: VR128:v8i16:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7392,7 +7427,7 @@ SDNode *Select_ISD_BIT_CONVERT_v8i16(const SDValue &N) {
// Emits: VR128:v8i16:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7400,7 +7435,7 @@ SDNode *Select_ISD_BIT_CONVERT_v8i16(const SDValue &N) {
// Emits: VR128:v8i16:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7408,7 +7443,7 @@ SDNode *Select_ISD_BIT_CONVERT_v8i16(const SDValue &N) {
// Emits: VR128:v8i16:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7416,7 +7451,7 @@ SDNode *Select_ISD_BIT_CONVERT_v8i16(const SDValue &N) {
// Emits: VR128:v8i16:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
}
@@ -7425,44 +7460,44 @@ SDNode *Select_ISD_BIT_CONVERT_v8i16(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_81(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0101_0, SDValue &CPTmpN0101_1, SDValue &CPTmpN0101_2, SDValue &CPTmpN0101_3, SDValue &CPTmpN0101_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue Chain010 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
+DISABLE_INLINE SDNode *Emit_82(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0101_0, SDValue &CPTmpN0101_1, SDValue &CPTmpN0101_2, SDValue &CPTmpN0101_3, SDValue &CPTmpN0101_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue Chain010 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N010)->getMemOperand();
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, N0101, N0101, Chain010);
+ MemRefs0[0] = cast<MemSDNode>(N010.getNode())->getMemOperand();
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, N0101, N0101, Chain010);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N010.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_ISD_BIT_CONVERT_v2i32(const SDValue &N) {
+SDNode *Select_ISD_BIT_CONVERT_v2i32(SDNode *N) {
// Pattern: (bitconvert:v2i32 (vector_shuffle:v2i32 (build_vector:v2i32)<<P:Predicate_immAllZerosV>>, (scalar_to_vector:v2i32 (ld:v1i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckl>>)
// Emits: (MMX_PUNPCKLDQrm:v2i32 VR64:v8i8:$src, VR64:v8i8:$src)
// Pattern complexity = 56 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::VECTOR_SHUFFLE &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE &&
N0.hasOneUse() &&
Predicate_mmx_unpckl(N0.getNode())) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::BUILD_VECTOR &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllZerosV(N00.getNode())) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N01.hasOneUse()) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::LOAD &&
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::LOAD &&
N010.hasOneUse() &&
- IsLegalAndProfitableToFold(N010.getNode(), N01.getNode(), N.getNode())) {
- SDValue Chain010 = N010.getOperand(0);
+ IsLegalAndProfitableToFold(N010.getNode(), N01.getNode(), N)) {
+ SDValue Chain010 = N010.getNode()->getOperand(0);
if (Predicate_unindexedload(N010.getNode()) &&
Predicate_load(N010.getNode())) {
- SDValue N0101 = N010.getOperand(1);
+ SDValue N0101 = N010.getNode()->getOperand(1);
SDValue CPTmpN0101_0;
SDValue CPTmpN0101_1;
SDValue CPTmpN0101_2;
@@ -7471,7 +7506,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i32(const SDValue &N) {
if (SelectAddr(N, N0101, CPTmpN0101_0, CPTmpN0101_1, CPTmpN0101_2, CPTmpN0101_3, CPTmpN0101_4) &&
N0.getValueType() == MVT::v2i32 &&
N010.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_81(N, X86::MMX_PUNPCKLDQrm, MVT::v2i32, CPTmpN0101_0, CPTmpN0101_1, CPTmpN0101_2, CPTmpN0101_3, CPTmpN0101_4);
+ SDNode *Result = Emit_82(N, X86::MMX_PUNPCKLDQrm, MVT::v2i32, CPTmpN0101_0, CPTmpN0101_1, CPTmpN0101_2, CPTmpN0101_3, CPTmpN0101_4);
return Result;
}
}
@@ -7480,21 +7515,21 @@ SDNode *Select_ISD_BIT_CONVERT_v2i32(const SDValue &N) {
}
}
}
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v2i32 (vector_extract:i64 VR128:v2i64:$src, 0:iPTR))
// Emits: (MMX_MOVDQ2Qrr:v2i32 VR128:v16i8:$src)
// Pattern complexity = 11 cost = 1 size = 3
- if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ if (N0.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64 &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_80(N, X86::MMX_MOVDQ2Qrr, MVT::v2i32);
+ SDNode *Result = Emit_81(N, X86::MMX_MOVDQ2Qrr, MVT::v2i32);
return Result;
}
}
@@ -7504,7 +7539,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i32(const SDValue &N) {
// Emits: VR64:v2i32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7512,7 +7547,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i32(const SDValue &N) {
// Emits: VR64:v2i32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7520,7 +7555,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i32(const SDValue &N) {
// Emits: VR64:v2i32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7528,7 +7563,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i32(const SDValue &N) {
// Emits: VR64:v2i32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7536,7 +7571,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i32(const SDValue &N) {
// Emits: (MMX_MOVD64to64rr:v2i32 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_71(N, X86::MMX_MOVD64to64rr, MVT::v2i32);
+ SDNode *Result = Emit_72(N, X86::MMX_MOVD64to64rr, MVT::v2i32);
return Result;
}
@@ -7544,15 +7579,15 @@ SDNode *Select_ISD_BIT_CONVERT_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v4i32(const SDValue &N) {
+SDNode *Select_ISD_BIT_CONVERT_v4i32(SDNode *N) {
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v4i32 VR128:v2i64:$src)
// Emits: VR128:v4i32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7560,7 +7595,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4i32(const SDValue &N) {
// Emits: VR128:v4i32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7568,7 +7603,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4i32(const SDValue &N) {
// Emits: VR128:v4i32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7576,7 +7611,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4i32(const SDValue &N) {
// Emits: VR128:v4i32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7584,7 +7619,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4i32(const SDValue &N) {
// Emits: VR128:v4i32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
}
@@ -7593,35 +7628,35 @@ SDNode *Select_ISD_BIT_CONVERT_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v1i64(const SDValue &N) {
+SDNode *Select_ISD_BIT_CONVERT_v1i64(SDNode *N) {
// Pattern: (bitconvert:v1i64 (vector_extract:i64 VR128:v2i64:$src, 0:iPTR))
// Emits: (MMX_MOVDQ2Qrr:v1i64 VR128:v2i64:$src)
// Pattern complexity = 11 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64 &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_80(N, X86::MMX_MOVDQ2Qrr, MVT::v1i64);
+ SDNode *Result = Emit_81(N, X86::MMX_MOVDQ2Qrr, MVT::v1i64);
return Result;
}
}
}
}
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v1i64 VR64:v2i32:$src)
// Emits: VR64:v1i64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7629,7 +7664,7 @@ SDNode *Select_ISD_BIT_CONVERT_v1i64(const SDValue &N) {
// Emits: VR64:v1i64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7637,7 +7672,7 @@ SDNode *Select_ISD_BIT_CONVERT_v1i64(const SDValue &N) {
// Emits: VR64:v1i64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7645,7 +7680,7 @@ SDNode *Select_ISD_BIT_CONVERT_v1i64(const SDValue &N) {
// Emits: VR64:v1i64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7653,7 +7688,7 @@ SDNode *Select_ISD_BIT_CONVERT_v1i64(const SDValue &N) {
// Emits: (MMX_MOVD64to64rr:v1i64 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_71(N, X86::MMX_MOVD64to64rr, MVT::v1i64);
+ SDNode *Result = Emit_72(N, X86::MMX_MOVD64to64rr, MVT::v1i64);
return Result;
}
@@ -7661,15 +7696,15 @@ SDNode *Select_ISD_BIT_CONVERT_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v2i64(const SDValue &N) {
+SDNode *Select_ISD_BIT_CONVERT_v2i64(SDNode *N) {
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v2i64 VR128:v4i32:$src)
// Emits: VR128:v2i64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7677,7 +7712,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i64(const SDValue &N) {
// Emits: VR128:v2i64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7685,7 +7720,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i64(const SDValue &N) {
// Emits: VR128:v2i64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7693,7 +7728,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i64(const SDValue &N) {
// Emits: VR128:v2i64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7701,7 +7736,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2i64(const SDValue &N) {
// Emits: VR128:v2i64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
}
@@ -7710,14 +7745,14 @@ SDNode *Select_ISD_BIT_CONVERT_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v2f32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_BIT_CONVERT_v2f32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v2f32 VR64:v1i64:$src)
// Emits: VR64:v2f32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7725,7 +7760,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2f32(const SDValue &N) {
// Emits: VR64:v2f32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7733,7 +7768,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2f32(const SDValue &N) {
// Emits: VR64:v2f32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7741,7 +7776,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2f32(const SDValue &N) {
// Emits: VR64:v2f32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7749,7 +7784,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2f32(const SDValue &N) {
// Emits: (MMX_MOVD64to64rr:v2f32 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_71(N, X86::MMX_MOVD64to64rr, MVT::v2f32);
+ SDNode *Result = Emit_72(N, X86::MMX_MOVD64to64rr, MVT::v2f32);
return Result;
}
@@ -7757,15 +7792,15 @@ SDNode *Select_ISD_BIT_CONVERT_v2f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v4f32(const SDValue &N) {
+SDNode *Select_ISD_BIT_CONVERT_v4f32(SDNode *N) {
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v4f32 VR128:v2i64:$src)
// Emits: VR128:v4f32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7773,7 +7808,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4f32(const SDValue &N) {
// Emits: VR128:v4f32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7781,7 +7816,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4f32(const SDValue &N) {
// Emits: VR128:v4f32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7789,7 +7824,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4f32(const SDValue &N) {
// Emits: VR128:v4f32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7797,7 +7832,7 @@ SDNode *Select_ISD_BIT_CONVERT_v4f32(const SDValue &N) {
// Emits: VR128:v4f32:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
}
@@ -7806,15 +7841,15 @@ SDNode *Select_ISD_BIT_CONVERT_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BIT_CONVERT_v2f64(const SDValue &N) {
+SDNode *Select_ISD_BIT_CONVERT_v2f64(SDNode *N) {
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (bitconvert:v2f64 VR128:v2i64:$src)
// Emits: VR128:v2f64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7822,7 +7857,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2f64(const SDValue &N) {
// Emits: VR128:v2f64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7830,7 +7865,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2f64(const SDValue &N) {
// Emits: VR128:v2f64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7838,7 +7873,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2f64(const SDValue &N) {
// Emits: VR128:v2f64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
@@ -7846,7 +7881,7 @@ SDNode *Select_ISD_BIT_CONVERT_v2f64(const SDValue &N) {
// Emits: VR128:v2f64:$src
// Pattern complexity = 3 cost = 0 size = 0
if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_79(N);
+ SDNode *Result = Emit_80(N);
return Result;
}
}
@@ -7855,16 +7890,16 @@ SDNode *Select_ISD_BIT_CONVERT_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_82(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, N1, Chain);
+DISABLE_INLINE SDNode *Emit_83(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, N1, Chain);
}
-SDNode *Select_ISD_BR(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BasicBlock) {
- SDNode *Result = Emit_82(N, X86::JMP);
+SDNode *Select_ISD_BR(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BasicBlock) {
+ SDNode *Result = Emit_83(N, X86::JMP);
return Result;
}
@@ -7872,26 +7907,26 @@ SDNode *Select_ISD_BR(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_83(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_84(SDNode *N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N1.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain1);
- Chain1 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain1 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 6);
Chain1 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
const SDValue Froms[] = {
SDValue(N1.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -7900,21 +7935,21 @@ DISABLE_INLINE SDNode *Emit_83(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_ISD_BRIND(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+SDNode *Select_ISD_BRIND(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N) &&
(Chain.getNode() == N1.getNode() || IsChainCompatible(Chain.getNode(), N1.getNode()))) {
- SDValue Chain1 = N1.getOperand(0);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode())) {
// Pattern: (brind:isVoid (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
// Emits: (JMP32m:isVoid addr:iPTR:$dst)
// Pattern complexity = 25 cost = 1 size = 3
if (Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -7922,7 +7957,7 @@ SDNode *Select_ISD_BRIND(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_83(N, X86::JMP32m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_84(N, X86::JMP32m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -7932,7 +7967,7 @@ SDNode *Select_ISD_BRIND(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 3
if (Predicate_load(N1.getNode()) &&
Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -7940,7 +7975,7 @@ SDNode *Select_ISD_BRIND(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_83(N, X86::JMP64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_84(N, X86::JMP64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -7951,7 +7986,7 @@ SDNode *Select_ISD_BRIND(const SDValue &N) {
// Emits: (JMP32r:isVoid GR32:i32:$dst)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_82(N, X86::JMP32r);
+ SDNode *Result = Emit_83(N, X86::JMP32r);
return Result;
}
@@ -7959,7 +7994,7 @@ SDNode *Select_ISD_BRIND(const SDValue &N) {
// Emits: (JMP64r:isVoid GR64:i64:$dst)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_82(N, X86::JMP64r);
+ SDNode *Result = Emit_83(N, X86::JMP64r);
return Result;
}
@@ -7967,23 +8002,23 @@ SDNode *Select_ISD_BRIND(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BSWAP_i32(const SDValue &N) {
- SDNode *Result = Emit_71(N, X86::BSWAP32r, MVT::i32);
+SDNode *Select_ISD_BSWAP_i32(SDNode *N) {
+ SDNode *Result = Emit_72(N, X86::BSWAP32r, MVT::i32);
return Result;
}
-SDNode *Select_ISD_BSWAP_i64(const SDValue &N) {
- SDNode *Result = Emit_71(N, X86::BSWAP64r, MVT::i64);
+SDNode *Select_ISD_BSWAP_i64(SDNode *N) {
+ SDNode *Result = Emit_72(N, X86::BSWAP64r, MVT::i64);
return Result;
}
-DISABLE_INLINE SDNode *Emit_84(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0);
+DISABLE_INLINE SDNode *Emit_85(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ return CurDAG->SelectNodeTo(N, Opc0, VT0);
}
-SDNode *Select_ISD_BUILD_VECTOR_v8i8(const SDValue &N) {
+SDNode *Select_ISD_BUILD_VECTOR_v8i8(SDNode *N) {
if ((Subtarget->hasMMX()) &&
- Predicate_immAllZerosV(N.getNode())) {
- SDNode *Result = Emit_84(N, X86::MMX_V_SET0, MVT::v8i8);
+ Predicate_immAllZerosV(N)) {
+ SDNode *Result = Emit_85(N, X86::MMX_V_SET0, MVT::v8i8);
return Result;
}
@@ -7991,10 +8026,10 @@ SDNode *Select_ISD_BUILD_VECTOR_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BUILD_VECTOR_v16i8(const SDValue &N) {
+SDNode *Select_ISD_BUILD_VECTOR_v16i8(SDNode *N) {
if ((Subtarget->hasSSE1()) &&
- Predicate_immAllZerosV(N.getNode())) {
- SDNode *Result = Emit_84(N, X86::V_SET0, MVT::v16i8);
+ Predicate_immAllZerosV(N)) {
+ SDNode *Result = Emit_85(N, X86::V_SET0, MVT::v16i8);
return Result;
}
@@ -8002,10 +8037,10 @@ SDNode *Select_ISD_BUILD_VECTOR_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BUILD_VECTOR_v4i16(const SDValue &N) {
+SDNode *Select_ISD_BUILD_VECTOR_v4i16(SDNode *N) {
if ((Subtarget->hasMMX()) &&
- Predicate_immAllZerosV(N.getNode())) {
- SDNode *Result = Emit_84(N, X86::MMX_V_SET0, MVT::v4i16);
+ Predicate_immAllZerosV(N)) {
+ SDNode *Result = Emit_85(N, X86::MMX_V_SET0, MVT::v4i16);
return Result;
}
@@ -8013,10 +8048,10 @@ SDNode *Select_ISD_BUILD_VECTOR_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BUILD_VECTOR_v8i16(const SDValue &N) {
+SDNode *Select_ISD_BUILD_VECTOR_v8i16(SDNode *N) {
if ((Subtarget->hasSSE1()) &&
- Predicate_immAllZerosV(N.getNode())) {
- SDNode *Result = Emit_84(N, X86::V_SET0, MVT::v8i16);
+ Predicate_immAllZerosV(N)) {
+ SDNode *Result = Emit_85(N, X86::V_SET0, MVT::v8i16);
return Result;
}
@@ -8024,22 +8059,22 @@ SDNode *Select_ISD_BUILD_VECTOR_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BUILD_VECTOR_v2i32(const SDValue &N) {
+SDNode *Select_ISD_BUILD_VECTOR_v2i32(SDNode *N) {
if ((Subtarget->hasMMX())) {
// Pattern: (build_vector:v2i32)<<P:Predicate_immAllZerosV>>
// Emits: (MMX_V_SET0:v2i32)
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_immAllZerosV(N.getNode())) {
- SDNode *Result = Emit_84(N, X86::MMX_V_SET0, MVT::v2i32);
+ if (Predicate_immAllZerosV(N)) {
+ SDNode *Result = Emit_85(N, X86::MMX_V_SET0, MVT::v2i32);
return Result;
}
// Pattern: (build_vector:v2i32)<<P:Predicate_immAllOnesV>>
// Emits: (MMX_V_SETALLONES:v2i32)
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_immAllOnesV(N.getNode())) {
- SDNode *Result = Emit_84(N, X86::MMX_V_SETALLONES, MVT::v2i32);
+ if (Predicate_immAllOnesV(N)) {
+ SDNode *Result = Emit_85(N, X86::MMX_V_SETALLONES, MVT::v2i32);
return Result;
}
}
@@ -8048,14 +8083,14 @@ SDNode *Select_ISD_BUILD_VECTOR_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BUILD_VECTOR_v4i32(const SDValue &N) {
+SDNode *Select_ISD_BUILD_VECTOR_v4i32(SDNode *N) {
// Pattern: (build_vector:v4i32)<<P:Predicate_immAllZerosV>>
// Emits: (V_SET0:v4i32)
// Pattern complexity = 4 cost = 1 size = 3
if ((Subtarget->hasSSE1()) &&
- Predicate_immAllZerosV(N.getNode())) {
- SDNode *Result = Emit_84(N, X86::V_SET0, MVT::v4i32);
+ Predicate_immAllZerosV(N)) {
+ SDNode *Result = Emit_85(N, X86::V_SET0, MVT::v4i32);
return Result;
}
@@ -8063,8 +8098,8 @@ SDNode *Select_ISD_BUILD_VECTOR_v4i32(const SDValue &N) {
// Emits: (V_SETALLONES:v4i32)
// Pattern complexity = 4 cost = 1 size = 3
if ((Subtarget->hasSSE2()) &&
- Predicate_immAllOnesV(N.getNode())) {
- SDNode *Result = Emit_84(N, X86::V_SETALLONES, MVT::v4i32);
+ Predicate_immAllOnesV(N)) {
+ SDNode *Result = Emit_85(N, X86::V_SETALLONES, MVT::v4i32);
return Result;
}
@@ -8072,10 +8107,10 @@ SDNode *Select_ISD_BUILD_VECTOR_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BUILD_VECTOR_v1i64(const SDValue &N) {
+SDNode *Select_ISD_BUILD_VECTOR_v1i64(SDNode *N) {
if ((Subtarget->hasMMX()) &&
- Predicate_immAllZerosV(N.getNode())) {
- SDNode *Result = Emit_84(N, X86::MMX_V_SET0, MVT::v1i64);
+ Predicate_immAllZerosV(N)) {
+ SDNode *Result = Emit_85(N, X86::MMX_V_SET0, MVT::v1i64);
return Result;
}
@@ -8083,10 +8118,10 @@ SDNode *Select_ISD_BUILD_VECTOR_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BUILD_VECTOR_v2i64(const SDValue &N) {
+SDNode *Select_ISD_BUILD_VECTOR_v2i64(SDNode *N) {
if ((Subtarget->hasSSE1()) &&
- Predicate_immAllZerosV(N.getNode())) {
- SDNode *Result = Emit_84(N, X86::V_SET0, MVT::v2i64);
+ Predicate_immAllZerosV(N)) {
+ SDNode *Result = Emit_85(N, X86::V_SET0, MVT::v2i64);
return Result;
}
@@ -8094,10 +8129,10 @@ SDNode *Select_ISD_BUILD_VECTOR_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BUILD_VECTOR_v4f32(const SDValue &N) {
+SDNode *Select_ISD_BUILD_VECTOR_v4f32(SDNode *N) {
if ((Subtarget->hasSSE1()) &&
- Predicate_immAllZerosV(N.getNode())) {
- SDNode *Result = Emit_84(N, X86::V_SET0, MVT::v4f32);
+ Predicate_immAllZerosV(N)) {
+ SDNode *Result = Emit_85(N, X86::V_SET0, MVT::v4f32);
return Result;
}
@@ -8105,10 +8140,10 @@ SDNode *Select_ISD_BUILD_VECTOR_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_BUILD_VECTOR_v2f64(const SDValue &N) {
+SDNode *Select_ISD_BUILD_VECTOR_v2f64(SDNode *N) {
if ((Subtarget->hasSSE1()) &&
- Predicate_immAllZerosV(N.getNode())) {
- SDNode *Result = Emit_84(N, X86::V_SET0, MVT::v2f64);
+ Predicate_immAllZerosV(N)) {
+ SDNode *Result = Emit_85(N, X86::V_SET0, MVT::v2f64);
return Result;
}
@@ -8116,22 +8151,22 @@ SDNode *Select_ISD_BUILD_VECTOR_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_85(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_86(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
SDValue Ops0[] = { N1, N2, Chain, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 4 : 3);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 4 : 3);
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -8140,18 +8175,18 @@ DISABLE_INLINE SDNode *Emit_85(const SDValue &N, unsigned Opc0) {
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_ISD_CALLSEQ_END(const SDValue &N) {
+SDNode *Select_ISD_CALLSEQ_END(SDNode *N) {
// Pattern: (X86callseq_end:isVoid (timm:i32):$amt1, (timm:i32):$amt2)
// Emits: (ADJCALLSTACKUP32:isVoid (timm:i32):$amt1, (timm:i32):$amt2)
// Pattern complexity = 9 cost = 1 size = 3
if ((!Subtarget->is64Bit())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetConstant) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::TargetConstant) {
- SDNode *Result = Emit_85(N, X86::ADJCALLSTACKUP32);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TargetConstant) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::TargetConstant) {
+ SDNode *Result = Emit_86(N, X86::ADJCALLSTACKUP32);
return Result;
}
}
@@ -8161,12 +8196,12 @@ SDNode *Select_ISD_CALLSEQ_END(const SDValue &N) {
// Emits: (ADJCALLSTACKUP64:isVoid (timm:i32):$amt1, (timm:i32):$amt2)
// Pattern complexity = 9 cost = 1 size = 3
if ((Subtarget->is64Bit())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetConstant) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::TargetConstant) {
- SDNode *Result = Emit_85(N, X86::ADJCALLSTACKUP64);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TargetConstant) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::TargetConstant) {
+ SDNode *Result = Emit_86(N, X86::ADJCALLSTACKUP64);
return Result;
}
}
@@ -8176,15 +8211,15 @@ SDNode *Select_ISD_CALLSEQ_END(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_86(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, N1, Chain);
+DISABLE_INLINE SDNode *Emit_87(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, N1, Chain);
Chain = SDValue(ResNode, 0);
SDValue InFlag(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -8193,16 +8228,16 @@ DISABLE_INLINE SDNode *Emit_86(const SDValue &N, unsigned Opc0) {
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_ISD_CALLSEQ_START(const SDValue &N) {
+SDNode *Select_ISD_CALLSEQ_START(SDNode *N) {
// Pattern: (X86callseq_start:isVoid (timm:i32):$amt)
// Emits: (ADJCALLSTACKDOWN32:isVoid (timm:i32):$amt)
// Pattern complexity = 6 cost = 1 size = 3
if ((!Subtarget->is64Bit())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetConstant) {
- SDNode *Result = Emit_86(N, X86::ADJCALLSTACKDOWN32);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TargetConstant) {
+ SDNode *Result = Emit_87(N, X86::ADJCALLSTACKDOWN32);
return Result;
}
}
@@ -8211,10 +8246,10 @@ SDNode *Select_ISD_CALLSEQ_START(const SDValue &N) {
// Emits: (ADJCALLSTACKDOWN64:isVoid (timm:i32):$amt)
// Pattern complexity = 6 cost = 1 size = 3
if ((Subtarget->is64Bit())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TargetConstant) {
- SDNode *Result = Emit_86(N, X86::ADJCALLSTACKDOWN64);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TargetConstant) {
+ SDNode *Result = Emit_87(N, X86::ADJCALLSTACKDOWN64);
return Result;
}
}
@@ -8223,64 +8258,59 @@ SDNode *Select_ISD_CALLSEQ_START(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_87(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_88(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i8);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp0);
}
-SDNode *Select_ISD_Constant_i8(const SDValue &N) {
+SDNode *Select_ISD_Constant_i8(SDNode *N) {
// Pattern: 0:i8
// Emits: (MOV8r0:i8)
// Pattern complexity = 5 cost = 1 size = 3
if (cast<ConstantSDNode>(N)->getSExtValue() == INT64_C(0)) {
- SDNode *Result = Emit_84(N, X86::MOV8r0, MVT::i8);
+ SDNode *Result = Emit_85(N, X86::MOV8r0, MVT::i8);
return Result;
}
// Pattern: (imm:i8):$src
// Emits: (MOV8ri:i8 (imm:i8):$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_87(N, X86::MOV8ri, MVT::i8);
+ SDNode *Result = Emit_88(N, X86::MOV8ri, MVT::i8);
return Result;
}
-DISABLE_INLINE SDNode *Emit_88(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_89(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i16);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0);
-}
-DISABLE_INLINE SDNode *Emit_89(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
- SDValue Tmp1 = CurDAG->getTargetConstant(0x3ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp0, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp0);
}
-SDNode *Select_ISD_Constant_i16(const SDValue &N) {
+SDNode *Select_ISD_Constant_i16(SDNode *N) {
// Pattern: 0:i16
- // Emits: (EXTRACT_SUBREG:i16 (MOV32r0:i32), 3:i32)
- // Pattern complexity = 6 cost = 2 size = 3
+ // Emits: (MOV16r0:i16)
+ // Pattern complexity = 5 cost = 1 size = 3
if (cast<ConstantSDNode>(N)->getSExtValue() == INT64_C(0)) {
- SDNode *Result = Emit_89(N, X86::MOV32r0, TargetInstrInfo::EXTRACT_SUBREG, MVT::i32, MVT::i16);
+ SDNode *Result = Emit_85(N, X86::MOV16r0, MVT::i16);
return Result;
}
// Pattern: (imm:i16):$src
// Emits: (MOV16ri:i16 (imm:i16):$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_88(N, X86::MOV16ri, MVT::i16);
+ SDNode *Result = Emit_89(N, X86::MOV16ri, MVT::i16);
return Result;
}
-DISABLE_INLINE SDNode *Emit_90(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_90(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp0);
}
-SDNode *Select_ISD_Constant_i32(const SDValue &N) {
+SDNode *Select_ISD_Constant_i32(SDNode *N) {
// Pattern: 0:i32
// Emits: (MOV32r0:i32)
// Pattern complexity = 5 cost = 1 size = 3
if (cast<ConstantSDNode>(N)->getSExtValue() == INT64_C(0)) {
- SDNode *Result = Emit_84(N, X86::MOV32r0, MVT::i32);
+ SDNode *Result = Emit_85(N, X86::MOV32r0, MVT::i32);
return Result;
}
@@ -8291,30 +8321,24 @@ SDNode *Select_ISD_Constant_i32(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_91(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
+DISABLE_INLINE SDNode *Emit_91(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
SDValue Tmp0 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N)->getZExtValue()), MVT::i64);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Tmp0);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Tmp0);
}
-DISABLE_INLINE SDNode *Emit_92(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue Tmp0 = CurDAG->getTargetConstant(0x0ULL, MVT::i64);
- SDValue Tmp1(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
- SDValue Tmp2 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp0, Tmp1, Tmp2);
-}
-SDNode *Select_ISD_Constant_i64(const SDValue &N) {
+SDNode *Select_ISD_Constant_i64(SDNode *N) {
// Pattern: 0:i64
- // Emits: (SUBREG_TO_REG:i64 0:i64, (MOV32r0:i32), 4:i32)
- // Pattern complexity = 6 cost = 2 size = 3
+ // Emits: (MOV64r0:i64)
+ // Pattern complexity = 6 cost = 1 size = 3
if (cast<ConstantSDNode>(N)->getSExtValue() == INT64_C(0)) {
- SDNode *Result = Emit_92(N, X86::MOV32r0, TargetInstrInfo::SUBREG_TO_REG, MVT::i32, MVT::i64);
+ SDNode *Result = Emit_85(N, X86::MOV64r0, MVT::i64);
return Result;
}
// Pattern: (imm:i64)<<P:Predicate_i64immZExt32>>:$src
// Emits: (MOV64ri64i32:i64 (imm:i64):$src)
// Pattern complexity = 5 cost = 1 size = 3
- if (Predicate_i64immZExt32(N.getNode())) {
+ if (Predicate_i64immZExt32(N)) {
SDNode *Result = Emit_91(N, X86::MOV64ri64i32, MVT::i64);
return Result;
}
@@ -8322,7 +8346,7 @@ SDNode *Select_ISD_Constant_i64(const SDValue &N) {
// Pattern: (imm:i64)<<P:Predicate_i64immSExt32>>:$src
// Emits: (MOV64ri32:i64 (imm:i64):$src)
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_i64immSExt32(N.getNode())) {
+ if (Predicate_i64immSExt32(N)) {
SDNode *Result = Emit_91(N, X86::MOV64ri32, MVT::i64);
return Result;
}
@@ -8334,26 +8358,26 @@ SDNode *Select_ISD_Constant_i64(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_93(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp0);
+DISABLE_INLINE SDNode *Emit_92(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue Tmp0(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp0);
}
-SDNode *Select_ISD_ConstantFP_f32(const SDValue &N) {
+SDNode *Select_ISD_ConstantFP_f32(SDNode *N) {
if ((!Subtarget->hasSSE1())) {
// Pattern: (fpimm:f32)<<P:Predicate_fpimm0>>
// Emits: (LD_Fp032:f32)
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_fpimm0(N.getNode())) {
- SDNode *Result = Emit_84(N, X86::LD_Fp032, MVT::f32);
+ if (Predicate_fpimm0(N)) {
+ SDNode *Result = Emit_85(N, X86::LD_Fp032, MVT::f32);
return Result;
}
// Pattern: (fpimm:f32)<<P:Predicate_fpimm1>>
// Emits: (LD_Fp132:f32)
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_fpimm1(N.getNode())) {
- SDNode *Result = Emit_84(N, X86::LD_Fp132, MVT::f32);
+ if (Predicate_fpimm1(N)) {
+ SDNode *Result = Emit_85(N, X86::LD_Fp132, MVT::f32);
return Result;
}
}
@@ -8362,8 +8386,8 @@ SDNode *Select_ISD_ConstantFP_f32(const SDValue &N) {
// Emits: (FsFLD0SS:f32)
// Pattern complexity = 4 cost = 1 size = 3
if ((Subtarget->hasSSE1()) &&
- Predicate_fp32imm0(N.getNode())) {
- SDNode *Result = Emit_84(N, X86::FsFLD0SS, MVT::f32);
+ Predicate_fp32imm0(N)) {
+ SDNode *Result = Emit_85(N, X86::FsFLD0SS, MVT::f32);
return Result;
}
if ((!Subtarget->hasSSE1())) {
@@ -8371,16 +8395,16 @@ SDNode *Select_ISD_ConstantFP_f32(const SDValue &N) {
// Pattern: (fpimm:f32)<<P:Predicate_fpimmneg0>>
// Emits: (CHS_Fp32:f32 (LD_Fp032:f32))
// Pattern complexity = 4 cost = 2 size = 0
- if (Predicate_fpimmneg0(N.getNode())) {
- SDNode *Result = Emit_93(N, X86::LD_Fp032, X86::CHS_Fp32, MVT::f32, MVT::f32);
+ if (Predicate_fpimmneg0(N)) {
+ SDNode *Result = Emit_92(N, X86::LD_Fp032, X86::CHS_Fp32, MVT::f32, MVT::f32);
return Result;
}
// Pattern: (fpimm:f32)<<P:Predicate_fpimmneg1>>
// Emits: (CHS_Fp32:f32 (LD_Fp132:f32))
// Pattern complexity = 4 cost = 2 size = 0
- if (Predicate_fpimmneg1(N.getNode())) {
- SDNode *Result = Emit_93(N, X86::LD_Fp132, X86::CHS_Fp32, MVT::f32, MVT::f32);
+ if (Predicate_fpimmneg1(N)) {
+ SDNode *Result = Emit_92(N, X86::LD_Fp132, X86::CHS_Fp32, MVT::f32, MVT::f32);
return Result;
}
}
@@ -8389,22 +8413,22 @@ SDNode *Select_ISD_ConstantFP_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ConstantFP_f64(const SDValue &N) {
+SDNode *Select_ISD_ConstantFP_f64(SDNode *N) {
if ((!Subtarget->hasSSE2())) {
// Pattern: (fpimm:f64)<<P:Predicate_fpimm0>>
// Emits: (LD_Fp064:f64)
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_fpimm0(N.getNode())) {
- SDNode *Result = Emit_84(N, X86::LD_Fp064, MVT::f64);
+ if (Predicate_fpimm0(N)) {
+ SDNode *Result = Emit_85(N, X86::LD_Fp064, MVT::f64);
return Result;
}
// Pattern: (fpimm:f64)<<P:Predicate_fpimm1>>
// Emits: (LD_Fp164:f64)
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_fpimm1(N.getNode())) {
- SDNode *Result = Emit_84(N, X86::LD_Fp164, MVT::f64);
+ if (Predicate_fpimm1(N)) {
+ SDNode *Result = Emit_85(N, X86::LD_Fp164, MVT::f64);
return Result;
}
}
@@ -8413,8 +8437,8 @@ SDNode *Select_ISD_ConstantFP_f64(const SDValue &N) {
// Emits: (FsFLD0SD:f64)
// Pattern complexity = 4 cost = 1 size = 3
if ((Subtarget->hasSSE2()) &&
- Predicate_fpimm0(N.getNode())) {
- SDNode *Result = Emit_84(N, X86::FsFLD0SD, MVT::f64);
+ Predicate_fpimm0(N)) {
+ SDNode *Result = Emit_85(N, X86::FsFLD0SD, MVT::f64);
return Result;
}
if ((!Subtarget->hasSSE2())) {
@@ -8422,16 +8446,16 @@ SDNode *Select_ISD_ConstantFP_f64(const SDValue &N) {
// Pattern: (fpimm:f64)<<P:Predicate_fpimmneg0>>
// Emits: (CHS_Fp64:f64 (LD_Fp064:f64))
// Pattern complexity = 4 cost = 2 size = 0
- if (Predicate_fpimmneg0(N.getNode())) {
- SDNode *Result = Emit_93(N, X86::LD_Fp064, X86::CHS_Fp64, MVT::f64, MVT::f64);
+ if (Predicate_fpimmneg0(N)) {
+ SDNode *Result = Emit_92(N, X86::LD_Fp064, X86::CHS_Fp64, MVT::f64, MVT::f64);
return Result;
}
// Pattern: (fpimm:f64)<<P:Predicate_fpimmneg1>>
// Emits: (CHS_Fp64:f64 (LD_Fp164:f64))
// Pattern complexity = 4 cost = 2 size = 0
- if (Predicate_fpimmneg1(N.getNode())) {
- SDNode *Result = Emit_93(N, X86::LD_Fp164, X86::CHS_Fp64, MVT::f64, MVT::f64);
+ if (Predicate_fpimmneg1(N)) {
+ SDNode *Result = Emit_92(N, X86::LD_Fp164, X86::CHS_Fp64, MVT::f64, MVT::f64);
return Result;
}
}
@@ -8440,37 +8464,37 @@ SDNode *Select_ISD_ConstantFP_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ConstantFP_f80(const SDValue &N) {
+SDNode *Select_ISD_ConstantFP_f80(SDNode *N) {
// Pattern: (fpimm:f80)<<P:Predicate_fpimm0>>
// Emits: (LD_Fp080:f80)
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_fpimm0(N.getNode())) {
- SDNode *Result = Emit_84(N, X86::LD_Fp080, MVT::f80);
+ if (Predicate_fpimm0(N)) {
+ SDNode *Result = Emit_85(N, X86::LD_Fp080, MVT::f80);
return Result;
}
// Pattern: (fpimm:f80)<<P:Predicate_fpimm1>>
// Emits: (LD_Fp180:f80)
// Pattern complexity = 4 cost = 1 size = 0
- if (Predicate_fpimm1(N.getNode())) {
- SDNode *Result = Emit_84(N, X86::LD_Fp180, MVT::f80);
+ if (Predicate_fpimm1(N)) {
+ SDNode *Result = Emit_85(N, X86::LD_Fp180, MVT::f80);
return Result;
}
// Pattern: (fpimm:f80)<<P:Predicate_fpimmneg0>>
// Emits: (CHS_Fp80:f80 (LD_Fp080:f80))
// Pattern complexity = 4 cost = 2 size = 0
- if (Predicate_fpimmneg0(N.getNode())) {
- SDNode *Result = Emit_93(N, X86::LD_Fp080, X86::CHS_Fp80, MVT::f80, MVT::f80);
+ if (Predicate_fpimmneg0(N)) {
+ SDNode *Result = Emit_92(N, X86::LD_Fp080, X86::CHS_Fp80, MVT::f80, MVT::f80);
return Result;
}
// Pattern: (fpimm:f80)<<P:Predicate_fpimmneg1>>
// Emits: (CHS_Fp80:f80 (LD_Fp180:f80))
// Pattern complexity = 4 cost = 2 size = 0
- if (Predicate_fpimmneg1(N.getNode())) {
- SDNode *Result = Emit_93(N, X86::LD_Fp180, X86::CHS_Fp80, MVT::f80, MVT::f80);
+ if (Predicate_fpimmneg1(N)) {
+ SDNode *Result = Emit_92(N, X86::LD_Fp180, X86::CHS_Fp80, MVT::f80, MVT::f80);
return Result;
}
@@ -8478,38 +8502,38 @@ SDNode *Select_ISD_ConstantFP_f80(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_94(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0);
+DISABLE_INLINE SDNode *Emit_93(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0);
}
-DISABLE_INLINE SDNode *Emit_95(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_94(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_96(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_95(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, Tmp1);
}
-SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i32(const SDValue &N) {
+SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i32(SDNode *N) {
// Pattern: (extractelt:i32 (bitconvert:v4i32 VR128:v4f32:$src1), (imm:iPTR):$src2)
// Emits: (EXTRACTPSrr:i32 VR128:v4f32:$src1, (imm:i32):$src2)
// Pattern complexity = 9 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i32 &&
N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_96(N, X86::EXTRACTPSrr, MVT::i32);
+ SDNode *Result = Emit_95(N, X86::EXTRACTPSrr, MVT::i32);
return Result;
}
}
@@ -8519,14 +8543,14 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i32(const SDValue &N) {
// Emits: (MOVPDI2DIrr:i32 VR128:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_94(N, X86::MOVPDI2DIrr, MVT::i32);
+ SDNode *Result = Emit_93(N, X86::MOVPDI2DIrr, MVT::i32);
return Result;
}
}
@@ -8536,11 +8560,11 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i32(const SDValue &N) {
// Emits: (PEXTRDrr:i32 VR128:v4i32:$src1, (imm:i32):$src2)
// Pattern complexity = 6 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_95(N, X86::PEXTRDrr, MVT::i32);
+ SDNode *Result = Emit_94(N, X86::PEXTRDrr, MVT::i32);
return Result;
}
}
@@ -8549,20 +8573,20 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i64(const SDValue &N) {
+SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i64(SDNode *N) {
// Pattern: (vector_extract:i64 VR128:v2i64:$src, 0:iPTR)
// Emits: (MOVPQIto64rr:i64 VR128:v2i64:$src)
// Pattern complexity = 8 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_94(N, X86::MOVPQIto64rr, MVT::i64);
+ SDNode *Result = Emit_93(N, X86::MOVPQIto64rr, MVT::i64);
return Result;
}
}
@@ -8572,11 +8596,11 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i64(const SDValue &N) {
// Emits: (PEXTRQrr:i64 VR128:v2i64:$src1, (imm:i32):$src2)
// Pattern complexity = 6 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_95(N, X86::PEXTRQrr, MVT::i64);
+ SDNode *Result = Emit_94(N, X86::PEXTRQrr, MVT::i64);
return Result;
}
}
@@ -8585,16 +8609,16 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f32(const SDValue &N) {
+SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f32(SDNode *N) {
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_94(N, X86::MOVPS2SSrr, MVT::f32);
+ SDNode *Result = Emit_93(N, X86::MOVPS2SSrr, MVT::f32);
return Result;
}
}
@@ -8604,16 +8628,16 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f64(const SDValue &N) {
+SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f64(SDNode *N) {
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_94(N, X86::MOVPD2SDrr, MVT::f64);
+ SDNode *Result = Emit_93(N, X86::MOVPD2SDrr, MVT::f64);
return Result;
}
}
@@ -8623,9 +8647,9 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FABS_f32(const SDValue &N) {
+SDNode *Select_ISD_FABS_f32(SDNode *N) {
if ((!Subtarget->hasSSE1())) {
- SDNode *Result = Emit_71(N, X86::ABS_Fp32, MVT::f32);
+ SDNode *Result = Emit_72(N, X86::ABS_Fp32, MVT::f32);
return Result;
}
@@ -8633,9 +8657,9 @@ SDNode *Select_ISD_FABS_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FABS_f64(const SDValue &N) {
+SDNode *Select_ISD_FABS_f64(SDNode *N) {
if ((!Subtarget->hasSSE2())) {
- SDNode *Result = Emit_71(N, X86::ABS_Fp64, MVT::f64);
+ SDNode *Result = Emit_72(N, X86::ABS_Fp64, MVT::f64);
return Result;
}
@@ -8643,51 +8667,51 @@ SDNode *Select_ISD_FABS_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FABS_f80(const SDValue &N) {
- SDNode *Result = Emit_71(N, X86::ABS_Fp80, MVT::f80);
+SDNode *Select_ISD_FABS_f80(SDNode *N) {
+ SDNode *Result = Emit_72(N, X86::ABS_Fp80, MVT::f80);
return Result;
}
-DISABLE_INLINE SDNode *Emit_97(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N12 = N1.getOperand(2);
+DISABLE_INLINE SDNode *Emit_96(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_98(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N02 = N0.getOperand(2);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_97(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N02 = N0.getNode()->getOperand(2);
+ SDValue N1 = N->getOperand(1);
SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_ISD_FADD_f32(const SDValue &N) {
+SDNode *Select_ISD_FADD_f32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fadd:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
// Emits: (ADD_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_loadf32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -8704,14 +8728,14 @@ SDNode *Select_ISD_FADD_f32(const SDValue &N) {
// Pattern: (fadd:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>, RFP32:f32:$src1)
// Emits: (ADD_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_loadf32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -8725,20 +8749,20 @@ SDNode *Select_ISD_FADD_f32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fadd:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (ADDSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -8755,13 +8779,13 @@ SDNode *Select_ISD_FADD_f32(const SDValue &N) {
// Pattern: (fadd:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, FR32:f32:$src1)
// Emits: (ADDSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -8775,66 +8799,66 @@ SDNode *Select_ISD_FADD_f32(const SDValue &N) {
}
}
if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == X86ISD::FILD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == X86ISD::FILD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getOperand(2);
+ SDValue N12 = N1.getNode()->getOperand(2);
// Pattern: (fadd:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i16:Other))
// Emits: (ADD_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::ADD_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::ADD_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fadd:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i32:Other))
// Emits: (ADD_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::ADD_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::ADD_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- if (N0.getOpcode() == X86ISD::FILD &&
+ if (N0.getNode()->getOpcode() == X86ISD::FILD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N02 = N0.getOperand(2);
+ SDValue N02 = N0.getNode()->getOperand(2);
// Pattern: (fadd:f32 (X86fild:f32 addr:iPTR:$src2, i16:Other), RFP32:f32:$src1)
// Emits: (ADD_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02)->getVT() == MVT::i16) {
- SDNode *Result = Emit_98(N, X86::ADD_FpI16m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_97(N, X86::ADD_FpI16m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
// Pattern: (fadd:f32 (X86fild:f32 addr:iPTR:$src2, i32:Other), RFP32:f32:$src1)
// Emits: (ADD_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02)->getVT() == MVT::i32) {
- SDNode *Result = Emit_98(N, X86::ADD_FpI32m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_97(N, X86::ADD_FpI32m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -8862,16 +8886,16 @@ SDNode *Select_ISD_FADD_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FADD_f64(const SDValue &N) {
+SDNode *Select_ISD_FADD_f64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode())) {
// Pattern: (fadd:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
@@ -8879,7 +8903,7 @@ SDNode *Select_ISD_FADD_f64(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_load(N1.getNode()) &&
Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -8896,7 +8920,7 @@ SDNode *Select_ISD_FADD_f64(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extload(N1.getNode()) &&
Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -8910,10 +8934,10 @@ SDNode *Select_ISD_FADD_f64(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode())) {
// Pattern: (fadd:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>, RFP64:f64:$src1)
@@ -8921,7 +8945,7 @@ SDNode *Select_ISD_FADD_f64(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_load(N0.getNode()) &&
Predicate_loadf64(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -8938,7 +8962,7 @@ SDNode *Select_ISD_FADD_f64(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extload(N0.getNode()) &&
Predicate_extloadf32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -8953,20 +8977,20 @@ SDNode *Select_ISD_FADD_f64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fadd:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (ADDSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -8983,13 +9007,13 @@ SDNode *Select_ISD_FADD_f64(const SDValue &N) {
// Pattern: (fadd:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, FR64:f64:$src1)
// Emits: (ADDSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -9003,66 +9027,66 @@ SDNode *Select_ISD_FADD_f64(const SDValue &N) {
}
}
if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == X86ISD::FILD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == X86ISD::FILD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getOperand(2);
+ SDValue N12 = N1.getNode()->getOperand(2);
// Pattern: (fadd:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i16:Other))
// Emits: (ADD_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::ADD_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::ADD_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fadd:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i32:Other))
// Emits: (ADD_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::ADD_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::ADD_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- if (N0.getOpcode() == X86ISD::FILD &&
+ if (N0.getNode()->getOpcode() == X86ISD::FILD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N02 = N0.getOperand(2);
+ SDValue N02 = N0.getNode()->getOperand(2);
// Pattern: (fadd:f64 (X86fild:f64 addr:iPTR:$src2, i16:Other), RFP64:f64:$src1)
// Emits: (ADD_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02)->getVT() == MVT::i16) {
- SDNode *Result = Emit_98(N, X86::ADD_FpI16m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_97(N, X86::ADD_FpI16m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
// Pattern: (fadd:f64 (X86fild:f64 addr:iPTR:$src2, i32:Other), RFP64:f64:$src1)
// Emits: (ADD_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02)->getVT() == MVT::i32) {
- SDNode *Result = Emit_98(N, X86::ADD_FpI32m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_97(N, X86::ADD_FpI32m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -9090,15 +9114,15 @@ SDNode *Select_ISD_FADD_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FADD_f80(const SDValue &N) {
+SDNode *Select_ISD_FADD_f80(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_extload(N1.getNode())) {
@@ -9106,7 +9130,7 @@ SDNode *Select_ISD_FADD_f80(const SDValue &N) {
// Emits: (ADD_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -9122,7 +9146,7 @@ SDNode *Select_ISD_FADD_f80(const SDValue &N) {
// Emits: (ADD_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extloadf64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -9136,10 +9160,10 @@ SDNode *Select_ISD_FADD_f80(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_extload(N0.getNode())) {
@@ -9147,7 +9171,7 @@ SDNode *Select_ISD_FADD_f80(const SDValue &N) {
// Emits: (ADD_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extloadf32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -9163,7 +9187,7 @@ SDNode *Select_ISD_FADD_f80(const SDValue &N) {
// Emits: (ADD_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extloadf64(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -9177,64 +9201,64 @@ SDNode *Select_ISD_FADD_f80(const SDValue &N) {
}
}
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == X86ISD::FILD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == X86ISD::FILD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getOperand(2);
+ SDValue N12 = N1.getNode()->getOperand(2);
// Pattern: (fadd:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i16:Other))
// Emits: (ADD_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::ADD_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::ADD_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fadd:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i32:Other))
// Emits: (ADD_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::ADD_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::ADD_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- if (N0.getOpcode() == X86ISD::FILD &&
+ if (N0.getNode()->getOpcode() == X86ISD::FILD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N02 = N0.getOperand(2);
+ SDValue N02 = N0.getNode()->getOperand(2);
// Pattern: (fadd:f80 (X86fild:f80 addr:iPTR:$src2, i16:Other), RFP80:f80:$src1)
// Emits: (ADD_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02)->getVT() == MVT::i16) {
- SDNode *Result = Emit_98(N, X86::ADD_FpI16m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_97(N, X86::ADD_FpI16m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
// Pattern: (fadd:f80 (X86fild:f80 addr:iPTR:$src2, i32:Other), RFP80:f80:$src1)
// Emits: (ADD_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02)->getVT() == MVT::i32) {
- SDNode *Result = Emit_98(N, X86::ADD_FpI32m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_97(N, X86::ADD_FpI32m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -9248,24 +9272,24 @@ SDNode *Select_ISD_FADD_f80(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_FADD_v4f32(const SDValue &N) {
+SDNode *Select_ISD_FADD_v4f32(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fadd:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (ADDPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -9282,14 +9306,14 @@ SDNode *Select_ISD_FADD_v4f32(const SDValue &N) {
// Pattern: (fadd:v4f32 (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v4f32:$src1)
// Emits: (ADDPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -9315,24 +9339,24 @@ SDNode *Select_ISD_FADD_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FADD_v2f64(const SDValue &N) {
+SDNode *Select_ISD_FADD_v2f64(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fadd:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (ADDPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -9349,14 +9373,14 @@ SDNode *Select_ISD_FADD_v2f64(const SDValue &N) {
// Pattern: (fadd:v2f64 (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2f64:$src1)
// Emits: (ADDPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -9382,9 +9406,9 @@ SDNode *Select_ISD_FADD_v2f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FCOS_f32(const SDValue &N) {
+SDNode *Select_ISD_FCOS_f32(SDNode *N) {
if ((!Subtarget->hasSSE1())) {
- SDNode *Result = Emit_71(N, X86::COS_Fp32, MVT::f32);
+ SDNode *Result = Emit_72(N, X86::COS_Fp32, MVT::f32);
return Result;
}
@@ -9392,9 +9416,9 @@ SDNode *Select_ISD_FCOS_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FCOS_f64(const SDValue &N) {
+SDNode *Select_ISD_FCOS_f64(SDNode *N) {
if ((!Subtarget->hasSSE2())) {
- SDNode *Result = Emit_71(N, X86::COS_Fp64, MVT::f64);
+ SDNode *Result = Emit_72(N, X86::COS_Fp64, MVT::f64);
return Result;
}
@@ -9402,24 +9426,24 @@ SDNode *Select_ISD_FCOS_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FCOS_f80(const SDValue &N) {
- SDNode *Result = Emit_71(N, X86::COS_Fp80, MVT::f80);
+SDNode *Select_ISD_FCOS_f80(SDNode *N) {
+ SDNode *Result = Emit_72(N, X86::COS_Fp80, MVT::f80);
return Result;
}
-SDNode *Select_ISD_FDIV_f32(const SDValue &N) {
+SDNode *Select_ISD_FDIV_f32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_loadf32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -9449,15 +9473,15 @@ SDNode *Select_ISD_FDIV_f32(const SDValue &N) {
// Emits: (DIVSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -9471,50 +9495,50 @@ SDNode *Select_ISD_FDIV_f32(const SDValue &N) {
}
}
if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == X86ISD::FILD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == X86ISD::FILD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getOperand(2);
+ SDValue N12 = N1.getNode()->getOperand(2);
// Pattern: (fdiv:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i16:Other))
// Emits: (DIV_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::DIV_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::DIV_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fdiv:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i32:Other))
// Emits: (DIV_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::DIV_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::DIV_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fdiv:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i16:Other))
// Emits: (DIVR_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::DIVR_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::DIVR_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fdiv:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i32:Other))
// Emits: (DIVR_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::DIVR_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::DIVR_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -9542,15 +9566,15 @@ SDNode *Select_ISD_FDIV_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FDIV_f64(const SDValue &N) {
+SDNode *Select_ISD_FDIV_f64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode())) {
// Pattern: (fdiv:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
@@ -9558,7 +9582,7 @@ SDNode *Select_ISD_FDIV_f64(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_load(N1.getNode()) &&
Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -9575,7 +9599,7 @@ SDNode *Select_ISD_FDIV_f64(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extload(N1.getNode()) &&
Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -9592,7 +9616,7 @@ SDNode *Select_ISD_FDIV_f64(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_load(N1.getNode()) &&
Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -9609,7 +9633,7 @@ SDNode *Select_ISD_FDIV_f64(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extload(N1.getNode()) &&
Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -9628,15 +9652,15 @@ SDNode *Select_ISD_FDIV_f64(const SDValue &N) {
// Emits: (DIVSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -9650,50 +9674,50 @@ SDNode *Select_ISD_FDIV_f64(const SDValue &N) {
}
}
if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == X86ISD::FILD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == X86ISD::FILD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getOperand(2);
+ SDValue N12 = N1.getNode()->getOperand(2);
// Pattern: (fdiv:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i16:Other))
// Emits: (DIV_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::DIV_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::DIV_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fdiv:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i32:Other))
// Emits: (DIV_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::DIV_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::DIV_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fdiv:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i16:Other))
// Emits: (DIVR_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::DIVR_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::DIVR_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fdiv:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i32:Other))
// Emits: (DIVR_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::DIVR_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::DIVR_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -9721,14 +9745,14 @@ SDNode *Select_ISD_FDIV_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FDIV_f80(const SDValue &N) {
+SDNode *Select_ISD_FDIV_f80(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_extload(N1.getNode())) {
@@ -9736,7 +9760,7 @@ SDNode *Select_ISD_FDIV_f80(const SDValue &N) {
// Emits: (DIV_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -9752,7 +9776,7 @@ SDNode *Select_ISD_FDIV_f80(const SDValue &N) {
// Emits: (DIV_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extloadf64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -9768,7 +9792,7 @@ SDNode *Select_ISD_FDIV_f80(const SDValue &N) {
// Emits: (DIVR_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -9784,7 +9808,7 @@ SDNode *Select_ISD_FDIV_f80(const SDValue &N) {
// Emits: (DIVR_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extloadf64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -9797,48 +9821,48 @@ SDNode *Select_ISD_FDIV_f80(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::FILD &&
+ if (N1.getNode()->getOpcode() == X86ISD::FILD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getOperand(2);
+ SDValue N12 = N1.getNode()->getOperand(2);
// Pattern: (fdiv:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i16:Other))
// Emits: (DIV_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::DIV_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::DIV_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fdiv:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i32:Other))
// Emits: (DIV_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::DIV_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::DIV_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fdiv:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i16:Other))
// Emits: (DIVR_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::DIVR_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::DIVR_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fdiv:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i32:Other))
// Emits: (DIVR_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::DIVR_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::DIVR_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -9852,23 +9876,23 @@ SDNode *Select_ISD_FDIV_f80(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_FDIV_v4f32(const SDValue &N) {
+SDNode *Select_ISD_FDIV_v4f32(SDNode *N) {
// Pattern: (fdiv:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (DIVPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -9894,23 +9918,23 @@ SDNode *Select_ISD_FDIV_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FDIV_v2f64(const SDValue &N) {
+SDNode *Select_ISD_FDIV_v2f64(SDNode *N) {
// Pattern: (fdiv:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (DIVPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -9936,24 +9960,24 @@ SDNode *Select_ISD_FDIV_v2f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FMUL_f32(const SDValue &N) {
+SDNode *Select_ISD_FMUL_f32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fmul:f32 RFP32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
// Emits: (MUL_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_loadf32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -9970,14 +9994,14 @@ SDNode *Select_ISD_FMUL_f32(const SDValue &N) {
// Pattern: (fmul:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>, RFP32:f32:$src1)
// Emits: (MUL_Fp32m:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_loadf32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -9991,20 +10015,20 @@ SDNode *Select_ISD_FMUL_f32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fmul:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (MULSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -10021,13 +10045,13 @@ SDNode *Select_ISD_FMUL_f32(const SDValue &N) {
// Pattern: (fmul:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, FR32:f32:$src1)
// Emits: (MULSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -10041,66 +10065,66 @@ SDNode *Select_ISD_FMUL_f32(const SDValue &N) {
}
}
if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == X86ISD::FILD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == X86ISD::FILD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getOperand(2);
+ SDValue N12 = N1.getNode()->getOperand(2);
// Pattern: (fmul:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i16:Other))
// Emits: (MUL_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::MUL_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::MUL_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fmul:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i32:Other))
// Emits: (MUL_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::MUL_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::MUL_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- if (N0.getOpcode() == X86ISD::FILD &&
+ if (N0.getNode()->getOpcode() == X86ISD::FILD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N02 = N0.getOperand(2);
+ SDValue N02 = N0.getNode()->getOperand(2);
// Pattern: (fmul:f32 (X86fild:f32 addr:iPTR:$src2, i16:Other), RFP32:f32:$src1)
// Emits: (MUL_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02)->getVT() == MVT::i16) {
- SDNode *Result = Emit_98(N, X86::MUL_FpI16m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_97(N, X86::MUL_FpI16m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
// Pattern: (fmul:f32 (X86fild:f32 addr:iPTR:$src2, i32:Other), RFP32:f32:$src1)
// Emits: (MUL_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02)->getVT() == MVT::i32) {
- SDNode *Result = Emit_98(N, X86::MUL_FpI32m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_97(N, X86::MUL_FpI32m32, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -10128,16 +10152,16 @@ SDNode *Select_ISD_FMUL_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
+SDNode *Select_ISD_FMUL_f64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode())) {
// Pattern: (fmul:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
@@ -10145,7 +10169,7 @@ SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_load(N1.getNode()) &&
Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -10162,7 +10186,7 @@ SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extload(N1.getNode()) &&
Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -10176,10 +10200,10 @@ SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode())) {
// Pattern: (fmul:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>, RFP64:f64:$src1)
@@ -10187,7 +10211,7 @@ SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_load(N0.getNode()) &&
Predicate_loadf64(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -10204,7 +10228,7 @@ SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extload(N0.getNode()) &&
Predicate_extloadf32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -10219,20 +10243,20 @@ SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fmul:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (MULSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -10249,13 +10273,13 @@ SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
// Pattern: (fmul:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, FR64:f64:$src1)
// Emits: (MULSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -10269,66 +10293,66 @@ SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
}
}
if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == X86ISD::FILD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == X86ISD::FILD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getOperand(2);
+ SDValue N12 = N1.getNode()->getOperand(2);
// Pattern: (fmul:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i16:Other))
// Emits: (MUL_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::MUL_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::MUL_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fmul:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i32:Other))
// Emits: (MUL_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::MUL_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::MUL_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- if (N0.getOpcode() == X86ISD::FILD &&
+ if (N0.getNode()->getOpcode() == X86ISD::FILD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N02 = N0.getOperand(2);
+ SDValue N02 = N0.getNode()->getOperand(2);
// Pattern: (fmul:f64 (X86fild:f64 addr:iPTR:$src2, i16:Other), RFP64:f64:$src1)
// Emits: (MUL_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02)->getVT() == MVT::i16) {
- SDNode *Result = Emit_98(N, X86::MUL_FpI16m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_97(N, X86::MUL_FpI16m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
// Pattern: (fmul:f64 (X86fild:f64 addr:iPTR:$src2, i32:Other), RFP64:f64:$src1)
// Emits: (MUL_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02)->getVT() == MVT::i32) {
- SDNode *Result = Emit_98(N, X86::MUL_FpI32m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_97(N, X86::MUL_FpI32m64, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -10356,15 +10380,15 @@ SDNode *Select_ISD_FMUL_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FMUL_f80(const SDValue &N) {
+SDNode *Select_ISD_FMUL_f80(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_extload(N1.getNode())) {
@@ -10372,7 +10396,7 @@ SDNode *Select_ISD_FMUL_f80(const SDValue &N) {
// Emits: (MUL_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -10388,7 +10412,7 @@ SDNode *Select_ISD_FMUL_f80(const SDValue &N) {
// Emits: (MUL_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extloadf64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -10402,10 +10426,10 @@ SDNode *Select_ISD_FMUL_f80(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_extload(N0.getNode())) {
@@ -10413,7 +10437,7 @@ SDNode *Select_ISD_FMUL_f80(const SDValue &N) {
// Emits: (MUL_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extloadf32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -10429,7 +10453,7 @@ SDNode *Select_ISD_FMUL_f80(const SDValue &N) {
// Emits: (MUL_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extloadf64(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -10443,64 +10467,64 @@ SDNode *Select_ISD_FMUL_f80(const SDValue &N) {
}
}
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == X86ISD::FILD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == X86ISD::FILD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getOperand(2);
+ SDValue N12 = N1.getNode()->getOperand(2);
// Pattern: (fmul:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i16:Other))
// Emits: (MUL_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::MUL_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::MUL_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fmul:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i32:Other))
// Emits: (MUL_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::MUL_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::MUL_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- if (N0.getOpcode() == X86ISD::FILD &&
+ if (N0.getNode()->getOpcode() == X86ISD::FILD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N02 = N0.getOperand(2);
+ SDValue N02 = N0.getNode()->getOperand(2);
// Pattern: (fmul:f80 (X86fild:f80 addr:iPTR:$src2, i16:Other), RFP80:f80:$src1)
// Emits: (MUL_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02)->getVT() == MVT::i16) {
- SDNode *Result = Emit_98(N, X86::MUL_FpI16m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_97(N, X86::MUL_FpI16m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
// Pattern: (fmul:f80 (X86fild:f80 addr:iPTR:$src2, i32:Other), RFP80:f80:$src1)
// Emits: (MUL_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N02)->getVT() == MVT::i32) {
- SDNode *Result = Emit_98(N, X86::MUL_FpI32m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ if (cast<VTSDNode>(N02.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_97(N, X86::MUL_FpI32m80, MVT::f80, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -10514,24 +10538,24 @@ SDNode *Select_ISD_FMUL_f80(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_FMUL_v4f32(const SDValue &N) {
+SDNode *Select_ISD_FMUL_v4f32(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fmul:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (MULPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -10548,14 +10572,14 @@ SDNode *Select_ISD_FMUL_v4f32(const SDValue &N) {
// Pattern: (fmul:v4f32 (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v4f32:$src1)
// Emits: (MULPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -10581,24 +10605,24 @@ SDNode *Select_ISD_FMUL_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FMUL_v2f64(const SDValue &N) {
+SDNode *Select_ISD_FMUL_v2f64(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fmul:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (MULPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -10615,14 +10639,14 @@ SDNode *Select_ISD_FMUL_v2f64(const SDValue &N) {
// Pattern: (fmul:v2f64 (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2f64:$src1)
// Emits: (MULPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -10648,9 +10672,9 @@ SDNode *Select_ISD_FMUL_v2f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FNEG_f32(const SDValue &N) {
+SDNode *Select_ISD_FNEG_f32(SDNode *N) {
if ((!Subtarget->hasSSE1())) {
- SDNode *Result = Emit_71(N, X86::CHS_Fp32, MVT::f32);
+ SDNode *Result = Emit_72(N, X86::CHS_Fp32, MVT::f32);
return Result;
}
@@ -10658,9 +10682,9 @@ SDNode *Select_ISD_FNEG_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FNEG_f64(const SDValue &N) {
+SDNode *Select_ISD_FNEG_f64(SDNode *N) {
if ((!Subtarget->hasSSE2())) {
- SDNode *Result = Emit_71(N, X86::CHS_Fp64, MVT::f64);
+ SDNode *Result = Emit_72(N, X86::CHS_Fp64, MVT::f64);
return Result;
}
@@ -10668,26 +10692,26 @@ SDNode *Select_ISD_FNEG_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FNEG_f80(const SDValue &N) {
- SDNode *Result = Emit_71(N, X86::CHS_Fp80, MVT::f80);
+SDNode *Select_ISD_FNEG_f80(SDNode *N) {
+ SDNode *Result = Emit_72(N, X86::CHS_Fp80, MVT::f80);
return Result;
}
-SDNode *Select_ISD_FP_EXTEND_f64(const SDValue &N) {
+SDNode *Select_ISD_FP_EXTEND_f64(SDNode *N) {
// Pattern: (fextend:f64 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
// Emits: (CVTSS2SDrm:f64 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_loadf32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -10695,7 +10719,7 @@ SDNode *Select_ISD_FP_EXTEND_f64(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_78(N, X86::CVTSS2SDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::CVTSS2SDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -10706,9 +10730,9 @@ SDNode *Select_ISD_FP_EXTEND_f64(const SDValue &N) {
// Emits: (MOV_Fp3264:f64 RFP32:f32:$src)
// Pattern complexity = 3 cost = 1 size = 0
if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_71(N, X86::MOV_Fp3264, MVT::f64);
+ SDNode *Result = Emit_72(N, X86::MOV_Fp3264, MVT::f64);
return Result;
}
}
@@ -10717,9 +10741,9 @@ SDNode *Select_ISD_FP_EXTEND_f64(const SDValue &N) {
// Emits: (CVTSS2SDrr:f64 FR32:f32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_71(N, X86::CVTSS2SDrr, MVT::f64);
+ SDNode *Result = Emit_72(N, X86::CVTSS2SDrr, MVT::f64);
return Result;
}
}
@@ -10728,15 +10752,15 @@ SDNode *Select_ISD_FP_EXTEND_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FP_EXTEND_f80(const SDValue &N) {
+SDNode *Select_ISD_FP_EXTEND_f80(SDNode *N) {
// Pattern: (fextend:f80 RFP32:f32:$src)
// Emits: (MOV_Fp3280:f80 RFP32:f32:$src)
// Pattern complexity = 3 cost = 1 size = 0
if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_71(N, X86::MOV_Fp3280, MVT::f80);
+ SDNode *Result = Emit_72(N, X86::MOV_Fp3280, MVT::f80);
return Result;
}
}
@@ -10745,9 +10769,9 @@ SDNode *Select_ISD_FP_EXTEND_f80(const SDValue &N) {
// Emits: (MOV_Fp6480:f80 RFP64:f64:$src)
// Pattern complexity = 3 cost = 1 size = 0
if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_71(N, X86::MOV_Fp6480, MVT::f80);
+ SDNode *Result = Emit_72(N, X86::MOV_Fp6480, MVT::f80);
return Result;
}
}
@@ -10756,21 +10780,21 @@ SDNode *Select_ISD_FP_EXTEND_f80(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FP_ROUND_f32(const SDValue &N) {
+SDNode *Select_ISD_FP_ROUND_f32(SDNode *N) {
// Pattern: (fround:f32 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
// Emits: (CVTSD2SSrm:f32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2()) && (OptForSize)) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_loadf64(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -10778,20 +10802,20 @@ SDNode *Select_ISD_FP_ROUND_f32(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_78(N, X86::CVTSD2SSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::CVTSD2SSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (fround:f32 RFP64:f64:$src)
// Emits: (MOV_Fp6432:f32 RFP64:f64:$src)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_71(N, X86::MOV_Fp6432, MVT::f32);
+ SDNode *Result = Emit_72(N, X86::MOV_Fp6432, MVT::f32);
return Result;
}
@@ -10799,7 +10823,7 @@ SDNode *Select_ISD_FP_ROUND_f32(const SDValue &N) {
// Emits: (MOV_Fp8032:f32 RFP80:f80:$src)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::f80) {
- SDNode *Result = Emit_71(N, X86::MOV_Fp8032, MVT::f32);
+ SDNode *Result = Emit_72(N, X86::MOV_Fp8032, MVT::f32);
return Result;
}
}
@@ -10808,9 +10832,9 @@ SDNode *Select_ISD_FP_ROUND_f32(const SDValue &N) {
// Emits: (CVTSD2SSrr:f32 FR64:f64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_71(N, X86::CVTSD2SSrr, MVT::f32);
+ SDNode *Result = Emit_72(N, X86::CVTSD2SSrr, MVT::f32);
return Result;
}
}
@@ -10819,11 +10843,11 @@ SDNode *Select_ISD_FP_ROUND_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FP_ROUND_f64(const SDValue &N) {
+SDNode *Select_ISD_FP_ROUND_f64(SDNode *N) {
if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f80) {
- SDNode *Result = Emit_71(N, X86::MOV_Fp8064, MVT::f64);
+ SDNode *Result = Emit_72(N, X86::MOV_Fp8064, MVT::f64);
return Result;
}
}
@@ -10832,21 +10856,21 @@ SDNode *Select_ISD_FP_ROUND_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FP_TO_SINT_i32(const SDValue &N) {
+SDNode *Select_ISD_FP_TO_SINT_i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
// Pattern: (fp_to_sint:i32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
// Emits: (CVTTSS2SIrm:i32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_loadf32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -10854,7 +10878,7 @@ SDNode *Select_ISD_FP_TO_SINT_i32(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_78(N, X86::CVTTSS2SIrm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::CVTTSS2SIrm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -10865,14 +10889,14 @@ SDNode *Select_ISD_FP_TO_SINT_i32(const SDValue &N) {
// Emits: (CVTTSD2SIrm:i32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_loadf64(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -10880,7 +10904,7 @@ SDNode *Select_ISD_FP_TO_SINT_i32(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_78(N, X86::CVTTSD2SIrm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::CVTTSD2SIrm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -10892,9 +10916,9 @@ SDNode *Select_ISD_FP_TO_SINT_i32(const SDValue &N) {
// Emits: (CVTTSS2SIrr:i32 FR32:f32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_71(N, X86::CVTTSS2SIrr, MVT::i32);
+ SDNode *Result = Emit_72(N, X86::CVTTSS2SIrr, MVT::i32);
return Result;
}
}
@@ -10903,9 +10927,9 @@ SDNode *Select_ISD_FP_TO_SINT_i32(const SDValue &N) {
// Emits: (CVTTSD2SIrr:i32 FR64:f64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_71(N, X86::CVTTSD2SIrr, MVT::i32);
+ SDNode *Result = Emit_72(N, X86::CVTTSD2SIrr, MVT::i32);
return Result;
}
}
@@ -10914,21 +10938,21 @@ SDNode *Select_ISD_FP_TO_SINT_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FP_TO_SINT_i64(const SDValue &N) {
+SDNode *Select_ISD_FP_TO_SINT_i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
// Pattern: (fp_to_sint:i64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
// Emits: (CVTTSD2SI64rm:i64 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_loadf64(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -10936,7 +10960,7 @@ SDNode *Select_ISD_FP_TO_SINT_i64(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_78(N, X86::CVTTSD2SI64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::CVTTSD2SI64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -10947,14 +10971,14 @@ SDNode *Select_ISD_FP_TO_SINT_i64(const SDValue &N) {
// Emits: (CVTTSS2SI64rm:i64 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_loadf32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -10962,7 +10986,7 @@ SDNode *Select_ISD_FP_TO_SINT_i64(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_78(N, X86::CVTTSS2SI64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::CVTTSS2SI64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -10974,9 +10998,9 @@ SDNode *Select_ISD_FP_TO_SINT_i64(const SDValue &N) {
// Emits: (CVTTSD2SI64rr:i64 FR64:f64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_71(N, X86::CVTTSD2SI64rr, MVT::i64);
+ SDNode *Result = Emit_72(N, X86::CVTTSD2SI64rr, MVT::i64);
return Result;
}
}
@@ -10985,9 +11009,9 @@ SDNode *Select_ISD_FP_TO_SINT_i64(const SDValue &N) {
// Emits: (CVTTSS2SI64rr:i64 FR32:f32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_71(N, X86::CVTTSS2SI64rr, MVT::i64);
+ SDNode *Result = Emit_72(N, X86::CVTTSS2SI64rr, MVT::i64);
return Result;
}
}
@@ -10996,11 +11020,11 @@ SDNode *Select_ISD_FP_TO_SINT_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FP_TO_SINT_v2i32(const SDValue &N) {
+SDNode *Select_ISD_FP_TO_SINT_v2i32(SDNode *N) {
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_71(N, X86::Int_CVTTPD2PIrr, MVT::v2i32);
+ SDNode *Result = Emit_72(N, X86::Int_CVTTPD2PIrr, MVT::v2i32);
return Result;
}
}
@@ -11009,11 +11033,11 @@ SDNode *Select_ISD_FP_TO_SINT_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FP_TO_SINT_v4i32(const SDValue &N) {
+SDNode *Select_ISD_FP_TO_SINT_v4i32(SDNode *N) {
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_71(N, X86::Int_CVTTPS2DQrr, MVT::v4i32);
+ SDNode *Result = Emit_72(N, X86::Int_CVTTPS2DQrr, MVT::v4i32);
return Result;
}
}
@@ -11022,9 +11046,9 @@ SDNode *Select_ISD_FP_TO_SINT_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FSIN_f32(const SDValue &N) {
+SDNode *Select_ISD_FSIN_f32(SDNode *N) {
if ((!Subtarget->hasSSE1())) {
- SDNode *Result = Emit_71(N, X86::SIN_Fp32, MVT::f32);
+ SDNode *Result = Emit_72(N, X86::SIN_Fp32, MVT::f32);
return Result;
}
@@ -11032,9 +11056,9 @@ SDNode *Select_ISD_FSIN_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FSIN_f64(const SDValue &N) {
+SDNode *Select_ISD_FSIN_f64(SDNode *N) {
if ((!Subtarget->hasSSE2())) {
- SDNode *Result = Emit_71(N, X86::SIN_Fp64, MVT::f64);
+ SDNode *Result = Emit_72(N, X86::SIN_Fp64, MVT::f64);
return Result;
}
@@ -11042,32 +11066,32 @@ SDNode *Select_ISD_FSIN_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FSIN_f80(const SDValue &N) {
- SDNode *Result = Emit_71(N, X86::SIN_Fp80, MVT::f80);
+SDNode *Select_ISD_FSIN_f80(SDNode *N) {
+ SDNode *Result = Emit_72(N, X86::SIN_Fp80, MVT::f80);
return Result;
}
-SDNode *Select_ISD_FSQRT_f32(const SDValue &N) {
+SDNode *Select_ISD_FSQRT_f32(SDNode *N) {
// Pattern: (fsqrt:f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (SQRTSSm:f32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE1()) && (OptForSize)) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_78(N, X86::SQRTSSm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::SQRTSSm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -11078,7 +11102,7 @@ SDNode *Select_ISD_FSQRT_f32(const SDValue &N) {
// Emits: (SQRT_Fp32:f32 RFP32:f32:$src)
// Pattern complexity = 3 cost = 1 size = 0
if ((!Subtarget->hasSSE1())) {
- SDNode *Result = Emit_71(N, X86::SQRT_Fp32, MVT::f32);
+ SDNode *Result = Emit_72(N, X86::SQRT_Fp32, MVT::f32);
return Result;
}
@@ -11086,7 +11110,7 @@ SDNode *Select_ISD_FSQRT_f32(const SDValue &N) {
// Emits: (SQRTSSr:f32 FR32:f32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDNode *Result = Emit_71(N, X86::SQRTSSr, MVT::f32);
+ SDNode *Result = Emit_72(N, X86::SQRTSSr, MVT::f32);
return Result;
}
@@ -11094,27 +11118,27 @@ SDNode *Select_ISD_FSQRT_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FSQRT_f64(const SDValue &N) {
+SDNode *Select_ISD_FSQRT_f64(SDNode *N) {
// Pattern: (fsqrt:f64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (SQRTSDm:f64 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_78(N, X86::SQRTSDm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::SQRTSDm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -11125,7 +11149,7 @@ SDNode *Select_ISD_FSQRT_f64(const SDValue &N) {
// Emits: (SQRT_Fp64:f64 RFP64:f64:$src)
// Pattern complexity = 3 cost = 1 size = 0
if ((!Subtarget->hasSSE2())) {
- SDNode *Result = Emit_71(N, X86::SQRT_Fp64, MVT::f64);
+ SDNode *Result = Emit_72(N, X86::SQRT_Fp64, MVT::f64);
return Result;
}
@@ -11133,7 +11157,7 @@ SDNode *Select_ISD_FSQRT_f64(const SDValue &N) {
// Emits: (SQRTSDr:f64 FR64:f64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDNode *Result = Emit_71(N, X86::SQRTSDr, MVT::f64);
+ SDNode *Result = Emit_72(N, X86::SQRTSDr, MVT::f64);
return Result;
}
@@ -11141,33 +11165,33 @@ SDNode *Select_ISD_FSQRT_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FSQRT_f80(const SDValue &N) {
- SDNode *Result = Emit_71(N, X86::SQRT_Fp80, MVT::f80);
+SDNode *Select_ISD_FSQRT_f80(SDNode *N) {
+ SDNode *Result = Emit_72(N, X86::SQRT_Fp80, MVT::f80);
return Result;
}
-SDNode *Select_ISD_FSQRT_v4f32(const SDValue &N) {
+SDNode *Select_ISD_FSQRT_v4f32(SDNode *N) {
// Pattern: (fsqrt:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (SQRTPSm:v4f32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_78(N, X86::SQRTPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::SQRTPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -11178,7 +11202,7 @@ SDNode *Select_ISD_FSQRT_v4f32(const SDValue &N) {
// Emits: (SQRTPSr:v4f32 VR128:v4f32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDNode *Result = Emit_71(N, X86::SQRTPSr, MVT::v4f32);
+ SDNode *Result = Emit_72(N, X86::SQRTPSr, MVT::v4f32);
return Result;
}
@@ -11186,28 +11210,28 @@ SDNode *Select_ISD_FSQRT_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FSQRT_v2f64(const SDValue &N) {
+SDNode *Select_ISD_FSQRT_v2f64(SDNode *N) {
// Pattern: (fsqrt:v2f64 (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (SQRTPDm:v2f64 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_78(N, X86::SQRTPDm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::SQRTPDm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -11218,7 +11242,7 @@ SDNode *Select_ISD_FSQRT_v2f64(const SDValue &N) {
// Emits: (SQRTPDr:v2f64 VR128:v2f64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDNode *Result = Emit_71(N, X86::SQRTPDr, MVT::v2f64);
+ SDNode *Result = Emit_72(N, X86::SQRTPDr, MVT::v2f64);
return Result;
}
@@ -11226,19 +11250,19 @@ SDNode *Select_ISD_FSQRT_v2f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FSUB_f32(const SDValue &N) {
+SDNode *Select_ISD_FSUB_f32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_loadf32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -11268,15 +11292,15 @@ SDNode *Select_ISD_FSUB_f32(const SDValue &N) {
// Emits: (SUBSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -11290,50 +11314,50 @@ SDNode *Select_ISD_FSUB_f32(const SDValue &N) {
}
}
if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == X86ISD::FILD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == X86ISD::FILD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getOperand(2);
+ SDValue N12 = N1.getNode()->getOperand(2);
// Pattern: (fsub:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i16:Other))
// Emits: (SUB_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::SUB_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::SUB_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fsub:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i32:Other))
// Emits: (SUB_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::SUB_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::SUB_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fsub:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i16:Other))
// Emits: (SUBR_FpI16m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::SUBR_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::SUBR_FpI16m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fsub:f32 RFP32:f32:$src1, (X86fild:f32 addr:iPTR:$src2, i32:Other))
// Emits: (SUBR_FpI32m32:f32 RFP32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::SUBR_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::SUBR_FpI32m32, MVT::f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -11361,15 +11385,15 @@ SDNode *Select_ISD_FSUB_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
+SDNode *Select_ISD_FSUB_f64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode())) {
// Pattern: (fsub:f64 RFP64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
@@ -11377,7 +11401,7 @@ SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_load(N1.getNode()) &&
Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -11394,7 +11418,7 @@ SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extload(N1.getNode()) &&
Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -11411,7 +11435,7 @@ SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_load(N1.getNode()) &&
Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -11428,7 +11452,7 @@ SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extload(N1.getNode()) &&
Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -11447,15 +11471,15 @@ SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
// Emits: (SUBSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -11469,50 +11493,50 @@ SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
}
}
if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == X86ISD::FILD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == X86ISD::FILD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getOperand(2);
+ SDValue N12 = N1.getNode()->getOperand(2);
// Pattern: (fsub:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i16:Other))
// Emits: (SUB_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::SUB_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::SUB_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fsub:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i32:Other))
// Emits: (SUB_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::SUB_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::SUB_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fsub:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i16:Other))
// Emits: (SUBR_FpI16m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::SUBR_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::SUBR_FpI16m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fsub:f64 RFP64:f64:$src1, (X86fild:f64 addr:iPTR:$src2, i32:Other))
// Emits: (SUBR_FpI32m64:f64 RFP64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::SUBR_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::SUBR_FpI32m64, MVT::f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -11540,14 +11564,14 @@ SDNode *Select_ISD_FSUB_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FSUB_f80(const SDValue &N) {
+SDNode *Select_ISD_FSUB_f80(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_extload(N1.getNode())) {
@@ -11555,7 +11579,7 @@ SDNode *Select_ISD_FSUB_f80(const SDValue &N) {
// Emits: (SUB_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -11571,7 +11595,7 @@ SDNode *Select_ISD_FSUB_f80(const SDValue &N) {
// Emits: (SUB_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extloadf64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -11587,7 +11611,7 @@ SDNode *Select_ISD_FSUB_f80(const SDValue &N) {
// Emits: (SUBR_Fp80m32:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extloadf32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -11603,7 +11627,7 @@ SDNode *Select_ISD_FSUB_f80(const SDValue &N) {
// Emits: (SUBR_Fp80m64:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 0
if (Predicate_extloadf64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -11616,48 +11640,48 @@ SDNode *Select_ISD_FSUB_f80(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::FILD &&
+ if (N1.getNode()->getOpcode() == X86ISD::FILD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N12 = N1.getOperand(2);
+ SDValue N12 = N1.getNode()->getOperand(2);
// Pattern: (fsub:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i16:Other))
// Emits: (SUB_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::SUB_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::SUB_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fsub:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i32:Other))
// Emits: (SUB_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::SUB_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::SUB_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fsub:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i16:Other))
// Emits: (SUBR_FpI16m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i16) {
- SDNode *Result = Emit_97(N, X86::SUBR_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_96(N, X86::SUBR_FpI16m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
// Pattern: (fsub:f80 RFP80:f80:$src1, (X86fild:f80 addr:iPTR:$src2, i32:Other))
// Emits: (SUBR_FpI32m80:f80 RFP80:f80:$src1, addr:iPTR:$src2)
// Pattern complexity = 24 cost = 1 size = 0
- if (cast<VTSDNode>(N12)->getVT() == MVT::i32) {
- SDNode *Result = Emit_97(N, X86::SUBR_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ if (cast<VTSDNode>(N12.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_96(N, X86::SUBR_FpI32m80, MVT::f80, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -11671,23 +11695,23 @@ SDNode *Select_ISD_FSUB_f80(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_FSUB_v4f32(const SDValue &N) {
+SDNode *Select_ISD_FSUB_v4f32(SDNode *N) {
// Pattern: (fsub:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (SUBPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -11713,23 +11737,23 @@ SDNode *Select_ISD_FSUB_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FSUB_v2f64(const SDValue &N) {
+SDNode *Select_ISD_FSUB_v2f64(SDNode *N) {
// Pattern: (fsub:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (SUBPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -11755,7 +11779,7 @@ SDNode *Select_ISD_FSUB_v2f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FrameIndex_i32(const SDValue &N) {
+SDNode *Select_ISD_FrameIndex_i32(SDNode *N) {
// Pattern: lea32addr:i32:$src
// Emits: (LEA64_32r:i32 lea32addr:i32:$src)
@@ -11765,7 +11789,7 @@ SDNode *Select_ISD_FrameIndex_i32(const SDValue &N) {
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
@@ -11779,7 +11803,7 @@ SDNode *Select_ISD_FrameIndex_i32(const SDValue &N) {
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
@@ -11789,12 +11813,12 @@ SDNode *Select_ISD_FrameIndex_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_FrameIndex_i64(const SDValue &N) {
+SDNode *Select_ISD_FrameIndex_i64(SDNode *N) {
SDValue CPTmpN_0;
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
@@ -11803,53 +11827,53 @@ SDNode *Select_ISD_FrameIndex_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_99(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_98(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_100(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_99(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Tmp2, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i32(const SDValue &N) {
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i32(SDNode *N) {
// Pattern: (insertelt:v4i32 VR128:v4i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:iPTR):$src3)
// Emits: (PINSRDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
// Pattern complexity = 28 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_100(N, X86::PINSRDrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_99(N, X86::PINSRDrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -11861,11 +11885,11 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i32(const SDValue &N) {
// Emits: (PINSRDrr:v4i32 VR128:v4i32:$src1, GR32:i32:$src2, (imm:i32):$src3)
// Pattern complexity = 6 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_99(N, X86::PINSRDrr, MVT::v4i32);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_98(N, X86::PINSRDrr, MVT::v4i32);
return Result;
}
}
@@ -11874,32 +11898,32 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INSERT_VECTOR_ELT_v2i64(const SDValue &N) {
+SDNode *Select_ISD_INSERT_VECTOR_ELT_v2i64(SDNode *N) {
// Pattern: (insertelt:v2i64 VR128:v2i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:iPTR):$src3)
// Emits: (PINSRQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2, (imm:i32):$src3)
// Pattern complexity = 28 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_100(N, X86::PINSRQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_99(N, X86::PINSRQrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -11911,11 +11935,11 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v2i64(const SDValue &N) {
// Emits: (PINSRQrr:v2i64 VR128:v2i64:$src1, GR64:i64:$src2, (imm:i32):$src3)
// Pattern complexity = 6 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_99(N, X86::PINSRQrr, MVT::v2i64);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_98(N, X86::PINSRQrr, MVT::v2i64);
return Result;
}
}
@@ -11924,444 +11948,444 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v2i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_101(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_100(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N3, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
}
-DISABLE_INLINE SDNode *Emit_102(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain);
+DISABLE_INLINE SDNode *Emit_101(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Chain);
}
-DISABLE_INLINE SDNode *Emit_103(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_102(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 6);
-}
-DISABLE_INLINE SDNode *Emit_104(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 6);
+}
+DISABLE_INLINE SDNode *Emit_103(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EDI, N4, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EDI, N4, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
SDValue Ops0[] = { N2, N3, Chain, InFlag };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_105(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_104(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::RDI, N4, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::RDI, N4, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
SDValue Ops0[] = { N2, N3, Chain, InFlag };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_106(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_105(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EAX, N2, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EAX, N2, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::ECX, N3, InFlag).getNode();
+ ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::ECX, N3, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EDX, N4, InFlag).getNode();
+ ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EDX, N4, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain, InFlag);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Chain, InFlag);
}
-DISABLE_INLINE SDNode *Emit_107(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_106(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::ECX, N2, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::ECX, N2, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EAX, N3, InFlag).getNode();
+ ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EAX, N3, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain, InFlag);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Chain, InFlag);
}
-SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_VOID(SDNode *N) {
if ((Subtarget->hasSSE1())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_void:isVoid 718:iPTR, addr:iPTR:$dst, VR128:v4f32:$src)
+ // Pattern: (intrinsic_void:isVoid 714:iPTR, addr:iPTR:$dst, VR128:v4f32:$src)
// Emits: (MOVUPSmr_Int:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(718)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(714)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_101(N, X86::MOVUPSmr_Int, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_100(N, X86::MOVUPSmr_Int, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
- // Pattern: (intrinsic_void:isVoid 708:iPTR, addr:iPTR:$dst, VR128:v4f32:$src)
+ // Pattern: (intrinsic_void:isVoid 704:iPTR, addr:iPTR:$dst, VR128:v4f32:$src)
// Emits: (MOVNTPSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(708)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(704)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_101(N, X86::MOVNTPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_100(N, X86::MOVNTPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
- // Pattern: (intrinsic_void:isVoid 701:iPTR, addr:iPTR:$src)
+ // Pattern: (intrinsic_void:isVoid 697:iPTR, addr:iPTR:$src)
// Emits: (LDMXCSR:isVoid addr:iPTR:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(701)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(697)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_103(N, X86::LDMXCSR, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_102(N, X86::LDMXCSR, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
- // Pattern: (intrinsic_void:isVoid 717:iPTR, addr:iPTR:$dst)
+ // Pattern: (intrinsic_void:isVoid 713:iPTR, addr:iPTR:$dst)
// Emits: (STMXCSR:isVoid addr:iPTR:$dst)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(717)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(713)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_103(N, X86::STMXCSR, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_102(N, X86::STMXCSR, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
}
}
if ((Subtarget->hasSSE2())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_void:isVoid 596:iPTR, addr:iPTR:$dst, VR128:v2f64:$src)
+ // Pattern: (intrinsic_void:isVoid 592:iPTR, addr:iPTR:$dst, VR128:v2f64:$src)
// Emits: (MOVUPDmr_Int:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(596)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(592)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_101(N, X86::MOVUPDmr_Int, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_100(N, X86::MOVUPDmr_Int, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
- // Pattern: (intrinsic_void:isVoid 595:iPTR, addr:iPTR:$dst, VR128:v16i8:$src)
+ // Pattern: (intrinsic_void:isVoid 591:iPTR, addr:iPTR:$dst, VR128:v16i8:$src)
// Emits: (MOVDQUmr_Int:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(595)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(591)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_101(N, X86::MOVDQUmr_Int, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_100(N, X86::MOVDQUmr_Int, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
- // Pattern: (intrinsic_void:isVoid 541:iPTR, addr:iPTR:$dst, VR128:v2f64:$src)
+ // Pattern: (intrinsic_void:isVoid 537:iPTR, addr:iPTR:$dst, VR128:v2f64:$src)
// Emits: (MOVNTPDmr:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(541)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(537)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_101(N, X86::MOVNTPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_100(N, X86::MOVNTPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
- // Pattern: (intrinsic_void:isVoid 539:iPTR, addr:iPTR:$dst, VR128:v2i64:$src)
+ // Pattern: (intrinsic_void:isVoid 535:iPTR, addr:iPTR:$dst, VR128:v2i64:$src)
// Emits: (MOVNTDQmr:isVoid addr:iPTR:$dst, VR128:v2i64:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(539)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(535)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_101(N, X86::MOVNTDQmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_100(N, X86::MOVNTDQmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
- // Pattern: (intrinsic_void:isVoid 540:iPTR, addr:iPTR:$dst, GR32:i32:$src)
+ // Pattern: (intrinsic_void:isVoid 536:iPTR, addr:iPTR:$dst, GR32:i32:$src)
// Emits: (MOVNTImr:isVoid addr:iPTR:$dst, GR32:i32:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(540)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(536)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_101(N, X86::MOVNTImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_100(N, X86::MOVNTImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
- // Pattern: (intrinsic_void:isVoid 503:iPTR, addr:iPTR:$src)
+ // Pattern: (intrinsic_void:isVoid 499:iPTR, addr:iPTR:$src)
// Emits: (CLFLUSH:isVoid addr:iPTR:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(503)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(499)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_103(N, X86::CLFLUSH, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_102(N, X86::CLFLUSH, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
- // Pattern: (intrinsic_void:isVoid 594:iPTR, addr:iPTR:$dst, VR128:v4i32:$src)
+ // Pattern: (intrinsic_void:isVoid 590:iPTR, addr:iPTR:$dst, VR128:v4i32:$src)
// Emits: (MOVLQ128mr:isVoid addr:iPTR:$dst, VR128:v4i32:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(594)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(590)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_101(N, X86::MOVLQ128mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_100(N, X86::MOVLQ128mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_void:isVoid 456:iPTR, addr:iPTR:$dst, VR64:v1i64:$src)
+ // Pattern: (intrinsic_void:isVoid 452:iPTR, addr:iPTR:$dst, VR64:v1i64:$src)
// Emits: (MMX_MOVNTQmr:isVoid addr:iPTR:$dst, VR64:v1i64:$src)
// Pattern complexity = 26 cost = 1 size = 3
if ((Subtarget->hasMMX())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(456)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(452)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_101(N, X86::MMX_MOVNTQmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_100(N, X86::MMX_MOVNTQmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_void:isVoid 714:iPTR)
+ // Pattern: (intrinsic_void:isVoid 710:iPTR)
// Emits: (SFENCE:isVoid)
// Pattern complexity = 8 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(714)) {
- SDNode *Result = Emit_102(N, X86::SFENCE);
+ if (CN1 == INT64_C(710)) {
+ SDNode *Result = Emit_101(N, X86::SFENCE);
return Result;
}
}
}
if ((Subtarget->hasSSE2())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(532)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
+ if (CN1 == INT64_C(528)) {
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
- // Pattern: (intrinsic_void:isVoid 532:iPTR, VR128:v16i8:$src, VR128:v16i8:$mask, EDI:i32)
+ // Pattern: (intrinsic_void:isVoid 528:iPTR, VR128:v16i8:$src, VR128:v16i8:$mask, EDI:i32)
// Emits: (MASKMOVDQU:isVoid VR128:v16i8:$src, VR128:v16i8:$mask)
// Pattern complexity = 8 cost = 1 size = 3
if (N4.getValueType() == MVT::i32) {
- SDNode *Result = Emit_104(N, X86::MASKMOVDQU);
+ SDNode *Result = Emit_103(N, X86::MASKMOVDQU);
return Result;
}
- // Pattern: (intrinsic_void:isVoid 532:iPTR, VR128:v16i8:$src, VR128:v16i8:$mask, RDI:i64)
+ // Pattern: (intrinsic_void:isVoid 528:iPTR, VR128:v16i8:$src, VR128:v16i8:$mask, RDI:i64)
// Emits: (MASKMOVDQU64:isVoid VR128:v16i8:$src, VR128:v16i8:$mask)
// Pattern complexity = 8 cost = 1 size = 3
if (N4.getValueType() == MVT::i64) {
- SDNode *Result = Emit_105(N, X86::MASKMOVDQU64);
+ SDNode *Result = Emit_104(N, X86::MASKMOVDQU64);
return Result;
}
}
- // Pattern: (intrinsic_void:isVoid 529:iPTR)
+ // Pattern: (intrinsic_void:isVoid 525:iPTR)
// Emits: (LFENCE:isVoid)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(529)) {
- SDNode *Result = Emit_102(N, X86::LFENCE);
+ if (CN1 == INT64_C(525)) {
+ SDNode *Result = Emit_101(N, X86::LFENCE);
return Result;
}
- // Pattern: (intrinsic_void:isVoid 535:iPTR)
+ // Pattern: (intrinsic_void:isVoid 531:iPTR)
// Emits: (MFENCE:isVoid)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(535)) {
- SDNode *Result = Emit_102(N, X86::MFENCE);
+ if (CN1 == INT64_C(531)) {
+ SDNode *Result = Emit_101(N, X86::MFENCE);
return Result;
}
}
}
if ((Subtarget->hasSSE3())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_void:isVoid 611:iPTR, EAX:i32, ECX:i32, EDX:i32)
+ // Pattern: (intrinsic_void:isVoid 607:iPTR, EAX:i32, ECX:i32, EDX:i32)
// Emits: (MONITOR:isVoid)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(611)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
+ if (CN1 == INT64_C(607)) {
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
if (N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_106(N, X86::MONITOR);
+ SDNode *Result = Emit_105(N, X86::MONITOR);
return Result;
}
}
- // Pattern: (intrinsic_void:isVoid 612:iPTR, ECX:i32, EAX:i32)
+ // Pattern: (intrinsic_void:isVoid 608:iPTR, ECX:i32, EAX:i32)
// Emits: (MWAIT:isVoid)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(612)) {
- SDNode *Result = Emit_107(N, X86::MWAIT);
+ if (CN1 == INT64_C(608)) {
+ SDNode *Result = Emit_106(N, X86::MWAIT);
return Result;
}
}
}
if ((Subtarget->hasMMX())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_void:isVoid 453:iPTR)
+ // Pattern: (intrinsic_void:isVoid 449:iPTR)
// Emits: (MMX_EMMS:isVoid)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(453)) {
- SDNode *Result = Emit_102(N, X86::MMX_EMMS);
+ if (CN1 == INT64_C(449)) {
+ SDNode *Result = Emit_101(N, X86::MMX_EMMS);
return Result;
}
- // Pattern: (intrinsic_void:isVoid 454:iPTR)
+ // Pattern: (intrinsic_void:isVoid 450:iPTR)
// Emits: (MMX_FEMMS:isVoid)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(454)) {
- SDNode *Result = Emit_102(N, X86::MMX_FEMMS);
+ if (CN1 == INT64_C(450)) {
+ SDNode *Result = Emit_101(N, X86::MMX_FEMMS);
return Result;
}
- // Pattern: (intrinsic_void:isVoid 455:iPTR, VR64:v8i8:$src, VR64:v8i8:$mask, EDI:i32)
+ // Pattern: (intrinsic_void:isVoid 451:iPTR, VR64:v8i8:$src, VR64:v8i8:$mask, EDI:i32)
// Emits: (MMX_MASKMOVQ:isVoid VR64:v8i8:$src, VR64:v8i8:$mask)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(455)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
+ if (CN1 == INT64_C(451)) {
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
if (N4.getValueType() == MVT::i32) {
- SDNode *Result = Emit_104(N, X86::MMX_MASKMOVQ);
+ SDNode *Result = Emit_103(N, X86::MMX_MASKMOVQ);
return Result;
}
}
}
}
- // Pattern: (intrinsic_void:isVoid 455:iPTR, VR64:v8i8:$src, VR64:v8i8:$mask, RDI:i64)
+ // Pattern: (intrinsic_void:isVoid 451:iPTR, VR64:v8i8:$src, VR64:v8i8:$mask, RDI:i64)
// Emits: (MMX_MASKMOVQ64:isVoid VR64:v8i8:$src, VR64:v8i8:$mask)
// Pattern complexity = 8 cost = 1 size = 3
if ((Subtarget->hasMMX()) && (Subtarget->is64Bit())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(455)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
+ if (CN1 == INT64_C(451)) {
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
if (N4.getValueType() == MVT::i64) {
- SDNode *Result = Emit_105(N, X86::MMX_MASKMOVQ64);
+ SDNode *Result = Emit_104(N, X86::MMX_MASKMOVQ64);
return Result;
}
}
@@ -12372,142 +12396,142 @@ SDNode *Select_ISD_INTRINSIC_VOID(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_108(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1);
+DISABLE_INLINE SDNode *Emit_107(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1);
}
-DISABLE_INLINE SDNode *Emit_109(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_108(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_110(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue Chain2 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
+DISABLE_INLINE SDNode *Emit_109(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N2)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N2.getNode())->getMemOperand();
SDValue Ops0[] = { N1, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4, Chain2 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N2.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_111(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N2);
-}
-DISABLE_INLINE SDNode *Emit_112(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_110(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N2);
+}
+DISABLE_INLINE SDNode *Emit_111(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i8);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::i32, N1, N2, Tmp4);
-}
-DISABLE_INLINE SDNode *Emit_113(const SDValue &N, unsigned Opc0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue Chain2 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- SDValue N3 = N.getOperand(3);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::i32, N1, N2, Tmp4);
+}
+DISABLE_INLINE SDNode *Emit_112(SDNode *N, unsigned Opc0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue N3 = N->getOperand(3);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i8);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N2)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N2.getNode())->getMemOperand();
SDValue Ops0[] = { N1, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4, Tmp4, Chain2 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::i32, MVT::Other, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::i32, MVT::Other, Ops0, 8);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N2.getNode(), 1), SDValue(ResNode, 2));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_114(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
+DISABLE_INLINE SDNode *Emit_113(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N5)->getZExtValue()), MVT::i8);
SDValue Chain = CurDAG->getEntryNode();
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EAX, N2, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EAX, N2, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EDX, N4, InFlag).getNode();
+ ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EDX, N4, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
SDValue Ops0[] = { N1, N3, Tmp4, InFlag };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::i32, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_115(const SDValue &N, unsigned Opc0, SDValue &CPTmpN31_0, SDValue &CPTmpN31_1, SDValue &CPTmpN31_2, SDValue &CPTmpN31_3, SDValue &CPTmpN31_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue Chain3 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::i32, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_114(SDNode *N, unsigned Opc0, SDValue &CPTmpN31_0, SDValue &CPTmpN31_1, SDValue &CPTmpN31_2, SDValue &CPTmpN31_3, SDValue &CPTmpN31_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue Chain3 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N5)->getZExtValue()), MVT::i8);
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain3, N.getDebugLoc(), X86::EAX, N2, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain3, N->getDebugLoc(), X86::EAX, N2, InFlag).getNode();
Chain3 = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- ResNode = CurDAG->getCopyToReg(Chain3, N.getDebugLoc(), X86::EDX, N4, InFlag).getNode();
+ ResNode = CurDAG->getCopyToReg(Chain3, N->getDebugLoc(), X86::EDX, N4, InFlag).getNode();
Chain3 = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N3)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N3.getNode())->getMemOperand();
SDValue Ops0[] = { N1, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4, Tmp4, Chain3, InFlag };
- ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::i32, MVT::Other, Ops0, 9);
+ ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::i32, MVT::Other, Ops0, 9);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N3.getNode(), 1), SDValue(ResNode, 2));
return ResNode;
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((Subtarget->hasSSE42())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i32 672:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:i32 668:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
// Emits: (PCMPISTRIrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(672)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(668)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_113(N, X86::PCMPISTRIrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_112(N, X86::PCMPISTRIrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -12515,28 +12539,28 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 673:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:i32 669:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
// Emits: (PCMPISTRIArm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(673)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(669)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_113(N, X86::PCMPISTRIArm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_112(N, X86::PCMPISTRIArm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -12544,28 +12568,28 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 674:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:i32 670:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
// Emits: (PCMPISTRICrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(674)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(670)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_113(N, X86::PCMPISTRICrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_112(N, X86::PCMPISTRICrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -12573,28 +12597,28 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 675:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:i32 671:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
// Emits: (PCMPISTRIOrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(675)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(671)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_113(N, X86::PCMPISTRIOrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_112(N, X86::PCMPISTRIOrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -12602,28 +12626,28 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 676:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:i32 672:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
// Emits: (PCMPISTRISrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(676)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(672)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_113(N, X86::PCMPISTRISrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_112(N, X86::PCMPISTRISrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -12631,28 +12655,28 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 677:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:i32 673:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
// Emits: (PCMPISTRIZrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(677)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(673)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_113(N, X86::PCMPISTRIZrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_112(N, X86::PCMPISTRIZrm, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -12660,30 +12684,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 664:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:i32 660:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRIrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(664)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(660)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::LOAD &&
N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain3 = N3.getOperand(0);
+ IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
+ SDValue Chain3 = N3.getNode()->getOperand(0);
if (Predicate_unindexedload(N3.getNode()) &&
Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getOperand(1);
+ SDValue N31 = N3.getNode()->getOperand(1);
SDValue CPTmpN31_0;
SDValue CPTmpN31_1;
SDValue CPTmpN31_2;
SDValue CPTmpN31_3;
SDValue CPTmpN31_4;
if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
- if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_115(N, X86::PCMPESTRIrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_114(N, X86::PCMPESTRIrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
return Result;
}
}
@@ -12691,30 +12715,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 665:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:i32 661:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRIArm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(665)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(661)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::LOAD &&
N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain3 = N3.getOperand(0);
+ IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
+ SDValue Chain3 = N3.getNode()->getOperand(0);
if (Predicate_unindexedload(N3.getNode()) &&
Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getOperand(1);
+ SDValue N31 = N3.getNode()->getOperand(1);
SDValue CPTmpN31_0;
SDValue CPTmpN31_1;
SDValue CPTmpN31_2;
SDValue CPTmpN31_3;
SDValue CPTmpN31_4;
if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
- if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_115(N, X86::PCMPESTRIArm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_114(N, X86::PCMPESTRIArm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
return Result;
}
}
@@ -12722,30 +12746,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 666:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:i32 662:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRICrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(666)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(662)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::LOAD &&
N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain3 = N3.getOperand(0);
+ IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
+ SDValue Chain3 = N3.getNode()->getOperand(0);
if (Predicate_unindexedload(N3.getNode()) &&
Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getOperand(1);
+ SDValue N31 = N3.getNode()->getOperand(1);
SDValue CPTmpN31_0;
SDValue CPTmpN31_1;
SDValue CPTmpN31_2;
SDValue CPTmpN31_3;
SDValue CPTmpN31_4;
if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
- if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_115(N, X86::PCMPESTRICrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_114(N, X86::PCMPESTRICrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
return Result;
}
}
@@ -12753,30 +12777,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 667:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:i32 663:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRIOrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(667)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(663)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::LOAD &&
N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain3 = N3.getOperand(0);
+ IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
+ SDValue Chain3 = N3.getNode()->getOperand(0);
if (Predicate_unindexedload(N3.getNode()) &&
Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getOperand(1);
+ SDValue N31 = N3.getNode()->getOperand(1);
SDValue CPTmpN31_0;
SDValue CPTmpN31_1;
SDValue CPTmpN31_2;
SDValue CPTmpN31_3;
SDValue CPTmpN31_4;
if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
- if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_115(N, X86::PCMPESTRIOrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_114(N, X86::PCMPESTRIOrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
return Result;
}
}
@@ -12784,30 +12808,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 668:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:i32 664:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRISrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(668)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(664)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::LOAD &&
N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain3 = N3.getOperand(0);
+ IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
+ SDValue Chain3 = N3.getNode()->getOperand(0);
if (Predicate_unindexedload(N3.getNode()) &&
Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getOperand(1);
+ SDValue N31 = N3.getNode()->getOperand(1);
SDValue CPTmpN31_0;
SDValue CPTmpN31_1;
SDValue CPTmpN31_2;
SDValue CPTmpN31_3;
SDValue CPTmpN31_4;
if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
- if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_115(N, X86::PCMPESTRISrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_114(N, X86::PCMPESTRISrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
return Result;
}
}
@@ -12815,30 +12839,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:i32 669:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:i32 665:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRIZrm:isVoid VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(669)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(665)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::LOAD &&
N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain3 = N3.getOperand(0);
+ IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
+ SDValue Chain3 = N3.getNode()->getOperand(0);
if (Predicate_unindexedload(N3.getNode()) &&
Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getOperand(1);
+ SDValue N31 = N3.getNode()->getOperand(1);
SDValue CPTmpN31_0;
SDValue CPTmpN31_1;
SDValue CPTmpN31_2;
SDValue CPTmpN31_3;
SDValue CPTmpN31_4;
if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
- if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_115(N, X86::PCMPESTRIZrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_114(N, X86::PCMPESTRIZrm, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
return Result;
}
}
@@ -12848,55 +12872,55 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i32 694:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Pattern: (intrinsic_wo_chain:i32 690:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (Int_CVTSS2SIrm:i32 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(694)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(690)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSS2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::Int_CVTSS2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:i32 698:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Pattern: (intrinsic_wo_chain:i32 694:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (Int_CVTTSS2SIrm:i32 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(698)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(694)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTTSS2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::Int_CVTTSS2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -12905,55 +12929,55 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i32 518:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Pattern: (intrinsic_wo_chain:i32 514:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (Int_CVTSD2SIrm:i32 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(518)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(514)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSD2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::Int_CVTSD2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:i32 526:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Pattern: (intrinsic_wo_chain:i32 522:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (Int_CVTTSD2SIrm:i32 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(526)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(522)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTTSD2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::Int_CVTTSD2SIrm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -12962,83 +12986,83 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE42())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i32 663:iPTR, GR32:i32:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Pattern: (intrinsic_wo_chain:i32 659:iPTR, GR32:i32:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (CRC32m8:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(663)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(659)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::CRC32m8, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::CRC32m8, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:i32 660:iPTR, GR32:i32:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Pattern: (intrinsic_wo_chain:i32 656:iPTR, GR32:i32:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (CRC32m16:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(660)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(656)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::CRC32m16, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::CRC32m16, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:i32 661:iPTR, GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Pattern: (intrinsic_wo_chain:i32 657:iPTR, GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (CRC32m32:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(661)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(657)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::CRC32m32, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::CRC32m32, MVT::i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -13048,292 +13072,292 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE42())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i32 672:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:i32 668:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Emits: (PCMPISTRIrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(672)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPISTRIrr);
+ if (CN1 == INT64_C(668)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_111(N, X86::PCMPISTRIrr);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:i32 673:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:i32 669:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Emits: (PCMPISTRIArr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(673)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPISTRIArr);
+ if (CN1 == INT64_C(669)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_111(N, X86::PCMPISTRIArr);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:i32 674:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:i32 670:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Emits: (PCMPISTRICrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(674)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPISTRICrr);
+ if (CN1 == INT64_C(670)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_111(N, X86::PCMPISTRICrr);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:i32 675:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:i32 671:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Emits: (PCMPISTRIOrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(675)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPISTRIOrr);
+ if (CN1 == INT64_C(671)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_111(N, X86::PCMPISTRIOrr);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:i32 676:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:i32 672:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Emits: (PCMPISTRISrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(676)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPISTRISrr);
+ if (CN1 == INT64_C(672)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_111(N, X86::PCMPISTRISrr);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:i32 677:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:i32 673:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Emits: (PCMPISTRIZrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(677)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_112(N, X86::PCMPISTRIZrr);
+ if (CN1 == INT64_C(673)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_111(N, X86::PCMPISTRIZrr);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:i32 664:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:i32 660:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRIrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(664)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
- if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_114(N, X86::PCMPESTRIrr);
+ if (CN1 == INT64_C(660)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_113(N, X86::PCMPESTRIrr);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:i32 665:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:i32 661:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRIArr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(665)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
- if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_114(N, X86::PCMPESTRIArr);
+ if (CN1 == INT64_C(661)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_113(N, X86::PCMPESTRIArr);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:i32 666:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:i32 662:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRICrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(666)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
- if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_114(N, X86::PCMPESTRICrr);
+ if (CN1 == INT64_C(662)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_113(N, X86::PCMPESTRICrr);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:i32 667:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:i32 663:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRIOrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(667)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
- if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_114(N, X86::PCMPESTRIOrr);
+ if (CN1 == INT64_C(663)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_113(N, X86::PCMPESTRIOrr);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:i32 668:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:i32 664:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRISrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(668)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
- if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_114(N, X86::PCMPESTRISrr);
+ if (CN1 == INT64_C(664)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_113(N, X86::PCMPESTRISrr);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:i32 669:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:i32 665:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRIZrr:isVoid VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(669)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
- if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_114(N, X86::PCMPESTRIZrr);
+ if (CN1 == INT64_C(665)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_113(N, X86::PCMPESTRIZrr);
return Result;
}
}
}
}
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i32 694:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:i32 690:iPTR, VR128:v4f32:$src)
// Emits: (Int_CVTSS2SIrr:i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(694)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTSS2SIrr, MVT::i32);
+ if (CN1 == INT64_C(690)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTSS2SIrr, MVT::i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:i32 698:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:i32 694:iPTR, VR128:v4f32:$src)
// Emits: (Int_CVTTSS2SIrr:i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(698)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTSS2SIrr, MVT::i32);
+ if (CN1 == INT64_C(694)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTTSS2SIrr, MVT::i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:i32 707:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:i32 703:iPTR, VR128:v4f32:$src)
// Emits: (MOVMSKPSrr:i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(707)) {
- SDNode *Result = Emit_108(N, X86::MOVMSKPSrr, MVT::i32);
+ if (CN1 == INT64_C(703)) {
+ SDNode *Result = Emit_107(N, X86::MOVMSKPSrr, MVT::i32);
return Result;
}
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i32 538:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:i32 534:iPTR, VR128:v2f64:$src)
// Emits: (MOVMSKPDrr:i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(538)) {
- SDNode *Result = Emit_108(N, X86::MOVMSKPDrr, MVT::i32);
+ if (CN1 == INT64_C(534)) {
+ SDNode *Result = Emit_107(N, X86::MOVMSKPDrr, MVT::i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:i32 518:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:i32 514:iPTR, VR128:v2f64:$src)
// Emits: (Int_CVTSD2SIrr:i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(518)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTSD2SIrr, MVT::i32);
+ if (CN1 == INT64_C(514)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTSD2SIrr, MVT::i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:i32 526:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:i32 522:iPTR, VR128:v2f64:$src)
// Emits: (Int_CVTTSD2SIrr:i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(526)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTSD2SIrr, MVT::i32);
+ if (CN1 == INT64_C(522)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTTSD2SIrr, MVT::i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:i32 563:iPTR, VR128:v16i8:$src)
+ // Pattern: (intrinsic_wo_chain:i32 559:iPTR, VR128:v16i8:$src)
// Emits: (PMOVMSKBrr:i32 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(563)) {
- SDNode *Result = Emit_108(N, X86::PMOVMSKBrr, MVT::i32);
+ if (CN1 == INT64_C(559)) {
+ SDNode *Result = Emit_107(N, X86::PMOVMSKBrr, MVT::i32);
return Result;
}
}
}
if ((Subtarget->hasSSE42())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i32 663:iPTR, GR32:i32:$src1, GR8:i8:$src2)
+ // Pattern: (intrinsic_wo_chain:i32 659:iPTR, GR32:i32:$src1, GR8:i8:$src2)
// Emits: (CRC32r8:i32 GR32:i32:$src1, GR8:i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(663)) {
- SDNode *Result = Emit_111(N, X86::CRC32r8, MVT::i32);
+ if (CN1 == INT64_C(659)) {
+ SDNode *Result = Emit_110(N, X86::CRC32r8, MVT::i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:i32 660:iPTR, GR32:i32:$src1, GR16:i16:$src2)
+ // Pattern: (intrinsic_wo_chain:i32 656:iPTR, GR32:i32:$src1, GR16:i16:$src2)
// Emits: (CRC32r16:i32 GR32:i32:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(660)) {
- SDNode *Result = Emit_111(N, X86::CRC32r16, MVT::i32);
+ if (CN1 == INT64_C(656)) {
+ SDNode *Result = Emit_110(N, X86::CRC32r16, MVT::i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:i32 661:iPTR, GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern: (intrinsic_wo_chain:i32 657:iPTR, GR32:i32:$src1, GR32:i32:$src2)
// Emits: (CRC32r32:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(661)) {
- SDNode *Result = Emit_111(N, X86::CRC32r32, MVT::i32);
+ if (CN1 == INT64_C(657)) {
+ SDNode *Result = Emit_110(N, X86::CRC32r32, MVT::i32);
return Result;
}
}
}
- // Pattern: (intrinsic_wo_chain:i32 477:iPTR, VR64:v8i8:$src)
+ // Pattern: (intrinsic_wo_chain:i32 473:iPTR, VR64:v8i8:$src)
// Emits: (MMX_PMOVMSKBrr:i32 VR64:v8i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
if ((Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(477)) {
- SDNode *Result = Emit_108(N, X86::MMX_PMOVMSKBrr, MVT::i32);
+ if (CN1 == INT64_C(473)) {
+ SDNode *Result = Emit_107(N, X86::MMX_PMOVMSKBrr, MVT::i32);
return Result;
}
}
@@ -13343,58 +13367,58 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i64 519:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Pattern: (intrinsic_wo_chain:i64 515:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (Int_CVTSD2SI64rm:i64 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(519)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(515)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSD2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::Int_CVTSD2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:i64 527:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Pattern: (intrinsic_wo_chain:i64 523:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (Int_CVTTSD2SI64rm:i64 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(527)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(523)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTTSD2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::Int_CVTTSD2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -13403,55 +13427,55 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i64 695:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Pattern: (intrinsic_wo_chain:i64 691:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (Int_CVTSS2SI64rm:i64 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(695)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(691)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTSS2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::Int_CVTSS2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:i64 699:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Pattern: (intrinsic_wo_chain:i64 695:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (Int_CVTTSS2SI64rm:i64 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(699)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(695)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTTSS2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::Int_CVTTSS2SI64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -13460,31 +13484,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:i64 662:iPTR, GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Pattern: (intrinsic_wo_chain:i64 658:iPTR, GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (CRC64m64:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if ((Subtarget->hasSSE42())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(662)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(658)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::CRC64m64, MVT::i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::CRC64m64, MVT::i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -13494,62 +13518,62 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i64 519:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:i64 515:iPTR, VR128:v2f64:$src)
// Emits: (Int_CVTSD2SI64rr:i64 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(519)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTSD2SI64rr, MVT::i64);
+ if (CN1 == INT64_C(515)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTSD2SI64rr, MVT::i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:i64 527:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:i64 523:iPTR, VR128:v2f64:$src)
// Emits: (Int_CVTTSD2SI64rr:i64 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(527)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTSD2SI64rr, MVT::i64);
+ if (CN1 == INT64_C(523)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTTSD2SI64rr, MVT::i64);
return Result;
}
}
}
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:i64 695:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:i64 691:iPTR, VR128:v4f32:$src)
// Emits: (Int_CVTSS2SI64rr:i64 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(695)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTSS2SI64rr, MVT::i64);
+ if (CN1 == INT64_C(691)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTSS2SI64rr, MVT::i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:i64 699:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:i64 695:iPTR, VR128:v4f32:$src)
// Emits: (Int_CVTTSS2SI64rr:i64 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(699)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTSS2SI64rr, MVT::i64);
+ if (CN1 == INT64_C(695)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTTSS2SI64rr, MVT::i64);
return Result;
}
}
}
- // Pattern: (intrinsic_wo_chain:i64 662:iPTR, GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern: (intrinsic_wo_chain:i64 658:iPTR, GR64:i64:$src1, GR64:i64:$src2)
// Emits: (CRC64r64:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if ((Subtarget->hasSSE42())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(662)) {
- SDNode *Result = Emit_111(N, X86::CRC64r64, MVT::i64);
+ if (CN1 == INT64_C(658)) {
+ SDNode *Result = Emit_110(N, X86::CRC64r64, MVT::i64);
return Result;
}
}
@@ -13559,74 +13583,74 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_116(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
+DISABLE_INLINE SDNode *Emit_115(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_117(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN201_0, SDValue &CPTmpN201_1, SDValue &CPTmpN201_2, SDValue &CPTmpN201_3, SDValue &CPTmpN201_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N20 = N2.getOperand(0);
- SDValue Chain20 = N20.getOperand(0);
- SDValue N201 = N20.getOperand(1);
+DISABLE_INLINE SDNode *Emit_116(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN201_0, SDValue &CPTmpN201_1, SDValue &CPTmpN201_2, SDValue &CPTmpN201_3, SDValue &CPTmpN201_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ SDValue N201 = N20.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N20)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N20.getNode())->getMemOperand();
SDValue Ops0[] = { N1, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4, Chain20 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N20.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_118(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_117(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { N2, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i8 726:iPTR, (bitconvert:v8i8 (ld:v8i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v8i8 722:iPTR, (bitconvert:v8i8 (ld:v8i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PABSBrm64:v8i8 addr:iPTR:$src)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(726)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(722)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -13634,7 +13658,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_116(N, X86::PABSBrm64, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_115(N, X86::PABSBrm64, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -13642,23 +13666,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i8 750:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v8i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v8i8 746:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v8i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PSHUFBrm64:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(750)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(746)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -13666,7 +13690,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_117(N, X86::PSHUFBrm64, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSHUFBrm64, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13674,23 +13698,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i8 752:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v8i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v8i8 748:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v8i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PSIGNBrm64:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(752)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(748)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -13698,7 +13722,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_117(N, X86::PSIGNBrm64, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSIGNBrm64, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13708,27 +13732,27 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
}
}
if ((Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i8 460:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v8i8 456:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PADDSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(460)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(456)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -13736,7 +13760,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PADDSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PADDSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13744,22 +13768,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i8 462:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v8i8 458:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PADDUSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(462)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(458)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -13767,7 +13791,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PADDUSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PADDUSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13775,22 +13799,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i8 498:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v8i8 494:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PSUBSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(498)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(494)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -13798,7 +13822,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PSUBSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PSUBSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13806,22 +13830,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i8 500:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v8i8 496:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PSUBUSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(500)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(496)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -13829,7 +13853,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PSUBUSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PSUBUSBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13837,22 +13861,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i8 464:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v8i8 460:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PAVGBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(464)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(460)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -13860,7 +13884,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PAVGBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PAVGBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13868,22 +13892,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i8 476:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v8i8 472:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PMINUBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(476)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(472)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -13891,7 +13915,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMINUBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PMINUBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13899,22 +13923,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i8 474:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v8i8 470:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PMAXUBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(474)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(470)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -13922,7 +13946,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMAXUBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PMAXUBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13930,22 +13954,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i8 466:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v8i8 462:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PCMPEQBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(466)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(462)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -13953,7 +13977,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PCMPEQBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PCMPEQBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13961,22 +13985,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i8 469:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v8i8 465:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PCMPGTBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(469)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(465)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -13984,7 +14008,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PCMPGTBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PCMPGTBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -13992,22 +14016,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i8 458:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v8i8 454:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PACKSSWBrm:v8i8 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(458)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(454)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -14015,7 +14039,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PACKSSWBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PACKSSWBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14023,22 +14047,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i8 459:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v8i8 455:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PACKUSWBrm:v8i8 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(459)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(455)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -14046,7 +14070,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PACKUSWBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PACKUSWBrm, MVT::v8i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14054,30 +14078,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i8 460:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Pattern: (intrinsic_wo_chain:v8i8 456:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
// Emits: (MMX_PADDSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(460)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(456)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_118(N, X86::MMX_PADDSBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PADDSBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -14086,30 +14110,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i8 462:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Pattern: (intrinsic_wo_chain:v8i8 458:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
// Emits: (MMX_PADDUSBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(462)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(458)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_118(N, X86::MMX_PADDUSBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PADDUSBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -14118,30 +14142,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i8 464:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Pattern: (intrinsic_wo_chain:v8i8 460:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
// Emits: (MMX_PAVGBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(464)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(460)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_118(N, X86::MMX_PAVGBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PAVGBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -14150,30 +14174,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i8 476:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Pattern: (intrinsic_wo_chain:v8i8 472:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
// Emits: (MMX_PMINUBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(476)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(472)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_118(N, X86::MMX_PMINUBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PMINUBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -14182,30 +14206,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i8 474:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Pattern: (intrinsic_wo_chain:v8i8 470:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
// Emits: (MMX_PMAXUBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(474)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(470)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_118(N, X86::MMX_PMAXUBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PMAXUBrm, MVT::v8i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -14217,127 +14241,127 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
}
}
if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i8 726:iPTR, VR64:v8i8:$src)
+ // Pattern: (intrinsic_wo_chain:v8i8 722:iPTR, VR64:v8i8:$src)
// Emits: (PABSBrr64:v8i8 VR64:v8i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(726)) {
- SDNode *Result = Emit_108(N, X86::PABSBrr64, MVT::v8i8);
+ if (CN1 == INT64_C(722)) {
+ SDNode *Result = Emit_107(N, X86::PABSBrr64, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 750:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 746:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (PSHUFBrr64:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(750)) {
- SDNode *Result = Emit_111(N, X86::PSHUFBrr64, MVT::v8i8);
+ if (CN1 == INT64_C(746)) {
+ SDNode *Result = Emit_110(N, X86::PSHUFBrr64, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 752:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 748:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (PSIGNBrr64:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(752)) {
- SDNode *Result = Emit_111(N, X86::PSIGNBrr64, MVT::v8i8);
+ if (CN1 == INT64_C(748)) {
+ SDNode *Result = Emit_110(N, X86::PSIGNBrr64, MVT::v8i8);
return Result;
}
}
}
if ((Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i8 460:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 456:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (MMX_PADDSBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(460)) {
- SDNode *Result = Emit_111(N, X86::MMX_PADDSBrr, MVT::v8i8);
+ if (CN1 == INT64_C(456)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PADDSBrr, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 462:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 458:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (MMX_PADDUSBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(462)) {
- SDNode *Result = Emit_111(N, X86::MMX_PADDUSBrr, MVT::v8i8);
+ if (CN1 == INT64_C(458)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PADDUSBrr, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 498:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 494:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (MMX_PSUBSBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(498)) {
- SDNode *Result = Emit_111(N, X86::MMX_PSUBSBrr, MVT::v8i8);
+ if (CN1 == INT64_C(494)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PSUBSBrr, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 500:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 496:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (MMX_PSUBUSBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(500)) {
- SDNode *Result = Emit_111(N, X86::MMX_PSUBUSBrr, MVT::v8i8);
+ if (CN1 == INT64_C(496)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PSUBUSBrr, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 464:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 460:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (MMX_PAVGBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(464)) {
- SDNode *Result = Emit_111(N, X86::MMX_PAVGBrr, MVT::v8i8);
+ if (CN1 == INT64_C(460)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PAVGBrr, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 476:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 472:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (MMX_PMINUBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(476)) {
- SDNode *Result = Emit_111(N, X86::MMX_PMINUBrr, MVT::v8i8);
+ if (CN1 == INT64_C(472)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PMINUBrr, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 474:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 470:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (MMX_PMAXUBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(474)) {
- SDNode *Result = Emit_111(N, X86::MMX_PMAXUBrr, MVT::v8i8);
+ if (CN1 == INT64_C(470)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PMAXUBrr, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 466:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 462:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (MMX_PCMPEQBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(466)) {
- SDNode *Result = Emit_111(N, X86::MMX_PCMPEQBrr, MVT::v8i8);
+ if (CN1 == INT64_C(462)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PCMPEQBrr, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 469:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 465:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (MMX_PCMPGTBrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(469)) {
- SDNode *Result = Emit_111(N, X86::MMX_PCMPGTBrr, MVT::v8i8);
+ if (CN1 == INT64_C(465)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PCMPGTBrr, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 458:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 454:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PACKSSWBrr:v8i8 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(458)) {
- SDNode *Result = Emit_111(N, X86::MMX_PACKSSWBrr, MVT::v8i8);
+ if (CN1 == INT64_C(454)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PACKSSWBrr, MVT::v8i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i8 459:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i8 455:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PACKUSWBrr:v8i8 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(459)) {
- SDNode *Result = Emit_111(N, X86::MMX_PACKUSWBrr, MVT::v8i8);
+ if (CN1 == INT64_C(455)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PACKUSWBrr, MVT::v8i8);
return Result;
}
}
@@ -14347,184 +14371,184 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_119(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_118(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N2, Tmp4);
-}
-DISABLE_INLINE SDNode *Emit_120(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN201_0, SDValue &CPTmpN201_1, SDValue &CPTmpN201_2, SDValue &CPTmpN201_3, SDValue &CPTmpN201_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N20 = N2.getOperand(0);
- SDValue Chain20 = N20.getOperand(0);
- SDValue N201 = N20.getOperand(1);
- SDValue N3 = N.getOperand(3);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N2, Tmp4);
+}
+DISABLE_INLINE SDNode *Emit_119(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN201_0, SDValue &CPTmpN201_1, SDValue &CPTmpN201_2, SDValue &CPTmpN201_3, SDValue &CPTmpN201_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue N3 = N->getOperand(3);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N20)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N20.getNode())->getMemOperand();
SDValue Ops0[] = { N1, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4, Tmp4, Chain20 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N20.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_121(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_120(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue Chain = CurDAG->getEntryNode();
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::XMM0, N3, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::XMM0, N3, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N2, InFlag);
-}
-DISABLE_INLINE SDNode *Emit_122(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN201_0, SDValue &CPTmpN201_1, SDValue &CPTmpN201_2, SDValue &CPTmpN201_3, SDValue &CPTmpN201_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N20 = N2.getOperand(0);
- SDValue Chain20 = N20.getOperand(0);
- SDValue N201 = N20.getOperand(1);
- SDValue N3 = N.getOperand(3);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N2, InFlag);
+}
+DISABLE_INLINE SDNode *Emit_121(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN201_0, SDValue &CPTmpN201_1, SDValue &CPTmpN201_2, SDValue &CPTmpN201_3, SDValue &CPTmpN201_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N20 = N2.getNode()->getOperand(0);
+ SDValue Chain20 = N20.getNode()->getOperand(0);
+ SDValue N201 = N20.getNode()->getOperand(1);
+ SDValue N3 = N->getOperand(3);
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain20, N.getDebugLoc(), X86::XMM0, N3, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain20, N->getDebugLoc(), X86::XMM0, N3, InFlag).getNode();
Chain20 = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N20)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N20.getNode())->getMemOperand();
SDValue Ops0[] = { N1, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4, Chain20, InFlag };
- ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N20.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_123(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_122(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i8);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N2, Tmp4);
-}
-DISABLE_INLINE SDNode *Emit_124(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue Chain2 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- SDValue N3 = N.getOperand(3);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N2, Tmp4);
+}
+DISABLE_INLINE SDNode *Emit_123(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue N3 = N->getOperand(3);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i8);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N2)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N2.getNode())->getMemOperand();
SDValue Ops0[] = { N1, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4, Tmp4, Chain2 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N2.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_125(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
+DISABLE_INLINE SDNode *Emit_124(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N5)->getZExtValue()), MVT::i8);
SDValue Chain = CurDAG->getEntryNode();
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EAX, N2, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EAX, N2, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EDX, N4, InFlag).getNode();
+ ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EDX, N4, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
SDValue Ops0[] = { N1, N3, Tmp4, InFlag };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
-}
-DISABLE_INLINE SDNode *Emit_126(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN31_0, SDValue &CPTmpN31_1, SDValue &CPTmpN31_2, SDValue &CPTmpN31_3, SDValue &CPTmpN31_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue Chain3 = N3.getOperand(0);
- SDValue N31 = N3.getOperand(1);
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
+}
+DISABLE_INLINE SDNode *Emit_125(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN31_0, SDValue &CPTmpN31_1, SDValue &CPTmpN31_2, SDValue &CPTmpN31_3, SDValue &CPTmpN31_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue Chain3 = N3.getNode()->getOperand(0);
+ SDValue N31 = N3.getNode()->getOperand(1);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N5)->getZExtValue()), MVT::i8);
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain3, N.getDebugLoc(), X86::EAX, N2, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain3, N->getDebugLoc(), X86::EAX, N2, InFlag).getNode();
Chain3 = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- ResNode = CurDAG->getCopyToReg(Chain3, N.getDebugLoc(), X86::EDX, N4, InFlag).getNode();
+ ResNode = CurDAG->getCopyToReg(Chain3, N->getDebugLoc(), X86::EDX, N4, InFlag).getNode();
Chain3 = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N3)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N3.getNode())->getMemOperand();
SDValue Ops0[] = { N1, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4, Tmp4, Chain3, InFlag };
- ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 9);
+ ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 9);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N3.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_127(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_126(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { N2, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp4, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(622)) {
- SDValue N1 = N.getOperand(1);
+ if (CN1 == INT64_C(618)) {
+ SDValue N1 = N->getOperand(1);
- // Pattern: (intrinsic_wo_chain:v16i8 622:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v16i8 618:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
// Emits: (MPSADBWrmi:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i32):$src3)
// Pattern complexity = 36 cost = 1 size = 3
{
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
SDValue CPTmpN201_3;
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant &&
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_120(N, X86::MPSADBWrmi, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_119(N, X86::MPSADBWrmi, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14533,31 +14557,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 622:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v16i8 618:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1, (imm:i32):$src3)
// Emits: (MPSADBWrmi:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i32):$src3)
// Pattern complexity = 36 cost = 1 size = 3
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant &&
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_127(N, X86::MPSADBWrmi, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_126(N, X86::MPSADBWrmi, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -14568,28 +14592,28 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 546:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v16i8 542:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PADDSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(546)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(542)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -14597,7 +14621,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PADDSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PADDSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14605,23 +14629,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 548:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v16i8 544:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PADDUSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(548)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(544)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -14629,7 +14653,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PADDUSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PADDUSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14637,23 +14661,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 588:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v16i8 584:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PSUBSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(588)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(584)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -14661,7 +14685,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PSUBSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSUBSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14669,23 +14693,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 590:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v16i8 586:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PSUBUSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(590)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(586)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -14693,7 +14717,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PSUBUSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSUBUSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14701,23 +14725,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 550:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v16i8 546:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PAVGBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(550)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(546)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -14725,7 +14749,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PAVGBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PAVGBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14733,23 +14757,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 562:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v16i8 558:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PMINUBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(562)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(558)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -14757,7 +14781,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMINUBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMINUBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14765,23 +14789,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 560:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v16i8 556:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PMAXUBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(560)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(556)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -14789,7 +14813,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMAXUBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMAXUBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14797,23 +14821,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 552:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v16i8 548:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PCMPEQBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(552)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(548)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -14821,7 +14845,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PCMPEQBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PCMPEQBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14829,23 +14853,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 555:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v16i8 551:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PCMPGTBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(555)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(551)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -14853,7 +14877,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PCMPGTBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PCMPGTBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14861,23 +14885,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 544:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v16i8 540:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PACKSSWBrm:v16i8 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(544)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(540)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -14885,7 +14909,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PACKSSWBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PACKSSWBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14893,23 +14917,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 545:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v16i8 541:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PACKUSWBrm:v16i8 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(545)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(541)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -14917,7 +14941,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PACKUSWBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PACKUSWBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14927,27 +14951,27 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 727:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v16i8 723:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PABSBrm128:v16i8 addr:iPTR:$src)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(727)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(723)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -14955,7 +14979,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_116(N, X86::PABSBrm128, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_115(N, X86::PABSBrm128, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -14963,23 +14987,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 751:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v16i8 747:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PSHUFBrm128:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(751)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(747)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -14987,7 +15011,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PSHUFBrm128, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSHUFBrm128, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -14995,23 +15019,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 753:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v16i8 749:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PSIGNBrm128:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(753)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(749)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -15019,7 +15043,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PSIGNBrm128, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSIGNBrm128, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15029,28 +15053,28 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 635:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v16i8 631:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PMINSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(635)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(631)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -15058,7 +15082,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMINSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMINSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15066,23 +15090,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 631:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v16i8 627:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PMAXSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(631)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(627)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -15090,7 +15114,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMAXSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMAXSBrm, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15098,32 +15122,32 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 624:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), XMM0:v16i8)
+ // Pattern: (intrinsic_wo_chain:v16i8 620:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), XMM0:v16i8)
// Emits: (PBLENDVBrm0:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(624)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(620)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
SDValue CPTmpN201_3;
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N.getOperand(3);
+ SDValue N3 = N->getOperand(3);
if (N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_122(N, X86::PBLENDVBrm0, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_121(N, X86::PBLENDVBrm0, MVT::v16i8, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15134,36 +15158,36 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 546:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Pattern: (intrinsic_wo_chain:v16i8 542:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
// Emits: (PADDSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(546)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(542)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_118(N, X86::PADDSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PADDSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -15172,31 +15196,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 548:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Pattern: (intrinsic_wo_chain:v16i8 544:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
// Emits: (PADDUSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(548)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(544)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_118(N, X86::PADDUSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PADDUSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -15205,31 +15229,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 550:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Pattern: (intrinsic_wo_chain:v16i8 546:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
// Emits: (PAVGBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(550)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(546)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_118(N, X86::PAVGBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PAVGBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -15238,31 +15262,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 562:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Pattern: (intrinsic_wo_chain:v16i8 558:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
// Emits: (PMINUBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(562)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(558)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_118(N, X86::PMINUBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PMINUBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -15271,31 +15295,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 560:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Pattern: (intrinsic_wo_chain:v16i8 556:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
// Emits: (PMAXUBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(560)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(556)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_118(N, X86::PMAXUBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PMAXUBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -15306,36 +15330,36 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 635:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Pattern: (intrinsic_wo_chain:v16i8 631:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
// Emits: (PMINSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(635)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(631)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_118(N, X86::PMINSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PMINSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -15344,31 +15368,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 631:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Pattern: (intrinsic_wo_chain:v16i8 627:iPTR, (bitconvert:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
// Emits: (PMAXSBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(631)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(627)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_118(N, X86::PMAXSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PMAXSBrm, MVT::v16i8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -15379,33 +15403,33 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
if ((Subtarget->hasSSE42())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 678:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:v16i8 674:iPTR, VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src3)
// Emits: (PCMPISTRM128MEM:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$src3)
// Pattern complexity = 33 cost = 11 size = 3
- if (CN1 == INT64_C(678)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(674)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_124(N, X86::PCMPISTRM128MEM, MVT::v16i8, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_123(N, X86::PCMPISTRM128MEM, MVT::v16i8, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -15413,30 +15437,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 670:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:v16i8 666:iPTR, VR128:v16i8:$src1, EAX:i32, (ld:v16i8 addr:iPTR:$src3)<<P:Predicate_unindexedload>><<P:Predicate_load>>, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRM128MEM:v16i8 VR128:v16i8:$src1, addr:iPTR:$src3, (imm:i8):$src5)
// Pattern complexity = 33 cost = 11 size = 3
- if (CN1 == INT64_C(670)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(666)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::LOAD &&
N3.hasOneUse() &&
- IsLegalAndProfitableToFold(N3.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain3 = N3.getOperand(0);
+ IsLegalAndProfitableToFold(N3.getNode(), N, N)) {
+ SDValue Chain3 = N3.getNode()->getOperand(0);
if (Predicate_unindexedload(N3.getNode()) &&
Predicate_load(N3.getNode())) {
- SDValue N31 = N3.getOperand(1);
+ SDValue N31 = N3.getNode()->getOperand(1);
SDValue CPTmpN31_0;
SDValue CPTmpN31_1;
SDValue CPTmpN31_2;
SDValue CPTmpN31_3;
SDValue CPTmpN31_4;
if (SelectAddr(N, N31, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4)) {
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
- if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_126(N, X86::PCMPESTRM128MEM, MVT::v16i8, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_125(N, X86::PCMPESTRM128MEM, MVT::v16i8, CPTmpN31_0, CPTmpN31_1, CPTmpN31_2, CPTmpN31_3, CPTmpN31_4);
return Result;
}
}
@@ -15447,213 +15471,213 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 622:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v16i8 618:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i32):$src3)
// Emits: (MPSADBWrri:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i32):$src3)
// Pattern complexity = 11 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(622)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_119(N, X86::MPSADBWrri, MVT::v16i8);
+ if (CN1 == INT64_C(618)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_118(N, X86::MPSADBWrri, MVT::v16i8);
return Result;
}
}
}
}
if ((Subtarget->hasSSE42())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 678:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:v16i8 674:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Emits: (PCMPISTRM128REG:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$src3)
// Pattern complexity = 11 cost = 11 size = 3
- if (CN1 == INT64_C(678)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_123(N, X86::PCMPISTRM128REG, MVT::v16i8);
+ if (CN1 == INT64_C(674)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_122(N, X86::PCMPISTRM128REG, MVT::v16i8);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v16i8 670:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
+ // Pattern: (intrinsic_wo_chain:v16i8 666:iPTR, VR128:v16i8:$src1, EAX:i32, VR128:v16i8:$src3, EDX:i32, (imm:i8):$src5)
// Emits: (PCMPESTRM128REG:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src3, (imm:i8):$src5)
// Pattern complexity = 11 cost = 11 size = 3
- if (CN1 == INT64_C(670)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
- if (N5.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_125(N, X86::PCMPESTRM128REG, MVT::v16i8);
+ if (CN1 == INT64_C(666)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ if (N5.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_124(N, X86::PCMPESTRM128REG, MVT::v16i8);
return Result;
}
}
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 546:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 542:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PADDSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(546)) {
- SDNode *Result = Emit_111(N, X86::PADDSBrr, MVT::v16i8);
+ if (CN1 == INT64_C(542)) {
+ SDNode *Result = Emit_110(N, X86::PADDSBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 548:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 544:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PADDUSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(548)) {
- SDNode *Result = Emit_111(N, X86::PADDUSBrr, MVT::v16i8);
+ if (CN1 == INT64_C(544)) {
+ SDNode *Result = Emit_110(N, X86::PADDUSBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 588:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 584:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PSUBSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(588)) {
- SDNode *Result = Emit_111(N, X86::PSUBSBrr, MVT::v16i8);
+ if (CN1 == INT64_C(584)) {
+ SDNode *Result = Emit_110(N, X86::PSUBSBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 590:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 586:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PSUBUSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(590)) {
- SDNode *Result = Emit_111(N, X86::PSUBUSBrr, MVT::v16i8);
+ if (CN1 == INT64_C(586)) {
+ SDNode *Result = Emit_110(N, X86::PSUBUSBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 550:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 546:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PAVGBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(550)) {
- SDNode *Result = Emit_111(N, X86::PAVGBrr, MVT::v16i8);
+ if (CN1 == INT64_C(546)) {
+ SDNode *Result = Emit_110(N, X86::PAVGBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 562:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 558:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PMINUBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(562)) {
- SDNode *Result = Emit_111(N, X86::PMINUBrr, MVT::v16i8);
+ if (CN1 == INT64_C(558)) {
+ SDNode *Result = Emit_110(N, X86::PMINUBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 560:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 556:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PMAXUBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(560)) {
- SDNode *Result = Emit_111(N, X86::PMAXUBrr, MVT::v16i8);
+ if (CN1 == INT64_C(556)) {
+ SDNode *Result = Emit_110(N, X86::PMAXUBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 552:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 548:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PCMPEQBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(552)) {
- SDNode *Result = Emit_111(N, X86::PCMPEQBrr, MVT::v16i8);
+ if (CN1 == INT64_C(548)) {
+ SDNode *Result = Emit_110(N, X86::PCMPEQBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 555:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 551:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PCMPGTBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(555)) {
- SDNode *Result = Emit_111(N, X86::PCMPGTBrr, MVT::v16i8);
+ if (CN1 == INT64_C(551)) {
+ SDNode *Result = Emit_110(N, X86::PCMPGTBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 544:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 540:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PACKSSWBrr:v16i8 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(544)) {
- SDNode *Result = Emit_111(N, X86::PACKSSWBrr, MVT::v16i8);
+ if (CN1 == INT64_C(540)) {
+ SDNode *Result = Emit_110(N, X86::PACKSSWBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 545:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 541:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PACKUSWBrr:v16i8 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(545)) {
- SDNode *Result = Emit_111(N, X86::PACKUSWBrr, MVT::v16i8);
+ if (CN1 == INT64_C(541)) {
+ SDNode *Result = Emit_110(N, X86::PACKUSWBrr, MVT::v16i8);
return Result;
}
}
}
if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 727:iPTR, VR128:v16i8:$src)
+ // Pattern: (intrinsic_wo_chain:v16i8 723:iPTR, VR128:v16i8:$src)
// Emits: (PABSBrr128:v16i8 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(727)) {
- SDNode *Result = Emit_108(N, X86::PABSBrr128, MVT::v16i8);
+ if (CN1 == INT64_C(723)) {
+ SDNode *Result = Emit_107(N, X86::PABSBrr128, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 751:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 747:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PSHUFBrr128:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(751)) {
- SDNode *Result = Emit_111(N, X86::PSHUFBrr128, MVT::v16i8);
+ if (CN1 == INT64_C(747)) {
+ SDNode *Result = Emit_110(N, X86::PSHUFBrr128, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 753:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 749:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PSIGNBrr128:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(753)) {
- SDNode *Result = Emit_111(N, X86::PSIGNBrr128, MVT::v16i8);
+ if (CN1 == INT64_C(749)) {
+ SDNode *Result = Emit_110(N, X86::PSIGNBrr128, MVT::v16i8);
return Result;
}
}
}
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v16i8 635:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 631:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PMINSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(635)) {
- SDNode *Result = Emit_111(N, X86::PMINSBrr, MVT::v16i8);
+ if (CN1 == INT64_C(631)) {
+ SDNode *Result = Emit_110(N, X86::PMINSBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 631:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v16i8 627:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PMAXSBrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(631)) {
- SDNode *Result = Emit_111(N, X86::PMAXSBrr, MVT::v16i8);
+ if (CN1 == INT64_C(627)) {
+ SDNode *Result = Emit_110(N, X86::PMAXSBrr, MVT::v16i8);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v16i8 624:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, XMM0:v16i8)
+ // Pattern: (intrinsic_wo_chain:v16i8 620:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2, XMM0:v16i8)
// Emits: (PBLENDVBrr0:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(624)) {
- SDNode *Result = Emit_121(N, X86::PBLENDVBrr0, MVT::v16i8);
+ if (CN1 == INT64_C(620)) {
+ SDNode *Result = Emit_120(N, X86::PBLENDVBrr0, MVT::v16i8);
return Result;
}
}
@@ -15663,37 +15687,37 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v16i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_128(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_127(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, Tmp3);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, Tmp3);
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i16 730:iPTR, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 726:iPTR, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PABSWrm64:v4i16 addr:iPTR:$src)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(730)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(726)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -15701,7 +15725,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_116(N, X86::PABSWrm64, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_115(N, X86::PABSWrm64, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -15709,23 +15733,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 738:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 734:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PHADDWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(738)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(734)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -15733,7 +15757,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_117(N, X86::PHADDWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PHADDWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15741,23 +15765,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 736:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 732:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PHADDSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(736)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(732)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -15765,7 +15789,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_117(N, X86::PHADDSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PHADDSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15773,23 +15797,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 744:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 740:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PHSUBWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(744)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(740)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -15797,7 +15821,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_117(N, X86::PHSUBWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PHSUBWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15805,23 +15829,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 742:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 738:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PHSUBSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(742)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(738)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -15829,7 +15853,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_117(N, X86::PHSUBSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PHSUBSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15837,23 +15861,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 746:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v8i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 742:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v8i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PMADDUBSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(746)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(742)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -15861,7 +15885,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_117(N, X86::PMADDUBSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMADDUBSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15869,23 +15893,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 748:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 744:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PMULHRSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(748)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(744)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -15893,7 +15917,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_117(N, X86::PMULHRSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMULHRSWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15901,23 +15925,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 756:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 752:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PSIGNWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(756)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(752)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -15925,7 +15949,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_117(N, X86::PSIGNWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSIGNWrm64, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15935,27 +15959,27 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
if ((Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i16 461:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 457:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PADDSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(461)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(457)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -15963,7 +15987,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PADDSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PADDSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -15971,22 +15995,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 463:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 459:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PADDUSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(463)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(459)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -15994,7 +16018,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PADDUSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PADDUSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16002,22 +16026,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 499:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 495:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PSUBSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(499)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(495)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -16025,7 +16049,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PSUBSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PSUBSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16033,22 +16057,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 501:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 497:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PSUBUSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(501)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(497)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -16056,7 +16080,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PSUBUSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PSUBUSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16064,22 +16088,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 478:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 474:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PMULHWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(478)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(474)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -16087,7 +16111,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMULHWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PMULHWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16095,22 +16119,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 479:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 475:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PMULHUWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(479)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(475)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -16118,7 +16142,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMULHUWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PMULHUWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16126,22 +16150,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 465:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 461:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PAVGWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(465)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(461)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -16149,7 +16173,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PAVGWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PAVGWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16157,22 +16181,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 475:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 471:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PMINSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(475)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(471)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -16180,7 +16204,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMINSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PMINSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16188,22 +16212,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 473:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 469:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PMAXSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(473)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(469)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -16211,7 +16235,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMAXSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PMAXSWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16219,22 +16243,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 481:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 477:iPTR, VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PSADBWrm:v4i16 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(481)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(477)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -16242,7 +16266,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PSADBWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PSADBWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16250,22 +16274,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 494:iPTR, VR64:v4i16:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 490:iPTR, VR64:v4i16:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PSRLWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(494)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(490)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -16273,7 +16297,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PSRLWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PSRLWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16281,22 +16305,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 484:iPTR, VR64:v4i16:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 480:iPTR, VR64:v4i16:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PSLLWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(484)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(480)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -16304,7 +16328,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PSLLWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PSLLWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16312,22 +16336,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 489:iPTR, VR64:v4i16:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 485:iPTR, VR64:v4i16:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PSRAWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(489)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(485)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -16335,7 +16359,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PSRAWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PSRAWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16343,22 +16367,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 468:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 464:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PCMPEQWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(468)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(464)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -16366,7 +16390,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PCMPEQWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PCMPEQWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16374,22 +16398,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 471:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 467:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PCMPGTWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(471)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(467)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -16397,7 +16421,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PCMPGTWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PCMPGTWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16405,22 +16429,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 457:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v4i16 453:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PACKSSDWrm:v4i16 VR64:v2i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(457)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(453)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -16428,7 +16452,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PACKSSDWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PACKSSDWrm, MVT::v4i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -16438,36 +16462,36 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 748:iPTR, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>), VR64:v4i16:$src1)
+ // Pattern: (intrinsic_wo_chain:v4i16 744:iPTR, (bitconvert:v4i16 (ld:v4i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>), VR64:v4i16:$src1)
// Emits: (PMULHRSWrm64:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(748)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(744)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_118(N, X86::PMULHRSWrm64, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PMULHRSWrm64, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -16478,35 +16502,35 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
if ((Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i16 461:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Pattern: (intrinsic_wo_chain:v4i16 457:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
// Emits: (MMX_PADDSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(461)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(457)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_118(N, X86::MMX_PADDSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PADDSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -16515,30 +16539,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 463:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Pattern: (intrinsic_wo_chain:v4i16 459:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
// Emits: (MMX_PADDUSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(463)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(459)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_118(N, X86::MMX_PADDUSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PADDUSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -16547,30 +16571,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 478:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Pattern: (intrinsic_wo_chain:v4i16 474:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
// Emits: (MMX_PMULHWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(478)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(474)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_118(N, X86::MMX_PMULHWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PMULHWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -16579,30 +16603,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 479:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Pattern: (intrinsic_wo_chain:v4i16 475:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
// Emits: (MMX_PMULHUWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(479)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(475)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_118(N, X86::MMX_PMULHUWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PMULHUWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -16611,30 +16635,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 465:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Pattern: (intrinsic_wo_chain:v4i16 461:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
// Emits: (MMX_PAVGWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(465)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(461)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_118(N, X86::MMX_PAVGWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PAVGWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -16643,30 +16667,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 475:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Pattern: (intrinsic_wo_chain:v4i16 471:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
// Emits: (MMX_PMINSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(475)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(471)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_118(N, X86::MMX_PMINSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PMINSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -16675,30 +16699,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 473:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Pattern: (intrinsic_wo_chain:v4i16 469:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
// Emits: (MMX_PMAXSWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(473)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(469)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_118(N, X86::MMX_PMAXSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PMAXSWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -16707,30 +16731,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 481:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
+ // Pattern: (intrinsic_wo_chain:v4i16 477:iPTR, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
// Emits: (MMX_PSADBWrm:v4i16 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(481)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(477)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_118(N, X86::MMX_PSADBWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PSADBWrm, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -16742,250 +16766,250 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
}
}
if ((Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i16 497:iPTR, VR64:v4i16:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 493:iPTR, VR64:v4i16:$src1, (imm:i32):$src2)
// Emits: (MMX_PSRLWri:v4i16 VR64:v4i16:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(497)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, X86::MMX_PSRLWri, MVT::v4i16);
+ if (CN1 == INT64_C(493)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_127(N, X86::MMX_PSRLWri, MVT::v4i16);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 487:iPTR, VR64:v4i16:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 483:iPTR, VR64:v4i16:$src1, (imm:i32):$src2)
// Emits: (MMX_PSLLWri:v4i16 VR64:v4i16:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(487)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, X86::MMX_PSLLWri, MVT::v4i16);
+ if (CN1 == INT64_C(483)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_127(N, X86::MMX_PSLLWri, MVT::v4i16);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4i16 491:iPTR, VR64:v4i16:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 487:iPTR, VR64:v4i16:$src1, (imm:i32):$src2)
// Emits: (MMX_PSRAWri:v4i16 VR64:v4i16:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(491)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, X86::MMX_PSRAWri, MVT::v4i16);
+ if (CN1 == INT64_C(487)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_127(N, X86::MMX_PSRAWri, MVT::v4i16);
return Result;
}
}
}
}
if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i16 730:iPTR, VR64:v4i16:$src)
+ // Pattern: (intrinsic_wo_chain:v4i16 726:iPTR, VR64:v4i16:$src)
// Emits: (PABSWrr64:v4i16 VR64:v4i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(730)) {
- SDNode *Result = Emit_108(N, X86::PABSWrr64, MVT::v4i16);
+ if (CN1 == INT64_C(726)) {
+ SDNode *Result = Emit_107(N, X86::PABSWrr64, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 738:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 734:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (PHADDWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(738)) {
- SDNode *Result = Emit_111(N, X86::PHADDWrr64, MVT::v4i16);
+ if (CN1 == INT64_C(734)) {
+ SDNode *Result = Emit_110(N, X86::PHADDWrr64, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 736:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 732:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (PHADDSWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(736)) {
- SDNode *Result = Emit_111(N, X86::PHADDSWrr64, MVT::v4i16);
+ if (CN1 == INT64_C(732)) {
+ SDNode *Result = Emit_110(N, X86::PHADDSWrr64, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 744:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 740:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (PHSUBWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(744)) {
- SDNode *Result = Emit_111(N, X86::PHSUBWrr64, MVT::v4i16);
+ if (CN1 == INT64_C(740)) {
+ SDNode *Result = Emit_110(N, X86::PHSUBWrr64, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 742:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 738:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (PHSUBSWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(742)) {
- SDNode *Result = Emit_111(N, X86::PHSUBSWrr64, MVT::v4i16);
+ if (CN1 == INT64_C(738)) {
+ SDNode *Result = Emit_110(N, X86::PHSUBSWrr64, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 746:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 742:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (PMADDUBSWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(746)) {
- SDNode *Result = Emit_111(N, X86::PMADDUBSWrr64, MVT::v4i16);
+ if (CN1 == INT64_C(742)) {
+ SDNode *Result = Emit_110(N, X86::PMADDUBSWrr64, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 748:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 744:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (PMULHRSWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(748)) {
- SDNode *Result = Emit_111(N, X86::PMULHRSWrr64, MVT::v4i16);
+ if (CN1 == INT64_C(744)) {
+ SDNode *Result = Emit_110(N, X86::PMULHRSWrr64, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 756:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 752:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (PSIGNWrr64:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(756)) {
- SDNode *Result = Emit_111(N, X86::PSIGNWrr64, MVT::v4i16);
+ if (CN1 == INT64_C(752)) {
+ SDNode *Result = Emit_110(N, X86::PSIGNWrr64, MVT::v4i16);
return Result;
}
}
}
if ((Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i16 461:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 457:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PADDSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(461)) {
- SDNode *Result = Emit_111(N, X86::MMX_PADDSWrr, MVT::v4i16);
+ if (CN1 == INT64_C(457)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PADDSWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 463:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 459:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PADDUSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(463)) {
- SDNode *Result = Emit_111(N, X86::MMX_PADDUSWrr, MVT::v4i16);
+ if (CN1 == INT64_C(459)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PADDUSWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 499:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 495:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PSUBSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(499)) {
- SDNode *Result = Emit_111(N, X86::MMX_PSUBSWrr, MVT::v4i16);
+ if (CN1 == INT64_C(495)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PSUBSWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 501:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 497:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PSUBUSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(501)) {
- SDNode *Result = Emit_111(N, X86::MMX_PSUBUSWrr, MVT::v4i16);
+ if (CN1 == INT64_C(497)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PSUBUSWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 478:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 474:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PMULHWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(478)) {
- SDNode *Result = Emit_111(N, X86::MMX_PMULHWrr, MVT::v4i16);
+ if (CN1 == INT64_C(474)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PMULHWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 479:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 475:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PMULHUWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(479)) {
- SDNode *Result = Emit_111(N, X86::MMX_PMULHUWrr, MVT::v4i16);
+ if (CN1 == INT64_C(475)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PMULHUWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 465:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 461:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PAVGWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(465)) {
- SDNode *Result = Emit_111(N, X86::MMX_PAVGWrr, MVT::v4i16);
+ if (CN1 == INT64_C(461)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PAVGWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 475:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 471:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PMINSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(475)) {
- SDNode *Result = Emit_111(N, X86::MMX_PMINSWrr, MVT::v4i16);
+ if (CN1 == INT64_C(471)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PMINSWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 473:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 469:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PMAXSWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(473)) {
- SDNode *Result = Emit_111(N, X86::MMX_PMAXSWrr, MVT::v4i16);
+ if (CN1 == INT64_C(469)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PMAXSWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 481:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 477:iPTR, VR64:v8i8:$src1, VR64:v8i8:$src2)
// Emits: (MMX_PSADBWrr:v4i16 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(481)) {
- SDNode *Result = Emit_111(N, X86::MMX_PSADBWrr, MVT::v4i16);
+ if (CN1 == INT64_C(477)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PSADBWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 494:iPTR, VR64:v4i16:$src1, VR64:v1i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 490:iPTR, VR64:v4i16:$src1, VR64:v1i64:$src2)
// Emits: (MMX_PSRLWrr:v4i16 VR64:v4i16:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(494)) {
- SDNode *Result = Emit_111(N, X86::MMX_PSRLWrr, MVT::v4i16);
+ if (CN1 == INT64_C(490)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PSRLWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 484:iPTR, VR64:v4i16:$src1, VR64:v1i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 480:iPTR, VR64:v4i16:$src1, VR64:v1i64:$src2)
// Emits: (MMX_PSLLWrr:v4i16 VR64:v4i16:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(484)) {
- SDNode *Result = Emit_111(N, X86::MMX_PSLLWrr, MVT::v4i16);
+ if (CN1 == INT64_C(480)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PSLLWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 489:iPTR, VR64:v4i16:$src1, VR64:v1i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 485:iPTR, VR64:v4i16:$src1, VR64:v1i64:$src2)
// Emits: (MMX_PSRAWrr:v4i16 VR64:v4i16:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(489)) {
- SDNode *Result = Emit_111(N, X86::MMX_PSRAWrr, MVT::v4i16);
+ if (CN1 == INT64_C(485)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PSRAWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 468:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 464:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PCMPEQWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(468)) {
- SDNode *Result = Emit_111(N, X86::MMX_PCMPEQWrr, MVT::v4i16);
+ if (CN1 == INT64_C(464)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PCMPEQWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 471:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 467:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PCMPGTWrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(471)) {
- SDNode *Result = Emit_111(N, X86::MMX_PCMPGTWrr, MVT::v4i16);
+ if (CN1 == INT64_C(467)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PCMPGTWrr, MVT::v4i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i16 457:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i16 453:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
// Emits: (MMX_PACKSSDWrr:v4i16 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(457)) {
- SDNode *Result = Emit_111(N, X86::MMX_PACKSSDWrr, MVT::v4i16);
+ if (CN1 == INT64_C(453)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PACKSSDWrr, MVT::v4i16);
return Result;
}
}
@@ -16995,78 +17019,78 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i16(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_129(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue Chain100 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
+DISABLE_INLINE SDNode *Emit_128(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N100)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N100.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, Chain100 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N100.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_130(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN10001_0, SDValue &CPTmpN10001_1, SDValue &CPTmpN10001_2, SDValue &CPTmpN10001_3, SDValue &CPTmpN10001_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N1000 = N100.getOperand(0);
- SDValue Chain1000 = N1000.getOperand(0);
- SDValue N10001 = N1000.getOperand(1);
+DISABLE_INLINE SDNode *Emit_129(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN10001_0, SDValue &CPTmpN10001_1, SDValue &CPTmpN10001_2, SDValue &CPTmpN10001_3, SDValue &CPTmpN10001_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1000)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1000.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4, Chain1000 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1000.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_131(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
+DISABLE_INLINE SDNode *Emit_130(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 641:iPTR, (bitconvert:v16i8 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
+ // Pattern: (intrinsic_wo_chain:v8i16 637:iPTR, (bitconvert:v16i8 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
// Emits: (PMOVSXBWrm:v8i16 addr:iPTR:$src)
// Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(641)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(637)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N100.hasOneUse()) {
- SDValue N1000 = N100.getOperand(0);
- if (N1000.getOpcode() == ISD::LOAD &&
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
- SDValue Chain1000 = N1000.getOperand(0);
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
if (Predicate_unindexedload(N1000.getNode()) &&
Predicate_load(N1000.getNode()) &&
Predicate_loadi64(N1000.getNode())) {
- SDValue N10001 = N1000.getOperand(1);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
SDValue CPTmpN10001_0;
SDValue CPTmpN10001_1;
SDValue CPTmpN10001_2;
@@ -17075,7 +17099,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v2i64 &&
N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_130(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -17085,28 +17109,28 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 647:iPTR, (bitconvert:v16i8 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
+ // Pattern: (intrinsic_wo_chain:v8i16 643:iPTR, (bitconvert:v16i8 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
// Emits: (PMOVZXBWrm:v8i16 addr:iPTR:$src)
// Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(647)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(643)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N100.hasOneUse()) {
- SDValue N1000 = N100.getOperand(0);
- if (N1000.getOpcode() == ISD::LOAD &&
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
- SDValue Chain1000 = N1000.getOperand(0);
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
if (Predicate_unindexedload(N1000.getNode()) &&
Predicate_load(N1000.getNode()) &&
Predicate_loadi64(N1000.getNode())) {
- SDValue N10001 = N1000.getOperand(1);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
SDValue CPTmpN10001_0;
SDValue CPTmpN10001_1;
SDValue CPTmpN10001_2;
@@ -17115,7 +17139,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v2i64 &&
N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_130(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -17125,33 +17149,33 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 625:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v8i16 621:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
// Emits: (PBLENDWrmi:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2, (imm:i32):$src3)
// Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(625)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(621)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
SDValue CPTmpN201_3;
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant &&
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_120(N, X86::PBLENDWrmi, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_119(N, X86::PBLENDWrmi, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17160,25 +17184,25 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 641:iPTR, (bitconvert:v16i8 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
+ // Pattern: (intrinsic_wo_chain:v8i16 637:iPTR, (bitconvert:v16i8 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
// Emits: (PMOVSXBWrm:v8i16 addr:iPTR:$src)
// Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(641)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(637)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
- SDValue Chain100 = N100.getOperand(0);
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_load(N100.getNode()) &&
Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
@@ -17187,7 +17211,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v2i64 &&
N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_129(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_128(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -17196,25 +17220,25 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 647:iPTR, (bitconvert:v16i8 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
+ // Pattern: (intrinsic_wo_chain:v8i16 643:iPTR, (bitconvert:v16i8 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
// Emits: (PMOVZXBWrm:v8i16 addr:iPTR:$src)
// Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(647)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(643)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
- SDValue Chain100 = N100.getOperand(0);
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_load(N100.getNode()) &&
Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
@@ -17223,7 +17247,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v2i64 &&
N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_129(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_128(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -17234,28 +17258,28 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 547:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 543:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PADDSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(547)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(543)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17263,7 +17287,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PADDSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PADDSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17271,23 +17295,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 549:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 545:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PADDUSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(549)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(545)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17295,7 +17319,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PADDUSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PADDUSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17303,23 +17327,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 589:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 585:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PSUBSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(589)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(585)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17327,7 +17351,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PSUBSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSUBSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17335,23 +17359,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 591:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 587:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PSUBUSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(591)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(587)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17359,7 +17383,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PSUBUSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSUBUSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17367,23 +17391,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 565:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 561:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PMULHUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(565)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(561)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17391,7 +17415,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMULHUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMULHUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17399,23 +17423,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 564:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 560:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PMULHWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(564)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(560)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17423,7 +17447,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMULHWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMULHWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17431,23 +17455,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 551:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 547:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PAVGWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(551)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(547)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17455,7 +17479,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PAVGWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PAVGWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17463,23 +17487,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 561:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 557:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PMINSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(561)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(557)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17487,7 +17511,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMINSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMINSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17495,23 +17519,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 559:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 555:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PMAXSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(559)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(555)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17519,7 +17543,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMAXSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMAXSWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17527,23 +17551,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 572:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 568:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PSLLWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(572)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(568)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17551,7 +17575,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PSLLWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSLLWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17559,23 +17583,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 584:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 580:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PSRLWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(584)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(580)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17583,7 +17607,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PSRLWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSRLWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17591,23 +17615,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 577:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 573:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PSRAWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(577)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(573)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17615,7 +17639,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PSRAWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSRAWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17623,23 +17647,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 554:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 550:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PCMPEQWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(554)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(550)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17647,7 +17671,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PCMPEQWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PCMPEQWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17655,23 +17679,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 557:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 553:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PCMPGTWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(557)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(553)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17679,7 +17703,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PCMPGTWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PCMPGTWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17687,23 +17711,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 543:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 539:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PACKSSDWrm:v8i16 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(543)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(539)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17711,7 +17735,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PACKSSDWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PACKSSDWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17721,27 +17745,27 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 731:iPTR, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 727:iPTR, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PABSWrm128:v8i16 addr:iPTR:$src)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(731)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(727)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -17749,7 +17773,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_116(N, X86::PABSWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_115(N, X86::PABSWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -17757,23 +17781,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 739:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 735:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PHADDWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(739)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(735)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17781,7 +17805,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_117(N, X86::PHADDWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PHADDWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17789,23 +17813,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 745:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 741:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PHSUBWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(745)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(741)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17813,7 +17837,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_117(N, X86::PHSUBWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PHSUBWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17821,23 +17845,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 743:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 739:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PHSUBSWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(743)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(739)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17845,7 +17869,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_117(N, X86::PHSUBSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PHSUBSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17853,23 +17877,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 747:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 743:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PMADDUBSWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(747)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(743)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17877,7 +17901,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMADDUBSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMADDUBSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17885,23 +17909,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 749:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 745:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PMULHRSWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(749)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(745)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17909,7 +17933,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_117(N, X86::PMULHRSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMULHRSWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17917,23 +17941,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 757:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 753:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PSIGNWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(757)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(753)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -17941,7 +17965,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_117(N, X86::PSIGNWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSIGNWrm128, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -17951,27 +17975,27 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 630:iPTR, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 626:iPTR, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PHMINPOSUWrm128:v8i16 addr:iPTR:$src)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(630)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(626)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -17979,7 +18003,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_116(N, X86::PHMINPOSUWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_115(N, X86::PHMINPOSUWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -17987,23 +18011,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 623:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 619:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PACKUSDWrm:v8i16 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(623)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(619)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -18011,7 +18035,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PACKUSDWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PACKUSDWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -18019,23 +18043,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 638:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 634:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PMINUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(638)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(634)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -18043,7 +18067,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMINUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMINUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -18051,23 +18075,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 634:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v8i16 630:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PMAXUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(634)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(630)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -18075,7 +18099,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMAXUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMAXUWrm, MVT::v8i16, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -18085,36 +18109,36 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 547:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Pattern: (intrinsic_wo_chain:v8i16 543:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
// Emits: (PADDSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(547)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(543)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_118(N, X86::PADDSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PADDSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18123,31 +18147,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 549:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Pattern: (intrinsic_wo_chain:v8i16 545:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
// Emits: (PADDUSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(549)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(545)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_118(N, X86::PADDUSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PADDUSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18156,31 +18180,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 565:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Pattern: (intrinsic_wo_chain:v8i16 561:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
// Emits: (PMULHUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(565)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(561)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_118(N, X86::PMULHUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PMULHUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18189,31 +18213,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 564:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Pattern: (intrinsic_wo_chain:v8i16 560:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
// Emits: (PMULHWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(564)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(560)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_118(N, X86::PMULHWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PMULHWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18222,31 +18246,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 551:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Pattern: (intrinsic_wo_chain:v8i16 547:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
// Emits: (PAVGWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(551)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(547)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_118(N, X86::PAVGWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PAVGWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18255,31 +18279,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 561:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Pattern: (intrinsic_wo_chain:v8i16 557:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
// Emits: (PMINSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(561)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(557)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_118(N, X86::PMINSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PMINSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18288,31 +18312,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 559:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Pattern: (intrinsic_wo_chain:v8i16 555:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
// Emits: (PMAXSWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(559)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(555)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_118(N, X86::PMAXSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PMAXSWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18323,36 +18347,36 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 749:iPTR, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>), VR128:v8i16:$src1)
+ // Pattern: (intrinsic_wo_chain:v8i16 745:iPTR, (bitconvert:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>), VR128:v8i16:$src1)
// Emits: (PMULHRSWrm128:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(749)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(745)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_118(N, X86::PMULHRSWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PMULHRSWrm128, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18363,36 +18387,36 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 638:iPTR, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Pattern: (intrinsic_wo_chain:v8i16 634:iPTR, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
// Emits: (PMINUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(638)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(634)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_118(N, X86::PMINUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PMINUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18401,31 +18425,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 634:iPTR, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Pattern: (intrinsic_wo_chain:v8i16 630:iPTR, (bitconvert:v8i16 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
// Emits: (PMAXUWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(634)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(630)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_118(N, X86::PMAXUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PMAXUWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18434,19 +18458,19 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 641:iPTR, (bitconvert:v16i8 (X86vzload:v2i64 addr:iPTR:$src)))
+ // Pattern: (intrinsic_wo_chain:v8i16 637:iPTR, (bitconvert:v16i8 (X86vzload:v2i64 addr:iPTR:$src)))
// Emits: (PMOVSXBWrm:v8i16 addr:iPTR:$src)
// Pattern complexity = 32 cost = 1 size = 3
- if (CN1 == INT64_C(641)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(637)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == X86ISD::VZEXT_LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -18454,26 +18478,26 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_131(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_130(N, X86::PMOVSXBWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 647:iPTR, (bitconvert:v16i8 (X86vzload:v2i64 addr:iPTR:$src)))
+ // Pattern: (intrinsic_wo_chain:v8i16 643:iPTR, (bitconvert:v16i8 (X86vzload:v2i64 addr:iPTR:$src)))
// Emits: (PMOVZXBWrm:v8i16 addr:iPTR:$src)
// Pattern complexity = 32 cost = 1 size = 3
- if (CN1 == INT64_C(647)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(643)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == X86ISD::VZEXT_LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -18481,7 +18505,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_131(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_130(N, X86::PMOVZXBWrm, MVT::v8i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18491,309 +18515,309 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 575:iPTR, VR128:v8i16:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 571:iPTR, VR128:v8i16:$src1, (imm:i32):$src2)
// Emits: (PSLLWri:v8i16 VR128:v8i16:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(575)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, X86::PSLLWri, MVT::v8i16);
+ if (CN1 == INT64_C(571)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_127(N, X86::PSLLWri, MVT::v8i16);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 587:iPTR, VR128:v8i16:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 583:iPTR, VR128:v8i16:$src1, (imm:i32):$src2)
// Emits: (PSRLWri:v8i16 VR128:v8i16:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(587)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, X86::PSRLWri, MVT::v8i16);
+ if (CN1 == INT64_C(583)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_127(N, X86::PSRLWri, MVT::v8i16);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 579:iPTR, VR128:v8i16:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 575:iPTR, VR128:v8i16:$src1, (imm:i32):$src2)
// Emits: (PSRAWri:v8i16 VR128:v8i16:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(579)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, X86::PSRAWri, MVT::v8i16);
+ if (CN1 == INT64_C(575)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_127(N, X86::PSRAWri, MVT::v8i16);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v8i16 625:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v8i16 621:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2, (imm:i32):$src3)
// Emits: (PBLENDWrri:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2, (imm:i32):$src3)
// Pattern complexity = 11 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(625)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_119(N, X86::PBLENDWrri, MVT::v8i16);
+ if (CN1 == INT64_C(621)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_118(N, X86::PBLENDWrri, MVT::v8i16);
return Result;
}
}
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 547:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 543:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PADDSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(547)) {
- SDNode *Result = Emit_111(N, X86::PADDSWrr, MVT::v8i16);
+ if (CN1 == INT64_C(543)) {
+ SDNode *Result = Emit_110(N, X86::PADDSWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 549:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 545:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PADDUSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(549)) {
- SDNode *Result = Emit_111(N, X86::PADDUSWrr, MVT::v8i16);
+ if (CN1 == INT64_C(545)) {
+ SDNode *Result = Emit_110(N, X86::PADDUSWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 589:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 585:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PSUBSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(589)) {
- SDNode *Result = Emit_111(N, X86::PSUBSWrr, MVT::v8i16);
+ if (CN1 == INT64_C(585)) {
+ SDNode *Result = Emit_110(N, X86::PSUBSWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 591:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 587:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PSUBUSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(591)) {
- SDNode *Result = Emit_111(N, X86::PSUBUSWrr, MVT::v8i16);
+ if (CN1 == INT64_C(587)) {
+ SDNode *Result = Emit_110(N, X86::PSUBUSWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 565:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 561:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PMULHUWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(565)) {
- SDNode *Result = Emit_111(N, X86::PMULHUWrr, MVT::v8i16);
+ if (CN1 == INT64_C(561)) {
+ SDNode *Result = Emit_110(N, X86::PMULHUWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 564:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 560:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PMULHWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(564)) {
- SDNode *Result = Emit_111(N, X86::PMULHWrr, MVT::v8i16);
+ if (CN1 == INT64_C(560)) {
+ SDNode *Result = Emit_110(N, X86::PMULHWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 551:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 547:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PAVGWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(551)) {
- SDNode *Result = Emit_111(N, X86::PAVGWrr, MVT::v8i16);
+ if (CN1 == INT64_C(547)) {
+ SDNode *Result = Emit_110(N, X86::PAVGWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 561:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 557:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PMINSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(561)) {
- SDNode *Result = Emit_111(N, X86::PMINSWrr, MVT::v8i16);
+ if (CN1 == INT64_C(557)) {
+ SDNode *Result = Emit_110(N, X86::PMINSWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 559:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 555:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PMAXSWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(559)) {
- SDNode *Result = Emit_111(N, X86::PMAXSWrr, MVT::v8i16);
+ if (CN1 == INT64_C(555)) {
+ SDNode *Result = Emit_110(N, X86::PMAXSWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 572:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 568:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PSLLWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(572)) {
- SDNode *Result = Emit_111(N, X86::PSLLWrr, MVT::v8i16);
+ if (CN1 == INT64_C(568)) {
+ SDNode *Result = Emit_110(N, X86::PSLLWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 584:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 580:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PSRLWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(584)) {
- SDNode *Result = Emit_111(N, X86::PSRLWrr, MVT::v8i16);
+ if (CN1 == INT64_C(580)) {
+ SDNode *Result = Emit_110(N, X86::PSRLWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 577:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 573:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PSRAWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(577)) {
- SDNode *Result = Emit_111(N, X86::PSRAWrr, MVT::v8i16);
+ if (CN1 == INT64_C(573)) {
+ SDNode *Result = Emit_110(N, X86::PSRAWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 554:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 550:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PCMPEQWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(554)) {
- SDNode *Result = Emit_111(N, X86::PCMPEQWrr, MVT::v8i16);
+ if (CN1 == INT64_C(550)) {
+ SDNode *Result = Emit_110(N, X86::PCMPEQWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 557:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 553:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PCMPGTWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(557)) {
- SDNode *Result = Emit_111(N, X86::PCMPGTWrr, MVT::v8i16);
+ if (CN1 == INT64_C(553)) {
+ SDNode *Result = Emit_110(N, X86::PCMPGTWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 543:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 539:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PACKSSDWrr:v8i16 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(543)) {
- SDNode *Result = Emit_111(N, X86::PACKSSDWrr, MVT::v8i16);
+ if (CN1 == INT64_C(539)) {
+ SDNode *Result = Emit_110(N, X86::PACKSSDWrr, MVT::v8i16);
return Result;
}
}
}
if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 731:iPTR, VR128:v8i16:$src)
+ // Pattern: (intrinsic_wo_chain:v8i16 727:iPTR, VR128:v8i16:$src)
// Emits: (PABSWrr128:v8i16 VR128:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(731)) {
- SDNode *Result = Emit_108(N, X86::PABSWrr128, MVT::v8i16);
+ if (CN1 == INT64_C(727)) {
+ SDNode *Result = Emit_107(N, X86::PABSWrr128, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 739:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 735:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PHADDWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(739)) {
- SDNode *Result = Emit_111(N, X86::PHADDWrr128, MVT::v8i16);
+ if (CN1 == INT64_C(735)) {
+ SDNode *Result = Emit_110(N, X86::PHADDWrr128, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 745:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 741:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PHSUBWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(745)) {
- SDNode *Result = Emit_111(N, X86::PHSUBWrr128, MVT::v8i16);
+ if (CN1 == INT64_C(741)) {
+ SDNode *Result = Emit_110(N, X86::PHSUBWrr128, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 743:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 739:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PHSUBSWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(743)) {
- SDNode *Result = Emit_111(N, X86::PHSUBSWrr128, MVT::v8i16);
+ if (CN1 == INT64_C(739)) {
+ SDNode *Result = Emit_110(N, X86::PHSUBSWrr128, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 747:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 743:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PMADDUBSWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(747)) {
- SDNode *Result = Emit_111(N, X86::PMADDUBSWrr128, MVT::v8i16);
+ if (CN1 == INT64_C(743)) {
+ SDNode *Result = Emit_110(N, X86::PMADDUBSWrr128, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 749:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 745:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PMULHRSWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(749)) {
- SDNode *Result = Emit_111(N, X86::PMULHRSWrr128, MVT::v8i16);
+ if (CN1 == INT64_C(745)) {
+ SDNode *Result = Emit_110(N, X86::PMULHRSWrr128, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 757:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 753:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PSIGNWrr128:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(757)) {
- SDNode *Result = Emit_111(N, X86::PSIGNWrr128, MVT::v8i16);
+ if (CN1 == INT64_C(753)) {
+ SDNode *Result = Emit_110(N, X86::PSIGNWrr128, MVT::v8i16);
return Result;
}
}
}
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v8i16 630:iPTR, VR128:v8i16:$src)
+ // Pattern: (intrinsic_wo_chain:v8i16 626:iPTR, VR128:v8i16:$src)
// Emits: (PHMINPOSUWrr128:v8i16 VR128:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(630)) {
- SDNode *Result = Emit_108(N, X86::PHMINPOSUWrr128, MVT::v8i16);
+ if (CN1 == INT64_C(626)) {
+ SDNode *Result = Emit_107(N, X86::PHMINPOSUWrr128, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 623:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 619:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PACKUSDWrr:v8i16 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(623)) {
- SDNode *Result = Emit_111(N, X86::PACKUSDWrr, MVT::v8i16);
+ if (CN1 == INT64_C(619)) {
+ SDNode *Result = Emit_110(N, X86::PACKUSDWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 638:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 634:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PMINUWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(638)) {
- SDNode *Result = Emit_111(N, X86::PMINUWrr, MVT::v8i16);
+ if (CN1 == INT64_C(634)) {
+ SDNode *Result = Emit_110(N, X86::PMINUWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 634:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v8i16 630:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PMAXUWrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(634)) {
- SDNode *Result = Emit_111(N, X86::PMAXUWrr, MVT::v8i16);
+ if (CN1 == INT64_C(630)) {
+ SDNode *Result = Emit_110(N, X86::PMAXUWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 641:iPTR, VR128:v16i8:$src)
+ // Pattern: (intrinsic_wo_chain:v8i16 637:iPTR, VR128:v16i8:$src)
// Emits: (PMOVSXBWrr:v8i16 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(641)) {
- SDNode *Result = Emit_108(N, X86::PMOVSXBWrr, MVT::v8i16);
+ if (CN1 == INT64_C(637)) {
+ SDNode *Result = Emit_107(N, X86::PMOVSXBWrr, MVT::v8i16);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v8i16 647:iPTR, VR128:v16i8:$src)
+ // Pattern: (intrinsic_wo_chain:v8i16 643:iPTR, VR128:v16i8:$src)
// Emits: (PMOVZXBWrr:v8i16 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(647)) {
- SDNode *Result = Emit_108(N, X86::PMOVZXBWrr, MVT::v8i16);
+ if (CN1 == INT64_C(643)) {
+ SDNode *Result = Emit_107(N, X86::PMOVZXBWrr, MVT::v8i16);
return Result;
}
}
@@ -18803,30 +18827,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i32 728:iPTR, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v2i32 724:iPTR, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PABSDrm64:v2i32 addr:iPTR:$src)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(728)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(724)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -18834,7 +18858,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_116(N, X86::PABSDrm64, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_115(N, X86::PABSDrm64, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -18842,23 +18866,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i32 734:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v2i32 730:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PHADDDrm64:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(734)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(730)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -18866,7 +18890,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_117(N, X86::PHADDDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PHADDDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -18874,23 +18898,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i32 740:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v2i32 736:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PHSUBDrm64:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(740)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(736)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -18898,7 +18922,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_117(N, X86::PHSUBDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PHSUBDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -18906,23 +18930,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i32 754:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v2i32 750:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PSIGNDrm64:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(754)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(750)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -18930,7 +18954,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_117(N, X86::PSIGNDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSIGNDrm64, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -18940,27 +18964,27 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
}
}
if ((Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i32 480:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v2i32 476:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PMULUDQrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(480)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(476)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -18968,7 +18992,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMULUDQrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PMULUDQrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -18976,22 +19000,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i32 472:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v2i32 468:iPTR, VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PMADDWDrm:v2i32 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(472)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(468)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -18999,7 +19023,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PMADDWDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PMADDWDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -19007,22 +19031,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i32 492:iPTR, VR64:v2i32:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v2i32 488:iPTR, VR64:v2i32:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PSRLDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(492)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(488)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -19030,7 +19054,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PSRLDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PSRLDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -19038,22 +19062,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i32 482:iPTR, VR64:v2i32:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v2i32 478:iPTR, VR64:v2i32:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PSLLDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(482)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(478)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -19061,7 +19085,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PSLLDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PSLLDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -19069,22 +19093,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i32 488:iPTR, VR64:v2i32:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v2i32 484:iPTR, VR64:v2i32:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PSRADrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(488)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(484)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -19092,7 +19116,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PSRADrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PSRADrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -19100,22 +19124,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i32 467:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v2i32 463:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PCMPEQDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(467)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(463)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -19123,7 +19147,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PCMPEQDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PCMPEQDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -19131,22 +19155,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i32 470:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v2i32 466:iPTR, VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PCMPGTDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(470)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(466)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -19154,7 +19178,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PCMPGTDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PCMPGTDrm, MVT::v2i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -19162,30 +19186,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i32 480:iPTR, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v2i32:$src1)
+ // Pattern: (intrinsic_wo_chain:v2i32 476:iPTR, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v2i32:$src1)
// Emits: (MMX_PMULUDQrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(480)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(476)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_118(N, X86::MMX_PMULUDQrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PMULUDQrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -19194,30 +19218,30 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i32 472:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
+ // Pattern: (intrinsic_wo_chain:v2i32 468:iPTR, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
// Emits: (MMX_PMADDWDrm:v2i32 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(472)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(468)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_118(N, X86::MMX_PMADDWDrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::MMX_PMADDWDrm, MVT::v2i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -19228,55 +19252,55 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i32 691:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Pattern: (intrinsic_wo_chain:v2i32 687:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (Int_CVTPS2PIrm:v2i32 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(691)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(687)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTPS2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::Int_CVTPS2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v2i32 697:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Pattern: (intrinsic_wo_chain:v2i32 693:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (Int_CVTTPS2PIrm:v2i32 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(697)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(693)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTTPS2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::Int_CVTTPS2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -19285,57 +19309,57 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i32 688:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v2i32 684:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (Int_CVTPD2PIrm:v2i32 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(688)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(684)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTPD2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::Int_CVTPD2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v2i32 696:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v2i32 692:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (Int_CVTTPD2PIrm:v2i32 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(696)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(692)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTTPD2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::Int_CVTTPD2PIrm, MVT::v2i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -19345,192 +19369,192 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
}
}
if ((Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i32 495:iPTR, VR64:v2i32:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 491:iPTR, VR64:v2i32:$src1, (imm:i32):$src2)
// Emits: (MMX_PSRLDri:v2i32 VR64:v2i32:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(495)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, X86::MMX_PSRLDri, MVT::v2i32);
+ if (CN1 == INT64_C(491)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_127(N, X86::MMX_PSRLDri, MVT::v2i32);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v2i32 485:iPTR, VR64:v2i32:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 481:iPTR, VR64:v2i32:$src1, (imm:i32):$src2)
// Emits: (MMX_PSLLDri:v2i32 VR64:v2i32:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(485)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, X86::MMX_PSLLDri, MVT::v2i32);
+ if (CN1 == INT64_C(481)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_127(N, X86::MMX_PSLLDri, MVT::v2i32);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v2i32 490:iPTR, VR64:v2i32:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 486:iPTR, VR64:v2i32:$src1, (imm:i32):$src2)
// Emits: (MMX_PSRADri:v2i32 VR64:v2i32:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(490)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, X86::MMX_PSRADri, MVT::v2i32);
+ if (CN1 == INT64_C(486)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_127(N, X86::MMX_PSRADri, MVT::v2i32);
return Result;
}
}
}
}
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i32 691:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v2i32 687:iPTR, VR128:v4f32:$src)
// Emits: (Int_CVTPS2PIrr:v2i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(691)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPS2PIrr, MVT::v2i32);
+ if (CN1 == INT64_C(687)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTPS2PIrr, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 697:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v2i32 693:iPTR, VR128:v4f32:$src)
// Emits: (Int_CVTTPS2PIrr:v2i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(697)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTPS2PIrr, MVT::v2i32);
+ if (CN1 == INT64_C(693)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTTPS2PIrr, MVT::v2i32);
return Result;
}
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i32 688:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:v2i32 684:iPTR, VR128:v2f64:$src)
// Emits: (Int_CVTPD2PIrr:v2i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(688)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPD2PIrr, MVT::v2i32);
+ if (CN1 == INT64_C(684)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTPD2PIrr, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 696:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:v2i32 692:iPTR, VR128:v2f64:$src)
// Emits: (Int_CVTTPD2PIrr:v2i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(696)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTPD2PIrr, MVT::v2i32);
+ if (CN1 == INT64_C(692)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTTPD2PIrr, MVT::v2i32);
return Result;
}
}
}
if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i32 728:iPTR, VR64:v2i32:$src)
+ // Pattern: (intrinsic_wo_chain:v2i32 724:iPTR, VR64:v2i32:$src)
// Emits: (PABSDrr64:v2i32 VR64:v2i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(728)) {
- SDNode *Result = Emit_108(N, X86::PABSDrr64, MVT::v2i32);
+ if (CN1 == INT64_C(724)) {
+ SDNode *Result = Emit_107(N, X86::PABSDrr64, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 734:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 730:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
// Emits: (PHADDDrr64:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(734)) {
- SDNode *Result = Emit_111(N, X86::PHADDDrr64, MVT::v2i32);
+ if (CN1 == INT64_C(730)) {
+ SDNode *Result = Emit_110(N, X86::PHADDDrr64, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 740:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 736:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
// Emits: (PHSUBDrr64:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(740)) {
- SDNode *Result = Emit_111(N, X86::PHSUBDrr64, MVT::v2i32);
+ if (CN1 == INT64_C(736)) {
+ SDNode *Result = Emit_110(N, X86::PHSUBDrr64, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 754:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 750:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
// Emits: (PSIGNDrr64:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(754)) {
- SDNode *Result = Emit_111(N, X86::PSIGNDrr64, MVT::v2i32);
+ if (CN1 == INT64_C(750)) {
+ SDNode *Result = Emit_110(N, X86::PSIGNDrr64, MVT::v2i32);
return Result;
}
}
}
if ((Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i32 480:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 476:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
// Emits: (MMX_PMULUDQrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(480)) {
- SDNode *Result = Emit_111(N, X86::MMX_PMULUDQrr, MVT::v2i32);
+ if (CN1 == INT64_C(476)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PMULUDQrr, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 472:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 468:iPTR, VR64:v4i16:$src1, VR64:v4i16:$src2)
// Emits: (MMX_PMADDWDrr:v2i32 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(472)) {
- SDNode *Result = Emit_111(N, X86::MMX_PMADDWDrr, MVT::v2i32);
+ if (CN1 == INT64_C(468)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PMADDWDrr, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 492:iPTR, VR64:v2i32:$src1, VR64:v1i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 488:iPTR, VR64:v2i32:$src1, VR64:v1i64:$src2)
// Emits: (MMX_PSRLDrr:v2i32 VR64:v2i32:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(492)) {
- SDNode *Result = Emit_111(N, X86::MMX_PSRLDrr, MVT::v2i32);
+ if (CN1 == INT64_C(488)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PSRLDrr, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 482:iPTR, VR64:v2i32:$src1, VR64:v1i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 478:iPTR, VR64:v2i32:$src1, VR64:v1i64:$src2)
// Emits: (MMX_PSLLDrr:v2i32 VR64:v2i32:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(482)) {
- SDNode *Result = Emit_111(N, X86::MMX_PSLLDrr, MVT::v2i32);
+ if (CN1 == INT64_C(478)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PSLLDrr, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 488:iPTR, VR64:v2i32:$src1, VR64:v1i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 484:iPTR, VR64:v2i32:$src1, VR64:v1i64:$src2)
// Emits: (MMX_PSRADrr:v2i32 VR64:v2i32:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(488)) {
- SDNode *Result = Emit_111(N, X86::MMX_PSRADrr, MVT::v2i32);
+ if (CN1 == INT64_C(484)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PSRADrr, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 467:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 463:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
// Emits: (MMX_PCMPEQDrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(467)) {
- SDNode *Result = Emit_111(N, X86::MMX_PCMPEQDrr, MVT::v2i32);
+ if (CN1 == INT64_C(463)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PCMPEQDrr, MVT::v2i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i32 470:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i32 466:iPTR, VR64:v2i32:$src1, VR64:v2i32:$src2)
// Emits: (MMX_PCMPGTDrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(470)) {
- SDNode *Result = Emit_111(N, X86::MMX_PCMPGTDrr, MVT::v2i32);
+ if (CN1 == INT64_C(466)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PCMPGTDrr, MVT::v2i32);
return Result;
}
}
@@ -19540,50 +19564,50 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_132(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_131(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { N2, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i32 643:iPTR, (bitconvert:v8i16 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
+ // Pattern: (intrinsic_wo_chain:v4i32 639:iPTR, (bitconvert:v8i16 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
// Emits: (PMOVSXWDrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(643)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(639)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N100.hasOneUse()) {
- SDValue N1000 = N100.getOperand(0);
- if (N1000.getOpcode() == ISD::LOAD &&
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
- SDValue Chain1000 = N1000.getOperand(0);
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
if (Predicate_unindexedload(N1000.getNode()) &&
Predicate_load(N1000.getNode()) &&
Predicate_loadi64(N1000.getNode())) {
- SDValue N10001 = N1000.getOperand(1);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
SDValue CPTmpN10001_0;
SDValue CPTmpN10001_1;
SDValue CPTmpN10001_2;
@@ -19592,7 +19616,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v2i64 &&
N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_130(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -19602,28 +19626,28 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 649:iPTR, (bitconvert:v8i16 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
+ // Pattern: (intrinsic_wo_chain:v4i32 645:iPTR, (bitconvert:v8i16 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
// Emits: (PMOVZXWDrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(649)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(645)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N100.hasOneUse()) {
- SDValue N1000 = N100.getOperand(0);
- if (N1000.getOpcode() == ISD::LOAD &&
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
- SDValue Chain1000 = N1000.getOperand(0);
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
if (Predicate_unindexedload(N1000.getNode()) &&
Predicate_load(N1000.getNode()) &&
Predicate_loadi64(N1000.getNode())) {
- SDValue N10001 = N1000.getOperand(1);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
SDValue CPTmpN10001_0;
SDValue CPTmpN10001_1;
SDValue CPTmpN10001_2;
@@ -19632,7 +19656,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v2i64 &&
N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_130(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -19642,27 +19666,27 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 639:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
+ // Pattern: (intrinsic_wo_chain:v4i32 635:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
// Emits: (PMOVSXBDrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(639)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(635)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N100.hasOneUse()) {
- SDValue N1000 = N100.getOperand(0);
- if (N1000.getOpcode() == ISD::LOAD &&
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
- SDValue Chain1000 = N1000.getOperand(0);
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
if (Predicate_unindexedload(N1000.getNode()) &&
Predicate_loadi32(N1000.getNode())) {
- SDValue N10001 = N1000.getOperand(1);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
SDValue CPTmpN10001_0;
SDValue CPTmpN10001_1;
SDValue CPTmpN10001_2;
@@ -19671,7 +19695,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v4i32 &&
N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_130(N, X86::PMOVSXBDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVSXBDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -19681,27 +19705,27 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 645:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
+ // Pattern: (intrinsic_wo_chain:v4i32 641:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
// Emits: (PMOVZXBDrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(645)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(641)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N100.hasOneUse()) {
- SDValue N1000 = N100.getOperand(0);
- if (N1000.getOpcode() == ISD::LOAD &&
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
- SDValue Chain1000 = N1000.getOperand(0);
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
if (Predicate_unindexedload(N1000.getNode()) &&
Predicate_loadi32(N1000.getNode())) {
- SDValue N10001 = N1000.getOperand(1);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
SDValue CPTmpN10001_0;
SDValue CPTmpN10001_1;
SDValue CPTmpN10001_2;
@@ -19710,7 +19734,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v4i32 &&
N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_130(N, X86::PMOVZXBDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVZXBDrm, MVT::v4i32, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -19720,25 +19744,25 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 643:iPTR, (bitconvert:v8i16 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
+ // Pattern: (intrinsic_wo_chain:v4i32 639:iPTR, (bitconvert:v8i16 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
// Emits: (PMOVSXWDrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(643)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(639)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
- SDValue Chain100 = N100.getOperand(0);
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_load(N100.getNode()) &&
Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
@@ -19747,7 +19771,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v2i64 &&
N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_129(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_128(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -19756,25 +19780,25 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 649:iPTR, (bitconvert:v8i16 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
+ // Pattern: (intrinsic_wo_chain:v4i32 645:iPTR, (bitconvert:v8i16 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
// Emits: (PMOVZXWDrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(649)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(645)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
- SDValue Chain100 = N100.getOperand(0);
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_load(N100.getNode()) &&
Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
@@ -19783,7 +19807,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v2i64 &&
N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_129(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_128(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -19792,24 +19816,24 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 639:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
+ // Pattern: (intrinsic_wo_chain:v4i32 635:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
// Emits: (PMOVSXBDrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(639)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(635)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
- SDValue Chain100 = N100.getOperand(0);
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
@@ -19818,7 +19842,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v4i32 &&
N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_129(N, X86::PMOVSXBDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_128(N, X86::PMOVSXBDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -19827,24 +19851,24 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 645:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
+ // Pattern: (intrinsic_wo_chain:v4i32 641:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
// Emits: (PMOVZXBDrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(645)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(641)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
- SDValue Chain100 = N100.getOperand(0);
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
@@ -19853,7 +19877,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v4i32 &&
N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_129(N, X86::PMOVZXBDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_128(N, X86::PMOVZXBDrm, MVT::v4i32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -19864,28 +19888,28 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i32 558:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v4i32 554:iPTR, VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PMADDWDrm:v4i32 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(558)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(554)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -19893,7 +19917,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMADDWDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMADDWDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -19901,23 +19925,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 568:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v4i32 564:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PSLLDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(568)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(564)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -19925,7 +19949,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PSLLDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSLLDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -19933,23 +19957,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 580:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v4i32 576:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PSRLDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(580)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(576)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -19957,7 +19981,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PSRLDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSRLDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -19965,23 +19989,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 576:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v4i32 572:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PSRADrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(576)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(572)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -19989,7 +20013,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PSRADrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSRADrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -19997,23 +20021,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 553:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v4i32 549:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PCMPEQDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(553)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(549)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -20021,7 +20045,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PCMPEQDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PCMPEQDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -20029,23 +20053,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 556:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v4i32 552:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PCMPGTDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(556)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(552)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -20053,7 +20077,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PCMPGTDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PCMPGTDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -20063,27 +20087,27 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i32 729:iPTR, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v4i32 725:iPTR, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PABSDrm128:v4i32 addr:iPTR:$src)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(729)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(725)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -20091,7 +20115,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_116(N, X86::PABSDrm128, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_115(N, X86::PABSDrm128, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -20099,23 +20123,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 735:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v4i32 731:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PHADDDrm128:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(735)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(731)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -20123,7 +20147,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_117(N, X86::PHADDDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PHADDDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -20131,23 +20155,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 737:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
+ // Pattern: (intrinsic_wo_chain:v4i32 733:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>))
// Emits: (PHADDSWrm128:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(737)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(733)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop64(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -20155,7 +20179,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_117(N, X86::PHADDSWrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PHADDSWrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -20163,23 +20187,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 741:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v4i32 737:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PHSUBDrm128:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(741)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(737)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -20187,7 +20211,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_117(N, X86::PHSUBDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PHSUBDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -20195,23 +20219,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 755:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v4i32 751:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PSIGNDrm128:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(755)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(751)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -20219,7 +20243,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_117(N, X86::PSIGNDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSIGNDrm128, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -20229,28 +20253,28 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i32 636:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v4i32 632:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PMINSDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(636)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(632)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -20258,7 +20282,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMINSDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMINSDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -20266,23 +20290,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 637:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v4i32 633:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PMINUDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(637)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(633)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -20290,7 +20314,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMINUDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMINUDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -20298,23 +20322,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 632:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v4i32 628:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PMAXSDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(632)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(628)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -20322,7 +20346,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMAXSDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMAXSDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -20330,23 +20354,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 633:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v4i32 629:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PMAXUDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(633)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(629)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -20354,7 +20378,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMAXUDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMAXUDrm, MVT::v4i32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -20364,36 +20388,36 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 558:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
+ // Pattern: (intrinsic_wo_chain:v4i32 554:iPTR, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
// Emits: (PMADDWDrm:v4i32 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(558)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(554)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_118(N, X86::PMADDWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PMADDWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -20404,36 +20428,36 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i32 636:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
+ // Pattern: (intrinsic_wo_chain:v4i32 632:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
// Emits: (PMINSDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(636)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(632)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_118(N, X86::PMINSDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PMINSDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -20442,31 +20466,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 637:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
+ // Pattern: (intrinsic_wo_chain:v4i32 633:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
// Emits: (PMINUDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(637)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(633)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_118(N, X86::PMINUDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PMINUDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -20475,31 +20499,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 632:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
+ // Pattern: (intrinsic_wo_chain:v4i32 628:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
// Emits: (PMAXSDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(632)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(628)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_118(N, X86::PMAXSDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PMAXSDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -20508,31 +20532,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 633:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
+ // Pattern: (intrinsic_wo_chain:v4i32 629:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
// Emits: (PMAXUDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(633)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(629)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_118(N, X86::PMAXUDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PMAXUDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -20541,19 +20565,19 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 643:iPTR, (bitconvert:v8i16 (X86vzload:v2i64 addr:iPTR:$src)))
+ // Pattern: (intrinsic_wo_chain:v4i32 639:iPTR, (bitconvert:v8i16 (X86vzload:v2i64 addr:iPTR:$src)))
// Emits: (PMOVSXWDrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 32 cost = 1 size = 3
- if (CN1 == INT64_C(643)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(639)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == X86ISD::VZEXT_LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -20561,26 +20585,26 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_131(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_130(N, X86::PMOVSXWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 649:iPTR, (bitconvert:v8i16 (X86vzload:v2i64 addr:iPTR:$src)))
+ // Pattern: (intrinsic_wo_chain:v4i32 645:iPTR, (bitconvert:v8i16 (X86vzload:v2i64 addr:iPTR:$src)))
// Emits: (PMOVZXWDrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 32 cost = 1 size = 3
- if (CN1 == INT64_C(649)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(645)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == X86ISD::VZEXT_LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -20588,7 +20612,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_131(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_130(N, X86::PMOVZXWDrm, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -20597,109 +20621,109 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i32 516:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v4i32 512:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (Int_CVTPS2DQrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(516)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(512)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTPS2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::Int_CVTPS2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 525:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v4i32 521:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (Int_CVTTPS2DQrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(525)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(521)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTTPS2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::Int_CVTTPS2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 514:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v4i32 510:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (Int_CVTPD2DQrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(514)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(510)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTPD2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::Int_CVTPD2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 524:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v4i32 520:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (Int_CVTTPD2DQrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(524)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(520)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTTPD2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::Int_CVTTPD2DQrm, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -20708,57 +20732,57 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(652)) {
- SDValue N1 = N.getOperand(1);
+ if (CN1 == INT64_C(648)) {
+ SDValue N1 = N->getOperand(1);
- // Pattern: (intrinsic_wo_chain:v4i32 652:iPTR, VR128:v4i32:$src1, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v4i32 648:iPTR, VR128:v4i32:$src1, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PMULLDrm_int:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
{
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode()) &&
Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::PMULLDrm_int, MVT::v4i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::PMULLDrm_int, MVT::v4i32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 652:iPTR, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v4i32:$src1)
+ // Pattern: (intrinsic_wo_chain:v4i32 648:iPTR, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v4i32:$src1)
// Emits: (PMULLDrm_int:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (N1.getOpcode() == ISD::LOAD &&
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_132(N, X86::PMULLDrm_int, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_131(N, X86::PMULLDrm_int, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -20768,250 +20792,250 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i32 573:iPTR, VR128:v4i32:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 569:iPTR, VR128:v4i32:$src1, (imm:i32):$src2)
// Emits: (PSLLDri:v4i32 VR128:v4i32:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(573)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, X86::PSLLDri, MVT::v4i32);
+ if (CN1 == INT64_C(569)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_127(N, X86::PSLLDri, MVT::v4i32);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 585:iPTR, VR128:v4i32:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 581:iPTR, VR128:v4i32:$src1, (imm:i32):$src2)
// Emits: (PSRLDri:v4i32 VR128:v4i32:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(585)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, X86::PSRLDri, MVT::v4i32);
+ if (CN1 == INT64_C(581)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_127(N, X86::PSRLDri, MVT::v4i32);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 578:iPTR, VR128:v4i32:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 574:iPTR, VR128:v4i32:$src1, (imm:i32):$src2)
// Emits: (PSRADri:v4i32 VR128:v4i32:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(578)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, X86::PSRADri, MVT::v4i32);
+ if (CN1 == INT64_C(574)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_127(N, X86::PSRADri, MVT::v4i32);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4i32 516:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v4i32 512:iPTR, VR128:v4f32:$src)
// Emits: (Int_CVTPS2DQrr:v4i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(516)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPS2DQrr, MVT::v4i32);
+ if (CN1 == INT64_C(512)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTPS2DQrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 525:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v4i32 521:iPTR, VR128:v4f32:$src)
// Emits: (Int_CVTTPS2DQrr:v4i32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(525)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTPS2DQrr, MVT::v4i32);
+ if (CN1 == INT64_C(521)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTTPS2DQrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 514:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:v4i32 510:iPTR, VR128:v2f64:$src)
// Emits: (Int_CVTPD2DQrr:v4i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(514)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPD2DQrr, MVT::v4i32);
+ if (CN1 == INT64_C(510)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTPD2DQrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 524:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:v4i32 520:iPTR, VR128:v2f64:$src)
// Emits: (Int_CVTTPD2DQrr:v4i32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(524)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTTPD2DQrr, MVT::v4i32);
+ if (CN1 == INT64_C(520)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTTPD2DQrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 558:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 554:iPTR, VR128:v8i16:$src1, VR128:v8i16:$src2)
// Emits: (PMADDWDrr:v4i32 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(558)) {
- SDNode *Result = Emit_111(N, X86::PMADDWDrr, MVT::v4i32);
+ if (CN1 == INT64_C(554)) {
+ SDNode *Result = Emit_110(N, X86::PMADDWDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 568:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 564:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PSLLDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(568)) {
- SDNode *Result = Emit_111(N, X86::PSLLDrr, MVT::v4i32);
+ if (CN1 == INT64_C(564)) {
+ SDNode *Result = Emit_110(N, X86::PSLLDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 580:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 576:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PSRLDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(580)) {
- SDNode *Result = Emit_111(N, X86::PSRLDrr, MVT::v4i32);
+ if (CN1 == INT64_C(576)) {
+ SDNode *Result = Emit_110(N, X86::PSRLDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 576:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 572:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PSRADrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(576)) {
- SDNode *Result = Emit_111(N, X86::PSRADrr, MVT::v4i32);
+ if (CN1 == INT64_C(572)) {
+ SDNode *Result = Emit_110(N, X86::PSRADrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 553:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 549:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PCMPEQDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(553)) {
- SDNode *Result = Emit_111(N, X86::PCMPEQDrr, MVT::v4i32);
+ if (CN1 == INT64_C(549)) {
+ SDNode *Result = Emit_110(N, X86::PCMPEQDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 556:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 552:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PCMPGTDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(556)) {
- SDNode *Result = Emit_111(N, X86::PCMPGTDrr, MVT::v4i32);
+ if (CN1 == INT64_C(552)) {
+ SDNode *Result = Emit_110(N, X86::PCMPGTDrr, MVT::v4i32);
return Result;
}
}
}
if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i32 729:iPTR, VR128:v4i32:$src)
+ // Pattern: (intrinsic_wo_chain:v4i32 725:iPTR, VR128:v4i32:$src)
// Emits: (PABSDrr128:v4i32 VR128:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(729)) {
- SDNode *Result = Emit_108(N, X86::PABSDrr128, MVT::v4i32);
+ if (CN1 == INT64_C(725)) {
+ SDNode *Result = Emit_107(N, X86::PABSDrr128, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 735:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 731:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PHADDDrr128:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(735)) {
- SDNode *Result = Emit_111(N, X86::PHADDDrr128, MVT::v4i32);
+ if (CN1 == INT64_C(731)) {
+ SDNode *Result = Emit_110(N, X86::PHADDDrr128, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 737:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 733:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PHADDSWrr128:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(737)) {
- SDNode *Result = Emit_111(N, X86::PHADDSWrr128, MVT::v4i32);
+ if (CN1 == INT64_C(733)) {
+ SDNode *Result = Emit_110(N, X86::PHADDSWrr128, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 741:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 737:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PHSUBDrr128:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(741)) {
- SDNode *Result = Emit_111(N, X86::PHSUBDrr128, MVT::v4i32);
+ if (CN1 == INT64_C(737)) {
+ SDNode *Result = Emit_110(N, X86::PHSUBDrr128, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 755:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 751:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PSIGNDrr128:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(755)) {
- SDNode *Result = Emit_111(N, X86::PSIGNDrr128, MVT::v4i32);
+ if (CN1 == INT64_C(751)) {
+ SDNode *Result = Emit_110(N, X86::PSIGNDrr128, MVT::v4i32);
return Result;
}
}
}
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4i32 636:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 632:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PMINSDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(636)) {
- SDNode *Result = Emit_111(N, X86::PMINSDrr, MVT::v4i32);
+ if (CN1 == INT64_C(632)) {
+ SDNode *Result = Emit_110(N, X86::PMINSDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 637:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 633:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PMINUDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(637)) {
- SDNode *Result = Emit_111(N, X86::PMINUDrr, MVT::v4i32);
+ if (CN1 == INT64_C(633)) {
+ SDNode *Result = Emit_110(N, X86::PMINUDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 632:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 628:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PMAXSDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(632)) {
- SDNode *Result = Emit_111(N, X86::PMAXSDrr, MVT::v4i32);
+ if (CN1 == INT64_C(628)) {
+ SDNode *Result = Emit_110(N, X86::PMAXSDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 633:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 629:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PMAXUDrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(633)) {
- SDNode *Result = Emit_111(N, X86::PMAXUDrr, MVT::v4i32);
+ if (CN1 == INT64_C(629)) {
+ SDNode *Result = Emit_110(N, X86::PMAXUDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 652:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4i32 648:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PMULLDrr_int:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(652)) {
- SDNode *Result = Emit_111(N, X86::PMULLDrr_int, MVT::v4i32);
+ if (CN1 == INT64_C(648)) {
+ SDNode *Result = Emit_110(N, X86::PMULLDrr_int, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 643:iPTR, VR128:v8i16:$src)
+ // Pattern: (intrinsic_wo_chain:v4i32 639:iPTR, VR128:v8i16:$src)
// Emits: (PMOVSXWDrr:v4i32 VR128:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(643)) {
- SDNode *Result = Emit_108(N, X86::PMOVSXWDrr, MVT::v4i32);
+ if (CN1 == INT64_C(639)) {
+ SDNode *Result = Emit_107(N, X86::PMOVSXWDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 649:iPTR, VR128:v8i16:$src)
+ // Pattern: (intrinsic_wo_chain:v4i32 645:iPTR, VR128:v8i16:$src)
// Emits: (PMOVZXWDrr:v4i32 VR128:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(649)) {
- SDNode *Result = Emit_108(N, X86::PMOVZXWDrr, MVT::v4i32);
+ if (CN1 == INT64_C(645)) {
+ SDNode *Result = Emit_107(N, X86::PMOVZXWDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 639:iPTR, VR128:v16i8:$src)
+ // Pattern: (intrinsic_wo_chain:v4i32 635:iPTR, VR128:v16i8:$src)
// Emits: (PMOVSXBDrr:v4i32 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(639)) {
- SDNode *Result = Emit_108(N, X86::PMOVSXBDrr, MVT::v4i32);
+ if (CN1 == INT64_C(635)) {
+ SDNode *Result = Emit_107(N, X86::PMOVSXBDrr, MVT::v4i32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4i32 645:iPTR, VR128:v16i8:$src)
+ // Pattern: (intrinsic_wo_chain:v4i32 641:iPTR, VR128:v16i8:$src)
// Emits: (PMOVZXBDrr:v4i32 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(645)) {
- SDNode *Result = Emit_108(N, X86::PMOVZXBDrr, MVT::v4i32);
+ if (CN1 == INT64_C(641)) {
+ SDNode *Result = Emit_107(N, X86::PMOVZXBDrr, MVT::v4i32);
return Result;
}
}
@@ -21021,56 +21045,56 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_133(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_132(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i8);
SDValue Tmp5 = Transform_BYTE_imm(Tmp4.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N2, Tmp5);
-}
-DISABLE_INLINE SDNode *Emit_134(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue Chain2 = N2.getOperand(0);
- SDValue N21 = N2.getOperand(1);
- SDValue N3 = N.getOperand(3);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N2, Tmp5);
+}
+DISABLE_INLINE SDNode *Emit_133(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN21_0, SDValue &CPTmpN21_1, SDValue &CPTmpN21_2, SDValue &CPTmpN21_3, SDValue &CPTmpN21_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue Chain2 = N2.getNode()->getOperand(0);
+ SDValue N21 = N2.getNode()->getOperand(1);
+ SDValue N3 = N->getOperand(3);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i8);
SDValue Tmp5 = Transform_BYTE_imm(Tmp4.getNode());
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N2)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N2.getNode())->getMemOperand();
SDValue Ops0[] = { N1, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4, Tmp5, Chain2 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N2.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v1i64 493:iPTR, VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v1i64 489:iPTR, VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PSRLQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(493)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(489)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -21078,7 +21102,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PSRLQrm, MVT::v1i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PSRLQrm, MVT::v1i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -21086,22 +21110,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v1i64 483:iPTR, VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
+ // Pattern: (intrinsic_wo_chain:v1i64 479:iPTR, VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PSLLQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(483)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(479)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -21109,7 +21133,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_117(N, X86::MMX_PSLLQrm, MVT::v1i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::MMX_PSLLQrm, MVT::v1i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -21119,34 +21143,34 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v1i64 732:iPTR, VR64:v1i64:$src1, (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:v1i64 728:iPTR, VR64:v1i64:$src1, (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop64>>, (imm:i8):$src3)
// Emits: (PALIGNR64rm:v1i64 VR64:v8i8:$src1, addr:iPTR:$src2, (BYTE_imm:i8 (imm:i8):$src3))
// Pattern complexity = 33 cost = 1 size = 3
if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(732)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(728)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode()) &&
Predicate_memop64(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_134(N, X86::PALIGNR64rm, MVT::v1i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_133(N, X86::PALIGNR64rm, MVT::v1i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -21157,75 +21181,75 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
}
}
if ((Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v1i64 496:iPTR, VR64:v1i64:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v1i64 492:iPTR, VR64:v1i64:$src1, (imm:i32):$src2)
// Emits: (MMX_PSRLQri:v1i64 VR64:v1i64:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(496)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, X86::MMX_PSRLQri, MVT::v1i64);
+ if (CN1 == INT64_C(492)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_127(N, X86::MMX_PSRLQri, MVT::v1i64);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v1i64 486:iPTR, VR64:v1i64:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v1i64 482:iPTR, VR64:v1i64:$src1, (imm:i32):$src2)
// Emits: (MMX_PSLLQri:v1i64 VR64:v1i64:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(486)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, X86::MMX_PSLLQri, MVT::v1i64);
+ if (CN1 == INT64_C(482)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_127(N, X86::MMX_PSLLQri, MVT::v1i64);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v1i64 732:iPTR, VR64:v1i64:$src1, VR64:v1i64:$src2, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:v1i64 728:iPTR, VR64:v1i64:$src1, VR64:v1i64:$src2, (imm:i8):$src3)
// Emits: (PALIGNR64rr:v1i64 VR64:v8i8:$src1, VR64:v8i8:$src2, (BYTE_imm:i8 (imm:i8):$src3))
// Pattern complexity = 11 cost = 1 size = 3
if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(732)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_133(N, X86::PALIGNR64rr, MVT::v1i64);
+ if (CN1 == INT64_C(728)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_132(N, X86::PALIGNR64rr, MVT::v1i64);
return Result;
}
}
}
}
if ((Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v1i64 493:iPTR, VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v1i64 489:iPTR, VR64:v1i64:$src1, VR64:v1i64:$src2)
// Emits: (MMX_PSRLQrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(493)) {
- SDNode *Result = Emit_111(N, X86::MMX_PSRLQrr, MVT::v1i64);
+ if (CN1 == INT64_C(489)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PSRLQrr, MVT::v1i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v1i64 483:iPTR, VR64:v1i64:$src1, VR64:v1i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v1i64 479:iPTR, VR64:v1i64:$src1, VR64:v1i64:$src2)
// Emits: (MMX_PSLLQrr:v1i64 VR64:v1i64:$src1, VR64:v1i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(483)) {
- SDNode *Result = Emit_111(N, X86::MMX_PSLLQrr, MVT::v1i64);
+ if (CN1 == INT64_C(479)) {
+ SDNode *Result = Emit_110(N, X86::MMX_PSLLQrr, MVT::v1i64);
return Result;
}
}
@@ -21235,44 +21259,44 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v1i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_135(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_134(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
SDValue Tmp4 = Transform_BYTE_imm(Tmp3.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, Tmp4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, Tmp4);
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i64 642:iPTR, (bitconvert:v4i32 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
+ // Pattern: (intrinsic_wo_chain:v2i64 638:iPTR, (bitconvert:v4i32 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
// Emits: (PMOVSXDQrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(642)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(638)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N100.hasOneUse()) {
- SDValue N1000 = N100.getOperand(0);
- if (N1000.getOpcode() == ISD::LOAD &&
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
- SDValue Chain1000 = N1000.getOperand(0);
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
if (Predicate_unindexedload(N1000.getNode()) &&
Predicate_load(N1000.getNode()) &&
Predicate_loadi64(N1000.getNode())) {
- SDValue N10001 = N1000.getOperand(1);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
SDValue CPTmpN10001_0;
SDValue CPTmpN10001_1;
SDValue CPTmpN10001_2;
@@ -21281,7 +21305,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v2i64 &&
N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_130(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -21291,28 +21315,28 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 648:iPTR, (bitconvert:v4i32 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
+ // Pattern: (intrinsic_wo_chain:v2i64 644:iPTR, (bitconvert:v4i32 (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))))
// Emits: (PMOVZXDQrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(648)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(644)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N100.hasOneUse()) {
- SDValue N1000 = N100.getOperand(0);
- if (N1000.getOpcode() == ISD::LOAD &&
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
- SDValue Chain1000 = N1000.getOperand(0);
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
if (Predicate_unindexedload(N1000.getNode()) &&
Predicate_load(N1000.getNode()) &&
Predicate_loadi64(N1000.getNode())) {
- SDValue N10001 = N1000.getOperand(1);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
SDValue CPTmpN10001_0;
SDValue CPTmpN10001_1;
SDValue CPTmpN10001_2;
@@ -21321,7 +21345,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v2i64 &&
N1000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_130(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -21331,27 +21355,27 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 644:iPTR, (bitconvert:v8i16 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
+ // Pattern: (intrinsic_wo_chain:v2i64 640:iPTR, (bitconvert:v8i16 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
// Emits: (PMOVSXWQrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(644)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(640)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N100.hasOneUse()) {
- SDValue N1000 = N100.getOperand(0);
- if (N1000.getOpcode() == ISD::LOAD &&
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
- SDValue Chain1000 = N1000.getOperand(0);
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
if (Predicate_unindexedload(N1000.getNode()) &&
Predicate_loadi32(N1000.getNode())) {
- SDValue N10001 = N1000.getOperand(1);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
SDValue CPTmpN10001_0;
SDValue CPTmpN10001_1;
SDValue CPTmpN10001_2;
@@ -21360,7 +21384,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v4i32 &&
N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_130(N, X86::PMOVSXWQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVSXWQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -21370,27 +21394,27 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 650:iPTR, (bitconvert:v8i16 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
+ // Pattern: (intrinsic_wo_chain:v2i64 646:iPTR, (bitconvert:v8i16 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
// Emits: (PMOVZXWQrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(650)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(646)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N100.hasOneUse()) {
- SDValue N1000 = N100.getOperand(0);
- if (N1000.getOpcode() == ISD::LOAD &&
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
- SDValue Chain1000 = N1000.getOperand(0);
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
if (Predicate_unindexedload(N1000.getNode()) &&
Predicate_loadi32(N1000.getNode())) {
- SDValue N10001 = N1000.getOperand(1);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
SDValue CPTmpN10001_0;
SDValue CPTmpN10001_1;
SDValue CPTmpN10001_2;
@@ -21399,7 +21423,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v4i32 &&
N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_130(N, X86::PMOVZXWQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVZXWQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -21409,27 +21433,27 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 640:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
+ // Pattern: (intrinsic_wo_chain:v2i64 636:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
// Emits: (PMOVSXBQrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(640)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(636)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N100.hasOneUse()) {
- SDValue N1000 = N100.getOperand(0);
- if (N1000.getOpcode() == ISD::LOAD &&
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
- SDValue Chain1000 = N1000.getOperand(0);
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
if (Predicate_unindexedload(N1000.getNode()) &&
Predicate_loadi32(N1000.getNode())) {
- SDValue N10001 = N1000.getOperand(1);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
SDValue CPTmpN10001_0;
SDValue CPTmpN10001_1;
SDValue CPTmpN10001_2;
@@ -21438,7 +21462,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v4i32 &&
N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_130(N, X86::PMOVSXBQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVSXBQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -21448,27 +21472,27 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 646:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
+ // Pattern: (intrinsic_wo_chain:v2i64 642:iPTR, (bitconvert:v16i8 (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))))
// Emits: (PMOVZXBQrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 39 cost = 1 size = 3
- if (CN1 == INT64_C(646)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(642)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == X86ISD::VZEXT_MOVL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_MOVL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N100.hasOneUse()) {
- SDValue N1000 = N100.getOperand(0);
- if (N1000.getOpcode() == ISD::LOAD &&
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ if (N1000.getNode()->getOpcode() == ISD::LOAD &&
N1000.hasOneUse() &&
- IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N.getNode())) {
- SDValue Chain1000 = N1000.getOperand(0);
+ IsLegalAndProfitableToFold(N1000.getNode(), N100.getNode(), N)) {
+ SDValue Chain1000 = N1000.getNode()->getOperand(0);
if (Predicate_unindexedload(N1000.getNode()) &&
Predicate_loadi32(N1000.getNode())) {
- SDValue N10001 = N1000.getOperand(1);
+ SDValue N10001 = N1000.getNode()->getOperand(1);
SDValue CPTmpN10001_0;
SDValue CPTmpN10001_1;
SDValue CPTmpN10001_2;
@@ -21477,7 +21501,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N10001, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4) &&
N10.getValueType() == MVT::v4i32 &&
N1000.getValueType() == MVT::i32) {
- SDNode *Result = Emit_130(N, X86::PMOVZXBQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
+ SDNode *Result = Emit_129(N, X86::PMOVZXBQrm, MVT::v2i64, CPTmpN10001_0, CPTmpN10001_1, CPTmpN10001_2, CPTmpN10001_3, CPTmpN10001_4);
return Result;
}
}
@@ -21487,25 +21511,25 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 642:iPTR, (bitconvert:v4i32 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
+ // Pattern: (intrinsic_wo_chain:v2i64 638:iPTR, (bitconvert:v4i32 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
// Emits: (PMOVSXDQrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(642)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(638)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
- SDValue Chain100 = N100.getOperand(0);
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_load(N100.getNode()) &&
Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
@@ -21514,7 +21538,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v2i64 &&
N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_129(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_128(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -21523,25 +21547,25 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 648:iPTR, (bitconvert:v4i32 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
+ // Pattern: (intrinsic_wo_chain:v2i64 644:iPTR, (bitconvert:v4i32 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)))
// Emits: (PMOVZXDQrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(648)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(644)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
- SDValue Chain100 = N100.getOperand(0);
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_load(N100.getNode()) &&
Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
@@ -21550,7 +21574,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v2i64 &&
N100.getValueType() == MVT::i64) {
- SDNode *Result = Emit_129(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_128(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -21559,24 +21583,24 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 644:iPTR, (bitconvert:v8i16 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
+ // Pattern: (intrinsic_wo_chain:v2i64 640:iPTR, (bitconvert:v8i16 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
// Emits: (PMOVSXWQrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(644)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(640)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
- SDValue Chain100 = N100.getOperand(0);
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
@@ -21585,7 +21609,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v4i32 &&
N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_129(N, X86::PMOVSXWQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_128(N, X86::PMOVSXWQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -21594,24 +21618,24 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 650:iPTR, (bitconvert:v8i16 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
+ // Pattern: (intrinsic_wo_chain:v2i64 646:iPTR, (bitconvert:v8i16 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
// Emits: (PMOVZXWQrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(650)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(646)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
- SDValue Chain100 = N100.getOperand(0);
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
@@ -21620,7 +21644,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v4i32 &&
N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_129(N, X86::PMOVZXWQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_128(N, X86::PMOVZXWQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -21629,24 +21653,24 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 640:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16_anyext>>)))
+ // Pattern: (intrinsic_wo_chain:v2i64 636:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16_anyext>>)))
// Emits: (PMOVSXBQrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(640)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(636)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
- SDValue Chain100 = N100.getOperand(0);
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_loadi16_anyext(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
@@ -21655,7 +21679,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v4i32 &&
N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_129(N, X86::PMOVSXBQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_128(N, X86::PMOVSXBQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -21664,24 +21688,24 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 646:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16_anyext>>)))
+ // Pattern: (intrinsic_wo_chain:v2i64 642:iPTR, (bitconvert:v16i8 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16_anyext>>)))
// Emits: (PMOVZXBQrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(646)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(642)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
- SDValue Chain100 = N100.getOperand(0);
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_loadi16_anyext(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
@@ -21690,7 +21714,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v4i32 &&
N100.getValueType() == MVT::i32) {
- SDNode *Result = Emit_129(N, X86::PMOVZXBQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_128(N, X86::PMOVZXBQrm, MVT::v2i64, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -21701,28 +21725,28 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i64 566:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v2i64 562:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PMULUDQrm:v2i64 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(566)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(562)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -21730,7 +21754,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PMULUDQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMULUDQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -21738,23 +21762,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 567:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v2i64 563:iPTR, VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PSADBWrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(567)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(563)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -21762,7 +21786,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PSADBWrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSADBWrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -21770,23 +21794,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 571:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v2i64 567:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PSLLQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(571)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(567)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -21794,7 +21818,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PSLLQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSLLQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -21802,23 +21826,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 583:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v2i64 579:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PSRLQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(583)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(579)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -21826,7 +21850,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_117(N, X86::PSRLQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PSRLQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -21836,28 +21860,28 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i64 626:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v2i64 622:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PCMPEQQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(626)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(622)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -21865,7 +21889,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PCMPEQQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PCMPEQQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -21873,23 +21897,23 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 651:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v2i64 647:iPTR, VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PMULDQrm:v2i64 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(651)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(647)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -21897,7 +21921,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PMULDQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PMULDQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -21907,28 +21931,28 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 671:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v2i64 667:iPTR, VR128:v2i64:$src1, (bitconvert:v2i64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PCMPGTQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
if ((Subtarget->hasSSE42())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(671)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(667)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
@@ -21936,7 +21960,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4) &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_117(N, X86::PCMPGTQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_116(N, X86::PCMPGTQrm, MVT::v2i64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -21946,34 +21970,34 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 733:iPTR, VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:v2i64 729:iPTR, VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$src3)
// Emits: (PALIGNR128rm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2, (BYTE_imm:i8 (imm:i8):$src3))
// Pattern complexity = 33 cost = 1 size = 3
if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(733)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(729)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode()) &&
Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_134(N, X86::PALIGNR128rm, MVT::v2i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_133(N, X86::PALIGNR128rm, MVT::v2i64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -21983,36 +22007,36 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i64 566:iPTR, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
+ // Pattern: (intrinsic_wo_chain:v2i64 562:iPTR, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
// Emits: (PMULUDQrm:v2i64 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(566)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(562)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_118(N, X86::PMULUDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PMULUDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -22021,31 +22045,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 567:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
+ // Pattern: (intrinsic_wo_chain:v2i64 563:iPTR, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v16i8:$src1)
// Emits: (PSADBWrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(567)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(563)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_118(N, X86::PSADBWrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PSADBWrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -22056,36 +22080,36 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i64 626:iPTR, (bitconvert:v2i64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v2i64:$src1)
+ // Pattern: (intrinsic_wo_chain:v2i64 622:iPTR, (bitconvert:v2i64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v2i64:$src1)
// Emits: (PCMPEQQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(626)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(622)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_118(N, X86::PCMPEQQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PCMPEQQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -22094,31 +22118,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 651:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
+ // Pattern: (intrinsic_wo_chain:v2i64 647:iPTR, (bitconvert:v4i32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4i32:$src1)
// Emits: (PMULDQrm:v2i64 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(651)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(647)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_118(N, X86::PMULDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_117(N, X86::PMULDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -22127,19 +22151,19 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 642:iPTR, (bitconvert:v4i32 (X86vzload:v2i64 addr:iPTR:$src)))
+ // Pattern: (intrinsic_wo_chain:v2i64 638:iPTR, (bitconvert:v4i32 (X86vzload:v2i64 addr:iPTR:$src)))
// Emits: (PMOVSXDQrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 32 cost = 1 size = 3
- if (CN1 == INT64_C(642)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(638)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == X86ISD::VZEXT_LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -22147,26 +22171,26 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_131(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_130(N, X86::PMOVSXDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 648:iPTR, (bitconvert:v4i32 (X86vzload:v2i64 addr:iPTR:$src)))
+ // Pattern: (intrinsic_wo_chain:v2i64 644:iPTR, (bitconvert:v4i32 (X86vzload:v2i64 addr:iPTR:$src)))
// Emits: (PMOVZXDQrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 32 cost = 1 size = 3
- if (CN1 == INT64_C(648)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(644)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == X86ISD::VZEXT_LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == X86ISD::VZEXT_LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -22174,7 +22198,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_131(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_130(N, X86::PMOVZXDQrm, MVT::v2i64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -22184,225 +22208,225 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i64 574:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 570:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
// Emits: (PSLLQri:v2i64 VR128:v2i64:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(574)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, X86::PSLLQri, MVT::v2i64);
+ if (CN1 == INT64_C(570)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_127(N, X86::PSLLQri, MVT::v2i64);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 586:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 582:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
// Emits: (PSRLQri:v2i64 VR128:v2i64:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(586)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, X86::PSRLQri, MVT::v2i64);
+ if (CN1 == INT64_C(582)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_127(N, X86::PSRLQri, MVT::v2i64);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 569:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 565:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
// Emits: (PSLLDQri:v2i64 VR128:v16i8:$src1, (BYTE_imm:i32 (imm:i32):$src2))
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(569)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_135(N, X86::PSLLDQri, MVT::v2i64);
+ if (CN1 == INT64_C(565)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_134(N, X86::PSLLDQri, MVT::v2i64);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 581:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 577:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
// Emits: (PSRLDQri:v2i64 VR128:v16i8:$src1, (BYTE_imm:i32 (imm:i32):$src2))
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(581)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_135(N, X86::PSRLDQri, MVT::v2i64);
+ if (CN1 == INT64_C(577)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_134(N, X86::PSRLDQri, MVT::v2i64);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 570:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 566:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
// Emits: (PSLLDQri:v2i64 VR128:v16i8:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(570)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, X86::PSLLDQri, MVT::v2i64);
+ if (CN1 == INT64_C(566)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_127(N, X86::PSLLDQri, MVT::v2i64);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 582:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 578:iPTR, VR128:v2i64:$src1, (imm:i32):$src2)
// Emits: (PSRLDQri:v2i64 VR128:v16i8:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(582)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, X86::PSRLDQri, MVT::v2i64);
+ if (CN1 == INT64_C(578)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_127(N, X86::PSRLDQri, MVT::v2i64);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 733:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2, (imm:i8):$src3)
+ // Pattern: (intrinsic_wo_chain:v2i64 729:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2, (imm:i8):$src3)
// Emits: (PALIGNR128rr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2, (BYTE_imm:i8 (imm:i8):$src3))
// Pattern complexity = 11 cost = 1 size = 3
if ((Subtarget->hasSSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(733)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_133(N, X86::PALIGNR128rr, MVT::v2i64);
+ if (CN1 == INT64_C(729)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_132(N, X86::PALIGNR128rr, MVT::v2i64);
return Result;
}
}
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i64 566:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 562:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PMULUDQrr:v2i64 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(566)) {
- SDNode *Result = Emit_111(N, X86::PMULUDQrr, MVT::v2i64);
+ if (CN1 == INT64_C(562)) {
+ SDNode *Result = Emit_110(N, X86::PMULUDQrr, MVT::v2i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i64 567:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 563:iPTR, VR128:v16i8:$src1, VR128:v16i8:$src2)
// Emits: (PSADBWrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(567)) {
- SDNode *Result = Emit_111(N, X86::PSADBWrr, MVT::v2i64);
+ if (CN1 == INT64_C(563)) {
+ SDNode *Result = Emit_110(N, X86::PSADBWrr, MVT::v2i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i64 571:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 567:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
// Emits: (PSLLQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(571)) {
- SDNode *Result = Emit_111(N, X86::PSLLQrr, MVT::v2i64);
+ if (CN1 == INT64_C(567)) {
+ SDNode *Result = Emit_110(N, X86::PSLLQrr, MVT::v2i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i64 583:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 579:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
// Emits: (PSRLQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(583)) {
- SDNode *Result = Emit_111(N, X86::PSRLQrr, MVT::v2i64);
+ if (CN1 == INT64_C(579)) {
+ SDNode *Result = Emit_110(N, X86::PSRLQrr, MVT::v2i64);
return Result;
}
}
}
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2i64 626:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 622:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
// Emits: (PCMPEQQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(626)) {
- SDNode *Result = Emit_111(N, X86::PCMPEQQrr, MVT::v2i64);
+ if (CN1 == INT64_C(622)) {
+ SDNode *Result = Emit_110(N, X86::PCMPEQQrr, MVT::v2i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i64 651:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 647:iPTR, VR128:v4i32:$src1, VR128:v4i32:$src2)
// Emits: (PMULDQrr:v2i64 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(651)) {
- SDNode *Result = Emit_111(N, X86::PMULDQrr, MVT::v2i64);
+ if (CN1 == INT64_C(647)) {
+ SDNode *Result = Emit_110(N, X86::PMULDQrr, MVT::v2i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i64 642:iPTR, VR128:v4i32:$src)
+ // Pattern: (intrinsic_wo_chain:v2i64 638:iPTR, VR128:v4i32:$src)
// Emits: (PMOVSXDQrr:v2i64 VR128:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(642)) {
- SDNode *Result = Emit_108(N, X86::PMOVSXDQrr, MVT::v2i64);
+ if (CN1 == INT64_C(638)) {
+ SDNode *Result = Emit_107(N, X86::PMOVSXDQrr, MVT::v2i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i64 648:iPTR, VR128:v4i32:$src)
+ // Pattern: (intrinsic_wo_chain:v2i64 644:iPTR, VR128:v4i32:$src)
// Emits: (PMOVZXDQrr:v2i64 VR128:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(648)) {
- SDNode *Result = Emit_108(N, X86::PMOVZXDQrr, MVT::v2i64);
+ if (CN1 == INT64_C(644)) {
+ SDNode *Result = Emit_107(N, X86::PMOVZXDQrr, MVT::v2i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i64 644:iPTR, VR128:v8i16:$src)
+ // Pattern: (intrinsic_wo_chain:v2i64 640:iPTR, VR128:v8i16:$src)
// Emits: (PMOVSXWQrr:v2i64 VR128:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(644)) {
- SDNode *Result = Emit_108(N, X86::PMOVSXWQrr, MVT::v2i64);
+ if (CN1 == INT64_C(640)) {
+ SDNode *Result = Emit_107(N, X86::PMOVSXWQrr, MVT::v2i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i64 650:iPTR, VR128:v8i16:$src)
+ // Pattern: (intrinsic_wo_chain:v2i64 646:iPTR, VR128:v8i16:$src)
// Emits: (PMOVZXWQrr:v2i64 VR128:v8i16:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(650)) {
- SDNode *Result = Emit_108(N, X86::PMOVZXWQrr, MVT::v2i64);
+ if (CN1 == INT64_C(646)) {
+ SDNode *Result = Emit_107(N, X86::PMOVZXWQrr, MVT::v2i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i64 640:iPTR, VR128:v16i8:$src)
+ // Pattern: (intrinsic_wo_chain:v2i64 636:iPTR, VR128:v16i8:$src)
// Emits: (PMOVSXBQrr:v2i64 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(640)) {
- SDNode *Result = Emit_108(N, X86::PMOVSXBQrr, MVT::v2i64);
+ if (CN1 == INT64_C(636)) {
+ SDNode *Result = Emit_107(N, X86::PMOVSXBQrr, MVT::v2i64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2i64 646:iPTR, VR128:v16i8:$src)
+ // Pattern: (intrinsic_wo_chain:v2i64 642:iPTR, VR128:v16i8:$src)
// Emits: (PMOVZXBQrr:v2i64 VR128:v16i8:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(646)) {
- SDNode *Result = Emit_108(N, X86::PMOVZXBQrr, MVT::v2i64);
+ if (CN1 == INT64_C(642)) {
+ SDNode *Result = Emit_107(N, X86::PMOVZXBQrr, MVT::v2i64);
return Result;
}
}
}
- // Pattern: (intrinsic_wo_chain:v2i64 671:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2i64 667:iPTR, VR128:v2i64:$src1, VR128:v2i64:$src2)
// Emits: (PCMPGTQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if ((Subtarget->hasSSE42())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(671)) {
- SDNode *Result = Emit_111(N, X86::PCMPGTQrr, MVT::v2i64);
+ if (CN1 == INT64_C(667)) {
+ SDNode *Result = Emit_110(N, X86::PCMPGTQrr, MVT::v2i64);
return Result;
}
}
@@ -22412,84 +22436,84 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_136(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPInChain, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4, SDValue &Chain2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_135(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPInChain, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4, SDValue &Chain2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
ReplaceUses(SDValue(CPInChain.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_137(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPInChain, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4, SDValue &Chain1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_136(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPInChain, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4, SDValue &Chain1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
ReplaceUses(SDValue(CPInChain.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_138(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_137(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Tmp3, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_139(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPInChain, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4, SDValue &Chain2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_138(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPInChain, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4, SDValue &Chain2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue Tmp4 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i32);
SDValue Ops0[] = { N1, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp4, Chain2 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
ReplaceUses(SDValue(CPInChain.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 614:iPTR, VR128:v4f32:$src1, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v4f32 610:iPTR, VR128:v4f32:$src1, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
// Emits: (BLENDPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
// Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(614)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(610)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
SDValue CPTmpN201_3;
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant &&
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_120(N, X86::BLENDPSrmi, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_119(N, X86::BLENDPSrmi, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -22497,35 +22521,35 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
}
}
}
- if (CN1 == INT64_C(618)) {
- SDValue N1 = N.getOperand(1);
+ if (CN1 == INT64_C(614)) {
+ SDValue N1 = N->getOperand(1);
- // Pattern: (intrinsic_wo_chain:v4f32 618:iPTR, VR128:v4f32:$src1, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v4f32 614:iPTR, VR128:v4f32:$src1, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
// Emits: (DPPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
// Pattern complexity = 36 cost = 1 size = 3
{
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
SDValue CPTmpN201_3;
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant &&
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_120(N, X86::DPPSrmi, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_119(N, X86::DPPSrmi, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -22534,31 +22558,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 618:iPTR, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4f32:$src1, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v4f32 614:iPTR, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v4f32:$src1, (imm:i32):$src3)
// Emits: (DPPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
// Pattern complexity = 36 cost = 1 size = 3
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant &&
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_127(N, X86::DPPSrmi, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_126(N, X86::DPPSrmi, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -22569,33 +22593,33 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 681:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$cc)
+ // Pattern: (intrinsic_wo_chain:v4f32 677:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$cc)
// Emits: (Int_CMPSSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src, (imm:i8):$cc)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(681)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(677)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_124(N, X86::Int_CMPSSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_123(N, X86::Int_CMPSSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -22603,29 +22627,29 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 680:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$cc)
+ // Pattern: (intrinsic_wo_chain:v4f32 676:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$cc)
// Emits: (CMPPSrmi:v4f32 VR128:v4f32:$src1, addr:iPTR:$src, (imm:i8):$cc)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(680)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(676)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode()) &&
Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_124(N, X86::CMPPSrmi, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_123(N, X86::CMPPSrmi, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -22635,27 +22659,27 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 513:iPTR, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v4f32 509:iPTR, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (Int_CVTDQ2PSrm:v4f32 addr:iPTR:$src)
// Pattern complexity = 33 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(513)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(509)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -22663,7 +22687,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::Int_CVTDQ2PSrm, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_115(N, X86::Int_CVTDQ2PSrm, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -22673,33 +22697,33 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 657:iPTR, (ld:v4f32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 653:iPTR, (ld:v4f32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i32):$src2)
// Emits: (ROUNDPSm_Int:v4f32 addr:iPTR:$src1, (imm:i32):$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(657)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(653)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_138(N, X86::ROUNDPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_137(N, X86::ROUNDPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -22707,32 +22731,32 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 616:iPTR, VR128:v4f32:$src1, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), XMM0:v4f32)
+ // Pattern: (intrinsic_wo_chain:v4f32 612:iPTR, VR128:v4f32:$src1, (bitconvert:v4f32 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), XMM0:v4f32)
// Emits: (BLENDVPSrm0:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(616)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(612)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
SDValue CPTmpN201_3;
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N.getOperand(3);
+ SDValue N3 = N->getOperand(3);
if (N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_122(N, X86::BLENDVPSrm0, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_121(N, X86::BLENDVPSrm0, MVT::v4f32, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -22743,216 +22767,216 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 693:iPTR, VR128:v4f32:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Pattern: (intrinsic_wo_chain:v4f32 689:iPTR, VR128:v4f32:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
// Emits: (Int_CVTSI2SS64rm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(693)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(689)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode()) &&
Predicate_loadi64(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::Int_CVTSI2SS64rm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTSI2SS64rm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 690:iPTR, VR128:v4f32:$src1, (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Pattern: (intrinsic_wo_chain:v4f32 686:iPTR, VR128:v4f32:$src1, (ld:v2i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (Int_CVTPI2PSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(690)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(686)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::Int_CVTPI2PSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTPI2PSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 692:iPTR, VR128:v4f32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Pattern: (intrinsic_wo_chain:v4f32 688:iPTR, VR128:v4f32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
// Emits: (Int_CVTSI2SSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(692)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(688)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_loadi32(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::Int_CVTSI2SSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTSI2SSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 703:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v4f32 699:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (MAXPSrm_Int:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(703)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(699)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode()) &&
Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::MAXPSrm_Int, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::MAXPSrm_Int, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 705:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v4f32 701:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (MINPSrm_Int:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(705)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(701)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode()) &&
Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::MINPSrm_Int, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::MINPSrm_Int, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 715:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v4f32 711:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (SQRTPSm_Int:v4f32 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(715)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(711)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::SQRTPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::SQRTPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 712:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v4f32 708:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (RSQRTPSm_Int:v4f32 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(712)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(708)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::RSQRTPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::RSQRTPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 710:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v4f32 706:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (RCPPSm_Int:v4f32 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(710)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(706)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::RCPPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::RCPPSm_Int, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -22961,57 +22985,57 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 515:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v4f32 511:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (Int_CVTPD2PSrm:v4f32 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(515)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(511)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTPD2PSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::Int_CVTPD2PSrm, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 520:iPTR, VR128:v4f32:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Pattern: (intrinsic_wo_chain:v4f32 516:iPTR, VR128:v4f32:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (Int_CVTSD2SSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(520)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(516)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::Int_CVTSD2SSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTSD2SSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -23020,86 +23044,86 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 605:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v4f32 601:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (ADDSUBPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(605)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(601)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode()) &&
Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::ADDSUBPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::ADDSUBPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 607:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v4f32 603:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (HADDPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(607)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(603)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode()) &&
Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::HADDPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::HADDPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 609:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v4f32 605:iPTR, VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (HSUBPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(609)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(605)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode()) &&
Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::HSUBPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::HSUBPSrm, MVT::v4f32, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -23108,17 +23132,17 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 659:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v4f32 655:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2, (imm:i32):$src3)
// Emits: (ROUNDSSm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2, (imm:i32):$src3)
// Pattern complexity = 29 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(659)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(655)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -23126,10 +23150,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN2_4;
SDValue CPInChain;
SDValue Chain2;
- if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_139(N, X86::ROUNDSSm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_138(N, X86::ROUNDSSm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
@@ -23137,17 +23161,17 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 679:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 675:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
// Emits: (ADDSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(679)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(675)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -23155,18 +23179,18 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN2_4;
SDValue CPInChain;
SDValue Chain2;
- if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_136(N, X86::ADDSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::ADDSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 709:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 705:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
// Emits: (MULSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(709)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(705)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -23174,18 +23198,18 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN2_4;
SDValue CPInChain;
SDValue Chain2;
- if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_136(N, X86::MULSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::MULSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 719:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 715:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
// Emits: (SUBSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(719)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(715)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -23193,18 +23217,18 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN2_4;
SDValue CPInChain;
SDValue Chain2;
- if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_136(N, X86::SUBSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::SUBSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 700:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 696:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
// Emits: (DIVSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(700)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(696)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -23212,18 +23236,18 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN2_4;
SDValue CPInChain;
SDValue Chain2;
- if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_136(N, X86::DIVSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::DIVSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 704:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 700:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
// Emits: (MAXSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(704)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(700)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -23231,18 +23255,18 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN2_4;
SDValue CPInChain;
SDValue Chain2;
- if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_136(N, X86::MAXSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::MAXSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 706:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 702:iPTR, VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
// Emits: (MINSSrm_Int:v4f32 VR128:v4f32:$src1, sse_load_f32:v4f32:$src2)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(706)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(702)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -23250,17 +23274,17 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN2_4;
SDValue CPInChain;
SDValue Chain2;
- if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_136(N, X86::MINSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::MINSSrm_Int, MVT::v4f32, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 716:iPTR, sse_load_f32:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v4f32 712:iPTR, sse_load_f32:v4f32:$src)
// Emits: (SQRTSSm_Int:v4f32 sse_load_f32:v4f32:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(716)) {
- SDValue N1 = N.getOperand(1);
+ if (CN1 == INT64_C(712)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -23268,17 +23292,17 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN1_4;
SDValue CPInChain;
SDValue Chain1;
- if (SelectScalarSSELoad(N, N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
- SDNode *Result = Emit_137(N, X86::SQRTSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
+ SDNode *Result = Emit_136(N, X86::SQRTSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 713:iPTR, sse_load_f32:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v4f32 709:iPTR, sse_load_f32:v4f32:$src)
// Emits: (RSQRTSSm_Int:v4f32 sse_load_f32:v4f32:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(713)) {
- SDValue N1 = N.getOperand(1);
+ if (CN1 == INT64_C(709)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -23286,17 +23310,17 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN1_4;
SDValue CPInChain;
SDValue Chain1;
- if (SelectScalarSSELoad(N, N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
- SDNode *Result = Emit_137(N, X86::RSQRTSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
+ SDNode *Result = Emit_136(N, X86::RSQRTSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 711:iPTR, sse_load_f32:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v4f32 707:iPTR, sse_load_f32:v4f32:$src)
// Emits: (RCPSSm_Int:v4f32 sse_load_f32:v4f32:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(711)) {
- SDValue N1 = N.getOperand(1);
+ if (CN1 == INT64_C(707)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -23304,8 +23328,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
SDValue CPTmpN1_4;
SDValue CPInChain;
SDValue Chain1;
- if (SelectScalarSSELoad(N, N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
- SDNode *Result = Emit_137(N, X86::RCPSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
+ SDNode *Result = Emit_136(N, X86::RCPSSm_Int, MVT::v4f32, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
return Result;
}
}
@@ -23313,332 +23337,332 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 681:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src, (imm:i8):$cc)
+ // Pattern: (intrinsic_wo_chain:v4f32 677:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src, (imm:i8):$cc)
// Emits: (Int_CMPSSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src, (imm:i8):$cc)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(681)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_123(N, X86::Int_CMPSSrr, MVT::v4f32);
+ if (CN1 == INT64_C(677)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_122(N, X86::Int_CMPSSrr, MVT::v4f32);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 680:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src, (imm:i8):$cc)
+ // Pattern: (intrinsic_wo_chain:v4f32 676:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src, (imm:i8):$cc)
// Emits: (CMPPSrri:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src, (imm:i8):$cc)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(680)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_123(N, X86::CMPPSrri, MVT::v4f32);
+ if (CN1 == INT64_C(676)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_122(N, X86::CMPPSrri, MVT::v4f32);
return Result;
}
}
}
}
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 657:iPTR, VR128:v4f32:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 653:iPTR, VR128:v4f32:$src1, (imm:i32):$src2)
// Emits: (ROUNDPSr_Int:v4f32 VR128:v4f32:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(657)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, X86::ROUNDPSr_Int, MVT::v4f32);
+ if (CN1 == INT64_C(653)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_127(N, X86::ROUNDPSr_Int, MVT::v4f32);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 659:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v4f32 655:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
// Emits: (ROUNDSSr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(659)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_119(N, X86::ROUNDSSr_Int, MVT::v4f32);
+ if (CN1 == INT64_C(655)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_118(N, X86::ROUNDSSr_Int, MVT::v4f32);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 614:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v4f32 610:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
// Emits: (BLENDPSrri:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(614)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_119(N, X86::BLENDPSrri, MVT::v4f32);
+ if (CN1 == INT64_C(610)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_118(N, X86::BLENDPSrri, MVT::v4f32);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 618:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v4f32 614:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
// Emits: (DPPSrri:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(618)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_119(N, X86::DPPSrri, MVT::v4f32);
+ if (CN1 == INT64_C(614)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_118(N, X86::DPPSrri, MVT::v4f32);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 620:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v4f32 616:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
// Emits: (INSERTPSrr:v4f32 VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i32):$src3)
// Pattern complexity = 11 cost = 1 size = 3
{
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(620)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_119(N, X86::INSERTPSrr, MVT::v4f32);
+ if (CN1 == INT64_C(616)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_118(N, X86::INSERTPSrr, MVT::v4f32);
return Result;
}
}
}
}
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 693:iPTR, VR128:v4f32:$src1, GR64:i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 689:iPTR, VR128:v4f32:$src1, GR64:i64:$src2)
// Emits: (Int_CVTSI2SS64rr:v4f32 VR128:v4f32:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(693)) {
- SDNode *Result = Emit_111(N, X86::Int_CVTSI2SS64rr, MVT::v4f32);
+ if (CN1 == INT64_C(689)) {
+ SDNode *Result = Emit_110(N, X86::Int_CVTSI2SS64rr, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 690:iPTR, VR128:v4f32:$src1, VR64:v2i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 686:iPTR, VR128:v4f32:$src1, VR64:v2i32:$src2)
// Emits: (Int_CVTPI2PSrr:v4f32 VR128:v4f32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(690)) {
- SDNode *Result = Emit_111(N, X86::Int_CVTPI2PSrr, MVT::v4f32);
+ if (CN1 == INT64_C(686)) {
+ SDNode *Result = Emit_110(N, X86::Int_CVTPI2PSrr, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 692:iPTR, VR128:v4f32:$src1, GR32:i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 688:iPTR, VR128:v4f32:$src1, GR32:i32:$src2)
// Emits: (Int_CVTSI2SSrr:v4f32 VR128:v4f32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(692)) {
- SDNode *Result = Emit_111(N, X86::Int_CVTSI2SSrr, MVT::v4f32);
+ if (CN1 == INT64_C(688)) {
+ SDNode *Result = Emit_110(N, X86::Int_CVTSI2SSrr, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 679:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 675:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (ADDSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(679)) {
- SDNode *Result = Emit_111(N, X86::ADDSSrr_Int, MVT::v4f32);
+ if (CN1 == INT64_C(675)) {
+ SDNode *Result = Emit_110(N, X86::ADDSSrr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 709:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 705:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (MULSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(709)) {
- SDNode *Result = Emit_111(N, X86::MULSSrr_Int, MVT::v4f32);
+ if (CN1 == INT64_C(705)) {
+ SDNode *Result = Emit_110(N, X86::MULSSrr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 719:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 715:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (SUBSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(719)) {
- SDNode *Result = Emit_111(N, X86::SUBSSrr_Int, MVT::v4f32);
+ if (CN1 == INT64_C(715)) {
+ SDNode *Result = Emit_110(N, X86::SUBSSrr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 700:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 696:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (DIVSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(700)) {
- SDNode *Result = Emit_111(N, X86::DIVSSrr_Int, MVT::v4f32);
+ if (CN1 == INT64_C(696)) {
+ SDNode *Result = Emit_110(N, X86::DIVSSrr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 704:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 700:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (MAXSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(704)) {
- SDNode *Result = Emit_111(N, X86::MAXSSrr_Int, MVT::v4f32);
+ if (CN1 == INT64_C(700)) {
+ SDNode *Result = Emit_110(N, X86::MAXSSrr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 703:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 699:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (MAXPSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(703)) {
- SDNode *Result = Emit_111(N, X86::MAXPSrr_Int, MVT::v4f32);
+ if (CN1 == INT64_C(699)) {
+ SDNode *Result = Emit_110(N, X86::MAXPSrr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 706:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 702:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (MINSSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(706)) {
- SDNode *Result = Emit_111(N, X86::MINSSrr_Int, MVT::v4f32);
+ if (CN1 == INT64_C(702)) {
+ SDNode *Result = Emit_110(N, X86::MINSSrr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 705:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 701:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (MINPSrr_Int:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(705)) {
- SDNode *Result = Emit_111(N, X86::MINPSrr_Int, MVT::v4f32);
+ if (CN1 == INT64_C(701)) {
+ SDNode *Result = Emit_110(N, X86::MINPSrr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 716:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v4f32 712:iPTR, VR128:v4f32:$src)
// Emits: (SQRTSSr_Int:v4f32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(716)) {
- SDNode *Result = Emit_108(N, X86::SQRTSSr_Int, MVT::v4f32);
+ if (CN1 == INT64_C(712)) {
+ SDNode *Result = Emit_107(N, X86::SQRTSSr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 715:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v4f32 711:iPTR, VR128:v4f32:$src)
// Emits: (SQRTPSr_Int:v4f32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(715)) {
- SDNode *Result = Emit_108(N, X86::SQRTPSr_Int, MVT::v4f32);
+ if (CN1 == INT64_C(711)) {
+ SDNode *Result = Emit_107(N, X86::SQRTPSr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 713:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v4f32 709:iPTR, VR128:v4f32:$src)
// Emits: (RSQRTSSr_Int:v4f32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(713)) {
- SDNode *Result = Emit_108(N, X86::RSQRTSSr_Int, MVT::v4f32);
+ if (CN1 == INT64_C(709)) {
+ SDNode *Result = Emit_107(N, X86::RSQRTSSr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 712:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v4f32 708:iPTR, VR128:v4f32:$src)
// Emits: (RSQRTPSr_Int:v4f32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(712)) {
- SDNode *Result = Emit_108(N, X86::RSQRTPSr_Int, MVT::v4f32);
+ if (CN1 == INT64_C(708)) {
+ SDNode *Result = Emit_107(N, X86::RSQRTPSr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 711:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v4f32 707:iPTR, VR128:v4f32:$src)
// Emits: (RCPSSr_Int:v4f32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(711)) {
- SDNode *Result = Emit_108(N, X86::RCPSSr_Int, MVT::v4f32);
+ if (CN1 == INT64_C(707)) {
+ SDNode *Result = Emit_107(N, X86::RCPSSr_Int, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 710:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v4f32 706:iPTR, VR128:v4f32:$src)
// Emits: (RCPPSr_Int:v4f32 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(710)) {
- SDNode *Result = Emit_108(N, X86::RCPPSr_Int, MVT::v4f32);
+ if (CN1 == INT64_C(706)) {
+ SDNode *Result = Emit_107(N, X86::RCPPSr_Int, MVT::v4f32);
return Result;
}
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 513:iPTR, VR128:v4i32:$src)
+ // Pattern: (intrinsic_wo_chain:v4f32 509:iPTR, VR128:v4i32:$src)
// Emits: (Int_CVTDQ2PSrr:v4f32 VR128:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(513)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTDQ2PSrr, MVT::v4f32);
+ if (CN1 == INT64_C(509)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTDQ2PSrr, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 515:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:v4f32 511:iPTR, VR128:v2f64:$src)
// Emits: (Int_CVTPD2PSrr:v4f32 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(515)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPD2PSrr, MVT::v4f32);
+ if (CN1 == INT64_C(511)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTPD2PSrr, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 520:iPTR, VR128:v4f32:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 516:iPTR, VR128:v4f32:$src1, VR128:v2f64:$src2)
// Emits: (Int_CVTSD2SSrr:v4f32 VR128:v4f32:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(520)) {
- SDNode *Result = Emit_111(N, X86::Int_CVTSD2SSrr, MVT::v4f32);
+ if (CN1 == INT64_C(516)) {
+ SDNode *Result = Emit_110(N, X86::Int_CVTSD2SSrr, MVT::v4f32);
return Result;
}
}
}
if ((Subtarget->hasSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v4f32 605:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 601:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (ADDSUBPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(605)) {
- SDNode *Result = Emit_111(N, X86::ADDSUBPSrr, MVT::v4f32);
+ if (CN1 == INT64_C(601)) {
+ SDNode *Result = Emit_110(N, X86::ADDSUBPSrr, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 607:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 603:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (HADDPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(607)) {
- SDNode *Result = Emit_111(N, X86::HADDPSrr, MVT::v4f32);
+ if (CN1 == INT64_C(603)) {
+ SDNode *Result = Emit_110(N, X86::HADDPSrr, MVT::v4f32);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v4f32 609:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v4f32 605:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2)
// Emits: (HSUBPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(609)) {
- SDNode *Result = Emit_111(N, X86::HSUBPSrr, MVT::v4f32);
+ if (CN1 == INT64_C(605)) {
+ SDNode *Result = Emit_110(N, X86::HSUBPSrr, MVT::v4f32);
return Result;
}
}
}
- // Pattern: (intrinsic_wo_chain:v4f32 616:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, XMM0:v4f32)
+ // Pattern: (intrinsic_wo_chain:v4f32 612:iPTR, VR128:v4f32:$src1, VR128:v4f32:$src2, XMM0:v4f32)
// Emits: (BLENDVPSrr0:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(616)) {
- SDNode *Result = Emit_121(N, X86::BLENDVPSrr0, MVT::v4f32);
+ if (CN1 == INT64_C(612)) {
+ SDNode *Result = Emit_120(N, X86::BLENDVPSrr0, MVT::v4f32);
return Result;
}
}
@@ -23648,41 +23672,41 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2f64 613:iPTR, VR128:v2f64:$src1, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v2f64 609:iPTR, VR128:v2f64:$src1, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
// Emits: (BLENDPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2, (imm:i32):$src3)
// Pattern complexity = 36 cost = 1 size = 3
- if (CN1 == INT64_C(613)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(609)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
SDValue CPTmpN201_3;
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant &&
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_120(N, X86::BLENDPDrmi, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_119(N, X86::BLENDPDrmi, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -23690,35 +23714,35 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
}
}
}
- if (CN1 == INT64_C(617)) {
- SDValue N1 = N.getOperand(1);
+ if (CN1 == INT64_C(613)) {
+ SDValue N1 = N->getOperand(1);
- // Pattern: (intrinsic_wo_chain:v2f64 617:iPTR, VR128:v2f64:$src1, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v2f64 613:iPTR, VR128:v2f64:$src1, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (imm:i32):$src3)
// Emits: (DPPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2, (imm:i32):$src3)
// Pattern complexity = 36 cost = 1 size = 3
{
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
SDValue CPTmpN201_3;
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant &&
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant &&
N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_120(N, X86::DPPDrmi, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_119(N, X86::DPPDrmi, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -23727,31 +23751,31 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 617:iPTR, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v2f64:$src1, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v2f64 613:iPTR, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v2f64:$src1, (imm:i32):$src3)
// Emits: (DPPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2, (imm:i32):$src3)
// Pattern complexity = 36 cost = 1 size = 3
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant &&
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_127(N, X86::DPPDrmi, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_126(N, X86::DPPDrmi, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -23762,33 +23786,33 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2f64 505:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$cc)
+ // Pattern: (intrinsic_wo_chain:v2f64 501:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$cc)
// Emits: (Int_CMPSDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src, (imm:i8):$cc)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(505)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(501)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_124(N, X86::Int_CMPSDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_123(N, X86::Int_CMPSDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -23796,22 +23820,22 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 512:iPTR, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
+ // Pattern: (intrinsic_wo_chain:v2f64 508:iPTR, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (Int_CVTDQ2PDrm:v2f64 addr:iPTR:$src)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(512)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(508)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -23819,7 +23843,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_116(N, X86::Int_CVTDQ2PDrm, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_115(N, X86::Int_CVTDQ2PDrm, MVT::v2f64, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -23827,29 +23851,29 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 504:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$cc)
+ // Pattern: (intrinsic_wo_chain:v2f64 500:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$cc)
// Emits: (CMPPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src, (imm:i8):$cc)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(504)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(500)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode()) &&
Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_124(N, X86::CMPPDrmi, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_123(N, X86::CMPPDrmi, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -23859,33 +23883,33 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2f64 656:iPTR, (ld:v2f64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 652:iPTR, (ld:v2f64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i32):$src2)
// Emits: (ROUNDPDm_Int:v2f64 addr:iPTR:$src1, (imm:i32):$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(656)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(652)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_138(N, X86::ROUNDPDm_Int, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_137(N, X86::ROUNDPDm_Int, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -23893,32 +23917,32 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 615:iPTR, VR128:v2f64:$src1, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), XMM0:v2f64)
+ // Pattern: (intrinsic_wo_chain:v2f64 611:iPTR, VR128:v2f64:$src1, (bitconvert:v2f64 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), XMM0:v2f64)
// Emits: (BLENDVPDrm0:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
- if (CN1 == INT64_C(615)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::BIT_CONVERT &&
+ if (CN1 == INT64_C(611)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N2.hasOneUse()) {
- SDValue N20 = N2.getOperand(0);
- if (N20.getOpcode() == ISD::LOAD &&
+ SDValue N20 = N2.getNode()->getOperand(0);
+ if (N20.getNode()->getOpcode() == ISD::LOAD &&
N20.hasOneUse() &&
- IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N.getNode())) {
- SDValue Chain20 = N20.getOperand(0);
+ IsLegalAndProfitableToFold(N20.getNode(), N2.getNode(), N)) {
+ SDValue Chain20 = N20.getNode()->getOperand(0);
if (Predicate_unindexedload(N20.getNode()) &&
Predicate_load(N20.getNode()) &&
Predicate_memop(N20.getNode())) {
- SDValue N201 = N20.getOperand(1);
+ SDValue N201 = N20.getNode()->getOperand(1);
SDValue CPTmpN201_0;
SDValue CPTmpN201_1;
SDValue CPTmpN201_2;
SDValue CPTmpN201_3;
SDValue CPTmpN201_4;
if (SelectAddr(N, N201, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4)) {
- SDValue N3 = N.getOperand(3);
+ SDValue N3 = N->getOperand(3);
if (N20.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_122(N, X86::BLENDVPDrm0, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
+ SDNode *Result = Emit_121(N, X86::BLENDVPDrm0, MVT::v2f64, CPTmpN201_0, CPTmpN201_1, CPTmpN201_2, CPTmpN201_3, CPTmpN201_4);
return Result;
}
}
@@ -23929,214 +23953,214 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2f64 522:iPTR, VR128:v2f64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Pattern: (intrinsic_wo_chain:v2f64 518:iPTR, VR128:v2f64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
// Emits: (Int_CVTSI2SD64rm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(522)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(518)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode()) &&
Predicate_loadi64(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::Int_CVTSI2SD64rm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTSI2SD64rm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 689:iPTR, (ld:v2i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Pattern: (intrinsic_wo_chain:v2f64 685:iPTR, (ld:v2i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (Int_CVTPI2PDrm:v2f64 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(689)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(685)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTPI2PDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::Int_CVTPI2PDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 533:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v2f64 529:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (MAXPDrm_Int:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(533)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(529)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode()) &&
Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::MAXPDrm_Int, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::MAXPDrm_Int, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 536:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v2f64 532:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (MINPDrm_Int:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(536)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(532)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode()) &&
Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::MINPDrm_Int, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::MINPDrm_Int, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 517:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Pattern: (intrinsic_wo_chain:v2f64 513:iPTR, (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (Int_CVTPS2PDrm:v2f64 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(517)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(513)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::Int_CVTPS2PDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::Int_CVTPS2PDrm, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 521:iPTR, VR128:v2f64:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Pattern: (intrinsic_wo_chain:v2f64 517:iPTR, VR128:v2f64:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
// Emits: (Int_CVTSI2SDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(521)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(517)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_loadi32(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::Int_CVTSI2SDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTSI2SDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 523:iPTR, VR128:v2f64:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Pattern: (intrinsic_wo_chain:v2f64 519:iPTR, VR128:v2f64:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (Int_CVTSS2SDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(523)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(519)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::Int_CVTSS2SDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::Int_CVTSS2SDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 592:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v2f64 588:iPTR, (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (SQRTPDm_Int:v2f64 addr:iPTR:$src)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(592)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(588)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_109(N, X86::SQRTPDm_Int, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_108(N, X86::SQRTPDm_Int, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -24145,86 +24169,86 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2f64 604:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v2f64 600:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (ADDSUBPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(604)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(600)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode()) &&
Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::ADDSUBPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::ADDSUBPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 606:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v2f64 602:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (HADDPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(606)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(602)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode()) &&
Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::HADDPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::HADDPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 608:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
+ // Pattern: (intrinsic_wo_chain:v2f64 604:iPTR, VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (HSUBPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(608)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::LOAD &&
+ if (CN1 == INT64_C(604)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::LOAD &&
N2.hasOneUse() &&
- IsLegalAndProfitableToFold(N2.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain2 = N2.getOperand(0);
+ IsLegalAndProfitableToFold(N2.getNode(), N, N)) {
+ SDValue Chain2 = N2.getNode()->getOperand(0);
if (Predicate_unindexedload(N2.getNode()) &&
Predicate_load(N2.getNode()) &&
Predicate_memop(N2.getNode())) {
- SDValue N21 = N2.getOperand(1);
+ SDValue N21 = N2.getNode()->getOperand(1);
SDValue CPTmpN21_0;
SDValue CPTmpN21_1;
SDValue CPTmpN21_2;
SDValue CPTmpN21_3;
SDValue CPTmpN21_4;
if (SelectAddr(N, N21, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4)) {
- SDNode *Result = Emit_110(N, X86::HSUBPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
+ SDNode *Result = Emit_109(N, X86::HSUBPDrm, MVT::v2f64, CPTmpN21_0, CPTmpN21_1, CPTmpN21_2, CPTmpN21_3, CPTmpN21_4);
return Result;
}
}
@@ -24233,17 +24257,17 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 658:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v2f64 654:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2, (imm:i32):$src3)
// Emits: (ROUNDSDm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2, (imm:i32):$src3)
// Pattern complexity = 29 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(658)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(654)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -24251,10 +24275,10 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN2_4;
SDValue CPInChain;
SDValue Chain2;
- if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_139(N, X86::ROUNDSDm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_138(N, X86::ROUNDSDm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
@@ -24262,17 +24286,17 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2f64 502:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 498:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
// Emits: (ADDSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(502)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(498)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -24280,18 +24304,18 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN2_4;
SDValue CPInChain;
SDValue Chain2;
- if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_136(N, X86::ADDSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::ADDSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 542:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 538:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
// Emits: (MULSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(542)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(538)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -24299,18 +24323,18 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN2_4;
SDValue CPInChain;
SDValue Chain2;
- if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_136(N, X86::MULSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::MULSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 597:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 593:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
// Emits: (SUBSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(597)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(593)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -24318,18 +24342,18 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN2_4;
SDValue CPInChain;
SDValue Chain2;
- if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_136(N, X86::SUBSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::SUBSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 528:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 524:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
// Emits: (DIVSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(528)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(524)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -24337,18 +24361,18 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN2_4;
SDValue CPInChain;
SDValue Chain2;
- if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_136(N, X86::DIVSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::DIVSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 534:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 530:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
// Emits: (MAXSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(534)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(530)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -24356,18 +24380,18 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN2_4;
SDValue CPInChain;
SDValue Chain2;
- if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_136(N, X86::MAXSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::MAXSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 537:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 533:iPTR, VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
// Emits: (MINSDrm_Int:v2f64 VR128:v2f64:$src1, sse_load_f64:v2f64:$src2)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(537)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(533)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -24375,17 +24399,17 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN2_4;
SDValue CPInChain;
SDValue Chain2;
- if (SelectScalarSSELoad(N, N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
- SDNode *Result = Emit_136(N, X86::MINSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, CPInChain, Chain2)) {
+ SDNode *Result = Emit_135(N, X86::MINSDrm_Int, MVT::v2f64, CPInChain, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain2);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 593:iPTR, sse_load_f64:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:v2f64 589:iPTR, sse_load_f64:v2f64:$src)
// Emits: (SQRTSDm_Int:v2f64 sse_load_f64:v2f64:$src)
// Pattern complexity = 26 cost = 1 size = 3
- if (CN1 == INT64_C(593)) {
- SDValue N1 = N.getOperand(1);
+ if (CN1 == INT64_C(589)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
@@ -24393,8 +24417,8 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
SDValue CPTmpN1_4;
SDValue CPInChain;
SDValue Chain1;
- if (SelectScalarSSELoad(N, N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
- SDNode *Result = Emit_137(N, X86::SQRTSDm_Int, MVT::v2f64, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
+ if (SelectScalarSSELoad(N, SDValue(N, 0), N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, CPInChain, Chain1)) {
+ SDNode *Result = Emit_136(N, X86::SQRTSDm_Int, MVT::v2f64, CPInChain, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain1);
return Result;
}
}
@@ -24402,273 +24426,273 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2f64 505:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src, (imm:i8):$cc)
+ // Pattern: (intrinsic_wo_chain:v2f64 501:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src, (imm:i8):$cc)
// Emits: (Int_CMPSDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src, (imm:i8):$cc)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(505)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_123(N, X86::Int_CMPSDrr, MVT::v2f64);
+ if (CN1 == INT64_C(501)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_122(N, X86::Int_CMPSDrr, MVT::v2f64);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 504:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src, (imm:i8):$cc)
+ // Pattern: (intrinsic_wo_chain:v2f64 500:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src, (imm:i8):$cc)
// Emits: (CMPPDrri:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src, (imm:i8):$cc)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(504)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_123(N, X86::CMPPDrri, MVT::v2f64);
+ if (CN1 == INT64_C(500)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_122(N, X86::CMPPDrri, MVT::v2f64);
return Result;
}
}
}
}
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2f64 656:iPTR, VR128:v2f64:$src1, (imm:i32):$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 652:iPTR, VR128:v2f64:$src1, (imm:i32):$src2)
// Emits: (ROUNDPDr_Int:v2f64 VR128:v2f64:$src1, (imm:i32):$src2)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(656)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_128(N, X86::ROUNDPDr_Int, MVT::v2f64);
+ if (CN1 == INT64_C(652)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_127(N, X86::ROUNDPDr_Int, MVT::v2f64);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 658:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v2f64 654:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
// Emits: (ROUNDSDr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(658)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_119(N, X86::ROUNDSDr_Int, MVT::v2f64);
+ if (CN1 == INT64_C(654)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_118(N, X86::ROUNDSDr_Int, MVT::v2f64);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 613:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v2f64 609:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
// Emits: (BLENDPDrri:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(613)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_119(N, X86::BLENDPDrri, MVT::v2f64);
+ if (CN1 == INT64_C(609)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_118(N, X86::BLENDPDrri, MVT::v2f64);
return Result;
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 617:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
+ // Pattern: (intrinsic_wo_chain:v2f64 613:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
// Emits: (DPPDrri:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i32):$src3)
// Pattern complexity = 11 cost = 1 size = 3
- if (CN1 == INT64_C(617)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_119(N, X86::DPPDrri, MVT::v2f64);
+ if (CN1 == INT64_C(613)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_118(N, X86::DPPDrri, MVT::v2f64);
return Result;
}
}
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2f64 522:iPTR, VR128:v2f64:$src1, GR64:i64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 518:iPTR, VR128:v2f64:$src1, GR64:i64:$src2)
// Emits: (Int_CVTSI2SD64rr:v2f64 VR128:v2f64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(522)) {
- SDNode *Result = Emit_111(N, X86::Int_CVTSI2SD64rr, MVT::v2f64);
+ if (CN1 == INT64_C(518)) {
+ SDNode *Result = Emit_110(N, X86::Int_CVTSI2SD64rr, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 689:iPTR, VR64:v2i32:$src)
+ // Pattern: (intrinsic_wo_chain:v2f64 685:iPTR, VR64:v2i32:$src)
// Emits: (Int_CVTPI2PDrr:v2f64 VR64:v2i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(689)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPI2PDrr, MVT::v2f64);
+ if (CN1 == INT64_C(685)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTPI2PDrr, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 502:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 498:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (ADDSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(502)) {
- SDNode *Result = Emit_111(N, X86::ADDSDrr_Int, MVT::v2f64);
+ if (CN1 == INT64_C(498)) {
+ SDNode *Result = Emit_110(N, X86::ADDSDrr_Int, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 542:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 538:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (MULSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(542)) {
- SDNode *Result = Emit_111(N, X86::MULSDrr_Int, MVT::v2f64);
+ if (CN1 == INT64_C(538)) {
+ SDNode *Result = Emit_110(N, X86::MULSDrr_Int, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 597:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 593:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (SUBSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(597)) {
- SDNode *Result = Emit_111(N, X86::SUBSDrr_Int, MVT::v2f64);
+ if (CN1 == INT64_C(593)) {
+ SDNode *Result = Emit_110(N, X86::SUBSDrr_Int, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 528:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 524:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (DIVSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(528)) {
- SDNode *Result = Emit_111(N, X86::DIVSDrr_Int, MVT::v2f64);
+ if (CN1 == INT64_C(524)) {
+ SDNode *Result = Emit_110(N, X86::DIVSDrr_Int, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 534:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 530:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (MAXSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(534)) {
- SDNode *Result = Emit_111(N, X86::MAXSDrr_Int, MVT::v2f64);
+ if (CN1 == INT64_C(530)) {
+ SDNode *Result = Emit_110(N, X86::MAXSDrr_Int, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 533:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 529:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (MAXPDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(533)) {
- SDNode *Result = Emit_111(N, X86::MAXPDrr_Int, MVT::v2f64);
+ if (CN1 == INT64_C(529)) {
+ SDNode *Result = Emit_110(N, X86::MAXPDrr_Int, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 537:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 533:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (MINSDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(537)) {
- SDNode *Result = Emit_111(N, X86::MINSDrr_Int, MVT::v2f64);
+ if (CN1 == INT64_C(533)) {
+ SDNode *Result = Emit_110(N, X86::MINSDrr_Int, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 536:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 532:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (MINPDrr_Int:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(536)) {
- SDNode *Result = Emit_111(N, X86::MINPDrr_Int, MVT::v2f64);
+ if (CN1 == INT64_C(532)) {
+ SDNode *Result = Emit_110(N, X86::MINPDrr_Int, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 512:iPTR, VR128:v4i32:$src)
+ // Pattern: (intrinsic_wo_chain:v2f64 508:iPTR, VR128:v4i32:$src)
// Emits: (Int_CVTDQ2PDrr:v2f64 VR128:v4i32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(512)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTDQ2PDrr, MVT::v2f64);
+ if (CN1 == INT64_C(508)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTDQ2PDrr, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 517:iPTR, VR128:v4f32:$src)
+ // Pattern: (intrinsic_wo_chain:v2f64 513:iPTR, VR128:v4f32:$src)
// Emits: (Int_CVTPS2PDrr:v2f64 VR128:v4f32:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(517)) {
- SDNode *Result = Emit_108(N, X86::Int_CVTPS2PDrr, MVT::v2f64);
+ if (CN1 == INT64_C(513)) {
+ SDNode *Result = Emit_107(N, X86::Int_CVTPS2PDrr, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 521:iPTR, VR128:v2f64:$src1, GR32:i32:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 517:iPTR, VR128:v2f64:$src1, GR32:i32:$src2)
// Emits: (Int_CVTSI2SDrr:v2f64 VR128:v2f64:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(521)) {
- SDNode *Result = Emit_111(N, X86::Int_CVTSI2SDrr, MVT::v2f64);
+ if (CN1 == INT64_C(517)) {
+ SDNode *Result = Emit_110(N, X86::Int_CVTSI2SDrr, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 523:iPTR, VR128:v2f64:$src1, VR128:v4f32:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 519:iPTR, VR128:v2f64:$src1, VR128:v4f32:$src2)
// Emits: (Int_CVTSS2SDrr:v2f64 VR128:v2f64:$src1, VR128:v4f32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(523)) {
- SDNode *Result = Emit_111(N, X86::Int_CVTSS2SDrr, MVT::v2f64);
+ if (CN1 == INT64_C(519)) {
+ SDNode *Result = Emit_110(N, X86::Int_CVTSS2SDrr, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 593:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:v2f64 589:iPTR, VR128:v2f64:$src)
// Emits: (SQRTSDr_Int:v2f64 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(593)) {
- SDNode *Result = Emit_108(N, X86::SQRTSDr_Int, MVT::v2f64);
+ if (CN1 == INT64_C(589)) {
+ SDNode *Result = Emit_107(N, X86::SQRTSDr_Int, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 592:iPTR, VR128:v2f64:$src)
+ // Pattern: (intrinsic_wo_chain:v2f64 588:iPTR, VR128:v2f64:$src)
// Emits: (SQRTPDr_Int:v2f64 VR128:v2f64:$src)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(592)) {
- SDNode *Result = Emit_108(N, X86::SQRTPDr_Int, MVT::v2f64);
+ if (CN1 == INT64_C(588)) {
+ SDNode *Result = Emit_107(N, X86::SQRTPDr_Int, MVT::v2f64);
return Result;
}
}
}
if ((Subtarget->hasSSE3())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (intrinsic_wo_chain:v2f64 604:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 600:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (ADDSUBPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(604)) {
- SDNode *Result = Emit_111(N, X86::ADDSUBPDrr, MVT::v2f64);
+ if (CN1 == INT64_C(600)) {
+ SDNode *Result = Emit_110(N, X86::ADDSUBPDrr, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 606:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 602:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (HADDPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(606)) {
- SDNode *Result = Emit_111(N, X86::HADDPDrr, MVT::v2f64);
+ if (CN1 == INT64_C(602)) {
+ SDNode *Result = Emit_110(N, X86::HADDPDrr, MVT::v2f64);
return Result;
}
- // Pattern: (intrinsic_wo_chain:v2f64 608:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
+ // Pattern: (intrinsic_wo_chain:v2f64 604:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2)
// Emits: (HSUBPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
- if (CN1 == INT64_C(608)) {
- SDNode *Result = Emit_111(N, X86::HSUBPDrr, MVT::v2f64);
+ if (CN1 == INT64_C(604)) {
+ SDNode *Result = Emit_110(N, X86::HSUBPDrr, MVT::v2f64);
return Result;
}
}
}
- // Pattern: (intrinsic_wo_chain:v2f64 615:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, XMM0:v2f64)
+ // Pattern: (intrinsic_wo_chain:v2f64 611:iPTR, VR128:v2f64:$src1, VR128:v2f64:$src2, XMM0:v2f64)
// Emits: (BLENDVPDrr0:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(615)) {
- SDNode *Result = Emit_121(N, X86::BLENDVPDrr0, MVT::v2f64);
+ if (CN1 == INT64_C(611)) {
+ SDNode *Result = Emit_120(N, X86::BLENDVPDrr0, MVT::v2f64);
return Result;
}
}
@@ -24678,57 +24702,57 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_140(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_139(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(SDNode *N) {
- // Pattern: (intrinsic_w_chain:v16i8 530:iPTR, addr:iPTR:$src)
+ // Pattern: (intrinsic_w_chain:v16i8 526:iPTR, addr:iPTR:$src)
// Emits: (MOVDQUrm_Int:v16i8 addr:iPTR:$src)
// Pattern complexity = 26 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(530)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(526)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_140(N, X86::MOVDQUrm_Int, MVT::v16i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_139(N, X86::MOVDQUrm_Int, MVT::v16i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
}
}
- // Pattern: (intrinsic_w_chain:v16i8 610:iPTR, addr:iPTR:$src)
+ // Pattern: (intrinsic_w_chain:v16i8 606:iPTR, addr:iPTR:$src)
// Emits: (LDDQUrm:v16i8 addr:iPTR:$src)
// Pattern complexity = 26 cost = 1 size = 3
if ((Subtarget->hasSSE3())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(610)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(606)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_140(N, X86::LDDQUrm, MVT::v16i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_139(N, X86::LDDQUrm, MVT::v16i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -24739,22 +24763,22 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2i64(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2i64(SDNode *N) {
if ((Subtarget->hasSSE41())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(621)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(617)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_140(N, X86::MOVNTDQArm, MVT::v2i64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_139(N, X86::MOVNTDQArm, MVT::v2i64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -24765,22 +24789,22 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4f32(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4f32(SDNode *N) {
if ((Subtarget->hasSSE1())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(702)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(698)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_140(N, X86::MOVUPSrm_Int, MVT::v4f32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_139(N, X86::MOVUPSrm_Int, MVT::v4f32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -24791,22 +24815,22 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2f64(const SDValue &N) {
+SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2f64(SDNode *N) {
if ((Subtarget->hasSSE2())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(531)) {
- SDValue N2 = N.getOperand(2);
+ if (CN1 == INT64_C(527)) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_140(N, X86::MOVUPDrm_Int, MVT::v2f64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_139(N, X86::MOVUPDrm_Int, MVT::v2f64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -24817,33 +24841,33 @@ SDNode *Select_ISD_INTRINSIC_W_CHAIN_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_141(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_140(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-SDNode *Select_ISD_LOAD_i8(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode())) {
+SDNode *Select_ISD_LOAD_i8(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N)) {
// Pattern: (ld:i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>
// Emits: (MOV8rm:i8 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_load(N.getNode()) &&
- Predicate_loadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_load(N) &&
+ Predicate_loadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOV8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOV8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -24851,16 +24875,16 @@ SDNode *Select_ISD_LOAD_i8(const SDValue &N) {
// Pattern: (ld:i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
// Emits: (MOV8rm:i8 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextload(N.getNode()) &&
- Predicate_zextloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextload(N) &&
+ Predicate_zextloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOV8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOV8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -24868,16 +24892,16 @@ SDNode *Select_ISD_LOAD_i8(const SDValue &N) {
// Pattern: (ld:i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
// Emits: (MOV8rm:i8 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extload(N.getNode()) &&
- Predicate_extloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extload(N) &&
+ Predicate_extloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOV8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOV8rm, MVT::i8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -24887,22 +24911,22 @@ SDNode *Select_ISD_LOAD_i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_LOAD_i16(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode())) {
+SDNode *Select_ISD_LOAD_i16(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N)) {
// Pattern: (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>
// Emits: (MOV16rm:i16 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_loadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_loadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOV16rm, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOV16rm, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -24910,33 +24934,33 @@ SDNode *Select_ISD_LOAD_i16(const SDValue &N) {
// Pattern: (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
// Emits: (MOVSX16rm8:i16 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_sextload(N.getNode()) &&
- Predicate_sextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextload(N) &&
+ Predicate_sextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVSX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVSX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
- if (Predicate_zextload(N.getNode())) {
+ if (Predicate_zextload(N)) {
// Pattern: (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
// Emits: (MOVZX16rm8:i16 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -24944,33 +24968,33 @@ SDNode *Select_ISD_LOAD_i16(const SDValue &N) {
// Pattern: (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
// Emits: (MOVZX16rm8:i16 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
}
- if (Predicate_extload(N.getNode())) {
+ if (Predicate_extload(N)) {
// Pattern: (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
// Emits: (MOVZX16rm8:i16 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -24978,15 +25002,15 @@ SDNode *Select_ISD_LOAD_i16(const SDValue &N) {
// Pattern: (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
// Emits: (MOVZX16rm8:i16 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX16rm8, MVT::i16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -24997,23 +25021,23 @@ SDNode *Select_ISD_LOAD_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode())) {
- if (Predicate_load(N.getNode())) {
+SDNode *Select_ISD_LOAD_i32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N)) {
+ if (Predicate_load(N)) {
// Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_gsload>>
// Emits: (GS_MOV32rm:i32 addr:iPTR:$src)
// Pattern complexity = 27 cost = 1 size = 3
- if (Predicate_gsload(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_gsload(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::GS_MOV32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::GS_MOV32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25021,15 +25045,15 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_fsload>>
// Emits: (FS_MOV32rm:i32 addr:iPTR:$src)
// Pattern complexity = 27 cost = 1 size = 3
- if (Predicate_fsload(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_fsload(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::FS_MOV32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::FS_MOV32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25038,32 +25062,32 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>
// Emits: (MOV32rm:i32 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_loadi32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_loadi32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOV32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOV32rm, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
- if (Predicate_sextload(N.getNode())) {
+ if (Predicate_sextload(N)) {
// Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
// Emits: (MOVSX32rm8:i32 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_sextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVSX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVSX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25071,33 +25095,33 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
// Emits: (MOVSX32rm16:i32 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_sextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVSX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVSX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
}
- if (Predicate_zextload(N.getNode())) {
+ if (Predicate_zextload(N)) {
// Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
// Emits: (MOVZX32rm8:i32 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25105,15 +25129,15 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
// Emits: (MOVZX32rm16:i32 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25121,33 +25145,33 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
// Emits: (MOVZX32rm8:i32 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
}
- if (Predicate_extload(N.getNode())) {
+ if (Predicate_extload(N)) {
// Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
// Emits: (MOVZX32rm8:i32 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25155,15 +25179,15 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
// Emits: (MOVZX32rm8:i32 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX32rm8, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25171,15 +25195,15 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
// Emits: (MOVZX32rm16:i32 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25188,16 +25212,16 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
// Emits: (MOVSX32rm16:i32 addr:iPTR:$dst)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_sextload(N.getNode()) &&
- Predicate_sextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextload(N) &&
+ Predicate_sextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVSX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVSX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25205,16 +25229,16 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
// Emits: (MOVZX32rm16:i32 addr:iPTR:$dst)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextload(N.getNode()) &&
- Predicate_zextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextload(N) &&
+ Predicate_zextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25222,16 +25246,16 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
// Pattern: (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
// Emits: (MOVZX32rm16:i32 addr:iPTR:$dst)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extload(N.getNode()) &&
- Predicate_extloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extload(N) &&
+ Predicate_extloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX32rm16, MVT::i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25241,38 +25265,38 @@ SDNode *Select_ISD_LOAD_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_142(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_141(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp0 = CurDAG->getTargetConstant(0x0ULL, MVT::i64);
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, MVT::Other, Ops0, 6), 0);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, MVT::Other, Ops0, 6), 0);
Chain = SDValue(Tmp2.getNode(), 1);
SDValue Tmp3 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
MachineSDNode::mmo_iterator MemRefs1 = MF->allocateMemRefsArray(1);
MemRefs1[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops1[] = { Tmp0, Tmp2, Tmp3, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, MVT::Other, Ops1, 4);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc1, VT1, MVT::Other, Ops1, 4);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs1, MemRefs1 + 1);
return ResNode;
}
-SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode())) {
- if (Predicate_load(N.getNode())) {
+SDNode *Select_ISD_LOAD_i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N)) {
+ if (Predicate_load(N)) {
// Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_gsload>>
// Emits: (MOV64GSrm:i64 addr:iPTR:$src)
// Pattern complexity = 27 cost = 1 size = 3
- if (Predicate_gsload(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_gsload(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOV64GSrm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOV64GSrm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25280,15 +25304,15 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
// Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_fsload>>
// Emits: (MOV64FSrm:i64 addr:iPTR:$src)
// Pattern complexity = 27 cost = 1 size = 3
- if (Predicate_fsload(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_fsload(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOV64FSrm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOV64FSrm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25296,31 +25320,31 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
// Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
// Emits: (MOV64rm:i64 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOV64rm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOV64rm, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
- if (Predicate_sextload(N.getNode())) {
+ if (Predicate_sextload(N)) {
// Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>
// Emits: (MOVSX64rm8:i64 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_sextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVSX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVSX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25328,15 +25352,15 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
// Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
// Emits: (MOVSX64rm16:i64 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_sextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVSX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVSX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25344,33 +25368,33 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
// Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>>
// Emits: (MOVSX64rm32:i64 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_sextloadi32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextloadi32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVSX64rm32, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVSX64rm32, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
}
- if (Predicate_zextload(N.getNode())) {
+ if (Predicate_zextload(N)) {
// Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>
// Emits: (MOVZX64rm8:i64 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25378,15 +25402,15 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
// Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
// Emits: (MOVZX64rm16:i64 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25394,15 +25418,15 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
// Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>
// Emits: (MOVZX64rm32:i64 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextloadi32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX64rm32, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX64rm32, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25410,33 +25434,33 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
// Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>
// Emits: (MOVZX64rm8:i64 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
}
- if (Predicate_extload(N.getNode())) {
+ if (Predicate_extload(N)) {
// Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>
// Emits: (MOVZX64rm8:i64 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extloadi1(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi1(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25444,15 +25468,15 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
// Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>
// Emits: (MOVZX64rm8:i64 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extloadi8(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi8(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX64rm8, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25460,15 +25484,15 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
// Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
// Emits: (MOVZX64rm16:i64 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25477,16 +25501,16 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
// Pattern: (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>
// Emits: (MOVSX64rm16:i64 addr:iPTR:$dst)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_sextload(N.getNode()) &&
- Predicate_sextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_sextload(N) &&
+ Predicate_sextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVSX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVSX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25494,33 +25518,33 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
// Pattern: (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>
// Emits: (MOVZX64rm16:i64 addr:iPTR:$dst)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_zextload(N.getNode()) &&
- Predicate_zextloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_zextload(N) &&
+ Predicate_zextloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
- if (Predicate_extload(N.getNode())) {
+ if (Predicate_extload(N)) {
// Pattern: (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>
// Emits: (MOVZX64rm16:i64 addr:iPTR:$dst)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_extloadi16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi16(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVZX64rm16, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25528,15 +25552,15 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
// Pattern: (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>>
// Emits: (SUBREG_TO_REG:i64 0:i64, (MOV32rm:i32 addr:iPTR:$src), 4:i32)
// Pattern complexity = 22 cost = 2 size = 3
- if (Predicate_extloadi32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadi32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_142(N, X86::MOV32rm, TargetInstrInfo::SUBREG_TO_REG, MVT::i32, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_141(N, X86::MOV32rm, TargetInstrInfo::SUBREG_TO_REG, MVT::i32, MVT::i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25547,45 +25571,45 @@ SDNode *Select_ISD_LOAD_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_LOAD_f32(const SDValue &N) {
+SDNode *Select_ISD_LOAD_f32(SDNode *N) {
// Pattern: (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>
// Emits: (LD_Fp32m:f32 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 0
if ((!Subtarget->hasSSE1())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode()) &&
- Predicate_load(N.getNode()) &&
- Predicate_loadf32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N) &&
+ Predicate_load(N) &&
+ Predicate_loadf32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::LD_Fp32m, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::LD_Fp32m, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
}
if ((Subtarget->hasSSE1())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode()) &&
- Predicate_load(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N) &&
+ Predicate_load(N)) {
// Pattern: (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>
// Emits: (MOVSSrm:f32 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_loadf32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_loadf32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVSSrm, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVSSrm, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25593,15 +25617,15 @@ SDNode *Select_ISD_LOAD_f32(const SDValue &N) {
// Pattern: (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_alignedload>>
// Emits: (FsMOVAPSrm:f32 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_alignedload(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_alignedload(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::FsMOVAPSrm, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::FsMOVAPSrm, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25612,37 +25636,37 @@ SDNode *Select_ISD_LOAD_f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_143(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_142(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
- SDValue Tmp1(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, MVT::Other, Ops0, 6), 0);
+ SDValue Tmp1(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, MVT::Other, Ops0, 6), 0);
Chain = SDValue(Tmp1.getNode(), 1);
MachineSDNode::mmo_iterator MemRefs1 = MF->allocateMemRefsArray(1);
MemRefs1[0] = cast<MemSDNode>(N)->getMemOperand();
- SDNode *ResNode = CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp1);
+ SDNode *ResNode = CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp1);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs1, MemRefs1 + 1);
- ReplaceUses(SDValue(N.getNode(), 1), Chain);
+ ReplaceUses(SDValue(N, 1), Chain);
return ResNode;
}
-SDNode *Select_ISD_LOAD_f64(const SDValue &N) {
+SDNode *Select_ISD_LOAD_f64(SDNode *N) {
if ((!Subtarget->hasSSE2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N)) {
// Pattern: (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>
// Emits: (LD_Fp64m:f64 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 0
- if (Predicate_load(N.getNode()) &&
- Predicate_loadf64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_load(N) &&
+ Predicate_loadf64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::LD_Fp64m, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::LD_Fp64m, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25650,16 +25674,16 @@ SDNode *Select_ISD_LOAD_f64(const SDValue &N) {
// Pattern: (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>
// Emits: (LD_Fp32m64:f64 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 0
- if (Predicate_extload(N.getNode()) &&
- Predicate_extloadf32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extload(N) &&
+ Predicate_extloadf32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::LD_Fp32m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::LD_Fp32m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25670,18 +25694,18 @@ SDNode *Select_ISD_LOAD_f64(const SDValue &N) {
// Emits: (MOVSDrm:f64 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode()) &&
- Predicate_load(N.getNode()) &&
- Predicate_loadf64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N) &&
+ Predicate_load(N) &&
+ Predicate_loadf64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVSDrm, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVSDrm, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25691,18 +25715,18 @@ SDNode *Select_ISD_LOAD_f64(const SDValue &N) {
// Emits: (CVTSS2SDrm:f64 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
if ((Subtarget->hasSSE2()) && (OptForSize)) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode()) &&
- Predicate_extload(N.getNode()) &&
- Predicate_extloadf32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N) &&
+ Predicate_extload(N) &&
+ Predicate_extloadf32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::CVTSS2SDrm, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::CVTSS2SDrm, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25712,18 +25736,18 @@ SDNode *Select_ISD_LOAD_f64(const SDValue &N) {
// Emits: (FsMOVAPDrm:f64 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode()) &&
- Predicate_load(N.getNode()) &&
- Predicate_alignedload(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N) &&
+ Predicate_load(N) &&
+ Predicate_alignedload(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::FsMOVAPDrm, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::FsMOVAPDrm, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25733,18 +25757,18 @@ SDNode *Select_ISD_LOAD_f64(const SDValue &N) {
// Emits: (CVTSS2SDrr:f64 (MOVSSrm:f32 addr:iPTR:$src))
// Pattern complexity = 22 cost = 2 size = 6
if ((Subtarget->hasSSE2()) && (!OptForSize)) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode()) &&
- Predicate_extload(N.getNode()) &&
- Predicate_extloadf32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N) &&
+ Predicate_extload(N) &&
+ Predicate_extloadf32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_143(N, X86::MOVSSrm, X86::CVTSS2SDrr, MVT::f32, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_142(N, X86::MOVSSrm, X86::CVTSS2SDrr, MVT::f32, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25754,40 +25778,40 @@ SDNode *Select_ISD_LOAD_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_LOAD_f80(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode())) {
+SDNode *Select_ISD_LOAD_f80(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N)) {
// Pattern: (ld:f80 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf80>>
// Emits: (LD_Fp80m:f80 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 0
- if (Predicate_load(N.getNode()) &&
- Predicate_loadf80(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_load(N) &&
+ Predicate_loadf80(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::LD_Fp80m, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::LD_Fp80m, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
- if (Predicate_extload(N.getNode())) {
+ if (Predicate_extload(N)) {
// Pattern: (ld:f80 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf64>>
// Emits: (LD_Fp64m80:f80 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 0
- if (Predicate_extloadf64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadf64(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::LD_Fp64m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::LD_Fp64m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25795,15 +25819,15 @@ SDNode *Select_ISD_LOAD_f80(const SDValue &N) {
// Pattern: (ld:f80 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadf32>>
// Emits: (LD_Fp32m80:f80 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 0
- if (Predicate_extloadf32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_extloadf32(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::LD_Fp32m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::LD_Fp32m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25814,24 +25838,24 @@ SDNode *Select_ISD_LOAD_f80(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_LOAD_v4i32(const SDValue &N) {
+SDNode *Select_ISD_LOAD_v4i32(SDNode *N) {
if ((Subtarget->hasSSE1())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode()) &&
- Predicate_load(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N) &&
+ Predicate_load(N)) {
// Pattern: (ld:v4i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_alignedload>>
// Emits: (MOVAPSrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_alignedload(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_alignedload(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVAPSrm, MVT::v4i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVAPSrm, MVT::v4i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25839,14 +25863,14 @@ SDNode *Select_ISD_LOAD_v4i32(const SDValue &N) {
// Pattern: (ld:v4i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
// Emits: (MOVUPSrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVUPSrm, MVT::v4i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVUPSrm, MVT::v4i32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25856,19 +25880,19 @@ SDNode *Select_ISD_LOAD_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_LOAD_v1i64(const SDValue &N) {
+SDNode *Select_ISD_LOAD_v1i64(SDNode *N) {
if ((Subtarget->hasMMX())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode()) &&
- Predicate_load(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N) &&
+ Predicate_load(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MMX_MOVQ64rm, MVT::v1i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MMX_MOVQ64rm, MVT::v1i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25878,24 +25902,24 @@ SDNode *Select_ISD_LOAD_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_LOAD_v2i64(const SDValue &N) {
+SDNode *Select_ISD_LOAD_v2i64(SDNode *N) {
if ((Subtarget->hasSSE2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode()) &&
- Predicate_load(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N) &&
+ Predicate_load(N)) {
// Pattern: (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_alignedload>>
// Emits: (MOVAPSrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_alignedload(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_alignedload(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVAPSrm, MVT::v2i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVAPSrm, MVT::v2i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25903,14 +25927,14 @@ SDNode *Select_ISD_LOAD_v2i64(const SDValue &N) {
// Pattern: (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
// Emits: (MOVUPSrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVUPSrm, MVT::v2i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVUPSrm, MVT::v2i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25920,24 +25944,24 @@ SDNode *Select_ISD_LOAD_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_LOAD_v4f32(const SDValue &N) {
+SDNode *Select_ISD_LOAD_v4f32(SDNode *N) {
if ((Subtarget->hasSSE1())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode()) &&
- Predicate_load(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N) &&
+ Predicate_load(N)) {
// Pattern: (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_alignedload>>
// Emits: (MOVAPSrm:v4f32 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_alignedload(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_alignedload(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVAPSrm, MVT::v4f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVAPSrm, MVT::v4f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25945,14 +25969,14 @@ SDNode *Select_ISD_LOAD_v4f32(const SDValue &N) {
// Pattern: (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
// Emits: (MOVUPSrm:v4f32 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVUPSrm, MVT::v4f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVUPSrm, MVT::v4f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25962,24 +25986,24 @@ SDNode *Select_ISD_LOAD_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_LOAD_v2f64(const SDValue &N) {
+SDNode *Select_ISD_LOAD_v2f64(SDNode *N) {
if ((Subtarget->hasSSE2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedload(N.getNode()) &&
- Predicate_load(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedload(N) &&
+ Predicate_load(N)) {
// Pattern: (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_alignedload>>
// Emits: (MOVAPDrm:v2f64 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_alignedload(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ if (Predicate_alignedload(N)) {
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVAPDrm, MVT::v2f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVAPDrm, MVT::v2f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -25987,14 +26011,14 @@ SDNode *Select_ISD_LOAD_v2f64(const SDValue &N) {
// Pattern: (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>
// Emits: (MOVUPDrm:v2f64 addr:iPTR:$src)
// Pattern complexity = 22 cost = 1 size = 3
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_141(N, X86::MOVUPDrm, MVT::v2f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_140(N, X86::MOVUPDrm, MVT::v2f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -26004,20 +26028,20 @@ SDNode *Select_ISD_LOAD_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_144(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue N4 = N.getOperand(4);
- SDValue N5 = N.getOperand(5);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain);
+DISABLE_INLINE SDNode *Emit_143(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue N4 = N->getOperand(4);
+ SDValue N5 = N->getOperand(5);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Chain);
}
-SDNode *Select_ISD_MEMBARRIER(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_MEMBARRIER(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -26025,28 +26049,28 @@ SDNode *Select_ISD_MEMBARRIER(const SDValue &N) {
// Emits: (SFENCE:isVoid)
// Pattern complexity = 28 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N2);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(0)) {
- SDValue N3 = N.getOperand(3);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N3);
+ SDValue N3 = N->getOperand(3);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N3.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(0)) {
- SDValue N4 = N.getOperand(4);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N4);
+ SDValue N4 = N->getOperand(4);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N4.getNode());
if (Tmp6) {
int64_t CN7 = Tmp6->getSExtValue();
if (CN7 == INT64_C(1)) {
- SDValue N5 = N.getOperand(5);
- ConstantSDNode *Tmp8 = dyn_cast<ConstantSDNode>(N5);
+ SDValue N5 = N->getOperand(5);
+ ConstantSDNode *Tmp8 = dyn_cast<ConstantSDNode>(N5.getNode());
if (Tmp8) {
int64_t CN9 = Tmp8->getSExtValue();
if (CN9 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_144(N, X86::SFENCE);
+ SDNode *Result = Emit_143(N, X86::SFENCE);
return Result;
}
}
@@ -26062,28 +26086,28 @@ SDNode *Select_ISD_MEMBARRIER(const SDValue &N) {
// Emits: (LFENCE:isVoid)
// Pattern complexity = 28 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N2);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp2 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp2) {
int64_t CN3 = Tmp2->getSExtValue();
if (CN3 == INT64_C(0)) {
- SDValue N3 = N.getOperand(3);
- ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N3);
+ SDValue N3 = N->getOperand(3);
+ ConstantSDNode *Tmp4 = dyn_cast<ConstantSDNode>(N3.getNode());
if (Tmp4) {
int64_t CN5 = Tmp4->getSExtValue();
if (CN5 == INT64_C(0)) {
- SDValue N4 = N.getOperand(4);
- ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N4);
+ SDValue N4 = N->getOperand(4);
+ ConstantSDNode *Tmp6 = dyn_cast<ConstantSDNode>(N4.getNode());
if (Tmp6) {
int64_t CN7 = Tmp6->getSExtValue();
if (CN7 == INT64_C(0)) {
- SDValue N5 = N.getOperand(5);
- ConstantSDNode *Tmp8 = dyn_cast<ConstantSDNode>(N5);
+ SDValue N5 = N->getOperand(5);
+ ConstantSDNode *Tmp8 = dyn_cast<ConstantSDNode>(N5.getNode());
if (Tmp8) {
int64_t CN9 = Tmp8->getSExtValue();
if (CN9 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_144(N, X86::LFENCE);
+ SDNode *Result = Emit_143(N, X86::LFENCE);
return Result;
}
}
@@ -26096,15 +26120,15 @@ SDNode *Select_ISD_MEMBARRIER(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDValue N4 = N.getOperand(4);
- if (N4.getOpcode() == ISD::Constant) {
- SDValue N5 = N.getOperand(5);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N5);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N4 = N->getOperand(4);
+ if (N4.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N5 = N->getOperand(5);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N5.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -26113,7 +26137,7 @@ SDNode *Select_ISD_MEMBARRIER(const SDValue &N) {
// Pattern complexity = 20 cost = 1 size = 3
if (CN1 == INT64_C(0) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_144(N, X86::NOOP);
+ SDNode *Result = Emit_143(N, X86::NOOP);
return Result;
}
@@ -26122,7 +26146,7 @@ SDNode *Select_ISD_MEMBARRIER(const SDValue &N) {
// Pattern complexity = 20 cost = 1 size = 3
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_144(N, X86::MFENCE);
+ SDNode *Result = Emit_143(N, X86::MFENCE);
return Result;
}
}
@@ -26135,56 +26159,56 @@ SDNode *Select_ISD_MEMBARRIER(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_145(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_144(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Chain = CurDAG->getEntryNode();
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::AL, N0, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::AL, N0, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i8, MVT::i32, N1, InFlag);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::i8, MVT::i32, N1, InFlag);
}
-DISABLE_INLINE SDNode *Emit_146(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_145(SDNode *N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain1, N.getDebugLoc(), X86::AL, N0, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain1, N->getDebugLoc(), X86::AL, N0, InFlag).getNode();
Chain1 = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1, InFlag };
- ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i8, MVT::i32, MVT::Other, Ops0, 7);
+ ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i8, MVT::i32, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 2));
return ResNode;
}
-SDNode *Select_ISD_MUL_i8(const SDValue &N) {
+SDNode *Select_ISD_MUL_i8(SDNode *N) {
// Pattern: (mul:i8 AL:i8, (ld:i8 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
// Emits: (MUL8m:isVoid addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_loadi8(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_146(N, X86::MUL8m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_145(N, X86::MUL8m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -26194,55 +26218,55 @@ SDNode *Select_ISD_MUL_i8(const SDValue &N) {
// Pattern: (mul:i8 AL:i8, GR8:i8:$src)
// Emits: (MUL8r:isVoid GR8:i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_145(N, X86::MUL8r);
+ SDNode *Result = Emit_144(N, X86::MUL8r);
return Result;
}
-DISABLE_INLINE SDNode *Emit_147(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_146(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 2));
return ResNode;
}
-SDNode *Select_ISD_MUL_i16(const SDValue &N) {
+SDNode *Select_ISD_MUL_i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (mul:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Emits: (IMUL16rmi8:i16 addr:iPTR:$src1, (imm:i16):$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_147(N, X86::IMUL16rmi8, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_146(N, X86::IMUL16rmi8, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
// Pattern: (mul:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16):$src2)
// Emits: (IMUL16rmi:i16 addr:iPTR:$src1, (imm:i16):$src2)
// Pattern complexity = 28 cost = 1 size = 3
- SDNode *Result = Emit_147(N, X86::IMUL16rmi, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_146(N, X86::IMUL16rmi, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -26253,14 +26277,14 @@ SDNode *Select_ISD_MUL_i16(const SDValue &N) {
// Emits: (IMUL16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -26277,13 +26301,13 @@ SDNode *Select_ISD_MUL_i16(const SDValue &N) {
// Pattern: (mul:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src1)
// Emits: (IMUL16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -26297,9 +26321,9 @@ SDNode *Select_ISD_MUL_i16(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (mul:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Emits: (IMUL16rri8:i16 GR16:i16:$src1, (imm:i16):$src2)
@@ -26324,51 +26348,51 @@ SDNode *Select_ISD_MUL_i16(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_148(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_147(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 2));
return ResNode;
}
-SDNode *Select_ISD_MUL_i32(const SDValue &N) {
+SDNode *Select_ISD_MUL_i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (mul:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Emits: (IMUL32rmi8:i32 addr:iPTR:$src1, (imm:i32):$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_148(N, X86::IMUL32rmi8, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_147(N, X86::IMUL32rmi8, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
// Pattern: (mul:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32):$src2)
// Emits: (IMUL32rmi:i32 addr:iPTR:$src1, (imm:i32):$src2)
// Pattern complexity = 28 cost = 1 size = 3
- SDNode *Result = Emit_148(N, X86::IMUL32rmi, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_147(N, X86::IMUL32rmi, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -26379,14 +26403,14 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
// Emits: (IMUL32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -26403,13 +26427,13 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
// Pattern: (mul:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src1)
// Emits: (IMUL32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -26431,7 +26455,7 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
@@ -26445,15 +26469,15 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (mul:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Emits: (IMUL32rri8:i32 GR32:i32:$src1, (imm:i32):$src2)
@@ -26478,44 +26502,44 @@ SDNode *Select_ISD_MUL_i32(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_149(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_148(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 2));
return ResNode;
}
-SDNode *Select_ISD_MUL_i64(const SDValue &N) {
+SDNode *Select_ISD_MUL_i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (mul:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Emits: (IMUL64rmi8:i64 addr:iPTR:$src1, (imm:i64):$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_149(N, X86::IMUL64rmi8, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_148(N, X86::IMUL64rmi8, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -26523,7 +26547,7 @@ SDNode *Select_ISD_MUL_i64(const SDValue &N) {
// Emits: (IMUL64rmi32:i64 addr:iPTR:$src1, (imm:i64):$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_149(N, X86::IMUL64rmi32, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_148(N, X86::IMUL64rmi32, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -26535,14 +26559,14 @@ SDNode *Select_ISD_MUL_i64(const SDValue &N) {
// Emits: (IMUL64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -26559,13 +26583,13 @@ SDNode *Select_ISD_MUL_i64(const SDValue &N) {
// Pattern: (mul:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
// Emits: (IMUL64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -26587,15 +26611,15 @@ SDNode *Select_ISD_MUL_i64(const SDValue &N) {
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (mul:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Emits: (IMUL64rri8:i64 GR64:i64:$src1, (imm:i64):$src2)
@@ -26622,24 +26646,24 @@ SDNode *Select_ISD_MUL_i64(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_MUL_v16i8(const SDValue &N) {
+SDNode *Select_ISD_MUL_v16i8(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (mul:v16i8 VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PMULLDrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -26656,14 +26680,14 @@ SDNode *Select_ISD_MUL_v16i8(const SDValue &N) {
// Pattern: (mul:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v16i8:$src1)
// Emits: (PMULLDrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -26681,26 +26705,26 @@ SDNode *Select_ISD_MUL_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_MUL_v4i16(const SDValue &N) {
+SDNode *Select_ISD_MUL_v4i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (mul:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PMULLWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -26719,23 +26743,23 @@ SDNode *Select_ISD_MUL_v4i16(const SDValue &N) {
// Pattern: (mul:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
// Emits: (MMX_PMULLWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v1i64) {
SDNode *Result = Emit_17(N, X86::MMX_PMULLWrm, MVT::v4i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
@@ -26758,27 +26782,27 @@ SDNode *Select_ISD_MUL_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_MUL_v8i16(const SDValue &N) {
+SDNode *Select_ISD_MUL_v8i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (mul:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PMULLWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -26797,24 +26821,24 @@ SDNode *Select_ISD_MUL_v8i16(const SDValue &N) {
// Pattern: (mul:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), VR128:v8i16:$src1)
// Emits: (PMULLWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode()) &&
Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_17(N, X86::PMULLWrm, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
@@ -26837,7 +26861,7 @@ SDNode *Select_ISD_MUL_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_MUL_v4i32(const SDValue &N) {
+SDNode *Select_ISD_MUL_v4i32(SDNode *N) {
if ((Subtarget->hasSSE41())) {
SDNode *Result = Emit_15(N, X86::PMULLDrr, MVT::v4i32);
return Result;
@@ -26847,22 +26871,22 @@ SDNode *Select_ISD_MUL_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_OR_i8(const SDValue &N) {
+SDNode *Select_ISD_OR_i8(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (or:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (OR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -26879,13 +26903,13 @@ SDNode *Select_ISD_OR_i8(const SDValue &N) {
// Pattern: (or:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src1)
// Emits: (OR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -26903,9 +26927,9 @@ SDNode *Select_ISD_OR_i8(const SDValue &N) {
// Emits: (OR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_3(N, X86::OR8ri, MVT::i8);
return Result;
}
@@ -26918,110 +26942,110 @@ SDNode *Select_ISD_OR_i8(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_150(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
+DISABLE_INLINE SDNode *Emit_149(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue Chain = CurDAG->getEntryNode();
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N0.getDebugLoc(), X86::CL, N01, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N0.getNode()->getDebugLoc(), X86::CL, N01, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N10, InFlag);
-}
-DISABLE_INLINE SDNode *Emit_151(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, N10, InFlag);
+}
+DISABLE_INLINE SDNode *Emit_150(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
SDValue Chain = CurDAG->getEntryNode();
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N01.getDebugLoc(), X86::CX, N010, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N01.getNode()->getDebugLoc(), X86::CX, N010, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N10, InFlag);
-}
-DISABLE_INLINE SDNode *Emit_152(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, N10, InFlag);
+}
+DISABLE_INLINE SDNode *Emit_151(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i8);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N10, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_153(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, N10, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_152(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Chain = CurDAG->getEntryNode();
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N01.getDebugLoc(), X86::CL, N011, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N01.getNode()->getDebugLoc(), X86::CL, N011, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N00, InFlag);
-}
-DISABLE_INLINE SDNode *Emit_154(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N10, N00, InFlag);
+}
+DISABLE_INLINE SDNode *Emit_153(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
SDValue Chain = CurDAG->getEntryNode();
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N010.getDebugLoc(), X86::CX, N0101, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N010.getNode()->getDebugLoc(), X86::CX, N0101, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N00, InFlag);
-}
-DISABLE_INLINE SDNode *Emit_155(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N10, N00, InFlag);
+}
+DISABLE_INLINE SDNode *Emit_154(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i8);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N00, Tmp2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N10, N00, Tmp2);
}
-SDNode *Select_ISD_OR_i16(const SDValue &N) {
+SDNode *Select_ISD_OR_i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (or:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (OR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -27038,13 +27062,13 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
// Pattern: (or:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src1)
// Emits: (OR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -27058,35 +27082,35 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (or:i16 (srl:i16 GR16:i16:$src1, (trunc:i8 CX:i16:$amt)), (shl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))))
// Emits: (SHRD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 23 cost = 1 size = 3
- if (N0.getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::TRUNCATE) {
- SDValue N010 = N01.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::TRUNCATE) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::SUB) {
- SDValue N1100 = N110.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1100);
+ if (N0.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1100.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1101 = N110.getOperand(1);
+ SDValue N1101 = N110.getNode()->getOperand(1);
if (N010 == N1101 &&
N01.getValueType() == MVT::i8 &&
N010.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8 &&
N110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_151(N, X86::SHRD16rrCL, MVT::i16);
+ SDNode *Result = Emit_150(N, X86::SHRD16rrCL, MVT::i16);
return Result;
}
}
@@ -27096,35 +27120,35 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::TRUNCATE) {
- SDValue N010 = N01.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N010 = N01.getNode()->getOperand(0);
// Pattern: (or:i16 (shl:i16 GR16:i16:$src1, (trunc:i8 CX:i16:$amt)), (srl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))))
// Emits: (SHLD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 23 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::TRUNCATE) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::SUB) {
- SDValue N1100 = N110.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1100);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1100.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1101 = N110.getOperand(1);
+ SDValue N1101 = N110.getNode()->getOperand(1);
if (N010 == N1101 &&
N01.getValueType() == MVT::i8 &&
N010.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8 &&
N110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_151(N, X86::SHLD16rrCL, MVT::i16);
+ SDNode *Result = Emit_150(N, X86::SHLD16rrCL, MVT::i16);
return Result;
}
}
@@ -27137,25 +27161,25 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
// Pattern: (or:i16 (shl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))), (srl:i16 GR16:i16:$src1, (trunc:i8 CX:i16:$amt)))
// Emits: (SHRD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 23 cost = 1 size = 3
- if (N010.getOpcode() == ISD::SUB) {
- SDValue N0100 = N010.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0100);
+ if (N010.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0100.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N0101 = N010.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::TRUNCATE) {
- SDValue N110 = N11.getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
if (N0101 == N110 &&
N01.getValueType() == MVT::i8 &&
N010.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8 &&
N110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_154(N, X86::SHRD16rrCL, MVT::i16);
+ SDNode *Result = Emit_153(N, X86::SHRD16rrCL, MVT::i16);
return Result;
}
}
@@ -27165,34 +27189,34 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+ if (N0.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
// Pattern: (or:i16 (srl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))), (shl:i16 GR16:i16:$src1, (trunc:i8 CX:i16:$amt)))
// Emits: (SHLD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 23 cost = 1 size = 3
- if (N01.getOpcode() == ISD::TRUNCATE) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::SUB) {
- SDValue N0100 = N010.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0100);
+ if (N01.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0100.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N0101 = N010.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::TRUNCATE) {
- SDValue N110 = N11.getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
if (N0101 == N110 &&
N01.getValueType() == MVT::i8 &&
N010.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8 &&
N110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_154(N, X86::SHLD16rrCL, MVT::i16);
+ SDNode *Result = Emit_153(N, X86::SHLD16rrCL, MVT::i16);
return Result;
}
}
@@ -27205,21 +27229,21 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
// Pattern: (or:i16 (srl:i16 GR16:i16:$src1, CL:i8:$amt), (shl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)))
// Emits: (SHRD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 17 cost = 1 size = 3
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SUB) {
- SDValue N110 = N11.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N110);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N110.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
if (N01 == N111 &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_150(N, X86::SHRD16rrCL, MVT::i16);
+ SDNode *Result = Emit_149(N, X86::SHRD16rrCL, MVT::i16);
return Result;
}
}
@@ -27227,29 +27251,29 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+ if (N0.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
// Pattern: (or:i16 (shl:i16 GR16:i16:$src1, CL:i8:$amt), (srl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)))
// Emits: (SHLD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 17 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SUB) {
- SDValue N110 = N11.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N110);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N110.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
if (N01 == N111 &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_150(N, X86::SHLD16rrCL, MVT::i16);
+ SDNode *Result = Emit_149(N, X86::SHLD16rrCL, MVT::i16);
return Result;
}
}
@@ -27261,21 +27285,21 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
// Pattern: (or:i16 (shl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)), (srl:i16 GR16:i16:$src1, CL:i8:$amt))
// Emits: (SHRD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 17 cost = 1 size = 3
- if (N01.getOpcode() == ISD::SUB) {
- SDValue N010 = N01.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N010);
+ if (N01.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N010.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N011 == N11 &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_153(N, X86::SHRD16rrCL, MVT::i16);
+ SDNode *Result = Emit_152(N, X86::SHRD16rrCL, MVT::i16);
return Result;
}
}
@@ -27287,24 +27311,24 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
// Pattern: (or:i16 (srl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)), (shl:i16 GR16:i16:$src1, CL:i8:$amt))
// Emits: (SHLD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 17 cost = 1 size = 3
- if (N0.getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SUB) {
- SDValue N010 = N01.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N010);
+ if (N0.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N010.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N011 == N11 &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_153(N, X86::SHLD16rrCL, MVT::i16);
+ SDNode *Result = Emit_152(N, X86::SHLD16rrCL, MVT::i16);
return Result;
}
}
@@ -27317,20 +27341,20 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
// Pattern: (or:i16 (srl:i16 GR16:i16:$src1, (imm:i8):$amt1), (shl:i16 GR16:i16:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>
// Emits: (SHRD16rri8:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$amt1)
// Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shrd(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ if (Predicate_shrd(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_152(N, X86::SHRD16rri8, MVT::i16);
+ SDNode *Result = Emit_151(N, X86::SHRD16rri8, MVT::i16);
return Result;
}
}
@@ -27341,20 +27365,20 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
// Pattern: (or:i16 (shl:i16 GR16:i16:$src1, (imm:i8):$amt1), (srl:i16 GR16:i16:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>
// Emits: (SHLD16rri8:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$amt1)
// Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shld(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ if (Predicate_shld(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_152(N, X86::SHLD16rri8, MVT::i16);
+ SDNode *Result = Emit_151(N, X86::SHLD16rri8, MVT::i16);
return Result;
}
}
@@ -27365,20 +27389,20 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
// Pattern: (or:i16 (shl:i16 GR16:i16:$src2, (imm:i8):$amt2), (srl:i16 GR16:i16:$src1, (imm:i8):$amt1))<<P:Predicate_shrd>>
// Emits: (SHRD16rri8:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$amt1)
// Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shrd(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ if (Predicate_shrd(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_155(N, X86::SHRD16rri8, MVT::i16);
+ SDNode *Result = Emit_154(N, X86::SHRD16rri8, MVT::i16);
return Result;
}
}
@@ -27389,30 +27413,58 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
// Pattern: (or:i16 (srl:i16 GR16:i16:$src2, (imm:i8):$amt2), (shl:i16 GR16:i16:$src1, (imm:i8):$amt1))<<P:Predicate_shld>>
// Emits: (SHLD16rri8:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$amt1)
// Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shld(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ if (Predicate_shld(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_155(N, X86::SHLD16rri8, MVT::i16);
+ SDNode *Result = Emit_154(N, X86::SHLD16rri8, MVT::i16);
return Result;
}
}
}
}
}
+ if (Predicate_or_is_add(N)) {
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
+
+ // Pattern: (or:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)<<P:Predicate_or_is_add>>
+ // Emits: (ADD16ri8:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (Predicate_i16immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_5(N, X86::ADD16ri8, MVT::i16);
+ return Result;
+ }
+
+ // Pattern: (or:i16 GR16:i16:$src1, (imm:i16):$src2)<<P:Predicate_or_is_add>>
+ // Emits: (ADD16ri:i16 GR16:i16:$src1, (imm:i16):$src2)
+ // Pattern complexity = 12 cost = 1 size = 3
+ SDNode *Result = Emit_5(N, X86::ADD16ri, MVT::i16);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:i16 GR16:i16:$src1, GR16:i16:$src2)<<P:Predicate_or_is_add>>
+ // Emits: (ADD16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
+ // Pattern complexity = 9 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::ADD16rr, MVT::i16);
+ return Result;
+ }
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (or:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Emits: (OR16ri8:i16 GR16:i16:$src1, (imm:i16):$src2)
@@ -27437,58 +27489,58 @@ SDNode *Select_ISD_OR_i16(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_156(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
+DISABLE_INLINE SDNode *Emit_155(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
SDValue Chain = CurDAG->getEntryNode();
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N01.getDebugLoc(), X86::ECX, N010, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N01.getNode()->getDebugLoc(), X86::ECX, N010, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N10, InFlag);
-}
-DISABLE_INLINE SDNode *Emit_157(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N00, N10, InFlag);
+}
+DISABLE_INLINE SDNode *Emit_156(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
SDValue Chain = CurDAG->getEntryNode();
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N010.getDebugLoc(), X86::ECX, N0101, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N010.getNode()->getDebugLoc(), X86::ECX, N0101, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N00, InFlag);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N10, N00, InFlag);
}
-SDNode *Select_ISD_OR_i32(const SDValue &N) {
+SDNode *Select_ISD_OR_i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (or:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (OR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -27505,13 +27557,13 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Pattern: (or:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src1)
// Emits: (OR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -27525,35 +27577,35 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (or:i32 (srl:i32 GR32:i32:$src1, (trunc:i8 ECX:i32:$amt)), (shl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))))
// Emits: (SHRD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 23 cost = 1 size = 3
- if (N0.getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::TRUNCATE) {
- SDValue N010 = N01.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::TRUNCATE) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::SUB) {
- SDValue N1100 = N110.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1100);
+ if (N0.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1100.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N1101 = N110.getOperand(1);
+ SDValue N1101 = N110.getNode()->getOperand(1);
if (N010 == N1101 &&
N01.getValueType() == MVT::i8 &&
N010.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8 &&
N110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_156(N, X86::SHRD32rrCL, MVT::i32);
+ SDNode *Result = Emit_155(N, X86::SHRD32rrCL, MVT::i32);
return Result;
}
}
@@ -27563,35 +27615,35 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::TRUNCATE) {
- SDValue N010 = N01.getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N010 = N01.getNode()->getOperand(0);
// Pattern: (or:i32 (shl:i32 GR32:i32:$src1, (trunc:i8 ECX:i32:$amt)), (srl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))))
// Emits: (SHLD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 23 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::TRUNCATE) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::SUB) {
- SDValue N1100 = N110.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1100);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N1100 = N110.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1100.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N1101 = N110.getOperand(1);
+ SDValue N1101 = N110.getNode()->getOperand(1);
if (N010 == N1101 &&
N01.getValueType() == MVT::i8 &&
N010.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8 &&
N110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_156(N, X86::SHLD32rrCL, MVT::i32);
+ SDNode *Result = Emit_155(N, X86::SHLD32rrCL, MVT::i32);
return Result;
}
}
@@ -27604,25 +27656,25 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Pattern: (or:i32 (shl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))), (srl:i32 GR32:i32:$src1, (trunc:i8 ECX:i32:$amt)))
// Emits: (SHRD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 23 cost = 1 size = 3
- if (N010.getOpcode() == ISD::SUB) {
- SDValue N0100 = N010.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0100);
+ if (N010.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0100.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N0101 = N010.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::TRUNCATE) {
- SDValue N110 = N11.getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
if (N0101 == N110 &&
N01.getValueType() == MVT::i8 &&
N010.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8 &&
N110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_157(N, X86::SHRD32rrCL, MVT::i32);
+ SDNode *Result = Emit_156(N, X86::SHRD32rrCL, MVT::i32);
return Result;
}
}
@@ -27632,34 +27684,34 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+ if (N0.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
// Pattern: (or:i32 (srl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))), (shl:i32 GR32:i32:$src1, (trunc:i8 ECX:i32:$amt)))
// Emits: (SHLD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 23 cost = 1 size = 3
- if (N01.getOpcode() == ISD::TRUNCATE) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::SUB) {
- SDValue N0100 = N010.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0100);
+ if (N01.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ if (N010.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N0100 = N010.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0100.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N0101 = N010.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::TRUNCATE) {
- SDValue N110 = N11.getOperand(0);
+ SDValue N0101 = N010.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N110 = N11.getNode()->getOperand(0);
if (N0101 == N110 &&
N01.getValueType() == MVT::i8 &&
N010.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8 &&
N110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_157(N, X86::SHLD32rrCL, MVT::i32);
+ SDNode *Result = Emit_156(N, X86::SHLD32rrCL, MVT::i32);
return Result;
}
}
@@ -27672,21 +27724,21 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Pattern: (or:i32 (srl:i32 GR32:i32:$src1, CL:i8:$amt), (shl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)))
// Emits: (SHRD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 17 cost = 1 size = 3
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SUB) {
- SDValue N110 = N11.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N110);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N110.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
if (N01 == N111 &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_150(N, X86::SHRD32rrCL, MVT::i32);
+ SDNode *Result = Emit_149(N, X86::SHRD32rrCL, MVT::i32);
return Result;
}
}
@@ -27694,29 +27746,29 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+ if (N0.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
// Pattern: (or:i32 (shl:i32 GR32:i32:$src1, CL:i8:$amt), (srl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)))
// Emits: (SHLD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 17 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SUB) {
- SDValue N110 = N11.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N110);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N110.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
if (N01 == N111 &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_150(N, X86::SHLD32rrCL, MVT::i32);
+ SDNode *Result = Emit_149(N, X86::SHLD32rrCL, MVT::i32);
return Result;
}
}
@@ -27728,21 +27780,21 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Pattern: (or:i32 (shl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)), (srl:i32 GR32:i32:$src1, CL:i8:$amt))
// Emits: (SHRD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 17 cost = 1 size = 3
- if (N01.getOpcode() == ISD::SUB) {
- SDValue N010 = N01.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N010);
+ if (N01.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N010.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N011 == N11 &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_153(N, X86::SHRD32rrCL, MVT::i32);
+ SDNode *Result = Emit_152(N, X86::SHRD32rrCL, MVT::i32);
return Result;
}
}
@@ -27754,24 +27806,24 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Pattern: (or:i32 (srl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)), (shl:i32 GR32:i32:$src1, CL:i8:$amt))
// Emits: (SHLD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 17 cost = 1 size = 3
- if (N0.getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SUB) {
- SDValue N010 = N01.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N010);
+ if (N0.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N010 = N01.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N010.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
if (N011 == N11 &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_153(N, X86::SHLD32rrCL, MVT::i32);
+ SDNode *Result = Emit_152(N, X86::SHLD32rrCL, MVT::i32);
return Result;
}
}
@@ -27784,20 +27836,20 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Pattern: (or:i32 (srl:i32 GR32:i32:$src1, (imm:i8):$amt1), (shl:i32 GR32:i32:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>
// Emits: (SHRD32rri8:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$amt1)
// Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shrd(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ if (Predicate_shrd(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_152(N, X86::SHRD32rri8, MVT::i32);
+ SDNode *Result = Emit_151(N, X86::SHRD32rri8, MVT::i32);
return Result;
}
}
@@ -27808,20 +27860,20 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Pattern: (or:i32 (shl:i32 GR32:i32:$src1, (imm:i8):$amt1), (srl:i32 GR32:i32:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>
// Emits: (SHLD32rri8:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$amt1)
// Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shld(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ if (Predicate_shld(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_152(N, X86::SHLD32rri8, MVT::i32);
+ SDNode *Result = Emit_151(N, X86::SHLD32rri8, MVT::i32);
return Result;
}
}
@@ -27832,20 +27884,20 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Pattern: (or:i32 (shl:i32 GR32:i32:$src2, (imm:i8):$amt2), (srl:i32 GR32:i32:$src1, (imm:i8):$amt1))<<P:Predicate_shrd>>
// Emits: (SHRD32rri8:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$amt1)
// Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shrd(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ if (Predicate_shrd(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_155(N, X86::SHRD32rri8, MVT::i32);
+ SDNode *Result = Emit_154(N, X86::SHRD32rri8, MVT::i32);
return Result;
}
}
@@ -27856,20 +27908,20 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
// Pattern: (or:i32 (srl:i32 GR32:i32:$src2, (imm:i8):$amt2), (shl:i32 GR32:i32:$src1, (imm:i8):$amt1))<<P:Predicate_shld>>
// Emits: (SHLD32rri8:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$amt1)
// Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shld(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ if (Predicate_shld(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_155(N, X86::SHLD32rri8, MVT::i32);
+ SDNode *Result = Emit_154(N, X86::SHLD32rri8, MVT::i32);
return Result;
}
}
@@ -27885,7 +27937,7 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
@@ -27899,15 +27951,43 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
}
+ if (Predicate_or_is_add(N)) {
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
+
+ // Pattern: (or:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)<<P:Predicate_or_is_add>>
+ // Emits: (ADD32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (Predicate_i32immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_8(N, X86::ADD32ri8, MVT::i32);
+ return Result;
+ }
+
+ // Pattern: (or:i32 GR32:i32:$src1, (imm:i32):$src2)<<P:Predicate_or_is_add>>
+ // Emits: (ADD32ri:i32 GR32:i32:$src1, (imm:i32):$src2)
+ // Pattern complexity = 12 cost = 1 size = 3
+ SDNode *Result = Emit_8(N, X86::ADD32ri, MVT::i32);
+ return Result;
+ }
+ }
+
+ // Pattern: (or:i32 GR32:i32:$src1, GR32:i32:$src2)<<P:Predicate_or_is_add>>
+ // Emits: (ADD32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
+ // Pattern complexity = 9 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::ADD32rr, MVT::i32);
+ return Result;
+ }
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (or:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Emits: (OR32ri8:i32 GR32:i32:$src1, (imm:i32):$src2)
@@ -27932,58 +28012,22 @@ SDNode *Select_ISD_OR_i32(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_158(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N1100 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- SDValue Chain = CurDAG->getEntryNode();
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N01.getDebugLoc(), X86::RCX, N010, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00, N10, InFlag);
-}
-DISABLE_INLINE SDNode *Emit_159(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N010 = N01.getOperand(0);
- SDValue N0100 = N010.getOperand(0);
- SDValue N0101 = N010.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue Chain = CurDAG->getEntryNode();
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N010.getDebugLoc(), X86::RCX, N0101, InFlag).getNode();
- Chain = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N10, N00, InFlag);
-}
-SDNode *Select_ISD_OR_i64(const SDValue &N) {
+SDNode *Select_ISD_OR_i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (or:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (OR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -28000,13 +28044,13 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
// Pattern: (or:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
// Emits: (OR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -28019,280 +28063,24 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
}
}
}
- {
- SDValue N0 = N.getOperand(0);
-
- // Pattern: (or:i64 (srl:i64 GR64:i64:$src1, (trunc:i8 RCX:i64:$amt)), (shl:i64 GR64:i64:$src2, (trunc:i8 (sub:i64 64:i64, RCX:i64:$amt))))
- // Emits: (SHRD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 23 cost = 1 size = 3
- if (N0.getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::TRUNCATE) {
- SDValue N010 = N01.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::TRUNCATE) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::SUB) {
- SDValue N1100 = N110.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1100);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(64)) {
- SDValue N1101 = N110.getOperand(1);
- if (N010 == N1101 &&
- N01.getValueType() == MVT::i8 &&
- N010.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8 &&
- N110.getValueType() == MVT::i64) {
- SDNode *Result = Emit_158(N, X86::SHRD64rrCL, MVT::i64);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if (N0.getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::TRUNCATE) {
- SDValue N010 = N01.getOperand(0);
-
- // Pattern: (or:i64 (shl:i64 GR64:i64:$src1, (trunc:i8 RCX:i64:$amt)), (srl:i64 GR64:i64:$src2, (trunc:i8 (sub:i64 64:i64, RCX:i64:$amt))))
- // Emits: (SHLD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 23 cost = 1 size = 3
- {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::TRUNCATE) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::SUB) {
- SDValue N1100 = N110.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1100);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(64)) {
- SDValue N1101 = N110.getOperand(1);
- if (N010 == N1101 &&
- N01.getValueType() == MVT::i8 &&
- N010.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8 &&
- N110.getValueType() == MVT::i64) {
- SDNode *Result = Emit_158(N, X86::SHLD64rrCL, MVT::i64);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i64 (shl:i64 GR64:i64:$src2, (trunc:i8 (sub:i64 64:i64, RCX:i64:$amt))), (srl:i64 GR64:i64:$src1, (trunc:i8 RCX:i64:$amt)))
- // Emits: (SHRD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 23 cost = 1 size = 3
- if (N010.getOpcode() == ISD::SUB) {
- SDValue N0100 = N010.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0100);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(64)) {
- SDValue N0101 = N010.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::TRUNCATE) {
- SDValue N110 = N11.getOperand(0);
- if (N0101 == N110 &&
- N01.getValueType() == MVT::i8 &&
- N010.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8 &&
- N110.getValueType() == MVT::i64) {
- SDNode *Result = Emit_159(N, X86::SHRD64rrCL, MVT::i64);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- if (N0.getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
-
- // Pattern: (or:i64 (srl:i64 GR64:i64:$src2, (trunc:i8 (sub:i64 64:i64, RCX:i64:$amt))), (shl:i64 GR64:i64:$src1, (trunc:i8 RCX:i64:$amt)))
- // Emits: (SHLD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 23 cost = 1 size = 3
- if (N01.getOpcode() == ISD::TRUNCATE) {
- SDValue N010 = N01.getOperand(0);
- if (N010.getOpcode() == ISD::SUB) {
- SDValue N0100 = N010.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0100);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(64)) {
- SDValue N0101 = N010.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::TRUNCATE) {
- SDValue N110 = N11.getOperand(0);
- if (N0101 == N110 &&
- N01.getValueType() == MVT::i8 &&
- N010.getValueType() == MVT::i64 &&
- N11.getValueType() == MVT::i8 &&
- N110.getValueType() == MVT::i64) {
- SDNode *Result = Emit_159(N, X86::SHLD64rrCL, MVT::i64);
- return Result;
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i64 (srl:i64 GR64:i64:$src1, CL:i8:$amt), (shl:i64 GR64:i64:$src2, (sub:i8 64:i8, CL:i8:$amt)))
- // Emits: (SHRD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 17 cost = 1 size = 3
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SUB) {
- SDValue N110 = N11.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N110);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(64)) {
- SDValue N111 = N11.getOperand(1);
- if (N01 == N111 &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_150(N, X86::SHRD64rrCL, MVT::i64);
- return Result;
- }
- }
- }
- }
- }
- }
- if (N0.getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
-
- // Pattern: (or:i64 (shl:i64 GR64:i64:$src1, CL:i8:$amt), (srl:i64 GR64:i64:$src2, (sub:i8 64:i8, CL:i8:$amt)))
- // Emits: (SHLD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 17 cost = 1 size = 3
- {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SUB) {
- SDValue N110 = N11.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N110);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(64)) {
- SDValue N111 = N11.getOperand(1);
- if (N01 == N111 &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_150(N, X86::SHLD64rrCL, MVT::i64);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i64 (shl:i64 GR64:i64:$src2, (sub:i8 64:i8, CL:i8:$amt)), (srl:i64 GR64:i64:$src1, CL:i8:$amt))
- // Emits: (SHRD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 17 cost = 1 size = 3
- if (N01.getOpcode() == ISD::SUB) {
- SDValue N010 = N01.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N010);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(64)) {
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N011 == N11 &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_153(N, X86::SHRD64rrCL, MVT::i64);
- return Result;
- }
- }
- }
- }
- }
- }
-
- // Pattern: (or:i64 (srl:i64 GR64:i64:$src2, (sub:i8 64:i8, CL:i8:$amt)), (shl:i64 GR64:i64:$src1, CL:i8:$amt))
- // Emits: (SHLD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
- // Pattern complexity = 17 cost = 1 size = 3
- if (N0.getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::SUB) {
- SDValue N010 = N01.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N010);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(64)) {
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N011 == N11 &&
- N01.getValueType() == MVT::i8 &&
- N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_153(N, X86::SHLD64rrCL, MVT::i64);
- return Result;
- }
- }
- }
- }
- }
- }
- }
// Pattern: (or:i64 (srl:i64 GR64:i64:$src1, (imm:i8):$amt1), (shl:i64 GR64:i64:$src2, (imm:i8):$amt2))<<P:Predicate_shrd>>
// Emits: (SHRD64rri8:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$amt1)
// Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shrd(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ if (Predicate_shrd(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_152(N, X86::SHRD64rri8, MVT::i64);
+ SDNode *Result = Emit_151(N, X86::SHRD64rri8, MVT::i64);
return Result;
}
}
@@ -28303,20 +28091,20 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
// Pattern: (or:i64 (shl:i64 GR64:i64:$src1, (imm:i8):$amt1), (srl:i64 GR64:i64:$src2, (imm:i8):$amt2))<<P:Predicate_shld>>
// Emits: (SHLD64rri8:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$amt1)
// Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shld(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ if (Predicate_shld(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_152(N, X86::SHLD64rri8, MVT::i64);
+ SDNode *Result = Emit_151(N, X86::SHLD64rri8, MVT::i64);
return Result;
}
}
@@ -28327,20 +28115,20 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
// Pattern: (or:i64 (shl:i64 GR64:i64:$src2, (imm:i8):$amt2), (srl:i64 GR64:i64:$src1, (imm:i8):$amt1))<<P:Predicate_shrd>>
// Emits: (SHRD64rri8:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$amt1)
// Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shrd(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SHL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SRL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ if (Predicate_shrd(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_155(N, X86::SHRD64rri8, MVT::i64);
+ SDNode *Result = Emit_154(N, X86::SHRD64rri8, MVT::i64);
return Result;
}
}
@@ -28351,20 +28139,20 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
// Pattern: (or:i64 (srl:i64 GR64:i64:$src2, (imm:i8):$amt2), (shl:i64 GR64:i64:$src1, (imm:i8):$amt1))<<P:Predicate_shld>>
// Emits: (SHLD64rri8:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$amt1)
// Pattern complexity = 16 cost = 1 size = 3
- if (Predicate_shld(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SRL) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ if (Predicate_shld(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
N01.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_155(N, X86::SHLD64rri8, MVT::i64);
+ SDNode *Result = Emit_154(N, X86::SHLD64rri8, MVT::i64);
return Result;
}
}
@@ -28380,15 +28168,45 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
}
+ if (Predicate_or_is_add(N)) {
+ {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
+
+ // Pattern: (or:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)<<P:Predicate_or_is_add>>
+ // Emits: (ADD64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (Predicate_i64immSExt8(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::ADD64ri8, MVT::i64);
+ return Result;
+ }
+
+ // Pattern: (or:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)<<P:Predicate_or_is_add>>
+ // Emits: (ADD64ri32:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
+ // Pattern complexity = 13 cost = 1 size = 3
+ if (Predicate_i64immSExt32(N1.getNode())) {
+ SDNode *Result = Emit_12(N, X86::ADD64ri32, MVT::i64);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (or:i64 GR64:i64:$src1, GR64:i64:$src2)<<P:Predicate_or_is_add>>
+ // Emits: (ADD64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
+ // Pattern complexity = 9 cost = 1 size = 3
+ SDNode *Result = Emit_1(N, X86::ADD64rr, MVT::i64);
+ return Result;
+ }
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (or:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Emits: (OR64ri8:i64 GR64:i64:$src1, (imm:i64):$src2)
@@ -28415,23 +28233,23 @@ SDNode *Select_ISD_OR_i64(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_OR_v1i64(const SDValue &N) {
+SDNode *Select_ISD_OR_v1i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (or:v1i64 VR64:v1i64:$src1, (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (MMX_PORrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -28448,13 +28266,13 @@ SDNode *Select_ISD_OR_v1i64(const SDValue &N) {
// Pattern: (or:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR64:v1i64:$src1)
// Emits: (MMX_PORrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -28480,25 +28298,25 @@ SDNode *Select_ISD_OR_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_OR_v2i64(const SDValue &N) {
+SDNode *Select_ISD_OR_v2i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
// Pattern: (or:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (ORPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -28506,7 +28324,7 @@ SDNode *Select_ISD_OR_v2i64(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_56(N, X86::ORPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_57(N, X86::ORPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -28518,18 +28336,18 @@ SDNode *Select_ISD_OR_v2i64(const SDValue &N) {
// Emits: (ORPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -28537,7 +28355,7 @@ SDNode *Select_ISD_OR_v2i64(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N00.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_56(N, X86::ORPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_57(N, X86::ORPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -28549,26 +28367,26 @@ SDNode *Select_ISD_OR_v2i64(const SDValue &N) {
// Emits: (ORPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
if (N10.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_61(N, X86::ORPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_62(N, X86::ORPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -28577,30 +28395,30 @@ SDNode *Select_ISD_OR_v2i64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (or:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v2f64:$src1))
// Emits: (ORPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
if (N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_61(N, X86::ORPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_62(N, X86::ORPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -28612,15 +28430,15 @@ SDNode *Select_ISD_OR_v2i64(const SDValue &N) {
// Emits: (PORrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -28637,14 +28455,14 @@ SDNode *Select_ISD_OR_v2i64(const SDValue &N) {
// Pattern: (or:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
// Emits: (PORrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -28663,15 +28481,15 @@ SDNode *Select_ISD_OR_v2i64(const SDValue &N) {
// Emits: (ORPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 9 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
if (N00.getValueType() == MVT::v2f64 &&
N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_58(N, X86::ORPDrr, MVT::v2i64);
+ SDNode *Result = Emit_59(N, X86::ORPDrr, MVT::v2i64);
return Result;
}
}
@@ -28698,28 +28516,28 @@ SDNode *Select_ISD_OR_v2i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_160(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_157(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 6);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 6);
}
-SDNode *Select_ISD_PREFETCH(const SDValue &N) {
+SDNode *Select_ISD_PREFETCH(SDNode *N) {
if ((Subtarget->hasSSE1())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDValue N3 = N.getOperand(3);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N3);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N3 = N->getOperand(3);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N3.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -28728,7 +28546,7 @@ SDNode *Select_ISD_PREFETCH(const SDValue &N) {
// Pattern complexity = 29 cost = 1 size = 3
if (CN1 == INT64_C(3) &&
N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_160(N, X86::PREFETCHT0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_157(N, X86::PREFETCHT0, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -28737,7 +28555,7 @@ SDNode *Select_ISD_PREFETCH(const SDValue &N) {
// Pattern complexity = 29 cost = 1 size = 3
if (CN1 == INT64_C(2) &&
N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_160(N, X86::PREFETCHT1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_157(N, X86::PREFETCHT1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -28746,7 +28564,7 @@ SDNode *Select_ISD_PREFETCH(const SDValue &N) {
// Pattern complexity = 29 cost = 1 size = 3
if (CN1 == INT64_C(1) &&
N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_160(N, X86::PREFETCHT2, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_157(N, X86::PREFETCHT2, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -28755,7 +28573,7 @@ SDNode *Select_ISD_PREFETCH(const SDValue &N) {
// Pattern complexity = 29 cost = 1 size = 3
if (CN1 == INT64_C(0) &&
N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_160(N, X86::PREFETCHNTA, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_157(N, X86::PREFETCHNTA, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -28767,36 +28585,36 @@ SDNode *Select_ISD_PREFETCH(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_161(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_158(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Chain = CurDAG->getEntryNode();
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::CL, N1, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::CL, N1, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, InFlag);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, InFlag);
}
-DISABLE_INLINE SDNode *Emit_162(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_159(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1);
}
-SDNode *Select_ISD_ROTL_i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ROTL_i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (rotl:i8 GR8:i8:$src1, 1:i8)
// Emits: (ROL8r1:i8 GR8:i8:$src1)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_94(N, X86::ROL8r1, MVT::i8);
+ SDNode *Result = Emit_93(N, X86::ROL8r1, MVT::i8);
return Result;
}
}
@@ -28805,9 +28623,9 @@ SDNode *Select_ISD_ROTL_i8(const SDValue &N) {
// Pattern: (rotl:i8 GR8:i8:$src1, (imm:i8):$src2)
// Emits: (ROL8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::ROL8ri, MVT::i8);
+ SDNode *Result = Emit_159(N, X86::ROL8ri, MVT::i8);
return Result;
}
@@ -28815,7 +28633,7 @@ SDNode *Select_ISD_ROTL_i8(const SDValue &N) {
// Emits: (ROL8rCL:i8 GR8:i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::ROL8rCL, MVT::i8);
+ SDNode *Result = Emit_158(N, X86::ROL8rCL, MVT::i8);
return Result;
}
@@ -28823,20 +28641,20 @@ SDNode *Select_ISD_ROTL_i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ROTL_i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ROTL_i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (rotl:i16 GR16:i16:$src1, 1:i8)
// Emits: (ROL16r1:i16 GR16:i16:$src1)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_94(N, X86::ROL16r1, MVT::i16);
+ SDNode *Result = Emit_93(N, X86::ROL16r1, MVT::i16);
return Result;
}
}
@@ -28845,9 +28663,9 @@ SDNode *Select_ISD_ROTL_i16(const SDValue &N) {
// Pattern: (rotl:i16 GR16:i16:$src1, (imm:i8):$src2)
// Emits: (ROL16ri:i16 GR16:i16:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::ROL16ri, MVT::i16);
+ SDNode *Result = Emit_159(N, X86::ROL16ri, MVT::i16);
return Result;
}
@@ -28855,7 +28673,7 @@ SDNode *Select_ISD_ROTL_i16(const SDValue &N) {
// Emits: (ROL16rCL:i16 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::ROL16rCL, MVT::i16);
+ SDNode *Result = Emit_158(N, X86::ROL16rCL, MVT::i16);
return Result;
}
@@ -28863,20 +28681,20 @@ SDNode *Select_ISD_ROTL_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ROTL_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ROTL_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (rotl:i32 GR32:i32:$src1, 1:i8)
// Emits: (ROL32r1:i32 GR32:i32:$src1)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_94(N, X86::ROL32r1, MVT::i32);
+ SDNode *Result = Emit_93(N, X86::ROL32r1, MVT::i32);
return Result;
}
}
@@ -28885,9 +28703,9 @@ SDNode *Select_ISD_ROTL_i32(const SDValue &N) {
// Pattern: (rotl:i32 GR32:i32:$src1, (imm:i8):$src2)
// Emits: (ROL32ri:i32 GR32:i32:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::ROL32ri, MVT::i32);
+ SDNode *Result = Emit_159(N, X86::ROL32ri, MVT::i32);
return Result;
}
@@ -28895,7 +28713,7 @@ SDNode *Select_ISD_ROTL_i32(const SDValue &N) {
// Emits: (ROL32rCL:i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::ROL32rCL, MVT::i32);
+ SDNode *Result = Emit_158(N, X86::ROL32rCL, MVT::i32);
return Result;
}
@@ -28903,20 +28721,20 @@ SDNode *Select_ISD_ROTL_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ROTL_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ROTL_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (rotl:i64 GR64:i64:$src1, 1:i8)
// Emits: (ROL64r1:i64 GR64:i64:$src1)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_94(N, X86::ROL64r1, MVT::i64);
+ SDNode *Result = Emit_93(N, X86::ROL64r1, MVT::i64);
return Result;
}
}
@@ -28925,9 +28743,9 @@ SDNode *Select_ISD_ROTL_i64(const SDValue &N) {
// Pattern: (rotl:i64 GR64:i64:$src1, (imm:i8):$src2)
// Emits: (ROL64ri:i64 GR64:i64:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::ROL64ri, MVT::i64);
+ SDNode *Result = Emit_159(N, X86::ROL64ri, MVT::i64);
return Result;
}
@@ -28935,7 +28753,7 @@ SDNode *Select_ISD_ROTL_i64(const SDValue &N) {
// Emits: (ROL64rCL:i64 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::ROL64rCL, MVT::i64);
+ SDNode *Result = Emit_158(N, X86::ROL64rCL, MVT::i64);
return Result;
}
@@ -28943,20 +28761,20 @@ SDNode *Select_ISD_ROTL_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ROTR_i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ROTR_i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (rotr:i8 GR8:i8:$src1, 1:i8)
// Emits: (ROR8r1:i8 GR8:i8:$src1)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_94(N, X86::ROR8r1, MVT::i8);
+ SDNode *Result = Emit_93(N, X86::ROR8r1, MVT::i8);
return Result;
}
}
@@ -28965,9 +28783,9 @@ SDNode *Select_ISD_ROTR_i8(const SDValue &N) {
// Pattern: (rotr:i8 GR8:i8:$src1, (imm:i8):$src2)
// Emits: (ROR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::ROR8ri, MVT::i8);
+ SDNode *Result = Emit_159(N, X86::ROR8ri, MVT::i8);
return Result;
}
@@ -28975,7 +28793,7 @@ SDNode *Select_ISD_ROTR_i8(const SDValue &N) {
// Emits: (ROR8rCL:i8 GR8:i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::ROR8rCL, MVT::i8);
+ SDNode *Result = Emit_158(N, X86::ROR8rCL, MVT::i8);
return Result;
}
@@ -28983,20 +28801,20 @@ SDNode *Select_ISD_ROTR_i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ROTR_i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ROTR_i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (rotr:i16 GR16:i16:$src1, 1:i8)
// Emits: (ROR16r1:i16 GR16:i16:$src1)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_94(N, X86::ROR16r1, MVT::i16);
+ SDNode *Result = Emit_93(N, X86::ROR16r1, MVT::i16);
return Result;
}
}
@@ -29005,9 +28823,9 @@ SDNode *Select_ISD_ROTR_i16(const SDValue &N) {
// Pattern: (rotr:i16 GR16:i16:$src1, (imm:i8):$src2)
// Emits: (ROR16ri:i16 GR16:i16:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::ROR16ri, MVT::i16);
+ SDNode *Result = Emit_159(N, X86::ROR16ri, MVT::i16);
return Result;
}
@@ -29015,7 +28833,7 @@ SDNode *Select_ISD_ROTR_i16(const SDValue &N) {
// Emits: (ROR16rCL:i16 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::ROR16rCL, MVT::i16);
+ SDNode *Result = Emit_158(N, X86::ROR16rCL, MVT::i16);
return Result;
}
@@ -29023,20 +28841,20 @@ SDNode *Select_ISD_ROTR_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ROTR_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ROTR_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (rotr:i32 GR32:i32:$src1, 1:i8)
// Emits: (ROR32r1:i32 GR32:i32:$src1)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_94(N, X86::ROR32r1, MVT::i32);
+ SDNode *Result = Emit_93(N, X86::ROR32r1, MVT::i32);
return Result;
}
}
@@ -29045,9 +28863,9 @@ SDNode *Select_ISD_ROTR_i32(const SDValue &N) {
// Pattern: (rotr:i32 GR32:i32:$src1, (imm:i8):$src2)
// Emits: (ROR32ri:i32 GR32:i32:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::ROR32ri, MVT::i32);
+ SDNode *Result = Emit_159(N, X86::ROR32ri, MVT::i32);
return Result;
}
@@ -29055,7 +28873,7 @@ SDNode *Select_ISD_ROTR_i32(const SDValue &N) {
// Emits: (ROR32rCL:i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::ROR32rCL, MVT::i32);
+ SDNode *Result = Emit_158(N, X86::ROR32rCL, MVT::i32);
return Result;
}
@@ -29063,20 +28881,20 @@ SDNode *Select_ISD_ROTR_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ROTR_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_ROTR_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (rotr:i64 GR64:i64:$src1, 1:i8)
// Emits: (ROR64r1:i64 GR64:i64:$src1)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_94(N, X86::ROR64r1, MVT::i64);
+ SDNode *Result = Emit_93(N, X86::ROR64r1, MVT::i64);
return Result;
}
}
@@ -29085,9 +28903,9 @@ SDNode *Select_ISD_ROTR_i64(const SDValue &N) {
// Pattern: (rotr:i64 GR64:i64:$src1, (imm:i8):$src2)
// Emits: (ROR64ri:i64 GR64:i64:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::ROR64ri, MVT::i64);
+ SDNode *Result = Emit_159(N, X86::ROR64ri, MVT::i64);
return Result;
}
@@ -29095,7 +28913,7 @@ SDNode *Select_ISD_ROTR_i64(const SDValue &N) {
// Emits: (ROR64rCL:i64 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::ROR64rCL, MVT::i64);
+ SDNode *Result = Emit_158(N, X86::ROR64rCL, MVT::i64);
return Result;
}
@@ -29103,20 +28921,20 @@ SDNode *Select_ISD_ROTR_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i32(const SDValue &N) {
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i32(SDNode *N) {
// Pattern: (scalar_to_vector:v2i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
// Emits: (MMX_MOVD64rm:v2i32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -29124,7 +28942,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i32(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_78(N, X86::MMX_MOVD64rm, MVT::v2i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::MMX_MOVD64rm, MVT::v2i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -29135,9 +28953,9 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i32(const SDValue &N) {
// Emits: (MMX_MOVD64rr:v2i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_71(N, X86::MMX_MOVD64rr, MVT::v2i32);
+ SDNode *Result = Emit_72(N, X86::MMX_MOVD64rr, MVT::v2i32);
return Result;
}
}
@@ -29146,20 +28964,20 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i32(const SDValue &N) {
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i32(SDNode *N) {
// Pattern: (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
// Emits: (MOVDI2PDIrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -29167,7 +28985,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i32(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_78(N, X86::MOVDI2PDIrm, MVT::v4i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::MOVDI2PDIrm, MVT::v4i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -29178,9 +28996,9 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i32(const SDValue &N) {
// Emits: (MOVDI2PDIrr:v4i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_71(N, X86::MOVDI2PDIrr, MVT::v4i32);
+ SDNode *Result = Emit_72(N, X86::MOVDI2PDIrr, MVT::v4i32);
return Result;
}
}
@@ -29189,11 +29007,11 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v1i64(const SDValue &N) {
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v1i64(SDNode *N) {
if ((Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_71(N, X86::MMX_MOVD64rrv164, MVT::v1i64);
+ SDNode *Result = Emit_72(N, X86::MMX_MOVD64rrv164, MVT::v1i64);
return Result;
}
}
@@ -29202,26 +29020,26 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v1i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_163(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N00);
+DISABLE_INLINE SDNode *Emit_160(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N00);
}
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i64(const SDValue &N) {
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i64(SDNode *N) {
// Pattern: (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
// Emits: (MOVQI2PQIrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -29229,23 +29047,23 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i64(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_78(N, X86::MOVQI2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::MOVQI2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
if (N0.getValueType() == MVT::i64) {
// Pattern: (scalar_to_vector:v2i64 (bitconvert:i64 VR64:v8i8:$src))
// Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
// Pattern complexity = 6 cost = 1 size = 3
if (N00.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_163(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
+ SDNode *Result = Emit_160(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
return Result;
}
@@ -29253,7 +29071,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i64(const SDValue &N) {
// Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
// Pattern complexity = 6 cost = 1 size = 3
if (N00.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_163(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
+ SDNode *Result = Emit_160(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
return Result;
}
@@ -29261,7 +29079,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i64(const SDValue &N) {
// Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
// Pattern complexity = 6 cost = 1 size = 3
if (N00.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_163(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
+ SDNode *Result = Emit_160(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
return Result;
}
@@ -29269,7 +29087,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i64(const SDValue &N) {
// Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
// Pattern complexity = 6 cost = 1 size = 3
if (N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_163(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
+ SDNode *Result = Emit_160(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
return Result;
}
}
@@ -29280,9 +29098,9 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i64(const SDValue &N) {
// Emits: (MOV64toPQIrr:v2i64 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_71(N, X86::MOV64toPQIrr, MVT::v2i64);
+ SDNode *Result = Emit_72(N, X86::MOV64toPQIrr, MVT::v2i64);
return Result;
}
}
@@ -29291,21 +29109,21 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v4f32(const SDValue &N) {
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v4f32(SDNode *N) {
// Pattern: (scalar_to_vector:v4f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>)
// Emits: (MOVSS2PSrm:v4f32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_loadf32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -29313,7 +29131,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v4f32(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_78(N, X86::MOVSS2PSrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::MOVSS2PSrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -29324,9 +29142,9 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v4f32(const SDValue &N) {
// Emits: (MOVSS2PSrr:v4f32 FR32:f32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_71(N, X86::MOVSS2PSrr, MVT::v4f32);
+ SDNode *Result = Emit_72(N, X86::MOVSS2PSrr, MVT::v4f32);
return Result;
}
}
@@ -29335,21 +29153,21 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f64(const SDValue &N) {
+SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f64(SDNode *N) {
// Pattern: (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)
// Emits: (MOVSD2PDrm:v2f64 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_loadf64(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -29357,7 +29175,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f64(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_78(N, X86::MOVSD2PDrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::MOVSD2PDrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -29368,9 +29186,9 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f64(const SDValue &N) {
// Emits: (MOVSD2PDrr:v2f64 FR64:f64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_71(N, X86::MOVSD2PDrr, MVT::v2f64);
+ SDNode *Result = Emit_72(N, X86::MOVSD2PDrr, MVT::v2f64);
return Result;
}
}
@@ -29379,38 +29197,38 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_164(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N0);
+DISABLE_INLINE SDNode *Emit_161(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N0);
}
-DISABLE_INLINE SDNode *Emit_165(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_162(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue Chain = CurDAG->getEntryNode();
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N1.getDebugLoc(), X86::CL, N10, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N1.getNode()->getDebugLoc(), X86::CL, N10, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, InFlag);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, InFlag);
}
-SDNode *Select_ISD_SHL_i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SHL_i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (shl:i8 GR8:i8:$src1, (and:i8 CL:i8:$amt, 31:i8))
// Emits: (SHL8rCL:i8 GR8:i8:$src1)
// Pattern complexity = 11 cost = 1 size = 3
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(31)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_165(N, X86::SHL8rCL, MVT::i8);
+ SDNode *Result = Emit_162(N, X86::SHL8rCL, MVT::i8);
return Result;
}
}
@@ -29419,12 +29237,12 @@ SDNode *Select_ISD_SHL_i8(const SDValue &N) {
// Emits: (ADD8rr:i8 GR8:i8:$src1, GR8:i8:$src1)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_164(N, X86::ADD8rr, MVT::i8);
+ SDNode *Result = Emit_161(N, X86::ADD8rr, MVT::i8);
return Result;
}
}
@@ -29433,9 +29251,9 @@ SDNode *Select_ISD_SHL_i8(const SDValue &N) {
// Pattern: (shl:i8 GR8:i8:$src1, (imm:i8):$src2)
// Emits: (SHL8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHL8ri, MVT::i8);
+ SDNode *Result = Emit_159(N, X86::SHL8ri, MVT::i8);
return Result;
}
@@ -29443,7 +29261,7 @@ SDNode *Select_ISD_SHL_i8(const SDValue &N) {
// Emits: (SHL8rCL:i8 GR8:i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::SHL8rCL, MVT::i8);
+ SDNode *Result = Emit_158(N, X86::SHL8rCL, MVT::i8);
return Result;
}
@@ -29451,21 +29269,21 @@ SDNode *Select_ISD_SHL_i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SHL_i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SHL_i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (shl:i16 GR16:i16:$src1, (and:i8 CL:i8:$amt, 31:i8))
// Emits: (SHL16rCL:i16 GR16:i16:$src1)
// Pattern complexity = 11 cost = 1 size = 3
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(31)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_165(N, X86::SHL16rCL, MVT::i16);
+ SDNode *Result = Emit_162(N, X86::SHL16rCL, MVT::i16);
return Result;
}
}
@@ -29474,12 +29292,12 @@ SDNode *Select_ISD_SHL_i16(const SDValue &N) {
// Emits: (ADD16rr:i16 GR16:i16:$src1, GR16:i16:$src1)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_164(N, X86::ADD16rr, MVT::i16);
+ SDNode *Result = Emit_161(N, X86::ADD16rr, MVT::i16);
return Result;
}
}
@@ -29488,9 +29306,9 @@ SDNode *Select_ISD_SHL_i16(const SDValue &N) {
// Pattern: (shl:i16 GR16:i16:$src1, (imm:i8):$src2)
// Emits: (SHL16ri:i16 GR16:i16:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHL16ri, MVT::i16);
+ SDNode *Result = Emit_159(N, X86::SHL16ri, MVT::i16);
return Result;
}
@@ -29498,7 +29316,7 @@ SDNode *Select_ISD_SHL_i16(const SDValue &N) {
// Emits: (SHL16rCL:i16 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::SHL16rCL, MVT::i16);
+ SDNode *Result = Emit_158(N, X86::SHL16rCL, MVT::i16);
return Result;
}
@@ -29506,7 +29324,7 @@ SDNode *Select_ISD_SHL_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SHL_i32(const SDValue &N) {
+SDNode *Select_ISD_SHL_i32(SDNode *N) {
// Pattern: lea32addr:i32:$src
// Emits: (LEA64_32r:i32 lea32addr:i32:$src)
@@ -29516,7 +29334,7 @@ SDNode *Select_ISD_SHL_i32(const SDValue &N) {
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
@@ -29530,25 +29348,25 @@ SDNode *Select_ISD_SHL_i32(const SDValue &N) {
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
}
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (shl:i32 GR32:i32:$src1, (and:i8 CL:i8:$amt, 31:i8))
// Emits: (SHL32rCL:i32 GR32:i32:$src1)
// Pattern complexity = 11 cost = 1 size = 3
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(31)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_165(N, X86::SHL32rCL, MVT::i32);
+ SDNode *Result = Emit_162(N, X86::SHL32rCL, MVT::i32);
return Result;
}
}
@@ -29557,12 +29375,12 @@ SDNode *Select_ISD_SHL_i32(const SDValue &N) {
// Emits: (ADD32rr:i32 GR32:i32:$src1, GR32:i32:$src1)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_164(N, X86::ADD32rr, MVT::i32);
+ SDNode *Result = Emit_161(N, X86::ADD32rr, MVT::i32);
return Result;
}
}
@@ -29571,9 +29389,9 @@ SDNode *Select_ISD_SHL_i32(const SDValue &N) {
// Pattern: (shl:i32 GR32:i32:$src1, (imm:i8):$src2)
// Emits: (SHL32ri:i32 GR32:i32:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHL32ri, MVT::i32);
+ SDNode *Result = Emit_159(N, X86::SHL32ri, MVT::i32);
return Result;
}
@@ -29581,7 +29399,7 @@ SDNode *Select_ISD_SHL_i32(const SDValue &N) {
// Emits: (SHL32rCL:i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::SHL32rCL, MVT::i32);
+ SDNode *Result = Emit_158(N, X86::SHL32rCL, MVT::i32);
return Result;
}
@@ -29589,7 +29407,7 @@ SDNode *Select_ISD_SHL_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SHL_i64(const SDValue &N) {
+SDNode *Select_ISD_SHL_i64(SDNode *N) {
// Pattern: lea64addr:i64:$src
// Emits: (LEA64r:i64 lea64addr:i64:$src)
@@ -29599,25 +29417,25 @@ SDNode *Select_ISD_SHL_i64(const SDValue &N) {
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
}
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (shl:i64 GR64:i64:$src1, (and:i8 CL:i8:$amt, 63:i8))
// Emits: (SHL64rCL:i64 GR64:i64:$src1)
// Pattern complexity = 11 cost = 1 size = 3
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(63)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_165(N, X86::SHL64rCL, MVT::i64);
+ SDNode *Result = Emit_162(N, X86::SHL64rCL, MVT::i64);
return Result;
}
}
@@ -29626,12 +29444,12 @@ SDNode *Select_ISD_SHL_i64(const SDValue &N) {
// Emits: (ADD64rr:i64 GR64:i64:$src1, GR64:i64:$src1)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_164(N, X86::ADD64rr, MVT::i64);
+ SDNode *Result = Emit_161(N, X86::ADD64rr, MVT::i64);
return Result;
}
}
@@ -29640,9 +29458,9 @@ SDNode *Select_ISD_SHL_i64(const SDValue &N) {
// Pattern: (shl:i64 GR64:i64:$src1, (imm:i8):$src2)
// Emits: (SHL64ri:i64 GR64:i64:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHL64ri, MVT::i64);
+ SDNode *Result = Emit_159(N, X86::SHL64ri, MVT::i64);
return Result;
}
@@ -29650,7 +29468,7 @@ SDNode *Select_ISD_SHL_i64(const SDValue &N) {
// Emits: (SHL64rCL:i64 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::SHL64rCL, MVT::i64);
+ SDNode *Result = Emit_158(N, X86::SHL64rCL, MVT::i64);
return Result;
}
@@ -29658,10 +29476,10 @@ SDNode *Select_ISD_SHL_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SIGN_EXTEND_i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_SIGN_EXTEND_i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_71(N, X86::MOVSX16rr8, MVT::i16);
+ SDNode *Result = Emit_72(N, X86::MOVSX16rr8, MVT::i16);
return Result;
}
@@ -29669,14 +29487,14 @@ SDNode *Select_ISD_SIGN_EXTEND_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SIGN_EXTEND_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_SIGN_EXTEND_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (sext:i32 GR8:i8:$src)
// Emits: (MOVSX32rr8:i32 GR8:i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_71(N, X86::MOVSX32rr8, MVT::i32);
+ SDNode *Result = Emit_72(N, X86::MOVSX32rr8, MVT::i32);
return Result;
}
@@ -29684,7 +29502,7 @@ SDNode *Select_ISD_SIGN_EXTEND_i32(const SDValue &N) {
// Emits: (MOVSX32rr16:i32 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_71(N, X86::MOVSX32rr16, MVT::i32);
+ SDNode *Result = Emit_72(N, X86::MOVSX32rr16, MVT::i32);
return Result;
}
@@ -29692,14 +29510,14 @@ SDNode *Select_ISD_SIGN_EXTEND_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SIGN_EXTEND_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_SIGN_EXTEND_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (sext:i64 GR8:i8:$src)
// Emits: (MOVSX64rr8:i64 GR8:i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_71(N, X86::MOVSX64rr8, MVT::i64);
+ SDNode *Result = Emit_72(N, X86::MOVSX64rr8, MVT::i64);
return Result;
}
@@ -29707,7 +29525,7 @@ SDNode *Select_ISD_SIGN_EXTEND_i64(const SDValue &N) {
// Emits: (MOVSX64rr16:i64 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_71(N, X86::MOVSX64rr16, MVT::i64);
+ SDNode *Result = Emit_72(N, X86::MOVSX64rr16, MVT::i64);
return Result;
}
@@ -29715,7 +29533,7 @@ SDNode *Select_ISD_SIGN_EXTEND_i64(const SDValue &N) {
// Emits: (MOVSX64rr32:i64 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_71(N, X86::MOVSX64rr32, MVT::i64);
+ SDNode *Result = Emit_72(N, X86::MOVSX64rr32, MVT::i64);
return Result;
}
@@ -29723,32 +29541,32 @@ SDNode *Select_ISD_SIGN_EXTEND_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_166(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_163(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
SDValue Tmp3 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- SDValue Tmp4(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp2, Tmp3), 0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc2, VT2, Tmp4);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp2, Tmp3), 0);
+ return CurDAG->SelectNodeTo(N, Opc2, VT2, Tmp4);
}
-DISABLE_INLINE SDNode *Emit_167(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_164(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2);
}
-SDNode *Select_ISD_SIGN_EXTEND_INREG_i16(const SDValue &N) {
+SDNode *Select_ISD_SIGN_EXTEND_INREG_i16(SDNode *N) {
// Pattern: (sext_inreg:i16 GR16:i16:$src, i8:Other)
// Emits: (MOVSX16rr8:i16 (EXTRACT_SUBREG:i8 GR16:i16:$src, 1:i32))
// Pattern complexity = 3 cost = 2 size = 3
if ((Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
- SDNode *Result = Emit_167(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX16rr8, MVT::i8, MVT::i16);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
+ SDNode *Result = Emit_164(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX16rr8, MVT::i8, MVT::i16);
return Result;
}
}
@@ -29757,10 +29575,10 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i16(const SDValue &N) {
// Emits: (MOVSX16rr8:i16 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 1:i32))
// Pattern complexity = 3 cost = 3 size = 3
if ((!Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
- SDNode *Result = Emit_166(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX16rr8, MVT::i16, MVT::i8, MVT::i16);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
+ SDNode *Result = Emit_163(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX16rr8, MVT::i16, MVT::i8, MVT::i16);
return Result;
}
}
@@ -29769,32 +29587,32 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i16(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_168(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_165(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(0x3ULL, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_169(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_166(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(X86::GR32_ABCDRegClassID, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
SDValue Tmp3 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- SDValue Tmp4(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp2, Tmp3), 0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc2, VT2, Tmp4);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp2, Tmp3), 0);
+ return CurDAG->SelectNodeTo(N, Opc2, VT2, Tmp4);
}
-SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
+SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(SDNode *N) {
// Pattern: (sext_inreg:i32 GR32:i32:$src, i16:Other)
// Emits: (MOVSX32rr16:i32 (EXTRACT_SUBREG:i16 GR32:i32:$src, 3:i32))
// Pattern complexity = 3 cost = 2 size = 3
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
- SDNode *Result = Emit_168(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX32rr16, MVT::i16, MVT::i32);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_165(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX32rr16, MVT::i16, MVT::i32);
return Result;
}
}
@@ -29803,10 +29621,10 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
// Emits: (MOVSX32rr8:i32 (EXTRACT_SUBREG:i8 GR32:i32:$src, 1:i32))
// Pattern complexity = 3 cost = 2 size = 3
if ((Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
- SDNode *Result = Emit_167(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX32rr8, MVT::i8, MVT::i32);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
+ SDNode *Result = Emit_164(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX32rr8, MVT::i8, MVT::i32);
return Result;
}
}
@@ -29815,10 +29633,10 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
// Emits: (MOVSX32rr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR32:i32:$src, GR32_ABCD:i32), 1:i32))
// Pattern complexity = 3 cost = 3 size = 3
if ((!Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
- SDNode *Result = Emit_169(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX32rr8, MVT::i32, MVT::i8, MVT::i32);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
+ SDNode *Result = Emit_166(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX32rr8, MVT::i32, MVT::i8, MVT::i32);
return Result;
}
}
@@ -29827,38 +29645,38 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_170(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_167(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2);
}
-SDNode *Select_ISD_SIGN_EXTEND_INREG_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SIGN_EXTEND_INREG_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (sext_inreg:i64 GR64:i64:$src, i32:Other)
// Emits: (MOVSX64rr32:i64 (EXTRACT_SUBREG:i32 GR64:i64:$src, 4:i32))
// Pattern complexity = 3 cost = 2 size = 3
- if (cast<VTSDNode>(N1)->getVT() == MVT::i32) {
- SDNode *Result = Emit_170(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX64rr32, MVT::i32, MVT::i64);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_167(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX64rr32, MVT::i32, MVT::i64);
return Result;
}
// Pattern: (sext_inreg:i64 GR64:i64:$src, i16:Other)
// Emits: (MOVSX64rr16:i64 (EXTRACT_SUBREG:i16 GR64:i64:$src, 3:i32))
// Pattern complexity = 3 cost = 2 size = 3
- if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
- SDNode *Result = Emit_168(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX64rr16, MVT::i16, MVT::i64);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_165(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX64rr16, MVT::i16, MVT::i64);
return Result;
}
// Pattern: (sext_inreg:i64 GR64:i64:$src, i8:Other)
// Emits: (MOVSX64rr8:i64 (EXTRACT_SUBREG:i8 GR64:i64:$src, 1:i32))
// Pattern complexity = 3 cost = 2 size = 3
- if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
- SDNode *Result = Emit_167(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX64rr8, MVT::i8, MVT::i64);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
+ SDNode *Result = Emit_164(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVSX64rr8, MVT::i8, MVT::i64);
return Result;
}
@@ -29866,13 +29684,13 @@ SDNode *Select_ISD_SIGN_EXTEND_INREG_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SINT_TO_FP_f32(const SDValue &N) {
+SDNode *Select_ISD_SINT_TO_FP_f32(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode())) {
// Pattern: (sint_to_fp:f32 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
@@ -29880,7 +29698,7 @@ SDNode *Select_ISD_SINT_TO_FP_f32(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 3
if (Predicate_load(N0.getNode()) &&
Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -29888,7 +29706,7 @@ SDNode *Select_ISD_SINT_TO_FP_f32(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_78(N, X86::CVTSI2SS64rm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::CVTSI2SS64rm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -29897,7 +29715,7 @@ SDNode *Select_ISD_SINT_TO_FP_f32(const SDValue &N) {
// Emits: (CVTSI2SSrm:f32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -29905,7 +29723,7 @@ SDNode *Select_ISD_SINT_TO_FP_f32(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_78(N, X86::CVTSI2SSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::CVTSI2SSrm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -29913,13 +29731,13 @@ SDNode *Select_ISD_SINT_TO_FP_f32(const SDValue &N) {
}
}
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (sint_to_fp:f32 GR64:i64:$src)
// Emits: (CVTSI2SS64rr:f32 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_71(N, X86::CVTSI2SS64rr, MVT::f32);
+ SDNode *Result = Emit_72(N, X86::CVTSI2SS64rr, MVT::f32);
return Result;
}
@@ -29927,7 +29745,7 @@ SDNode *Select_ISD_SINT_TO_FP_f32(const SDValue &N) {
// Emits: (CVTSI2SSrr:f32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_71(N, X86::CVTSI2SSrr, MVT::f32);
+ SDNode *Result = Emit_72(N, X86::CVTSI2SSrr, MVT::f32);
return Result;
}
}
@@ -29936,13 +29754,13 @@ SDNode *Select_ISD_SINT_TO_FP_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SINT_TO_FP_f64(const SDValue &N) {
+SDNode *Select_ISD_SINT_TO_FP_f64(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode())) {
// Pattern: (sint_to_fp:f64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
@@ -29950,7 +29768,7 @@ SDNode *Select_ISD_SINT_TO_FP_f64(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 3
if (Predicate_load(N0.getNode()) &&
Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -29958,7 +29776,7 @@ SDNode *Select_ISD_SINT_TO_FP_f64(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_78(N, X86::CVTSI2SD64rm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::CVTSI2SD64rm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -29967,7 +29785,7 @@ SDNode *Select_ISD_SINT_TO_FP_f64(const SDValue &N) {
// Emits: (CVTSI2SDrm:f64 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -29975,7 +29793,7 @@ SDNode *Select_ISD_SINT_TO_FP_f64(const SDValue &N) {
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_78(N, X86::CVTSI2SDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::CVTSI2SDrm, MVT::f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -29983,13 +29801,13 @@ SDNode *Select_ISD_SINT_TO_FP_f64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (sint_to_fp:f64 GR64:i64:$src)
// Emits: (CVTSI2SD64rr:f64 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_71(N, X86::CVTSI2SD64rr, MVT::f64);
+ SDNode *Result = Emit_72(N, X86::CVTSI2SD64rr, MVT::f64);
return Result;
}
@@ -29997,7 +29815,7 @@ SDNode *Select_ISD_SINT_TO_FP_f64(const SDValue &N) {
// Emits: (CVTSI2SDrr:f64 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_71(N, X86::CVTSI2SDrr, MVT::f64);
+ SDNode *Result = Emit_72(N, X86::CVTSI2SDrr, MVT::f64);
return Result;
}
}
@@ -30006,11 +29824,11 @@ SDNode *Select_ISD_SINT_TO_FP_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SINT_TO_FP_v4f32(const SDValue &N) {
+SDNode *Select_ISD_SINT_TO_FP_v4f32(SDNode *N) {
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_71(N, X86::Int_CVTDQ2PSrr, MVT::v4f32);
+ SDNode *Result = Emit_72(N, X86::Int_CVTDQ2PSrr, MVT::v4f32);
return Result;
}
}
@@ -30019,11 +29837,11 @@ SDNode *Select_ISD_SINT_TO_FP_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SINT_TO_FP_v2f64(const SDValue &N) {
+SDNode *Select_ISD_SINT_TO_FP_v2f64(SDNode *N) {
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_71(N, X86::Int_CVTPI2PDrr, MVT::v2f64);
+ SDNode *Result = Emit_72(N, X86::Int_CVTPI2PDrr, MVT::v2f64);
return Result;
}
}
@@ -30032,21 +29850,21 @@ SDNode *Select_ISD_SINT_TO_FP_v2f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SRA_i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SRA_i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (sra:i8 GR8:i8:$src1, (and:i8 CL:i8:$amt, 31:i8))
// Emits: (SAR8rCL:i8 GR8:i8:$src1)
// Pattern complexity = 11 cost = 1 size = 3
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(31)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_165(N, X86::SAR8rCL, MVT::i8);
+ SDNode *Result = Emit_162(N, X86::SAR8rCL, MVT::i8);
return Result;
}
}
@@ -30055,12 +29873,12 @@ SDNode *Select_ISD_SRA_i8(const SDValue &N) {
// Emits: (SAR8r1:i8 GR8:i8:$src1)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_94(N, X86::SAR8r1, MVT::i8);
+ SDNode *Result = Emit_93(N, X86::SAR8r1, MVT::i8);
return Result;
}
}
@@ -30069,9 +29887,9 @@ SDNode *Select_ISD_SRA_i8(const SDValue &N) {
// Pattern: (sra:i8 GR8:i8:$src1, (imm:i8):$src2)
// Emits: (SAR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SAR8ri, MVT::i8);
+ SDNode *Result = Emit_159(N, X86::SAR8ri, MVT::i8);
return Result;
}
@@ -30079,7 +29897,7 @@ SDNode *Select_ISD_SRA_i8(const SDValue &N) {
// Emits: (SAR8rCL:i8 GR8:i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::SAR8rCL, MVT::i8);
+ SDNode *Result = Emit_158(N, X86::SAR8rCL, MVT::i8);
return Result;
}
@@ -30087,21 +29905,21 @@ SDNode *Select_ISD_SRA_i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SRA_i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SRA_i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (sra:i16 GR16:i16:$src1, (and:i8 CL:i8:$amt, 31:i8))
// Emits: (SAR16rCL:i16 GR16:i16:$src1)
// Pattern complexity = 11 cost = 1 size = 3
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(31)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_165(N, X86::SAR16rCL, MVT::i16);
+ SDNode *Result = Emit_162(N, X86::SAR16rCL, MVT::i16);
return Result;
}
}
@@ -30110,12 +29928,12 @@ SDNode *Select_ISD_SRA_i16(const SDValue &N) {
// Emits: (SAR16r1:i16 GR16:i16:$src1)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_94(N, X86::SAR16r1, MVT::i16);
+ SDNode *Result = Emit_93(N, X86::SAR16r1, MVT::i16);
return Result;
}
}
@@ -30124,9 +29942,9 @@ SDNode *Select_ISD_SRA_i16(const SDValue &N) {
// Pattern: (sra:i16 GR16:i16:$src1, (imm:i8):$src2)
// Emits: (SAR16ri:i16 GR16:i16:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SAR16ri, MVT::i16);
+ SDNode *Result = Emit_159(N, X86::SAR16ri, MVT::i16);
return Result;
}
@@ -30134,7 +29952,7 @@ SDNode *Select_ISD_SRA_i16(const SDValue &N) {
// Emits: (SAR16rCL:i16 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::SAR16rCL, MVT::i16);
+ SDNode *Result = Emit_158(N, X86::SAR16rCL, MVT::i16);
return Result;
}
@@ -30142,21 +29960,21 @@ SDNode *Select_ISD_SRA_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SRA_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SRA_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (sra:i32 GR32:i32:$src1, (and:i8 CL:i8:$amt, 31:i8))
// Emits: (SAR32rCL:i32 GR32:i32:$src1)
// Pattern complexity = 11 cost = 1 size = 3
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(31)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_165(N, X86::SAR32rCL, MVT::i32);
+ SDNode *Result = Emit_162(N, X86::SAR32rCL, MVT::i32);
return Result;
}
}
@@ -30165,12 +29983,12 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
// Emits: (SAR32r1:i32 GR32:i32:$src1)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_94(N, X86::SAR32r1, MVT::i32);
+ SDNode *Result = Emit_93(N, X86::SAR32r1, MVT::i32);
return Result;
}
}
@@ -30179,9 +29997,9 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
// Pattern: (sra:i32 GR32:i32:$src1, (imm:i8):$src2)
// Emits: (SAR32ri:i32 GR32:i32:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SAR32ri, MVT::i32);
+ SDNode *Result = Emit_159(N, X86::SAR32ri, MVT::i32);
return Result;
}
@@ -30189,7 +30007,7 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
// Emits: (SAR32rCL:i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::SAR32rCL, MVT::i32);
+ SDNode *Result = Emit_158(N, X86::SAR32rCL, MVT::i32);
return Result;
}
@@ -30197,21 +30015,21 @@ SDNode *Select_ISD_SRA_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SRA_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SRA_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (sra:i64 GR64:i64:$src1, (and:i8 CL:i8:$amt, 63:i8))
// Emits: (SAR64rCL:i64 GR64:i64:$src1)
// Pattern complexity = 11 cost = 1 size = 3
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(63)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_165(N, X86::SAR64rCL, MVT::i64);
+ SDNode *Result = Emit_162(N, X86::SAR64rCL, MVT::i64);
return Result;
}
}
@@ -30220,12 +30038,12 @@ SDNode *Select_ISD_SRA_i64(const SDValue &N) {
// Emits: (SAR64r1:i64 GR64:i64:$src1)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_94(N, X86::SAR64r1, MVT::i64);
+ SDNode *Result = Emit_93(N, X86::SAR64r1, MVT::i64);
return Result;
}
}
@@ -30234,9 +30052,9 @@ SDNode *Select_ISD_SRA_i64(const SDValue &N) {
// Pattern: (sra:i64 GR64:i64:$src1, (imm:i8):$src2)
// Emits: (SAR64ri:i64 GR64:i64:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SAR64ri, MVT::i64);
+ SDNode *Result = Emit_159(N, X86::SAR64ri, MVT::i64);
return Result;
}
@@ -30244,7 +30062,7 @@ SDNode *Select_ISD_SRA_i64(const SDValue &N) {
// Emits: (SAR64rCL:i64 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::SAR64rCL, MVT::i64);
+ SDNode *Result = Emit_158(N, X86::SAR64rCL, MVT::i64);
return Result;
}
@@ -30252,21 +30070,21 @@ SDNode *Select_ISD_SRA_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SRL_i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SRL_i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (srl:i8 GR8:i8:$src1, (and:i8 CL:i8:$amt, 31:i8))
// Emits: (SHR8rCL:i8 GR8:i8:$src1)
// Pattern complexity = 11 cost = 1 size = 3
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(31)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_165(N, X86::SHR8rCL, MVT::i8);
+ SDNode *Result = Emit_162(N, X86::SHR8rCL, MVT::i8);
return Result;
}
}
@@ -30275,12 +30093,12 @@ SDNode *Select_ISD_SRL_i8(const SDValue &N) {
// Emits: (SHR8r1:i8 GR8:i8:$src1)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_94(N, X86::SHR8r1, MVT::i8);
+ SDNode *Result = Emit_93(N, X86::SHR8r1, MVT::i8);
return Result;
}
}
@@ -30289,9 +30107,9 @@ SDNode *Select_ISD_SRL_i8(const SDValue &N) {
// Pattern: (srl:i8 GR8:i8:$src1, (imm:i8):$src2)
// Emits: (SHR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHR8ri, MVT::i8);
+ SDNode *Result = Emit_159(N, X86::SHR8ri, MVT::i8);
return Result;
}
@@ -30299,7 +30117,7 @@ SDNode *Select_ISD_SRL_i8(const SDValue &N) {
// Emits: (SHR8rCL:i8 GR8:i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::SHR8rCL, MVT::i8);
+ SDNode *Result = Emit_158(N, X86::SHR8rCL, MVT::i8);
return Result;
}
@@ -30307,97 +30125,93 @@ SDNode *Select_ISD_SRL_i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_171(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_168(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, unsigned Opc3, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, MVT::SimpleValueType VT2, MVT::SimpleValueType VT3) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp3), 0);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp3), 0);
SDValue Tmp5 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
- SDValue Tmp6(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp4, Tmp5), 0);
- SDValue Tmp7(CurDAG->getMachineNode(Opc2, N.getDebugLoc(), VT2, Tmp6), 0);
+ SDValue Tmp6(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp4, Tmp5), 0);
+ SDValue Tmp7(CurDAG->getMachineNode(Opc2, N->getDebugLoc(), VT2, Tmp6), 0);
SDValue Tmp8 = CurDAG->getTargetConstant(0x3ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc3, VT3, Tmp7, Tmp8);
+ return CurDAG->SelectNodeTo(N, Opc3, VT3, Tmp7, Tmp8);
}
-SDNode *Select_ISD_SRL_i16(const SDValue &N) {
-
- // Pattern: (srl:i16 GR16:i16:$src1, (and:i8 CL:i8:$amt, 31:i8))
- // Emits: (SHR16rCL:i16 GR16:i16:$src1)
- // Pattern complexity = 11 cost = 1 size = 3
+SDNode *Select_ISD_SRL_i16(SDNode *N) {
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+
+ // Pattern: (srl:i16 GR16:i16:$src1, (and:i8 CL:i8:$amt, 31:i8))
+ // Emits: (SHR16rCL:i16 GR16:i16:$src1)
+ // Pattern complexity = 11 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(31)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_165(N, X86::SHR16rCL, MVT::i16);
+ SDNode *Result = Emit_162(N, X86::SHR16rCL, MVT::i16);
return Result;
}
}
- }
- // Pattern: (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>
- // Emits: (EXTRACT_SUBREG:i16 (MOVZX32rr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32)), 3:i32)
- // Pattern complexity = 9 cost = 4 size = 3
- if ((!Subtarget->is64Bit()) &&
- Predicate_srl_su(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ // Pattern: (srl:i16 GR16:i16:$src1, 1:i8)
+ // Emits: (SHR16r1:i16 GR16:i16:$src1)
+ // Pattern complexity = 8 cost = 1 size = 3
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(8) &&
+ if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_171(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8, MVT::i32, MVT::i16);
+ SDNode *Result = Emit_93(N, X86::SHR16r1, MVT::i16);
return Result;
}
}
}
- // Pattern: (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>
- // Emits: (EXTRACT_SUBREG:i16 (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32)), 3:i32)
- // Pattern complexity = 9 cost = 4 size = 3
- if ((Subtarget->is64Bit()) &&
- Predicate_srl_su(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ // Pattern: (srl:i16 GR16:i16:$src, 8:i8)
+ // Emits: (EXTRACT_SUBREG:i16 (MOVZX32rr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32)), 3:i32)
+ // Pattern complexity = 8 cost = 4 size = 3
+ if ((!Subtarget->is64Bit())) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(8) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_171(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8, MVT::i32, MVT::i16);
+ SDNode *Result = Emit_168(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8, MVT::i32, MVT::i16);
return Result;
}
}
}
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- // Pattern: (srl:i16 GR16:i16:$src1, 1:i8)
- // Emits: (SHR16r1:i16 GR16:i16:$src1)
- // Pattern complexity = 8 cost = 1 size = 3
- {
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ // Pattern: (srl:i16 GR16:i16:$src, 8:i8)
+ // Emits: (EXTRACT_SUBREG:i16 (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32)), 3:i32)
+ // Pattern complexity = 8 cost = 4 size = 3
+ if ((Subtarget->is64Bit())) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(1) &&
+ if (CN1 == INT64_C(8) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_94(N, X86::SHR16r1, MVT::i16);
+ SDNode *Result = Emit_168(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8, MVT::i32, MVT::i16);
return Result;
}
}
}
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (srl:i16 GR16:i16:$src1, (imm:i8):$src2)
// Emits: (SHR16ri:i16 GR16:i16:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHR16ri, MVT::i16);
+ SDNode *Result = Emit_159(N, X86::SHR16ri, MVT::i16);
return Result;
}
@@ -30405,7 +30219,7 @@ SDNode *Select_ISD_SRL_i16(const SDValue &N) {
// Emits: (SHR16rCL:i16 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::SHR16rCL, MVT::i16);
+ SDNode *Result = Emit_158(N, X86::SHR16rCL, MVT::i16);
return Result;
}
@@ -30413,21 +30227,21 @@ SDNode *Select_ISD_SRL_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SRL_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SRL_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (srl:i32 GR32:i32:$src1, (and:i8 CL:i8:$amt, 31:i8))
// Emits: (SHR32rCL:i32 GR32:i32:$src1)
// Pattern complexity = 11 cost = 1 size = 3
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(31)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_165(N, X86::SHR32rCL, MVT::i32);
+ SDNode *Result = Emit_162(N, X86::SHR32rCL, MVT::i32);
return Result;
}
}
@@ -30436,12 +30250,12 @@ SDNode *Select_ISD_SRL_i32(const SDValue &N) {
// Emits: (SHR32r1:i32 GR32:i32:$src1)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_94(N, X86::SHR32r1, MVT::i32);
+ SDNode *Result = Emit_93(N, X86::SHR32r1, MVT::i32);
return Result;
}
}
@@ -30450,9 +30264,9 @@ SDNode *Select_ISD_SRL_i32(const SDValue &N) {
// Pattern: (srl:i32 GR32:i32:$src1, (imm:i8):$src2)
// Emits: (SHR32ri:i32 GR32:i32:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHR32ri, MVT::i32);
+ SDNode *Result = Emit_159(N, X86::SHR32ri, MVT::i32);
return Result;
}
@@ -30460,7 +30274,7 @@ SDNode *Select_ISD_SRL_i32(const SDValue &N) {
// Emits: (SHR32rCL:i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::SHR32rCL, MVT::i32);
+ SDNode *Result = Emit_158(N, X86::SHR32rCL, MVT::i32);
return Result;
}
@@ -30468,21 +30282,21 @@ SDNode *Select_ISD_SRL_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SRL_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_ISD_SRL_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (srl:i64 GR64:i64:$src1, (and:i8 CL:i8:$amt, 63:i8))
// Emits: (SHR64rCL:i64 GR64:i64:$src1)
// Pattern complexity = 11 cost = 1 size = 3
- if (N1.getOpcode() == ISD::AND) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ if (N1.getNode()->getOpcode() == ISD::AND) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0 &&
CheckAndMask(N10, Tmp0, INT64_C(63)) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_165(N, X86::SHR64rCL, MVT::i64);
+ SDNode *Result = Emit_162(N, X86::SHR64rCL, MVT::i64);
return Result;
}
}
@@ -30491,12 +30305,12 @@ SDNode *Select_ISD_SRL_i64(const SDValue &N) {
// Emits: (SHR64r1:i64 GR64:i64:$src1)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1) &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_94(N, X86::SHR64r1, MVT::i64);
+ SDNode *Result = Emit_93(N, X86::SHR64r1, MVT::i64);
return Result;
}
}
@@ -30505,9 +30319,9 @@ SDNode *Select_ISD_SRL_i64(const SDValue &N) {
// Pattern: (srl:i64 GR64:i64:$src1, (imm:i8):$src2)
// Emits: (SHR64ri:i64 GR64:i64:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_162(N, X86::SHR64ri, MVT::i64);
+ SDNode *Result = Emit_159(N, X86::SHR64ri, MVT::i64);
return Result;
}
@@ -30515,7 +30329,7 @@ SDNode *Select_ISD_SRL_i64(const SDValue &N) {
// Emits: (SHR64rCL:i64 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_161(N, X86::SHR64rCL, MVT::i64);
+ SDNode *Result = Emit_158(N, X86::SHR64rCL, MVT::i64);
return Result;
}
@@ -30523,77 +30337,77 @@ SDNode *Select_ISD_SRL_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_172(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_169(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp1, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_173(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_170(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp1, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_174(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_171(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp1, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_175(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_172(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N1, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_176(const SDValue &N, unsigned Opc0, SDValue &CPTmpN111_0, SDValue &CPTmpN111_1, SDValue &CPTmpN111_2, SDValue &CPTmpN111_3, SDValue &CPTmpN111_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue Chain11 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_173(SDNode *N, unsigned Opc0, SDValue &CPTmpN111_0, SDValue &CPTmpN111_1, SDValue &CPTmpN111_2, SDValue &CPTmpN111_3, SDValue &CPTmpN111_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue Chain11 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N11.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain11);
- Chain11 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain11 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N11)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N11.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4, Chain11 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 6);
Chain11 = SDValue(ResNode, 1);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N11.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 1),
@@ -30602,30 +30416,30 @@ DISABLE_INLINE SDNode *Emit_176(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_177(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_174(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 6);
Chain10 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -30634,30 +30448,30 @@ DISABLE_INLINE SDNode *Emit_177(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_178(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_175(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 6);
Chain10 = SDValue(ResNode, 1);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 1),
@@ -30666,30 +30480,30 @@ DISABLE_INLINE SDNode *Emit_178(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_179(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_176(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, N11, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
Chain10 = SDValue(ResNode, 1);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 1),
@@ -30698,31 +30512,31 @@ DISABLE_INLINE SDNode *Emit_179(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_180(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_177(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i8);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
Chain10 = SDValue(ResNode, 1);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 1),
@@ -30731,31 +30545,31 @@ DISABLE_INLINE SDNode *Emit_180(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_181(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_178(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i16);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
Chain10 = SDValue(ResNode, 1);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 1),
@@ -30764,31 +30578,31 @@ DISABLE_INLINE SDNode *Emit_181(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_182(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_179(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
Chain10 = SDValue(ResNode, 1);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 1),
@@ -30797,34 +30611,34 @@ DISABLE_INLINE SDNode *Emit_182(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_183(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_180(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain10, N1.getDebugLoc(), X86::CL, N11, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain10, N1.getNode()->getDebugLoc(), X86::CL, N11, InFlag).getNode();
Chain10 = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10, InFlag };
- ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
Chain10 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -30833,31 +30647,31 @@ DISABLE_INLINE SDNode *Emit_183(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_184(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_181(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i8);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
Chain10 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -30866,35 +30680,35 @@ DISABLE_INLINE SDNode *Emit_184(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_185(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N12 = N1.getOperand(2);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_182(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain10, N1.getDebugLoc(), X86::CL, N12, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain10, N1.getNode()->getDebugLoc(), X86::CL, N12, InFlag).getNode();
Chain10 = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, N11, Chain10, InFlag };
- ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
Chain10 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -30903,32 +30717,32 @@ DISABLE_INLINE SDNode *Emit_185(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_186(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N12 = N1.getOperand(2);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_183(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N12)->getZExtValue()), MVT::i8);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, N11, Tmp2, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
Chain10 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -30937,33 +30751,33 @@ DISABLE_INLINE SDNode *Emit_186(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_187(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_184(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue InFlag = N1.getOperand(2);
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue InFlag = N1.getNode()->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, N11, Chain10, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, 8);
Chain10 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
SDValue(N1.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -30973,34 +30787,34 @@ DISABLE_INLINE SDNode *Emit_187(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 3);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_188(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_185(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i8);
- SDValue InFlag = N1.getOperand(2);
+ SDValue InFlag = N1.getNode()->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, 8);
Chain10 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
SDValue(N1.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -31010,34 +30824,34 @@ DISABLE_INLINE SDNode *Emit_188(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 3);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_189(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_186(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i16);
- SDValue InFlag = N1.getOperand(2);
+ SDValue InFlag = N1.getNode()->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, 8);
Chain10 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
SDValue(N1.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -31047,34 +30861,34 @@ DISABLE_INLINE SDNode *Emit_189(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 3);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_190(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_187(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
- SDValue InFlag = N1.getOperand(2);
+ SDValue InFlag = N1.getNode()->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, 8);
Chain10 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
SDValue(N1.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -31084,60 +30898,60 @@ DISABLE_INLINE SDNode *Emit_190(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 3);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_191(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_188(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N1.getDebugLoc(), X86::EFLAGS, N11, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N1.getNode()->getDebugLoc(), X86::EFLAGS, N11, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Chain, InFlag };
- ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_192(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_189(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp1, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_193(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_190(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i64);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
Chain10 = SDValue(ResNode, 1);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 1),
@@ -31146,34 +30960,34 @@ DISABLE_INLINE SDNode *Emit_193(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_194(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_191(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i64);
- SDValue InFlag = N1.getOperand(2);
+ SDValue InFlag = N1.getNode()->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp1, Chain10, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, 8);
Chain10 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
SDValue(N1.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -31183,130 +30997,130 @@ DISABLE_INLINE SDNode *Emit_194(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 3);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_195(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_192(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N2 = N->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N10, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_196(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_193(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N10, Tmp2, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_197(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_194(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N100, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_198(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N1000 = N100.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_195(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N1000, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_199(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_196(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N10, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_200(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_197(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N100, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_201(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_198(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N11)->getZExtValue()), MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N100, Tmp2, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_202(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_199(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFFFFFFFF80ULL, MVT::i16);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp3, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
Chain10 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -31315,31 +31129,31 @@ DISABLE_INLINE SDNode *Emit_202(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_203(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_200(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFFFFFFFF80ULL, MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp3, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
Chain10 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -31348,36 +31162,36 @@ DISABLE_INLINE SDNode *Emit_203(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_204(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_201(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain10, N11.getDebugLoc(), X86::CL, N110, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain10, N11.getNode()->getDebugLoc(), X86::CL, N110, InFlag).getNode();
Chain10 = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10, InFlag };
- ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
Chain10 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -31386,40 +31200,40 @@ DISABLE_INLINE SDNode *Emit_204(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_205(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue Chain100 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- SDValue N1110 = N111.getOperand(0);
- SDValue N1111 = N111.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_202(SDNode *N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N1111 = N111.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N100.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain100);
- Chain100 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain100 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain100, N10.getDebugLoc(), X86::CL, N101, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain100, N10.getNode()->getDebugLoc(), X86::CL, N101, InFlag).getNode();
Chain100 = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N100)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N100.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, N110, Chain100, InFlag };
- ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
Chain100 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N100.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -31428,42 +31242,42 @@ DISABLE_INLINE SDNode *Emit_205(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_206(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue Chain100 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- SDValue N101 = N10.getOperand(1);
- SDValue N1010 = N101.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- SDValue N1110 = N111.getOperand(0);
- SDValue N11100 = N1110.getOperand(0);
- SDValue N11101 = N1110.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_203(SDNode *N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N11100 = N1110.getNode()->getOperand(0);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N100.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain100);
- Chain100 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain100 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain100, N101.getDebugLoc(), X86::ECX, N1010, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain100, N101.getNode()->getDebugLoc(), X86::ECX, N1010, InFlag).getNode();
Chain100 = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N100)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N100.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, N110, Chain100, InFlag };
- ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
Chain100 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N100.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -31472,35 +31286,35 @@ DISABLE_INLINE SDNode *Emit_206(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_207(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue Chain100 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_204(SDNode *N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N100.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain100);
- Chain100 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain100 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i8);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N100)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N100.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, N110, Tmp2, Chain100 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
Chain100 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N100.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -31509,42 +31323,42 @@ DISABLE_INLINE SDNode *Emit_207(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_208(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue Chain100 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- SDValue N101 = N10.getOperand(1);
- SDValue N1010 = N101.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- SDValue N1110 = N111.getOperand(0);
- SDValue N11100 = N1110.getOperand(0);
- SDValue N11101 = N1110.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_205(SDNode *N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N11100 = N1110.getNode()->getOperand(0);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N100.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain100);
- Chain100 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain100 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain100, N101.getDebugLoc(), X86::CX, N1010, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain100, N101.getNode()->getDebugLoc(), X86::CX, N1010, InFlag).getNode();
Chain100 = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N100)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N100.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, N110, Chain100, InFlag };
- ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
Chain100 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N100.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -31553,29 +31367,29 @@ DISABLE_INLINE SDNode *Emit_208(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_209(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_206(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 6);
Chain10 = SDValue(ResNode, 1);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 1),
@@ -31584,44 +31398,44 @@ DISABLE_INLINE SDNode *Emit_209(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_210(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_207(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(0x3ULL, MVT::i32);
- SDValue Tmp3(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N1, Tmp2), 0);
+ SDValue Tmp3(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N1, Tmp2), 0);
MachineSDNode::mmo_iterator MemRefs1 = MF->allocateMemRefsArray(1);
MemRefs1[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops1[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp3, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc1, MVT::Other, Ops1, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc1, MVT::Other, Ops1, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs1, MemRefs1 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_211(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_208(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFFFFFFFF80ULL, MVT::i64);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp3, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
Chain10 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -31630,31 +31444,31 @@ DISABLE_INLINE SDNode *Emit_211(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_212(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_209(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue Tmp3 = CurDAG->getTargetConstant(0xFFFFFFFF80000000ULL, MVT::i64);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp3, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
Chain10 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -31663,128 +31477,84 @@ DISABLE_INLINE SDNode *Emit_212(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_213(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_210(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp4 = CurDAG->getTargetConstant(X86::GR64_ABCDRegClassID, MVT::i32);
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N100, Tmp4), 0);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N100, Tmp4), 0);
SDValue Tmp6 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
- SDValue Tmp7(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp5, Tmp6), 0);
+ SDValue Tmp7(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp5, Tmp6), 0);
MachineSDNode::mmo_iterator MemRefs2 = MF->allocateMemRefsArray(1);
MemRefs2[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops2[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp7, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc2, MVT::Other, Ops2, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc2, MVT::Other, Ops2, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs2, MemRefs2 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_214(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_211(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp4 = CurDAG->getTargetConstant(X86::GR32_ABCDRegClassID, MVT::i32);
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N100, Tmp4), 0);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N100, Tmp4), 0);
SDValue Tmp6 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
- SDValue Tmp7(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp5, Tmp6), 0);
+ SDValue Tmp7(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp5, Tmp6), 0);
MachineSDNode::mmo_iterator MemRefs2 = MF->allocateMemRefsArray(1);
MemRefs2[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops2[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp7, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc2, MVT::Other, Ops2, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc2, MVT::Other, Ops2, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs2, MemRefs2 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_215(const SDValue &N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_212(SDNode *N, unsigned Opc0, unsigned Opc1, unsigned Opc2, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp4 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
- SDValue Tmp5(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N100, Tmp4), 0);
+ SDValue Tmp5(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N100, Tmp4), 0);
SDValue Tmp6 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
- SDValue Tmp7(CurDAG->getMachineNode(Opc1, N.getDebugLoc(), VT1, Tmp5, Tmp6), 0);
+ SDValue Tmp7(CurDAG->getMachineNode(Opc1, N->getDebugLoc(), VT1, Tmp5, Tmp6), 0);
MachineSDNode::mmo_iterator MemRefs2 = MF->allocateMemRefsArray(1);
MemRefs2[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops2[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, Tmp7, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc2, MVT::Other, Ops2, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc2, MVT::Other, Ops2, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs2, MemRefs2 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_216(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue Chain100 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- SDValue N101 = N10.getOperand(1);
- SDValue N1010 = N101.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- SDValue N1110 = N111.getOperand(0);
- SDValue N11100 = N1110.getOperand(0);
- SDValue N11101 = N1110.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N100.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain100);
- Chain100 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain100, N101.getDebugLoc(), X86::RCX, N1010, InFlag).getNode();
- Chain100 = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N100)->getMemOperand();
- SDValue Ops0[] = { CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, N110, Chain100, InFlag };
- ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
- Chain100 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N100.getNode(), 1),
- SDValue(N.getNode(), 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain100.getNode(), Chain100.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_217(const SDValue &N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_213(SDNode *N, unsigned Opc0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N10.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain10);
- Chain10 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain10 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, N11, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
Chain10 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N10.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -31793,31 +31563,31 @@ DISABLE_INLINE SDNode *Emit_217(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_218(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue Chain100 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_214(SDNode *N, unsigned Opc0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N100.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain100);
- Chain100 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain100 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N100)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N100.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, N11, Chain100 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
Chain100 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N100.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -31826,46 +31596,46 @@ DISABLE_INLINE SDNode *Emit_218(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_219(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N1000 = N100.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_215(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N101)->getZExtValue()), MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N1000, Tmp2, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_220(const SDValue &N, unsigned Opc0, SDValue &CPTmpN111_0, SDValue &CPTmpN111_1, SDValue &CPTmpN111_2, SDValue &CPTmpN111_3, SDValue &CPTmpN111_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue Chain11 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_216(SDNode *N, unsigned Opc0, SDValue &CPTmpN111_0, SDValue &CPTmpN111_1, SDValue &CPTmpN111_2, SDValue &CPTmpN111_3, SDValue &CPTmpN111_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue Chain11 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N11.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain11);
- Chain11 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain11 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N11)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N11.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4, N10, Chain11 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
Chain11 = SDValue(ResNode, 1);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N11.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 1),
@@ -31874,33 +31644,33 @@ DISABLE_INLINE SDNode *Emit_220(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_221(const SDValue &N, unsigned Opc0, SDValue &CPTmpN111_0, SDValue &CPTmpN111_1, SDValue &CPTmpN111_2, SDValue &CPTmpN111_3, SDValue &CPTmpN111_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue Chain11 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_217(SDNode *N, unsigned Opc0, SDValue &CPTmpN111_0, SDValue &CPTmpN111_1, SDValue &CPTmpN111_2, SDValue &CPTmpN111_3, SDValue &CPTmpN111_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue Chain11 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N11.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain11);
- Chain11 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue InFlag = N1.getOperand(2);
+ Chain11 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ SDValue InFlag = N1.getNode()->getOperand(2);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N11)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N11.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4, N10, Chain11, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, 8);
Chain11 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
SDValue(N11.getNode(), 1),
SDValue(N1.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -31910,40 +31680,40 @@ DISABLE_INLINE SDNode *Emit_221(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 3);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_222(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N1010 = N101.getOperand(0);
- SDValue N1011 = N101.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue Chain110 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- SDValue N111 = N11.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_218(SDNode *N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue Chain110 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N110.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain110);
- Chain110 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain110 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain110, N101.getDebugLoc(), X86::CL, N1011, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain110, N101.getNode()->getDebugLoc(), X86::CL, N1011, InFlag).getNode();
Chain110 = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N110)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N110.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4, N100, Chain110, InFlag };
- ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
Chain110 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N110.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -31952,42 +31722,42 @@ DISABLE_INLINE SDNode *Emit_222(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_223(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N1010 = N101.getOperand(0);
- SDValue N10100 = N1010.getOperand(0);
- SDValue N10101 = N1010.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue Chain110 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- SDValue N111 = N11.getOperand(1);
- SDValue N1110 = N111.getOperand(0);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_219(SDNode *N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N10100 = N1010.getNode()->getOperand(0);
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue Chain110 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N110.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain110);
- Chain110 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain110 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain110, N1010.getDebugLoc(), X86::ECX, N10101, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain110, N1010.getNode()->getDebugLoc(), X86::ECX, N10101, InFlag).getNode();
Chain110 = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N110)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N110.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4, N100, Chain110, InFlag };
- ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
Chain110 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N110.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -31996,79 +31766,35 @@ DISABLE_INLINE SDNode *Emit_223(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_224(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue Chain110 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- SDValue N111 = N11.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_220(SDNode *N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue Chain110 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N110.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain110);
- Chain110 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain110 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N111)->getZExtValue()), MVT::i8);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N110)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N110.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4, N100, Tmp2, Chain110 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
- Chain110 = SDValue(ResNode, 0);
- cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
- const SDValue Froms[] = {
- SDValue(N110.getNode(), 1),
- SDValue(N.getNode(), 0)
- };
- const SDValue Tos[] = {
- SDValue(ResNode, 0),
- SDValue(Chain110.getNode(), Chain110.getResNo())
- };
- ReplaceUses(Froms, Tos, 2);
- return ResNode;
-}
-DISABLE_INLINE SDNode *Emit_225(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N1010 = N101.getOperand(0);
- SDValue N10100 = N1010.getOperand(0);
- SDValue N10101 = N1010.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue Chain110 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- SDValue N111 = N11.getOperand(1);
- SDValue N1110 = N111.getOperand(0);
- SDValue N2 = N.getOperand(2);
- SmallVector<SDValue, 8> InChains;
- if (Chain.getNode() != N110.getNode()) {
- InChains.push_back(Chain);
- }
- InChains.push_back(Chain110);
- Chain110 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
- SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain110, N1010.getDebugLoc(), X86::CX, N10101, InFlag).getNode();
- Chain110 = SDValue(ResNode, 0);
- InFlag = SDValue(ResNode, 1);
- MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
- MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N110)->getMemOperand();
- SDValue Ops0[] = { CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4, N100, Chain110, InFlag };
- ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
Chain110 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N110.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -32077,42 +31803,42 @@ DISABLE_INLINE SDNode *Emit_225(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_226(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N1010 = N101.getOperand(0);
- SDValue N10100 = N1010.getOperand(0);
- SDValue N10101 = N1010.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- SDValue N110 = N11.getOperand(0);
- SDValue Chain110 = N110.getOperand(0);
- SDValue N1101 = N110.getOperand(1);
- SDValue N111 = N11.getOperand(1);
- SDValue N1110 = N111.getOperand(0);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_221(SDNode *N, unsigned Opc0, SDValue &CPTmpN1101_0, SDValue &CPTmpN1101_1, SDValue &CPTmpN1101_2, SDValue &CPTmpN1101_3, SDValue &CPTmpN1101_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N10100 = N1010.getNode()->getOperand(0);
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue Chain110 = N110.getNode()->getOperand(0);
+ SDValue N1101 = N110.getNode()->getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ SDValue N2 = N->getOperand(2);
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N110.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain110);
- Chain110 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain110 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain110, N1010.getDebugLoc(), X86::RCX, N10101, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain110, N1010.getNode()->getDebugLoc(), X86::CX, N10101, InFlag).getNode();
Chain110 = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(2);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
- MemRefs0[1] = cast<MemSDNode>(N110)->getMemOperand();
+ MemRefs0[1] = cast<MemSDNode>(N110.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4, N100, Chain110, InFlag };
- ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
Chain110 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 2);
const SDValue Froms[] = {
SDValue(N110.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -32121,63 +31847,63 @@ DISABLE_INLINE SDNode *Emit_226(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_ISD_STORE(const SDValue &N) {
+SDNode *Select_ISD_STORE(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
{
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::OR &&
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::OR &&
N1.hasOneUse()) {
{
- SDValue N10 = N1.getOperand(0);
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (st:isVoid (or:i32 (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (trunc:i8 ECX:i32:$amt)), (shl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 67 cost = 1 size = 3
- if (N10.getOpcode() == ISD::SRL &&
+ if (N10.getNode()->getOpcode() == ISD::SRL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
(Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
SDValue CPTmpN1001_3;
SDValue CPTmpN1001_4;
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getOperand(0);
- if (N1110.getOpcode() == ISD::SUB) {
- SDValue N11100 = N1110.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ if (N1110.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N11101 = N1110.getOperand(1);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
if (N1010 == N11101) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N1001 == N2 &&
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N1010.getValueType() == MVT::i32 &&
N111.getValueType() == MVT::i8 &&
N1110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_206(N, X86::SHRD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_203(N, X86::SHRD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -32195,48 +31921,48 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (or:i32 (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (trunc:i8 ECX:i32:$amt)), (srl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 67 cost = 1 size = 3
- if (N10.getOpcode() == ISD::SHL &&
+ if (N10.getNode()->getOpcode() == ISD::SHL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
(Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
SDValue CPTmpN1001_3;
SDValue CPTmpN1001_4;
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getOperand(0);
- if (N1110.getOpcode() == ISD::SUB) {
- SDValue N11100 = N1110.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ if (N1110.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N11101 = N1110.getOperand(1);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
if (N1010 == N11101) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N1001 == N2 &&
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N1010.getValueType() == MVT::i32 &&
N111.getValueType() == MVT::i8 &&
N1110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_206(N, X86::SHLD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_203(N, X86::SHLD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -32254,107 +31980,48 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (or:i16 (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt)), (shl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 67 cost = 1 size = 3
- if (N10.getOpcode() == ISD::SRL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi16(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getOperand(0);
- if (N1110.getOpcode() == ISD::SUB) {
- SDValue N11100 = N1110.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N11101 = N1110.getOperand(1);
- if (N1010 == N11101) {
- SDValue N2 = N.getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N1010.getValueType() == MVT::i16 &&
- N111.getValueType() == MVT::i8 &&
- N1110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_208(N, X86::SHRD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i16 (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt)), (srl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 67 cost = 1 size = 3
- if (N10.getOpcode() == ISD::SHL &&
+ if (N10.getNode()->getOpcode() == ISD::SRL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
(Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_loadi16(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
SDValue CPTmpN1001_3;
SDValue CPTmpN1001_4;
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getOperand(0);
- if (N1110.getOpcode() == ISD::SUB) {
- SDValue N11100 = N1110.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ if (N1110.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N11101 = N1110.getOperand(1);
+ SDValue N11101 = N1110.getNode()->getOperand(1);
if (N1010 == N11101) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N1001 == N2 &&
N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
N1010.getValueType() == MVT::i16 &&
N111.getValueType() == MVT::i8 &&
N1110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_208(N, X86::SHLD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_205(N, X86::SHRD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -32368,113 +32035,52 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
+ if (N10.getNode()->getOpcode() == ISD::SHL) {
- // Pattern: (st:isVoid (or:i64 (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (trunc:i8 RCX:i64:$amt)), (shl:i64 GR64:i64:$src2, (trunc:i8 (sub:i64 64:i64, RCX:i64:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 67 cost = 1 size = 3
- if (N10.getOpcode() == ISD::SRL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getOperand(0);
- if (N1110.getOpcode() == ISD::SUB) {
- SDValue N11100 = N1110.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(64)) {
- SDValue N11101 = N1110.getOperand(1);
- if (N1010 == N11101) {
- SDValue N2 = N.getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N101.getValueType() == MVT::i8 &&
- N1010.getValueType() == MVT::i64 &&
- N111.getValueType() == MVT::i8 &&
- N1110.getValueType() == MVT::i64) {
- SDNode *Result = Emit_216(N, X86::SHRD64mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (N10.getOpcode() == ISD::SHL) {
-
- // Pattern: (st:isVoid (or:i64 (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (trunc:i8 RCX:i64:$amt)), (srl:i64 GR64:i64:$src2, (trunc:i8 (sub:i64 64:i64, RCX:i64:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern: (st:isVoid (or:i16 (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt)), (srl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt)))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 67 cost = 1 size = 3
if (N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
(Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ Predicate_loadi16(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
SDValue CPTmpN1001_3;
SDValue CPTmpN1001_4;
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getOperand(0);
- if (N1110.getOpcode() == ISD::SUB) {
- SDValue N11100 = N1110.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ if (N1110.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N11100 = N1110.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11100.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(64)) {
- SDValue N11101 = N1110.getOperand(1);
+ if (CN1 == INT64_C(16)) {
+ SDValue N11101 = N1110.getNode()->getOperand(1);
if (N1010 == N11101) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N1001 == N2 &&
- N1.getValueType() == MVT::i64 &&
+ N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
- N1010.getValueType() == MVT::i64 &&
+ N1010.getValueType() == MVT::i16 &&
N111.getValueType() == MVT::i8 &&
- N1110.getValueType() == MVT::i64) {
- SDNode *Result = Emit_216(N, X86::SHLD64mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ N1110.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_205(N, X86::SHLD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -32492,47 +32098,47 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (or:i32 (shl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))), (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (trunc:i8 ECX:i32:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 67 cost = 1 size = 3
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getOperand(0);
- if (N1010.getOpcode() == ISD::SUB) {
- SDValue N10100 = N1010.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ if (N1010.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N10101 = N1010.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRL &&
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL &&
N11.hasOneUse()) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::LOAD &&
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
(Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getOperand(0);
+ SDValue Chain110 = N110.getNode()->getOperand(0);
if (Predicate_unindexedload(N110.getNode()) &&
Predicate_loadi32(N110.getNode())) {
- SDValue N1101 = N110.getOperand(1);
+ SDValue N1101 = N110.getNode()->getOperand(1);
SDValue CPTmpN1101_0;
SDValue CPTmpN1101_1;
SDValue CPTmpN1101_2;
SDValue CPTmpN1101_3;
SDValue CPTmpN1101_4;
if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
if (N10101 == N1110) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N1101 == N2 &&
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N1010.getValueType() == MVT::i32 &&
N111.getValueType() == MVT::i8 &&
N1110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_223(N, X86::SHRD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_219(N, X86::SHRD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -32550,48 +32156,48 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (or:i32 (srl:i32 GR32:i32:$src2, (trunc:i8 (sub:i32 32:i32, ECX:i32:$amt))), (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (trunc:i8 ECX:i32:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 67 cost = 1 size = 3
- if (N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getOperand(0);
- if (N1010.getOpcode() == ISD::SUB) {
- SDValue N10100 = N1010.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100);
+ if (N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ if (N1010.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N10101 = N1010.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SHL &&
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL &&
N11.hasOneUse()) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::LOAD &&
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
(Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getOperand(0);
+ SDValue Chain110 = N110.getNode()->getOperand(0);
if (Predicate_unindexedload(N110.getNode()) &&
Predicate_loadi32(N110.getNode())) {
- SDValue N1101 = N110.getOperand(1);
+ SDValue N1101 = N110.getNode()->getOperand(1);
SDValue CPTmpN1101_0;
SDValue CPTmpN1101_1;
SDValue CPTmpN1101_2;
SDValue CPTmpN1101_3;
SDValue CPTmpN1101_4;
if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
if (N10101 == N1110) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N1101 == N2 &&
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N1010.getValueType() == MVT::i32 &&
N111.getValueType() == MVT::i8 &&
N1110.getValueType() == MVT::i32) {
- SDNode *Result = Emit_223(N, X86::SHLD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_219(N, X86::SHLD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -32609,167 +32215,48 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (or:i16 (shl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))), (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 67 cost = 1 size = 3
- if (N10.getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getOperand(0);
- if (N1010.getOpcode() == ISD::SUB) {
- SDValue N10100 = N1010.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N10101 = N1010.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_loadi16(N110.getNode())) {
- SDValue N1101 = N110.getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getOperand(0);
- if (N10101 == N1110) {
- SDValue N2 = N.getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N1010.getValueType() == MVT::i16 &&
- N111.getValueType() == MVT::i8 &&
- N1110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_225(N, X86::SHRD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i16 (srl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))), (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 67 cost = 1 size = 3
- if (N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getOperand(0);
- if (N1010.getOpcode() == ISD::SUB) {
- SDValue N10100 = N1010.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100);
+ if (N10.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ if (N1010.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N10101 = N1010.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SHL &&
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL &&
N11.hasOneUse()) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::LOAD &&
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
(Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getOperand(0);
+ SDValue Chain110 = N110.getNode()->getOperand(0);
if (Predicate_unindexedload(N110.getNode()) &&
Predicate_loadi16(N110.getNode())) {
- SDValue N1101 = N110.getOperand(1);
+ SDValue N1101 = N110.getNode()->getOperand(1);
SDValue CPTmpN1101_0;
SDValue CPTmpN1101_1;
SDValue CPTmpN1101_2;
SDValue CPTmpN1101_3;
SDValue CPTmpN1101_4;
if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
if (N10101 == N1110) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N1101 == N2 &&
N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
N1010.getValueType() == MVT::i16 &&
N111.getValueType() == MVT::i8 &&
N1110.getValueType() == MVT::i16) {
- SDNode *Result = Emit_225(N, X86::SHLD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i64 (shl:i64 GR64:i64:$src2, (trunc:i8 (sub:i64 64:i64, RCX:i64:$amt))), (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (trunc:i8 RCX:i64:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 67 cost = 1 size = 3
- if (N10.getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getOperand(0);
- if (N1010.getOpcode() == ISD::SUB) {
- SDValue N10100 = N1010.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(64)) {
- SDValue N10101 = N1010.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_load(N110.getNode()) &&
- Predicate_loadi64(N110.getNode())) {
- SDValue N1101 = N110.getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getOperand(0);
- if (N10101 == N1110) {
- SDValue N2 = N.getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N101.getValueType() == MVT::i8 &&
- N1010.getValueType() == MVT::i64 &&
- N111.getValueType() == MVT::i8 &&
- N1110.getValueType() == MVT::i64) {
- SDNode *Result = Emit_226(N, X86::SHRD64mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_221(N, X86::SHRD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -32783,54 +32270,53 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N10.getOpcode() == ISD::SRL) {
+ if (N10.getNode()->getOpcode() == ISD::SRL) {
- // Pattern: (st:isVoid (or:i64 (srl:i64 GR64:i64:$src2, (trunc:i8 (sub:i64 64:i64, RCX:i64:$amt))), (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (trunc:i8 RCX:i64:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern: (st:isVoid (or:i16 (srl:i16 GR16:i16:$src2, (trunc:i8 (sub:i16 16:i16, CX:i16:$amt))), (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (trunc:i8 CX:i16:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 67 cost = 1 size = 3
{
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::TRUNCATE) {
- SDValue N1010 = N101.getOperand(0);
- if (N1010.getOpcode() == ISD::SUB) {
- SDValue N10100 = N1010.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ if (N1010.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N10100 = N1010.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10100.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(64)) {
- SDValue N10101 = N1010.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SHL &&
+ if (CN1 == INT64_C(16)) {
+ SDValue N10101 = N1010.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL &&
N11.hasOneUse()) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::LOAD &&
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
(Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getOperand(0);
+ SDValue Chain110 = N110.getNode()->getOperand(0);
if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_load(N110.getNode()) &&
- Predicate_loadi64(N110.getNode())) {
- SDValue N1101 = N110.getOperand(1);
+ Predicate_loadi16(N110.getNode())) {
+ SDValue N1101 = N110.getNode()->getOperand(1);
SDValue CPTmpN1101_0;
SDValue CPTmpN1101_1;
SDValue CPTmpN1101_2;
SDValue CPTmpN1101_3;
SDValue CPTmpN1101_4;
if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::TRUNCATE) {
- SDValue N1110 = N111.getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::TRUNCATE) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
if (N10101 == N1110) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N1101 == N2 &&
- N1.getValueType() == MVT::i64 &&
+ N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
- N1010.getValueType() == MVT::i64 &&
+ N1010.getValueType() == MVT::i16 &&
N111.getValueType() == MVT::i8 &&
- N1110.getValueType() == MVT::i64) {
- SDNode *Result = Emit_226(N, X86::SHLD64mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ N1110.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_221(N, X86::SHLD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -32849,40 +32335,40 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 61 cost = 1 size = 3
if (N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
(Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
SDValue CPTmpN1001_3;
SDValue CPTmpN1001_4;
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::SUB) {
- SDValue N1110 = N111.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N1111 = N111.getOperand(1);
+ SDValue N1111 = N111.getNode()->getOperand(1);
if (N101 == N1111) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N1001 == N2 &&
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_205(N, X86::SHRD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_202(N, X86::SHRD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -32899,42 +32385,42 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (or:i32 (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8:$amt), (srl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 61 cost = 1 size = 3
- if (N10.getOpcode() == ISD::SHL &&
+ if (N10.getNode()->getOpcode() == ISD::SHL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
(Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
SDValue CPTmpN1001_3;
SDValue CPTmpN1001_4;
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::SUB) {
- SDValue N1110 = N111.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N1111 = N111.getOperand(1);
+ SDValue N1111 = N111.getNode()->getOperand(1);
if (N101 == N1111) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N1001 == N2 &&
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_205(N, X86::SHLD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_202(N, X86::SHLD32mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -32950,42 +32436,42 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (or:i16 (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt), (shl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 61 cost = 1 size = 3
- if (N10.getOpcode() == ISD::SRL &&
+ if (N10.getNode()->getOpcode() == ISD::SRL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
(Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_loadi16(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
SDValue CPTmpN1001_3;
SDValue CPTmpN1001_4;
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::SUB) {
- SDValue N1110 = N111.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1111 = N111.getOperand(1);
+ SDValue N1111 = N111.getNode()->getOperand(1);
if (N101 == N1111) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N1001 == N2 &&
N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_205(N, X86::SHRD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_202(N, X86::SHRD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -32997,150 +32483,46 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
+ if (N10.getNode()->getOpcode() == ISD::SHL) {
- // Pattern: (st:isVoid (or:i16 (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt), (srl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
- // Pattern complexity = 61 cost = 1 size = 3
- if (N10.getOpcode() == ISD::SHL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_loadi16(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::SUB) {
- SDValue N1110 = N111.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(16)) {
- SDValue N1111 = N111.getOperand(1);
- if (N101 == N1111) {
- SDValue N2 = N.getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i16 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_205(N, X86::SHLD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i64 (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8:$amt), (shl:i64 GR64:i64:$src2, (sub:i8 64:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 61 cost = 1 size = 3
- if (N10.getOpcode() == ISD::SRL &&
- N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
- N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
- (Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getOperand(0);
- if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
- SDValue CPTmpN1001_0;
- SDValue CPTmpN1001_1;
- SDValue CPTmpN1001_2;
- SDValue CPTmpN1001_3;
- SDValue CPTmpN1001_4;
- if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::SUB) {
- SDValue N1110 = N111.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(64)) {
- SDValue N1111 = N111.getOperand(1);
- if (N101 == N1111) {
- SDValue N2 = N.getOperand(2);
- if (N1001 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_205(N, X86::SHRD64mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- if (N10.getOpcode() == ISD::SHL) {
-
- // Pattern: (st:isVoid (or:i64 (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8:$amt), (srl:i64 GR64:i64:$src2, (sub:i8 64:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern: (st:isVoid (or:i16 (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt), (srl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt))), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 61 cost = 1 size = 3
if (N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
(Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
- Predicate_load(N100.getNode()) &&
- Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ Predicate_loadi16(N100.getNode())) {
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
SDValue CPTmpN1001_3;
SDValue CPTmpN1001_4;
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::SUB) {
- SDValue N1110 = N111.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N1110 = N111.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1110.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(64)) {
- SDValue N1111 = N111.getOperand(1);
+ if (CN1 == INT64_C(16)) {
+ SDValue N1111 = N111.getNode()->getOperand(1);
if (N101 == N1111) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N1001 == N2 &&
- N1.getValueType() == MVT::i64 &&
+ N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_205(N, X86::SHLD64mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_202(N, X86::SHLD16mrCL, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -33156,41 +32538,41 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (or:i32 (shl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)), (srl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 61 cost = 1 size = 3
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::SUB) {
- SDValue N1010 = N101.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N1011 = N101.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRL &&
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL &&
N11.hasOneUse()) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::LOAD &&
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
(Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getOperand(0);
+ SDValue Chain110 = N110.getNode()->getOperand(0);
if (Predicate_unindexedload(N110.getNode()) &&
Predicate_loadi32(N110.getNode())) {
- SDValue N1101 = N110.getOperand(1);
+ SDValue N1101 = N110.getNode()->getOperand(1);
SDValue CPTmpN1101_0;
SDValue CPTmpN1101_1;
SDValue CPTmpN1101_2;
SDValue CPTmpN1101_3;
SDValue CPTmpN1101_4;
if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
if (N1011 == N111) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N1101 == N2 &&
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_222(N, X86::SHRD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_218(N, X86::SHRD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33206,42 +32588,42 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (or:i32 (srl:i32 GR32:i32:$src2, (sub:i8 32:i8, CL:i8:$amt)), (shl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 61 cost = 1 size = 3
- if (N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::SUB) {
- SDValue N1010 = N101.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010);
+ if (N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(32)) {
- SDValue N1011 = N101.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SHL &&
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL &&
N11.hasOneUse()) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::LOAD &&
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
(Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getOperand(0);
+ SDValue Chain110 = N110.getNode()->getOperand(0);
if (Predicate_unindexedload(N110.getNode()) &&
Predicate_loadi32(N110.getNode())) {
- SDValue N1101 = N110.getOperand(1);
+ SDValue N1101 = N110.getNode()->getOperand(1);
SDValue CPTmpN1101_0;
SDValue CPTmpN1101_1;
SDValue CPTmpN1101_2;
SDValue CPTmpN1101_3;
SDValue CPTmpN1101_4;
if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
if (N1011 == N111) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N1101 == N2 &&
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_222(N, X86::SHLD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_218(N, X86::SHLD32mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33257,42 +32639,42 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (or:i16 (shl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)), (srl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 61 cost = 1 size = 3
- if (N10.getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::SUB) {
- SDValue N1010 = N101.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010);
+ if (N10.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1011 = N101.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRL &&
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL &&
N11.hasOneUse()) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::LOAD &&
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
(Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getOperand(0);
+ SDValue Chain110 = N110.getNode()->getOperand(0);
if (Predicate_unindexedload(N110.getNode()) &&
Predicate_loadi16(N110.getNode())) {
- SDValue N1101 = N110.getOperand(1);
+ SDValue N1101 = N110.getNode()->getOperand(1);
SDValue CPTmpN1101_0;
SDValue CPTmpN1101_1;
SDValue CPTmpN1101_2;
SDValue CPTmpN1101_3;
SDValue CPTmpN1101_4;
if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
if (N1011 == N111) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N1101 == N2 &&
N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_222(N, X86::SHRD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_218(N, X86::SHRD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33308,146 +32690,42 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (or:i16 (srl:i16 GR16:i16:$src2, (sub:i8 16:i8, CL:i8:$amt)), (shl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 61 cost = 1 size = 3
- if (N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::SUB) {
- SDValue N1010 = N101.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010);
+ if (N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::SUB) {
+ SDValue N1010 = N101.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(16)) {
- SDValue N1011 = N101.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SHL &&
+ SDValue N1011 = N101.getNode()->getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL &&
N11.hasOneUse()) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::LOAD &&
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
(Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getOperand(0);
+ SDValue Chain110 = N110.getNode()->getOperand(0);
if (Predicate_unindexedload(N110.getNode()) &&
Predicate_loadi16(N110.getNode())) {
- SDValue N1101 = N110.getOperand(1);
+ SDValue N1101 = N110.getNode()->getOperand(1);
SDValue CPTmpN1101_0;
SDValue CPTmpN1101_1;
SDValue CPTmpN1101_2;
SDValue CPTmpN1101_3;
SDValue CPTmpN1101_4;
if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
if (N1011 == N111) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N1101 == N2 &&
N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_222(N, X86::SHLD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i64 (shl:i64 GR64:i64:$src2, (sub:i8 64:i8, CL:i8:$amt)), (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHRD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 61 cost = 1 size = 3
- if (N10.getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::SUB) {
- SDValue N1010 = N101.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(64)) {
- SDValue N1011 = N101.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_load(N110.getNode()) &&
- Predicate_loadi64(N110.getNode())) {
- SDValue N1101 = N110.getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getOperand(1);
- if (N1011 == N111) {
- SDValue N2 = N.getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_222(N, X86::SHRD64mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
- return Result;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
-
- // Pattern: (st:isVoid (or:i64 (srl:i64 GR64:i64:$src2, (sub:i8 64:i8, CL:i8:$amt)), (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8:$amt)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
- // Emits: (SHLD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
- // Pattern complexity = 61 cost = 1 size = 3
- if (N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::SUB) {
- SDValue N1010 = N101.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1010);
- if (Tmp0) {
- int64_t CN1 = Tmp0->getSExtValue();
- if (CN1 == INT64_C(64)) {
- SDValue N1011 = N101.getOperand(1);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SHL &&
- N11.hasOneUse()) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::LOAD &&
- N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
- (Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getOperand(0);
- if (Predicate_unindexedload(N110.getNode()) &&
- Predicate_load(N110.getNode()) &&
- Predicate_loadi64(N110.getNode())) {
- SDValue N1101 = N110.getOperand(1);
- SDValue CPTmpN1101_0;
- SDValue CPTmpN1101_1;
- SDValue CPTmpN1101_2;
- SDValue CPTmpN1101_3;
- SDValue CPTmpN1101_4;
- if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getOperand(1);
- if (N1011 == N111) {
- SDValue N2 = N.getOperand(2);
- if (N1101 == N2 &&
- N1.getValueType() == MVT::i64 &&
- N101.getValueType() == MVT::i8 &&
- N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_222(N, X86::SHLD64mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_218(N, X86::SHLD16mrCL, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33465,37 +32743,37 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHRD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$amt1)
// Pattern complexity = 60 cost = 1 size = 3
if (Predicate_shrd(N1.getNode())) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SRL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
(Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
SDValue CPTmpN1001_3;
SDValue CPTmpN1001_4;
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1001 == N2 &&
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_207(N, X86::SHRD32mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_204(N, X86::SHRD32mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -33511,37 +32789,37 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHLD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$amt1)
// Pattern complexity = 60 cost = 1 size = 3
if (Predicate_shld(N1.getNode())) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SHL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SHL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
(Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_loadi32(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
SDValue CPTmpN1001_3;
SDValue CPTmpN1001_4;
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1001 == N2 &&
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_207(N, X86::SHLD32mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_204(N, X86::SHLD32mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -33557,37 +32835,37 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHRD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$amt1)
// Pattern complexity = 60 cost = 1 size = 3
if (Predicate_shrd(N1.getNode())) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SRL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
(Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_loadi16(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
SDValue CPTmpN1001_3;
SDValue CPTmpN1001_4;
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1001 == N2 &&
N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_207(N, X86::SHRD16mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_204(N, X86::SHRD16mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -33603,37 +32881,37 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHLD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$amt1)
// Pattern complexity = 60 cost = 1 size = 3
if (Predicate_shld(N1.getNode())) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SHL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SHL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
(Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_loadi16(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
SDValue CPTmpN1001_3;
SDValue CPTmpN1001_4;
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1001 == N2 &&
N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_207(N, X86::SHLD16mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_204(N, X86::SHLD16mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -33649,38 +32927,38 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHRD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$amt1)
// Pattern complexity = 60 cost = 1 size = 3
if (Predicate_shrd(N1.getNode())) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SRL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
(Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_load(N100.getNode()) &&
Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
SDValue CPTmpN1001_3;
SDValue CPTmpN1001_4;
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SHL) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1001 == N2 &&
N1.getValueType() == MVT::i64 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_207(N, X86::SHRD64mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_204(N, X86::SHRD64mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -33696,38 +32974,38 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHLD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$amt1)
// Pattern complexity = 60 cost = 1 size = 3
if (Predicate_shld(N1.getNode())) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SHL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SHL &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
(Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_load(N100.getNode()) &&
Predicate_loadi64(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
SDValue CPTmpN1001_3;
SDValue CPTmpN1001_4;
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRL) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1001 == N2 &&
N1.getValueType() == MVT::i64 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_207(N, X86::SHLD64mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_204(N, X86::SHLD64mri8, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -33743,37 +33021,37 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHRD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$amt1)
// Pattern complexity = 60 cost = 1 size = 3
if (Predicate_shrd(N1.getNode())) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL &&
N11.hasOneUse()) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::LOAD &&
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
(Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getOperand(0);
+ SDValue Chain110 = N110.getNode()->getOperand(0);
if (Predicate_unindexedload(N110.getNode()) &&
Predicate_loadi32(N110.getNode())) {
- SDValue N1101 = N110.getOperand(1);
+ SDValue N1101 = N110.getNode()->getOperand(1);
SDValue CPTmpN1101_0;
SDValue CPTmpN1101_1;
SDValue CPTmpN1101_2;
SDValue CPTmpN1101_3;
SDValue CPTmpN1101_4;
if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1101 == N2 &&
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_224(N, X86::SHRD32mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_220(N, X86::SHRD32mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33789,37 +33067,37 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHLD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$amt1)
// Pattern complexity = 60 cost = 1 size = 3
if (Predicate_shld(N1.getNode())) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SHL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL &&
N11.hasOneUse()) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::LOAD &&
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
(Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getOperand(0);
+ SDValue Chain110 = N110.getNode()->getOperand(0);
if (Predicate_unindexedload(N110.getNode()) &&
Predicate_loadi32(N110.getNode())) {
- SDValue N1101 = N110.getOperand(1);
+ SDValue N1101 = N110.getNode()->getOperand(1);
SDValue CPTmpN1101_0;
SDValue CPTmpN1101_1;
SDValue CPTmpN1101_2;
SDValue CPTmpN1101_3;
SDValue CPTmpN1101_4;
if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1101 == N2 &&
N1.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_224(N, X86::SHLD32mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_220(N, X86::SHLD32mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33835,37 +33113,37 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHRD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$amt1)
// Pattern complexity = 60 cost = 1 size = 3
if (Predicate_shrd(N1.getNode())) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL &&
N11.hasOneUse()) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::LOAD &&
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
(Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getOperand(0);
+ SDValue Chain110 = N110.getNode()->getOperand(0);
if (Predicate_unindexedload(N110.getNode()) &&
Predicate_loadi16(N110.getNode())) {
- SDValue N1101 = N110.getOperand(1);
+ SDValue N1101 = N110.getNode()->getOperand(1);
SDValue CPTmpN1101_0;
SDValue CPTmpN1101_1;
SDValue CPTmpN1101_2;
SDValue CPTmpN1101_3;
SDValue CPTmpN1101_4;
if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1101 == N2 &&
N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_224(N, X86::SHRD16mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_220(N, X86::SHRD16mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33881,37 +33159,37 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHLD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$amt1)
// Pattern complexity = 60 cost = 1 size = 3
if (Predicate_shld(N1.getNode())) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SHL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL &&
N11.hasOneUse()) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::LOAD &&
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
(Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getOperand(0);
+ SDValue Chain110 = N110.getNode()->getOperand(0);
if (Predicate_unindexedload(N110.getNode()) &&
Predicate_loadi16(N110.getNode())) {
- SDValue N1101 = N110.getOperand(1);
+ SDValue N1101 = N110.getNode()->getOperand(1);
SDValue CPTmpN1101_0;
SDValue CPTmpN1101_1;
SDValue CPTmpN1101_2;
SDValue CPTmpN1101_3;
SDValue CPTmpN1101_4;
if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1101 == N2 &&
N1.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_224(N, X86::SHLD16mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_220(N, X86::SHLD16mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33927,38 +33205,38 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHRD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$amt1)
// Pattern complexity = 60 cost = 1 size = 3
if (Predicate_shrd(N1.getNode())) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SHL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SRL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SHL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SRL &&
N11.hasOneUse()) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::LOAD &&
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
(Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getOperand(0);
+ SDValue Chain110 = N110.getNode()->getOperand(0);
if (Predicate_unindexedload(N110.getNode()) &&
Predicate_load(N110.getNode()) &&
Predicate_loadi64(N110.getNode())) {
- SDValue N1101 = N110.getOperand(1);
+ SDValue N1101 = N110.getNode()->getOperand(1);
SDValue CPTmpN1101_0;
SDValue CPTmpN1101_1;
SDValue CPTmpN1101_2;
SDValue CPTmpN1101_3;
SDValue CPTmpN1101_4;
if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1101 == N2 &&
N1.getValueType() == MVT::i64 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_224(N, X86::SHRD64mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_220(N, X86::SHRD64mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -33974,38 +33252,38 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHLD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$amt1)
// Pattern complexity = 60 cost = 1 size = 3
if (Predicate_shld(N1.getNode())) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SRL) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::SHL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRL) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::SHL &&
N11.hasOneUse()) {
- SDValue N110 = N11.getOperand(0);
- if (N110.getOpcode() == ISD::LOAD &&
+ SDValue N110 = N11.getNode()->getOperand(0);
+ if (N110.getNode()->getOpcode() == ISD::LOAD &&
N110.hasOneUse() &&
- IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N110.getNode(), N11.getNode(), N) &&
(Chain.getNode() == N110.getNode() || IsChainCompatible(Chain.getNode(), N110.getNode()))) {
- SDValue Chain110 = N110.getOperand(0);
+ SDValue Chain110 = N110.getNode()->getOperand(0);
if (Predicate_unindexedload(N110.getNode()) &&
Predicate_load(N110.getNode()) &&
Predicate_loadi64(N110.getNode())) {
- SDValue N1101 = N110.getOperand(1);
+ SDValue N1101 = N110.getNode()->getOperand(1);
SDValue CPTmpN1101_0;
SDValue CPTmpN1101_1;
SDValue CPTmpN1101_2;
SDValue CPTmpN1101_3;
SDValue CPTmpN1101_4;
if (SelectAddr(N, N1101, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4)) {
- SDValue N111 = N11.getOperand(1);
- if (N111.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ if (N111.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N1101 == N2 &&
N1.getValueType() == MVT::i64 &&
N101.getValueType() == MVT::i8 &&
N111.getValueType() == MVT::i8) {
- SDNode *Result = Emit_224(N, X86::SHLD64mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
+ SDNode *Result = Emit_220(N, X86::SHLD64mri8, CPTmpN1101_0, CPTmpN1101_1, CPTmpN1101_2, CPTmpN1101_3, CPTmpN1101_4);
return Result;
}
}
@@ -34017,14 +33295,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::SHL &&
+ if (N1.getNode()->getOpcode() == ISD::SHL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (shl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -34032,25 +33310,25 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 55 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0 &&
CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHL8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_201(N, X86::SHL8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34062,25 +33340,25 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHL16mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 55 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0 &&
CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHL16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_201(N, X86::SHL16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34092,25 +33370,25 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHL32mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 55 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0 &&
CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHL32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_201(N, X86::SHL32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34120,14 +33398,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::SRL &&
+ if (N1.getNode()->getOpcode() == ISD::SRL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (srl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -34135,25 +33413,25 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 55 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0 &&
CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_201(N, X86::SHR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34165,25 +33443,25 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHR16mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 55 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0 &&
CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_201(N, X86::SHR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34195,25 +33473,25 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHR32mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 55 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0 &&
CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_201(N, X86::SHR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34223,14 +33501,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::SRA &&
+ if (N1.getNode()->getOpcode() == ISD::SRA &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (sra:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (and:i8 CL:i8:$amt, 31:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -34238,25 +33516,25 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 55 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0 &&
CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SAR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_201(N, X86::SAR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34268,25 +33546,25 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SAR16mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 55 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0 &&
CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SAR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_201(N, X86::SAR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34298,25 +33576,25 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SAR32mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 55 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0 &&
CheckAndMask(N110, Tmp0, INT64_C(31))) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SAR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_201(N, X86::SAR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34330,36 +33608,36 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (and:i8 CL:i8:$amt, 63:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHL64mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 55 cost = 1 size = 3
- if (N1.getOpcode() == ISD::SHL &&
+ if (N1.getNode()->getOpcode() == ISD::SHL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0 &&
CheckAndMask(N110, Tmp0, INT64_C(63))) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHL64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_201(N, X86::SHL64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34372,36 +33650,36 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (and:i8 CL:i8:$amt, 63:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHR64mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 55 cost = 1 size = 3
- if (N1.getOpcode() == ISD::SRL &&
+ if (N1.getNode()->getOpcode() == ISD::SRL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0 &&
CheckAndMask(N110, Tmp0, INT64_C(63))) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SHR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_201(N, X86::SHR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34414,36 +33692,36 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (sra:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (and:i8 CL:i8:$amt, 63:i8)), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SAR64mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 55 cost = 1 size = 3
- if (N1.getOpcode() == ISD::SRA &&
+ if (N1.getNode()->getOpcode() == ISD::SRA &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::AND) {
- SDValue N110 = N11.getOperand(0);
- SDValue N111 = N11.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::AND) {
+ SDValue N110 = N11.getNode()->getOperand(0);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N111.getNode());
if (Tmp0 &&
CheckAndMask(N110, Tmp0, INT64_C(63))) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_204(N, X86::SAR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_201(N, X86::SAR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34452,19 +33730,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::SUB &&
+ if (N1.getNode()->getOpcode() == ISD::SUB &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::LOAD &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getOperand(0);
+ SDValue Chain11 = N11.getNode()->getOperand(0);
if (Predicate_unindexedload(N11.getNode())) {
// Pattern: (st:isVoid (sub:i8 0:i8, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -34472,17 +33750,17 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 52 cost = 1 size = 2
if (Predicate_load(N11.getNode()) &&
Predicate_loadi8(N11.getNode())) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue CPTmpN111_0;
SDValue CPTmpN111_1;
SDValue CPTmpN111_2;
SDValue CPTmpN111_3;
SDValue CPTmpN111_4;
if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N111 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_176(N, X86::NEG8m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_173(N, X86::NEG8m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -34492,17 +33770,17 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (NEG16m:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 2
if (Predicate_loadi16(N11.getNode())) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue CPTmpN111_0;
SDValue CPTmpN111_1;
SDValue CPTmpN111_2;
SDValue CPTmpN111_3;
SDValue CPTmpN111_4;
if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N111 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_176(N, X86::NEG16m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_173(N, X86::NEG16m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -34512,17 +33790,17 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (NEG32m:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 2
if (Predicate_loadi32(N11.getNode())) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue CPTmpN111_0;
SDValue CPTmpN111_1;
SDValue CPTmpN111_2;
SDValue CPTmpN111_3;
SDValue CPTmpN111_4;
if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N111 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_176(N, X86::NEG32m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_173(N, X86::NEG32m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -34536,33 +33814,33 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (add:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (INC8m:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 2
- if (N1.getOpcode() == ISD::ADD &&
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_178(N, X86::INC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_175(N, X86::INC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34574,40 +33852,40 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
if ((!Subtarget->is64Bit())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::ADD &&
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (INC16m:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 2
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::INC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_175(N, X86::INC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34619,22 +33897,22 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (INC32m:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 2
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_178(N, X86::INC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_175(N, X86::INC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34651,37 +33929,37 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (DEC8m:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 2
{
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::ADD &&
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(-1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_178(N, X86::DEC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_175(N, X86::DEC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34693,40 +33971,40 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
if ((!Subtarget->is64Bit())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::ADD &&
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, -1:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (DEC16m:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 2
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(-1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::DEC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_175(N, X86::DEC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34738,22 +34016,22 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (DEC32m:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 2
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(-1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_178(N, X86::DEC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_175(N, X86::DEC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34766,41 +34044,41 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
{
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
// Pattern: (st:isVoid (sub:i64 0:i64, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (NEG64m:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 2
- if (N1.getOpcode() == ISD::SUB &&
+ if (N1.getNode()->getOpcode() == ISD::SUB &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::LOAD &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getOperand(0);
+ SDValue Chain11 = N11.getNode()->getOperand(0);
if (Predicate_unindexedload(N11.getNode()) &&
Predicate_load(N11.getNode()) &&
Predicate_loadi64(N11.getNode())) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue CPTmpN111_0;
SDValue CPTmpN111_1;
SDValue CPTmpN111_2;
SDValue CPTmpN111_3;
SDValue CPTmpN111_4;
if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N111 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_176(N, X86::NEG64m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_173(N, X86::NEG64m, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -34809,26 +34087,26 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::ADD &&
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -34836,10 +34114,10 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (INC64m:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 2
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_178(N, X86::INC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_175(N, X86::INC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34848,10 +34126,10 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (DEC64m:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 2
if (CN1 == INT64_C(-1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_178(N, X86::DEC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_175(N, X86::DEC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34863,40 +34141,40 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
if ((Subtarget->is64Bit())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::ADD &&
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 1:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (INC64_16m:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 2
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::INC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_175(N, X86::INC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34908,22 +34186,22 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (INC64_32m:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 2
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_178(N, X86::INC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_175(N, X86::INC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34935,22 +34213,22 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (DEC64_16m:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 2
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(-1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_178(N, X86::DEC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_175(N, X86::DEC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34962,22 +34240,22 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (DEC64_32m:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 2
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(-1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_178(N, X86::DEC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_175(N, X86::DEC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -34990,18 +34268,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
{
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SHL &&
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SHL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (shl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -35009,23 +34287,23 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 52 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::SHL8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::SHL8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35037,23 +34315,23 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHL16m1:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::SHL16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::SHL16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35065,23 +34343,23 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHL32m1:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::SHL32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::SHL32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35091,14 +34369,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::SRL &&
+ if (N1.getNode()->getOpcode() == ISD::SRL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (srl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -35106,23 +34384,23 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 52 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::SHR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::SHR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35134,23 +34412,23 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHR16m1:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::SHR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::SHR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35162,23 +34440,23 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHR32m1:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::SHR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::SHR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35188,14 +34466,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::SRA &&
+ if (N1.getNode()->getOpcode() == ISD::SRA &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (sra:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -35203,23 +34481,23 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 52 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::SAR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::SAR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35231,23 +34509,23 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SAR16m1:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::SAR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::SAR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35259,23 +34537,23 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SAR32m1:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::SAR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::SAR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35285,14 +34563,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::ROTL &&
+ if (N1.getNode()->getOpcode() == ISD::ROTL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (rotl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -35300,23 +34578,23 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 52 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::ROL8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::ROL8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35328,23 +34606,23 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ROL16m1:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::ROL16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::ROL16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35356,23 +34634,23 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ROL32m1:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::ROL32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::ROL32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35382,14 +34660,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::ROTR &&
+ if (N1.getNode()->getOpcode() == ISD::ROTR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (rotr:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -35397,23 +34675,23 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 52 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::ROR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::ROR8m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35425,23 +34703,23 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ROR16m1:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::ROR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::ROR16m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35453,23 +34731,23 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ROR32m1:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::ROR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::ROR32m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35483,34 +34761,34 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHL64m1:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 3
- if (N1.getOpcode() == ISD::SHL &&
+ if (N1.getNode()->getOpcode() == ISD::SHL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::SHL64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::SHL64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35523,34 +34801,34 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHR64m1:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 3
- if (N1.getOpcode() == ISD::SRL &&
+ if (N1.getNode()->getOpcode() == ISD::SRL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::SHR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::SHR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35563,34 +34841,34 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (sra:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SAR64m1:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 3
- if (N1.getOpcode() == ISD::SRA &&
+ if (N1.getNode()->getOpcode() == ISD::SRA &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::SAR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::SAR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35603,34 +34881,34 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (rotl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ROL64m1:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 3
- if (N1.getOpcode() == ISD::ROTL &&
+ if (N1.getNode()->getOpcode() == ISD::ROTL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::ROL64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::ROL64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35643,34 +34921,34 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (rotr:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, 1:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ROR64m1:isVoid addr:iPTR:$dst)
// Pattern complexity = 52 cost = 1 size = 3
- if (N1.getOpcode() == ISD::ROTR &&
+ if (N1.getNode()->getOpcode() == ISD::ROTR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(1)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::ROR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::ROR64m1, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35679,36 +34957,36 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::ADD &&
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, 128:i16), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SUB16mi8:isVoid addr:iPTR:$dst, -128:i16)
// Pattern complexity = 52 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(128)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_202(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_199(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35720,22 +34998,22 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SUB32mi8:isVoid addr:iPTR:$dst, -128:i32)
// Pattern complexity = 52 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(128)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_203(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_200(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35744,15 +35022,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
if (Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -35760,10 +35038,10 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SUB64mi8:isVoid addr:iPTR:$dst, -128:i64)
// Pattern complexity = 52 cost = 1 size = 3
if (CN1 == INT64_C(128)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_211(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_208(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35772,10 +35050,10 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SUB64mi32:isVoid addr:iPTR:$dst, -2147483648:i64)
// Pattern complexity = 52 cost = 1 size = 3
if (CN1 == INT64_C(34359738368)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_212(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_209(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35785,14 +35063,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::XOR &&
+ if (N1.getNode()->getOpcode() == ISD::XOR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (xor:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8)<<P:Predicate_immAllOnes>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -35800,20 +35078,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 51 cost = 1 size = 2
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_177(N, X86::NOT8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::NOT8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35824,20 +35102,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (NOT16m:isVoid addr:iPTR:$dst)
// Pattern complexity = 51 cost = 1 size = 2
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_177(N, X86::NOT16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::NOT16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35848,20 +35126,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (NOT32m:isVoid addr:iPTR:$dst)
// Pattern complexity = 51 cost = 1 size = 2
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_177(N, X86::NOT32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::NOT32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35870,34 +35148,34 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::AND &&
+ if (N1.getNode()->getOpcode() == ISD::AND &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (st:isVoid (and:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (AND16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_181(N, X86::AND16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::AND16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35906,10 +35184,10 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_182(N, X86::AND32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::AND32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35918,34 +35196,34 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::OR &&
+ if (N1.getNode()->getOpcode() == ISD::OR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (st:isVoid (or:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (OR16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_181(N, X86::OR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::OR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35954,10 +35232,10 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_182(N, X86::OR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::OR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -35966,34 +35244,34 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::XOR &&
+ if (N1.getNode()->getOpcode() == ISD::XOR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (st:isVoid (xor:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (XOR16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_181(N, X86::XOR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::XOR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36002,10 +35280,10 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_182(N, X86::XOR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::XOR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36014,34 +35292,34 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::ADD &&
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (st:isVoid (add:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ADD16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_181(N, X86::ADD16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::ADD16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36050,10 +35328,10 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADD32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_182(N, X86::ADD32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::ADD32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36062,34 +35340,34 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::ADDE &&
+ if (N1.getNode()->getOpcode() == ISD::ADDE &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (st:isVoid (adde:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ADC16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_189(N, X86::ADC16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_186(N, X86::ADC16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36098,10 +35376,10 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADC32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_190(N, X86::ADC32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_187(N, X86::ADC32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36110,34 +35388,34 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::SUB &&
+ if (N1.getNode()->getOpcode() == ISD::SUB &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (st:isVoid (sub:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SUB16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_181(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36146,10 +35424,10 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SUB32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_182(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36158,34 +35436,34 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::SUBE &&
+ if (N1.getNode()->getOpcode() == ISD::SUBE &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (st:isVoid (sube:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SBB16mi8:isVoid addr:iPTR:$dst, (imm:i16):$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_189(N, X86::SBB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_186(N, X86::SBB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36194,10 +35472,10 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SBB32mi8:isVoid addr:iPTR:$dst, (imm:i32):$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_190(N, X86::SBB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_187(N, X86::SBB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36206,34 +35484,34 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::ADD &&
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ADD64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_193(N, X86::ADD64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::ADD64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36242,10 +35520,10 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADD64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_193(N, X86::ADD64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::ADD64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36254,27 +35532,27 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::ADDE &&
+ if (N1.getNode()->getOpcode() == ISD::ADDE &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
@@ -36282,14 +35560,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADC64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
// Pattern complexity = 51 cost = 1 size = 3
{
- SDNode *Result = Emit_194(N, X86::ADC64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_191(N, X86::ADC64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
// Pattern: (st:isVoid (adde:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ADC64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
// Pattern complexity = 51 cost = 1 size = 3
- SDNode *Result = Emit_194(N, X86::ADC64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_191(N, X86::ADC64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36297,34 +35575,34 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::SUB &&
+ if (N1.getNode()->getOpcode() == ISD::SUB &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (st:isVoid (sub:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SUB64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_193(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36333,10 +35611,10 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SUB64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_193(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36345,34 +35623,34 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::SUBE &&
+ if (N1.getNode()->getOpcode() == ISD::SUBE &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (st:isVoid (sube:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SBB64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_194(N, X86::SBB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_191(N, X86::SBB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36381,10 +35659,10 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SBB64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_194(N, X86::SBB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_191(N, X86::SBB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36397,31 +35675,31 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (xor:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_immAllOnes>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (NOT64m:isVoid addr:iPTR:$dst)
// Pattern complexity = 51 cost = 1 size = 3
- if (N1.getOpcode() == ISD::XOR &&
+ if (N1.getNode()->getOpcode() == ISD::XOR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_immAllOnes(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_177(N, X86::NOT64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_174(N, X86::NOT64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36429,14 +35707,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::AND &&
+ if (N1.getNode()->getOpcode() == ISD::AND &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
@@ -36444,20 +35722,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src)
// Pattern complexity = 51 cost = 1 size = 3
{
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_193(N, X86::AND64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::AND64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36468,20 +35746,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_193(N, X86::AND64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::AND64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36490,14 +35768,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::OR &&
+ if (N1.getNode()->getOpcode() == ISD::OR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
@@ -36505,20 +35783,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src)
// Pattern complexity = 51 cost = 1 size = 3
{
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_193(N, X86::OR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::OR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36529,20 +35807,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_193(N, X86::OR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::OR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36551,14 +35829,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::XOR &&
+ if (N1.getNode()->getOpcode() == ISD::XOR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
@@ -36566,20 +35844,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR64mi8:isVoid addr:iPTR:$dst, (imm:i64):$src)
// Pattern complexity = 51 cost = 1 size = 3
{
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_193(N, X86::XOR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::XOR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36590,20 +35868,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_193(N, X86::XOR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::XOR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36612,34 +35890,34 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::ADD &&
+ if (N1.getNode()->getOpcode() == X86ISD::ADD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (X86add_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ADD16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_181(N, X86::ADD16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::ADD16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36650,20 +35928,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADD32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_182(N, X86::ADD32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::ADD32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36672,34 +35950,34 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::SUB &&
+ if (N1.getNode()->getOpcode() == X86ISD::SUB &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (X86sub_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SUB16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_181(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::SUB16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36710,20 +35988,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SUB32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_182(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::SUB32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36732,34 +36010,34 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::OR &&
+ if (N1.getNode()->getOpcode() == X86ISD::OR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (X86or_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (OR16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_181(N, X86::OR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::OR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36770,20 +36048,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_182(N, X86::OR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::OR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36792,34 +36070,34 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::XOR &&
+ if (N1.getNode()->getOpcode() == X86ISD::XOR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (X86xor_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (XOR16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_181(N, X86::XOR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::XOR16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36830,20 +36108,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_182(N, X86::XOR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::XOR32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36852,34 +36130,34 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::AND &&
+ if (N1.getNode()->getOpcode() == X86ISD::AND &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (X86and_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (AND16mi8:isVoid addr:iPTR:$dst, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_i16immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_181(N, X86::AND16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::AND16mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36890,20 +36168,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND32mi8:isVoid addr:iPTR:$dst, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant &&
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant &&
Predicate_i32immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_182(N, X86::AND32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::AND32mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36912,35 +36190,35 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::ADD &&
+ if (N1.getNode()->getOpcode() == X86ISD::ADD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (st:isVoid (X86add_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ADD64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_193(N, X86::ADD64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::ADD64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36949,10 +36227,10 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADD64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_193(N, X86::ADD64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::ADD64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36961,35 +36239,35 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::SUB &&
+ if (N1.getNode()->getOpcode() == X86ISD::SUB &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (st:isVoid (X86sub_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SUB64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_193(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::SUB64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -36998,10 +36276,10 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SUB64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_193(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::SUB64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37010,35 +36288,35 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::OR &&
+ if (N1.getNode()->getOpcode() == X86ISD::OR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (st:isVoid (X86or_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (OR64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_193(N, X86::OR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::OR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37047,10 +36325,10 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_193(N, X86::OR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::OR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37059,35 +36337,35 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::XOR &&
+ if (N1.getNode()->getOpcode() == X86ISD::XOR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (st:isVoid (X86xor_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (XOR64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_193(N, X86::XOR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::XOR64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37096,10 +36374,10 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_193(N, X86::XOR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::XOR64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37108,35 +36386,35 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::AND &&
+ if (N1.getNode()->getOpcode() == X86ISD::AND &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (st:isVoid (X86and_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (AND64mi8:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i64immSExt8(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_193(N, X86::AND64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::AND64mi8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37145,10 +36423,10 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND64mi32:isVoid addr:iPTR:$dst, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if (Predicate_i64immSExt32(N11.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_193(N, X86::AND64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_190(N, X86::AND64mi32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37164,37 +36442,37 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVLPSmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
// Pattern complexity = 51 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::VECTOR_SHUFFLE &&
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE &&
N1.hasOneUse() &&
Predicate_movlp(N1.getNode())) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N) &&
(Chain.getNode() == N100.getNode() || IsChainCompatible(Chain.getNode(), N100.getNode()))) {
- SDValue Chain100 = N100.getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_load(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
SDValue CPTmpN1001_3;
SDValue CPTmpN1001_4;
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N1001 == N2 &&
N1.getValueType() == MVT::v4i32 &&
N100.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_218(N, X86::MOVLPSmr, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_214(N, X86::MOVLPSmr, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -37205,18 +36483,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
{
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::AND &&
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::AND &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (and:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -37224,19 +36502,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::AND8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::AND8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37247,19 +36525,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_181(N, X86::AND16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::AND16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37270,19 +36548,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND32mi:isVoid addr:iPTR:$dst, (imm:i32):$src)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_182(N, X86::AND32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::AND32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37291,14 +36569,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::OR &&
+ if (N1.getNode()->getOpcode() == ISD::OR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (or:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -37306,19 +36584,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::OR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::OR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37329,19 +36607,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_181(N, X86::OR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::OR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37352,19 +36630,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR32mi:isVoid addr:iPTR:$dst, (imm:i32):$src)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_182(N, X86::OR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::OR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37373,14 +36651,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::XOR &&
+ if (N1.getNode()->getOpcode() == ISD::XOR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (xor:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -37388,19 +36666,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::XOR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::XOR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37411,19 +36689,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_181(N, X86::XOR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::XOR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37434,19 +36712,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR32mi:isVoid addr:iPTR:$dst, (imm:i32):$src)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_182(N, X86::XOR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::XOR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37455,14 +36733,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::SHL &&
+ if (N1.getNode()->getOpcode() == ISD::SHL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (shl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -37470,20 +36748,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::SHL8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::SHL8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37494,20 +36772,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHL16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::SHL16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::SHL16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37518,20 +36796,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHL32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::SHL32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::SHL32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37540,14 +36818,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::SRL &&
+ if (N1.getNode()->getOpcode() == ISD::SRL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (srl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -37555,20 +36833,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::SHR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::SHR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37579,20 +36857,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHR16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::SHR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::SHR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37603,20 +36881,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHR32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::SHR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::SHR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37625,14 +36903,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::SRA &&
+ if (N1.getNode()->getOpcode() == ISD::SRA &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (sra:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -37640,20 +36918,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::SAR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::SAR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37664,20 +36942,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SAR16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::SAR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::SAR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37688,20 +36966,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SAR32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::SAR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::SAR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37710,14 +36988,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::ROTL &&
+ if (N1.getNode()->getOpcode() == ISD::ROTL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (rotl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -37725,20 +37003,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::ROL8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::ROL8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37749,20 +37027,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ROL16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::ROL16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::ROL16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37773,20 +37051,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ROL32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::ROL32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::ROL32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37795,14 +37073,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::ROTR &&
+ if (N1.getNode()->getOpcode() == ISD::ROTR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (rotr:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -37810,20 +37088,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::ROR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::ROR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37834,20 +37112,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ROR16mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::ROR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::ROR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37858,20 +37136,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ROR32mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::ROR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::ROR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37884,31 +37162,31 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86shld:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHLD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$src3)
// Pattern complexity = 50 cost = 1 size = 3
- if (N1.getOpcode() == X86ISD::SHLD &&
+ if (N1.getNode()->getOpcode() == X86ISD::SHLD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N12 = N1.getOperand(2);
- if (N12.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
+ if (N12.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_186(N, X86::SHLD32mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::SHLD32mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37920,31 +37198,31 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86shrd:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHRD32mri8:isVoid addr:iPTR:$dst, GR32:i32:$src2, (imm:i8):$src3)
// Pattern complexity = 50 cost = 1 size = 3
- if (N1.getOpcode() == X86ISD::SHRD &&
+ if (N1.getNode()->getOpcode() == X86ISD::SHRD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N12 = N1.getOperand(2);
- if (N12.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
+ if (N12.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_186(N, X86::SHRD32mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::SHRD32mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37956,31 +37234,31 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86shld:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHLD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$src3)
// Pattern complexity = 50 cost = 1 size = 3
- if (N1.getOpcode() == X86ISD::SHLD &&
+ if (N1.getNode()->getOpcode() == X86ISD::SHLD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N12 = N1.getOperand(2);
- if (N12.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
+ if (N12.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_186(N, X86::SHLD16mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::SHLD16mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -37992,31 +37270,31 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86shrd:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHRD16mri8:isVoid addr:iPTR:$dst, GR16:i16:$src2, (imm:i8):$src3)
// Pattern complexity = 50 cost = 1 size = 3
- if (N1.getOpcode() == X86ISD::SHRD &&
+ if (N1.getNode()->getOpcode() == X86ISD::SHRD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N12 = N1.getOperand(2);
- if (N12.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
+ if (N12.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_186(N, X86::SHRD16mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::SHRD16mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38024,14 +37302,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::ADD &&
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (add:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -38039,19 +37317,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::ADD8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::ADD8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38062,19 +37340,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADD16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_181(N, X86::ADD16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::ADD16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38085,19 +37363,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADD32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_182(N, X86::ADD32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::ADD32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38106,14 +37384,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::ADDE &&
+ if (N1.getNode()->getOpcode() == ISD::ADDE &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (adde:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -38121,19 +37399,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_188(N, X86::ADC8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_185(N, X86::ADC8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38144,19 +37422,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADC16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_189(N, X86::ADC16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_186(N, X86::ADC16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38167,19 +37445,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADC32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_190(N, X86::ADC32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_187(N, X86::ADC32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38188,14 +37466,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::SUB &&
+ if (N1.getNode()->getOpcode() == ISD::SUB &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (sub:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -38203,19 +37481,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SUB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::SUB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38226,19 +37504,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SUB16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_181(N, X86::SUB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::SUB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38249,19 +37527,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SUB32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_182(N, X86::SUB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::SUB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38270,14 +37548,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::SUBE &&
+ if (N1.getNode()->getOpcode() == ISD::SUBE &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (sube:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -38285,19 +37563,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_188(N, X86::SBB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_185(N, X86::SBB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38308,19 +37586,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SBB16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_189(N, X86::SBB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_186(N, X86::SBB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38331,19 +37609,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SBB32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_190(N, X86::SBB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_187(N, X86::SBB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38356,31 +37634,31 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHL64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
// Pattern complexity = 50 cost = 1 size = 3
- if (N1.getOpcode() == ISD::SHL &&
+ if (N1.getNode()->getOpcode() == ISD::SHL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::SHL64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::SHL64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38392,31 +37670,31 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHR64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
// Pattern complexity = 50 cost = 1 size = 3
- if (N1.getOpcode() == ISD::SRL &&
+ if (N1.getNode()->getOpcode() == ISD::SRL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::SHR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::SHR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38428,31 +37706,31 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (sra:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SAR64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
// Pattern complexity = 50 cost = 1 size = 3
- if (N1.getOpcode() == ISD::SRA &&
+ if (N1.getNode()->getOpcode() == ISD::SRA &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::SAR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::SAR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38464,31 +37742,31 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (rotl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ROL64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
// Pattern complexity = 50 cost = 1 size = 3
- if (N1.getOpcode() == ISD::ROTL &&
+ if (N1.getNode()->getOpcode() == ISD::ROTL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::ROL64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::ROL64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38500,31 +37778,31 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (rotr:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i8):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ROR64mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
// Pattern complexity = 50 cost = 1 size = 3
- if (N1.getOpcode() == ISD::ROTR &&
+ if (N1.getNode()->getOpcode() == ISD::ROTR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_184(N, X86::ROR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_181(N, X86::ROR64mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38536,32 +37814,32 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86shld:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHLD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$src3)
// Pattern complexity = 50 cost = 1 size = 3
- if (N1.getOpcode() == X86ISD::SHLD &&
+ if (N1.getNode()->getOpcode() == X86ISD::SHLD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N12 = N1.getOperand(2);
- if (N12.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
+ if (N12.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_186(N, X86::SHLD64mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::SHLD64mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38573,32 +37851,32 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86shrd:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, (imm:i8):$src3), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHRD64mri8:isVoid addr:iPTR:$dst, GR64:i64:$src2, (imm:i8):$src3)
// Pattern complexity = 50 cost = 1 size = 3
- if (N1.getOpcode() == X86ISD::SHRD &&
+ if (N1.getNode()->getOpcode() == X86ISD::SHRD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N12 = N1.getOperand(2);
- if (N12.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
+ if (N12.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_186(N, X86::SHRD64mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_183(N, X86::SHRD64mri8, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38606,14 +37884,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::ADD &&
+ if (N1.getNode()->getOpcode() == X86ISD::ADD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (X86add_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -38621,19 +37899,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::ADD8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::ADD8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38644,19 +37922,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADD16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_181(N, X86::ADD16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::ADD16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38667,19 +37945,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADD32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_182(N, X86::ADD32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::ADD32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38688,14 +37966,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::SUB &&
+ if (N1.getNode()->getOpcode() == X86ISD::SUB &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (X86sub_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -38703,19 +37981,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::SUB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::SUB8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38726,19 +38004,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SUB16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_181(N, X86::SUB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::SUB16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38749,19 +38027,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SUB32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_182(N, X86::SUB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::SUB32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38770,14 +38048,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::OR &&
+ if (N1.getNode()->getOpcode() == X86ISD::OR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (X86or_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -38785,19 +38063,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::OR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::OR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38808,19 +38086,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_181(N, X86::OR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::OR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38831,19 +38109,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_182(N, X86::OR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::OR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38852,14 +38130,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::XOR &&
+ if (N1.getNode()->getOpcode() == X86ISD::XOR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (X86xor_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -38867,19 +38145,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::XOR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::XOR8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38890,19 +38168,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_181(N, X86::XOR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::XOR16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38913,19 +38191,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_182(N, X86::XOR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::XOR32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38934,14 +38212,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::AND &&
+ if (N1.getNode()->getOpcode() == X86ISD::AND &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (X86and_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, (imm:i8):$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -38949,19 +38227,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_180(N, X86::AND8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_177(N, X86::AND8mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38972,19 +38250,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND16mi:isVoid addr:iPTR:$dst, (imm:i16):$src2)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_181(N, X86::AND16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_178(N, X86::AND16mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -38995,19 +38273,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND32mi:isVoid addr:iPTR:$dst, (imm:i32):$src2)
// Pattern complexity = 50 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_182(N, X86::AND32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_179(N, X86::AND32mi, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39023,33 +38301,33 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVLPSmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
// Pattern complexity = 48 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::VECTOR_SHUFFLE &&
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE &&
N1.hasOneUse() &&
Predicate_movlp(N1.getNode())) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_217(N, X86::MOVLPSmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_213(N, X86::MOVLPSmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39059,37 +38337,37 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::VECTOR_SHUFFLE &&
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE &&
N1.hasOneUse() &&
Predicate_movlp(N1.getNode())) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2) {
// Pattern: (st:isVoid (vector_shuffle:v2f64 (ld:v2f64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR128:v2f64:$src2)<<P:Predicate_movlp>>, addr:iPTR:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (MOVLPDmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
// Pattern complexity = 48 cost = 1 size = 3
if (N1.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_217(N, X86::MOVLPDmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_213(N, X86::MOVLPDmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -39097,7 +38375,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVLPDmr:isVoid addr:iPTR:$src1, VR128:v16i8:$src2)
// Pattern complexity = 48 cost = 1 size = 3
if (N1.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_217(N, X86::MOVLPDmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_213(N, X86::MOVLPDmr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39108,37 +38386,37 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
{
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
// Pattern: (st:isVoid (X86inc_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (INC8m:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 2
- if (N1.getOpcode() == X86ISD::INC &&
+ if (N1.getNode()->getOpcode() == X86ISD::INC &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N10.getValueType() == MVT::i8) {
- SDNode *Result = Emit_209(N, X86::INC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_206(N, X86::INC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39149,29 +38427,29 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86dec_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (DEC8m:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 2
- if (N1.getOpcode() == X86ISD::DEC &&
+ if (N1.getNode()->getOpcode() == X86ISD::DEC &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N10.getValueType() == MVT::i8) {
- SDNode *Result = Emit_209(N, X86::DEC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_206(N, X86::DEC8m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39181,36 +38459,36 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
if ((!Subtarget->is64Bit())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
// Pattern: (st:isVoid (X86inc_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (INC16m:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 2
- if (N1.getOpcode() == X86ISD::INC &&
+ if (N1.getNode()->getOpcode() == X86ISD::INC &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N10.getValueType() == MVT::i16) {
- SDNode *Result = Emit_209(N, X86::INC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_206(N, X86::INC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39221,28 +38499,28 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86dec_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (DEC16m:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 2
- if (N1.getOpcode() == X86ISD::DEC &&
+ if (N1.getNode()->getOpcode() == X86ISD::DEC &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N10.getValueType() == MVT::i16) {
- SDNode *Result = Emit_209(N, X86::DEC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_206(N, X86::DEC16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39253,28 +38531,28 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86inc_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (INC32m:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 2
- if (N1.getOpcode() == X86ISD::INC &&
+ if (N1.getNode()->getOpcode() == X86ISD::INC &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N10.getValueType() == MVT::i32) {
- SDNode *Result = Emit_209(N, X86::INC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_206(N, X86::INC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39285,28 +38563,28 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86dec_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (DEC32m:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 2
- if (N1.getOpcode() == X86ISD::DEC &&
+ if (N1.getNode()->getOpcode() == X86ISD::DEC &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N10.getValueType() == MVT::i32) {
- SDNode *Result = Emit_209(N, X86::DEC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_206(N, X86::DEC32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39316,36 +38594,36 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
if ((Subtarget->is64Bit())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
// Pattern: (st:isVoid (X86inc_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (INC64_16m:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 2
- if (N1.getOpcode() == X86ISD::INC &&
+ if (N1.getNode()->getOpcode() == X86ISD::INC &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N10.getValueType() == MVT::i16) {
- SDNode *Result = Emit_209(N, X86::INC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_206(N, X86::INC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39356,28 +38634,28 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86dec_flag:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (DEC64_16m:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 2
- if (N1.getOpcode() == X86ISD::DEC &&
+ if (N1.getNode()->getOpcode() == X86ISD::DEC &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N10.getValueType() == MVT::i16) {
- SDNode *Result = Emit_209(N, X86::DEC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_206(N, X86::DEC64_16m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39388,28 +38666,28 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86inc_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (INC64_32m:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 2
- if (N1.getOpcode() == X86ISD::INC &&
+ if (N1.getNode()->getOpcode() == X86ISD::INC &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N10.getValueType() == MVT::i32) {
- SDNode *Result = Emit_209(N, X86::INC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_206(N, X86::INC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39420,28 +38698,28 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86dec_flag:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (DEC64_32m:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 2
- if (N1.getOpcode() == X86ISD::DEC &&
+ if (N1.getNode()->getOpcode() == X86ISD::DEC &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N10.getValueType() == MVT::i32) {
- SDNode *Result = Emit_209(N, X86::DEC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_206(N, X86::DEC64_32m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39450,37 +38728,37 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
// Pattern: (st:isVoid (X86inc_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (INC64m:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 2
- if (N1.getOpcode() == X86ISD::INC &&
+ if (N1.getNode()->getOpcode() == X86ISD::INC &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N10.getValueType() == MVT::i64) {
- SDNode *Result = Emit_209(N, X86::INC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_206(N, X86::INC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39491,61 +38769,61 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86dec_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (DEC64m:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 2
- if (N1.getOpcode() == X86ISD::DEC &&
+ if (N1.getNode()->getOpcode() == X86ISD::DEC &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N10.getValueType() == MVT::i64) {
- SDNode *Result = Emit_209(N, X86::DEC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_206(N, X86::DEC64m, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
}
- if (N1.getOpcode() == ISD::AND &&
+ if (N1.getNode()->getOpcode() == ISD::AND &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2) {
// Pattern: (st:isVoid (and:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (AND8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_179(N, X86::AND8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::AND8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -39553,7 +38831,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_179(N, X86::AND16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::AND16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -39561,7 +38839,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::AND32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::AND32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39569,32 +38847,32 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::OR &&
+ if (N1.getNode()->getOpcode() == ISD::OR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2) {
// Pattern: (st:isVoid (or:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (OR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_179(N, X86::OR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::OR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -39602,7 +38880,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_179(N, X86::OR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::OR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -39610,7 +38888,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::OR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::OR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39618,32 +38896,32 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::XOR &&
+ if (N1.getNode()->getOpcode() == ISD::XOR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2) {
// Pattern: (st:isVoid (xor:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (XOR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_179(N, X86::XOR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::XOR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -39651,7 +38929,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_179(N, X86::XOR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::XOR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -39659,7 +38937,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::XOR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::XOR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39667,14 +38945,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::SHL &&
+ if (N1.getNode()->getOpcode() == ISD::SHL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (shl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -39682,19 +38960,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHL8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::SHL8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39704,19 +38982,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHL16mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHL16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::SHL16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39726,19 +39004,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHL32mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHL32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::SHL32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39746,14 +39024,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::SRL &&
+ if (N1.getNode()->getOpcode() == ISD::SRL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (srl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -39761,19 +39039,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::SHR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39783,19 +39061,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHR16mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::SHR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39805,19 +39083,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SHR32mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::SHR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39825,14 +39103,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::SRA &&
+ if (N1.getNode()->getOpcode() == ISD::SRA &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (sra:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -39840,19 +39118,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SAR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::SAR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39862,19 +39140,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SAR16mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SAR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::SAR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39884,19 +39162,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SAR32mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SAR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::SAR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39904,14 +39182,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::ROTL &&
+ if (N1.getNode()->getOpcode() == ISD::ROTL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (rotl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -39919,19 +39197,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::ROL8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::ROL8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39941,19 +39219,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ROL16mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::ROL16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::ROL16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39963,19 +39241,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ROL32mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::ROL32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::ROL32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -39983,14 +39261,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::ROTR &&
+ if (N1.getNode()->getOpcode() == ISD::ROTR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (rotr:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -39998,19 +39276,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::ROR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::ROR8mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40020,19 +39298,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ROR16mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::ROR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::ROR16mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40042,19 +39320,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ROR32mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::ROR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::ROR32mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40066,30 +39344,30 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86shld:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHLD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == X86ISD::SHLD &&
+ if (N1.getNode()->getOpcode() == X86ISD::SHLD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N12 = N1.getOperand(2);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_185(N, X86::SHLD32mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::SHLD32mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40100,30 +39378,30 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86shrd:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHRD32mrCL:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == X86ISD::SHRD &&
+ if (N1.getNode()->getOpcode() == X86ISD::SHRD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N12 = N1.getOperand(2);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_185(N, X86::SHRD32mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::SHRD32mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40134,30 +39412,30 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86shld:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHLD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == X86ISD::SHLD &&
+ if (N1.getNode()->getOpcode() == X86ISD::SHLD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N12 = N1.getOperand(2);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_185(N, X86::SHLD16mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::SHLD16mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40168,62 +39446,62 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86shrd:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src2, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHRD16mrCL:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == X86ISD::SHRD &&
+ if (N1.getNode()->getOpcode() == X86ISD::SHRD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N12 = N1.getOperand(2);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_185(N, X86::SHRD16mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::SHRD16mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
}
- if (N1.getOpcode() == ISD::ADD &&
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2) {
// Pattern: (st:isVoid (add:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ADD8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_179(N, X86::ADD8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::ADD8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -40231,7 +39509,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADD16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_179(N, X86::ADD16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::ADD16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -40239,7 +39517,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADD32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::ADD32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::ADD32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40247,32 +39525,32 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::ADDE &&
+ if (N1.getNode()->getOpcode() == ISD::ADDE &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2) {
// Pattern: (st:isVoid (adde:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ADC8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_187(N, X86::ADC8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::ADC8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -40280,7 +39558,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADC16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_187(N, X86::ADC16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::ADC16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -40288,7 +39566,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADC32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_187(N, X86::ADC32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::ADC32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40296,32 +39574,32 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::SUB &&
+ if (N1.getNode()->getOpcode() == ISD::SUB &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2) {
// Pattern: (st:isVoid (sub:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SUB8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_179(N, X86::SUB8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::SUB8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -40329,7 +39607,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SUB16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_179(N, X86::SUB16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::SUB16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -40337,7 +39615,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SUB32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::SUB32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::SUB32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40345,32 +39623,32 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::SUBE &&
+ if (N1.getNode()->getOpcode() == ISD::SUBE &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2) {
// Pattern: (st:isVoid (sube:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SBB8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_187(N, X86::SBB8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::SBB8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -40378,7 +39656,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SBB16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_187(N, X86::SBB16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::SBB16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
@@ -40386,7 +39664,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SBB32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_187(N, X86::SBB32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::SBB32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40398,28 +39676,28 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (add:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ADD64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == ISD::ADD &&
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_179(N, X86::ADD64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::ADD64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40430,28 +39708,28 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (adde:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ADC64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == ISD::ADDE &&
+ if (N1.getNode()->getOpcode() == ISD::ADDE &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_187(N, X86::ADC64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::ADC64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40462,28 +39740,28 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (sub:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SUB64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == ISD::SUB &&
+ if (N1.getNode()->getOpcode() == ISD::SUB &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_179(N, X86::SUB64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::SUB64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40494,28 +39772,28 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (sube:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SBB64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == ISD::SUBE &&
+ if (N1.getNode()->getOpcode() == ISD::SUBE &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_187(N, X86::SBB64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_184(N, X86::SBB64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40526,30 +39804,30 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (shl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHL64mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == ISD::SHL &&
+ if (N1.getNode()->getOpcode() == ISD::SHL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHL64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::SHL64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40560,30 +39838,30 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (srl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHR64mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == ISD::SRL &&
+ if (N1.getNode()->getOpcode() == ISD::SRL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SHR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::SHR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40594,30 +39872,30 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (sra:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SAR64mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == ISD::SRA &&
+ if (N1.getNode()->getOpcode() == ISD::SRA &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::SAR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::SAR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40628,30 +39906,30 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (rotl:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ROL64mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == ISD::ROTL &&
+ if (N1.getNode()->getOpcode() == ISD::ROTL &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::ROL64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::ROL64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40662,30 +39940,30 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (rotr:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ROR64mCL:isVoid addr:iPTR:$dst)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == ISD::ROTR &&
+ if (N1.getNode()->getOpcode() == ISD::ROTR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N11.getValueType() == MVT::i8) {
- SDNode *Result = Emit_183(N, X86::ROR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_180(N, X86::ROR64mCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40696,31 +39974,31 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86shld:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHLD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == X86ISD::SHLD &&
+ if (N1.getNode()->getOpcode() == X86ISD::SHLD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N12 = N1.getOperand(2);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_185(N, X86::SHLD64mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::SHLD64mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40731,31 +40009,31 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86shrd:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2, CL:i8), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SHRD64mrCL:isVoid addr:iPTR:$dst, GR64:i64:$src2)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == X86ISD::SHRD &&
+ if (N1.getNode()->getOpcode() == X86ISD::SHRD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N12 = N1.getOperand(2);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N12 = N1.getNode()->getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64 &&
N12.getValueType() == MVT::i8) {
- SDNode *Result = Emit_185(N, X86::SHRD64mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_182(N, X86::SHRD64mrCL, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40766,28 +40044,28 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (and:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (AND64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == ISD::AND &&
+ if (N1.getNode()->getOpcode() == ISD::AND &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_179(N, X86::AND64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::AND64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40798,28 +40076,28 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (or:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (OR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == ISD::OR &&
+ if (N1.getNode()->getOpcode() == ISD::OR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_179(N, X86::OR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::OR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40830,42 +40108,42 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (xor:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (XOR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == ISD::XOR &&
+ if (N1.getNode()->getOpcode() == ISD::XOR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_179(N, X86::XOR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::XOR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
}
- if (N1.getOpcode() == X86ISD::ADD &&
+ if (N1.getNode()->getOpcode() == X86ISD::ADD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (X86add_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -40873,18 +40151,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_179(N, X86::ADD8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::ADD8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40894,18 +40172,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADD16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_179(N, X86::ADD16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::ADD16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40915,18 +40193,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADD32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::ADD32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::ADD32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40934,14 +40212,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::SUB &&
+ if (N1.getNode()->getOpcode() == X86ISD::SUB &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (X86sub_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -40949,18 +40227,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_179(N, X86::SUB8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::SUB8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40970,18 +40248,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SUB16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_179(N, X86::SUB16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::SUB16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -40991,18 +40269,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SUB32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::SUB32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::SUB32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41010,14 +40288,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::OR &&
+ if (N1.getNode()->getOpcode() == X86ISD::OR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (X86or_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -41025,18 +40303,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_179(N, X86::OR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::OR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41046,18 +40324,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_179(N, X86::OR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::OR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41067,18 +40345,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::OR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::OR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41086,14 +40364,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::XOR &&
+ if (N1.getNode()->getOpcode() == X86ISD::XOR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (X86xor_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -41101,18 +40379,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_179(N, X86::XOR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::XOR8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41122,18 +40400,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_179(N, X86::XOR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::XOR16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41143,18 +40421,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::XOR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::XOR32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41162,14 +40440,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == X86ISD::AND &&
+ if (N1.getNode()->getOpcode() == X86ISD::AND &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode())) {
// Pattern: (st:isVoid (X86and_flag:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
@@ -41177,18 +40455,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_load(N10.getNode()) &&
Predicate_loadi8(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_179(N, X86::AND8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::AND8mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41198,18 +40476,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_179(N, X86::AND16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::AND16mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41219,18 +40497,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (Predicate_loadi32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_179(N, X86::AND32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::AND32mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41242,29 +40520,29 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86add_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ADD64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == X86ISD::ADD &&
+ if (N1.getNode()->getOpcode() == X86ISD::ADD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_179(N, X86::ADD64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::ADD64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41275,29 +40553,29 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86sub_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (SUB64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == X86ISD::SUB &&
+ if (N1.getNode()->getOpcode() == X86ISD::SUB &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_179(N, X86::SUB64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::SUB64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41308,29 +40586,29 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86or_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (OR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == X86ISD::OR &&
+ if (N1.getNode()->getOpcode() == X86ISD::OR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_179(N, X86::OR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::OR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41341,29 +40619,29 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86xor_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (XOR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == X86ISD::XOR &&
+ if (N1.getNode()->getOpcode() == X86ISD::XOR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_179(N, X86::XOR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::XOR64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -41374,61 +40652,61 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86and_flag:i64 (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (AND64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == X86ISD::AND &&
+ if (N1.getNode()->getOpcode() == X86ISD::AND &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N10.getNode() || IsChainCompatible(Chain.getNode(), N10.getNode()))) {
- SDValue Chain10 = N10.getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadi64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
if (N101 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_179(N, X86::AND64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_176(N, X86::AND64mr, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
}
}
}
- if (N1.getOpcode() == ISD::AND &&
+ if (N1.getNode()->getOpcode() == ISD::AND &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getOperand(0);
+ SDValue Chain11 = N11.getNode()->getOperand(0);
if (Predicate_unindexedload(N11.getNode()) &&
Predicate_load(N11.getNode())) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue CPTmpN111_0;
SDValue CPTmpN111_1;
SDValue CPTmpN111_2;
SDValue CPTmpN111_3;
SDValue CPTmpN111_4;
if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N111 == N2) {
// Pattern: (st:isVoid (and:i8 GR8:i8:$src, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (AND8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_220(N, X86::AND8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_216(N, X86::AND8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
@@ -41436,7 +40714,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_220(N, X86::AND16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_216(N, X86::AND16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
@@ -41444,7 +40722,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (AND32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_220(N, X86::AND32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_216(N, X86::AND32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -41452,32 +40730,32 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::OR &&
+ if (N1.getNode()->getOpcode() == ISD::OR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getOperand(0);
+ SDValue Chain11 = N11.getNode()->getOperand(0);
if (Predicate_unindexedload(N11.getNode()) &&
Predicate_load(N11.getNode())) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue CPTmpN111_0;
SDValue CPTmpN111_1;
SDValue CPTmpN111_2;
SDValue CPTmpN111_3;
SDValue CPTmpN111_4;
if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N111 == N2) {
// Pattern: (st:isVoid (or:i8 GR8:i8:$src, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (OR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_220(N, X86::OR8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_216(N, X86::OR8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
@@ -41485,7 +40763,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_220(N, X86::OR16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_216(N, X86::OR16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
@@ -41493,7 +40771,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (OR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_220(N, X86::OR32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_216(N, X86::OR32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -41501,32 +40779,32 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::XOR &&
+ if (N1.getNode()->getOpcode() == ISD::XOR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getOperand(0);
+ SDValue Chain11 = N11.getNode()->getOperand(0);
if (Predicate_unindexedload(N11.getNode()) &&
Predicate_load(N11.getNode())) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue CPTmpN111_0;
SDValue CPTmpN111_1;
SDValue CPTmpN111_2;
SDValue CPTmpN111_3;
SDValue CPTmpN111_4;
if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N111 == N2) {
// Pattern: (st:isVoid (xor:i8 GR8:i8:$src, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (XOR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_220(N, X86::XOR8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_216(N, X86::XOR8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
@@ -41534,7 +40812,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_220(N, X86::XOR16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_216(N, X86::XOR16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
@@ -41542,7 +40820,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (XOR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_220(N, X86::XOR32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_216(N, X86::XOR32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -41550,32 +40828,32 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::ADD &&
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getOperand(0);
+ SDValue Chain11 = N11.getNode()->getOperand(0);
if (Predicate_unindexedload(N11.getNode()) &&
Predicate_load(N11.getNode())) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue CPTmpN111_0;
SDValue CPTmpN111_1;
SDValue CPTmpN111_2;
SDValue CPTmpN111_3;
SDValue CPTmpN111_4;
if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N111 == N2) {
// Pattern: (st:isVoid (add:i8 GR8:i8:$src2, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ADD8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_220(N, X86::ADD8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_216(N, X86::ADD8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
@@ -41583,7 +40861,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADD16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_220(N, X86::ADD16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_216(N, X86::ADD16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
@@ -41591,7 +40869,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADD32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_220(N, X86::ADD32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_216(N, X86::ADD32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -41599,32 +40877,32 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
}
- if (N1.getOpcode() == ISD::ADDE &&
+ if (N1.getNode()->getOpcode() == ISD::ADDE &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getOperand(0);
+ SDValue Chain11 = N11.getNode()->getOperand(0);
if (Predicate_unindexedload(N11.getNode()) &&
Predicate_load(N11.getNode())) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue CPTmpN111_0;
SDValue CPTmpN111_1;
SDValue CPTmpN111_2;
SDValue CPTmpN111_3;
SDValue CPTmpN111_4;
if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N111 == N2) {
// Pattern: (st:isVoid (adde:i8 GR8:i8:$src2, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ADC8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_221(N, X86::ADC8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_217(N, X86::ADC8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
@@ -41632,7 +40910,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADC16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_221(N, X86::ADC16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_217(N, X86::ADC16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
@@ -41640,7 +40918,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ADC32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
// Pattern complexity = 47 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_221(N, X86::ADC32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_217(N, X86::ADC32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -41652,28 +40930,28 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (add:i64 GR64:i64:$src2, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ADD64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == ISD::ADD &&
+ if (N1.getNode()->getOpcode() == ISD::ADD &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getOperand(0);
+ SDValue Chain11 = N11.getNode()->getOperand(0);
if (Predicate_unindexedload(N11.getNode()) &&
Predicate_load(N11.getNode())) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue CPTmpN111_0;
SDValue CPTmpN111_1;
SDValue CPTmpN111_2;
SDValue CPTmpN111_3;
SDValue CPTmpN111_4;
if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N111 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_220(N, X86::ADD64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_216(N, X86::ADD64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -41684,28 +40962,28 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (adde:i64 GR64:i64:$src2, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ADC64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == ISD::ADDE &&
+ if (N1.getNode()->getOpcode() == ISD::ADDE &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getOperand(0);
+ SDValue Chain11 = N11.getNode()->getOperand(0);
if (Predicate_unindexedload(N11.getNode()) &&
Predicate_load(N11.getNode())) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue CPTmpN111_0;
SDValue CPTmpN111_1;
SDValue CPTmpN111_2;
SDValue CPTmpN111_3;
SDValue CPTmpN111_4;
if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N111 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_221(N, X86::ADC64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_217(N, X86::ADC64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -41716,28 +40994,28 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (and:i64 GR64:i64:$src, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (AND64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == ISD::AND &&
+ if (N1.getNode()->getOpcode() == ISD::AND &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getOperand(0);
+ SDValue Chain11 = N11.getNode()->getOperand(0);
if (Predicate_unindexedload(N11.getNode()) &&
Predicate_load(N11.getNode())) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue CPTmpN111_0;
SDValue CPTmpN111_1;
SDValue CPTmpN111_2;
SDValue CPTmpN111_3;
SDValue CPTmpN111_4;
if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N111 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_220(N, X86::AND64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_216(N, X86::AND64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -41748,28 +41026,28 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (or:i64 GR64:i64:$src, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (OR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == ISD::OR &&
+ if (N1.getNode()->getOpcode() == ISD::OR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getOperand(0);
+ SDValue Chain11 = N11.getNode()->getOperand(0);
if (Predicate_unindexedload(N11.getNode()) &&
Predicate_load(N11.getNode())) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue CPTmpN111_0;
SDValue CPTmpN111_1;
SDValue CPTmpN111_2;
SDValue CPTmpN111_3;
SDValue CPTmpN111_4;
if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N111 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_220(N, X86::OR64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_216(N, X86::OR64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -41780,28 +41058,456 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (xor:i64 GR64:i64:$src, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (XOR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
// Pattern complexity = 47 cost = 1 size = 3
- if (N1.getOpcode() == ISD::XOR &&
+ if (N1.getNode()->getOpcode() == ISD::XOR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
N11.hasOneUse() &&
- IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
(Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
- SDValue Chain11 = N11.getOperand(0);
+ SDValue Chain11 = N11.getNode()->getOperand(0);
if (Predicate_unindexedload(N11.getNode()) &&
Predicate_load(N11.getNode())) {
- SDValue N111 = N11.getOperand(1);
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_216(N, X86::XOR64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ if (N1.getNode()->getOpcode() == X86ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N11.getNode())) {
+
+ // Pattern: (st:isVoid (X86add_flag:i8 GR8:i8:$src2, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_load(N11.getNode()) &&
+ Predicate_loadi8(N11.getNode())) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_216(N, X86::ADD8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86add_flag:i16 GR16:i16:$src2, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi16(N11.getNode())) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_216(N, X86::ADD16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86add_flag:i32 GR32:i32:$src2, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi32(N11.getNode())) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_216(N, X86::ADD32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getNode()->getOpcode() == X86ISD::OR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N11.getNode())) {
+
+ // Pattern: (st:isVoid (X86or_flag:i8 GR8:i8:$src2, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_load(N11.getNode()) &&
+ Predicate_loadi8(N11.getNode())) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_216(N, X86::OR8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86or_flag:i16 GR16:i16:$src2, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi16(N11.getNode())) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_216(N, X86::OR16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86or_flag:i32 GR32:i32:$src2, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi32(N11.getNode())) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_216(N, X86::OR32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getNode()->getOpcode() == X86ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N11.getNode())) {
+
+ // Pattern: (st:isVoid (X86xor_flag:i8 GR8:i8:$src2, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_load(N11.getNode()) &&
+ Predicate_loadi8(N11.getNode())) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_216(N, X86::XOR8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86xor_flag:i16 GR16:i16:$src2, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi16(N11.getNode())) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_216(N, X86::XOR16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86xor_flag:i32 GR32:i32:$src2, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi32(N11.getNode())) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_216(N, X86::XOR32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+ if (N1.getNode()->getOpcode() == X86ISD::AND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N11.getNode())) {
+
+ // Pattern: (st:isVoid (X86and_flag:i8 GR8:i8:$src2, (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND8mr:isVoid addr:iPTR:$dst, GR8:i8:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_load(N11.getNode()) &&
+ Predicate_loadi8(N11.getNode())) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i8) {
+ SDNode *Result = Emit_216(N, X86::AND8mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86and_flag:i16 GR16:i16:$src2, (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND16mr:isVoid addr:iPTR:$dst, GR16:i16:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi16(N11.getNode())) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i16) {
+ SDNode *Result = Emit_216(N, X86::AND16mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86and_flag:i32 GR32:i32:$src2, (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND32mr:isVoid addr:iPTR:$dst, GR32:i32:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (Predicate_loadi32(N11.getNode())) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_216(N, X86::AND32mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86add_flag:i64 GR64:i64:$src2, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (ADD64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == X86ISD::ADD &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N11.getNode()) &&
+ Predicate_load(N11.getNode()) &&
+ Predicate_loadi64(N11.getNode())) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_216(N, X86::ADD64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86or_flag:i64 GR64:i64:$src2, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (OR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == X86ISD::OR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N11.getNode()) &&
+ Predicate_load(N11.getNode()) &&
+ Predicate_loadi64(N11.getNode())) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_216(N, X86::OR64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86xor_flag:i64 GR64:i64:$src2, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (XOR64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == X86ISD::XOR &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N11.getNode()) &&
+ Predicate_load(N11.getNode()) &&
+ Predicate_loadi64(N11.getNode())) {
+ SDValue N111 = N11.getNode()->getOperand(1);
+ SDValue CPTmpN111_0;
+ SDValue CPTmpN111_1;
+ SDValue CPTmpN111_2;
+ SDValue CPTmpN111_3;
+ SDValue CPTmpN111_4;
+ if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
+ SDValue N2 = N->getOperand(2);
+ if (N111 == N2 &&
+ N1.getValueType() == MVT::i64) {
+ SDNode *Result = Emit_216(N, X86::XOR64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (st:isVoid (X86and_flag:i64 GR64:i64:$src2, (ld:i64 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
+ // Emits: (AND64mr:isVoid addr:iPTR:$dst, GR64:i64:$src2)
+ // Pattern complexity = 47 cost = 1 size = 3
+ if (N1.getNode()->getOpcode() == X86ISD::AND &&
+ N1.hasOneUse()) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::LOAD &&
+ N11.hasOneUse() &&
+ IsLegalAndProfitableToFold(N11.getNode(), N1.getNode(), N) &&
+ (Chain.getNode() == N11.getNode() || IsChainCompatible(Chain.getNode(), N11.getNode()))) {
+ SDValue Chain11 = N11.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N11.getNode()) &&
+ Predicate_load(N11.getNode()) &&
+ Predicate_loadi64(N11.getNode())) {
+ SDValue N111 = N11.getNode()->getOperand(1);
SDValue CPTmpN111_0;
SDValue CPTmpN111_1;
SDValue CPTmpN111_2;
SDValue CPTmpN111_3;
SDValue CPTmpN111_4;
if (SelectAddr(N, N111, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
if (N111 == N2 &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_220(N, X86::XOR64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
+ SDNode *Result = Emit_216(N, X86::AND64mr, CPTmpN111_0, CPTmpN111_1, CPTmpN111_2, CPTmpN111_3, CPTmpN111_4);
return Result;
}
}
@@ -41815,25 +41521,25 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVHPSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
// Pattern complexity = 40 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::VECTOR_SHUFFLE &&
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE &&
Predicate_unpckh(N10.getNode())) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N1000 = N100.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::UNDEF) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::UNDEF) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -41843,7 +41549,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::f64 &&
N10.getValueType() == MVT::v2f64 &&
N1000.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_198(N, X86::MOVHPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_195(N, X86::MOVHPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -41859,23 +41565,23 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVHPDmr:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
// Pattern complexity = 37 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::VECTOR_SHUFFLE &&
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE &&
Predicate_unpckh(N10.getNode())) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::UNDEF) {
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::UNDEF) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -41884,7 +41590,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::f64 &&
N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_200(N, X86::MOVHPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_197(N, X86::MOVHPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -41899,22 +41605,22 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV8mr_NOREX:isVoid addr:i64:$dst, (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i64 GR64:i64:$src, GR64_ABCD:i64), 2:i32))
// Pattern complexity = 35 cost = 3 size = 3
{
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TRUNCATE &&
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TRUNCATE &&
Predicate_trunc_su(N1.getNode())) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SRL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRL &&
Predicate_srl_su(N10.getNode())) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(8)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -41924,7 +41630,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i8 &&
N10.getValueType() == MVT::i64 &&
N101.getValueType() == MVT::i8) {
- SDNode *Result = Emit_213(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i64, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_210(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i64, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -41934,22 +41640,22 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
if ((Subtarget->is64Bit())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::TRUNCATE &&
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::TRUNCATE &&
Predicate_trunc_su(N1.getNode())) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SRL &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SRL &&
Predicate_srl_su(N10.getNode())) {
- SDValue N100 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N101.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(8)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -41963,7 +41669,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 35 cost = 3 size = 3
if (N10.getValueType() == MVT::i32 &&
N101.getValueType() == MVT::i8) {
- SDNode *Result = Emit_214(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i32, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_211(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i32, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -41972,7 +41678,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 35 cost = 3 size = 3
if (N10.getValueType() == MVT::i16 &&
N101.getValueType() == MVT::i8) {
- SDNode *Result = Emit_215(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i16, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_212(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV8mr_NOREX, MVT::i16, MVT::i8, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -41987,19 +41693,19 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (EXTRACTPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src1, (imm:i32):$src2)
// Pattern complexity = 34 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N1000 = N100.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- if (N101.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N1000 = N100.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ if (N101.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42010,7 +41716,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N10.getValueType() == MVT::i32 &&
N100.getValueType() == MVT::v4i32 &&
N1000.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_219(N, X86::EXTRACTPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_215(N, X86::EXTRACTPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42024,20 +41730,20 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVLPSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
// Pattern complexity = 33 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42047,7 +41753,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::f64 &&
N10.getValueType() == MVT::v2f64 &&
N100.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_197(N, X86::MOVLPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_194(N, X86::MOVLPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42061,17 +41767,17 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (EXTRACTPSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src1, (imm:i32):$src2)
// Pattern complexity = 31 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42081,7 +41787,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
N1.getValueType() == MVT::i32 &&
N10.getValueType() == MVT::v4i32 &&
N100.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_201(N, X86::EXTRACTPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_198(N, X86::EXTRACTPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42090,13 +41796,13 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
{
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == X86ISD::SETCC) {
- SDValue N10 = N1.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == X86ISD::SETCC) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N10.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -42104,15 +41810,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SETEm:isVoid addr:iPTR:$dst)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_191(N, X86::SETEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_188(N, X86::SETEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42121,15 +41827,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SETNEm:isVoid addr:iPTR:$dst)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_191(N, X86::SETNEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_188(N, X86::SETNEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42138,15 +41844,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SETLm:isVoid addr:iPTR:$dst)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_191(N, X86::SETLm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_188(N, X86::SETLm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42155,15 +41861,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SETGEm:isVoid addr:iPTR:$dst)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_191(N, X86::SETGEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_188(N, X86::SETGEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42172,15 +41878,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SETLEm:isVoid addr:iPTR:$dst)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_191(N, X86::SETLEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_188(N, X86::SETLEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42189,15 +41895,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SETGm:isVoid addr:iPTR:$dst)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_191(N, X86::SETGm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_188(N, X86::SETGm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42206,15 +41912,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SETBm:isVoid addr:iPTR:$dst)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_191(N, X86::SETBm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_188(N, X86::SETBm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42223,15 +41929,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SETAEm:isVoid addr:iPTR:$dst)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_191(N, X86::SETAEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_188(N, X86::SETAEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42240,15 +41946,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SETBEm:isVoid addr:iPTR:$dst)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_191(N, X86::SETBEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_188(N, X86::SETBEm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42257,15 +41963,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SETAm:isVoid addr:iPTR:$dst)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_191(N, X86::SETAm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_188(N, X86::SETAm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42274,15 +41980,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SETSm:isVoid addr:iPTR:$dst)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_191(N, X86::SETSm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_188(N, X86::SETSm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42291,15 +41997,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SETNSm:isVoid addr:iPTR:$dst)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_191(N, X86::SETNSm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_188(N, X86::SETNSm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42308,15 +42014,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SETPm:isVoid addr:iPTR:$dst)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_191(N, X86::SETPm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_188(N, X86::SETPm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42325,15 +42031,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SETNPm:isVoid addr:iPTR:$dst)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_191(N, X86::SETNPm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_188(N, X86::SETNPm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42342,15 +42048,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SETOm:isVoid addr:iPTR:$dst)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_191(N, X86::SETOm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_188(N, X86::SETOm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42359,15 +42065,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (SETNOm:isVoid addr:iPTR:$dst)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDNode *Result = Emit_191(N, X86::SETNOm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_188(N, X86::SETNOm, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42380,18 +42086,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVPS2SSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
// Pattern complexity = 30 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42400,7 +42106,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::f32 &&
N10.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_199(N, X86::MOVPS2SSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_196(N, X86::MOVPS2SSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42409,18 +42115,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N11.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42433,7 +42139,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 30 cost = 1 size = 3
if (N1.getValueType() == MVT::f64 &&
N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_199(N, X86::MOVLPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_196(N, X86::MOVLPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42442,7 +42148,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 30 cost = 1 size = 3
if (N1.getValueType() == MVT::i64 &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_199(N, X86::MOVPQI2QImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_196(N, X86::MOVPQI2QImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42451,7 +42157,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 30 cost = 1 size = 3
if (N1.getValueType() == MVT::f64 &&
N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_199(N, X86::MOVPD2SDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_196(N, X86::MOVPD2SDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42460,7 +42166,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 30 cost = 1 size = 3
if (N1.getValueType() == MVT::i32 &&
N10.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_199(N, X86::MOVPDI2DImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_196(N, X86::MOVPDI2DImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42470,15 +42176,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
if ((Subtarget->hasSSE41())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
- SDValue N10 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- if (N11.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ if (N11.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42491,7 +42197,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 28 cost = 1 size = 3
if (N1.getValueType() == MVT::i64 &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_196(N, X86::PEXTRQmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_193(N, X86::PEXTRQmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42500,7 +42206,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 28 cost = 1 size = 3
if (N1.getValueType() == MVT::i32 &&
N10.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_196(N, X86::PEXTRDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_193(N, X86::PEXTRDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42509,18 +42215,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
if ((TM.getCodeModel() == CodeModel::Small ||TM.getCodeModel() == CodeModel::Kernel) && (TM.getRelocationModel() == Reloc::Static)) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == X86ISD::Wrapper) {
- SDValue N10 = N1.getOperand(0);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == X86ISD::Wrapper) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (st:isVoid (X86Wrapper:i64 (tconstpool:i64):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (MOV64mi32:isVoid addr:iPTR:$dst, (tconstpool:i64):$src)
// Pattern complexity = 28 cost = 1 size = 3
- if (N10.getOpcode() == ISD::TargetConstantPool) {
- SDValue N2 = N.getOperand(2);
+ if (N10.getNode()->getOpcode() == ISD::TargetConstantPool) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42528,7 +42234,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_195(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42536,8 +42242,8 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86Wrapper:i64 (tjumptable:i64):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (MOV64mi32:isVoid addr:iPTR:$dst, (tjumptable:i64):$src)
// Pattern complexity = 28 cost = 1 size = 3
- if (N10.getOpcode() == ISD::TargetJumpTable) {
- SDValue N2 = N.getOperand(2);
+ if (N10.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42545,7 +42251,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_195(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42553,8 +42259,8 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86Wrapper:i64 (tglobaladdr:i64):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (MOV64mi32:isVoid addr:iPTR:$dst, (tglobaladdr:i64):$src)
// Pattern complexity = 28 cost = 1 size = 3
- if (N10.getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N2 = N.getOperand(2);
+ if (N10.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42562,7 +42268,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_195(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42570,8 +42276,8 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86Wrapper:i64 (texternalsym:i64):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (MOV64mi32:isVoid addr:iPTR:$dst, (texternalsym:i64):$src)
// Pattern complexity = 28 cost = 1 size = 3
- if (N10.getOpcode() == ISD::TargetExternalSymbol) {
- SDValue N2 = N.getOperand(2);
+ if (N10.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42579,7 +42285,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_195(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42587,8 +42293,8 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86Wrapper:i64 (tblockaddress:i64):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (MOV64mi32:isVoid addr:iPTR:$dst, (tblockaddress:i64):$src)
// Pattern complexity = 28 cost = 1 size = 3
- if (N10.getOpcode() == ISD::TargetBlockAddress) {
- SDValue N2 = N.getOperand(2);
+ if (N10.getNode()->getOpcode() == ISD::TargetBlockAddress) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42596,7 +42302,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_195(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42604,18 +42310,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
{
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == X86ISD::Wrapper) {
- SDValue N10 = N1.getOperand(0);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == X86ISD::Wrapper) {
+ SDValue N10 = N1.getNode()->getOperand(0);
// Pattern: (st:isVoid (X86Wrapper:i32 (tglobaladdr:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (MOV32mi:isVoid addr:iPTR:$dst, (tglobaladdr:i32):$src)
// Pattern complexity = 28 cost = 1 size = 3
- if (N10.getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N2 = N.getOperand(2);
+ if (N10.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42623,7 +42329,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_195(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_192(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42631,8 +42337,8 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86Wrapper:i32 (texternalsym:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (MOV32mi:isVoid addr:iPTR:$dst, (texternalsym:i32):$src)
// Pattern complexity = 28 cost = 1 size = 3
- if (N10.getOpcode() == ISD::TargetExternalSymbol) {
- SDValue N2 = N.getOperand(2);
+ if (N10.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42640,7 +42346,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_195(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_192(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42648,8 +42354,8 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid (X86Wrapper:i32 (tblockaddress:i32):$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (MOV32mi:isVoid addr:iPTR:$dst, (tblockaddress:i32):$src)
// Pattern complexity = 28 cost = 1 size = 3
- if (N10.getOpcode() == ISD::TargetBlockAddress) {
- SDValue N2 = N.getOperand(2);
+ if (N10.getNode()->getOpcode() == ISD::TargetBlockAddress) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42657,18 +42363,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_195(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_192(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
}
- if (N1.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (st:isVoid (imm:i64)<<P:Predicate_i64immSExt32>>:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (MOV64mi32:isVoid addr:iPTR:$dst, (imm:i64):$src)
// Pattern complexity = 26 cost = 1 size = 3
if (Predicate_i64immSExt32(N1.getNode())) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42676,11 +42382,11 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_192(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_189(N, X86::MOV64mi32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42692,7 +42398,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV8mi:isVoid addr:iPTR:$dst, (imm:i8):$src)
// Pattern complexity = 25 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_172(N, X86::MOV8mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_169(N, X86::MOV8mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42700,7 +42406,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
// Pattern complexity = 25 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_173(N, X86::MOV16mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_170(N, X86::MOV16mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42708,7 +42414,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV32mi:isVoid addr:iPTR:$dst, (imm:i32):$src)
// Pattern complexity = 25 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_174(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_171(N, X86::MOV32mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42716,13 +42422,13 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getOperand(0);
- SDValue N2 = N.getOperand(2);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42735,7 +42441,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 3
if (N1.getValueType() == MVT::i64 &&
N10.getValueType() == MVT::f64) {
- SDNode *Result = Emit_195(N, X86::MOVSDto64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_192(N, X86::MOVSDto64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42744,7 +42450,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 3
if (N1.getValueType() == MVT::i32 &&
N10.getValueType() == MVT::f32) {
- SDNode *Result = Emit_195(N, X86::MOVSS2DImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_192(N, X86::MOVSS2DImr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42752,13 +42458,13 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
{
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_truncstore(N.getNode()) &&
- Predicate_truncstorei16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
- SDValue N2 = N.getOperand(2);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_truncstore(N) &&
+ Predicate_truncstorei16(N)) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42770,7 +42476,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
// Pattern complexity = 25 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_173(N, X86::MOV16mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_170(N, X86::MOV16mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42778,7 +42484,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV16mi:isVoid addr:iPTR:$dst, (imm:i16):$src)
// Pattern complexity = 25 cost = 1 size = 3
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_173(N, X86::MOV16mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_170(N, X86::MOV16mi, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42790,11 +42496,11 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ST_Fp32m:isVoid addr:iPTR:$op, RFP32:f32:$src)
// Pattern complexity = 22 cost = 1 size = 0
if ((!Subtarget->hasSSE1())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42802,22 +42508,22 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_175(N, X86::ST_Fp32m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::ST_Fp32m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
}
if ((!Subtarget->hasSSE2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N)) {
// Pattern: (st:isVoid RFP64:f64:$src, addr:iPTR:$op)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstoref32>>
// Emits: (ST_Fp64m32:isVoid addr:iPTR:$op, RFP64:f64:$src)
// Pattern complexity = 22 cost = 1 size = 0
- if (Predicate_truncstore(N.getNode()) &&
- Predicate_truncstoref32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstore(N) &&
+ Predicate_truncstoref32(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42825,7 +42531,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_175(N, X86::ST_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::ST_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42833,9 +42539,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid RFP64:f64:$src, addr:iPTR:$op)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (ST_Fp64m:isVoid addr:iPTR:$op, RFP64:f64:$src)
// Pattern complexity = 22 cost = 1 size = 0
- if (Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42843,23 +42549,23 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_175(N, X86::ST_Fp64m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::ST_Fp64m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
}
}
{
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode())) {
- if (Predicate_truncstore(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N)) {
+ if (Predicate_truncstore(N)) {
// Pattern: (st:isVoid RFP80:f80:$src, addr:iPTR:$op)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstoref32>>
// Emits: (ST_Fp80m32:isVoid addr:iPTR:$op, RFP80:f80:$src)
// Pattern complexity = 22 cost = 1 size = 0
- if (Predicate_truncstoref32(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstoref32(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42867,7 +42573,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_175(N, X86::ST_Fp80m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::ST_Fp80m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42875,9 +42581,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid RFP80:f80:$src, addr:iPTR:$op)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstoref64>>
// Emits: (ST_Fp80m64:isVoid addr:iPTR:$op, RFP80:f80:$src)
// Pattern complexity = 22 cost = 1 size = 0
- if (Predicate_truncstoref64(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstoref64(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42885,14 +42591,14 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_175(N, X86::ST_Fp80m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::ST_Fp80m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
}
- if (Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42904,7 +42610,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (ST_FpP80m:isVoid addr:iPTR:$op, RFP80:f80:$src)
// Pattern complexity = 22 cost = 1 size = 0
if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_175(N, X86::ST_FpP80m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::ST_FpP80m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42912,7 +42618,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV8mr:isVoid addr:iPTR:$dst, GR8:i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_175(N, X86::MOV8mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MOV8mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42920,7 +42626,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV16mr:isVoid addr:iPTR:$dst, GR16:i16:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::i16) {
- SDNode *Result = Emit_175(N, X86::MOV16mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MOV16mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42928,7 +42634,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV32mr:isVoid addr:iPTR:$dst, GR32:i32:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_175(N, X86::MOV32mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MOV32mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -42936,7 +42642,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV64mr:isVoid addr:iPTR:$dst, GR64:i64:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_175(N, X86::MOV64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MOV64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42944,16 +42650,16 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
}
}
if ((Subtarget->hasSSE1())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
// Pattern: (st:isVoid FR32:f32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (MOVSSmr:isVoid addr:iPTR:$dst, FR32:f32:$src)
// Pattern complexity = 22 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42961,7 +42667,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_175(N, X86::MOVSSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MOVSSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42969,9 +42675,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid VR128:v4f32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_alignedstore>>
// Emits: (MOVAPSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_alignedstore(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_alignedstore(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42979,7 +42685,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_175(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -42987,8 +42693,8 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid VR128:v4f32:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (MOVUPSmr:isVoid addr:iPTR:$dst, VR128:v4f32:$src)
// Pattern complexity = 22 cost = 1 size = 3
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -42996,22 +42702,22 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_175(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
}
if ((Subtarget->hasSSE2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
// Pattern: (st:isVoid FR64:f64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (MOVSDmr:isVoid addr:iPTR:$dst, FR64:f64:$src)
// Pattern complexity = 22 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -43019,7 +42725,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_175(N, X86::MOVSDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MOVSDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -43027,9 +42733,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid VR128:v2f64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_alignedstore>>
// Emits: (MOVAPDmr:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_alignedstore(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_alignedstore(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -43037,7 +42743,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_175(N, X86::MOVAPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MOVAPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -43045,8 +42751,8 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Pattern: (st:isVoid VR128:v2f64:$src, addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
// Emits: (MOVUPDmr:isVoid addr:iPTR:$dst, VR128:v2f64:$src)
// Pattern complexity = 22 cost = 1 size = 3
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -43054,7 +42760,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_175(N, X86::MOVUPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MOVUPDmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -43064,11 +42770,11 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v1i64:$src)
// Pattern complexity = 22 cost = 1 size = 3
if ((Subtarget->hasMMX())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -43076,18 +42782,18 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4) &&
N1.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_175(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
}
if ((Subtarget->hasSSE2())) {
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode()) &&
- Predicate_store(N.getNode())) {
- if (Predicate_alignedstore(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N) &&
+ Predicate_store(N)) {
+ if (Predicate_alignedstore(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -43099,7 +42805,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVAPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_175(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43107,7 +42813,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVAPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_175(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43115,7 +42821,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVAPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_175(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43123,13 +42829,13 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVAPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_175(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MOVAPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
}
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -43141,7 +42847,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVUPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_175(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43149,7 +42855,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVUPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_175(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43157,7 +42863,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVUPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_175(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43165,17 +42871,17 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOVUPSmr:isVoid addr:iPTR:$dst, VR128:v16i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_175(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MOVUPSmr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
}
}
- SDValue Chain = N.getOperand(0);
- if (Predicate_unindexedstore(N.getNode())) {
- if (Predicate_store(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue Chain = N->getOperand(0);
+ if (Predicate_unindexedstore(N)) {
+ if (Predicate_store(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -43187,7 +42893,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v8i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_175(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43195,7 +42901,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v8i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v4i16) {
- SDNode *Result = Emit_175(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43203,7 +42909,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v8i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v2i32) {
- SDNode *Result = Emit_175(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43211,7 +42917,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v8i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v2f32) {
- SDNode *Result = Emit_175(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43219,15 +42925,15 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MMX_MOVQ64mr:isVoid addr:iPTR:$dst, VR64:v8i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (N1.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_175(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_172(N, X86::MMX_MOVQ64mr, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
}
- if (Predicate_truncstore(N.getNode()) &&
- Predicate_truncstorei16(N.getNode())) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ if (Predicate_truncstore(N) &&
+ Predicate_truncstorei16(N)) {
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -43239,7 +42945,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV16mr:isVoid addr:iPTR:$dst, (EXTRACT_SUBREG:i16 GR32:i32:$src, 3:i32))
// Pattern complexity = 22 cost = 2 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_210(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV16mr, MVT::i16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_207(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV16mr, MVT::i16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -43247,7 +42953,7 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
// Emits: (MOV16mr:isVoid addr:iPTR:$dst, (EXTRACT_SUBREG:i16 GR64:i64:$src, 3:i32))
// Pattern complexity = 22 cost = 2 size = 3
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_210(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV16mr, MVT::i16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_207(N, TargetInstrInfo::EXTRACT_SUBREG, X86::MOV16mr, MVT::i16, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -43258,26 +42964,26 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_227(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N1);
+DISABLE_INLINE SDNode *Emit_222(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N1);
}
-SDNode *Select_ISD_SUB_i8(const SDValue &N) {
+SDNode *Select_ISD_SUB_i8(SDNode *N) {
// Pattern: (sub:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (SUB8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -43291,17 +42997,17 @@ SDNode *Select_ISD_SUB_i8(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (sub:i8 0:i8, GR8:i8:$src)
// Emits: (NEG8r:i8 GR8:i8:$src)
// Pattern complexity = 8 cost = 1 size = 2
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_227(N, X86::NEG8r, MVT::i8);
+ SDNode *Result = Emit_222(N, X86::NEG8r, MVT::i8);
return Result;
}
}
@@ -43310,8 +43016,8 @@ SDNode *Select_ISD_SUB_i8(const SDValue &N) {
// Pattern: (sub:i8 GR8:i8:$src1, (imm:i8):$src2)
// Emits: (SUB8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_3(N, X86::SUB8ri, MVT::i8);
return Result;
}
@@ -43324,21 +43030,21 @@ SDNode *Select_ISD_SUB_i8(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_SUB_i16(const SDValue &N) {
+SDNode *Select_ISD_SUB_i16(SDNode *N) {
// Pattern: (sub:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (SUB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -43352,23 +43058,23 @@ SDNode *Select_ISD_SUB_i16(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (sub:i16 0:i16, GR16:i16:$src)
// Emits: (NEG16r:i16 GR16:i16:$src)
// Pattern complexity = 8 cost = 1 size = 2
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_227(N, X86::NEG16r, MVT::i16);
+ SDNode *Result = Emit_222(N, X86::NEG16r, MVT::i16);
return Result;
}
}
}
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (sub:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Emits: (SUB16ri8:i16 GR16:i16:$src1, (imm:i16):$src2)
@@ -43393,21 +43099,21 @@ SDNode *Select_ISD_SUB_i16(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_SUB_i32(const SDValue &N) {
+SDNode *Select_ISD_SUB_i32(SDNode *N) {
// Pattern: (sub:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (SUB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -43429,7 +43135,7 @@ SDNode *Select_ISD_SUB_i32(const SDValue &N) {
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
@@ -43443,29 +43149,29 @@ SDNode *Select_ISD_SUB_i32(const SDValue &N) {
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
}
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (sub:i32 0:i32, GR32:i32:$src)
// Emits: (NEG32r:i32 GR32:i32:$src)
// Pattern complexity = 8 cost = 1 size = 2
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_227(N, X86::NEG32r, MVT::i32);
+ SDNode *Result = Emit_222(N, X86::NEG32r, MVT::i32);
return Result;
}
}
}
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (sub:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Emits: (SUB32ri8:i32 GR32:i32:$src1, (imm:i32):$src2)
@@ -43490,21 +43196,21 @@ SDNode *Select_ISD_SUB_i32(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_SUB_i64(const SDValue &N) {
+SDNode *Select_ISD_SUB_i64(SDNode *N) {
// Pattern: (sub:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (SUB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -43526,29 +43232,29 @@ SDNode *Select_ISD_SUB_i64(const SDValue &N) {
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
}
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (sub:i64 0:i64, GR64:i64:$src)
// Emits: (NEG64r:i64 GR64:i64:$src)
// Pattern complexity = 8 cost = 1 size = 2
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_227(N, X86::NEG64r, MVT::i64);
+ SDNode *Result = Emit_222(N, X86::NEG64r, MVT::i64);
return Result;
}
}
}
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (sub:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Emits: (SUB64ri8:i64 GR64:i64:$src1, (imm:i64):$src2)
@@ -43575,25 +43281,25 @@ SDNode *Select_ISD_SUB_i64(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_SUB_v8i8(const SDValue &N) {
+SDNode *Select_ISD_SUB_v8i8(SDNode *N) {
// Pattern: (sub:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PSUBBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -43621,26 +43327,26 @@ SDNode *Select_ISD_SUB_v8i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SUB_v16i8(const SDValue &N) {
+SDNode *Select_ISD_SUB_v16i8(SDNode *N) {
// Pattern: (sub:v16i8 VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PSUBBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -43668,25 +43374,25 @@ SDNode *Select_ISD_SUB_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SUB_v4i16(const SDValue &N) {
+SDNode *Select_ISD_SUB_v4i16(SDNode *N) {
// Pattern: (sub:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PSUBWrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -43714,26 +43420,26 @@ SDNode *Select_ISD_SUB_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SUB_v8i16(const SDValue &N) {
+SDNode *Select_ISD_SUB_v8i16(SDNode *N) {
// Pattern: (sub:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PSUBWrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -43761,25 +43467,25 @@ SDNode *Select_ISD_SUB_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SUB_v2i32(const SDValue &N) {
+SDNode *Select_ISD_SUB_v2i32(SDNode *N) {
// Pattern: (sub:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PSUBDrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -43807,26 +43513,26 @@ SDNode *Select_ISD_SUB_v2i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SUB_v4i32(const SDValue &N) {
+SDNode *Select_ISD_SUB_v4i32(SDNode *N) {
// Pattern: (sub:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PSUBDrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -43854,25 +43560,25 @@ SDNode *Select_ISD_SUB_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SUB_v1i64(const SDValue &N) {
+SDNode *Select_ISD_SUB_v1i64(SDNode *N) {
// Pattern: (sub:v1i64 VR64:v1i64:$src1, (bitconvert:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PSUBQrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -43900,23 +43606,23 @@ SDNode *Select_ISD_SUB_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SUB_v2i64(const SDValue &N) {
+SDNode *Select_ISD_SUB_v2i64(SDNode *N) {
// Pattern: (sub:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PSUBQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -43942,21 +43648,21 @@ SDNode *Select_ISD_SUB_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_SUBC_i32(const SDValue &N) {
+SDNode *Select_ISD_SUBC_i32(SDNode *N) {
// Pattern: (subc:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (SUB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -43970,9 +43676,9 @@ SDNode *Select_ISD_SUBC_i32(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (subc:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Emits: (SUB32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
@@ -43997,21 +43703,21 @@ SDNode *Select_ISD_SUBC_i32(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_SUBC_i64(const SDValue &N) {
+SDNode *Select_ISD_SUBC_i64(SDNode *N) {
// Pattern: (subc:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (SUB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -44025,9 +43731,9 @@ SDNode *Select_ISD_SUBC_i64(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (subc:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Emits: (SUB64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
@@ -44052,21 +43758,21 @@ SDNode *Select_ISD_SUBC_i64(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_SUBE_i8(const SDValue &N) {
+SDNode *Select_ISD_SUBE_i8(SDNode *N) {
// Pattern: (sube:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (SBB8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -44084,9 +43790,9 @@ SDNode *Select_ISD_SUBE_i8(const SDValue &N) {
// Emits: (SBB8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_27(N, X86::SBB8ri, MVT::i8);
return Result;
}
@@ -44099,21 +43805,21 @@ SDNode *Select_ISD_SUBE_i8(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_SUBE_i16(const SDValue &N) {
+SDNode *Select_ISD_SUBE_i16(SDNode *N) {
// Pattern: (sube:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (SBB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -44127,9 +43833,9 @@ SDNode *Select_ISD_SUBE_i16(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (sube:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Emits: (SBB16ri8:i16 GR16:i16:$src1, (imm:i16):$src2)
@@ -44154,21 +43860,21 @@ SDNode *Select_ISD_SUBE_i16(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
+SDNode *Select_ISD_SUBE_i32(SDNode *N) {
// Pattern: (sube:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (SBB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -44182,9 +43888,9 @@ SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (sube:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Emits: (SBB32ri8:i32 GR32:i32:$src1, (imm:i32):$src2)
@@ -44209,21 +43915,21 @@ SDNode *Select_ISD_SUBE_i32(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_SUBE_i64(const SDValue &N) {
+SDNode *Select_ISD_SUBE_i64(SDNode *N) {
// Pattern: (sube:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (SBB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -44237,9 +43943,9 @@ SDNode *Select_ISD_SUBE_i64(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (sube:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Emits: (SBB64ri8:i64 GR64:i64:$src1, (imm:i64):$src2)
@@ -44266,60 +43972,60 @@ SDNode *Select_ISD_SUBE_i64(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_228(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Chain);
+DISABLE_INLINE SDNode *Emit_223(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Chain);
}
-SDNode *Select_ISD_TRAP(const SDValue &N) {
- SDNode *Result = Emit_228(N, X86::TRAP);
+SDNode *Select_ISD_TRAP(SDNode *N) {
+ SDNode *Result = Emit_223(N, X86::TRAP);
return Result;
}
-DISABLE_INLINE SDNode *Emit_229(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
+DISABLE_INLINE SDNode *Emit_224(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
SDValue Tmp1 = CurDAG->getTargetConstant(X86::GR32_ABCDRegClassID, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
SDValue Tmp3 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2, Tmp3);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_230(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
+DISABLE_INLINE SDNode *Emit_225(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
SDValue Tmp1 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
- SDValue Tmp2(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N0, Tmp1), 0);
+ SDValue Tmp2(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N0, Tmp1), 0);
SDValue Tmp3 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp2, Tmp3);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp2, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_231(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+DISABLE_INLINE SDNode *Emit_226(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(X86::GR16_ABCDRegClassID, MVT::i32);
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N00, Tmp3), 0);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N00, Tmp3), 0);
SDValue Tmp5 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp4, Tmp5);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp4, Tmp5);
}
-DISABLE_INLINE SDNode *Emit_232(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+DISABLE_INLINE SDNode *Emit_227(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(X86::GR32_ABCDRegClassID, MVT::i32);
- SDValue Tmp4(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0, N00, Tmp3), 0);
+ SDValue Tmp4(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0, N00, Tmp3), 0);
SDValue Tmp5 = CurDAG->getTargetConstant(0x2ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp4, Tmp5);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp4, Tmp5);
}
-DISABLE_INLINE SDNode *Emit_233(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
+DISABLE_INLINE SDNode *Emit_228(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
SDValue Tmp1 = CurDAG->getTargetConstant(0x1ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1);
}
-SDNode *Select_ISD_TRUNCATE_i8(const SDValue &N) {
+SDNode *Select_ISD_TRUNCATE_i8(SDNode *N) {
if ((!Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SRL &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRL &&
Predicate_srl_su(N0.getNode())) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(8)) {
@@ -44329,7 +44035,7 @@ SDNode *Select_ISD_TRUNCATE_i8(const SDValue &N) {
// Pattern complexity = 12 cost = 2 size = 0
if (N0.getValueType() == MVT::i16 &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_231(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i32, MVT::i8);
+ SDNode *Result = Emit_226(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i32, MVT::i8);
return Result;
}
@@ -44338,7 +44044,7 @@ SDNode *Select_ISD_TRUNCATE_i8(const SDValue &N) {
// Pattern complexity = 12 cost = 2 size = 0
if (N0.getValueType() == MVT::i32 &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_232(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8);
+ SDNode *Result = Emit_227(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8);
return Result;
}
}
@@ -44350,20 +44056,20 @@ SDNode *Select_ISD_TRUNCATE_i8(const SDValue &N) {
// Emits: (EXTRACT_SUBREG:i8 GR64:i64:$src, 1:i32)
// Pattern complexity = 3 cost = 1 size = 0
{
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_233(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i8);
+ SDNode *Result = Emit_228(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i8);
return Result;
}
}
if ((Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (trunc:i8 GR32:i32:$src)
// Emits: (EXTRACT_SUBREG:i8 GR32:i32:$src, 1:i32)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_233(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i8);
+ SDNode *Result = Emit_228(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i8);
return Result;
}
@@ -44371,18 +44077,18 @@ SDNode *Select_ISD_TRUNCATE_i8(const SDValue &N) {
// Emits: (EXTRACT_SUBREG:i8 GR16:i16:$src, 1:i32)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_233(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i8);
+ SDNode *Result = Emit_228(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i8);
return Result;
}
}
if ((!Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (trunc:i8 GR32:i32:$src)
// Emits: (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i32 GR32:i32:$src, GR32_ABCD:i32), 1:i32)
// Pattern complexity = 3 cost = 2 size = 0
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_229(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i32, MVT::i8);
+ SDNode *Result = Emit_224(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i32, MVT::i8);
return Result;
}
@@ -44390,7 +44096,7 @@ SDNode *Select_ISD_TRUNCATE_i8(const SDValue &N) {
// Emits: (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 1:i32)
// Pattern complexity = 3 cost = 2 size = 0
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_230(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8);
+ SDNode *Result = Emit_225(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16, MVT::i8);
return Result;
}
}
@@ -44399,19 +44105,19 @@ SDNode *Select_ISD_TRUNCATE_i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_234(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
+DISABLE_INLINE SDNode *Emit_229(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
SDValue Tmp1 = CurDAG->getTargetConstant(0x3ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1);
}
-SDNode *Select_ISD_TRUNCATE_i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_TRUNCATE_i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (trunc:i16 GR32:i32:$src)
// Emits: (EXTRACT_SUBREG:i16 GR32:i32:$src, 3:i32)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_234(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16);
+ SDNode *Result = Emit_229(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16);
return Result;
}
@@ -44419,7 +44125,7 @@ SDNode *Select_ISD_TRUNCATE_i16(const SDValue &N) {
// Emits: (EXTRACT_SUBREG:i16 GR64:i64:$src, 3:i32)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_234(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16);
+ SDNode *Result = Emit_229(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i16);
return Result;
}
@@ -44427,15 +44133,15 @@ SDNode *Select_ISD_TRUNCATE_i16(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_235(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
+DISABLE_INLINE SDNode *Emit_230(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
SDValue Tmp1 = CurDAG->getTargetConstant(0x4ULL, MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1);
}
-SDNode *Select_ISD_TRUNCATE_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_TRUNCATE_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_235(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i32);
+ SDNode *Result = Emit_230(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::i32);
return Result;
}
@@ -44443,26 +44149,26 @@ SDNode *Select_ISD_TRUNCATE_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_VECTOR_SHUFFLE_v8i8(const SDValue &N) {
+SDNode *Select_ISD_VECTOR_SHUFFLE_v8i8(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasMMX())) {
// Pattern: (vector_shuffle:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckh>>
// Emits: (MMX_PUNPCKHBWrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_mmx_unpckh(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_mmx_unpckh(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -44481,19 +44187,19 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i8(const SDValue &N) {
// Pattern: (vector_shuffle:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckl>>
// Emits: (MMX_PUNPCKLBWrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_mmx_unpckl(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_mmx_unpckl(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -44513,11 +44219,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i8(const SDValue &N) {
// Pattern: (vector_shuffle:v8i8 VR64:v8i8:$src, (undef:v8i8))<<P:Predicate_mmx_unpckl_undef>>
// Emits: (MMX_PUNPCKLBWrr:v8i8 VR64:v8i8:$src, VR64:v8i8:$src)
// Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_mmx_unpckl_undef(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::MMX_PUNPCKLBWrr, MVT::v8i8);
+ if (Predicate_mmx_unpckl_undef(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::MMX_PUNPCKLBWrr, MVT::v8i8);
return Result;
}
}
@@ -44525,11 +44231,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i8(const SDValue &N) {
// Pattern: (vector_shuffle:v8i8 VR64:v8i8:$src, (undef:v8i8))<<P:Predicate_mmx_unpckh_undef>>
// Emits: (MMX_PUNPCKHBWrr:v8i8 VR64:v8i8:$src, VR64:v8i8:$src)
// Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_mmx_unpckh_undef(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::MMX_PUNPCKHBWrr, MVT::v8i8);
+ if (Predicate_mmx_unpckh_undef(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::MMX_PUNPCKHBWrr, MVT::v8i8);
return Result;
}
}
@@ -44538,7 +44244,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i8(const SDValue &N) {
// Pattern: (vector_shuffle:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)<<P:Predicate_mmx_unpckh>>
// Emits: (MMX_PUNPCKHBWrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_mmx_unpckh(N.getNode())) {
+ if (Predicate_mmx_unpckh(N)) {
SDNode *Result = Emit_15(N, X86::MMX_PUNPCKHBWrr, MVT::v8i8);
return Result;
}
@@ -44546,7 +44252,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i8(const SDValue &N) {
// Pattern: (vector_shuffle:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)<<P:Predicate_mmx_unpckl>>
// Emits: (MMX_PUNPCKLBWrr:v8i8 VR64:v8i8:$src1, VR64:v8i8:$src2)
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_mmx_unpckl(N.getNode())) {
+ if (Predicate_mmx_unpckl(N)) {
SDNode *Result = Emit_15(N, X86::MMX_PUNPCKLBWrr, MVT::v8i8);
return Result;
}
@@ -44556,33 +44262,33 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_236(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp3 = Transform_SHUFFLE_get_palign_imm(N.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N0, Tmp3);
+DISABLE_INLINE SDNode *Emit_231(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp3 = Transform_SHUFFLE_get_palign_imm(SDValue(N, 0).getNode());
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N0, Tmp3);
}
-SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
+SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
// Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckl>>
// Emits: (PUNPCKLBWrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_unpckl(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_unpckl(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -44601,20 +44307,20 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src1, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckh>>
// Emits: (PUNPCKHBWrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_unpckh(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_unpckh(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -44635,11 +44341,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src, (undef:v16i8))<<P:Predicate_unpckl_undef>>
// Emits: (PUNPCKLBWrr:v16i8 VR128:v16i8:$src, VR128:v16i8:$src)
// Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_unpckl_undef(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::PUNPCKLBWrr, MVT::v16i8);
+ if (Predicate_unpckl_undef(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::PUNPCKLBWrr, MVT::v16i8);
return Result;
}
}
@@ -44647,11 +44353,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src, (undef:v16i8))<<P:Predicate_unpckh_undef>>
// Emits: (PUNPCKHBWrr:v16i8 VR128:v16i8:$src, VR128:v16i8:$src)
// Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_unpckh_undef(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::PUNPCKHBWrr, MVT::v16i8);
+ if (Predicate_unpckh_undef(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::PUNPCKHBWrr, MVT::v16i8);
return Result;
}
}
@@ -44661,8 +44367,8 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Emits: (PALIGNR128rr:v16i8 VR128:v16i8:$src2, VR128:v16i8:$src1, (SHUFFLE_get_palign_imm:i8 VR128:i8:$src3))
// Pattern complexity = 9 cost = 1 size = 3
if ((Subtarget->hasSSSE3()) &&
- Predicate_palign(N.getNode())) {
- SDNode *Result = Emit_236(N, X86::PALIGNR128rr, MVT::v16i8);
+ Predicate_palign(N)) {
+ SDNode *Result = Emit_231(N, X86::PALIGNR128rr, MVT::v16i8);
return Result;
}
if ((Subtarget->hasSSE2())) {
@@ -44670,7 +44376,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)<<P:Predicate_unpckl>>
// Emits: (PUNPCKLBWrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_unpckl(N.getNode())) {
+ if (Predicate_unpckl(N)) {
SDNode *Result = Emit_15(N, X86::PUNPCKLBWrr, MVT::v16i8);
return Result;
}
@@ -44678,7 +44384,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
// Pattern: (vector_shuffle:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)<<P:Predicate_unpckh>>
// Emits: (PUNPCKHBWrr:v16i8 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_unpckh(N.getNode())) {
+ if (Predicate_unpckh(N)) {
SDNode *Result = Emit_15(N, X86::PUNPCKHBWrr, MVT::v16i8);
return Result;
}
@@ -44688,56 +44394,56 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v16i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_237(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp2 = Transform_MMX_SHUFFLE_get_shuf_imm(N.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
+DISABLE_INLINE SDNode *Emit_232(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp2 = Transform_MMX_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_238(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue Chain00 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp2 = Transform_MMX_SHUFFLE_get_shuf_imm(N.getNode());
+DISABLE_INLINE SDNode *Emit_233(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp2 = Transform_MMX_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp2, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_ISD_VECTOR_SHUFFLE_v4i16(const SDValue &N) {
+SDNode *Select_ISD_VECTOR_SHUFFLE_v4i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasMMX())) {
// Pattern: (vector_shuffle:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>), (undef:v4i16))<<P:Predicate_mmx_pshufw>><<X:MMX_SHUFFLE_get_shuf_imm>>:$src2
// Emits: (MMX_PSHUFWmi:v4i16 addr:iPTR:$src1, (MMX_SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>>), (undef:v4i16)):$src2))
// Pattern complexity = 32 cost = 1 size = 3
- if (Predicate_mmx_pshufw(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_mmx_pshufw(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_238(N, X86::MMX_PSHUFWmi, MVT::v4i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_233(N, X86::MMX_PSHUFWmi, MVT::v4i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -44749,19 +44455,19 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i16(const SDValue &N) {
// Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckh>>
// Emits: (MMX_PUNPCKHWDrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_mmx_unpckh(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_mmx_unpckh(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -44780,19 +44486,19 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i16(const SDValue &N) {
// Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckl>>
// Emits: (MMX_PUNPCKLWDrm:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_mmx_unpckl(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_mmx_unpckl(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -44812,11 +44518,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i16(const SDValue &N) {
// Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src, (undef:v4i16))<<P:Predicate_mmx_unpckl_undef>>
// Emits: (MMX_PUNPCKLWDrr:v4i16 VR64:v8i8:$src, VR64:v8i8:$src)
// Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_mmx_unpckl_undef(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::MMX_PUNPCKLWDrr, MVT::v4i16);
+ if (Predicate_mmx_unpckl_undef(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::MMX_PUNPCKLWDrr, MVT::v4i16);
return Result;
}
}
@@ -44824,11 +44530,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i16(const SDValue &N) {
// Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src, (undef:v4i16))<<P:Predicate_mmx_unpckh_undef>>
// Emits: (MMX_PUNPCKHWDrr:v4i16 VR64:v8i8:$src, VR64:v8i8:$src)
// Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_mmx_unpckh_undef(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::MMX_PUNPCKHWDrr, MVT::v4i16);
+ if (Predicate_mmx_unpckh_undef(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::MMX_PUNPCKHWDrr, MVT::v4i16);
return Result;
}
}
@@ -44837,11 +44543,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i16(const SDValue &N) {
// Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src1, (undef:v4i16))<<P:Predicate_mmx_pshufw>><<X:MMX_SHUFFLE_get_shuf_imm>>:$src2
// Emits: (MMX_PSHUFWri:v4i16 VR64:v4i16:$src1, (MMX_SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4i16 VR64:v4i16:$src1, (undef:v4i16)):$src2))
// Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_mmx_pshufw(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_237(N, X86::MMX_PSHUFWri, MVT::v4i16);
+ if (Predicate_mmx_pshufw(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_232(N, X86::MMX_PSHUFWri, MVT::v4i16);
return Result;
}
}
@@ -44849,7 +44555,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i16(const SDValue &N) {
// Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)<<P:Predicate_mmx_unpckh>>
// Emits: (MMX_PUNPCKHWDrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_mmx_unpckh(N.getNode())) {
+ if (Predicate_mmx_unpckh(N)) {
SDNode *Result = Emit_15(N, X86::MMX_PUNPCKHWDrr, MVT::v4i16);
return Result;
}
@@ -44857,7 +44563,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i16(const SDValue &N) {
// Pattern: (vector_shuffle:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)<<P:Predicate_mmx_unpckl>>
// Emits: (MMX_PUNPCKLWDrr:v4i16 VR64:v4i16:$src1, VR64:v4i16:$src2)
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_mmx_unpckl(N.getNode())) {
+ if (Predicate_mmx_unpckl(N)) {
SDNode *Result = Emit_15(N, X86::MMX_PUNPCKLWDrr, MVT::v4i16);
return Result;
}
@@ -44867,78 +44573,78 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i16(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_239(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp2 = Transform_SHUFFLE_get_pshufhw_imm(N.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
+DISABLE_INLINE SDNode *Emit_234(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp2 = Transform_SHUFFLE_get_pshufhw_imm(SDValue(N, 0).getNode());
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_240(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue Chain00 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp2 = Transform_SHUFFLE_get_pshufhw_imm(N.getNode());
+DISABLE_INLINE SDNode *Emit_235(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp2 = Transform_SHUFFLE_get_pshufhw_imm(SDValue(N, 0).getNode());
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp2, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_241(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp2 = Transform_SHUFFLE_get_pshuflw_imm(N.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_242(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue Chain00 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp2 = Transform_SHUFFLE_get_pshuflw_imm(N.getNode());
+DISABLE_INLINE SDNode *Emit_236(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp2 = Transform_SHUFFLE_get_pshuflw_imm(SDValue(N, 0).getNode());
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_237(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp2 = Transform_SHUFFLE_get_pshuflw_imm(SDValue(N, 0).getNode());
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp2, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(const SDValue &N) {
+SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
// Pattern: (vector_shuffle:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v8i16))<<P:Predicate_pshufhw>><<X:SHUFFLE_get_pshufhw_imm>>:$src2
// Emits: (PSHUFHWmi:v8i16 addr:iPTR:$src1, (SHUFFLE_get_pshufhw_imm:i8 (vector_shuffle:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v8i16)):$src2))
// Pattern complexity = 32 cost = 1 size = 3
- if (Predicate_pshufhw(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_pshufhw(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode()) &&
Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_240(N, X86::PSHUFHWmi, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_235(N, X86::PSHUFHWmi, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -44950,29 +44656,29 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(const SDValue &N) {
// Pattern: (vector_shuffle:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v8i16))<<P:Predicate_pshuflw>><<X:SHUFFLE_get_pshuflw_imm>>:$src2
// Emits: (PSHUFLWmi:v8i16 addr:iPTR:$src1, (SHUFFLE_get_pshuflw_imm:i8 (vector_shuffle:v8i16 (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v8i16)):$src2))
// Pattern complexity = 32 cost = 1 size = 3
- if (Predicate_pshuflw(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_pshuflw(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode()) &&
Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_242(N, X86::PSHUFLWmi, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_237(N, X86::PSHUFLWmi, MVT::v8i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -44984,20 +44690,20 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(const SDValue &N) {
// Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckl>>
// Emits: (PUNPCKLWDrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_unpckl(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_unpckl(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -45016,20 +44722,20 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(const SDValue &N) {
// Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src1, (bitconvert:v8i16 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckh>>
// Emits: (PUNPCKHWDrm:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_unpckh(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_unpckh(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -45050,11 +44756,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(const SDValue &N) {
// Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src, (undef:v8i16))<<P:Predicate_unpckl_undef>>
// Emits: (PUNPCKLWDrr:v8i16 VR128:v16i8:$src, VR128:v16i8:$src)
// Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_unpckl_undef(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::PUNPCKLWDrr, MVT::v8i16);
+ if (Predicate_unpckl_undef(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::PUNPCKLWDrr, MVT::v8i16);
return Result;
}
}
@@ -45062,11 +44768,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(const SDValue &N) {
// Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src, (undef:v8i16))<<P:Predicate_unpckh_undef>>
// Emits: (PUNPCKHWDrr:v8i16 VR128:v16i8:$src, VR128:v16i8:$src)
// Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_unpckh_undef(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::PUNPCKHWDrr, MVT::v8i16);
+ if (Predicate_unpckh_undef(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::PUNPCKHWDrr, MVT::v8i16);
return Result;
}
}
@@ -45076,8 +44782,8 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(const SDValue &N) {
// Emits: (PALIGNR128rr:v8i16 VR128:v16i8:$src2, VR128:v16i8:$src1, (SHUFFLE_get_palign_imm:i8 VR128:i8:$src3))
// Pattern complexity = 9 cost = 1 size = 3
if ((Subtarget->hasSSSE3()) &&
- Predicate_palign(N.getNode())) {
- SDNode *Result = Emit_236(N, X86::PALIGNR128rr, MVT::v8i16);
+ Predicate_palign(N)) {
+ SDNode *Result = Emit_231(N, X86::PALIGNR128rr, MVT::v8i16);
return Result;
}
if ((Subtarget->hasSSE2())) {
@@ -45085,11 +44791,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(const SDValue &N) {
// Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src1, (undef:v8i16))<<P:Predicate_pshufhw>><<X:SHUFFLE_get_pshufhw_imm>>:$src2
// Emits: (PSHUFHWri:v8i16 VR128:v8i16:$src1, (SHUFFLE_get_pshufhw_imm:i8 (vector_shuffle:v8i16 VR128:v8i16:$src1, (undef:v8i16)):$src2))
// Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_pshufhw(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_239(N, X86::PSHUFHWri, MVT::v8i16);
+ if (Predicate_pshufhw(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_234(N, X86::PSHUFHWri, MVT::v8i16);
return Result;
}
}
@@ -45097,11 +44803,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(const SDValue &N) {
// Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src1, (undef:v8i16))<<P:Predicate_pshuflw>><<X:SHUFFLE_get_pshuflw_imm>>:$src2
// Emits: (PSHUFLWri:v8i16 VR128:v8i16:$src1, (SHUFFLE_get_pshuflw_imm:i8 (vector_shuffle:v8i16 VR128:v8i16:$src1, (undef:v8i16)):$src2))
// Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_pshuflw(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_241(N, X86::PSHUFLWri, MVT::v8i16);
+ if (Predicate_pshuflw(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_236(N, X86::PSHUFLWri, MVT::v8i16);
return Result;
}
}
@@ -45109,7 +44815,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(const SDValue &N) {
// Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)<<P:Predicate_unpckl>>
// Emits: (PUNPCKLWDrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_unpckl(N.getNode())) {
+ if (Predicate_unpckl(N)) {
SDNode *Result = Emit_15(N, X86::PUNPCKLWDrr, MVT::v8i16);
return Result;
}
@@ -45117,7 +44823,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(const SDValue &N) {
// Pattern: (vector_shuffle:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)<<P:Predicate_unpckh>>
// Emits: (PUNPCKHWDrr:v8i16 VR128:v8i16:$src1, VR128:v8i16:$src2)
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_unpckh(N.getNode())) {
+ if (Predicate_unpckh(N)) {
SDNode *Result = Emit_15(N, X86::PUNPCKHWDrr, MVT::v8i16);
return Result;
}
@@ -45127,26 +44833,26 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_VECTOR_SHUFFLE_v2i32(const SDValue &N) {
+SDNode *Select_ISD_VECTOR_SHUFFLE_v2i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasMMX())) {
// Pattern: (vector_shuffle:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckh>>
// Emits: (MMX_PUNPCKHDQrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_mmx_unpckh(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_mmx_unpckh(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -45165,19 +44871,19 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i32(const SDValue &N) {
// Pattern: (vector_shuffle:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))<<P:Predicate_mmx_unpckl>>
// Emits: (MMX_PUNPCKLDQrm:v2i32 VR64:v2i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_mmx_unpckl(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_mmx_unpckl(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -45197,11 +44903,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i32(const SDValue &N) {
// Pattern: (vector_shuffle:v2i32 VR64:v2i32:$src, (undef:v2i32))<<P:Predicate_mmx_unpckl_undef>>
// Emits: (MMX_PUNPCKLDQrr:v2i32 VR64:v8i8:$src, VR64:v8i8:$src)
// Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_mmx_unpckl_undef(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::MMX_PUNPCKLDQrr, MVT::v2i32);
+ if (Predicate_mmx_unpckl_undef(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::MMX_PUNPCKLDQrr, MVT::v2i32);
return Result;
}
}
@@ -45209,11 +44915,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i32(const SDValue &N) {
// Pattern: (vector_shuffle:v2i32 VR64:v2i32:$src, (undef:v2i32))<<P:Predicate_mmx_unpckh_undef>>
// Emits: (MMX_PUNPCKHDQrr:v2i32 VR64:v8i8:$src, VR64:v8i8:$src)
// Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_mmx_unpckh_undef(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::MMX_PUNPCKHDQrr, MVT::v2i32);
+ if (Predicate_mmx_unpckh_undef(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::MMX_PUNPCKHDQrr, MVT::v2i32);
return Result;
}
}
@@ -45222,7 +44928,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i32(const SDValue &N) {
// Pattern: (vector_shuffle:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)<<P:Predicate_mmx_unpckh>>
// Emits: (MMX_PUNPCKHDQrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_mmx_unpckh(N.getNode())) {
+ if (Predicate_mmx_unpckh(N)) {
SDNode *Result = Emit_15(N, X86::MMX_PUNPCKHDQrr, MVT::v2i32);
return Result;
}
@@ -45230,7 +44936,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i32(const SDValue &N) {
// Pattern: (vector_shuffle:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)<<P:Predicate_mmx_unpckl>>
// Emits: (MMX_PUNPCKLDQrr:v2i32 VR64:v2i32:$src1, VR64:v2i32:$src2)
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_mmx_unpckl(N.getNode())) {
+ if (Predicate_mmx_unpckl(N)) {
SDNode *Result = Emit_15(N, X86::MMX_PUNPCKLDQrr, MVT::v2i32);
return Result;
}
@@ -45240,92 +44946,92 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_243(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp2 = Transform_SHUFFLE_get_shuf_imm(N.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
+DISABLE_INLINE SDNode *Emit_238(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp2 = Transform_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2);
}
-DISABLE_INLINE SDNode *Emit_244(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue Chain00 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp2 = Transform_SHUFFLE_get_shuf_imm(N.getNode());
+DISABLE_INLINE SDNode *Emit_239(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp2 = Transform_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp2, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_245(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue Chain00 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_240(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_246(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(N.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, Tmp3);
-}
-DISABLE_INLINE SDNode *Emit_247(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(N.getNode());
+DISABLE_INLINE SDNode *Emit_241(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, Tmp3);
+}
+DISABLE_INLINE SDNode *Emit_242(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { N0, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp3, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
+SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((Subtarget->hasSSE3())) {
// Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_movshdup>>
// Emits: (MOVSHDUPrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_movshdup(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_movshdup(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode()) &&
Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_245(N, X86::MOVSHDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_240(N, X86::MOVSHDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -45337,29 +45043,29 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_movsldup>>
// Emits: (MOVSLDUPrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_movsldup(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_movsldup(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode()) &&
Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_245(N, X86::MOVSLDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_240(N, X86::MOVSLDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -45373,16 +45079,16 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)<<P:Predicate_movlp>>
// Emits: (MOVLPSrm:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 46 cost = 1 size = 3
- if (Predicate_movlp(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (Predicate_movlp(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -45399,29 +45105,29 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src2
// Emits: (PSHUFDmi:v4i32 addr:iPTR:$src1, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32)):$src2))
// Pattern complexity = 37 cost = 1 size = 3
- if (Predicate_pshufd(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_pshufd(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode()) &&
Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_244(N, X86::PSHUFDmi, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_239(N, X86::PSHUFDmi, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -45435,29 +45141,29 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Emits: (MOVDDUPrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 37 cost = 1 size = 3
if ((Subtarget->hasSSE3()) &&
- Predicate_movddup(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_movddup(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode()) &&
Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_245(N, X86::MOVDDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_240(N, X86::MOVDDUPrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -45470,29 +45176,29 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 (bitconvert:v4i32 (ld:v4f32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>), (undef:v4i32))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src2
// Emits: (PSHUFDmi:v4i32 addr:iPTR:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src2))
// Pattern complexity = 32 cost = 1 size = 3
- if (Predicate_pshufd(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_pshufd(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode()) &&
Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_244(N, X86::PSHUFDmi, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_239(N, X86::PSHUFDmi, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -45504,20 +45210,20 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckl>>
// Emits: (PUNPCKLDQrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_unpckl(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_unpckl(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -45536,20 +45242,20 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_unpckh>>
// Emits: (PUNPCKHDQrm:v4i32 VR128:v4i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_unpckh(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_unpckh(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -45568,20 +45274,20 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (bitconvert:v4i32 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
// Emits: (SHUFPSrmi:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
// Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_shufp(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_shufp(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -45589,7 +45295,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4) &&
N10.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_247(N, X86::SHUFPSrmi, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_242(N, X86::SHUFPSrmi, MVT::v4i32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -45602,11 +45308,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (undef:v4i32))<<P:Predicate_movhlps_undef>>
// Emits: (MOVHLPSrr:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src1)
// Pattern complexity = 27 cost = 1 size = 3
- if (Predicate_movhlps_undef(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::MOVHLPSrr, MVT::v4i32);
+ if (Predicate_movhlps_undef(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::MOVHLPSrr, MVT::v4i32);
return Result;
}
}
@@ -45614,7 +45320,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_movlhps>>
// Emits: (MOVLHPSrr:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 24 cost = 1 size = 3
- if (Predicate_movlhps(N.getNode())) {
+ if (Predicate_movlhps(N)) {
SDNode *Result = Emit_15(N, X86::MOVLHPSrr, MVT::v4i32);
return Result;
}
@@ -45622,7 +45328,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_movhlps>>
// Emits: (MOVHLPSrr:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 24 cost = 1 size = 3
- if (Predicate_movhlps(N.getNode())) {
+ if (Predicate_movhlps(N)) {
SDNode *Result = Emit_15(N, X86::MOVHLPSrr, MVT::v4i32);
return Result;
}
@@ -45631,11 +45337,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src, (undef:v4i32))<<P:Predicate_movshdup>>
// Emits: (MOVSHDUPrr:v4i32 VR128:v16i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_movshdup(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_94(N, X86::MOVSHDUPrr, MVT::v4i32);
+ if (Predicate_movshdup(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_93(N, X86::MOVSHDUPrr, MVT::v4i32);
return Result;
}
}
@@ -45643,11 +45349,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src, (undef:v4i32))<<P:Predicate_movsldup>>
// Emits: (MOVSLDUPrr:v4i32 VR128:v16i8:$src)
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_movsldup(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_94(N, X86::MOVSLDUPrr, MVT::v4i32);
+ if (Predicate_movsldup(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_93(N, X86::MOVSLDUPrr, MVT::v4i32);
return Result;
}
}
@@ -45657,11 +45363,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src, (undef:v4i32))<<P:Predicate_unpckl_undef>>:$src2
// Emits: (PSHUFDri:v4i32 VR128:v16i8:$src, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src2))
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_unpckl_undef(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_243(N, X86::PSHUFDri, MVT::v4i32);
+ if (Predicate_unpckl_undef(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_238(N, X86::PSHUFDri, MVT::v4i32);
return Result;
}
}
@@ -45669,11 +45375,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src, (undef:v4i32))<<P:Predicate_unpckh_undef>>:$src2
// Emits: (PSHUFDri:v4i32 VR128:v16i8:$src, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src2))
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_unpckh_undef(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_243(N, X86::PSHUFDri, MVT::v4i32);
+ if (Predicate_unpckh_undef(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_238(N, X86::PSHUFDri, MVT::v4i32);
return Result;
}
}
@@ -45683,7 +45389,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_movl>>
// Emits: (MOVLPSrr:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 19 cost = 1 size = 3
- if (Predicate_movl(N.getNode())) {
+ if (Predicate_movl(N)) {
SDNode *Result = Emit_15(N, X86::MOVLPSrr, MVT::v4i32);
return Result;
}
@@ -45691,7 +45397,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_movlp>>
// Emits: (MOVLPDrr:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 19 cost = 1 size = 3
- if (Predicate_movlp(N.getNode())) {
+ if (Predicate_movlp(N)) {
SDNode *Result = Emit_15(N, X86::MOVLPDrr, MVT::v4i32);
return Result;
}
@@ -45699,11 +45405,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src, (undef:v4i32))<<P:Predicate_unpckl_undef>>
// Emits: (PUNPCKLDQrr:v4i32 VR128:v16i8:$src, VR128:v16i8:$src)
// Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_unpckl_undef(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::PUNPCKLDQrr, MVT::v4i32);
+ if (Predicate_unpckl_undef(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::PUNPCKLDQrr, MVT::v4i32);
return Result;
}
}
@@ -45711,11 +45417,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src, (undef:v4i32))<<P:Predicate_unpckh_undef>>
// Emits: (PUNPCKHDQrr:v4i32 VR128:v16i8:$src, VR128:v16i8:$src)
// Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_unpckh_undef(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::PUNPCKHDQrr, MVT::v4i32);
+ if (Predicate_unpckh_undef(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::PUNPCKHDQrr, MVT::v4i32);
return Result;
}
}
@@ -45723,11 +45429,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, (undef:v4i32))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src2
// Emits: (PSHUFDri:v4i32 VR128:v4i32:$src1, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4i32 VR128:v4i32:$src1, (undef:v4i32)):$src2))
// Pattern complexity = 12 cost = 1 size = 3
- if (Predicate_pshufd(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_243(N, X86::PSHUFDri, MVT::v4i32);
+ if (Predicate_pshufd(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_238(N, X86::PSHUFDri, MVT::v4i32);
return Result;
}
}
@@ -45737,8 +45443,8 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Emits: (PALIGNR128rr:v4i32 VR128:v16i8:$src2, VR128:v16i8:$src1, (SHUFFLE_get_palign_imm:i8 VR128:i8:$src3))
// Pattern complexity = 9 cost = 1 size = 3
if ((Subtarget->hasSSSE3()) &&
- Predicate_palign(N.getNode())) {
- SDNode *Result = Emit_236(N, X86::PALIGNR128rr, MVT::v4i32);
+ Predicate_palign(N)) {
+ SDNode *Result = Emit_231(N, X86::PALIGNR128rr, MVT::v4i32);
return Result;
}
if ((Subtarget->hasSSE2())) {
@@ -45746,7 +45452,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_unpckl>>
// Emits: (PUNPCKLDQrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_unpckl(N.getNode())) {
+ if (Predicate_unpckl(N)) {
SDNode *Result = Emit_15(N, X86::PUNPCKLDQrr, MVT::v4i32);
return Result;
}
@@ -45754,7 +45460,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_unpckh>>
// Emits: (PUNPCKHDQrr:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_unpckh(N.getNode())) {
+ if (Predicate_unpckh(N)) {
SDNode *Result = Emit_15(N, X86::PUNPCKHDQrr, MVT::v4i32);
return Result;
}
@@ -45762,8 +45468,8 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
// Pattern: (vector_shuffle:v4i32 VR128:v4i32:$src1, VR128:v4i32:$src2)<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
// Emits: (SHUFPSrri:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_shufp(N.getNode())) {
- SDNode *Result = Emit_246(N, X86::SHUFPSrri, MVT::v4i32);
+ if (Predicate_shufp(N)) {
+ SDNode *Result = Emit_241(N, X86::SHUFPSrri, MVT::v4i32);
return Result;
}
}
@@ -45772,49 +45478,49 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_248(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N100);
+DISABLE_INLINE SDNode *Emit_243(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N100);
}
-DISABLE_INLINE SDNode *Emit_249(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_244(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_250(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(N.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N0, Tmp3);
+DISABLE_INLINE SDNode *Emit_245(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N0, Tmp3);
}
-SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
+SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
// Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)<<P:Predicate_movlp>>
// Emits: (MOVLPDrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 46 cost = 1 size = 3
if ((Subtarget->hasSSE2()) &&
- Predicate_movlp(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ Predicate_movlp(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -45832,25 +45538,25 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
// Emits: (MOVDDUPrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 34 cost = 1 size = 3
if ((Subtarget->hasSSE3()) &&
- Predicate_movddup(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ Predicate_movddup(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_249(N, X86::MOVDDUPrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_244(N, X86::MOVDDUPrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -45863,11 +45569,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
// Emits: (MOVLHPSrr:v2i64 VR128:v16i8:$src, VR128:v16i8:$src)
// Pattern complexity = 27 cost = 1 size = 3
if ((Subtarget->hasSSE1()) &&
- Predicate_movddup(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::MOVLHPSrr, MVT::v2i64);
+ Predicate_movddup(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::MOVLHPSrr, MVT::v2i64);
return Result;
}
}
@@ -45877,17 +45583,17 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
// Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckl>>
// Emits: (PUNPCKLQDQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 26 cost = 1 size = 3
- if (Predicate_unpckl(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (Predicate_unpckl(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -45904,17 +45610,17 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
// Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckh>>
// Emits: (PUNPCKHQDQrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 26 cost = 1 size = 3
- if (Predicate_unpckh(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (Predicate_unpckh(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -45933,7 +45639,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
// Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)<<P:Predicate_movl>>
// Emits: (MOVLPDrr:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 19 cost = 1 size = 3
- if (Predicate_movl(N.getNode())) {
+ if (Predicate_movl(N)) {
SDNode *Result = Emit_15(N, X86::MOVLPDrr, MVT::v2i64);
return Result;
}
@@ -45941,11 +45647,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
// Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src, (undef:v2i64))<<P:Predicate_splat_lo>>
// Emits: (PUNPCKLQDQrr:v2i64 VR128:v16i8:$src, VR128:v16i8:$src)
// Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_splat_lo(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::PUNPCKLQDQrr, MVT::v2i64);
+ if (Predicate_splat_lo(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::PUNPCKLQDQrr, MVT::v2i64);
return Result;
}
}
@@ -45953,11 +45659,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
// Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src, (undef:v2i64))<<P:Predicate_unpckh>>
// Emits: (PUNPCKHQDQrr:v2i64 VR128:v16i8:$src, VR128:v16i8:$src)
// Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_unpckh(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::PUNPCKHQDQrr, MVT::v2i64);
+ if (Predicate_unpckh(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::PUNPCKHQDQrr, MVT::v2i64);
return Result;
}
}
@@ -45965,18 +45671,18 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
// Pattern: (vector_shuffle:v2i64 (build_vector:v2i64)<<P:Predicate_immAllZerosV>>, (scalar_to_vector:v2i64 (bitconvert:i64 VR64:v8i8:$src)))<<P:Predicate_movl>>
// Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
// Pattern complexity = 14 cost = 1 size = 3
- if (Predicate_movl(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BUILD_VECTOR &&
+ if (Predicate_movl(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BUILD_VECTOR &&
Predicate_immAllZerosV(N0.getNode())) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N100 = N10.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR) {
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N100 = N10.getNode()->getOperand(0);
if (N10.getValueType() == MVT::i64 &&
N100.getValueType() == MVT::v8i8) {
- SDNode *Result = Emit_248(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
+ SDNode *Result = Emit_243(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
return Result;
}
}
@@ -45987,11 +45693,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
// Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, (undef:v2i64))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src3
// Emits: (SHUFPDrri:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
// Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_pshufd(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_250(N, X86::SHUFPDrri, MVT::v2i64);
+ if (Predicate_pshufd(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_245(N, X86::SHUFPDrri, MVT::v2i64);
return Result;
}
}
@@ -45999,7 +45705,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
// Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)<<P:Predicate_unpckl>>
// Emits: (PUNPCKLQDQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_unpckl(N.getNode())) {
+ if (Predicate_unpckl(N)) {
SDNode *Result = Emit_15(N, X86::PUNPCKLQDQrr, MVT::v2i64);
return Result;
}
@@ -46007,7 +45713,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
// Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)<<P:Predicate_unpckh>>
// Emits: (PUNPCKHQDQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_unpckh(N.getNode())) {
+ if (Predicate_unpckh(N)) {
SDNode *Result = Emit_15(N, X86::PUNPCKHQDQrr, MVT::v2i64);
return Result;
}
@@ -46015,8 +45721,8 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
// Pattern: (vector_shuffle:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
// Emits: (SHUFPDrri:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_shufp(N.getNode())) {
- SDNode *Result = Emit_246(N, X86::SHUFPDrri, MVT::v2i64);
+ if (Predicate_shufp(N)) {
+ SDNode *Result = Emit_241(N, X86::SHUFPDrri, MVT::v2i64);
return Result;
}
}
@@ -46025,65 +45731,65 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_251(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue N100 = N10.getOperand(0);
- SDValue Chain100 = N100.getOperand(0);
- SDValue N1001 = N100.getOperand(1);
+DISABLE_INLINE SDNode *Emit_246(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1001_0, SDValue &CPTmpN1001_1, SDValue &CPTmpN1001_2, SDValue &CPTmpN1001_3, SDValue &CPTmpN1001_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue N100 = N10.getNode()->getOperand(0);
+ SDValue Chain100 = N100.getNode()->getOperand(0);
+ SDValue N1001 = N100.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N100)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N100.getNode())->getMemOperand();
SDValue Ops0[] = { N0, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4, Chain100 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N100.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_252(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(N.getNode());
+DISABLE_INLINE SDNode *Emit_247(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Tmp3, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_253(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(N.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N1, N0, Tmp3);
+DISABLE_INLINE SDNode *Emit_248(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Tmp3 = Transform_SHUFFLE_get_shuf_imm(SDValue(N, 0).getNode());
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N1, N0, Tmp3);
}
-SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
+SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((Subtarget->hasSSE1())) {
// Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (bitconvert:v4f32 (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)))<<P:Predicate_movlp>>
// Emits: (MOVLPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_movlp(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_movlp(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
- SDValue Chain100 = N100.getOperand(0);
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_load(N100.getNode()) &&
Predicate_loadf64(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
@@ -46092,7 +45798,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v2f64 &&
N100.getValueType() == MVT::f64) {
- SDNode *Result = Emit_251(N, X86::MOVLPSrm, MVT::v4f32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_246(N, X86::MOVLPSrm, MVT::v4f32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -46104,23 +45810,23 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (bitconvert:v4f32 (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>)))<<P:Predicate_movlhps>>
// Emits: (MOVHPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 52 cost = 1 size = 3
- if (Predicate_movlhps(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ if (Predicate_movlhps(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N10.hasOneUse()) {
- SDValue N100 = N10.getOperand(0);
- if (N100.getOpcode() == ISD::LOAD &&
+ SDValue N100 = N10.getNode()->getOperand(0);
+ if (N100.getNode()->getOpcode() == ISD::LOAD &&
N100.hasOneUse() &&
- IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N.getNode())) {
- SDValue Chain100 = N100.getOperand(0);
+ IsLegalAndProfitableToFold(N100.getNode(), N10.getNode(), N)) {
+ SDValue Chain100 = N100.getNode()->getOperand(0);
if (Predicate_unindexedload(N100.getNode()) &&
Predicate_load(N100.getNode()) &&
Predicate_loadf64(N100.getNode())) {
- SDValue N1001 = N100.getOperand(1);
+ SDValue N1001 = N100.getNode()->getOperand(1);
SDValue CPTmpN1001_0;
SDValue CPTmpN1001_1;
SDValue CPTmpN1001_2;
@@ -46129,7 +45835,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
if (SelectAddr(N, N1001, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4) &&
N10.getValueType() == MVT::v2f64 &&
N100.getValueType() == MVT::f64) {
- SDNode *Result = Emit_251(N, X86::MOVHPSrm, MVT::v4f32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
+ SDNode *Result = Emit_246(N, X86::MOVHPSrm, MVT::v4f32, CPTmpN1001_0, CPTmpN1001_1, CPTmpN1001_2, CPTmpN1001_3, CPTmpN1001_4);
return Result;
}
}
@@ -46141,16 +45847,16 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)<<P:Predicate_movlp>>
// Emits: (MOVLPSrm:v4f32 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 46 cost = 1 size = 3
- if (Predicate_movlp(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (Predicate_movlp(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -46169,29 +45875,29 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Emits: (MOVDDUPrm:v4f32 addr:iPTR:$src)
// Pattern complexity = 37 cost = 1 size = 3
if ((Subtarget->hasSSE3()) &&
- Predicate_movddup(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ Predicate_movddup(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode()) &&
Predicate_memop(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_245(N, X86::MOVDDUPrm, MVT::v4f32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_240(N, X86::MOVDDUPrm, MVT::v4f32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -46204,17 +45910,17 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckh>>
// Emits: (UNPCKHPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 36 cost = 1 size = 3
- if (Predicate_unpckh(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (Predicate_unpckh(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -46231,17 +45937,17 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckl>>
// Emits: (UNPCKLPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 36 cost = 1 size = 3
- if (Predicate_unpckl(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (Predicate_unpckl(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -46260,25 +45966,25 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern: (vector_shuffle:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (undef:v4f32))<<P:Predicate_movshdup>>
// Emits: (MOVSHDUPrm:v4f32 addr:iPTR:$src)
// Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_movshdup(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ if (Predicate_movshdup(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_249(N, X86::MOVSHDUPrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_244(N, X86::MOVSHDUPrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -46289,25 +45995,25 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern: (vector_shuffle:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (undef:v4f32))<<P:Predicate_movsldup>>
// Emits: (MOVSLDUPrm:v4f32 addr:iPTR:$src)
// Pattern complexity = 29 cost = 1 size = 3
- if (Predicate_movsldup(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ if (Predicate_movsldup(N)) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_249(N, X86::MOVSLDUPrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_244(N, X86::MOVSLDUPrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -46321,11 +46027,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Emits: (MOVLHPSrr:v4f32 VR128:v16i8:$src, VR128:v16i8:$src)
// Pattern complexity = 27 cost = 1 size = 3
if ((Subtarget->hasSSE1()) &&
- Predicate_movddup(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::MOVLHPSrr, MVT::v4f32);
+ Predicate_movddup(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::MOVLHPSrr, MVT::v4f32);
return Result;
}
}
@@ -46333,11 +46039,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (undef:v4f32))<<P:Predicate_movhlps_undef>>
// Emits: (MOVHLPSrr:v4f32 VR128:v16i8:$src1, VR128:v16i8:$src1)
// Pattern complexity = 27 cost = 1 size = 3
- if (Predicate_movhlps_undef(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::MOVHLPSrr, MVT::v4f32);
+ if (Predicate_movhlps_undef(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::MOVHLPSrr, MVT::v4f32);
return Result;
}
}
@@ -46347,24 +46053,24 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern complexity = 26 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE1()) &&
- Predicate_shufp(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ Predicate_shufp(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_252(N, X86::SHUFPSrmi, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_247(N, X86::SHUFPSrmi, MVT::v4f32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -46375,7 +46081,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_movlhps>>
// Emits: (MOVLHPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 24 cost = 1 size = 3
- if (Predicate_movlhps(N.getNode())) {
+ if (Predicate_movlhps(N)) {
SDNode *Result = Emit_15(N, X86::MOVLHPSrr, MVT::v4f32);
return Result;
}
@@ -46383,7 +46089,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_movhlps>>
// Emits: (MOVHLPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 24 cost = 1 size = 3
- if (Predicate_movhlps(N.getNode())) {
+ if (Predicate_movhlps(N)) {
SDNode *Result = Emit_15(N, X86::MOVHLPSrr, MVT::v4f32);
return Result;
}
@@ -46393,11 +46099,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src, (undef:v4f32))<<P:Predicate_unpckl_undef>>:$src2
// Emits: (PSHUFDri:v4f32 VR128:v16i8:$src, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src2))
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_unpckl_undef(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_243(N, X86::PSHUFDri, MVT::v4f32);
+ if (Predicate_unpckl_undef(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_238(N, X86::PSHUFDri, MVT::v4f32);
return Result;
}
}
@@ -46405,11 +46111,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src, (undef:v4f32))<<P:Predicate_unpckh_undef>>:$src2
// Emits: (PSHUFDri:v4f32 VR128:v16i8:$src, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src2))
// Pattern complexity = 22 cost = 1 size = 3
- if (Predicate_unpckh_undef(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_243(N, X86::PSHUFDri, MVT::v4f32);
+ if (Predicate_unpckh_undef(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_238(N, X86::PSHUFDri, MVT::v4f32);
return Result;
}
}
@@ -46419,7 +46125,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Emits: (MOVLPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 19 cost = 1 size = 3
if ((Subtarget->hasSSE1()) &&
- Predicate_movl(N.getNode())) {
+ Predicate_movl(N)) {
SDNode *Result = Emit_15(N, X86::MOVLPSrr, MVT::v4f32);
return Result;
}
@@ -46428,7 +46134,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Emits: (MOVLPDrr:v4f32 VR128:v16i8:$src1, VR128:v16i8:$src2)
// Pattern complexity = 19 cost = 1 size = 3
if ((Subtarget->hasSSE2()) &&
- Predicate_movlp(N.getNode())) {
+ Predicate_movlp(N)) {
SDNode *Result = Emit_15(N, X86::MOVLPDrr, MVT::v4f32);
return Result;
}
@@ -46437,11 +46143,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src, (undef:v4f32))<<P:Predicate_unpckl_undef>>
// Emits: (UNPCKLPSrr:v4f32 VR128:v16i8:$src, VR128:v16i8:$src)
// Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_unpckl_undef(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::UNPCKLPSrr, MVT::v4f32);
+ if (Predicate_unpckl_undef(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::UNPCKLPSrr, MVT::v4f32);
return Result;
}
}
@@ -46449,11 +46155,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src, (undef:v4f32))<<P:Predicate_unpckh_undef>>
// Emits: (UNPCKHPSrr:v4f32 VR128:v16i8:$src, VR128:v16i8:$src)
// Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_unpckh_undef(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::UNPCKHPSrr, MVT::v4f32);
+ if (Predicate_unpckh_undef(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::UNPCKHPSrr, MVT::v4f32);
return Result;
}
}
@@ -46461,7 +46167,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_unpckh>>
// Emits: (UNPCKHPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 14 cost = 1 size = 3
- if (Predicate_unpckh(N.getNode())) {
+ if (Predicate_unpckh(N)) {
SDNode *Result = Emit_15(N, X86::UNPCKHPSrr, MVT::v4f32);
return Result;
}
@@ -46469,7 +46175,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_unpckl>>
// Emits: (UNPCKLPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 14 cost = 1 size = 3
- if (Predicate_unpckl(N.getNode())) {
+ if (Predicate_unpckl(N)) {
SDNode *Result = Emit_15(N, X86::UNPCKLPSrr, MVT::v4f32);
return Result;
}
@@ -46479,11 +46185,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Emits: (PSHUFDri:v4f32 VR128:v16i8:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src2))
// Pattern complexity = 12 cost = 1 size = 3
if ((Subtarget->hasSSE2()) &&
- Predicate_pshufd(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_243(N, X86::PSHUFDri, MVT::v4f32);
+ Predicate_pshufd(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_238(N, X86::PSHUFDri, MVT::v4f32);
return Result;
}
}
@@ -46492,8 +46198,8 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Emits: (PALIGNR128rr:v4f32 VR128:v16i8:$src2, VR128:v16i8:$src1, (SHUFFLE_get_palign_imm:i8 VR128:i8:$src3))
// Pattern complexity = 9 cost = 1 size = 3
if ((Subtarget->hasSSSE3()) &&
- Predicate_palign(N.getNode())) {
- SDNode *Result = Emit_236(N, X86::PALIGNR128rr, MVT::v4f32);
+ Predicate_palign(N)) {
+ SDNode *Result = Emit_231(N, X86::PALIGNR128rr, MVT::v4f32);
return Result;
}
if ((Subtarget->hasSSE3())) {
@@ -46501,11 +46207,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src, (undef:v4f32))<<P:Predicate_movshdup>>
// Emits: (MOVSHDUPrr:v4f32 VR128:v4f32:$src)
// Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_movshdup(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_94(N, X86::MOVSHDUPrr, MVT::v4f32);
+ if (Predicate_movshdup(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_93(N, X86::MOVSHDUPrr, MVT::v4f32);
return Result;
}
}
@@ -46513,11 +46219,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src, (undef:v4f32))<<P:Predicate_movsldup>>
// Emits: (MOVSLDUPrr:v4f32 VR128:v4f32:$src)
// Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_movsldup(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_94(N, X86::MOVSLDUPrr, MVT::v4f32);
+ if (Predicate_movsldup(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_93(N, X86::MOVSLDUPrr, MVT::v4f32);
return Result;
}
}
@@ -46527,11 +46233,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, (undef:v4f32))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src3
// Emits: (SHUFPSrri:v4f32 VR128:v16i8:$src1, VR128:v16i8:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
// Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_pshufd(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_250(N, X86::SHUFPSrri, MVT::v4f32);
+ if (Predicate_pshufd(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_245(N, X86::SHUFPSrri, MVT::v4f32);
return Result;
}
}
@@ -46539,16 +46245,16 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
// Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
// Emits: (SHUFPSrri:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2):$src3))
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_shufp(N.getNode())) {
- SDNode *Result = Emit_246(N, X86::SHUFPSrri, MVT::v4f32);
+ if (Predicate_shufp(N)) {
+ SDNode *Result = Emit_241(N, X86::SHUFPSrri, MVT::v4f32);
return Result;
}
// Pattern: (vector_shuffle:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2)<<P:Predicate_movlp>>:$src3
// Emits: (SHUFPSrri:v4f32 VR128:v16i8:$src2, VR128:v16i8:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_movlp(N.getNode())) {
- SDNode *Result = Emit_253(N, X86::SHUFPSrri, MVT::v4f32);
+ if (Predicate_movlp(N)) {
+ SDNode *Result = Emit_248(N, X86::SHUFPSrri, MVT::v4f32);
return Result;
}
}
@@ -46557,42 +46263,42 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v4f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_254(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0001_0, SDValue &CPTmpN0001_1, SDValue &CPTmpN0001_2, SDValue &CPTmpN0001_3, SDValue &CPTmpN0001_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N000 = N00.getOperand(0);
- SDValue Chain000 = N000.getOperand(0);
- SDValue N0001 = N000.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_249(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0001_0, SDValue &CPTmpN0001_1, SDValue &CPTmpN0001_2, SDValue &CPTmpN0001_3, SDValue &CPTmpN0001_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue Chain000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N000)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N000.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4, Chain000 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N000.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
+SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
if ((Subtarget->hasSSE2())) {
// Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>))<<P:Predicate_movlp>>
// Emits: (MOVLPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 49 cost = 1 size = 3
- if (Predicate_movlp(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ if (Predicate_movlp(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadf64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -46611,20 +46317,20 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
// Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>))<<P:Predicate_movlhps>>
// Emits: (MOVHPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 49 cost = 1 size = 3
- if (Predicate_movlhps(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ if (Predicate_movlhps(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadf64(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -46643,16 +46349,16 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
// Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)<<P:Predicate_movlp>>
// Emits: (MOVLPDrm:v2f64 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 46 cost = 1 size = 3
- if (Predicate_movlp(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (Predicate_movlp(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -46669,17 +46375,17 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
// Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckh>>
// Emits: (UNPCKHPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 36 cost = 1 size = 3
- if (Predicate_unpckh(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (Predicate_unpckh(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -46696,17 +46402,17 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
// Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_unpckl>>
// Emits: (UNPCKLPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 36 cost = 1 size = 3
- if (Predicate_unpckl(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ if (Predicate_unpckl(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -46721,37 +46427,37 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE3()) &&
- Predicate_movddup(N.getNode())) {
- SDValue N0 = N.getOperand(0);
+ Predicate_movddup(N)) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (vector_shuffle:v2f64 (bitconvert:v2f64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)), (undef:v2f64))<<P:Predicate_movddup>>
// Emits: (MOVDDUPrm:v2f64 addr:iPTR:$src)
// Pattern complexity = 35 cost = 1 size = 3
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N00.hasOneUse()) {
- SDValue N000 = N00.getOperand(0);
- if (N000.getOpcode() == ISD::LOAD &&
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::LOAD &&
N000.hasOneUse() &&
- IsLegalAndProfitableToFold(N000.getNode(), N00.getNode(), N.getNode())) {
- SDValue Chain000 = N000.getOperand(0);
+ IsLegalAndProfitableToFold(N000.getNode(), N00.getNode(), N)) {
+ SDValue Chain000 = N000.getNode()->getOperand(0);
if (Predicate_unindexedload(N000.getNode()) &&
Predicate_load(N000.getNode()) &&
Predicate_loadi64(N000.getNode())) {
- SDValue N0001 = N000.getOperand(1);
+ SDValue N0001 = N000.getNode()->getOperand(1);
SDValue CPTmpN0001_0;
SDValue CPTmpN0001_1;
SDValue CPTmpN0001_2;
SDValue CPTmpN0001_3;
SDValue CPTmpN0001_4;
if (SelectAddr(N, N0001, CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::v2i64 &&
N000.getValueType() == MVT::i64) {
- SDNode *Result = Emit_254(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4);
+ SDNode *Result = Emit_249(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4);
return Result;
}
}
@@ -46763,23 +46469,23 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
// Pattern: (vector_shuffle:v2f64 (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (undef:v2f64))<<P:Predicate_movddup>>
// Emits: (MOVDDUPrm:v2f64 addr:iPTR:$src)
// Pattern complexity = 34 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_249(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_244(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -46789,27 +46495,27 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
// Pattern: (vector_shuffle:v2f64 (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>), (undef:v2f64))<<P:Predicate_movddup>>
// Emits: (MOVDDUPrm:v2f64 addr:iPTR:$src)
// Pattern complexity = 32 cost = 1 size = 3
- if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode()) &&
Predicate_loadf64(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF &&
N00.getValueType() == MVT::f64) {
- SDNode *Result = Emit_245(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_240(N, X86::MOVDDUPrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -46822,24 +46528,24 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
// Emits: (SHUFPDrmi:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>):$src3))
// Pattern complexity = 26 cost = 1 size = 3
if ((Subtarget->hasSSE2()) &&
- Predicate_shufp(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ Predicate_shufp(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_252(N, X86::SHUFPDrmi, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_247(N, X86::SHUFPDrmi, MVT::v2f64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -46847,16 +46553,16 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- if (Predicate_movl(N.getNode())) {
+ if (Predicate_movl(N)) {
// Pattern: (vector_shuffle:v2f64 (bitconvert:v2f64)<<P:Predicate_immAllZerosV_bc>>, VR128:v2f64:$src)<<P:Predicate_movl>>
// Emits: (MOVZPQILo2PQIrr:v2f64 VR128:v16i8:$src)
// Pattern complexity = 23 cost = 1 size = 3
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
Predicate_immAllZerosV_bc(N0.getNode())) {
- SDNode *Result = Emit_108(N, X86::MOVZPQILo2PQIrr, MVT::v2f64);
+ SDNode *Result = Emit_107(N, X86::MOVZPQILo2PQIrr, MVT::v2f64);
return Result;
}
}
@@ -46871,24 +46577,24 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
// Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src, (undef:v2f64))<<P:Predicate_splat_lo>>
// Emits: (UNPCKLPDrr:v2f64 VR128:v16i8:$src, VR128:v16i8:$src)
// Pattern complexity = 17 cost = 1 size = 3
- if (Predicate_splat_lo(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::UNPCKLPDrr, MVT::v2f64);
+ if (Predicate_splat_lo(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::UNPCKLPDrr, MVT::v2f64);
return Result;
}
}
- if (Predicate_unpckh(N.getNode())) {
+ if (Predicate_unpckh(N)) {
// Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src, (undef:v2f64))<<P:Predicate_unpckh>>
// Emits: (UNPCKHPDrr:v2f64 VR128:v16i8:$src, VR128:v16i8:$src)
// Pattern complexity = 17 cost = 1 size = 3
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_164(N, X86::UNPCKHPDrr, MVT::v2f64);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_161(N, X86::UNPCKHPDrr, MVT::v2f64);
return Result;
}
}
@@ -46903,7 +46609,7 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
// Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)<<P:Predicate_unpckl>>
// Emits: (UNPCKLPDrr:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 14 cost = 1 size = 3
- if (Predicate_unpckl(N.getNode())) {
+ if (Predicate_unpckl(N)) {
SDNode *Result = Emit_15(N, X86::UNPCKLPDrr, MVT::v2f64);
return Result;
}
@@ -46913,11 +46619,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
// Emits: (MOVDDUPrr:v2f64 VR128:v2f64:$src)
// Pattern complexity = 7 cost = 1 size = 3
if ((Subtarget->hasSSE3()) &&
- Predicate_movddup(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_94(N, X86::MOVDDUPrr, MVT::v2f64);
+ Predicate_movddup(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_93(N, X86::MOVDDUPrr, MVT::v2f64);
return Result;
}
}
@@ -46926,11 +46632,11 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
// Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, (undef:v2f64))<<P:Predicate_pshufd>><<X:SHUFFLE_get_shuf_imm>>:$src3
// Emits: (SHUFPDrri:v2f64 VR128:v16i8:$src1, VR128:v16i8:$src1, (SHUFFLE_get_shuf_imm:i8 VR128:i8:$src3))
// Pattern complexity = 7 cost = 1 size = 3
- if (Predicate_pshufd(N.getNode())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::UNDEF) {
- SDNode *Result = Emit_250(N, X86::SHUFPDrri, MVT::v2f64);
+ if (Predicate_pshufd(N)) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::UNDEF) {
+ SDNode *Result = Emit_245(N, X86::SHUFPDrri, MVT::v2f64);
return Result;
}
}
@@ -46938,8 +46644,8 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
// Pattern: (vector_shuffle:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2)<<P:Predicate_shufp>><<X:SHUFFLE_get_shuf_imm>>:$src3
// Emits: (SHUFPDrri:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2, (SHUFFLE_get_shuf_imm:i8 (vector_shuffle:v2f64 VR128:v2f64:$src1, VR128:v2f64:$src2):$src3))
// Pattern complexity = 4 cost = 1 size = 3
- if (Predicate_shufp(N.getNode())) {
- SDNode *Result = Emit_246(N, X86::SHUFPDrri, MVT::v2f64);
+ if (Predicate_shufp(N)) {
+ SDNode *Result = Emit_241(N, X86::SHUFPDrri, MVT::v2f64);
return Result;
}
}
@@ -46948,22 +46654,22 @@ SDNode *Select_ISD_VECTOR_SHUFFLE_v2f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_XOR_i8(const SDValue &N) {
+SDNode *Select_ISD_XOR_i8(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (xor:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (XOR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -46980,13 +46686,13 @@ SDNode *Select_ISD_XOR_i8(const SDValue &N) {
// Pattern: (xor:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR8:i8:$src1)
// Emits: (XOR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -47000,15 +46706,15 @@ SDNode *Select_ISD_XOR_i8(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (xor:i8 GR8:i8:$src, (imm:i8)<<P:Predicate_immAllOnes>>)
// Emits: (NOT8r:i8 GR8:i8:$src)
// Pattern complexity = 22 cost = 1 size = 2
if (Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_94(N, X86::NOT8r, MVT::i8);
+ SDNode *Result = Emit_93(N, X86::NOT8r, MVT::i8);
return Result;
}
@@ -47027,22 +46733,22 @@ SDNode *Select_ISD_XOR_i8(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_XOR_i16(const SDValue &N) {
+SDNode *Select_ISD_XOR_i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (xor:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (XOR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -47059,13 +46765,13 @@ SDNode *Select_ISD_XOR_i16(const SDValue &N) {
// Pattern: (xor:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR16:i16:$src1)
// Emits: (XOR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -47079,15 +46785,15 @@ SDNode *Select_ISD_XOR_i16(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (xor:i16 GR16:i16:$src, (imm:i16)<<P:Predicate_immAllOnes>>)
// Emits: (NOT16r:i16 GR16:i16:$src)
// Pattern complexity = 22 cost = 1 size = 2
if (Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_94(N, X86::NOT16r, MVT::i16);
+ SDNode *Result = Emit_93(N, X86::NOT16r, MVT::i16);
return Result;
}
@@ -47114,22 +46820,22 @@ SDNode *Select_ISD_XOR_i16(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_XOR_i32(const SDValue &N) {
+SDNode *Select_ISD_XOR_i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (xor:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (XOR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -47146,13 +46852,13 @@ SDNode *Select_ISD_XOR_i32(const SDValue &N) {
// Pattern: (xor:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR32:i32:$src1)
// Emits: (XOR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -47166,15 +46872,15 @@ SDNode *Select_ISD_XOR_i32(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (xor:i32 GR32:i32:$src, (imm:i32)<<P:Predicate_immAllOnes>>)
// Emits: (NOT32r:i32 GR32:i32:$src)
// Pattern complexity = 22 cost = 1 size = 2
if (Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_94(N, X86::NOT32r, MVT::i32);
+ SDNode *Result = Emit_93(N, X86::NOT32r, MVT::i32);
return Result;
}
@@ -47201,22 +46907,22 @@ SDNode *Select_ISD_XOR_i32(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_XOR_i64(const SDValue &N) {
+SDNode *Select_ISD_XOR_i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (xor:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (XOR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -47233,13 +46939,13 @@ SDNode *Select_ISD_XOR_i64(const SDValue &N) {
// Pattern: (xor:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, GR64:i64:$src1)
// Emits: (XOR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -47253,15 +46959,15 @@ SDNode *Select_ISD_XOR_i64(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (xor:i64 GR64:i64:$src, (imm:i64)<<P:Predicate_immAllOnes>>)
// Emits: (NOT64r:i64 GR64:i64:$src)
// Pattern complexity = 22 cost = 1 size = 3
if (Predicate_immAllOnes(N1.getNode())) {
- SDNode *Result = Emit_94(N, X86::NOT64r, MVT::i64);
+ SDNode *Result = Emit_93(N, X86::NOT64r, MVT::i64);
return Result;
}
@@ -47290,23 +46996,23 @@ SDNode *Select_ISD_XOR_i64(const SDValue &N) {
return Result;
}
-SDNode *Select_ISD_XOR_v1i64(const SDValue &N) {
+SDNode *Select_ISD_XOR_v1i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (xor:v1i64 VR64:v1i64:$src1, (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (MMX_PXORrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -47323,13 +47029,13 @@ SDNode *Select_ISD_XOR_v1i64(const SDValue &N) {
// Pattern: (xor:v1i64 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>, VR64:v1i64:$src1)
// Emits: (MMX_PXORrm:v1i64 VR64:v1i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -47355,25 +47061,25 @@ SDNode *Select_ISD_XOR_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_XOR_v2i64(const SDValue &N) {
+SDNode *Select_ISD_XOR_v2i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
// Pattern: (xor:v2i64 (bitconvert:v2i64 VR128:v4f32:$src1), (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (XORPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -47381,7 +47087,7 @@ SDNode *Select_ISD_XOR_v2i64(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_56(N, X86::XORPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_57(N, X86::XORPSrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -47393,18 +47099,18 @@ SDNode *Select_ISD_XOR_v2i64(const SDValue &N) {
// Emits: (XORPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -47412,7 +47118,7 @@ SDNode *Select_ISD_XOR_v2i64(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N00.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_56(N, X86::XORPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_57(N, X86::XORPDrm, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -47424,26 +47130,26 @@ SDNode *Select_ISD_XOR_v2i64(const SDValue &N) {
// Emits: (XORPSrm:v2i64 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
if (N10.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_61(N, X86::XORPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_62(N, X86::XORPSrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -47452,30 +47158,30 @@ SDNode *Select_ISD_XOR_v2i64(const SDValue &N) {
}
}
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (xor:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (bitconvert:v2i64 VR128:v2f64:$src1))
// Emits: (XORPDrm:v2i64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
if (N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_61(N, X86::XORPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_62(N, X86::XORPDrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -47487,15 +47193,15 @@ SDNode *Select_ISD_XOR_v2i64(const SDValue &N) {
// Emits: (PXORrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -47512,14 +47218,14 @@ SDNode *Select_ISD_XOR_v2i64(const SDValue &N) {
// Pattern: (xor:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
// Emits: (PXORrm:v2i64 VR128:v2i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -47538,15 +47244,15 @@ SDNode *Select_ISD_XOR_v2i64(const SDValue &N) {
// Emits: (XORPDrr:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 9 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N00 = N0.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT) {
- SDValue N10 = N1.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT) {
+ SDValue N10 = N1.getNode()->getOperand(0);
if (N00.getValueType() == MVT::v2f64 &&
N10.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_58(N, X86::XORPDrr, MVT::v2i64);
+ SDNode *Result = Emit_59(N, X86::XORPDrr, MVT::v2i64);
return Result;
}
}
@@ -47573,10 +47279,10 @@ SDNode *Select_ISD_XOR_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ZERO_EXTEND_i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_ZERO_EXTEND_i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_71(N, X86::MOVZX16rr8, MVT::i16);
+ SDNode *Result = Emit_72(N, X86::MOVZX16rr8, MVT::i16);
return Result;
}
@@ -47584,24 +47290,24 @@ SDNode *Select_ISD_ZERO_EXTEND_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ZERO_EXTEND_i32(const SDValue &N) {
+SDNode *Select_ISD_ZERO_EXTEND_i32(SDNode *N) {
// Pattern: (zext:i32 (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>)
// Emits: (MOVZX32rr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32))
// Pattern complexity = 12 cost = 3 size = 3
if ((!Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SRL &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRL &&
Predicate_srl_su(N0.getNode())) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(8) &&
N0.getValueType() == MVT::i16 &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_73(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i16, MVT::i8, MVT::i32);
+ SDNode *Result = Emit_74(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32rr8, MVT::i16, MVT::i8, MVT::i32);
return Result;
}
}
@@ -47612,30 +47318,30 @@ SDNode *Select_ISD_ZERO_EXTEND_i32(const SDValue &N) {
// Emits: (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32))
// Pattern complexity = 12 cost = 3 size = 3
if ((Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SRL &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SRL &&
Predicate_srl_su(N0.getNode())) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(8) &&
N0.getValueType() == MVT::i16 &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_73(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, MVT::i16, MVT::i8, MVT::i32);
+ SDNode *Result = Emit_74(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, MVT::i16, MVT::i8, MVT::i32);
return Result;
}
}
}
}
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (zext:i32 GR8:i8:$src)
// Emits: (MOVZX32rr8:i32 GR8:i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_71(N, X86::MOVZX32rr8, MVT::i32);
+ SDNode *Result = Emit_72(N, X86::MOVZX32rr8, MVT::i32);
return Result;
}
@@ -47643,7 +47349,7 @@ SDNode *Select_ISD_ZERO_EXTEND_i32(const SDValue &N) {
// Emits: (MOVZX32rr16:i32 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_71(N, X86::MOVZX32rr16, MVT::i32);
+ SDNode *Result = Emit_72(N, X86::MOVZX32rr16, MVT::i32);
return Result;
}
@@ -47651,23 +47357,23 @@ SDNode *Select_ISD_ZERO_EXTEND_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_ISD_ZERO_EXTEND_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_ISD_ZERO_EXTEND_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (zext:i64 (srl:i16 GR16:i16:$src, 8:i8)<<P:Predicate_srl_su>>)
// Emits: (SUBREG_TO_REG:i64 0:i64, (MOVZX32_NOREXrr8:i32 (EXTRACT_SUBREG:i8 (COPY_TO_REGCLASS:i16 GR16:i16:$src, GR16_ABCD:i16), 2:i32)), 4:i32)
// Pattern complexity = 12 cost = 4 size = 3
- if (N0.getOpcode() == ISD::SRL &&
+ if (N0.getNode()->getOpcode() == ISD::SRL &&
Predicate_srl_su(N0.getNode())) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N01.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(8) &&
N0.getValueType() == MVT::i16 &&
N01.getValueType() == MVT::i8) {
- SDNode *Result = Emit_75(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetInstrInfo::SUBREG_TO_REG, MVT::i16, MVT::i8, MVT::i32, MVT::i64);
+ SDNode *Result = Emit_76(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, X86::MOVZX32_NOREXrr8, TargetInstrInfo::SUBREG_TO_REG, MVT::i16, MVT::i8, MVT::i32, MVT::i64);
return Result;
}
}
@@ -47678,7 +47384,7 @@ SDNode *Select_ISD_ZERO_EXTEND_i64(const SDValue &N) {
// Pattern complexity = 4 cost = 1 size = 0
if (Predicate_def32(N0.getNode()) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_74(N, TargetInstrInfo::SUBREG_TO_REG, MVT::i64);
+ SDNode *Result = Emit_75(N, TargetInstrInfo::SUBREG_TO_REG, MVT::i64);
return Result;
}
@@ -47686,7 +47392,7 @@ SDNode *Select_ISD_ZERO_EXTEND_i64(const SDValue &N) {
// Emits: (MOVZX64rr8:i64 GR8:i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_71(N, X86::MOVZX64rr8, MVT::i64);
+ SDNode *Result = Emit_72(N, X86::MOVZX64rr8, MVT::i64);
return Result;
}
@@ -47694,7 +47400,7 @@ SDNode *Select_ISD_ZERO_EXTEND_i64(const SDValue &N) {
// Emits: (MOVZX64rr16:i64 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_71(N, X86::MOVZX64rr16, MVT::i64);
+ SDNode *Result = Emit_72(N, X86::MOVZX64rr16, MVT::i64);
return Result;
}
@@ -47702,7 +47408,7 @@ SDNode *Select_ISD_ZERO_EXTEND_i64(const SDValue &N) {
// Emits: (MOVZX64rr32:i64 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_71(N, X86::MOVZX64rr32, MVT::i64);
+ SDNode *Result = Emit_72(N, X86::MOVZX64rr32, MVT::i64);
return Result;
}
@@ -47710,29 +47416,54 @@ SDNode *Select_ISD_ZERO_EXTEND_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_ADD_i8(const SDValue &N) {
-
- // Pattern: (X86add_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
- // Emits: (ADD8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+SDNode *Select_X86ISD_ADD_i8(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi8(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::ADD8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86add_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
+ // Emits: (ADD8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi8(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::ADD8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86add_flag:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src1)
+ // Emits: (ADD8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadi8(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::ADD8rm, MVT::i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -47743,9 +47474,9 @@ SDNode *Select_X86ISD_ADD_i8(const SDValue &N) {
// Emits: (ADD8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_3(N, X86::ADD8ri, MVT::i8);
return Result;
}
@@ -47758,37 +47489,61 @@ SDNode *Select_X86ISD_ADD_i8(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_ADD_i16(const SDValue &N) {
-
- // Pattern: (X86add_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
- // Emits: (ADD16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+SDNode *Select_X86ISD_ADD_i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi16(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::ADD16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86add_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
+ // Emits: (ADD16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi16(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::ADD16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86add_flag:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src1)
+ // Emits: (ADD16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi16(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::ADD16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86add_flag:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Emits: (ADD16ri8:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
@@ -47813,37 +47568,61 @@ SDNode *Select_X86ISD_ADD_i16(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_ADD_i32(const SDValue &N) {
-
- // Pattern: (X86add_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (ADD32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+SDNode *Select_X86ISD_ADD_i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::ADD32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86add_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (ADD32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi32(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::ADD32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86add_flag:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src1)
+ // Emits: (ADD32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::ADD32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86add_flag:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Emits: (ADD32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
@@ -47868,38 +47647,63 @@ SDNode *Select_X86ISD_ADD_i32(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_ADD_i64(const SDValue &N) {
-
- // Pattern: (X86add_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (ADD64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+SDNode *Select_X86ISD_ADD_i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::ADD64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86add_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (ADD64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi64(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::ADD64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86add_flag:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src1)
+ // Emits: (ADD64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadi64(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::ADD64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86add_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Emits: (ADD64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
@@ -47926,29 +47730,54 @@ SDNode *Select_X86ISD_ADD_i64(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_AND_i8(const SDValue &N) {
-
- // Pattern: (X86and_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
- // Emits: (AND8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+SDNode *Select_X86ISD_AND_i8(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi8(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::AND8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86and_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
+ // Emits: (AND8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi8(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::AND8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86and_flag:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src1)
+ // Emits: (AND8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadi8(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::AND8rm, MVT::i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -47959,9 +47788,9 @@ SDNode *Select_X86ISD_AND_i8(const SDValue &N) {
// Emits: (AND8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_3(N, X86::AND8ri, MVT::i8);
return Result;
}
@@ -47974,37 +47803,61 @@ SDNode *Select_X86ISD_AND_i8(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_AND_i16(const SDValue &N) {
-
- // Pattern: (X86and_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
- // Emits: (AND16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+SDNode *Select_X86ISD_AND_i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi16(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::AND16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86and_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
+ // Emits: (AND16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi16(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::AND16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86and_flag:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src1)
+ // Emits: (AND16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi16(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::AND16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86and_flag:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Emits: (AND16ri8:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
@@ -48029,37 +47882,61 @@ SDNode *Select_X86ISD_AND_i16(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_AND_i32(const SDValue &N) {
-
- // Pattern: (X86and_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (AND32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+SDNode *Select_X86ISD_AND_i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::AND32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86and_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (AND32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi32(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::AND32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86and_flag:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src1)
+ // Emits: (AND32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::AND32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86and_flag:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Emits: (AND32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
@@ -48084,38 +47961,63 @@ SDNode *Select_X86ISD_AND_i32(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_AND_i64(const SDValue &N) {
-
- // Pattern: (X86and_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (AND64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+SDNode *Select_X86ISD_AND_i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::AND64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86and_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (AND64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi64(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::AND64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86and_flag:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src1)
+ // Emits: (AND64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadi64(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::AND64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86and_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Emits: (AND64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
@@ -48142,23 +48044,23 @@ SDNode *Select_X86ISD_AND_i64(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_255(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_250(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EFLAGS, N3, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EFLAGS, N3, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, N1, Chain, InFlag);
-}
-SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BasicBlock) {
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, N1, Chain, InFlag);
+}
+SDNode *Select_X86ISD_BRCOND(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BasicBlock) {
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -48166,7 +48068,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JE:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_255(N, X86::JE);
+ SDNode *Result = Emit_250(N, X86::JE);
return Result;
}
@@ -48174,7 +48076,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JNE:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_255(N, X86::JNE);
+ SDNode *Result = Emit_250(N, X86::JNE);
return Result;
}
@@ -48182,7 +48084,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JL:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_255(N, X86::JL);
+ SDNode *Result = Emit_250(N, X86::JL);
return Result;
}
@@ -48190,7 +48092,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JLE:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_255(N, X86::JLE);
+ SDNode *Result = Emit_250(N, X86::JLE);
return Result;
}
@@ -48198,7 +48100,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JG:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_255(N, X86::JG);
+ SDNode *Result = Emit_250(N, X86::JG);
return Result;
}
@@ -48206,7 +48108,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JGE:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_255(N, X86::JGE);
+ SDNode *Result = Emit_250(N, X86::JGE);
return Result;
}
@@ -48214,7 +48116,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JB:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_255(N, X86::JB);
+ SDNode *Result = Emit_250(N, X86::JB);
return Result;
}
@@ -48222,7 +48124,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JBE:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_255(N, X86::JBE);
+ SDNode *Result = Emit_250(N, X86::JBE);
return Result;
}
@@ -48230,7 +48132,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JA:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_255(N, X86::JA);
+ SDNode *Result = Emit_250(N, X86::JA);
return Result;
}
@@ -48238,7 +48140,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JAE:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_255(N, X86::JAE);
+ SDNode *Result = Emit_250(N, X86::JAE);
return Result;
}
@@ -48246,7 +48148,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JS:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_255(N, X86::JS);
+ SDNode *Result = Emit_250(N, X86::JS);
return Result;
}
@@ -48254,7 +48156,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JNS:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_255(N, X86::JNS);
+ SDNode *Result = Emit_250(N, X86::JNS);
return Result;
}
@@ -48262,7 +48164,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JP:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_255(N, X86::JP);
+ SDNode *Result = Emit_250(N, X86::JP);
return Result;
}
@@ -48270,7 +48172,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JNP:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_255(N, X86::JNP);
+ SDNode *Result = Emit_250(N, X86::JNP);
return Result;
}
@@ -48278,7 +48180,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JO:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_255(N, X86::JO);
+ SDNode *Result = Emit_250(N, X86::JO);
return Result;
}
@@ -48286,7 +48188,7 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
// Emits: (JNO:isVoid (bb:Other):$dst)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_255(N, X86::JNO);
+ SDNode *Result = Emit_250(N, X86::JNO);
return Result;
}
}
@@ -48296,42 +48198,42 @@ SDNode *Select_X86ISD_BRCOND(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_256(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N0);
+DISABLE_INLINE SDNode *Emit_251(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N0);
}
-DISABLE_INLINE SDNode *Emit_257(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
+DISABLE_INLINE SDNode *Emit_252(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, MVT::Other, Ops0, 6);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 2));
return ResNode;
}
-SDNode *Select_X86ISD_BSF_i16(const SDValue &N) {
+SDNode *Select_X86ISD_BSF_i16(SDNode *N) {
// Pattern: (X86bsf:i16 (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
// Emits: (BSF16rm:i16 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_257(N, X86::BSF16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_252(N, X86::BSF16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48341,30 +48243,30 @@ SDNode *Select_X86ISD_BSF_i16(const SDValue &N) {
// Pattern: (X86bsf:i16 GR16:i16:$src)
// Emits: (BSF16rr:i16 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_256(N, X86::BSF16rr, MVT::i16);
+ SDNode *Result = Emit_251(N, X86::BSF16rr, MVT::i16);
return Result;
}
-SDNode *Select_X86ISD_BSF_i32(const SDValue &N) {
+SDNode *Select_X86ISD_BSF_i32(SDNode *N) {
// Pattern: (X86bsf:i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
// Emits: (BSF32rm:i32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_257(N, X86::BSF32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_252(N, X86::BSF32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48374,31 +48276,31 @@ SDNode *Select_X86ISD_BSF_i32(const SDValue &N) {
// Pattern: (X86bsf:i32 GR32:i32:$src)
// Emits: (BSF32rr:i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_256(N, X86::BSF32rr, MVT::i32);
+ SDNode *Result = Emit_251(N, X86::BSF32rr, MVT::i32);
return Result;
}
-SDNode *Select_X86ISD_BSF_i64(const SDValue &N) {
+SDNode *Select_X86ISD_BSF_i64(SDNode *N) {
// Pattern: (X86bsf:i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
// Emits: (BSF64rm:i64 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_257(N, X86::BSF64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_252(N, X86::BSF64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48408,30 +48310,30 @@ SDNode *Select_X86ISD_BSF_i64(const SDValue &N) {
// Pattern: (X86bsf:i64 GR64:i64:$src)
// Emits: (BSF64rr:i64 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_256(N, X86::BSF64rr, MVT::i64);
+ SDNode *Result = Emit_251(N, X86::BSF64rr, MVT::i64);
return Result;
}
-SDNode *Select_X86ISD_BSR_i16(const SDValue &N) {
+SDNode *Select_X86ISD_BSR_i16(SDNode *N) {
// Pattern: (X86bsr:i16 (ld:i16 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
// Emits: (BSR16rm:i16 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_257(N, X86::BSR16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_252(N, X86::BSR16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48441,30 +48343,30 @@ SDNode *Select_X86ISD_BSR_i16(const SDValue &N) {
// Pattern: (X86bsr:i16 GR16:i16:$src)
// Emits: (BSR16rr:i16 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_256(N, X86::BSR16rr, MVT::i16);
+ SDNode *Result = Emit_251(N, X86::BSR16rr, MVT::i16);
return Result;
}
-SDNode *Select_X86ISD_BSR_i32(const SDValue &N) {
+SDNode *Select_X86ISD_BSR_i32(SDNode *N) {
// Pattern: (X86bsr:i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
// Emits: (BSR32rm:i32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_257(N, X86::BSR32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_252(N, X86::BSR32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48474,31 +48376,31 @@ SDNode *Select_X86ISD_BSR_i32(const SDValue &N) {
// Pattern: (X86bsr:i32 GR32:i32:$src)
// Emits: (BSR32rr:i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_256(N, X86::BSR32rr, MVT::i32);
+ SDNode *Result = Emit_251(N, X86::BSR32rr, MVT::i32);
return Result;
}
-SDNode *Select_X86ISD_BSR_i64(const SDValue &N) {
+SDNode *Select_X86ISD_BSR_i64(SDNode *N) {
// Pattern: (X86bsr:i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
// Emits: (BSR64rm:i64 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_257(N, X86::BSR64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_252(N, X86::BSR64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48508,100 +48410,100 @@ SDNode *Select_X86ISD_BSR_i64(const SDValue &N) {
// Pattern: (X86bsr:i64 GR64:i64:$src)
// Emits: (BSR64rr:i64 GR64:i64:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_256(N, X86::BSR64rr, MVT::i64);
+ SDNode *Result = Emit_251(N, X86::BSR64rr, MVT::i64);
return Result;
}
-DISABLE_INLINE SDNode *Emit_258(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N0, N1);
+DISABLE_INLINE SDNode *Emit_253(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, N1);
}
-DISABLE_INLINE SDNode *Emit_259(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_254(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N0, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_260(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_255(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N0, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_261(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_256(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_262(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_257(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_263(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_258(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N0, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_264(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_259(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i64);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_X86ISD_BT(const SDValue &N) {
+SDNode *Select_X86ISD_BT(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode())) {
// Pattern: (X86bt:isVoid (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Emits: (BT16mi8:isVoid addr:iPTR:$src1, (imm:i16):$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_i16immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_261(N, X86::BT16mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_256(N, X86::BT16mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48611,18 +48513,18 @@ SDNode *Select_X86ISD_BT(const SDValue &N) {
// Emits: (BT32mi8:isVoid addr:iPTR:$src1, (imm:i32):$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_i32immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, X86::BT32mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_257(N, X86::BT32mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48633,18 +48535,18 @@ SDNode *Select_X86ISD_BT(const SDValue &N) {
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_load(N0.getNode()) &&
Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_i64immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_264(N, X86::BT64mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_259(N, X86::BT64mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -48652,16 +48554,16 @@ SDNode *Select_X86ISD_BT(const SDValue &N) {
}
}
}
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86bt:isVoid GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Emits: (BT16ri8:isVoid GR16:i16:$src1, (imm:i16):$src2)
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i16immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_259(N, X86::BT16ri8);
+ SDNode *Result = Emit_254(N, X86::BT16ri8);
return Result;
}
@@ -48670,7 +48572,7 @@ SDNode *Select_X86ISD_BT(const SDValue &N) {
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i32immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_260(N, X86::BT32ri8);
+ SDNode *Result = Emit_255(N, X86::BT32ri8);
return Result;
}
@@ -48679,7 +48581,7 @@ SDNode *Select_X86ISD_BT(const SDValue &N) {
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i64immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_263(N, X86::BT64ri8);
+ SDNode *Result = Emit_258(N, X86::BT64ri8);
return Result;
}
}
@@ -48688,7 +48590,7 @@ SDNode *Select_X86ISD_BT(const SDValue &N) {
// Emits: (BT16rr:isVoid GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_258(N, X86::BT16rr);
+ SDNode *Result = Emit_253(N, X86::BT16rr);
return Result;
}
@@ -48696,7 +48598,7 @@ SDNode *Select_X86ISD_BT(const SDValue &N) {
// Emits: (BT32rr:isVoid GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_258(N, X86::BT32rr);
+ SDNode *Result = Emit_253(N, X86::BT32rr);
return Result;
}
@@ -48704,7 +48606,7 @@ SDNode *Select_X86ISD_BT(const SDValue &N) {
// Emits: (BT64rr:isVoid GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_258(N, X86::BT64rr);
+ SDNode *Result = Emit_253(N, X86::BT64rr);
return Result;
}
@@ -48712,28 +48614,28 @@ SDNode *Select_X86ISD_BT(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_265(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_260(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SmallVector<SDValue, 8> Ops0;
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
Ops0.push_back(N1);
- for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N.getOperand(i));
+ for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N->getOperand(i));
}
Ops0.push_back(Chain);
if (HasInFlag)
Ops0.push_back(InFlag);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -48742,44 +48644,44 @@ DISABLE_INLINE SDNode *Emit_265(const SDValue &N, unsigned Opc0, unsigned NumInp
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_266(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4, unsigned NumInputRootOps) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_261(SDNode *N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4, unsigned NumInputRootOps) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SmallVector<SDValue, 8> Ops0;
SmallVector<SDValue, 8> InChains;
if (Chain.getNode() != N1.getNode()) {
InChains.push_back(Chain);
}
InChains.push_back(Chain1);
- Chain1 = CurDAG->getNode(ISD::TokenFactor, N.getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
+ Chain1 = CurDAG->getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, &InChains[0], InChains.size());
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
Ops0.push_back(CPTmpN11_0);
Ops0.push_back(CPTmpN11_1);
Ops0.push_back(CPTmpN11_2);
Ops0.push_back(CPTmpN11_3);
Ops0.push_back(CPTmpN11_4);
- for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N.getOperand(i));
+ for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N->getOperand(i));
}
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
Ops0.push_back(Chain1);
if (HasInFlag)
Ops0.push_back(InFlag);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
Chain1 = SDValue(ResNode, 0);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
SDValue(N1.getNode(), 1),
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
SDValue(ResNode, 0),
@@ -48789,29 +48691,29 @@ DISABLE_INLINE SDNode *Emit_266(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 3);
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_267(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_262(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SmallVector<SDValue, 8> Ops0;
SDValue Tmp0 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
Ops0.push_back(Tmp0);
- for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N.getOperand(i));
+ for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N->getOperand(i));
}
Ops0.push_back(Chain);
if (HasInFlag)
Ops0.push_back(InFlag);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, &Ops0[0], Ops0.size());
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -48820,22 +48722,22 @@ DISABLE_INLINE SDNode *Emit_267(const SDValue &N, unsigned Opc0, unsigned NumInp
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_X86ISD_CALL(const SDValue &N) {
+SDNode *Select_X86ISD_CALL(SDNode *N) {
// Pattern: (X86call:isVoid (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
// Emits: (CALL32m:isVoid addr:iPTR:$dst)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N) &&
(Chain.getNode() == N1.getNode() || IsChainCompatible(Chain.getNode(), N1.getNode()))) {
- SDValue Chain1 = N1.getOperand(0);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -48843,7 +48745,7 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_266(N, X86::CALL32m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
+ SDNode *Result = Emit_261(N, X86::CALL32m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
return Result;
}
}
@@ -48854,17 +48756,17 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
// Emits: (CALL64m:isVoid addr:iPTR:$dst)
// Pattern complexity = 25 cost = 1 size = 3
if ((!Subtarget->isTargetWin64())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N) &&
(Chain.getNode() == N1.getNode() || IsChainCompatible(Chain.getNode(), N1.getNode()))) {
- SDValue Chain1 = N1.getOperand(0);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -48872,7 +48774,7 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_266(N, X86::CALL64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
+ SDNode *Result = Emit_261(N, X86::CALL64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
return Result;
}
}
@@ -48883,17 +48785,17 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
// Emits: (WINCALL64m:isVoid addr:iPTR:$dst)
// Pattern complexity = 25 cost = 1 size = 3
if ((Subtarget->isTargetWin64())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode()) &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N) &&
(Chain.getNode() == N1.getNode() || IsChainCompatible(Chain.getNode(), N1.getNode()))) {
- SDValue Chain1 = N1.getOperand(0);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -48901,75 +48803,75 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_266(N, X86::WINCALL64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
+ SDNode *Result = Emit_261(N, X86::WINCALL64m, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, 1);
return Result;
}
}
}
}
if ((!Subtarget->isTargetWin64())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (X86call:isVoid (tglobaladdr:i64):$dst)
// Emits: (CALL64pcrel32:isVoid (tglobaladdr:i64):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::TargetGlobalAddress &&
+ if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_265(N, X86::CALL64pcrel32, 1);
+ SDNode *Result = Emit_260(N, X86::CALL64pcrel32, 1);
return Result;
}
// Pattern: (X86call:isVoid (texternalsym:i64):$dst)
// Emits: (CALL64pcrel32:isVoid (texternalsym:i64):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::TargetExternalSymbol &&
+ if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_265(N, X86::CALL64pcrel32, 1);
+ SDNode *Result = Emit_260(N, X86::CALL64pcrel32, 1);
return Result;
}
}
if ((Subtarget->isTargetWin64())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (X86call:isVoid (tglobaladdr:i64):$dst)
// Emits: (WINCALL64pcrel32:isVoid (tglobaladdr:i64):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::TargetGlobalAddress &&
+ if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_265(N, X86::WINCALL64pcrel32, 1);
+ SDNode *Result = Emit_260(N, X86::WINCALL64pcrel32, 1);
return Result;
}
// Pattern: (X86call:isVoid (texternalsym:i64):$dst)
// Emits: (WINCALL64pcrel32:isVoid (texternalsym:i64):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::TargetExternalSymbol &&
+ if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_265(N, X86::WINCALL64pcrel32, 1);
+ SDNode *Result = Emit_260(N, X86::WINCALL64pcrel32, 1);
return Result;
}
}
{
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (X86call:isVoid (tglobaladdr:i32):$dst)
// Emits: (CALLpcrel32:isVoid (tglobaladdr:i32):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::TargetGlobalAddress &&
+ if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_265(N, X86::CALLpcrel32, 1);
+ SDNode *Result = Emit_260(N, X86::CALLpcrel32, 1);
return Result;
}
// Pattern: (X86call:isVoid (texternalsym:i32):$dst)
// Emits: (CALLpcrel32:isVoid (texternalsym:i32):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::TargetExternalSymbol &&
+ if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_265(N, X86::CALLpcrel32, 1);
+ SDNode *Result = Emit_260(N, X86::CALLpcrel32, 1);
return Result;
}
}
@@ -48978,11 +48880,11 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
// Emits: (CALLpcrel32:isVoid (imm:i32):$dst)
// Pattern complexity = 6 cost = 1 size = 3
if ((Subtarget->IsLegalToCallImmediateAddr(TM))) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_267(N, X86::CALLpcrel32, 1);
+ SDNode *Result = Emit_262(N, X86::CALLpcrel32, 1);
return Result;
}
}
@@ -48991,10 +48893,10 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
// Emits: (CALL32r:isVoid GR32:i32:$dst)
// Pattern complexity = 3 cost = 1 size = 3
{
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_265(N, X86::CALL32r, 1);
+ SDNode *Result = Emit_260(N, X86::CALL32r, 1);
return Result;
}
}
@@ -49003,10 +48905,10 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
// Emits: (CALL64r:isVoid GR64:i64:$dst)
// Pattern complexity = 3 cost = 1 size = 3
if ((!Subtarget->isTargetWin64())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_265(N, X86::CALL64r, 1);
+ SDNode *Result = Emit_260(N, X86::CALL64r, 1);
return Result;
}
}
@@ -49015,10 +48917,10 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
// Emits: (WINCALL64r:isVoid GR64:i64:$dst)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->isTargetWin64())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_265(N, X86::WINCALL64r, 1);
+ SDNode *Result = Emit_260(N, X86::WINCALL64r, 1);
return Result;
}
}
@@ -49027,26 +48929,26 @@ SDNode *Select_X86ISD_CALL(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_268(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_263(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i8);
SDValue Chain = CurDAG->getEntryNode();
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EFLAGS, N3, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EFLAGS, N3, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
SDValue Ops0[] = { N0, N1, Tmp2, InFlag };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, Ops0, 4);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, Ops0, 4);
}
-SDNode *Select_X86ISD_CMOV_i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_268(N, X86::CMOV_GR8, MVT::i8);
+SDNode *Select_X86ISD_CMOV_i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_263(N, X86::CMOV_GR8, MVT::i8);
return Result;
}
@@ -49054,76 +48956,76 @@ SDNode *Select_X86ISD_CMOV_i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_269(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_264(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue Chain = CurDAG->getEntryNode();
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EFLAGS, N3, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EFLAGS, N3, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, InFlag);
-}
-DISABLE_INLINE SDNode *Emit_270(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, InFlag);
+}
+DISABLE_INLINE SDNode *Emit_265(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain1, N.getDebugLoc(), X86::EFLAGS, N3, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain1, N->getDebugLoc(), X86::EFLAGS, N3, InFlag).getNode();
Chain1 = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1, InFlag };
- ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_271(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_266(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain0, N.getDebugLoc(), X86::EFLAGS, N3, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain0, N->getDebugLoc(), X86::EFLAGS, N3, InFlag).getNode();
Chain0 = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { N1, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Chain0, InFlag };
- ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
+SDNode *Select_X86ISD_CMOV_i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_loadi16(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -49131,7 +49033,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_270(N, X86::CMOVB16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVB16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49139,7 +49041,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVAE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_270(N, X86::CMOVAE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVAE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49147,7 +49049,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_270(N, X86::CMOVE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49155,7 +49057,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_270(N, X86::CMOVNE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVNE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49163,7 +49065,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVBE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_270(N, X86::CMOVBE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVBE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49171,7 +49073,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVA16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_270(N, X86::CMOVA16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVA16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49179,7 +49081,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVL16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_270(N, X86::CMOVL16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVL16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49187,7 +49089,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVGE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_270(N, X86::CMOVGE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVGE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49195,7 +49097,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVLE16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_270(N, X86::CMOVLE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVLE16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49203,7 +49105,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVG16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_270(N, X86::CMOVG16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVG16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49211,7 +49113,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVS16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_270(N, X86::CMOVS16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVS16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49219,7 +49121,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNS16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_270(N, X86::CMOVNS16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVNS16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49227,7 +49129,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVP16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_270(N, X86::CMOVP16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVP16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49235,7 +49137,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNP16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_270(N, X86::CMOVNP16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVNP16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49243,7 +49145,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVO16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_270(N, X86::CMOVO16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVO16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49251,7 +49153,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNO16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_270(N, X86::CMOVNO16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVNO16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -49259,22 +49161,22 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -49282,7 +49184,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVL16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_271(N, X86::CMOVL16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVL16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49290,7 +49192,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVG16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_271(N, X86::CMOVG16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVG16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49298,7 +49200,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVLE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_271(N, X86::CMOVLE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVLE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49306,7 +49208,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNP16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_271(N, X86::CMOVNP16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVNP16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49314,7 +49216,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVP16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_271(N, X86::CMOVP16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVP16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49322,7 +49224,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNS16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_271(N, X86::CMOVNS16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVNS16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49330,7 +49232,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVS16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_271(N, X86::CMOVS16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVS16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49338,7 +49240,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNO16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_271(N, X86::CMOVNO16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVNO16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49346,7 +49248,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVO16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_271(N, X86::CMOVO16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVO16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49354,7 +49256,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVAE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_271(N, X86::CMOVAE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVAE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49362,7 +49264,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVB16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_271(N, X86::CMOVB16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVB16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49370,7 +49272,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_271(N, X86::CMOVNE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVNE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49378,7 +49280,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_271(N, X86::CMOVE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49386,7 +49288,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVA16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_271(N, X86::CMOVA16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVA16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49394,7 +49296,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVBE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_271(N, X86::CMOVBE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVBE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49402,7 +49304,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVGE16rm:i16 GR16:i16:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_271(N, X86::CMOVGE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVGE16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -49410,10 +49312,10 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
}
}
}
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -49421,7 +49323,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVB16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_269(N, X86::CMOVB16rr, MVT::i16);
+ SDNode *Result = Emit_264(N, X86::CMOVB16rr, MVT::i16);
return Result;
}
@@ -49429,7 +49331,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVAE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_269(N, X86::CMOVAE16rr, MVT::i16);
+ SDNode *Result = Emit_264(N, X86::CMOVAE16rr, MVT::i16);
return Result;
}
@@ -49437,7 +49339,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_269(N, X86::CMOVE16rr, MVT::i16);
+ SDNode *Result = Emit_264(N, X86::CMOVE16rr, MVT::i16);
return Result;
}
@@ -49445,7 +49347,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_269(N, X86::CMOVNE16rr, MVT::i16);
+ SDNode *Result = Emit_264(N, X86::CMOVNE16rr, MVT::i16);
return Result;
}
@@ -49453,7 +49355,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVBE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_269(N, X86::CMOVBE16rr, MVT::i16);
+ SDNode *Result = Emit_264(N, X86::CMOVBE16rr, MVT::i16);
return Result;
}
@@ -49461,7 +49363,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVA16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_269(N, X86::CMOVA16rr, MVT::i16);
+ SDNode *Result = Emit_264(N, X86::CMOVA16rr, MVT::i16);
return Result;
}
@@ -49469,7 +49371,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVL16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_269(N, X86::CMOVL16rr, MVT::i16);
+ SDNode *Result = Emit_264(N, X86::CMOVL16rr, MVT::i16);
return Result;
}
@@ -49477,7 +49379,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVGE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_269(N, X86::CMOVGE16rr, MVT::i16);
+ SDNode *Result = Emit_264(N, X86::CMOVGE16rr, MVT::i16);
return Result;
}
@@ -49485,7 +49387,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVLE16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_269(N, X86::CMOVLE16rr, MVT::i16);
+ SDNode *Result = Emit_264(N, X86::CMOVLE16rr, MVT::i16);
return Result;
}
@@ -49493,7 +49395,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVG16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_269(N, X86::CMOVG16rr, MVT::i16);
+ SDNode *Result = Emit_264(N, X86::CMOVG16rr, MVT::i16);
return Result;
}
@@ -49501,7 +49403,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVS16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_269(N, X86::CMOVS16rr, MVT::i16);
+ SDNode *Result = Emit_264(N, X86::CMOVS16rr, MVT::i16);
return Result;
}
@@ -49509,7 +49411,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNS16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_269(N, X86::CMOVNS16rr, MVT::i16);
+ SDNode *Result = Emit_264(N, X86::CMOVNS16rr, MVT::i16);
return Result;
}
@@ -49517,7 +49419,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVP16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_269(N, X86::CMOVP16rr, MVT::i16);
+ SDNode *Result = Emit_264(N, X86::CMOVP16rr, MVT::i16);
return Result;
}
@@ -49525,7 +49427,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNP16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_269(N, X86::CMOVNP16rr, MVT::i16);
+ SDNode *Result = Emit_264(N, X86::CMOVNP16rr, MVT::i16);
return Result;
}
@@ -49533,7 +49435,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVO16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_269(N, X86::CMOVO16rr, MVT::i16);
+ SDNode *Result = Emit_264(N, X86::CMOVO16rr, MVT::i16);
return Result;
}
@@ -49541,7 +49443,7 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
// Emits: (CMOVNO16rr:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_269(N, X86::CMOVNO16rr, MVT::i16);
+ SDNode *Result = Emit_264(N, X86::CMOVNO16rr, MVT::i16);
return Result;
}
}
@@ -49550,26 +49452,26 @@ SDNode *Select_X86ISD_CMOV_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
+SDNode *Select_X86ISD_CMOV_i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -49577,7 +49479,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_270(N, X86::CMOVB32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVB32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49585,7 +49487,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVAE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_270(N, X86::CMOVAE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVAE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49593,7 +49495,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_270(N, X86::CMOVE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49601,7 +49503,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_270(N, X86::CMOVNE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVNE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49609,7 +49511,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVBE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_270(N, X86::CMOVBE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVBE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49617,7 +49519,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVA32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_270(N, X86::CMOVA32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVA32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49625,7 +49527,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVL32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_270(N, X86::CMOVL32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVL32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49633,7 +49535,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVGE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_270(N, X86::CMOVGE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVGE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49641,7 +49543,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVLE32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_270(N, X86::CMOVLE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVLE32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49649,7 +49551,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVG32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_270(N, X86::CMOVG32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVG32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49657,7 +49559,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVS32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_270(N, X86::CMOVS32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVS32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49665,7 +49567,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNS32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_270(N, X86::CMOVNS32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVNS32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49673,7 +49575,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVP32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_270(N, X86::CMOVP32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVP32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49681,7 +49583,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNP32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_270(N, X86::CMOVNP32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVNP32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49689,7 +49591,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVO32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_270(N, X86::CMOVO32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVO32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -49697,7 +49599,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNO32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_270(N, X86::CMOVNO32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVNO32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -49705,38 +49607,30 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
- // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 7:i8, EFLAGS:i32)
- // Emits: (CMOVGE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
- // Pattern complexity = 30 cost = 1 size = 3
- if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_271(N, X86::CMOVGE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
- return Result;
- }
-
// Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 6:i8, EFLAGS:i32)
// Emits: (CMOVL32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_271(N, X86::CMOVL32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVL32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49744,7 +49638,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVG32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_271(N, X86::CMOVG32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVG32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49752,7 +49646,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVLE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_271(N, X86::CMOVLE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVLE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49760,7 +49654,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNP32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_271(N, X86::CMOVNP32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVNP32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49768,7 +49662,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVP32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_271(N, X86::CMOVP32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVP32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49776,7 +49670,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNS32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_271(N, X86::CMOVNS32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVNS32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49784,7 +49678,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVS32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_271(N, X86::CMOVS32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVS32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49792,7 +49686,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNO32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_271(N, X86::CMOVNO32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVNO32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49800,7 +49694,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVO32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_271(N, X86::CMOVO32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVO32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49808,7 +49702,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVAE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_271(N, X86::CMOVAE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVAE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49816,7 +49710,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVB32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_271(N, X86::CMOVB32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVB32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49824,7 +49718,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_271(N, X86::CMOVNE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVNE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49832,7 +49726,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_271(N, X86::CMOVE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49840,7 +49734,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVA32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_271(N, X86::CMOVA32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVA32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -49848,7 +49742,15 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVBE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_271(N, X86::CMOVBE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVBE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+
+ // Pattern: (X86cmov:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src2, 7:i8, EFLAGS:i32)
+ // Emits: (CMOVGE32rm:i32 GR32:i32:$src2, addr:iPTR:$src1)
+ // Pattern complexity = 30 cost = 1 size = 3
+ if (CN1 == INT64_C(7)) {
+ SDNode *Result = Emit_266(N, X86::CMOVGE32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -49856,10 +49758,10 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
}
}
}
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -49867,7 +49769,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVB32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_269(N, X86::CMOVB32rr, MVT::i32);
+ SDNode *Result = Emit_264(N, X86::CMOVB32rr, MVT::i32);
return Result;
}
@@ -49875,7 +49777,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVAE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_269(N, X86::CMOVAE32rr, MVT::i32);
+ SDNode *Result = Emit_264(N, X86::CMOVAE32rr, MVT::i32);
return Result;
}
@@ -49883,7 +49785,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_269(N, X86::CMOVE32rr, MVT::i32);
+ SDNode *Result = Emit_264(N, X86::CMOVE32rr, MVT::i32);
return Result;
}
@@ -49891,7 +49793,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_269(N, X86::CMOVNE32rr, MVT::i32);
+ SDNode *Result = Emit_264(N, X86::CMOVNE32rr, MVT::i32);
return Result;
}
@@ -49899,7 +49801,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVBE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_269(N, X86::CMOVBE32rr, MVT::i32);
+ SDNode *Result = Emit_264(N, X86::CMOVBE32rr, MVT::i32);
return Result;
}
@@ -49907,7 +49809,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVA32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_269(N, X86::CMOVA32rr, MVT::i32);
+ SDNode *Result = Emit_264(N, X86::CMOVA32rr, MVT::i32);
return Result;
}
@@ -49915,7 +49817,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVL32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_269(N, X86::CMOVL32rr, MVT::i32);
+ SDNode *Result = Emit_264(N, X86::CMOVL32rr, MVT::i32);
return Result;
}
@@ -49923,7 +49825,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVGE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_269(N, X86::CMOVGE32rr, MVT::i32);
+ SDNode *Result = Emit_264(N, X86::CMOVGE32rr, MVT::i32);
return Result;
}
@@ -49931,7 +49833,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVLE32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_269(N, X86::CMOVLE32rr, MVT::i32);
+ SDNode *Result = Emit_264(N, X86::CMOVLE32rr, MVT::i32);
return Result;
}
@@ -49939,7 +49841,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVG32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_269(N, X86::CMOVG32rr, MVT::i32);
+ SDNode *Result = Emit_264(N, X86::CMOVG32rr, MVT::i32);
return Result;
}
@@ -49947,7 +49849,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVS32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_269(N, X86::CMOVS32rr, MVT::i32);
+ SDNode *Result = Emit_264(N, X86::CMOVS32rr, MVT::i32);
return Result;
}
@@ -49955,7 +49857,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNS32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_269(N, X86::CMOVNS32rr, MVT::i32);
+ SDNode *Result = Emit_264(N, X86::CMOVNS32rr, MVT::i32);
return Result;
}
@@ -49963,7 +49865,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVP32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_269(N, X86::CMOVP32rr, MVT::i32);
+ SDNode *Result = Emit_264(N, X86::CMOVP32rr, MVT::i32);
return Result;
}
@@ -49971,7 +49873,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNP32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_269(N, X86::CMOVNP32rr, MVT::i32);
+ SDNode *Result = Emit_264(N, X86::CMOVNP32rr, MVT::i32);
return Result;
}
@@ -49979,7 +49881,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVO32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_269(N, X86::CMOVO32rr, MVT::i32);
+ SDNode *Result = Emit_264(N, X86::CMOVO32rr, MVT::i32);
return Result;
}
@@ -49987,7 +49889,7 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
// Emits: (CMOVNO32rr:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_269(N, X86::CMOVNO32rr, MVT::i32);
+ SDNode *Result = Emit_264(N, X86::CMOVNO32rr, MVT::i32);
return Result;
}
}
@@ -49996,27 +49898,27 @@ SDNode *Select_X86ISD_CMOV_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
+SDNode *Select_X86ISD_CMOV_i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -50024,7 +49926,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_270(N, X86::CMOVB64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVB64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50032,7 +49934,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVAE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_270(N, X86::CMOVAE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVAE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50040,7 +49942,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_270(N, X86::CMOVE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50048,7 +49950,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_270(N, X86::CMOVNE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVNE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50056,7 +49958,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVBE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_270(N, X86::CMOVBE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVBE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50064,7 +49966,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVA64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_270(N, X86::CMOVA64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVA64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50072,7 +49974,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVL64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_270(N, X86::CMOVL64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVL64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50080,7 +49982,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVGE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_270(N, X86::CMOVGE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVGE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50088,7 +49990,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVLE64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_270(N, X86::CMOVLE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVLE64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50096,7 +49998,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVG64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_270(N, X86::CMOVG64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVG64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50104,7 +50006,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVS64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_270(N, X86::CMOVS64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVS64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50112,7 +50014,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNS64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_270(N, X86::CMOVNS64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVNS64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50120,7 +50022,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVP64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_270(N, X86::CMOVP64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVP64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50128,7 +50030,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNP64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_270(N, X86::CMOVNP64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVNP64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50136,7 +50038,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVO64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_270(N, X86::CMOVO64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVO64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
@@ -50144,7 +50046,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNO64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_270(N, X86::CMOVNO64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_265(N, X86::CMOVNO64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -50152,23 +50054,23 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -50176,7 +50078,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVAE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_271(N, X86::CMOVAE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVAE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50184,7 +50086,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVB64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_271(N, X86::CMOVB64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVB64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50192,7 +50094,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_271(N, X86::CMOVNE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVNE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50200,7 +50102,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_271(N, X86::CMOVE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50208,7 +50110,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVA64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_271(N, X86::CMOVA64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVA64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50216,7 +50118,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVBE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_271(N, X86::CMOVBE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVBE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50224,7 +50126,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVGE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_271(N, X86::CMOVGE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVGE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50232,7 +50134,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVL64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_271(N, X86::CMOVL64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVL64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50240,7 +50142,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVG64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_271(N, X86::CMOVG64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVG64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50248,7 +50150,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVLE64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_271(N, X86::CMOVLE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVLE64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50256,7 +50158,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNP64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_271(N, X86::CMOVNP64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVNP64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50264,7 +50166,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVP64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_271(N, X86::CMOVP64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVP64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50272,7 +50174,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNS64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_271(N, X86::CMOVNS64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVNS64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50280,7 +50182,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVS64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_271(N, X86::CMOVS64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVS64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50288,7 +50190,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNO64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_271(N, X86::CMOVNO64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVNO64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -50296,7 +50198,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVO64rm:i64 GR64:i64:$src2, addr:iPTR:$src1)
// Pattern complexity = 30 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_271(N, X86::CMOVO64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_266(N, X86::CMOVO64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -50304,10 +50206,10 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
}
}
}
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -50315,7 +50217,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVB64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_269(N, X86::CMOVB64rr, MVT::i64);
+ SDNode *Result = Emit_264(N, X86::CMOVB64rr, MVT::i64);
return Result;
}
@@ -50323,7 +50225,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVAE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_269(N, X86::CMOVAE64rr, MVT::i64);
+ SDNode *Result = Emit_264(N, X86::CMOVAE64rr, MVT::i64);
return Result;
}
@@ -50331,7 +50233,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_269(N, X86::CMOVE64rr, MVT::i64);
+ SDNode *Result = Emit_264(N, X86::CMOVE64rr, MVT::i64);
return Result;
}
@@ -50339,7 +50241,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_269(N, X86::CMOVNE64rr, MVT::i64);
+ SDNode *Result = Emit_264(N, X86::CMOVNE64rr, MVT::i64);
return Result;
}
@@ -50347,7 +50249,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVBE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_269(N, X86::CMOVBE64rr, MVT::i64);
+ SDNode *Result = Emit_264(N, X86::CMOVBE64rr, MVT::i64);
return Result;
}
@@ -50355,7 +50257,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVA64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_269(N, X86::CMOVA64rr, MVT::i64);
+ SDNode *Result = Emit_264(N, X86::CMOVA64rr, MVT::i64);
return Result;
}
@@ -50363,7 +50265,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVL64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_269(N, X86::CMOVL64rr, MVT::i64);
+ SDNode *Result = Emit_264(N, X86::CMOVL64rr, MVT::i64);
return Result;
}
@@ -50371,7 +50273,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVGE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_269(N, X86::CMOVGE64rr, MVT::i64);
+ SDNode *Result = Emit_264(N, X86::CMOVGE64rr, MVT::i64);
return Result;
}
@@ -50379,7 +50281,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVLE64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_269(N, X86::CMOVLE64rr, MVT::i64);
+ SDNode *Result = Emit_264(N, X86::CMOVLE64rr, MVT::i64);
return Result;
}
@@ -50387,7 +50289,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVG64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_269(N, X86::CMOVG64rr, MVT::i64);
+ SDNode *Result = Emit_264(N, X86::CMOVG64rr, MVT::i64);
return Result;
}
@@ -50395,7 +50297,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVS64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_269(N, X86::CMOVS64rr, MVT::i64);
+ SDNode *Result = Emit_264(N, X86::CMOVS64rr, MVT::i64);
return Result;
}
@@ -50403,7 +50305,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNS64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_269(N, X86::CMOVNS64rr, MVT::i64);
+ SDNode *Result = Emit_264(N, X86::CMOVNS64rr, MVT::i64);
return Result;
}
@@ -50411,7 +50313,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVP64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_269(N, X86::CMOVP64rr, MVT::i64);
+ SDNode *Result = Emit_264(N, X86::CMOVP64rr, MVT::i64);
return Result;
}
@@ -50419,7 +50321,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNP64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_269(N, X86::CMOVNP64rr, MVT::i64);
+ SDNode *Result = Emit_264(N, X86::CMOVNP64rr, MVT::i64);
return Result;
}
@@ -50427,7 +50329,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVO64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_269(N, X86::CMOVO64rr, MVT::i64);
+ SDNode *Result = Emit_264(N, X86::CMOVO64rr, MVT::i64);
return Result;
}
@@ -50435,7 +50337,7 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
// Emits: (CMOVNO64rr:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_269(N, X86::CMOVNO64rr, MVT::i64);
+ SDNode *Result = Emit_264(N, X86::CMOVNO64rr, MVT::i64);
return Result;
}
}
@@ -50444,12 +50346,12 @@ SDNode *Select_X86ISD_CMOV_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
+SDNode *Select_X86ISD_CMOV_f32(SDNode *N) {
if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -50457,7 +50359,7 @@ SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
// Emits: (CMOVB_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_269(N, X86::CMOVB_Fp32, MVT::f32);
+ SDNode *Result = Emit_264(N, X86::CMOVB_Fp32, MVT::f32);
return Result;
}
@@ -50465,7 +50367,7 @@ SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
// Emits: (CMOVBE_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_269(N, X86::CMOVBE_Fp32, MVT::f32);
+ SDNode *Result = Emit_264(N, X86::CMOVBE_Fp32, MVT::f32);
return Result;
}
@@ -50473,7 +50375,7 @@ SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
// Emits: (CMOVE_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_269(N, X86::CMOVE_Fp32, MVT::f32);
+ SDNode *Result = Emit_264(N, X86::CMOVE_Fp32, MVT::f32);
return Result;
}
@@ -50481,7 +50383,7 @@ SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
// Emits: (CMOVP_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_269(N, X86::CMOVP_Fp32, MVT::f32);
+ SDNode *Result = Emit_264(N, X86::CMOVP_Fp32, MVT::f32);
return Result;
}
@@ -50489,7 +50391,7 @@ SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
// Emits: (CMOVNB_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_269(N, X86::CMOVNB_Fp32, MVT::f32);
+ SDNode *Result = Emit_264(N, X86::CMOVNB_Fp32, MVT::f32);
return Result;
}
@@ -50497,7 +50399,7 @@ SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
// Emits: (CMOVNBE_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_269(N, X86::CMOVNBE_Fp32, MVT::f32);
+ SDNode *Result = Emit_264(N, X86::CMOVNBE_Fp32, MVT::f32);
return Result;
}
@@ -50505,7 +50407,7 @@ SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
// Emits: (CMOVNE_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_269(N, X86::CMOVNE_Fp32, MVT::f32);
+ SDNode *Result = Emit_264(N, X86::CMOVNE_Fp32, MVT::f32);
return Result;
}
@@ -50513,7 +50415,7 @@ SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
// Emits: (CMOVNP_Fp32:f32 RFP32:f32:$src1, RFP32:f32:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_269(N, X86::CMOVNP_Fp32, MVT::f32);
+ SDNode *Result = Emit_264(N, X86::CMOVNP_Fp32, MVT::f32);
return Result;
}
}
@@ -50522,11 +50424,11 @@ SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
// Pattern: (X86cmov:f32 FR32:f32:$t, FR32:f32:$f, (imm:i8):$cond, EFLAGS:i32)
// Emits: (CMOV_FR32:f32 FR32:f32:$t, FR32:f32:$f, (imm:i8):$cond)
// Pattern complexity = 6 cost = 11 size = 3
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_268(N, X86::CMOV_FR32, MVT::f32);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_263(N, X86::CMOV_FR32, MVT::f32);
return Result;
}
@@ -50534,12 +50436,12 @@ SDNode *Select_X86ISD_CMOV_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
+SDNode *Select_X86ISD_CMOV_f64(SDNode *N) {
if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -50547,7 +50449,7 @@ SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
// Emits: (CMOVB_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_269(N, X86::CMOVB_Fp64, MVT::f64);
+ SDNode *Result = Emit_264(N, X86::CMOVB_Fp64, MVT::f64);
return Result;
}
@@ -50555,7 +50457,7 @@ SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
// Emits: (CMOVBE_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_269(N, X86::CMOVBE_Fp64, MVT::f64);
+ SDNode *Result = Emit_264(N, X86::CMOVBE_Fp64, MVT::f64);
return Result;
}
@@ -50563,7 +50465,7 @@ SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
// Emits: (CMOVE_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_269(N, X86::CMOVE_Fp64, MVT::f64);
+ SDNode *Result = Emit_264(N, X86::CMOVE_Fp64, MVT::f64);
return Result;
}
@@ -50571,7 +50473,7 @@ SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
// Emits: (CMOVP_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_269(N, X86::CMOVP_Fp64, MVT::f64);
+ SDNode *Result = Emit_264(N, X86::CMOVP_Fp64, MVT::f64);
return Result;
}
@@ -50579,7 +50481,7 @@ SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
// Emits: (CMOVNB_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_269(N, X86::CMOVNB_Fp64, MVT::f64);
+ SDNode *Result = Emit_264(N, X86::CMOVNB_Fp64, MVT::f64);
return Result;
}
@@ -50587,7 +50489,7 @@ SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
// Emits: (CMOVNBE_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_269(N, X86::CMOVNBE_Fp64, MVT::f64);
+ SDNode *Result = Emit_264(N, X86::CMOVNBE_Fp64, MVT::f64);
return Result;
}
@@ -50595,7 +50497,7 @@ SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
// Emits: (CMOVNE_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_269(N, X86::CMOVNE_Fp64, MVT::f64);
+ SDNode *Result = Emit_264(N, X86::CMOVNE_Fp64, MVT::f64);
return Result;
}
@@ -50603,7 +50505,7 @@ SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
// Emits: (CMOVNP_Fp64:f64 RFP64:f64:$src1, RFP64:f64:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_269(N, X86::CMOVNP_Fp64, MVT::f64);
+ SDNode *Result = Emit_264(N, X86::CMOVNP_Fp64, MVT::f64);
return Result;
}
}
@@ -50612,11 +50514,11 @@ SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
// Pattern: (X86cmov:f64 FR64:f64:$t, FR64:f64:$f, (imm:i8):$cond, EFLAGS:i32)
// Emits: (CMOV_FR64:f64 FR64:f64:$t, FR64:f64:$f, (imm:i8):$cond)
// Pattern complexity = 6 cost = 11 size = 3
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_268(N, X86::CMOV_FR64, MVT::f64);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_263(N, X86::CMOV_FR64, MVT::f64);
return Result;
}
@@ -50624,11 +50526,11 @@ SDNode *Select_X86ISD_CMOV_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_CMOV_f80(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2);
+SDNode *Select_X86ISD_CMOV_f80(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N2.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -50636,7 +50538,7 @@ SDNode *Select_X86ISD_CMOV_f80(const SDValue &N) {
// Emits: (CMOVB_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_269(N, X86::CMOVB_Fp80, MVT::f80);
+ SDNode *Result = Emit_264(N, X86::CMOVB_Fp80, MVT::f80);
return Result;
}
@@ -50644,7 +50546,7 @@ SDNode *Select_X86ISD_CMOV_f80(const SDValue &N) {
// Emits: (CMOVBE_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_269(N, X86::CMOVBE_Fp80, MVT::f80);
+ SDNode *Result = Emit_264(N, X86::CMOVBE_Fp80, MVT::f80);
return Result;
}
@@ -50652,7 +50554,7 @@ SDNode *Select_X86ISD_CMOV_f80(const SDValue &N) {
// Emits: (CMOVE_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_269(N, X86::CMOVE_Fp80, MVT::f80);
+ SDNode *Result = Emit_264(N, X86::CMOVE_Fp80, MVT::f80);
return Result;
}
@@ -50660,7 +50562,7 @@ SDNode *Select_X86ISD_CMOV_f80(const SDValue &N) {
// Emits: (CMOVP_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_269(N, X86::CMOVP_Fp80, MVT::f80);
+ SDNode *Result = Emit_264(N, X86::CMOVP_Fp80, MVT::f80);
return Result;
}
@@ -50668,7 +50570,7 @@ SDNode *Select_X86ISD_CMOV_f80(const SDValue &N) {
// Emits: (CMOVNB_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_269(N, X86::CMOVNB_Fp80, MVT::f80);
+ SDNode *Result = Emit_264(N, X86::CMOVNB_Fp80, MVT::f80);
return Result;
}
@@ -50676,7 +50578,7 @@ SDNode *Select_X86ISD_CMOV_f80(const SDValue &N) {
// Emits: (CMOVNBE_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_269(N, X86::CMOVNBE_Fp80, MVT::f80);
+ SDNode *Result = Emit_264(N, X86::CMOVNBE_Fp80, MVT::f80);
return Result;
}
@@ -50684,7 +50586,7 @@ SDNode *Select_X86ISD_CMOV_f80(const SDValue &N) {
// Emits: (CMOVNE_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_269(N, X86::CMOVNE_Fp80, MVT::f80);
+ SDNode *Result = Emit_264(N, X86::CMOVNE_Fp80, MVT::f80);
return Result;
}
@@ -50692,7 +50594,7 @@ SDNode *Select_X86ISD_CMOV_f80(const SDValue &N) {
// Emits: (CMOVNP_Fp80:f80 RFP80:f80:$src1, RFP80:f80:$src2)
// Pattern complexity = 8 cost = 1 size = 0
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_269(N, X86::CMOVNP_Fp80, MVT::f80);
+ SDNode *Result = Emit_264(N, X86::CMOVNP_Fp80, MVT::f80);
return Result;
}
}
@@ -50701,12 +50603,12 @@ SDNode *Select_X86ISD_CMOV_f80(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_CMOV_v1i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_268(N, X86::CMOV_V1I64, MVT::v1i64);
+SDNode *Select_X86ISD_CMOV_v1i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_263(N, X86::CMOV_V1I64, MVT::v1i64);
return Result;
}
@@ -50714,12 +50616,12 @@ SDNode *Select_X86ISD_CMOV_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_CMOV_v2i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_268(N, X86::CMOV_V2I64, MVT::v2i64);
+SDNode *Select_X86ISD_CMOV_v2i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_263(N, X86::CMOV_V2I64, MVT::v2i64);
return Result;
}
@@ -50727,12 +50629,12 @@ SDNode *Select_X86ISD_CMOV_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_CMOV_v4f32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_268(N, X86::CMOV_V4F32, MVT::v4f32);
+SDNode *Select_X86ISD_CMOV_v4f32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_263(N, X86::CMOV_V4F32, MVT::v4f32);
return Result;
}
@@ -50740,12 +50642,12 @@ SDNode *Select_X86ISD_CMOV_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_CMOV_v2f64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_268(N, X86::CMOV_V2F64, MVT::v2f64);
+SDNode *Select_X86ISD_CMOV_v2f64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_263(N, X86::CMOV_V2F64, MVT::v2f64);
return Result;
}
@@ -50753,201 +50655,201 @@ SDNode *Select_X86ISD_CMOV_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_272(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N00, N01);
+DISABLE_INLINE SDNode *Emit_267(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N00, N01);
}
-DISABLE_INLINE SDNode *Emit_273(const SDValue &N, unsigned Opc0, SDValue &CPTmpN011_0, SDValue &CPTmpN011_1, SDValue &CPTmpN011_2, SDValue &CPTmpN011_3, SDValue &CPTmpN011_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue Chain01 = N01.getOperand(0);
- SDValue N011 = N01.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_268(SDNode *N, unsigned Opc0, SDValue &CPTmpN011_0, SDValue &CPTmpN011_1, SDValue &CPTmpN011_2, SDValue &CPTmpN011_3, SDValue &CPTmpN011_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue Chain01 = N01.getNode()->getOperand(0);
+ SDValue N011 = N01.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N01)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N01.getNode())->getMemOperand();
SDValue Ops0[] = { N00, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4, Chain01 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N01.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_274(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_269(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i8);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N00, Tmp3);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N00, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_275(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_270(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i16);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N00, Tmp3);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N00, Tmp3);
}
-DISABLE_INLINE SDNode *Emit_276(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_271(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N00, Tmp3);
-}
-DISABLE_INLINE SDNode *Emit_277(const SDValue &N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue Chain00 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N00, Tmp3);
+}
+DISABLE_INLINE SDNode *Emit_272(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i8);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp3, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_278(const SDValue &N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue Chain00 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_273(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i16);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp3, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_279(const SDValue &N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue Chain00 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_274(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp3, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_280(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_275(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, N1, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_281(const SDValue &N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
+DISABLE_INLINE SDNode *Emit_276(SDNode *N, unsigned Opc0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_282(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_277(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N0, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, Tmp1);
}
-DISABLE_INLINE SDNode *Emit_283(const SDValue &N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
- SDValue N0 = N.getOperand(0);
- SDValue Chain0 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_278(SDNode *N, unsigned Opc0, SDValue &CPTmpN01_0, SDValue &CPTmpN01_1, SDValue &CPTmpN01_2, SDValue &CPTmpN01_3, SDValue &CPTmpN01_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i8);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N0)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N0.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4, Tmp1, Chain0 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N0.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_284(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_279(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i64);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N00, Tmp3);
-}
-DISABLE_INLINE SDNode *Emit_285(const SDValue &N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue Chain00 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N00, Tmp3);
+}
+DISABLE_INLINE SDNode *Emit_280(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp3 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N01)->getZExtValue()), MVT::i64);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Tmp3, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_286(const SDValue &N, unsigned Opc0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, N0, N0);
-}
-DISABLE_INLINE SDNode *Emit_287(const SDValue &N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue Chain00 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_281(SDNode *N, unsigned Opc0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, N0);
+}
+DISABLE_INLINE SDNode *Emit_282(SDNode *N, unsigned Opc0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
SDValue Ops0[] = { N01, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::i32, MVT::Other, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::i32, MVT::Other, Ops0, 7);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_X86ISD_CMP(const SDValue &N) {
+SDNode *Select_X86ISD_CMP(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode())) {
if (Predicate_load(N00.getNode())) {
@@ -50955,23 +50857,23 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST64mi32:isVoid addr:iPTR:$src1, (imm:i64):$src2)
// Pattern complexity = 37 cost = 1 size = 3
if (Predicate_loadi64(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_i64immSExt32(N01.getNode())) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_285(N, X86::TEST64mi32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_280(N, X86::TEST64mi32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -50983,22 +50885,22 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST8mi:isVoid addr:iPTR:$src1, (imm:i8):$src2)
// Pattern complexity = 36 cost = 1 size = 3
if (Predicate_loadi8(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_277(N, X86::TEST8mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_272(N, X86::TEST8mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -51011,22 +50913,22 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST16mi:isVoid addr:iPTR:$src1, (imm:i16):$src2)
// Pattern complexity = 36 cost = 1 size = 3
if (Predicate_loadi16(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_278(N, X86::TEST16mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_273(N, X86::TEST16mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -51038,22 +50940,22 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST32mi:isVoid addr:iPTR:$src1, (imm:i32):$src2)
// Pattern complexity = 36 cost = 1 size = 3
if (Predicate_loadi32(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_279(N, X86::TEST32mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_274(N, X86::TEST32mi, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -51063,11 +50965,11 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
}
}
{
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::LOAD &&
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::LOAD &&
N01.hasOneUse() &&
- IsLegalAndProfitableToFold(N01.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain01 = N01.getOperand(0);
+ IsLegalAndProfitableToFold(N01.getNode(), N0.getNode(), N)) {
+ SDValue Chain01 = N01.getNode()->getOperand(0);
if (Predicate_unindexedload(N01.getNode())) {
// Pattern: (X86cmp:isVoid (and:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>), 0:i8)
@@ -51075,20 +50977,20 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Pattern complexity = 33 cost = 1 size = 3
if (Predicate_load(N01.getNode()) &&
Predicate_loadi8(N01.getNode())) {
- SDValue N011 = N01.getOperand(1);
+ SDValue N011 = N01.getNode()->getOperand(1);
SDValue CPTmpN011_0;
SDValue CPTmpN011_1;
SDValue CPTmpN011_2;
SDValue CPTmpN011_3;
SDValue CPTmpN011_4;
if (SelectAddr(N, N011, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4)) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_273(N, X86::TEST8rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
+ SDNode *Result = Emit_268(N, X86::TEST8rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
return Result;
}
}
@@ -51099,20 +51001,20 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST16rm:isVoid GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
if (Predicate_loadi16(N01.getNode())) {
- SDValue N011 = N01.getOperand(1);
+ SDValue N011 = N01.getNode()->getOperand(1);
SDValue CPTmpN011_0;
SDValue CPTmpN011_1;
SDValue CPTmpN011_2;
SDValue CPTmpN011_3;
SDValue CPTmpN011_4;
if (SelectAddr(N, N011, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4)) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_273(N, X86::TEST16rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
+ SDNode *Result = Emit_268(N, X86::TEST16rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
return Result;
}
}
@@ -51123,20 +51025,20 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST32rm:isVoid GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
if (Predicate_loadi32(N01.getNode())) {
- SDValue N011 = N01.getOperand(1);
+ SDValue N011 = N01.getNode()->getOperand(1);
SDValue CPTmpN011_0;
SDValue CPTmpN011_1;
SDValue CPTmpN011_2;
SDValue CPTmpN011_3;
SDValue CPTmpN011_4;
if (SelectAddr(N, N011, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4)) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_273(N, X86::TEST32rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
+ SDNode *Result = Emit_268(N, X86::TEST32rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
return Result;
}
}
@@ -51148,20 +51050,20 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Pattern complexity = 33 cost = 1 size = 3
if (Predicate_load(N01.getNode()) &&
Predicate_loadi64(N01.getNode())) {
- SDValue N011 = N01.getOperand(1);
+ SDValue N011 = N01.getNode()->getOperand(1);
SDValue CPTmpN011_0;
SDValue CPTmpN011_1;
SDValue CPTmpN011_2;
SDValue CPTmpN011_3;
SDValue CPTmpN011_4;
if (SelectAddr(N, N011, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4)) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_273(N, X86::TEST64rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
+ SDNode *Result = Emit_268(N, X86::TEST64rm, CPTmpN011_0, CPTmpN011_1, CPTmpN011_2, CPTmpN011_3, CPTmpN011_4);
return Result;
}
}
@@ -51170,10 +51072,10 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
}
}
}
- if (N00.getOpcode() == ISD::LOAD &&
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode())) {
// Pattern: (X86cmp:isVoid (and:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src1), 0:i8)
@@ -51181,21 +51083,21 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Pattern complexity = 33 cost = 1 size = 3
if (Predicate_load(N00.getNode()) &&
Predicate_loadi8(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_287(N, X86::TEST8rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_282(N, X86::TEST8rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -51206,21 +51108,21 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST16rm:isVoid GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
if (Predicate_loadi16(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_287(N, X86::TEST16rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_282(N, X86::TEST16rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -51231,21 +51133,21 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST32rm:isVoid GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 33 cost = 1 size = 3
if (Predicate_loadi32(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_287(N, X86::TEST32rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_282(N, X86::TEST32rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -51257,21 +51159,21 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Pattern complexity = 33 cost = 1 size = 3
if (Predicate_load(N00.getNode()) &&
Predicate_loadi64(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_287(N, X86::TEST64rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_282(N, X86::TEST64rm, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -51280,28 +51182,28 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
}
}
}
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode())) {
// Pattern: (X86cmp:isVoid (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Emits: (CMP16mi8:isVoid addr:iPTR:$src1, (imm:i16):$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_i16immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_261(N, X86::CMP16mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_256(N, X86::CMP16mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -51311,40 +51213,40 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP32mi8:isVoid addr:iPTR:$src1, (imm:i32):$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_i32immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, X86::CMP32mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_257(N, X86::CMP32mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
if (Predicate_load(N0.getNode())) {
if (Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86cmp:isVoid (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Emits: (CMP64mi8:isVoid addr:iPTR:$src1, (imm:i64):$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_i64immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_264(N, X86::CMP64mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_259(N, X86::CMP64mi8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -51353,7 +51255,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_i64immSExt32(N1.getNode()) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_264(N, X86::CMP64mi32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_259(N, X86::CMP64mi32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -51364,17 +51266,17 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP8mi:isVoid addr:iPTR:$src1, (imm:i8):$src2)
// Pattern complexity = 28 cost = 1 size = 3
if (Predicate_loadi8(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_283(N, X86::CMP8mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_278(N, X86::CMP8mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -51385,17 +51287,17 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP16mi:isVoid addr:iPTR:$src1, (imm:i16):$src2)
// Pattern complexity = 28 cost = 1 size = 3
if (Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_261(N, X86::CMP16mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_256(N, X86::CMP16mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -51405,17 +51307,17 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP32mi:isVoid addr:iPTR:$src1, (imm:i32):$src2)
// Pattern complexity = 28 cost = 1 size = 3
if (Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_262(N, X86::CMP32mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_257(N, X86::CMP32mi, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -51426,16 +51328,16 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 3
if (Predicate_load(N0.getNode()) &&
Predicate_loadi8(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_280(N, X86::CMP8mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_275(N, X86::CMP8mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -51445,16 +51347,16 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP16mr:isVoid addr:iPTR:$src1, GR16:i16:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_280(N, X86::CMP16mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_275(N, X86::CMP16mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -51464,16 +51366,16 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP32mr:isVoid addr:iPTR:$src1, GR32:i32:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_280(N, X86::CMP32mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_275(N, X86::CMP32mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -51481,11 +51383,11 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
}
}
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode())) {
// Pattern: (X86cmp:isVoid GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
@@ -51493,7 +51395,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Pattern complexity = 25 cost = 1 size = 3
if (Predicate_load(N1.getNode()) &&
Predicate_loadi8(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -51501,7 +51403,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_281(N, X86::CMP8rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_276(N, X86::CMP8rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -51510,7 +51412,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP16rm:isVoid GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (Predicate_loadi16(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -51518,7 +51420,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_281(N, X86::CMP16rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_276(N, X86::CMP16rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -51527,7 +51429,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP32rm:isVoid GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -51535,7 +51437,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_281(N, X86::CMP32rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_276(N, X86::CMP32rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -51546,23 +51448,23 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Pattern: (X86cmp:isVoid (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src2)
// Emits: (CMP64mr:isVoid addr:iPTR:$src1, GR64:i64:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_280(N, X86::CMP64mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_275(N, X86::CMP64mr, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -51572,15 +51474,15 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Pattern: (X86cmp:isVoid GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
// Emits: (CMP64rm:isVoid GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -51588,7 +51490,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_281(N, X86::CMP64rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_276(N, X86::CMP64rm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -51599,16 +51501,16 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (UCOMISSrm:isVoid FR32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_loadf32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -51616,7 +51518,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_281(N, X86::UCOMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_276(N, X86::UCOMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -51627,16 +51529,16 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (UCOMISDrm:isVoid FR64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_loadf64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -51644,7 +51546,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_281(N, X86::UCOMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_276(N, X86::UCOMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -51652,14 +51554,14 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::AND) {
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::AND) {
if (Predicate_and_su(N0.getNode())) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -51668,7 +51570,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST8ri:isVoid GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 15 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_274(N, X86::TEST8ri);
+ SDNode *Result = Emit_269(N, X86::TEST8ri);
return Result;
}
@@ -51676,7 +51578,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST16ri:isVoid GR16:i16:$src1, (imm:i16):$src2)
// Pattern complexity = 15 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_275(N, X86::TEST16ri);
+ SDNode *Result = Emit_270(N, X86::TEST16ri);
return Result;
}
@@ -51684,7 +51586,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST32ri:isVoid GR32:i32:$src1, (imm:i32):$src2)
// Pattern complexity = 15 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_276(N, X86::TEST32ri);
+ SDNode *Result = Emit_271(N, X86::TEST32ri);
return Result;
}
}
@@ -51696,27 +51598,27 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST64ri32:isVoid GR64:i64:$src1, (imm:i64):$src2)
// Pattern complexity = 15 cost = 1 size = 3
{
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- if (N01.getOpcode() == ISD::Constant &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ if (N01.getNode()->getOpcode() == ISD::Constant &&
Predicate_i64immSExt32(N01.getNode())) {
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_284(N, X86::TEST64ri32);
+ SDNode *Result = Emit_279(N, X86::TEST64ri32);
return Result;
}
}
}
}
if (Predicate_and_su(N0.getNode())) {
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -51725,7 +51627,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST8rr:isVoid GR8:i8:$src1, GR8:i8:$src2)
// Pattern complexity = 12 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_272(N, X86::TEST8rr);
+ SDNode *Result = Emit_267(N, X86::TEST8rr);
return Result;
}
@@ -51733,7 +51635,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST16rr:isVoid GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 12 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_272(N, X86::TEST16rr);
+ SDNode *Result = Emit_267(N, X86::TEST16rr);
return Result;
}
@@ -51741,7 +51643,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST32rr:isVoid GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 12 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_272(N, X86::TEST32rr);
+ SDNode *Result = Emit_267(N, X86::TEST32rr);
return Result;
}
}
@@ -51751,22 +51653,22 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Pattern: (X86cmp:isVoid (and:i64 GR64:i64:$src1, GR64:i64:$src2), 0:i64)
// Emits: (TEST64rr:isVoid GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 11 cost = 1 size = 3
- SDValue N00 = N0.getOperand(0);
- SDValue N01 = N0.getOperand(1);
- SDValue N1 = N.getOperand(1);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue N1 = N->getOperand(1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_272(N, X86::TEST64rr);
+ SDNode *Result = Emit_267(N, X86::TEST64rr);
return Result;
}
}
}
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
@@ -51775,7 +51677,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST64rr:isVoid GR64:i64:$src1, GR64:i64:$src1)
// Pattern complexity = 8 cost = 1 size = 3
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_286(N, X86::TEST64rr);
+ SDNode *Result = Emit_281(N, X86::TEST64rr);
return Result;
}
@@ -51783,7 +51685,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST8rr:isVoid GR8:i8:$src1, GR8:i8:$src1)
// Pattern complexity = 8 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_286(N, X86::TEST8rr);
+ SDNode *Result = Emit_281(N, X86::TEST8rr);
return Result;
}
@@ -51791,7 +51693,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST16rr:isVoid GR16:i16:$src1, GR16:i16:$src1)
// Pattern complexity = 8 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_286(N, X86::TEST16rr);
+ SDNode *Result = Emit_281(N, X86::TEST16rr);
return Result;
}
@@ -51799,20 +51701,20 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (TEST32rr:isVoid GR32:i32:$src1, GR32:i32:$src1)
// Pattern complexity = 8 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_286(N, X86::TEST32rr);
+ SDNode *Result = Emit_281(N, X86::TEST32rr);
return Result;
}
}
}
}
- if (N1.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86cmp:isVoid GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Emits: (CMP16ri8:isVoid GR16:i16:$src1, (imm:i16):$src2)
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i16immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_259(N, X86::CMP16ri8);
+ SDNode *Result = Emit_254(N, X86::CMP16ri8);
return Result;
}
@@ -51821,7 +51723,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i32immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_260(N, X86::CMP32ri8);
+ SDNode *Result = Emit_255(N, X86::CMP32ri8);
return Result;
}
@@ -51830,7 +51732,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i64immSExt8(N1.getNode()) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_263(N, X86::CMP64ri8);
+ SDNode *Result = Emit_258(N, X86::CMP64ri8);
return Result;
}
@@ -51839,7 +51741,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Pattern complexity = 7 cost = 1 size = 3
if (Predicate_i64immSExt32(N1.getNode()) &&
N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_263(N, X86::CMP64ri32);
+ SDNode *Result = Emit_258(N, X86::CMP64ri32);
return Result;
}
@@ -51847,7 +51749,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP8ri:isVoid GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_282(N, X86::CMP8ri);
+ SDNode *Result = Emit_277(N, X86::CMP8ri);
return Result;
}
@@ -51855,7 +51757,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP16ri:isVoid GR16:i16:$src1, (imm:i16):$src2)
// Pattern complexity = 6 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_259(N, X86::CMP16ri);
+ SDNode *Result = Emit_254(N, X86::CMP16ri);
return Result;
}
@@ -51863,7 +51765,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP32ri:isVoid GR32:i32:$src1, (imm:i32):$src2)
// Pattern complexity = 6 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_260(N, X86::CMP32ri);
+ SDNode *Result = Emit_255(N, X86::CMP32ri);
return Result;
}
}
@@ -51873,10 +51775,10 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (UCOM_FpIr32:isVoid RFP32:f32:$lhs, RFP32:f32:$rhs)
// Pattern complexity = 3 cost = 1 size = 0
if ((!Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_258(N, X86::UCOM_FpIr32);
+ SDNode *Result = Emit_253(N, X86::UCOM_FpIr32);
return Result;
}
}
@@ -51885,22 +51787,22 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (UCOM_FpIr64:isVoid RFP64:f64:$lhs, RFP64:f64:$rhs)
// Pattern complexity = 3 cost = 1 size = 0
if ((!Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_258(N, X86::UCOM_FpIr64);
+ SDNode *Result = Emit_253(N, X86::UCOM_FpIr64);
return Result;
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (X86cmp:isVoid RFP80:f80:$lhs, RFP80:f80:$rhs)
// Emits: (UCOM_FpIr80:isVoid RFP80:f80:$lhs, RFP80:f80:$rhs)
// Pattern complexity = 3 cost = 1 size = 0
if (N0.getValueType() == MVT::f80) {
- SDNode *Result = Emit_258(N, X86::UCOM_FpIr80);
+ SDNode *Result = Emit_253(N, X86::UCOM_FpIr80);
return Result;
}
@@ -51908,7 +51810,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP8rr:isVoid GR8:i8:$src1, GR8:i8:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_258(N, X86::CMP8rr);
+ SDNode *Result = Emit_253(N, X86::CMP8rr);
return Result;
}
@@ -51916,7 +51818,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP16rr:isVoid GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_258(N, X86::CMP16rr);
+ SDNode *Result = Emit_253(N, X86::CMP16rr);
return Result;
}
@@ -51924,7 +51826,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP32rr:isVoid GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_258(N, X86::CMP32rr);
+ SDNode *Result = Emit_253(N, X86::CMP32rr);
return Result;
}
@@ -51932,7 +51834,7 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (CMP64rr:isVoid GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_258(N, X86::CMP64rr);
+ SDNode *Result = Emit_253(N, X86::CMP64rr);
return Result;
}
}
@@ -51941,10 +51843,10 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (UCOMISSrr:isVoid FR32:f32:$src1, FR32:f32:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::f32) {
- SDNode *Result = Emit_258(N, X86::UCOMISSrr);
+ SDNode *Result = Emit_253(N, X86::UCOMISSrr);
return Result;
}
}
@@ -51953,10 +51855,10 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
// Emits: (UCOMISDrr:isVoid FR64:f64:$src1, FR64:f64:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::f64) {
- SDNode *Result = Emit_258(N, X86::UCOMISDrr);
+ SDNode *Result = Emit_253(N, X86::UCOMISDrr);
return Result;
}
}
@@ -51965,54 +51867,54 @@ SDNode *Select_X86ISD_CMP(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_288(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_283(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i8);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_289(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue Chain1 = N1.getOperand(0);
- SDValue N11 = N1.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_284(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN11_0, SDValue &CPTmpN11_1, SDValue &CPTmpN11_2, SDValue &CPTmpN11_3, SDValue &CPTmpN11_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned char) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i8);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N1.getNode())->getMemOperand();
SDValue Ops0[] = { N0, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4, Tmp2, Chain1 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_X86ISD_CMPPD_v2i64(const SDValue &N) {
+SDNode *Select_X86ISD_CMPPD_v2i64(SDNode *N) {
// Pattern: (X86cmppd:v2i64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$cc)
// Emits: (CMPPDrmi:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$cc)
// Pattern complexity = 28 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_289(N, X86::CMPPDrmi, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_284(N, X86::CMPPDrmi, MVT::v2i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -52023,12 +51925,12 @@ SDNode *Select_X86ISD_CMPPD_v2i64(const SDValue &N) {
// Pattern: (X86cmppd:v2i64 VR128:v2f64:$src1, VR128:v2f64:$src2, (imm:i8):$cc)
// Emits: (CMPPDrri:v2i64 VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$cc)
// Pattern complexity = 6 cost = 1 size = 3
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_288(N, X86::CMPPDrri, MVT::v2i64);
+ SDNode *Result = Emit_283(N, X86::CMPPDrri, MVT::v2i64);
return Result;
}
@@ -52036,32 +51938,32 @@ SDNode *Select_X86ISD_CMPPD_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_CMPPS_v4i32(const SDValue &N) {
+SDNode *Select_X86ISD_CMPPS_v4i32(SDNode *N) {
// Pattern: (X86cmpps:v4i32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, (imm:i8):$cc)
// Emits: (CMPPSrmi:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i8):$cc)
// Pattern complexity = 28 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_289(N, X86::CMPPSrmi, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_284(N, X86::CMPPSrmi, MVT::v4i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -52072,12 +51974,12 @@ SDNode *Select_X86ISD_CMPPS_v4i32(const SDValue &N) {
// Pattern: (X86cmpps:v4i32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i8):$cc)
// Emits: (CMPPSrri:v4i32 VR128:v16i8:$src1, VR128:v16i8:$src2, (imm:i8):$cc)
// Pattern complexity = 6 cost = 1 size = 3
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_288(N, X86::CMPPSrri, MVT::v4i32);
+ SDNode *Result = Emit_283(N, X86::CMPPSrri, MVT::v4i32);
return Result;
}
@@ -52085,22 +51987,22 @@ SDNode *Select_X86ISD_CMPPS_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_COMI(const SDValue &N) {
+SDNode *Select_X86ISD_COMI(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
// Pattern: (X86comi:isVoid VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (Int_COMISSrm:isVoid VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -52108,7 +52010,7 @@ SDNode *Select_X86ISD_COMI(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_281(N, X86::Int_COMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_276(N, X86::Int_COMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -52119,15 +52021,15 @@ SDNode *Select_X86ISD_COMI(const SDValue &N) {
// Emits: (Int_COMISDrm:isVoid VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -52135,7 +52037,7 @@ SDNode *Select_X86ISD_COMI(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_281(N, X86::Int_COMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_276(N, X86::Int_COMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -52147,10 +52049,10 @@ SDNode *Select_X86ISD_COMI(const SDValue &N) {
// Emits: (Int_COMISSrr:isVoid VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_258(N, X86::Int_COMISSrr);
+ SDNode *Result = Emit_253(N, X86::Int_COMISSrr);
return Result;
}
}
@@ -52159,10 +52061,10 @@ SDNode *Select_X86ISD_COMI(const SDValue &N) {
// Emits: (Int_COMISDrr:isVoid VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_258(N, X86::Int_COMISDrr);
+ SDNode *Result = Emit_253(N, X86::Int_COMISDrr);
return Result;
}
}
@@ -52171,10 +52073,10 @@ SDNode *Select_X86ISD_COMI(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_DEC_i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_X86ISD_DEC_i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_256(N, X86::DEC8r, MVT::i8);
+ SDNode *Result = Emit_251(N, X86::DEC8r, MVT::i8);
return Result;
}
@@ -52182,15 +52084,15 @@ SDNode *Select_X86ISD_DEC_i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_DEC_i16(const SDValue &N) {
+SDNode *Select_X86ISD_DEC_i16(SDNode *N) {
// Pattern: (X86dec_flag:i16 GR16:i16:$src)
// Emits: (DEC16r:i16 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 1
if ((!Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_256(N, X86::DEC16r, MVT::i16);
+ SDNode *Result = Emit_251(N, X86::DEC16r, MVT::i16);
return Result;
}
}
@@ -52199,9 +52101,9 @@ SDNode *Select_X86ISD_DEC_i16(const SDValue &N) {
// Emits: (DEC64_16r:i16 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 2
if ((Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_256(N, X86::DEC64_16r, MVT::i16);
+ SDNode *Result = Emit_251(N, X86::DEC64_16r, MVT::i16);
return Result;
}
}
@@ -52210,15 +52112,15 @@ SDNode *Select_X86ISD_DEC_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_DEC_i32(const SDValue &N) {
+SDNode *Select_X86ISD_DEC_i32(SDNode *N) {
// Pattern: (X86dec_flag:i32 GR32:i32:$src)
// Emits: (DEC32r:i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 1
if ((!Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_256(N, X86::DEC32r, MVT::i32);
+ SDNode *Result = Emit_251(N, X86::DEC32r, MVT::i32);
return Result;
}
}
@@ -52227,9 +52129,9 @@ SDNode *Select_X86ISD_DEC_i32(const SDValue &N) {
// Emits: (DEC64_32r:i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 2
if ((Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_256(N, X86::DEC64_32r, MVT::i32);
+ SDNode *Result = Emit_251(N, X86::DEC64_32r, MVT::i32);
return Result;
}
}
@@ -52238,10 +52140,10 @@ SDNode *Select_X86ISD_DEC_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_DEC_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_X86ISD_DEC_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_256(N, X86::DEC64r, MVT::i64);
+ SDNode *Result = Emit_251(N, X86::DEC64r, MVT::i64);
return Result;
}
@@ -52249,15 +52151,15 @@ SDNode *Select_X86ISD_DEC_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_EH_RETURN(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_X86ISD_EH_RETURN(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (X86ehret:isVoid GR32:i32:$addr)
// Emits: (EH_RETURN:isVoid GR32:i32:$addr)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_82(N, X86::EH_RETURN);
+ SDNode *Result = Emit_83(N, X86::EH_RETURN);
return Result;
}
@@ -52265,7 +52167,7 @@ SDNode *Select_X86ISD_EH_RETURN(const SDValue &N) {
// Emits: (EH_RETURN64:isVoid GR64:i64:$addr)
// Pattern complexity = 3 cost = 1 size = 3
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_82(N, X86::EH_RETURN64);
+ SDNode *Result = Emit_83(N, X86::EH_RETURN64);
return Result;
}
@@ -52273,24 +52175,24 @@ SDNode *Select_X86ISD_EH_RETURN(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FAND_f32(const SDValue &N) {
+SDNode *Select_X86ISD_FAND_f32(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (X86fand:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (FsANDPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -52307,14 +52209,14 @@ SDNode *Select_X86ISD_FAND_f32(const SDValue &N) {
// Pattern: (X86fand:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR32:f32:$src1)
// Emits: (FsANDPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -52340,24 +52242,24 @@ SDNode *Select_X86ISD_FAND_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FAND_f64(const SDValue &N) {
+SDNode *Select_X86ISD_FAND_f64(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (X86fand:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (FsANDPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -52374,14 +52276,14 @@ SDNode *Select_X86ISD_FAND_f64(const SDValue &N) {
// Pattern: (X86fand:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR64:f64:$src1)
// Emits: (FsANDPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -52407,46 +52309,46 @@ SDNode *Select_X86ISD_FAND_f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_290(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_285(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
}
-SDNode *Select_X86ISD_FILD_f32(const SDValue &N) {
+SDNode *Select_X86ISD_FILD_f32(SDNode *N) {
if ((!Subtarget->hasSSE1())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
// Pattern: (X86fild:f32 addr:iPTR:$src, i16:Other)
// Emits: (ILD_Fp16m32:f32 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N2)->getVT() == MVT::i16) {
- SDNode *Result = Emit_290(N, X86::ILD_Fp16m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_285(N, X86::ILD_Fp16m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
// Pattern: (X86fild:f32 addr:iPTR:$src, i32:Other)
// Emits: (ILD_Fp32m32:f32 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N2)->getVT() == MVT::i32) {
- SDNode *Result = Emit_290(N, X86::ILD_Fp32m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_285(N, X86::ILD_Fp32m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
// Pattern: (X86fild:f32 addr:iPTR:$src, i64:Other)
// Emits: (ILD_Fp64m32:f32 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N2)->getVT() == MVT::i64) {
- SDNode *Result = Emit_290(N, X86::ILD_Fp64m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i64) {
+ SDNode *Result = Emit_285(N, X86::ILD_Fp64m32, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52456,39 +52358,39 @@ SDNode *Select_X86ISD_FILD_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FILD_f64(const SDValue &N) {
+SDNode *Select_X86ISD_FILD_f64(SDNode *N) {
if ((!Subtarget->hasSSE2())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
// Pattern: (X86fild:f64 addr:iPTR:$src, i16:Other)
// Emits: (ILD_Fp16m64:f64 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N2)->getVT() == MVT::i16) {
- SDNode *Result = Emit_290(N, X86::ILD_Fp16m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_285(N, X86::ILD_Fp16m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
// Pattern: (X86fild:f64 addr:iPTR:$src, i32:Other)
// Emits: (ILD_Fp32m64:f64 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N2)->getVT() == MVT::i32) {
- SDNode *Result = Emit_290(N, X86::ILD_Fp32m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_285(N, X86::ILD_Fp32m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
// Pattern: (X86fild:f64 addr:iPTR:$src, i64:Other)
// Emits: (ILD_Fp64m64:f64 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N2)->getVT() == MVT::i64) {
- SDNode *Result = Emit_290(N, X86::ILD_Fp64m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i64) {
+ SDNode *Result = Emit_285(N, X86::ILD_Fp64m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52498,38 +52400,38 @@ SDNode *Select_X86ISD_FILD_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FILD_f80(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_X86ISD_FILD_f80(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDValue N2 = N.getOperand(2);
+ SDValue N2 = N->getOperand(2);
// Pattern: (X86fild:f80 addr:iPTR:$src, i16:Other)
// Emits: (ILD_Fp16m80:f80 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N2)->getVT() == MVT::i16) {
- SDNode *Result = Emit_290(N, X86::ILD_Fp16m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_285(N, X86::ILD_Fp16m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
// Pattern: (X86fild:f80 addr:iPTR:$src, i32:Other)
// Emits: (ILD_Fp32m80:f80 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N2)->getVT() == MVT::i32) {
- SDNode *Result = Emit_290(N, X86::ILD_Fp32m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_285(N, X86::ILD_Fp32m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
// Pattern: (X86fild:f80 addr:iPTR:$src, i64:Other)
// Emits: (ILD_Fp64m80:f80 addr:iPTR:$src)
// Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N2)->getVT() == MVT::i64) {
- SDNode *Result = Emit_290(N, X86::ILD_Fp64m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i64) {
+ SDNode *Result = Emit_285(N, X86::ILD_Fp64m80, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52538,17 +52440,17 @@ SDNode *Select_X86ISD_FILD_f80(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_291(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_286(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, MVT::Flag, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, MVT::Flag, Ops0, 6);
Chain = SDValue(ResNode, 1);
SDValue InFlag(ResNode, 2);
const SDValue Froms[] = {
- SDValue(N.getNode(), 2),
- SDValue(N.getNode(), 1)
+ SDValue(N, 2),
+ SDValue(N, 1)
};
const SDValue Tos[] = {
InFlag,
@@ -52557,18 +52459,18 @@ DISABLE_INLINE SDNode *Emit_291(const SDValue &N, unsigned Opc0, MVT::SimpleValu
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_X86ISD_FILD_FLAG_f64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_X86ISD_FILD_FLAG_f64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDValue N2 = N.getOperand(2);
- if (cast<VTSDNode>(N2)->getVT() == MVT::i64) {
- SDNode *Result = Emit_291(N, X86::ILD_Fp64m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDValue N2 = N->getOperand(2);
+ if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::i64) {
+ SDNode *Result = Emit_286(N, X86::ILD_Fp64m64, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52577,18 +52479,18 @@ SDNode *Select_X86ISD_FILD_FLAG_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FLD_f32(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_X86ISD_FLD_f32(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDValue N2 = N.getOperand(2);
- if (cast<VTSDNode>(N2)->getVT() == MVT::f32) {
- SDNode *Result = Emit_290(N, X86::LD_Fp32m, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDValue N2 = N->getOperand(2);
+ if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::f32) {
+ SDNode *Result = Emit_285(N, X86::LD_Fp32m, MVT::f32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52597,18 +52499,18 @@ SDNode *Select_X86ISD_FLD_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FLD_f64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_X86ISD_FLD_f64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDValue N2 = N.getOperand(2);
- if (cast<VTSDNode>(N2)->getVT() == MVT::f64) {
- SDNode *Result = Emit_290(N, X86::LD_Fp64m, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDValue N2 = N->getOperand(2);
+ if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::f64) {
+ SDNode *Result = Emit_285(N, X86::LD_Fp64m, MVT::f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52617,18 +52519,18 @@ SDNode *Select_X86ISD_FLD_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FLD_f80(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_X86ISD_FLD_f80(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDValue N2 = N.getOperand(2);
- if (cast<VTSDNode>(N2)->getVT() == MVT::f80) {
- SDNode *Result = Emit_290(N, X86::LD_Fp80m, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDValue N2 = N->getOperand(2);
+ if (cast<VTSDNode>(N2.getNode())->getVT() == MVT::f80) {
+ SDNode *Result = Emit_285(N, X86::LD_Fp80m, MVT::f80, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -52637,22 +52539,22 @@ SDNode *Select_X86ISD_FLD_f80(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FMAX_f32(const SDValue &N) {
+SDNode *Select_X86ISD_FMAX_f32(SDNode *N) {
// Pattern: (X86fmax:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (MAXSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -52678,22 +52580,22 @@ SDNode *Select_X86ISD_FMAX_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FMAX_f64(const SDValue &N) {
+SDNode *Select_X86ISD_FMAX_f64(SDNode *N) {
// Pattern: (X86fmax:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (MAXSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -52719,23 +52621,23 @@ SDNode *Select_X86ISD_FMAX_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FMAX_v4f32(const SDValue &N) {
+SDNode *Select_X86ISD_FMAX_v4f32(SDNode *N) {
// Pattern: (X86fmax:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (MAXPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -52761,23 +52663,23 @@ SDNode *Select_X86ISD_FMAX_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FMAX_v2f64(const SDValue &N) {
+SDNode *Select_X86ISD_FMAX_v2f64(SDNode *N) {
// Pattern: (X86fmax:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (MAXPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -52803,22 +52705,22 @@ SDNode *Select_X86ISD_FMAX_v2f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FMIN_f32(const SDValue &N) {
+SDNode *Select_X86ISD_FMIN_f32(SDNode *N) {
// Pattern: (X86fmin:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (MINSSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -52844,22 +52746,22 @@ SDNode *Select_X86ISD_FMIN_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FMIN_f64(const SDValue &N) {
+SDNode *Select_X86ISD_FMIN_f64(SDNode *N) {
// Pattern: (X86fmin:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (MINSDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -52885,23 +52787,23 @@ SDNode *Select_X86ISD_FMIN_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FMIN_v4f32(const SDValue &N) {
+SDNode *Select_X86ISD_FMIN_v4f32(SDNode *N) {
// Pattern: (X86fmin:v4f32 VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (MINPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -52927,23 +52829,23 @@ SDNode *Select_X86ISD_FMIN_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FMIN_v2f64(const SDValue &N) {
+SDNode *Select_X86ISD_FMIN_v2f64(SDNode *N) {
// Pattern: (X86fmin:v2f64 VR128:v2f64:$src1, (ld:v2f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (MINPDrm:v2f64 VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -52969,22 +52871,22 @@ SDNode *Select_X86ISD_FMIN_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_292(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_287(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 6);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 6);
}
-SDNode *Select_X86ISD_FNSTCW16m(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_X86ISD_FNSTCW16m(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_292(N, X86::FNSTCW16m, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_287(N, X86::FNSTCW16m, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -52992,24 +52894,24 @@ SDNode *Select_X86ISD_FNSTCW16m(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FOR_f32(const SDValue &N) {
+SDNode *Select_X86ISD_FOR_f32(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (X86for:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (FsORPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -53026,14 +52928,14 @@ SDNode *Select_X86ISD_FOR_f32(const SDValue &N) {
// Pattern: (X86for:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR32:f32:$src1)
// Emits: (FsORPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -53059,24 +52961,24 @@ SDNode *Select_X86ISD_FOR_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FOR_f64(const SDValue &N) {
+SDNode *Select_X86ISD_FOR_f64(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (X86for:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (FsORPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -53093,14 +52995,14 @@ SDNode *Select_X86ISD_FOR_f64(const SDValue &N) {
// Pattern: (X86for:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR64:f64:$src1)
// Emits: (FsORPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -53126,18 +53028,18 @@ SDNode *Select_X86ISD_FOR_f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_293(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_288(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N1, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 7);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 7);
}
-SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(const SDValue &N) {
+SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(SDNode *N) {
if ((Subtarget->hasSSE3())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -53149,7 +53051,7 @@ SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(const SDValue &N) {
// Emits: (ISTT_Fp16m32:isVoid addr:iPTR:$op, RFP32:f32:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_293(N, X86::ISTT_Fp16m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_288(N, X86::ISTT_Fp16m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53157,7 +53059,7 @@ SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(const SDValue &N) {
// Emits: (ISTT_Fp16m64:isVoid addr:iPTR:$op, RFP64:f64:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_293(N, X86::ISTT_Fp16m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_288(N, X86::ISTT_Fp16m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53165,14 +53067,14 @@ SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(const SDValue &N) {
// Emits: (ISTT_Fp16m80:isVoid addr:iPTR:$op, RFP80:f80:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_293(N, X86::ISTT_Fp16m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_288(N, X86::ISTT_Fp16m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
}
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -53184,7 +53086,7 @@ SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(const SDValue &N) {
// Emits: (FP32_TO_INT16_IN_MEM:isVoid addr:iPTR:$dst, RFP32:f32:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_293(N, X86::FP32_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_288(N, X86::FP32_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53192,7 +53094,7 @@ SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(const SDValue &N) {
// Emits: (FP64_TO_INT16_IN_MEM:isVoid addr:iPTR:$dst, RFP64:f64:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_293(N, X86::FP64_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_288(N, X86::FP64_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53200,7 +53102,7 @@ SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(const SDValue &N) {
// Emits: (FP80_TO_INT16_IN_MEM:isVoid addr:iPTR:$dst, RFP80:f80:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_293(N, X86::FP80_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_288(N, X86::FP80_TO_INT16_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53209,11 +53111,11 @@ SDNode *Select_X86ISD_FP_TO_INT16_IN_MEM(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(const SDValue &N) {
+SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(SDNode *N) {
if ((Subtarget->hasSSE3())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -53225,7 +53127,7 @@ SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(const SDValue &N) {
// Emits: (ISTT_Fp32m32:isVoid addr:iPTR:$op, RFP32:f32:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_293(N, X86::ISTT_Fp32m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_288(N, X86::ISTT_Fp32m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53233,7 +53135,7 @@ SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(const SDValue &N) {
// Emits: (ISTT_Fp32m64:isVoid addr:iPTR:$op, RFP64:f64:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_293(N, X86::ISTT_Fp32m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_288(N, X86::ISTT_Fp32m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53241,14 +53143,14 @@ SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(const SDValue &N) {
// Emits: (ISTT_Fp32m80:isVoid addr:iPTR:$op, RFP80:f80:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_293(N, X86::ISTT_Fp32m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_288(N, X86::ISTT_Fp32m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
}
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -53260,7 +53162,7 @@ SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(const SDValue &N) {
// Emits: (FP32_TO_INT32_IN_MEM:isVoid addr:iPTR:$dst, RFP32:f32:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_293(N, X86::FP32_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_288(N, X86::FP32_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53268,7 +53170,7 @@ SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(const SDValue &N) {
// Emits: (FP64_TO_INT32_IN_MEM:isVoid addr:iPTR:$dst, RFP64:f64:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_293(N, X86::FP64_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_288(N, X86::FP64_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53276,7 +53178,7 @@ SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(const SDValue &N) {
// Emits: (FP80_TO_INT32_IN_MEM:isVoid addr:iPTR:$dst, RFP80:f80:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_293(N, X86::FP80_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_288(N, X86::FP80_TO_INT32_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53285,11 +53187,11 @@ SDNode *Select_X86ISD_FP_TO_INT32_IN_MEM(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(const SDValue &N) {
+SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(SDNode *N) {
if ((Subtarget->hasSSE3())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -53301,7 +53203,7 @@ SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(const SDValue &N) {
// Emits: (ISTT_Fp64m32:isVoid addr:iPTR:$op, RFP32:f32:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_293(N, X86::ISTT_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_288(N, X86::ISTT_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53309,7 +53211,7 @@ SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(const SDValue &N) {
// Emits: (ISTT_Fp64m64:isVoid addr:iPTR:$op, RFP64:f64:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_293(N, X86::ISTT_Fp64m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_288(N, X86::ISTT_Fp64m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53317,14 +53219,14 @@ SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(const SDValue &N) {
// Emits: (ISTT_Fp64m80:isVoid addr:iPTR:$op, RFP80:f80:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_293(N, X86::ISTT_Fp64m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_288(N, X86::ISTT_Fp64m80, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
}
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
@@ -53336,7 +53238,7 @@ SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(const SDValue &N) {
// Emits: (FP32_TO_INT64_IN_MEM:isVoid addr:iPTR:$dst, RFP32:f32:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_293(N, X86::FP32_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_288(N, X86::FP32_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53344,7 +53246,7 @@ SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(const SDValue &N) {
// Emits: (FP64_TO_INT64_IN_MEM:isVoid addr:iPTR:$dst, RFP64:f64:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_293(N, X86::FP64_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_288(N, X86::FP64_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53352,7 +53254,7 @@ SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(const SDValue &N) {
// Emits: (FP80_TO_INT64_IN_MEM:isVoid addr:iPTR:$dst, RFP80:f80:$src)
// Pattern complexity = 21 cost = 11 size = 3
if (N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_293(N, X86::FP80_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_288(N, X86::FP80_TO_INT64_IN_MEM, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53361,27 +53263,27 @@ SDNode *Select_X86ISD_FP_TO_INT64_IN_MEM(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FRCP_f32(const SDValue &N) {
+SDNode *Select_X86ISD_FRCP_f32(SDNode *N) {
// Pattern: (X86frcp:f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (RCPSSm:f32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE1()) && (OptForSize)) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_78(N, X86::RCPSSm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::RCPSSm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -53392,7 +53294,7 @@ SDNode *Select_X86ISD_FRCP_f32(const SDValue &N) {
// Emits: (RCPSSr:f32 FR32:f32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDNode *Result = Emit_71(N, X86::RCPSSr, MVT::f32);
+ SDNode *Result = Emit_72(N, X86::RCPSSr, MVT::f32);
return Result;
}
@@ -53400,28 +53302,28 @@ SDNode *Select_X86ISD_FRCP_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FRCP_v4f32(const SDValue &N) {
+SDNode *Select_X86ISD_FRCP_v4f32(SDNode *N) {
// Pattern: (X86frcp:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (RCPPSm:v4f32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_78(N, X86::RCPPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::RCPPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -53432,7 +53334,7 @@ SDNode *Select_X86ISD_FRCP_v4f32(const SDValue &N) {
// Emits: (RCPPSr:v4f32 VR128:v4f32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDNode *Result = Emit_71(N, X86::RCPPSr, MVT::v4f32);
+ SDNode *Result = Emit_72(N, X86::RCPPSr, MVT::v4f32);
return Result;
}
@@ -53440,27 +53342,27 @@ SDNode *Select_X86ISD_FRCP_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FRSQRT_f32(const SDValue &N) {
+SDNode *Select_X86ISD_FRSQRT_f32(SDNode *N) {
// Pattern: (X86frsqrt:f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (RSQRTSSm:f32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE1()) && (OptForSize)) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_78(N, X86::RSQRTSSm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::RSQRTSSm, MVT::f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -53471,7 +53373,7 @@ SDNode *Select_X86ISD_FRSQRT_f32(const SDValue &N) {
// Emits: (RSQRTSSr:f32 FR32:f32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDNode *Result = Emit_71(N, X86::RSQRTSSr, MVT::f32);
+ SDNode *Result = Emit_72(N, X86::RSQRTSSr, MVT::f32);
return Result;
}
@@ -53479,28 +53381,28 @@ SDNode *Select_X86ISD_FRSQRT_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FRSQRT_v4f32(const SDValue &N) {
+SDNode *Select_X86ISD_FRSQRT_v4f32(SDNode *N) {
// Pattern: (X86frsqrt:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (RSQRTPSm:v4f32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_78(N, X86::RSQRTPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::RSQRTPSm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -53511,7 +53413,7 @@ SDNode *Select_X86ISD_FRSQRT_v4f32(const SDValue &N) {
// Emits: (RSQRTPSr:v4f32 VR128:v4f32:$src)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDNode *Result = Emit_71(N, X86::RSQRTPSr, MVT::v4f32);
+ SDNode *Result = Emit_72(N, X86::RSQRTPSr, MVT::v4f32);
return Result;
}
@@ -53519,21 +53421,21 @@ SDNode *Select_X86ISD_FRSQRT_v4f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_294(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_289(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i32);
SDValue Tmp2 = Transform_BYTE_imm(Tmp1.getNode());
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp2);
}
-SDNode *Select_X86ISD_FSRL_v2f64(const SDValue &N) {
+SDNode *Select_X86ISD_FSRL_v2f64(SDNode *N) {
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
Predicate_i32immSExt8(N1.getNode()) &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_294(N, X86::PSRLDQri, MVT::v2f64);
+ SDNode *Result = Emit_289(N, X86::PSRLDQri, MVT::v2f64);
return Result;
}
}
@@ -53542,33 +53444,33 @@ SDNode *Select_X86ISD_FSRL_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_295(const SDValue &N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue InFlag = N.getOperand(4);
+DISABLE_INLINE SDNode *Emit_290(SDNode *N, unsigned Opc0, SDValue &CPTmpN2_0, SDValue &CPTmpN2_1, SDValue &CPTmpN2_2, SDValue &CPTmpN2_3, SDValue &CPTmpN2_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue InFlag = N->getOperand(4);
SDValue Ops0[] = { CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4, N1, Chain, InFlag };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, Ops0, 8);
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, Ops0, 8);
}
-SDNode *Select_X86ISD_FST(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+SDNode *Select_X86ISD_FST(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue CPTmpN2_0;
SDValue CPTmpN2_1;
SDValue CPTmpN2_2;
SDValue CPTmpN2_3;
SDValue CPTmpN2_4;
if (SelectAddr(N, N2, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4)) {
- SDValue N3 = N.getOperand(3);
- if (cast<VTSDNode>(N3)->getVT() == MVT::f32) {
+ SDValue N3 = N->getOperand(3);
+ if (cast<VTSDNode>(N3.getNode())->getVT() == MVT::f32) {
// Pattern: (X86fst:isVoid RFP32:f32:$src, addr:iPTR:$op, f32:Other)
// Emits: (ST_Fp32m:isVoid addr:iPTR:$op, RFP32:f32:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f32) {
- SDNode *Result = Emit_295(N, X86::ST_Fp32m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_290(N, X86::ST_Fp32m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
@@ -53576,7 +53478,7 @@ SDNode *Select_X86ISD_FST(const SDValue &N) {
// Emits: (ST_Fp64m32:isVoid addr:iPTR:$op, RFP64:f64:$src)
// Pattern complexity = 21 cost = 1 size = 0
if (N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_295(N, X86::ST_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_290(N, X86::ST_Fp64m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53584,36 +53486,36 @@ SDNode *Select_X86ISD_FST(const SDValue &N) {
// Pattern: (X86fst:isVoid RFP64:f64:$src, addr:iPTR:$op, f64:Other)
// Emits: (ST_Fp64m:isVoid addr:iPTR:$op, RFP64:f64:$src)
// Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N3)->getVT() == MVT::f64 &&
+ if (cast<VTSDNode>(N3.getNode())->getVT() == MVT::f64 &&
N1.getValueType() == MVT::f64) {
- SDNode *Result = Emit_295(N, X86::ST_Fp64m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_290(N, X86::ST_Fp64m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
// Pattern: (X86fst:isVoid RFP80:f80:$src, addr:iPTR:$op, f32:Other)
// Emits: (ST_Fp80m32:isVoid addr:iPTR:$op, RFP80:f80:$src)
// Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N3)->getVT() == MVT::f32 &&
+ if (cast<VTSDNode>(N3.getNode())->getVT() == MVT::f32 &&
N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_295(N, X86::ST_Fp80m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_290(N, X86::ST_Fp80m32, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
// Pattern: (X86fst:isVoid RFP80:f80:$src, addr:iPTR:$op, f64:Other)
// Emits: (ST_Fp80m64:isVoid addr:iPTR:$op, RFP80:f80:$src)
// Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N3)->getVT() == MVT::f64 &&
+ if (cast<VTSDNode>(N3.getNode())->getVT() == MVT::f64 &&
N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_295(N, X86::ST_Fp80m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_290(N, X86::ST_Fp80m64, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
// Pattern: (X86fst:isVoid RFP80:f80:$src, addr:iPTR:$op, f80:Other)
// Emits: (ST_FpP80m:isVoid addr:iPTR:$op, RFP80:f80:$src)
// Pattern complexity = 21 cost = 1 size = 0
- if (cast<VTSDNode>(N3)->getVT() == MVT::f80 &&
+ if (cast<VTSDNode>(N3.getNode())->getVT() == MVT::f80 &&
N1.getValueType() == MVT::f80) {
- SDNode *Result = Emit_295(N, X86::ST_FpP80m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
+ SDNode *Result = Emit_290(N, X86::ST_FpP80m, CPTmpN2_0, CPTmpN2_1, CPTmpN2_2, CPTmpN2_3, CPTmpN2_4);
return Result;
}
}
@@ -53622,24 +53524,24 @@ SDNode *Select_X86ISD_FST(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FXOR_f32(const SDValue &N) {
+SDNode *Select_X86ISD_FXOR_f32(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (X86fxor:f32 FR32:f32:$src1, (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (FsXORPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -53656,14 +53558,14 @@ SDNode *Select_X86ISD_FXOR_f32(const SDValue &N) {
// Pattern: (X86fxor:f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR32:f32:$src1)
// Emits: (FsXORPSrm:f32 FR32:f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -53689,24 +53591,24 @@ SDNode *Select_X86ISD_FXOR_f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_FXOR_f64(const SDValue &N) {
+SDNode *Select_X86ISD_FXOR_f64(SDNode *N) {
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (X86fxor:f64 FR64:f64:$src1, (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (FsXORPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -53723,14 +53625,14 @@ SDNode *Select_X86ISD_FXOR_f64(const SDValue &N) {
// Pattern: (X86fxor:f64 (ld:f64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, FR64:f64:$src1)
// Emits: (FsXORPDrm:f64 FR64:f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -53756,10 +53658,10 @@ SDNode *Select_X86ISD_FXOR_f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_INC_i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_X86ISD_INC_i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i8) {
- SDNode *Result = Emit_256(N, X86::INC8r, MVT::i8);
+ SDNode *Result = Emit_251(N, X86::INC8r, MVT::i8);
return Result;
}
@@ -53767,15 +53669,15 @@ SDNode *Select_X86ISD_INC_i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_INC_i16(const SDValue &N) {
+SDNode *Select_X86ISD_INC_i16(SDNode *N) {
// Pattern: (X86inc_flag:i16 GR16:i16:$src)
// Emits: (INC16r:i16 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 1
if ((!Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_256(N, X86::INC16r, MVT::i16);
+ SDNode *Result = Emit_251(N, X86::INC16r, MVT::i16);
return Result;
}
}
@@ -53784,9 +53686,9 @@ SDNode *Select_X86ISD_INC_i16(const SDValue &N) {
// Emits: (INC64_16r:i16 GR16:i16:$src)
// Pattern complexity = 3 cost = 1 size = 2
if ((Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i16) {
- SDNode *Result = Emit_256(N, X86::INC64_16r, MVT::i16);
+ SDNode *Result = Emit_251(N, X86::INC64_16r, MVT::i16);
return Result;
}
}
@@ -53795,15 +53697,15 @@ SDNode *Select_X86ISD_INC_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_INC_i32(const SDValue &N) {
+SDNode *Select_X86ISD_INC_i32(SDNode *N) {
// Pattern: (X86inc_flag:i32 GR32:i32:$src)
// Emits: (INC32r:i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 1
if ((!Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_256(N, X86::INC32r, MVT::i32);
+ SDNode *Result = Emit_251(N, X86::INC32r, MVT::i32);
return Result;
}
}
@@ -53812,9 +53714,9 @@ SDNode *Select_X86ISD_INC_i32(const SDValue &N) {
// Emits: (INC64_32r:i32 GR32:i32:$src)
// Pattern complexity = 3 cost = 1 size = 2
if ((Subtarget->is64Bit())) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
- SDNode *Result = Emit_256(N, X86::INC64_32r, MVT::i32);
+ SDNode *Result = Emit_251(N, X86::INC64_32r, MVT::i32);
return Result;
}
}
@@ -53823,10 +53725,10 @@ SDNode *Select_X86ISD_INC_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_INC_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_X86ISD_INC_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i64) {
- SDNode *Result = Emit_256(N, X86::INC64r, MVT::i64);
+ SDNode *Result = Emit_251(N, X86::INC64r, MVT::i64);
return Result;
}
@@ -53834,52 +53736,52 @@ SDNode *Select_X86ISD_INC_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_296(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_291(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { N0, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp2, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_X86ISD_INSERTPS_v4f32(const SDValue &N) {
+SDNode *Select_X86ISD_INSERTPS_v4f32(SDNode *N) {
// Pattern: (X86insrtps:v4f32 VR128:v4f32:$src1, (scalar_to_vector:v4f32 (ld:f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>), (imm:iPTR):$src3)
// Emits: (INSERTPSrm:v4f32 VR128:v4f32:$src1, addr:iPTR:$src2, (imm:i32):$src3)
// Pattern complexity = 31 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_loadf32(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::f32) {
- SDNode *Result = Emit_296(N, X86::INSERTPSrm, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_291(N, X86::INSERTPSrm, MVT::v4f32, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -53892,11 +53794,11 @@ SDNode *Select_X86ISD_INSERTPS_v4f32(const SDValue &N) {
// Emits: (INSERTPSrr:v4f32 VR128:v4f32:$src1, VR128:v4f32:$src2, (imm:i32):$src3)
// Pattern complexity = 6 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_99(N, X86::INSERTPSrr, MVT::v4f32);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_98(N, X86::INSERTPSrr, MVT::v4f32);
return Result;
}
}
@@ -53905,17 +53807,17 @@ SDNode *Select_X86ISD_INSERTPS_v4f32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_297(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue InFlag = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_292(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue InFlag = N->getOperand(2);
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, 7);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, 7);
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -53924,16 +53826,16 @@ DISABLE_INLINE SDNode *Emit_297(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_X86ISD_LCMPXCHG8_DAG(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_X86ISD_LCMPXCHG8_DAG(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_297(N, X86::LCMPXCHG8B, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_292(N, X86::LCMPXCHG8B, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -53941,19 +53843,19 @@ SDNode *Select_X86ISD_LCMPXCHG8_DAG(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_298(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- SDValue InFlag = N.getOperand(4);
+DISABLE_INLINE SDNode *Emit_293(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ SDValue InFlag = N->getOperand(4);
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, N2, Chain, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, 8);
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -53962,18 +53864,18 @@ DISABLE_INLINE SDNode *Emit_298(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_X86ISD_LCMPXCHG_DAG(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_X86ISD_LCMPXCHG_DAG(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N3);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N3.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -53982,7 +53884,7 @@ SDNode *Select_X86ISD_LCMPXCHG_DAG(const SDValue &N) {
// Pattern complexity = 26 cost = 1 size = 3
if (CN1 == INT64_C(4) &&
N2.getValueType() == MVT::i32) {
- SDNode *Result = Emit_298(N, X86::LCMPXCHG32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_293(N, X86::LCMPXCHG32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -53991,7 +53893,7 @@ SDNode *Select_X86ISD_LCMPXCHG_DAG(const SDValue &N) {
// Pattern complexity = 26 cost = 1 size = 3
if (CN1 == INT64_C(2) &&
N2.getValueType() == MVT::i16) {
- SDNode *Result = Emit_298(N, X86::LCMPXCHG16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_293(N, X86::LCMPXCHG16, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -54000,7 +53902,7 @@ SDNode *Select_X86ISD_LCMPXCHG_DAG(const SDValue &N) {
// Pattern complexity = 26 cost = 1 size = 3
if (CN1 == INT64_C(1) &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_298(N, X86::LCMPXCHG8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_293(N, X86::LCMPXCHG8, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -54009,7 +53911,7 @@ SDNode *Select_X86ISD_LCMPXCHG_DAG(const SDValue &N) {
// Pattern complexity = 26 cost = 1 size = 3
if (CN1 == INT64_C(8) &&
N2.getValueType() == MVT::i64) {
- SDNode *Result = Emit_298(N, X86::LCMPXCHG64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_293(N, X86::LCMPXCHG64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
}
@@ -54019,7 +53921,86 @@ SDNode *Select_X86ISD_LCMPXCHG_DAG(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_MUL_IMM_i32(const SDValue &N) {
+DISABLE_INLINE SDNode *Emit_294(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN0001_0, SDValue &CPTmpN0001_1, SDValue &CPTmpN0001_2, SDValue &CPTmpN0001_3, SDValue &CPTmpN0001_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue N000 = N00.getNode()->getOperand(0);
+ SDValue Chain000 = N000.getNode()->getOperand(0);
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
+ MemRefs0[0] = cast<MemSDNode>(N000.getNode())->getMemOperand();
+ SDValue Ops0[] = { CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4, Chain000 };
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
+ cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
+ ReplaceUses(SDValue(N000.getNode(), 1), SDValue(ResNode, 1));
+ return ResNode;
+}
+SDNode *Select_X86ISD_MOVQ2DQ_v2i64(SDNode *N) {
+ if (OptLevel != CodeGenOpt::None) {
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (MMX_X86movq2dq:v2i64 (bitconvert:v1i64 (scalar_to_vector:v2i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)))
+ // Emits: (MOVDI2PDIrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 31 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
+ N0.hasOneUse()) {
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ N00.hasOneUse()) {
+ SDValue N000 = N00.getNode()->getOperand(0);
+ if (N000.getNode()->getOpcode() == ISD::LOAD &&
+ N000.hasOneUse() &&
+ IsLegalAndProfitableToFold(N000.getNode(), N00.getNode(), N)) {
+ SDValue Chain000 = N000.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N000.getNode()) &&
+ Predicate_loadi32(N000.getNode())) {
+ SDValue N0001 = N000.getNode()->getOperand(1);
+ SDValue CPTmpN0001_0;
+ SDValue CPTmpN0001_1;
+ SDValue CPTmpN0001_2;
+ SDValue CPTmpN0001_3;
+ SDValue CPTmpN0001_4;
+ if (SelectAddr(N, N0001, CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4) &&
+ N00.getValueType() == MVT::v2i32 &&
+ N000.getValueType() == MVT::i32) {
+ SDNode *Result = Emit_294(N, X86::MOVDI2PDIrm, MVT::v2i64, CPTmpN0001_0, CPTmpN0001_1, CPTmpN0001_2, CPTmpN0001_3, CPTmpN0001_4);
+ return Result;
+ }
+ }
+ }
+ }
+ }
+
+ // Pattern: (MMX_X86movq2dq:v2i64 (ld:v1i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
+ // Emits: (MOVQI2PQIrm:v2i64 addr:iPTR:$src)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse()) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_79(N, X86::MOVQI2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (MMX_X86movq2dq:v2i64 VR64:v1i64:$src)
+ // Emits: (MMX_MOVQ2DQrr:v2i64 VR64:v8i8:$src)
+ // Pattern complexity = 3 cost = 1 size = 3
+ SDNode *Result = Emit_72(N, X86::MMX_MOVQ2DQrr, MVT::v2i64);
+ return Result;
+}
+
+SDNode *Select_X86ISD_MUL_IMM_i32(SDNode *N) {
// Pattern: lea32addr:i32:$src
// Emits: (LEA64_32r:i32 lea32addr:i32:$src)
@@ -54029,7 +54010,7 @@ SDNode *Select_X86ISD_MUL_IMM_i32(const SDValue &N) {
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA64_32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
@@ -54043,7 +54024,7 @@ SDNode *Select_X86ISD_MUL_IMM_i32(const SDValue &N) {
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA32r, MVT::i32, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
@@ -54053,12 +54034,12 @@ SDNode *Select_X86ISD_MUL_IMM_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_MUL_IMM_i64(const SDValue &N) {
+SDNode *Select_X86ISD_MUL_IMM_i64(SDNode *N) {
SDValue CPTmpN_0;
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
@@ -54067,29 +54048,54 @@ SDNode *Select_X86ISD_MUL_IMM_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_OR_i8(const SDValue &N) {
-
- // Pattern: (X86or_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
- // Emits: (OR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+SDNode *Select_X86ISD_OR_i8(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi8(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::OR8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86or_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
+ // Emits: (OR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi8(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::OR8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86or_flag:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src1)
+ // Emits: (OR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadi8(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::OR8rm, MVT::i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -54100,9 +54106,9 @@ SDNode *Select_X86ISD_OR_i8(const SDValue &N) {
// Emits: (OR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_3(N, X86::OR8ri, MVT::i8);
return Result;
}
@@ -54115,37 +54121,61 @@ SDNode *Select_X86ISD_OR_i8(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_OR_i16(const SDValue &N) {
-
- // Pattern: (X86or_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
- // Emits: (OR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+SDNode *Select_X86ISD_OR_i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi16(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::OR16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86or_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
+ // Emits: (OR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi16(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::OR16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86or_flag:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src1)
+ // Emits: (OR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi16(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::OR16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86or_flag:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Emits: (OR16ri8:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
@@ -54170,37 +54200,61 @@ SDNode *Select_X86ISD_OR_i16(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_OR_i32(const SDValue &N) {
-
- // Pattern: (X86or_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (OR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+SDNode *Select_X86ISD_OR_i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::OR32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86or_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (OR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi32(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::OR32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86or_flag:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src1)
+ // Emits: (OR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::OR32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86or_flag:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Emits: (OR32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
@@ -54225,38 +54279,63 @@ SDNode *Select_X86ISD_OR_i32(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_OR_i64(const SDValue &N) {
-
- // Pattern: (X86or_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (OR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+SDNode *Select_X86ISD_OR_i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::OR64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86or_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (OR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi64(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::OR64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86or_flag:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src1)
+ // Emits: (OR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadi64(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::OR64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86or_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Emits: (OR64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
@@ -54283,25 +54362,25 @@ SDNode *Select_X86ISD_OR_i64(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_PCMPEQB_v8i8(const SDValue &N) {
+SDNode *Select_X86ISD_PCMPEQB_v8i8(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (X86pcmpeqb:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PCMPEQBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -54320,23 +54399,23 @@ SDNode *Select_X86ISD_PCMPEQB_v8i8(const SDValue &N) {
// Pattern: (X86pcmpeqb:v8i8 (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v8i8:$src1)
// Emits: (MMX_PCMPEQBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v1i64) {
SDNode *Result = Emit_17(N, X86::MMX_PCMPEQBrm, MVT::v8i8, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
@@ -54354,23 +54433,23 @@ SDNode *Select_X86ISD_PCMPEQB_v8i8(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_PCMPEQB_v16i8(const SDValue &N) {
+SDNode *Select_X86ISD_PCMPEQB_v16i8(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (X86pcmpeqb:v16i8 VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PCMPEQBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -54387,14 +54466,14 @@ SDNode *Select_X86ISD_PCMPEQB_v16i8(const SDValue &N) {
// Pattern: (X86pcmpeqb:v16i8 (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v16i8:$src1)
// Emits: (PCMPEQBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -54415,25 +54494,25 @@ SDNode *Select_X86ISD_PCMPEQB_v16i8(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_PCMPEQD_v2i32(const SDValue &N) {
+SDNode *Select_X86ISD_PCMPEQD_v2i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (X86pcmpeqd:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PCMPEQDrm:v2i32 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -54452,23 +54531,23 @@ SDNode *Select_X86ISD_PCMPEQD_v2i32(const SDValue &N) {
// Pattern: (X86pcmpeqd:v2i32 (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v2i32:$src1)
// Emits: (MMX_PCMPEQDrm:v2i32 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v1i64) {
SDNode *Result = Emit_17(N, X86::MMX_PCMPEQDrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
@@ -54486,23 +54565,23 @@ SDNode *Select_X86ISD_PCMPEQD_v2i32(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_PCMPEQD_v4i32(const SDValue &N) {
+SDNode *Select_X86ISD_PCMPEQD_v4i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (X86pcmpeqd:v4i32 VR128:v4i32:$src1, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PCMPEQDrm:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -54519,14 +54598,14 @@ SDNode *Select_X86ISD_PCMPEQD_v4i32(const SDValue &N) {
// Pattern: (X86pcmpeqd:v4i32 (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v4i32:$src1)
// Emits: (PCMPEQDrm:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -54547,23 +54626,23 @@ SDNode *Select_X86ISD_PCMPEQD_v4i32(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_PCMPEQQ_v2i64(const SDValue &N) {
+SDNode *Select_X86ISD_PCMPEQQ_v2i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (X86pcmpeqq:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PCMPEQQrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -54580,14 +54659,14 @@ SDNode *Select_X86ISD_PCMPEQQ_v2i64(const SDValue &N) {
// Pattern: (X86pcmpeqq:v2i64 (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v2i64:$src1)
// Emits: (PCMPEQQrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -54608,25 +54687,25 @@ SDNode *Select_X86ISD_PCMPEQQ_v2i64(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_PCMPEQW_v4i16(const SDValue &N) {
+SDNode *Select_X86ISD_PCMPEQW_v4i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (X86pcmpeqw:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PCMPEQWrm:v4i16 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -54645,23 +54724,23 @@ SDNode *Select_X86ISD_PCMPEQW_v4i16(const SDValue &N) {
// Pattern: (X86pcmpeqw:v4i16 (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>), VR64:v4i16:$src1)
// Emits: (MMX_PCMPEQWrm:v4i16 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
SDValue CPTmpN001_3;
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4)) {
- SDValue N1 = N.getOperand(1);
+ SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v1i64) {
SDNode *Result = Emit_17(N, X86::MMX_PCMPEQWrm, MVT::v4i16, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
@@ -54679,23 +54758,23 @@ SDNode *Select_X86ISD_PCMPEQW_v4i16(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_PCMPEQW_v8i16(const SDValue &N) {
+SDNode *Select_X86ISD_PCMPEQW_v8i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (X86pcmpeqw:v8i16 VR128:v8i16:$src1, (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PCMPEQWrm:v8i16 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
{
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -54712,14 +54791,14 @@ SDNode *Select_X86ISD_PCMPEQW_v8i16(const SDValue &N) {
// Pattern: (X86pcmpeqw:v8i16 (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>, VR128:v8i16:$src1)
// Emits: (PCMPEQWrm:v8i16 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_memop(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
@@ -54740,24 +54819,24 @@ SDNode *Select_X86ISD_PCMPEQW_v8i16(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_PCMPGTB_v8i8(const SDValue &N) {
+SDNode *Select_X86ISD_PCMPGTB_v8i8(SDNode *N) {
// Pattern: (X86pcmpgtb:v8i8 VR64:v8i8:$src1, (bitconvert:v8i8 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PCMPGTBrm:v8i8 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -54780,22 +54859,22 @@ SDNode *Select_X86ISD_PCMPGTB_v8i8(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_PCMPGTB_v16i8(const SDValue &N) {
+SDNode *Select_X86ISD_PCMPGTB_v16i8(SDNode *N) {
// Pattern: (X86pcmpgtb:v16i8 VR128:v16i8:$src1, (ld:v16i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PCMPGTBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -54816,24 +54895,24 @@ SDNode *Select_X86ISD_PCMPGTB_v16i8(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_PCMPGTD_v2i32(const SDValue &N) {
+SDNode *Select_X86ISD_PCMPGTD_v2i32(SDNode *N) {
// Pattern: (X86pcmpgtd:v2i32 VR64:v2i32:$src1, (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PCMPGTDrm:v2i32 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -54856,22 +54935,22 @@ SDNode *Select_X86ISD_PCMPGTD_v2i32(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_PCMPGTD_v4i32(const SDValue &N) {
+SDNode *Select_X86ISD_PCMPGTD_v4i32(SDNode *N) {
// Pattern: (X86pcmpgtd:v4i32 VR128:v4i32:$src1, (ld:v4i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PCMPGTDrm:v4i32 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -54892,22 +54971,22 @@ SDNode *Select_X86ISD_PCMPGTD_v4i32(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_PCMPGTQ_v2i64(const SDValue &N) {
+SDNode *Select_X86ISD_PCMPGTQ_v2i64(SDNode *N) {
// Pattern: (X86pcmpgtq:v2i64 VR128:v2i64:$src1, (ld:v2i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PCMPGTQrm:v2i64 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -54928,24 +55007,24 @@ SDNode *Select_X86ISD_PCMPGTQ_v2i64(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_PCMPGTW_v4i16(const SDValue &N) {
+SDNode *Select_X86ISD_PCMPGTW_v4i16(SDNode *N) {
// Pattern: (X86pcmpgtw:v4i16 VR64:v4i16:$src1, (bitconvert:v4i16 (ld:v1i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_PCMPGTWrm:v4i16 VR64:v8i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 28 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -54968,22 +55047,22 @@ SDNode *Select_X86ISD_PCMPGTW_v4i16(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_PCMPGTW_v8i16(const SDValue &N) {
+SDNode *Select_X86ISD_PCMPGTW_v8i16(SDNode *N) {
// Pattern: (X86pcmpgtw:v8i16 VR128:v8i16:$src1, (ld:v8i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)
// Emits: (PCMPGTWrm:v8i16 VR128:v16i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_memop(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -55004,13 +55083,13 @@ SDNode *Select_X86ISD_PCMPGTW_v8i16(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_PEXTRB_i32(const SDValue &N) {
+SDNode *Select_X86ISD_PEXTRB_i32(SDNode *N) {
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v16i8) {
- SDNode *Result = Emit_95(N, X86::PEXTRBrr, MVT::i32);
+ SDNode *Result = Emit_94(N, X86::PEXTRBrr, MVT::i32);
return Result;
}
}
@@ -55019,23 +55098,23 @@ SDNode *Select_X86ISD_PEXTRB_i32(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_299(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_295(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N1)->getZExtValue()), MVT::i16);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, Tmp1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, Tmp1);
}
-SDNode *Select_X86ISD_PEXTRW_i32(const SDValue &N) {
+SDNode *Select_X86ISD_PEXTRW_i32(SDNode *N) {
// Pattern: (X86pextrw:i32 VR128:v8i16:$src1, (imm:iPTR):$src2)
// Emits: (PEXTRWri:i32 VR128:v8i16:$src1, (imm:i32):$src2)
// Pattern complexity = 6 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v8i16) {
- SDNode *Result = Emit_95(N, X86::PEXTRWri, MVT::i32);
+ SDNode *Result = Emit_94(N, X86::PEXTRWri, MVT::i32);
return Result;
}
}
@@ -55044,12 +55123,12 @@ SDNode *Select_X86ISD_PEXTRW_i32(const SDValue &N) {
// Emits: (MMX_PEXTRWri:i32 VR64:v4i16:$src1, (imm:i16):$src2)
// Pattern complexity = 6 cost = 1 size = 3
if ((Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i16 &&
N1.getValueType() == TLI.getPointerTy()) {
- SDNode *Result = Emit_299(N, X86::MMX_PEXTRWri, MVT::i32);
+ SDNode *Result = Emit_295(N, X86::MMX_PEXTRWri, MVT::i32);
return Result;
}
}
@@ -55058,32 +55137,32 @@ SDNode *Select_X86ISD_PEXTRW_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_PINSRB_v16i8(const SDValue &N) {
+SDNode *Select_X86ISD_PINSRB_v16i8(SDNode *N) {
// Pattern: (X86pinsrb:v16i8 VR128:v16i8:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, (imm:iPTR):$src3)
// Emits: (PINSRBrm:v16i8 VR128:v16i8:$src1, addr:iPTR:$src2, (imm:i32):$src3)
// Pattern complexity = 28 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_extload(N1.getNode()) &&
Predicate_extloadi8(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_100(N, X86::PINSRBrm, MVT::v16i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_99(N, X86::PINSRBrm, MVT::v16i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -55095,11 +55174,11 @@ SDNode *Select_X86ISD_PINSRB_v16i8(const SDValue &N) {
// Emits: (PINSRBrr:v16i8 VR128:v16i8:$src1, GR32:i32:$src2, (imm:i32):$src3)
// Pattern complexity = 6 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_99(N, X86::PINSRBrr, MVT::v16i8);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_98(N, X86::PINSRBrr, MVT::v16i8);
return Result;
}
}
@@ -55108,61 +55187,61 @@ SDNode *Select_X86ISD_PINSRB_v16i8(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_300(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_296(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i16);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, Tmp2);
-}
-DISABLE_INLINE SDNode *Emit_301(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N10 = N1.getOperand(0);
- SDValue Chain10 = N10.getOperand(0);
- SDValue N101 = N10.getOperand(1);
- SDValue N2 = N.getOperand(2);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, Tmp2);
+}
+DISABLE_INLINE SDNode *Emit_297(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN101_0, SDValue &CPTmpN101_1, SDValue &CPTmpN101_2, SDValue &CPTmpN101_3, SDValue &CPTmpN101_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N10 = N1.getNode()->getOperand(0);
+ SDValue Chain10 = N10.getNode()->getOperand(0);
+ SDValue N101 = N10.getNode()->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned short) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i16);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N10)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N10.getNode())->getMemOperand();
SDValue Ops0[] = { N0, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4, Tmp2, Chain10 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 8);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 8);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N10.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-SDNode *Select_X86ISD_PINSRW_v4i16(const SDValue &N) {
+SDNode *Select_X86ISD_PINSRW_v4i16(SDNode *N) {
// Pattern: (MMX_X86pinsrw:v4i16 VR64:v4i16:$src1, (anyext:i32 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>), (imm:iPTR):$src3)
// Emits: (MMX_PINSRWrmi:v4i16 VR64:v4i16:$src1, addr:iPTR:$src2, (imm:i16):$src3)
// Pattern complexity = 31 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::ANY_EXTEND &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::ANY_EXTEND &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_loadi16(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
SDValue CPTmpN101_3;
SDValue CPTmpN101_4;
if (SelectAddr(N, N101, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4)) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i16 &&
N1.getValueType() == MVT::i32 &&
N10.getValueType() == MVT::i16 &&
N2.getValueType() == TLI.getPointerTy()) {
- SDNode *Result = Emit_301(N, X86::MMX_PINSRWrmi, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
+ SDNode *Result = Emit_297(N, X86::MMX_PINSRWrmi, MVT::v4i16, CPTmpN101_0, CPTmpN101_1, CPTmpN101_2, CPTmpN101_3, CPTmpN101_4);
return Result;
}
}
@@ -55175,14 +55254,14 @@ SDNode *Select_X86ISD_PINSRW_v4i16(const SDValue &N) {
// Emits: (MMX_PINSRWrri:v4i16 VR64:v4i16:$src1, GR32:i32:$src2, (imm:i16):$src3)
// Pattern complexity = 6 cost = 1 size = 3
if ((Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i16 &&
N1.getValueType() == MVT::i32 &&
N2.getValueType() == TLI.getPointerTy()) {
- SDNode *Result = Emit_300(N, X86::MMX_PINSRWrri, MVT::v4i16);
+ SDNode *Result = Emit_296(N, X86::MMX_PINSRWrri, MVT::v4i16);
return Result;
}
}
@@ -55191,32 +55270,32 @@ SDNode *Select_X86ISD_PINSRW_v4i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_PINSRW_v8i16(const SDValue &N) {
+SDNode *Select_X86ISD_PINSRW_v8i16(SDNode *N) {
// Pattern: (X86pinsrw:v8i16 VR128:v8i16:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, (imm:iPTR):$src3)
// Emits: (PINSRWrmi:v8i16 VR128:v8i16:$src1, addr:iPTR:$src2, (imm:i32):$src3)
// Pattern complexity = 28 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_extload(N1.getNode()) &&
Predicate_extloadi16(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_100(N, X86::PINSRWrmi, MVT::v8i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_99(N, X86::PINSRWrmi, MVT::v8i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -55228,11 +55307,11 @@ SDNode *Select_X86ISD_PINSRW_v8i16(const SDValue &N) {
// Emits: (PINSRWrri:v8i16 VR128:v8i16:$src1, GR32:i32:$src2, (imm:i32):$src3)
// Pattern complexity = 6 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_99(N, X86::PINSRWrri, MVT::v8i16);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_98(N, X86::PINSRWrri, MVT::v8i16);
return Result;
}
}
@@ -55241,26 +55320,26 @@ SDNode *Select_X86ISD_PINSRW_v8i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_PSHUFB_v16i8(const SDValue &N) {
+SDNode *Select_X86ISD_PSHUFB_v16i8(SDNode *N) {
// Pattern: (X86pshufb:v16i8 VR128:v16i8:$src, (bitconvert:v16i8 (ld:v2i64 addr:iPTR:$mask)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
// Emits: (PSHUFBrm128:v16i8 VR128:v16i8:$src, addr:iPTR:$mask)
// Pattern complexity = 28 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSSE3())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N1.hasOneUse()) {
- SDValue N10 = N1.getOperand(0);
- if (N10.getOpcode() == ISD::LOAD &&
+ SDValue N10 = N1.getNode()->getOperand(0);
+ if (N10.getNode()->getOpcode() == ISD::LOAD &&
N10.hasOneUse() &&
- IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N.getNode())) {
- SDValue Chain10 = N10.getOperand(0);
+ IsLegalAndProfitableToFold(N10.getNode(), N1.getNode(), N)) {
+ SDValue Chain10 = N10.getNode()->getOperand(0);
if (Predicate_unindexedload(N10.getNode()) &&
Predicate_load(N10.getNode()) &&
Predicate_memop(N10.getNode())) {
- SDValue N101 = N10.getOperand(1);
+ SDValue N101 = N10.getNode()->getOperand(1);
SDValue CPTmpN101_0;
SDValue CPTmpN101_1;
SDValue CPTmpN101_2;
@@ -55288,29 +55367,29 @@ SDNode *Select_X86ISD_PSHUFB_v16i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_PTEST(const SDValue &N) {
+SDNode *Select_X86ISD_PTEST(SDNode *N) {
// Pattern: (X86ptest:isVoid VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (PTESTrm:isVoid VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None &&
(Subtarget->hasSSE41())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
SDValue CPTmpN11_3;
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_281(N, X86::PTESTrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_276(N, X86::PTESTrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -55321,7 +55400,7 @@ SDNode *Select_X86ISD_PTEST(const SDValue &N) {
// Emits: (PTESTrr:isVoid VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE41())) {
- SDNode *Result = Emit_258(N, X86::PTESTrr);
+ SDNode *Result = Emit_253(N, X86::PTESTrr);
return Result;
}
@@ -55329,14 +55408,14 @@ SDNode *Select_X86ISD_PTEST(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_302(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Chain);
+DISABLE_INLINE SDNode *Emit_298(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Chain);
Chain = SDValue(ResNode, 0);
SDValue InFlag(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -55345,21 +55424,21 @@ DISABLE_INLINE SDNode *Emit_302(const SDValue &N, unsigned Opc0) {
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_X86ISD_RDTSC_DAG(const SDValue &N) {
- SDNode *Result = Emit_302(N, X86::RDTSC);
+SDNode *Select_X86ISD_RDTSC_DAG(SDNode *N) {
+ SDNode *Result = Emit_298(N, X86::RDTSC);
return Result;
}
-DISABLE_INLINE SDNode *Emit_303(const SDValue &N, unsigned Opc0) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue InFlag = N.getOperand(2);
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Chain, InFlag);
+DISABLE_INLINE SDNode *Emit_299(SDNode *N, unsigned Opc0) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue InFlag = N->getOperand(2);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Chain, InFlag);
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -55368,39 +55447,39 @@ DISABLE_INLINE SDNode *Emit_303(const SDValue &N, unsigned Opc0) {
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_X86ISD_REP_MOVS(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_X86ISD_REP_MOVS(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (X86rep_movs:isVoid i8:Other)
// Emits: (REP_MOVSB:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
- if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
- SDNode *Result = Emit_303(N, X86::REP_MOVSB);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
+ SDNode *Result = Emit_299(N, X86::REP_MOVSB);
return Result;
}
// Pattern: (X86rep_movs:isVoid i16:Other)
// Emits: (REP_MOVSW:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
- if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
- SDNode *Result = Emit_303(N, X86::REP_MOVSW);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_299(N, X86::REP_MOVSW);
return Result;
}
// Pattern: (X86rep_movs:isVoid i32:Other)
// Emits: (REP_MOVSD:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
- if (cast<VTSDNode>(N1)->getVT() == MVT::i32) {
- SDNode *Result = Emit_303(N, X86::REP_MOVSD);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_299(N, X86::REP_MOVSD);
return Result;
}
// Pattern: (X86rep_movs:isVoid i64:Other)
// Emits: (REP_MOVSQ:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
- if (cast<VTSDNode>(N1)->getVT() == MVT::i64) {
- SDNode *Result = Emit_303(N, X86::REP_MOVSQ);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i64) {
+ SDNode *Result = Emit_299(N, X86::REP_MOVSQ);
return Result;
}
@@ -55408,39 +55487,39 @@ SDNode *Select_X86ISD_REP_MOVS(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_REP_STOS(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_X86ISD_REP_STOS(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (X86rep_stos:isVoid i8:Other)
// Emits: (REP_STOSB:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
- if (cast<VTSDNode>(N1)->getVT() == MVT::i8) {
- SDNode *Result = Emit_303(N, X86::REP_STOSB);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i8) {
+ SDNode *Result = Emit_299(N, X86::REP_STOSB);
return Result;
}
// Pattern: (X86rep_stos:isVoid i16:Other)
// Emits: (REP_STOSW:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
- if (cast<VTSDNode>(N1)->getVT() == MVT::i16) {
- SDNode *Result = Emit_303(N, X86::REP_STOSW);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i16) {
+ SDNode *Result = Emit_299(N, X86::REP_STOSW);
return Result;
}
// Pattern: (X86rep_stos:isVoid i32:Other)
// Emits: (REP_STOSD:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
- if (cast<VTSDNode>(N1)->getVT() == MVT::i32) {
- SDNode *Result = Emit_303(N, X86::REP_STOSD);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i32) {
+ SDNode *Result = Emit_299(N, X86::REP_STOSD);
return Result;
}
// Pattern: (X86rep_stos:isVoid i64:Other)
// Emits: (REP_STOSQ:isVoid)
// Pattern complexity = 3 cost = 1 size = 3
- if (cast<VTSDNode>(N1)->getVT() == MVT::i64) {
- SDNode *Result = Emit_303(N, X86::REP_STOSQ);
+ if (cast<VTSDNode>(N1.getNode())->getVT() == MVT::i64) {
+ SDNode *Result = Emit_299(N, X86::REP_STOSQ);
return Result;
}
@@ -55448,54 +55527,54 @@ SDNode *Select_X86ISD_REP_STOS(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_304(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_300(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SmallVector<SDValue, 8> Ops0;
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
- for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N.getOperand(i));
+ for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N->getOperand(i));
}
Ops0.push_back(Chain);
if (HasInFlag)
Ops0.push_back(InFlag);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, &Ops0[0], Ops0.size());
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, &Ops0[0], Ops0.size());
}
-DISABLE_INLINE SDNode *Emit_305(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_301(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SmallVector<SDValue, 8> Ops0;
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
Ops0.push_back(N1);
- for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N.getOperand(i));
+ for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N->getOperand(i));
}
Ops0.push_back(Chain);
if (HasInFlag)
Ops0.push_back(InFlag);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, &Ops0[0], Ops0.size());
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, &Ops0[0], Ops0.size());
}
-SDNode *Select_X86ISD_RET_FLAG(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_X86ISD_RET_FLAG(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (X86retflag:isVoid 0:i16)
// Emits: (RET:isVoid)
// Pattern complexity = 8 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_304(N, X86::RET, 1);
+ SDNode *Result = Emit_300(N, X86::RET, 1);
return Result;
}
}
@@ -55504,8 +55583,8 @@ SDNode *Select_X86ISD_RET_FLAG(const SDValue &N) {
// Pattern: (X86retflag:isVoid (timm:i16):$amt)
// Emits: (RETI:isVoid (timm:i16):$amt)
// Pattern complexity = 6 cost = 1 size = 3
- if (N1.getOpcode() == ISD::TargetConstant) {
- SDNode *Result = Emit_305(N, X86::RETI, 1);
+ if (N1.getNode()->getOpcode() == ISD::TargetConstant) {
+ SDNode *Result = Emit_301(N, X86::RETI, 1);
return Result;
}
@@ -55513,19 +55592,19 @@ SDNode *Select_X86ISD_RET_FLAG(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_306(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_302(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Chain = CurDAG->getEntryNode();
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::EFLAGS, N1, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::EFLAGS, N1, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, InFlag);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, InFlag);
}
-SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+SDNode *Select_X86ISD_SETCC_i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
@@ -55533,7 +55612,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETEr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(4)) {
- SDNode *Result = Emit_306(N, X86::SETEr, MVT::i8);
+ SDNode *Result = Emit_302(N, X86::SETEr, MVT::i8);
return Result;
}
@@ -55541,7 +55620,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETNEr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(9)) {
- SDNode *Result = Emit_306(N, X86::SETNEr, MVT::i8);
+ SDNode *Result = Emit_302(N, X86::SETNEr, MVT::i8);
return Result;
}
@@ -55549,7 +55628,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETLr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(7)) {
- SDNode *Result = Emit_306(N, X86::SETLr, MVT::i8);
+ SDNode *Result = Emit_302(N, X86::SETLr, MVT::i8);
return Result;
}
@@ -55557,7 +55636,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETGEr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(6)) {
- SDNode *Result = Emit_306(N, X86::SETGEr, MVT::i8);
+ SDNode *Result = Emit_302(N, X86::SETGEr, MVT::i8);
return Result;
}
@@ -55565,7 +55644,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETLEr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(8)) {
- SDNode *Result = Emit_306(N, X86::SETLEr, MVT::i8);
+ SDNode *Result = Emit_302(N, X86::SETLEr, MVT::i8);
return Result;
}
@@ -55573,7 +55652,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETGr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(5)) {
- SDNode *Result = Emit_306(N, X86::SETGr, MVT::i8);
+ SDNode *Result = Emit_302(N, X86::SETGr, MVT::i8);
return Result;
}
@@ -55581,7 +55660,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETBr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_306(N, X86::SETBr, MVT::i8);
+ SDNode *Result = Emit_302(N, X86::SETBr, MVT::i8);
return Result;
}
@@ -55589,7 +55668,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETAEr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(1)) {
- SDNode *Result = Emit_306(N, X86::SETAEr, MVT::i8);
+ SDNode *Result = Emit_302(N, X86::SETAEr, MVT::i8);
return Result;
}
@@ -55597,7 +55676,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETBEr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(3)) {
- SDNode *Result = Emit_306(N, X86::SETBEr, MVT::i8);
+ SDNode *Result = Emit_302(N, X86::SETBEr, MVT::i8);
return Result;
}
@@ -55605,7 +55684,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETAr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(0)) {
- SDNode *Result = Emit_306(N, X86::SETAr, MVT::i8);
+ SDNode *Result = Emit_302(N, X86::SETAr, MVT::i8);
return Result;
}
@@ -55613,7 +55692,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETSr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(15)) {
- SDNode *Result = Emit_306(N, X86::SETSr, MVT::i8);
+ SDNode *Result = Emit_302(N, X86::SETSr, MVT::i8);
return Result;
}
@@ -55621,7 +55700,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETNSr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(12)) {
- SDNode *Result = Emit_306(N, X86::SETNSr, MVT::i8);
+ SDNode *Result = Emit_302(N, X86::SETNSr, MVT::i8);
return Result;
}
@@ -55629,7 +55708,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETPr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(14)) {
- SDNode *Result = Emit_306(N, X86::SETPr, MVT::i8);
+ SDNode *Result = Emit_302(N, X86::SETPr, MVT::i8);
return Result;
}
@@ -55637,7 +55716,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETNPr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(11)) {
- SDNode *Result = Emit_306(N, X86::SETNPr, MVT::i8);
+ SDNode *Result = Emit_302(N, X86::SETNPr, MVT::i8);
return Result;
}
@@ -55645,7 +55724,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETOr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(13)) {
- SDNode *Result = Emit_306(N, X86::SETOr, MVT::i8);
+ SDNode *Result = Emit_302(N, X86::SETOr, MVT::i8);
return Result;
}
@@ -55653,7 +55732,7 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
// Emits: (SETNOr:i8)
// Pattern complexity = 8 cost = 1 size = 3
if (CN1 == INT64_C(10)) {
- SDNode *Result = Emit_306(N, X86::SETNOr, MVT::i8);
+ SDNode *Result = Emit_302(N, X86::SETNOr, MVT::i8);
return Result;
}
}
@@ -55662,13 +55741,13 @@ SDNode *Select_X86ISD_SETCC_i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_SETCC_CARRY_i8(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+SDNode *Select_X86ISD_SETCC_CARRY_i8(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_306(N, X86::SETB_C8r, MVT::i8);
+ SDNode *Result = Emit_302(N, X86::SETB_C8r, MVT::i8);
return Result;
}
}
@@ -55677,13 +55756,13 @@ SDNode *Select_X86ISD_SETCC_CARRY_i8(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_SETCC_CARRY_i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+SDNode *Select_X86ISD_SETCC_CARRY_i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_306(N, X86::SETB_C16r, MVT::i16);
+ SDNode *Result = Emit_302(N, X86::SETB_C16r, MVT::i16);
return Result;
}
}
@@ -55692,13 +55771,13 @@ SDNode *Select_X86ISD_SETCC_CARRY_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_SETCC_CARRY_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+SDNode *Select_X86ISD_SETCC_CARRY_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_306(N, X86::SETB_C32r, MVT::i32);
+ SDNode *Result = Emit_302(N, X86::SETB_C32r, MVT::i32);
return Result;
}
}
@@ -55707,13 +55786,13 @@ SDNode *Select_X86ISD_SETCC_CARRY_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_SETCC_CARRY_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0);
+SDNode *Select_X86ISD_SETCC_CARRY_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N0.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_306(N, X86::SETB_C64r, MVT::i64);
+ SDNode *Result = Emit_302(N, X86::SETB_C64r, MVT::i64);
return Result;
}
}
@@ -55722,28 +55801,28 @@ SDNode *Select_X86ISD_SETCC_CARRY_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_307(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+DISABLE_INLINE SDNode *Emit_303(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
SDValue Chain = CurDAG->getEntryNode();
SDValue InFlag(0, 0);
- SDNode *ResNode = CurDAG->getCopyToReg(Chain, N.getDebugLoc(), X86::CL, N2, InFlag).getNode();
+ SDNode *ResNode = CurDAG->getCopyToReg(Chain, N->getDebugLoc(), X86::CL, N2, InFlag).getNode();
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, N0, N1, InFlag);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, N0, N1, InFlag);
}
-SDNode *Select_X86ISD_SHLD_i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+SDNode *Select_X86ISD_SHLD_i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
// Pattern: (X86shld:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$src3)
// Emits: (SHLD16rri8:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$src3)
// Pattern complexity = 6 cost = 1 size = 3
- if (N2.getOpcode() == ISD::Constant &&
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_288(N, X86::SHLD16rri8, MVT::i16);
+ SDNode *Result = Emit_283(N, X86::SHLD16rri8, MVT::i16);
return Result;
}
@@ -55751,7 +55830,7 @@ SDNode *Select_X86ISD_SHLD_i16(const SDValue &N) {
// Emits: (SHLD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_307(N, X86::SHLD16rrCL, MVT::i16);
+ SDNode *Result = Emit_303(N, X86::SHLD16rrCL, MVT::i16);
return Result;
}
@@ -55759,17 +55838,17 @@ SDNode *Select_X86ISD_SHLD_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_SHLD_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+SDNode *Select_X86ISD_SHLD_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
// Pattern: (X86shld:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$src3)
// Emits: (SHLD32rri8:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$src3)
// Pattern complexity = 6 cost = 1 size = 3
- if (N2.getOpcode() == ISD::Constant &&
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_288(N, X86::SHLD32rri8, MVT::i32);
+ SDNode *Result = Emit_283(N, X86::SHLD32rri8, MVT::i32);
return Result;
}
@@ -55777,7 +55856,7 @@ SDNode *Select_X86ISD_SHLD_i32(const SDValue &N) {
// Emits: (SHLD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_307(N, X86::SHLD32rrCL, MVT::i32);
+ SDNode *Result = Emit_303(N, X86::SHLD32rrCL, MVT::i32);
return Result;
}
@@ -55785,17 +55864,17 @@ SDNode *Select_X86ISD_SHLD_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_SHLD_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+SDNode *Select_X86ISD_SHLD_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
// Pattern: (X86shld:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$src3)
// Emits: (SHLD64rri8:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$src3)
// Pattern complexity = 6 cost = 1 size = 3
- if (N2.getOpcode() == ISD::Constant &&
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_288(N, X86::SHLD64rri8, MVT::i64);
+ SDNode *Result = Emit_283(N, X86::SHLD64rri8, MVT::i64);
return Result;
}
@@ -55803,7 +55882,7 @@ SDNode *Select_X86ISD_SHLD_i64(const SDValue &N) {
// Emits: (SHLD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_307(N, X86::SHLD64rrCL, MVT::i64);
+ SDNode *Result = Emit_303(N, X86::SHLD64rrCL, MVT::i64);
return Result;
}
@@ -55811,17 +55890,17 @@ SDNode *Select_X86ISD_SHLD_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_SHRD_i16(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+SDNode *Select_X86ISD_SHRD_i16(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
// Pattern: (X86shrd:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$src3)
// Emits: (SHRD16rri8:i16 GR16:i16:$src1, GR16:i16:$src2, (imm:i8):$src3)
// Pattern complexity = 6 cost = 1 size = 3
- if (N2.getOpcode() == ISD::Constant &&
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_288(N, X86::SHRD16rri8, MVT::i16);
+ SDNode *Result = Emit_283(N, X86::SHRD16rri8, MVT::i16);
return Result;
}
@@ -55829,7 +55908,7 @@ SDNode *Select_X86ISD_SHRD_i16(const SDValue &N) {
// Emits: (SHRD16rrCL:i16 GR16:i16:$src1, GR16:i16:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_307(N, X86::SHRD16rrCL, MVT::i16);
+ SDNode *Result = Emit_303(N, X86::SHRD16rrCL, MVT::i16);
return Result;
}
@@ -55837,17 +55916,17 @@ SDNode *Select_X86ISD_SHRD_i16(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_SHRD_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+SDNode *Select_X86ISD_SHRD_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
// Pattern: (X86shrd:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$src3)
// Emits: (SHRD32rri8:i32 GR32:i32:$src1, GR32:i32:$src2, (imm:i8):$src3)
// Pattern complexity = 6 cost = 1 size = 3
- if (N2.getOpcode() == ISD::Constant &&
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_288(N, X86::SHRD32rri8, MVT::i32);
+ SDNode *Result = Emit_283(N, X86::SHRD32rri8, MVT::i32);
return Result;
}
@@ -55855,7 +55934,7 @@ SDNode *Select_X86ISD_SHRD_i32(const SDValue &N) {
// Emits: (SHRD32rrCL:i32 GR32:i32:$src1, GR32:i32:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_307(N, X86::SHRD32rrCL, MVT::i32);
+ SDNode *Result = Emit_303(N, X86::SHRD32rrCL, MVT::i32);
return Result;
}
@@ -55863,17 +55942,17 @@ SDNode *Select_X86ISD_SHRD_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_SHRD_i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
+SDNode *Select_X86ISD_SHRD_i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
// Pattern: (X86shrd:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$src3)
// Emits: (SHRD64rri8:i64 GR64:i64:$src1, GR64:i64:$src2, (imm:i8):$src3)
// Pattern complexity = 6 cost = 1 size = 3
- if (N2.getOpcode() == ISD::Constant &&
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_288(N, X86::SHRD64rri8, MVT::i64);
+ SDNode *Result = Emit_283(N, X86::SHRD64rri8, MVT::i64);
return Result;
}
@@ -55881,7 +55960,7 @@ SDNode *Select_X86ISD_SHRD_i64(const SDValue &N) {
// Emits: (SHRD64rrCL:i64 GR64:i64:$src1, GR64:i64:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if (N2.getValueType() == MVT::i8) {
- SDNode *Result = Emit_307(N, X86::SHRD64rrCL, MVT::i64);
+ SDNode *Result = Emit_303(N, X86::SHRD64rrCL, MVT::i64);
return Result;
}
@@ -55889,42 +55968,42 @@ SDNode *Select_X86ISD_SHRD_i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_308(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::i32, N0, N0);
+DISABLE_INLINE SDNode *Emit_304(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::i32, N0, N0);
}
-SDNode *Select_X86ISD_SMUL_i16(const SDValue &N) {
+SDNode *Select_X86ISD_SMUL_i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_loadi16(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86smul_flag:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Emits: (IMUL16rmi8:i16 addr:iPTR:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_i16immSExt8(N1.getNode())) {
- SDNode *Result = Emit_147(N, X86::IMUL16rmi8, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_146(N, X86::IMUL16rmi8, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
// Pattern: (X86smul_flag:i16 (ld:i16 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i16):$src2)
// Emits: (IMUL16rmi:i16 addr:iPTR:$src1, (imm:i16):$src2)
// Pattern complexity = 28 cost = 1 size = 3
- SDNode *Result = Emit_147(N, X86::IMUL16rmi, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_146(N, X86::IMUL16rmi, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -55934,44 +56013,68 @@ SDNode *Select_X86ISD_SMUL_i16(const SDValue &N) {
// Pattern: (X86smul_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
// Emits: (IMUL16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi16(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::IMUL16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi16(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::IMUL16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86smul_flag:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src1)
+ // Emits: (IMUL16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi16(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::IMUL16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (X86smul_flag:i16 GR16:i16:$src1, 2:i16)
// Emits: (ADD16rr:i16 GR16:i16:$src1, GR16:i16:$src1)
// Pattern complexity = 10 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_308(N, X86::ADD16rr, MVT::i16);
+ SDNode *Result = Emit_304(N, X86::ADD16rr, MVT::i16);
return Result;
}
}
}
- if (N1.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86smul_flag:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Emits: (IMUL16rri8:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
@@ -55996,37 +56099,37 @@ SDNode *Select_X86ISD_SMUL_i16(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_SMUL_i32(const SDValue &N) {
+SDNode *Select_X86ISD_SMUL_i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_loadi32(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86smul_flag:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Emits: (IMUL32rmi8:i32 addr:iPTR:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_i32immSExt8(N1.getNode())) {
- SDNode *Result = Emit_148(N, X86::IMUL32rmi8, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_147(N, X86::IMUL32rmi8, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
// Pattern: (X86smul_flag:i32 (ld:i32 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i32):$src2)
// Emits: (IMUL32rmi:i32 addr:iPTR:$src1, (imm:i32):$src2)
// Pattern complexity = 28 cost = 1 size = 3
- SDNode *Result = Emit_148(N, X86::IMUL32rmi, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_147(N, X86::IMUL32rmi, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -56036,44 +56139,68 @@ SDNode *Select_X86ISD_SMUL_i32(const SDValue &N) {
// Pattern: (X86smul_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
// Emits: (IMUL32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::IMUL32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi32(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::IMUL32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86smul_flag:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src1)
+ // Emits: (IMUL32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::IMUL32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (X86smul_flag:i32 GR32:i32:$src1, 2:i32)
// Emits: (ADD32rr:i32 GR32:i32:$src1, GR32:i32:$src1)
// Pattern complexity = 10 cost = 1 size = 3
{
- ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1);
+ ConstantSDNode *Tmp0 = dyn_cast<ConstantSDNode>(N1.getNode());
if (Tmp0) {
int64_t CN1 = Tmp0->getSExtValue();
if (CN1 == INT64_C(2)) {
- SDNode *Result = Emit_308(N, X86::ADD32rr, MVT::i32);
+ SDNode *Result = Emit_304(N, X86::ADD32rr, MVT::i32);
return Result;
}
}
}
- if (N1.getOpcode() == ISD::Constant) {
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86smul_flag:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Emits: (IMUL32rri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
@@ -56098,31 +56225,31 @@ SDNode *Select_X86ISD_SMUL_i32(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_SMUL_i64(const SDValue &N) {
+SDNode *Select_X86ISD_SMUL_i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
- IsLegalAndProfitableToFold(N0.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain0 = N0.getOperand(0);
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode()) &&
Predicate_loadi64(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86smul_flag:i64 (ld:i64 addr:iPTR:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Emits: (IMUL64rmi8:i64 addr:iPTR:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_i64immSExt8(N1.getNode())) {
- SDNode *Result = Emit_149(N, X86::IMUL64rmi8, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_148(N, X86::IMUL64rmi8, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
@@ -56130,7 +56257,7 @@ SDNode *Select_X86ISD_SMUL_i64(const SDValue &N) {
// Emits: (IMUL64rmi32:i64 addr:iPTR:$src1, (imm:i64)<<P:Predicate_i64immSExt32>>:$src2)
// Pattern complexity = 29 cost = 1 size = 3
if (Predicate_i64immSExt32(N1.getNode())) {
- SDNode *Result = Emit_149(N, X86::IMUL64rmi32, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_148(N, X86::IMUL64rmi32, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -56141,31 +56268,56 @@ SDNode *Select_X86ISD_SMUL_i64(const SDValue &N) {
// Pattern: (X86smul_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
// Emits: (IMUL64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::IMUL64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi64(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::IMUL64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86smul_flag:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src1)
+ // Emits: (IMUL64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadi64(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::IMUL64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86smul_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Emits: (IMUL64rri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
@@ -56192,22 +56344,22 @@ SDNode *Select_X86ISD_SMUL_i64(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_SUB_i8(const SDValue &N) {
+SDNode *Select_X86ISD_SUB_i8(SDNode *N) {
// Pattern: (X86sub_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
// Emits: (SUB8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_loadi8(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -56225,9 +56377,9 @@ SDNode *Select_X86ISD_SUB_i8(const SDValue &N) {
// Emits: (SUB8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_3(N, X86::SUB8ri, MVT::i8);
return Result;
}
@@ -56240,21 +56392,21 @@ SDNode *Select_X86ISD_SUB_i8(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_SUB_i16(const SDValue &N) {
+SDNode *Select_X86ISD_SUB_i16(SDNode *N) {
// Pattern: (X86sub_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
// Emits: (SUB16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_loadi16(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -56268,9 +56420,9 @@ SDNode *Select_X86ISD_SUB_i16(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86sub_flag:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Emits: (SUB16ri8:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
@@ -56295,21 +56447,21 @@ SDNode *Select_X86ISD_SUB_i16(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_SUB_i32(const SDValue &N) {
+SDNode *Select_X86ISD_SUB_i32(SDNode *N) {
// Pattern: (X86sub_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
// Emits: (SUB32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -56323,9 +56475,9 @@ SDNode *Select_X86ISD_SUB_i32(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86sub_flag:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Emits: (SUB32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
@@ -56350,22 +56502,22 @@ SDNode *Select_X86ISD_SUB_i32(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_SUB_i64(const SDValue &N) {
+SDNode *Select_X86ISD_SUB_i64(SDNode *N) {
// Pattern: (X86sub_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
// Emits: (SUB64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode()) &&
Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -56379,9 +56531,9 @@ SDNode *Select_X86ISD_SUB_i64(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86sub_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Emits: (SUB64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
@@ -56408,39 +56560,39 @@ SDNode *Select_X86ISD_SUB_i64(const SDValue &N) {
return Result;
}
-DISABLE_INLINE SDNode *Emit_309(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_305(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SmallVector<SDValue, 8> Ops0;
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i32);
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
Ops0.push_back(N1);
Ops0.push_back(Tmp1);
- for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
- Ops0.push_back(N.getOperand(i));
+ for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands()-(HasInFlag?1:0); i != e; ++i) {
+ Ops0.push_back(N->getOperand(i));
}
Ops0.push_back(Chain);
if (HasInFlag)
Ops0.push_back(InFlag);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, &Ops0[0], Ops0.size());
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, &Ops0[0], Ops0.size());
}
-SDNode *Select_X86ISD_TC_RETURN(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_X86ISD_TC_RETURN(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Pattern: (X86tcret:isVoid (tglobaladdr:i64):$dst, (imm:i32):$off)
// Emits: (TCRETURNdi64:isVoid (tglobaladdr:i64):$dst, (imm:i32):$off)
// Pattern complexity = 9 cost = 1 size = 3
- if (N1.getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_309(N, X86::TCRETURNdi64, 2);
+ SDNode *Result = Emit_305(N, X86::TCRETURNdi64, 2);
return Result;
}
}
@@ -56448,11 +56600,11 @@ SDNode *Select_X86ISD_TC_RETURN(const SDValue &N) {
// Pattern: (X86tcret:isVoid (texternalsym:i64):$dst, (imm:i32):$off)
// Emits: (TCRETURNdi64:isVoid (texternalsym:i64):$dst, (imm:i32):$off)
// Pattern complexity = 9 cost = 1 size = 3
- if (N1.getOpcode() == ISD::TargetExternalSymbol) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_309(N, X86::TCRETURNdi64, 2);
+ SDNode *Result = Emit_305(N, X86::TCRETURNdi64, 2);
return Result;
}
}
@@ -56460,11 +56612,11 @@ SDNode *Select_X86ISD_TC_RETURN(const SDValue &N) {
// Pattern: (X86tcret:isVoid (tglobaladdr:i32):$dst, (imm:i32):$off)
// Emits: (TCRETURNdi:isVoid (texternalsym:i32):$dst, (imm:i32):$off)
// Pattern complexity = 9 cost = 1 size = 3
- if (N1.getOpcode() == ISD::TargetGlobalAddress) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_309(N, X86::TCRETURNdi, 2);
+ SDNode *Result = Emit_305(N, X86::TCRETURNdi, 2);
return Result;
}
}
@@ -56472,22 +56624,22 @@ SDNode *Select_X86ISD_TC_RETURN(const SDValue &N) {
// Pattern: (X86tcret:isVoid (texternalsym:i32):$dst, (imm:i32):$off)
// Emits: (TCRETURNdi:isVoid (texternalsym:i32):$dst, (imm:i32):$off)
// Pattern complexity = 9 cost = 1 size = 3
- if (N1.getOpcode() == ISD::TargetExternalSymbol) {
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant &&
+ if (N1.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_309(N, X86::TCRETURNdi, 2);
+ SDNode *Result = Emit_305(N, X86::TCRETURNdi, 2);
return Result;
}
}
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86tcret:isVoid GR64:i64:$dst, (imm:i32):$off)
// Emits: (TCRETURNri64:isVoid GR64:i64:$dst, (imm:i32):$off)
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_309(N, X86::TCRETURNri64, 2);
+ SDNode *Result = Emit_305(N, X86::TCRETURNri64, 2);
return Result;
}
@@ -56495,7 +56647,7 @@ SDNode *Select_X86ISD_TC_RETURN(const SDValue &N) {
// Emits: (TCRETURNri:isVoid GR32:i32:$dst, (imm:i32):$off)
// Pattern complexity = 6 cost = 1 size = 3
if (N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_309(N, X86::TCRETURNri, 2);
+ SDNode *Result = Emit_305(N, X86::TCRETURNri, 2);
return Result;
}
}
@@ -56504,21 +56656,21 @@ SDNode *Select_X86ISD_TC_RETURN(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_310(const SDValue &N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- bool HasInFlag = (N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag);
+DISABLE_INLINE SDNode *Emit_306(SDNode *N, unsigned Opc0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ bool HasInFlag = (N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag);
SDValue InFlag(0, 0);
if (HasInFlag) {
- InFlag = N.getOperand(N.getNumOperands()-1);
+ InFlag = N->getOperand(N->getNumOperands()-1);
}
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, Chain, InFlag };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 6 : 5);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, MVT::Other, MVT::Flag, Ops0, HasInFlag ? 6 : 5);
Chain = SDValue(ResNode, 0);
InFlag = SDValue(ResNode, 1);
const SDValue Froms[] = {
- SDValue(N.getNode(), 1),
- SDValue(N.getNode(), 0)
+ SDValue(N, 1),
+ SDValue(N, 0)
};
const SDValue Tos[] = {
InFlag,
@@ -56527,21 +56679,21 @@ DISABLE_INLINE SDNode *Emit_310(const SDValue &N, unsigned Opc0, SDValue &CPTmpN
ReplaceUses(Froms, Tos, 2);
return ResNode;
}
-SDNode *Select_X86ISD_TLSADDR(const SDValue &N) {
+SDNode *Select_X86ISD_TLSADDR(SDNode *N) {
// Pattern: (X86tlsaddr:isVoid tls32addr:i32:$sym)
// Emits: (TLS_addr32:isVoid tls32addr:i32:$sym)
// Pattern complexity = 18 cost = 1 size = 3
if ((!Subtarget->is64Bit())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
if (SelectTLSADDRAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3) &&
N1.getValueType() == MVT::i32) {
- SDNode *Result = Emit_310(N, X86::TLS_addr32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3);
+ SDNode *Result = Emit_306(N, X86::TLS_addr32, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3);
return Result;
}
}
@@ -56550,15 +56702,15 @@ SDNode *Select_X86ISD_TLSADDR(const SDValue &N) {
// Emits: (TLS_addr64:isVoid tls64addr:i64:$sym)
// Pattern complexity = 18 cost = 1 size = 3
if ((Subtarget->is64Bit())) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
if (SelectTLSADDRAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3) &&
N1.getValueType() == MVT::i64) {
- SDNode *Result = Emit_310(N, X86::TLS_addr64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3);
+ SDNode *Result = Emit_306(N, X86::TLS_addr64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3);
return Result;
}
}
@@ -56567,22 +56719,22 @@ SDNode *Select_X86ISD_TLSADDR(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_UCOMI(const SDValue &N) {
+SDNode *Select_X86ISD_UCOMI(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
// Pattern: (X86ucomi:isVoid VR128:v4f32:$src1, (ld:v4f32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (Int_UCOMISSrm:isVoid VR128:v4f32:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -56590,7 +56742,7 @@ SDNode *Select_X86ISD_UCOMI(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_281(N, X86::Int_UCOMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_276(N, X86::Int_UCOMISSrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -56601,15 +56753,15 @@ SDNode *Select_X86ISD_UCOMI(const SDValue &N) {
// Emits: (Int_UCOMISDrm:isVoid VR128:v2f64:$src1, addr:iPTR:$src2)
// Pattern complexity = 25 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
if (Predicate_unindexedload(N1.getNode()) &&
Predicate_load(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
+ SDValue N11 = N1.getNode()->getOperand(1);
SDValue CPTmpN11_0;
SDValue CPTmpN11_1;
SDValue CPTmpN11_2;
@@ -56617,7 +56769,7 @@ SDNode *Select_X86ISD_UCOMI(const SDValue &N) {
SDValue CPTmpN11_4;
if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4) &&
N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_281(N, X86::Int_UCOMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDNode *Result = Emit_276(N, X86::Int_UCOMISDrm, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
return Result;
}
}
@@ -56629,10 +56781,10 @@ SDNode *Select_X86ISD_UCOMI(const SDValue &N) {
// Emits: (Int_UCOMISSrr:isVoid VR128:v4f32:$src1, VR128:v4f32:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_258(N, X86::Int_UCOMISSrr);
+ SDNode *Result = Emit_253(N, X86::Int_UCOMISSrr);
return Result;
}
}
@@ -56641,10 +56793,10 @@ SDNode *Select_X86ISD_UCOMI(const SDValue &N) {
// Emits: (Int_UCOMISDrr:isVoid VR128:v2f64:$src1, VR128:v2f64:$src2)
// Pattern complexity = 3 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::v2f64) {
- SDNode *Result = Emit_258(N, X86::Int_UCOMISDrr);
+ SDNode *Result = Emit_253(N, X86::Int_UCOMISDrr);
return Result;
}
}
@@ -56653,31 +56805,31 @@ SDNode *Select_X86ISD_UCOMI(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_311(const SDValue &N, unsigned Opc0, unsigned NumInputRootOps) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- SDValue N3 = N.getOperand(3);
+DISABLE_INLINE SDNode *Emit_307(SDNode *N, unsigned Opc0, unsigned NumInputRootOps) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ SDValue N3 = N->getOperand(3);
SmallVector<SDValue, 8> Ops0;
SDValue Tmp1 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N2)->getZExtValue()), MVT::i64);
SDValue Tmp2 = CurDAG->getTargetConstant(((uint64_t) cast<ConstantSDNode>(N3)->getZExtValue()), MVT::i64);
Ops0.push_back(N1);
Ops0.push_back(Tmp1);
Ops0.push_back(Tmp2);
- for (unsigned i = NumInputRootOps + 1, e = N.getNumOperands(); i != e; ++i) {
- Ops0.push_back(N.getOperand(i));
+ for (unsigned i = NumInputRootOps + 1, e = N->getNumOperands(); i != e; ++i) {
+ Ops0.push_back(N->getOperand(i));
}
Ops0.push_back(Chain);
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, MVT::Other, &Ops0[0], Ops0.size());
+ return CurDAG->SelectNodeTo(N, Opc0, MVT::Other, &Ops0[0], Ops0.size());
}
-SDNode *Select_X86ISD_VASTART_SAVE_XMM_REGS(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- SDValue N2 = N.getOperand(2);
- if (N2.getOpcode() == ISD::Constant) {
- SDValue N3 = N.getOperand(3);
- if (N3.getOpcode() == ISD::Constant) {
- SDNode *Result = Emit_311(N, X86::VASTART_SAVE_XMM_REGS, 3);
+SDNode *Select_X86ISD_VASTART_SAVE_XMM_REGS(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ SDValue N2 = N->getOperand(2);
+ if (N2.getNode()->getOpcode() == ISD::Constant) {
+ SDValue N3 = N->getOperand(3);
+ if (N3.getNode()->getOpcode() == ISD::Constant) {
+ SDNode *Result = Emit_307(N, X86::VASTART_SAVE_XMM_REGS, 3);
return Result;
}
}
@@ -56686,12 +56838,12 @@ SDNode *Select_X86ISD_VASTART_SAVE_XMM_REGS(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_VSHL_v1i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+SDNode *Select_X86ISD_VSHL_v1i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_95(N, X86::MMX_PSLLQri, MVT::v1i64);
+ SDNode *Result = Emit_94(N, X86::MMX_PSLLQri, MVT::v1i64);
return Result;
}
@@ -56699,13 +56851,13 @@ SDNode *Select_X86ISD_VSHL_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_VSHL_v2i64(const SDValue &N) {
+SDNode *Select_X86ISD_VSHL_v2i64(SDNode *N) {
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_294(N, X86::PSLLDQri, MVT::v2i64);
+ SDNode *Result = Emit_289(N, X86::PSLLDQri, MVT::v2i64);
return Result;
}
}
@@ -56714,12 +56866,12 @@ SDNode *Select_X86ISD_VSHL_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_VSRL_v1i64(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+SDNode *Select_X86ISD_VSRL_v1i64(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_95(N, X86::MMX_PSRLQri, MVT::v1i64);
+ SDNode *Result = Emit_94(N, X86::MMX_PSRLQri, MVT::v1i64);
return Result;
}
@@ -56727,13 +56879,13 @@ SDNode *Select_X86ISD_VSRL_v1i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_VSRL_v2i64(const SDValue &N) {
+SDNode *Select_X86ISD_VSRL_v2i64(SDNode *N) {
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant &&
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i8) {
- SDNode *Result = Emit_294(N, X86::PSRLDQri, MVT::v2i64);
+ SDNode *Result = Emit_289(N, X86::PSRLDQri, MVT::v2i64);
return Result;
}
}
@@ -56742,22 +56894,22 @@ SDNode *Select_X86ISD_VSRL_v2i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_312(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+DISABLE_INLINE SDNode *Emit_308(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN1_0, SDValue &CPTmpN1_1, SDValue &CPTmpN1_2, SDValue &CPTmpN1_3, SDValue &CPTmpN1_4) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue Ops0[] = { CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4, Chain };
- return CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ return CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
}
-SDNode *Select_X86ISD_VZEXT_LOAD_v2i64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_X86ISD_VZEXT_LOAD_v2i64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_312(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_308(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -56765,16 +56917,16 @@ SDNode *Select_X86ISD_VZEXT_LOAD_v2i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_VZEXT_LOAD_v2f64(const SDValue &N) {
- SDValue Chain = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
+SDNode *Select_X86ISD_VZEXT_LOAD_v2f64(SDNode *N) {
+ SDValue Chain = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
SDValue CPTmpN1_2;
SDValue CPTmpN1_3;
SDValue CPTmpN1_4;
if (SelectAddr(N, N1, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4)) {
- SDNode *Result = Emit_312(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
+ SDNode *Result = Emit_308(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN1_0, CPTmpN1_1, CPTmpN1_2, CPTmpN1_3, CPTmpN1_4);
return Result;
}
@@ -56782,42 +56934,42 @@ SDNode *Select_X86ISD_VZEXT_LOAD_v2f64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_313(const SDValue &N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue Chain00 = N00.getOperand(0);
- SDValue N001 = N00.getOperand(1);
+DISABLE_INLINE SDNode *Emit_309(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT0, SDValue &CPTmpN001_0, SDValue &CPTmpN001_1, SDValue &CPTmpN001_2, SDValue &CPTmpN001_3, SDValue &CPTmpN001_4) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue Chain00 = N00.getNode()->getOperand(0);
+ SDValue N001 = N00.getNode()->getOperand(1);
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
- MemRefs0[0] = cast<MemSDNode>(N00)->getMemOperand();
+ MemRefs0[0] = cast<MemSDNode>(N00.getNode())->getMemOperand();
SDValue Ops0[] = { CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4, Chain00 };
- SDNode *ResNode = CurDAG->SelectNodeTo(N.getNode(), Opc0, VT0, MVT::Other, Ops0, 6);
+ SDNode *ResNode = CurDAG->SelectNodeTo(N, Opc0, VT0, MVT::Other, Ops0, 6);
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
ReplaceUses(SDValue(N00.getNode(), 1), SDValue(ResNode, 1));
return ResNode;
}
-DISABLE_INLINE SDNode *Emit_314(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue Tmp1(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, N0, Tmp1);
+DISABLE_INLINE SDNode *Emit_310(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Tmp1(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, N0, Tmp1);
}
-SDNode *Select_X86ISD_VZEXT_MOVL_v2i32(const SDValue &N) {
+SDNode *Select_X86ISD_VZEXT_MOVL_v2i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
// Pattern: (X86vzmovl:v2i32 (scalar_to_vector:v2i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))
// Emits: (MMX_MOVZDI2PDIrm:v2i32 addr:iPTR:$src)
// Pattern complexity = 48 cost = 1 size = 3
if ((Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_loadi32(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
@@ -56825,7 +56977,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i32(const SDValue &N) {
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
N00.getValueType() == MVT::i32) {
- SDNode *Result = Emit_313(N, X86::MMX_MOVZDI2PDIrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_309(N, X86::MMX_MOVZDI2PDIrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -56836,17 +56988,17 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i32(const SDValue &N) {
// Pattern: (X86vzmovl:v2i32 (bitconvert:v2i32 (ld:v1i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MMX_MOVZDI2PDIrm:v2i32 addr:iPTR:$src)
// Pattern complexity = 48 cost = 1 size = 3
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
@@ -56854,7 +57006,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i32(const SDValue &N) {
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
N00.getValueType() == MVT::v1i64) {
- SDNode *Result = Emit_313(N, X86::MMX_MOVZDI2PDIrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_309(N, X86::MMX_MOVZDI2PDIrm, MVT::v2i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -56866,11 +57018,11 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i32(const SDValue &N) {
// Emits: (MMX_MOVZDI2PDIrr:v2i32 GR32:i32:$src)
// Pattern complexity = 21 cost = 1 size = 3
if ((Subtarget->hasMMX())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
- SDValue N00 = N0.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
if (N00.getValueType() == MVT::i32) {
- SDNode *Result = Emit_163(N, X86::MMX_MOVZDI2PDIrr, MVT::v2i32);
+ SDNode *Result = Emit_160(N, X86::MMX_MOVZDI2PDIrr, MVT::v2i32);
return Result;
}
}
@@ -56879,33 +57031,33 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i32(const SDValue &N) {
// Pattern: (X86vzmovl:v2i32 VR64:v2i32:$src)
// Emits: (MMX_PUNPCKLDQrr:v2i32 VR64:v8i8:$src, (MMX_V_SET0:v8i8))
// Pattern complexity = 18 cost = 2 size = 6
- SDNode *Result = Emit_314(N, X86::MMX_V_SET0, X86::MMX_PUNPCKLDQrr, MVT::v8i8, MVT::v2i32);
+ SDNode *Result = Emit_310(N, X86::MMX_V_SET0, X86::MMX_PUNPCKLDQrr, MVT::v8i8, MVT::v2i32);
return Result;
}
-DISABLE_INLINE SDNode *Emit_315(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp0, N0);
+DISABLE_INLINE SDNode *Emit_311(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue Tmp0(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp0, N0);
}
-SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(const SDValue &N) {
+SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
// Pattern: (X86vzmovl:v4i32 (scalar_to_vector:v4i32 (ld:i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>))
// Emits: (MOVZDI2PDIrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 48 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_loadi32(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
@@ -56913,24 +57065,24 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(const SDValue &N) {
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
N00.getValueType() == MVT::i32) {
- SDNode *Result = Emit_313(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_309(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
}
}
}
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
@@ -56942,7 +57094,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(const SDValue &N) {
// Emits: (MOVZDI2PDIrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 48 cost = 1 size = 3
if (N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_313(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_309(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
@@ -56950,7 +57102,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(const SDValue &N) {
// Emits: (MOVZDI2PDIrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 48 cost = 1 size = 3
if (N00.getValueType() == MVT::v2i64) {
- SDNode *Result = Emit_313(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_309(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -56961,19 +57113,19 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(const SDValue &N) {
// Pattern: (X86vzmovl:v4i32 (ld:v4i32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (MOVZDI2PDIrm:v4i32 addr:iPTR:$src)
// Pattern complexity = 45 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_78(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::MOVZDI2PDIrm, MVT::v4i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -56984,11 +57136,11 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(const SDValue &N) {
// Emits: (MOVZDI2PDIrr:v4i32 GR32:i32:$src)
// Pattern complexity = 21 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
- SDValue N00 = N0.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
if (N00.getValueType() == MVT::i32) {
- SDNode *Result = Emit_163(N, X86::MOVZDI2PDIrr, MVT::v4i32);
+ SDNode *Result = Emit_160(N, X86::MOVZDI2PDIrr, MVT::v4i32);
return Result;
}
}
@@ -56998,7 +57150,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(const SDValue &N) {
// Emits: (MOVLPSrr:v4i32 (V_SET0:v16i8), VR128:v16i8:$src)
// Pattern complexity = 18 cost = 2 size = 6
if ((Subtarget->hasSSE1())) {
- SDNode *Result = Emit_315(N, X86::V_SET0, X86::MOVLPSrr, MVT::v16i8, MVT::v4i32);
+ SDNode *Result = Emit_311(N, X86::V_SET0, X86::MOVLPSrr, MVT::v16i8, MVT::v4i32);
return Result;
}
@@ -57006,25 +57158,25 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(const SDValue &N) {
+SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
// Pattern: (X86vzmovl:v2i64 (scalar_to_vector:v2i64 (ld:i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>))
// Emits: (MOVZQI2PQIrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 48 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode()) &&
Predicate_loadi64(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
@@ -57032,7 +57184,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(const SDValue &N) {
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
N00.getValueType() == MVT::i64) {
- SDNode *Result = Emit_313(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_309(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -57040,17 +57192,17 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(const SDValue &N) {
}
}
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
@@ -57062,7 +57214,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(const SDValue &N) {
// Emits: (MOVZQI2PQIrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 48 cost = 1 size = 3
if (N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_313(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_309(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
@@ -57070,7 +57222,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(const SDValue &N) {
// Emits: (MOVZPQILo2PQIrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 48 cost = 1 size = 3
if (N00.getValueType() == MVT::v4i32) {
- SDNode *Result = Emit_313(N, X86::MOVZPQILo2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_309(N, X86::MOVZPQILo2PQIrm, MVT::v2i64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -57083,20 +57235,20 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(const SDValue &N) {
// Emits: (MOVZPQILo2PQIrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 45 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_78(N, X86::MOVZPQILo2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::MOVZPQILo2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -57106,20 +57258,20 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(const SDValue &N) {
// Pattern: (X86vzmovl:v2i64 (ld:v2i64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (MOVZQI2PQIrm:v2i64 addr:iPTR:$src)
// Pattern complexity = 45 cost = 1 size = 3
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_78(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::MOVZQI2PQIrm, MVT::v2i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -57131,11 +57283,11 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(const SDValue &N) {
// Emits: (MOVZQI2PQIrr:v2i64 GR64:i64:$src)
// Pattern complexity = 21 cost = 1 size = 3
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
- SDValue N00 = N0.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
if (N00.getValueType() == MVT::i64) {
- SDNode *Result = Emit_163(N, X86::MOVZQI2PQIrr, MVT::v2i64);
+ SDNode *Result = Emit_160(N, X86::MOVZQI2PQIrr, MVT::v2i64);
return Result;
}
}
@@ -57144,7 +57296,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(const SDValue &N) {
// Pattern: (X86vzmovl:v2i64 VR128:v2i64:$src)
// Emits: (MOVZPQILo2PQIrr:v2i64 VR128:v2i64:$src)
// Pattern complexity = 18 cost = 1 size = 3
- SDNode *Result = Emit_71(N, X86::MOVZPQILo2PQIrr, MVT::v2i64);
+ SDNode *Result = Emit_72(N, X86::MOVZPQILo2PQIrr, MVT::v2i64);
return Result;
}
@@ -57152,31 +57304,31 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2i64(const SDValue &N) {
return NULL;
}
-DISABLE_INLINE SDNode *Emit_316(const SDValue &N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
- SDValue N0 = N.getOperand(0);
- SDValue N00 = N0.getOperand(0);
- SDValue Tmp0(CurDAG->getMachineNode(Opc0, N.getDebugLoc(), VT0), 0);
- return CurDAG->SelectNodeTo(N.getNode(), Opc1, VT1, Tmp0, N00);
+DISABLE_INLINE SDNode *Emit_312(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::SimpleValueType VT0, MVT::SimpleValueType VT1) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N00 = N0.getNode()->getOperand(0);
+ SDValue Tmp0(CurDAG->getMachineNode(Opc0, N->getDebugLoc(), VT0), 0);
+ return CurDAG->SelectNodeTo(N, Opc1, VT1, Tmp0, N00);
}
-SDNode *Select_X86ISD_VZEXT_MOVL_v4f32(const SDValue &N) {
+SDNode *Select_X86ISD_VZEXT_MOVL_v4f32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
// Pattern: (X86vzmovl:v4f32 (scalar_to_vector:v4f32 (ld:f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf32>>))
// Emits: (MOVZSS2PSrm:v4f32 addr:iPTR:$src)
// Pattern complexity = 48 cost = 1 size = 3
if ((Subtarget->hasSSE1())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode()) &&
Predicate_loadf32(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
@@ -57184,7 +57336,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4f32(const SDValue &N) {
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
N00.getValueType() == MVT::f32) {
- SDNode *Result = Emit_313(N, X86::MOVZSS2PSrm, MVT::v4f32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_309(N, X86::MOVZSS2PSrm, MVT::v4f32, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -57195,20 +57347,20 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4f32(const SDValue &N) {
// Pattern: (X86vzmovl:v4f32 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (MOVZSS2PSrm:v4f32 addr:iPTR:$src)
// Pattern complexity = 25 cost = 1 size = 3
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::LOAD &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_78(N, X86::MOVZSS2PSrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::MOVZSS2PSrm, MVT::v4f32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -57220,11 +57372,11 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4f32(const SDValue &N) {
// Emits: (MOVLSS2PSrr:v4f32 (V_SET0:v16i8), FR32:f32:$src)
// Pattern complexity = 21 cost = 2 size = 6
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
- SDValue N00 = N0.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
if (N00.getValueType() == MVT::f32) {
- SDNode *Result = Emit_316(N, X86::V_SET0, X86::MOVLSS2PSrr, MVT::v16i8, MVT::v4f32);
+ SDNode *Result = Emit_312(N, X86::V_SET0, X86::MOVLSS2PSrr, MVT::v16i8, MVT::v4f32);
return Result;
}
}
@@ -57233,7 +57385,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4f32(const SDValue &N) {
// Pattern: (X86vzmovl:v4f32 VR128:v4f32:$src)
// Emits: (MOVLPSrr:v4f32 (V_SET0:v16i8), VR128:v16i8:$src)
// Pattern complexity = 18 cost = 2 size = 6
- SDNode *Result = Emit_315(N, X86::V_SET0, X86::MOVLPSrr, MVT::v16i8, MVT::v4f32);
+ SDNode *Result = Emit_311(N, X86::V_SET0, X86::MOVLPSrr, MVT::v16i8, MVT::v4f32);
return Result;
}
@@ -57241,25 +57393,25 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v4f32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_VZEXT_MOVL_v2f64(const SDValue &N) {
+SDNode *Select_X86ISD_VZEXT_MOVL_v2f64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
// Pattern: (X86vzmovl:v2f64 (scalar_to_vector:v2f64 (ld:f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadf64>>))
// Emits: (MOVZSD2PDrm:v2f64 addr:iPTR:$src)
// Pattern complexity = 48 cost = 1 size = 3
if ((Subtarget->hasSSE2())) {
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR &&
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode()) &&
Predicate_loadf64(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
@@ -57267,28 +57419,28 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2f64(const SDValue &N) {
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
N00.getValueType() == MVT::f64) {
- SDNode *Result = Emit_313(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_309(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
}
}
}
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (X86vzmovl:v2f64 (bitconvert:v2f64 (ld:v4f32 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>))
// Emits: (MOVZSD2PDrm:v2f64 addr:iPTR:$src)
// Pattern complexity = 48 cost = 1 size = 3
- if (N0.getOpcode() == ISD::BIT_CONVERT &&
+ if (N0.getNode()->getOpcode() == ISD::BIT_CONVERT &&
N0.hasOneUse()) {
- SDValue N00 = N0.getOperand(0);
- if (N00.getOpcode() == ISD::LOAD &&
+ SDValue N00 = N0.getNode()->getOperand(0);
+ if (N00.getNode()->getOpcode() == ISD::LOAD &&
N00.hasOneUse() &&
- IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N.getNode())) {
- SDValue Chain00 = N00.getOperand(0);
+ IsLegalAndProfitableToFold(N00.getNode(), N0.getNode(), N)) {
+ SDValue Chain00 = N00.getNode()->getOperand(0);
if (Predicate_unindexedload(N00.getNode()) &&
Predicate_load(N00.getNode())) {
- SDValue N001 = N00.getOperand(1);
+ SDValue N001 = N00.getNode()->getOperand(1);
SDValue CPTmpN001_0;
SDValue CPTmpN001_1;
SDValue CPTmpN001_2;
@@ -57296,7 +57448,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2f64(const SDValue &N) {
SDValue CPTmpN001_4;
if (SelectAddr(N, N001, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4) &&
N00.getValueType() == MVT::v4f32) {
- SDNode *Result = Emit_313(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
+ SDNode *Result = Emit_309(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN001_0, CPTmpN001_1, CPTmpN001_2, CPTmpN001_3, CPTmpN001_4);
return Result;
}
}
@@ -57306,19 +57458,19 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2f64(const SDValue &N) {
// Pattern: (X86vzmovl:v2f64 (ld:v2f64 addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
// Emits: (MOVZSD2PDrm:v2f64 addr:iPTR:$src)
// Pattern complexity = 45 cost = 1 size = 3
- if (N0.getOpcode() == ISD::LOAD &&
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse()) {
- SDValue Chain0 = N0.getOperand(0);
+ SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
- SDValue N01 = N0.getOperand(1);
+ SDValue N01 = N0.getNode()->getOperand(1);
SDValue CPTmpN01_0;
SDValue CPTmpN01_1;
SDValue CPTmpN01_2;
SDValue CPTmpN01_3;
SDValue CPTmpN01_4;
if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
- SDNode *Result = Emit_78(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
+ SDNode *Result = Emit_79(N, X86::MOVZSD2PDrm, MVT::v2f64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -57330,11 +57482,11 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2f64(const SDValue &N) {
// Emits: (MOVLSD2PDrr:v2f64 (V_SET0:v16i8), FR64:f64:$src)
// Pattern complexity = 21 cost = 2 size = 6
{
- SDValue N0 = N.getOperand(0);
- if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
- SDValue N00 = N0.getOperand(0);
+ SDValue N0 = N->getOperand(0);
+ if (N0.getNode()->getOpcode() == ISD::SCALAR_TO_VECTOR) {
+ SDValue N00 = N0.getNode()->getOperand(0);
if (N00.getValueType() == MVT::f64) {
- SDNode *Result = Emit_316(N, X86::V_SET0, X86::MOVLSD2PDrr, MVT::v16i8, MVT::v2f64);
+ SDNode *Result = Emit_312(N, X86::V_SET0, X86::MOVLSD2PDrr, MVT::v16i8, MVT::v2f64);
return Result;
}
}
@@ -57343,7 +57495,7 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2f64(const SDValue &N) {
// Pattern: (X86vzmovl:v2f64 VR128:v2f64:$src)
// Emits: (MOVZPQILo2PQIrr:v2f64 VR128:v16i8:$src)
// Pattern complexity = 3 cost = 1 size = 3
- SDNode *Result = Emit_71(N, X86::MOVZPQILo2PQIrr, MVT::v2f64);
+ SDNode *Result = Emit_72(N, X86::MOVZPQILo2PQIrr, MVT::v2f64);
return Result;
}
@@ -57351,54 +57503,54 @@ SDNode *Select_X86ISD_VZEXT_MOVL_v2f64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_Wrapper_i32(const SDValue &N) {
- SDValue N0 = N.getOperand(0);
+SDNode *Select_X86ISD_Wrapper_i32(SDNode *N) {
+ SDValue N0 = N->getOperand(0);
// Pattern: (X86Wrapper:i32 (tconstpool:i32):$dst)
// Emits: (MOV32ri:i32 (tconstpool:i32):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_71(N, X86::MOV32ri, MVT::i32);
+ if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_72(N, X86::MOV32ri, MVT::i32);
return Result;
}
// Pattern: (X86Wrapper:i32 (tjumptable:i32):$dst)
// Emits: (MOV32ri:i32 (tjumptable:i32):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetJumpTable) {
- SDNode *Result = Emit_71(N, X86::MOV32ri, MVT::i32);
+ if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDNode *Result = Emit_72(N, X86::MOV32ri, MVT::i32);
return Result;
}
// Pattern: (X86Wrapper:i32 (tglobaltlsaddr:i32):$dst)
// Emits: (MOV32ri:i32 (tglobaltlsaddr:i32):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetGlobalTLSAddress) {
- SDNode *Result = Emit_71(N, X86::MOV32ri, MVT::i32);
+ if (N0.getNode()->getOpcode() == ISD::TargetGlobalTLSAddress) {
+ SDNode *Result = Emit_72(N, X86::MOV32ri, MVT::i32);
return Result;
}
// Pattern: (X86Wrapper:i32 (tglobaladdr:i32):$dst)
// Emits: (MOV32ri:i32 (tglobaladdr:i32):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_71(N, X86::MOV32ri, MVT::i32);
+ if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_72(N, X86::MOV32ri, MVT::i32);
return Result;
}
// Pattern: (X86Wrapper:i32 (texternalsym:i32):$dst)
// Emits: (MOV32ri:i32 (texternalsym:i32):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetExternalSymbol) {
- SDNode *Result = Emit_71(N, X86::MOV32ri, MVT::i32);
+ if (N0.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
+ SDNode *Result = Emit_72(N, X86::MOV32ri, MVT::i32);
return Result;
}
// Pattern: (X86Wrapper:i32 (tblockaddress:i32):$dst)
// Emits: (MOV32ri:i32 (tblockaddress:i32):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetBlockAddress) {
- SDNode *Result = Emit_71(N, X86::MOV32ri, MVT::i32);
+ if (N0.getNode()->getOpcode() == ISD::TargetBlockAddress) {
+ SDNode *Result = Emit_72(N, X86::MOV32ri, MVT::i32);
return Result;
}
@@ -57406,133 +57558,133 @@ SDNode *Select_X86ISD_Wrapper_i32(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_Wrapper_i64(const SDValue &N) {
+SDNode *Select_X86ISD_Wrapper_i64(SDNode *N) {
if ((TM.getCodeModel() != CodeModel::Small &&TM.getCodeModel() != CodeModel::Kernel)) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (X86Wrapper:i64 (tconstpool:i64):$dst)
// Emits: (MOV64ri:i64 (tconstpool:i64):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_71(N, X86::MOV64ri, MVT::i64);
+ if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_72(N, X86::MOV64ri, MVT::i64);
return Result;
}
// Pattern: (X86Wrapper:i64 (tjumptable:i64):$dst)
// Emits: (MOV64ri:i64 (tjumptable:i64):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetJumpTable) {
- SDNode *Result = Emit_71(N, X86::MOV64ri, MVT::i64);
+ if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDNode *Result = Emit_72(N, X86::MOV64ri, MVT::i64);
return Result;
}
// Pattern: (X86Wrapper:i64 (tglobaladdr:i64):$dst)
// Emits: (MOV64ri:i64 (tglobaladdr:i64):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_71(N, X86::MOV64ri, MVT::i64);
+ if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_72(N, X86::MOV64ri, MVT::i64);
return Result;
}
// Pattern: (X86Wrapper:i64 (texternalsym:i64):$dst)
// Emits: (MOV64ri:i64 (texternalsym:i64):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetExternalSymbol) {
- SDNode *Result = Emit_71(N, X86::MOV64ri, MVT::i64);
+ if (N0.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
+ SDNode *Result = Emit_72(N, X86::MOV64ri, MVT::i64);
return Result;
}
// Pattern: (X86Wrapper:i64 (tblockaddress:i64):$dst)
// Emits: (MOV64ri:i64 (tblockaddress:i64):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetBlockAddress) {
- SDNode *Result = Emit_71(N, X86::MOV64ri, MVT::i64);
+ if (N0.getNode()->getOpcode() == ISD::TargetBlockAddress) {
+ SDNode *Result = Emit_72(N, X86::MOV64ri, MVT::i64);
return Result;
}
}
if ((TM.getCodeModel() == CodeModel::Small)) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (X86Wrapper:i64 (tconstpool:i64):$dst)
// Emits: (MOV64ri64i32:i64 (tconstpool:i64):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_71(N, X86::MOV64ri64i32, MVT::i64);
+ if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_72(N, X86::MOV64ri64i32, MVT::i64);
return Result;
}
// Pattern: (X86Wrapper:i64 (tjumptable:i64):$dst)
// Emits: (MOV64ri64i32:i64 (tjumptable:i64):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetJumpTable) {
- SDNode *Result = Emit_71(N, X86::MOV64ri64i32, MVT::i64);
+ if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDNode *Result = Emit_72(N, X86::MOV64ri64i32, MVT::i64);
return Result;
}
// Pattern: (X86Wrapper:i64 (tglobaladdr:i64):$dst)
// Emits: (MOV64ri64i32:i64 (tglobaladdr:i64):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_71(N, X86::MOV64ri64i32, MVT::i64);
+ if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_72(N, X86::MOV64ri64i32, MVT::i64);
return Result;
}
// Pattern: (X86Wrapper:i64 (texternalsym:i64):$dst)
// Emits: (MOV64ri64i32:i64 (texternalsym:i64):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetExternalSymbol) {
- SDNode *Result = Emit_71(N, X86::MOV64ri64i32, MVT::i64);
+ if (N0.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
+ SDNode *Result = Emit_72(N, X86::MOV64ri64i32, MVT::i64);
return Result;
}
// Pattern: (X86Wrapper:i64 (tblockaddress:i64):$dst)
// Emits: (MOV64ri64i32:i64 (tblockaddress:i64):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetBlockAddress) {
- SDNode *Result = Emit_71(N, X86::MOV64ri64i32, MVT::i64);
+ if (N0.getNode()->getOpcode() == ISD::TargetBlockAddress) {
+ SDNode *Result = Emit_72(N, X86::MOV64ri64i32, MVT::i64);
return Result;
}
}
if ((TM.getCodeModel() == CodeModel::Kernel)) {
- SDValue N0 = N.getOperand(0);
+ SDValue N0 = N->getOperand(0);
// Pattern: (X86Wrapper:i64 (tconstpool:i64):$dst)
// Emits: (MOV64ri32:i64 (tconstpool:i64):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetConstantPool) {
- SDNode *Result = Emit_71(N, X86::MOV64ri32, MVT::i64);
+ if (N0.getNode()->getOpcode() == ISD::TargetConstantPool) {
+ SDNode *Result = Emit_72(N, X86::MOV64ri32, MVT::i64);
return Result;
}
// Pattern: (X86Wrapper:i64 (tjumptable:i64):$dst)
// Emits: (MOV64ri32:i64 (tjumptable:i64):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetJumpTable) {
- SDNode *Result = Emit_71(N, X86::MOV64ri32, MVT::i64);
+ if (N0.getNode()->getOpcode() == ISD::TargetJumpTable) {
+ SDNode *Result = Emit_72(N, X86::MOV64ri32, MVT::i64);
return Result;
}
// Pattern: (X86Wrapper:i64 (tglobaladdr:i64):$dst)
// Emits: (MOV64ri32:i64 (tglobaladdr:i64):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetGlobalAddress) {
- SDNode *Result = Emit_71(N, X86::MOV64ri32, MVT::i64);
+ if (N0.getNode()->getOpcode() == ISD::TargetGlobalAddress) {
+ SDNode *Result = Emit_72(N, X86::MOV64ri32, MVT::i64);
return Result;
}
// Pattern: (X86Wrapper:i64 (texternalsym:i64):$dst)
// Emits: (MOV64ri32:i64 (texternalsym:i64):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetExternalSymbol) {
- SDNode *Result = Emit_71(N, X86::MOV64ri32, MVT::i64);
+ if (N0.getNode()->getOpcode() == ISD::TargetExternalSymbol) {
+ SDNode *Result = Emit_72(N, X86::MOV64ri32, MVT::i64);
return Result;
}
// Pattern: (X86Wrapper:i64 (tblockaddress:i64):$dst)
// Emits: (MOV64ri32:i64 (tblockaddress:i64):$dst)
// Pattern complexity = 6 cost = 1 size = 3
- if (N0.getOpcode() == ISD::TargetBlockAddress) {
- SDNode *Result = Emit_71(N, X86::MOV64ri32, MVT::i64);
+ if (N0.getNode()->getOpcode() == ISD::TargetBlockAddress) {
+ SDNode *Result = Emit_72(N, X86::MOV64ri32, MVT::i64);
return Result;
}
}
@@ -57541,12 +57693,12 @@ SDNode *Select_X86ISD_Wrapper_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_WrapperRIP_i64(const SDValue &N) {
+SDNode *Select_X86ISD_WrapperRIP_i64(SDNode *N) {
SDValue CPTmpN_0;
SDValue CPTmpN_1;
SDValue CPTmpN_2;
SDValue CPTmpN_3;
- if (SelectLEAAddr(N, N, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
+ if (SelectLEAAddr(N, SDValue(N, 0), CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3)) {
SDNode *Result = Emit_7(N, X86::LEA64r, MVT::i64, CPTmpN_0, CPTmpN_1, CPTmpN_2, CPTmpN_3);
return Result;
}
@@ -57555,29 +57707,54 @@ SDNode *Select_X86ISD_WrapperRIP_i64(const SDValue &N) {
return NULL;
}
-SDNode *Select_X86ISD_XOR_i8(const SDValue &N) {
-
- // Pattern: (X86xor_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
- // Emits: (XOR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+SDNode *Select_X86ISD_XOR_i8(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi8(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::XOR8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86xor_flag:i8 GR8:i8:$src1, (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>)
+ // Emits: (XOR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi8(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::XOR8rm, MVT::i8, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86xor_flag:i8 (ld:i8 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi8>>, GR8:i8:$src1)
+ // Emits: (XOR8rm:i8 GR8:i8:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadi8(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::XOR8rm, MVT::i8, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
@@ -57588,9 +57765,9 @@ SDNode *Select_X86ISD_XOR_i8(const SDValue &N) {
// Emits: (XOR8ri:i8 GR8:i8:$src1, (imm:i8):$src2)
// Pattern complexity = 6 cost = 1 size = 3
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_3(N, X86::XOR8ri, MVT::i8);
return Result;
}
@@ -57603,37 +57780,61 @@ SDNode *Select_X86ISD_XOR_i8(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_XOR_i16(const SDValue &N) {
-
- // Pattern: (X86xor_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
- // Emits: (XOR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+SDNode *Select_X86ISD_XOR_i16(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi16(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::XOR16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86xor_flag:i16 GR16:i16:$src1, (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>)
+ // Emits: (XOR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi16(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::XOR16rm, MVT::i16, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86xor_flag:i16 (ld:i16 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, GR16:i16:$src1)
+ // Emits: (XOR16rm:i16 GR16:i16:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi16(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::XOR16rm, MVT::i16, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86xor_flag:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
// Emits: (XOR16ri8:i16 GR16:i16:$src1, (imm:i16)<<P:Predicate_i16immSExt8>>:$src2)
@@ -57658,37 +57859,61 @@ SDNode *Select_X86ISD_XOR_i16(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_XOR_i32(const SDValue &N) {
-
- // Pattern: (X86xor_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
- // Emits: (XOR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+SDNode *Select_X86ISD_XOR_i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_loadi32(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::XOR32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86xor_flag:i32 GR32:i32:$src1, (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>)
+ // Emits: (XOR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_loadi32(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::XOR32rm, MVT::i32, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86xor_flag:i32 (ld:i32 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, GR32:i32:$src1)
+ // Emits: (XOR32rm:i32 GR32:i32:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_loadi32(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::XOR32rm, MVT::i32, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86xor_flag:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
// Emits: (XOR32ri8:i32 GR32:i32:$src1, (imm:i32)<<P:Predicate_i32immSExt8>>:$src2)
@@ -57713,38 +57938,63 @@ SDNode *Select_X86ISD_XOR_i32(const SDValue &N) {
return Result;
}
-SDNode *Select_X86ISD_XOR_i64(const SDValue &N) {
-
- // Pattern: (X86xor_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
- // Emits: (XOR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
- // Pattern complexity = 25 cost = 1 size = 3
+SDNode *Select_X86ISD_XOR_i64(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::LOAD &&
- N1.hasOneUse() &&
- IsLegalAndProfitableToFold(N1.getNode(), N.getNode(), N.getNode())) {
- SDValue Chain1 = N1.getOperand(0);
- if (Predicate_unindexedload(N1.getNode()) &&
- Predicate_load(N1.getNode()) &&
- Predicate_loadi64(N1.getNode())) {
- SDValue N11 = N1.getOperand(1);
- SDValue CPTmpN11_0;
- SDValue CPTmpN11_1;
- SDValue CPTmpN11_2;
- SDValue CPTmpN11_3;
- SDValue CPTmpN11_4;
- if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
- SDNode *Result = Emit_2(N, X86::XOR64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ SDValue N0 = N->getOperand(0);
+
+ // Pattern: (X86xor_flag:i64 GR64:i64:$src1, (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>)
+ // Emits: (XOR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ {
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::LOAD &&
+ N1.hasOneUse() &&
+ IsLegalAndProfitableToFold(N1.getNode(), N, N)) {
+ SDValue Chain1 = N1.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N1.getNode()) &&
+ Predicate_load(N1.getNode()) &&
+ Predicate_loadi64(N1.getNode())) {
+ SDValue N11 = N1.getNode()->getOperand(1);
+ SDValue CPTmpN11_0;
+ SDValue CPTmpN11_1;
+ SDValue CPTmpN11_2;
+ SDValue CPTmpN11_3;
+ SDValue CPTmpN11_4;
+ if (SelectAddr(N, N11, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4)) {
+ SDNode *Result = Emit_2(N, X86::XOR64rm, MVT::i64, CPTmpN11_0, CPTmpN11_1, CPTmpN11_2, CPTmpN11_3, CPTmpN11_4);
+ return Result;
+ }
+ }
+ }
+ }
+
+ // Pattern: (X86xor_flag:i64 (ld:i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_loadi64>>, GR64:i64:$src1)
+ // Emits: (XOR64rm:i64 GR64:i64:$src1, addr:iPTR:$src2)
+ // Pattern complexity = 25 cost = 1 size = 3
+ if (N0.getNode()->getOpcode() == ISD::LOAD &&
+ N0.hasOneUse() &&
+ IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
+ SDValue Chain0 = N0.getNode()->getOperand(0);
+ if (Predicate_unindexedload(N0.getNode()) &&
+ Predicate_load(N0.getNode()) &&
+ Predicate_loadi64(N0.getNode())) {
+ SDValue N01 = N0.getNode()->getOperand(1);
+ SDValue CPTmpN01_0;
+ SDValue CPTmpN01_1;
+ SDValue CPTmpN01_2;
+ SDValue CPTmpN01_3;
+ SDValue CPTmpN01_4;
+ if (SelectAddr(N, N01, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4)) {
+ SDNode *Result = Emit_4(N, X86::XOR64rm, MVT::i64, CPTmpN01_0, CPTmpN01_1, CPTmpN01_2, CPTmpN01_3, CPTmpN01_4);
return Result;
}
}
}
}
{
- SDValue N0 = N.getOperand(0);
- SDValue N1 = N.getOperand(1);
- if (N1.getOpcode() == ISD::Constant) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ if (N1.getNode()->getOpcode() == ISD::Constant) {
// Pattern: (X86xor_flag:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
// Emits: (XOR64ri8:i64 GR64:i64:$src1, (imm:i64)<<P:Predicate_i64immSExt8>>:$src2)
@@ -57772,11 +58022,11 @@ SDNode *Select_X86ISD_XOR_i64(const SDValue &N) {
}
// The main instruction selector code.
-SDNode *SelectCode(SDValue N) {
- MVT::SimpleValueType NVT = N.getNode()->getValueType(0).getSimpleVT().SimpleTy;
- switch (N.getOpcode()) {
+SDNode *SelectCode(SDNode *N) {
+ MVT::SimpleValueType NVT = N->getValueType(0).getSimpleVT().SimpleTy;
+ switch (N->getOpcode()) {
default:
- assert(!N.isMachineOpcode() && "Node already selected!");
+ assert(!N->isMachineOpcode() && "Node already selected!");
break;
case ISD::EntryToken: // These nodes remain the same.
case ISD::BasicBlock:
@@ -57798,7 +58048,7 @@ SDNode *SelectCode(SDValue N) {
}
case ISD::AssertSext:
case ISD::AssertZext: {
- ReplaceUses(N, N.getOperand(0));
+ ReplaceUses(SDValue(N, 0), N->getOperand(0));
return NULL;
}
case ISD::INLINEASM: return Select_INLINEASM(N);
@@ -59089,6 +59339,15 @@ SDNode *SelectCode(SDValue N) {
return Select_X86ISD_LCMPXCHG_DAG(N);
break;
}
+ case X86ISD::MOVQ2DQ: {
+ switch (NVT) {
+ case MVT::v2i64:
+ return Select_X86ISD_MOVQ2DQ_v2i64(N);
+ default:
+ break;
+ }
+ break;
+ }
case X86ISD::MUL_IMM: {
switch (NVT) {
case MVT::i32:
@@ -59447,9 +59706,9 @@ SDNode *SelectCode(SDValue N) {
}
} // end of big switch.
- if (N.getOpcode() != ISD::INTRINSIC_W_CHAIN &&
- N.getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
- N.getOpcode() != ISD::INTRINSIC_VOID) {
+ if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
+ N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
+ N->getOpcode() != ISD::INTRINSIC_VOID) {
CannotYetSelect(N);
} else {
CannotYetSelectIntrinsic(N);
diff --git a/libclamav/c++/X86GenFastISel.inc b/libclamav/c++/X86GenFastISel.inc
index a4b1dab..f1bea70 100644
--- a/libclamav/c++/X86GenFastISel.inc
+++ b/libclamav/c++/X86GenFastISel.inc
@@ -44,7 +44,7 @@ unsigned FastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
// Top-level FastEmit function.
-unsigned FastEmit_i(MVT VT, MVT RetVT, ISD::NodeType Opcode, uint64_t imm0) {
+unsigned FastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) {
switch (Opcode) {
case ISD::Constant: return FastEmit_ISD_Constant_i(VT, RetVT, imm0);
default: return 0;
@@ -1234,6 +1234,21 @@ unsigned FastEmit_X86ISD_INC_r(MVT VT, MVT RetVT, unsigned Op0) {
}
}
+// FastEmit functions for X86ISD::MOVQ2DQ.
+
+unsigned FastEmit_X86ISD_MOVQ2DQ_MVT_v1i64_r(MVT RetVT, unsigned Op0) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ return FastEmitInst_r(X86::MMX_MOVQ2DQrr, X86::VR128RegisterClass, Op0);
+}
+
+unsigned FastEmit_X86ISD_MOVQ2DQ_r(MVT VT, MVT RetVT, unsigned Op0) {
+ switch (VT.SimpleTy) {
+ case MVT::v1i64: return FastEmit_X86ISD_MOVQ2DQ_MVT_v1i64_r(RetVT, Op0);
+ default: return 0;
+ }
+}
+
// FastEmit functions for X86ISD::VZEXT_MOVL.
unsigned FastEmit_X86ISD_VZEXT_MOVL_MVT_v2i64_r(MVT RetVT, unsigned Op0) {
@@ -1264,7 +1279,7 @@ unsigned FastEmit_X86ISD_VZEXT_MOVL_r(MVT VT, MVT RetVT, unsigned Op0) {
// Top-level FastEmit function.
-unsigned FastEmit_r(MVT VT, MVT RetVT, ISD::NodeType Opcode, unsigned Op0) {
+unsigned FastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0) {
switch (Opcode) {
case ISD::ANY_EXTEND: return FastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0);
case ISD::BIT_CONVERT: return FastEmit_ISD_BIT_CONVERT_r(VT, RetVT, Op0);
@@ -1291,6 +1306,7 @@ unsigned FastEmit_r(MVT VT, MVT RetVT, ISD::NodeType Opcode, unsigned Op0) {
case X86ISD::FRCP: return FastEmit_X86ISD_FRCP_r(VT, RetVT, Op0);
case X86ISD::FRSQRT: return FastEmit_X86ISD_FRSQRT_r(VT, RetVT, Op0);
case X86ISD::INC: return FastEmit_X86ISD_INC_r(VT, RetVT, Op0);
+ case X86ISD::MOVQ2DQ: return FastEmit_X86ISD_MOVQ2DQ_r(VT, RetVT, Op0);
case X86ISD::VZEXT_MOVL: return FastEmit_X86ISD_VZEXT_MOVL_r(VT, RetVT, Op0);
default: return 0;
}
@@ -1846,7 +1862,7 @@ unsigned FastEmit_X86ISD_XOR_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1)
// Top-level FastEmit function.
-unsigned FastEmit_ri(MVT VT, MVT RetVT, ISD::NodeType Opcode, unsigned Op0, uint64_t imm1) {
+unsigned FastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) {
switch (Opcode) {
case ISD::ADD: return FastEmit_ISD_ADD_ri(VT, RetVT, Op0, imm1);
case ISD::ADDC: return FastEmit_ISD_ADDC_ri(VT, RetVT, Op0, imm1);
@@ -3454,7 +3470,7 @@ unsigned FastEmit_X86ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) {
// Top-level FastEmit function.
-unsigned FastEmit_rr(MVT VT, MVT RetVT, ISD::NodeType Opcode, unsigned Op0, unsigned Op1) {
+unsigned FastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, unsigned Op1) {
switch (Opcode) {
case ISD::ADD: return FastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1);
case ISD::ADDC: return FastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op1);
diff --git a/libclamav/c++/X86GenInstrInfo.inc b/libclamav/c++/X86GenInstrInfo.inc
index 52fe191..85b6478 100644
--- a/libclamav/c++/X86GenInstrInfo.inc
+++ b/libclamav/c++/X86GenInstrInfo.inc
@@ -28,43 +28,44 @@ static const unsigned ImplicitList13[] = { X86::EAX, 0 };
static const TargetRegisterClass* Barriers5[] = { &X86::GR32_ADRegClass, NULL };
static const unsigned ImplicitList14[] = { X86::EAX, X86::EDX, 0 };
static const unsigned ImplicitList15[] = { X86::RAX, 0 };
-static const unsigned ImplicitList16[] = { X86::RAX, X86::RDX, 0 };
-static const unsigned ImplicitList17[] = { X86::AX, X86::DX, 0 };
-static const unsigned ImplicitList18[] = { X86::AX, X86::DX, X86::EFLAGS, 0 };
+static const unsigned ImplicitList16[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, 0 };
+static const unsigned ImplicitList17[] = { X86::RAX, X86::RDX, X86::EFLAGS, 0 };
static const TargetRegisterClass* Barriers6[] = { &X86::CCRRegClass, &X86::GR32_ADRegClass, NULL };
-static const unsigned ImplicitList19[] = { X86::EAX, X86::EDX, X86::EFLAGS, 0 };
-static const unsigned ImplicitList20[] = { X86::RAX, X86::RDX, X86::EFLAGS, 0 };
-static const unsigned ImplicitList21[] = { X86::AL, X86::AH, X86::EFLAGS, 0 };
+static const unsigned ImplicitList18[] = { X86::EAX, X86::EDX, X86::EFLAGS, 0 };
+static const unsigned ImplicitList19[] = { X86::RAX, X86::RDX, 0 };
+static const unsigned ImplicitList20[] = { X86::AX, X86::DX, 0 };
+static const unsigned ImplicitList21[] = { X86::AX, X86::DX, X86::EFLAGS, 0 };
+static const unsigned ImplicitList22[] = { X86::AL, X86::AH, X86::EFLAGS, 0 };
static const TargetRegisterClass* Barriers7[] = { &X86::RFP32RegClass, &X86::RFP64RegClass, &X86::RFP80RegClass, NULL };
-static const unsigned ImplicitList22[] = { X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 0 };
-static const unsigned ImplicitList23[] = { X86::ST0, 0 };
-static const unsigned ImplicitList24[] = { X86::ST1, 0 };
-static const unsigned ImplicitList25[] = { X86::DX, 0 };
-static const unsigned ImplicitList26[] = { X86::AH, 0 };
-static const unsigned ImplicitList27[] = { X86::AX, X86::EFLAGS, 0 };
-static const unsigned ImplicitList28[] = { X86::EAX, X86::EFLAGS, 0 };
-static const unsigned ImplicitList29[] = { X86::RAX, X86::EFLAGS, 0 };
-static const unsigned ImplicitList30[] = { X86::AL, X86::EFLAGS, 0 };
-static const unsigned ImplicitList31[] = { X86::EBP, X86::ESP, 0 };
-static const unsigned ImplicitList32[] = { X86::RBP, X86::RSP, 0 };
-static const unsigned ImplicitList33[] = { X86::EDI, 0 };
-static const unsigned ImplicitList34[] = { X86::RDI, 0 };
-static const unsigned ImplicitList35[] = { X86::DX, X86::AX, 0 };
-static const unsigned ImplicitList36[] = { X86::DX, X86::EAX, 0 };
-static const unsigned ImplicitList37[] = { X86::DX, X86::AL, 0 };
-static const unsigned ImplicitList38[] = { X86::ECX, X86::EFLAGS, 0 };
-static const unsigned ImplicitList39[] = { X86::XMM0, X86::EFLAGS, 0 };
-static const unsigned ImplicitList40[] = { X86::CL, 0 };
-static const unsigned ImplicitList41[] = { X86::ECX, X86::EDI, X86::ESI, 0 };
-static const unsigned ImplicitList42[] = { X86::RCX, X86::RDI, X86::RSI, 0 };
-static const unsigned ImplicitList43[] = { X86::AL, X86::ECX, X86::EDI, 0 };
-static const unsigned ImplicitList44[] = { X86::ECX, X86::EDI, 0 };
-static const unsigned ImplicitList45[] = { X86::EAX, X86::ECX, X86::EDI, 0 };
-static const unsigned ImplicitList46[] = { X86::RAX, X86::RCX, X86::RDI, 0 };
-static const unsigned ImplicitList47[] = { X86::RCX, X86::RDI, 0 };
-static const unsigned ImplicitList48[] = { X86::AX, X86::ECX, X86::EDI, 0 };
+static const unsigned ImplicitList23[] = { X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 0 };
+static const unsigned ImplicitList24[] = { X86::ST0, 0 };
+static const unsigned ImplicitList25[] = { X86::ST1, 0 };
+static const unsigned ImplicitList26[] = { X86::DX, 0 };
+static const unsigned ImplicitList27[] = { X86::AH, 0 };
+static const unsigned ImplicitList28[] = { X86::AX, X86::EFLAGS, 0 };
+static const unsigned ImplicitList29[] = { X86::EAX, X86::EFLAGS, 0 };
+static const unsigned ImplicitList30[] = { X86::RAX, X86::EFLAGS, 0 };
+static const unsigned ImplicitList31[] = { X86::AL, X86::EFLAGS, 0 };
+static const unsigned ImplicitList32[] = { X86::EBP, X86::ESP, 0 };
+static const unsigned ImplicitList33[] = { X86::RBP, X86::RSP, 0 };
+static const unsigned ImplicitList34[] = { X86::EDI, 0 };
+static const unsigned ImplicitList35[] = { X86::RDI, 0 };
+static const unsigned ImplicitList36[] = { X86::DX, X86::AX, 0 };
+static const unsigned ImplicitList37[] = { X86::DX, X86::EAX, 0 };
+static const unsigned ImplicitList38[] = { X86::DX, X86::AL, 0 };
+static const unsigned ImplicitList39[] = { X86::ECX, X86::EFLAGS, 0 };
+static const unsigned ImplicitList40[] = { X86::XMM0, X86::EFLAGS, 0 };
+static const unsigned ImplicitList41[] = { X86::CL, 0 };
+static const unsigned ImplicitList42[] = { X86::ECX, X86::EDI, X86::ESI, 0 };
+static const unsigned ImplicitList43[] = { X86::RCX, X86::RDI, X86::RSI, 0 };
+static const unsigned ImplicitList44[] = { X86::AL, X86::ECX, X86::EDI, 0 };
+static const unsigned ImplicitList45[] = { X86::ECX, X86::EDI, 0 };
+static const unsigned ImplicitList46[] = { X86::EAX, X86::ECX, X86::EDI, 0 };
+static const unsigned ImplicitList47[] = { X86::RAX, X86::RCX, X86::RDI, 0 };
+static const unsigned ImplicitList48[] = { X86::RCX, X86::RDI, 0 };
+static const unsigned ImplicitList49[] = { X86::AX, X86::ECX, X86::EDI, 0 };
static const TargetRegisterClass* Barriers8[] = { &X86::CCRRegClass, &X86::RFP32RegClass, &X86::RFP64RegClass, &X86::RFP80RegClass, &X86::VR64RegClass, NULL };
-static const unsigned ImplicitList49[] = { X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, X86::ST1, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::EFLAGS, 0 };
+static const unsigned ImplicitList50[] = { X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, X86::ST1, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::EFLAGS, 0 };
static const TargetOperandInfo OperandInfo2[] = { { X86::RFP32RegClassID, 0, 0 }, { X86::RFP32RegClassID, 0, 0 }, };
static const TargetOperandInfo OperandInfo3[] = { { X86::RFP64RegClassID, 0, 0 }, { X86::RFP64RegClassID, 0, 0 }, };
@@ -284,2508 +285,2511 @@ static const TargetInstrDesc X86Insts[] = {
{ 8, 1, 1, 0, "IMPLICIT_DEF", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo5 }, // Inst #8 = IMPLICIT_DEF
{ 9, 4, 1, 0, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo202 }, // Inst #9 = SUBREG_TO_REG
{ 10, 3, 1, 0, "COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo76 }, // Inst #10 = COPY_TO_REGCLASS
- { 11, 0, 0, 0, "ABS_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(225<<24), NULL, NULL, NULL, 0 }, // Inst #11 = ABS_F
- { 12, 2, 1, 0, "ABS_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #12 = ABS_Fp32
- { 13, 2, 1, 0, "ABS_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #13 = ABS_Fp64
- { 14, 2, 1, 0, "ABS_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #14 = ABS_Fp80
- { 15, 1, 0, 0, "ADC16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #15 = ADC16i16
- { 16, 6, 0, 0, "ADC16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(2<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #16 = ADC16mi
- { 17, 6, 0, 0, "ADC16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #17 = ADC16mi8
- { 18, 6, 0, 0, "ADC16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #18 = ADC16mr
- { 19, 3, 1, 0, "ADC16ri", 0, 0|18|(1<<6)|(2<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #19 = ADC16ri
- { 20, 3, 1, 0, "ADC16ri8", 0, 0|18|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #20 = ADC16ri8
- { 21, 7, 1, 0, "ADC16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #21 = ADC16rm
- { 22, 3, 1, 0, "ADC16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #22 = ADC16rr
- { 23, 3, 1, 0, "ADC16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #23 = ADC16rr_REV
- { 24, 1, 0, 0, "ADC32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #24 = ADC32i32
- { 25, 6, 0, 0, "ADC32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #25 = ADC32mi
- { 26, 6, 0, 0, "ADC32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #26 = ADC32mi8
- { 27, 6, 0, 0, "ADC32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #27 = ADC32mr
- { 28, 3, 1, 0, "ADC32ri", 0, 0|18|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #28 = ADC32ri
- { 29, 3, 1, 0, "ADC32ri8", 0, 0|18|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #29 = ADC32ri8
- { 30, 7, 1, 0, "ADC32rm", 0|(1<<TID::MayLoad), 0|6|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #30 = ADC32rm
- { 31, 3, 1, 0, "ADC32rr", 0|(1<<TID::Commutable), 0|3|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #31 = ADC32rr
- { 32, 3, 1, 0, "ADC32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #32 = ADC32rr_REV
- { 33, 1, 0, 0, "ADC64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #33 = ADC64i32
- { 34, 6, 0, 0, "ADC64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #34 = ADC64mi32
- { 35, 6, 0, 0, "ADC64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #35 = ADC64mi8
- { 36, 6, 0, 0, "ADC64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #36 = ADC64mr
- { 37, 3, 1, 0, "ADC64ri32", 0, 0|18|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #37 = ADC64ri32
- { 38, 3, 1, 0, "ADC64ri8", 0, 0|18|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #38 = ADC64ri8
- { 39, 7, 1, 0, "ADC64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #39 = ADC64rm
- { 40, 3, 1, 0, "ADC64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #40 = ADC64rr
- { 41, 3, 1, 0, "ADC64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #41 = ADC64rr_REV
- { 42, 1, 0, 0, "ADC8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(20<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #42 = ADC8i8
- { 43, 6, 0, 0, "ADC8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #43 = ADC8mi
- { 44, 6, 0, 0, "ADC8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(16<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #44 = ADC8mr
- { 45, 3, 1, 0, "ADC8ri", 0, 0|18|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #45 = ADC8ri
- { 46, 7, 1, 0, "ADC8rm", 0|(1<<TID::MayLoad), 0|6|(18<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #46 = ADC8rm
- { 47, 3, 1, 0, "ADC8rr", 0|(1<<TID::Commutable), 0|3|(16<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #47 = ADC8rr
- { 48, 3, 1, 0, "ADC8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(18<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #48 = ADC8rr_REV
- { 49, 1, 0, 0, "ADD16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #49 = ADD16i16
- { 50, 6, 0, 0, "ADD16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #50 = ADD16mi
- { 51, 6, 0, 0, "ADD16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #51 = ADD16mi8
- { 52, 6, 0, 0, "ADD16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #52 = ADD16mr
- { 53, 3, 1, 0, "ADD16mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #53 = ADD16mrmrr
- { 54, 3, 1, 0, "ADD16ri", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #54 = ADD16ri
- { 55, 3, 1, 0, "ADD16ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #55 = ADD16ri8
- { 56, 7, 1, 0, "ADD16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #56 = ADD16rm
- { 57, 3, 1, 0, "ADD16rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<6)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #57 = ADD16rr
- { 58, 1, 0, 0, "ADD32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #58 = ADD32i32
- { 59, 6, 0, 0, "ADD32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #59 = ADD32mi
- { 60, 6, 0, 0, "ADD32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #60 = ADD32mi8
- { 61, 6, 0, 0, "ADD32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #61 = ADD32mr
- { 62, 3, 1, 0, "ADD32mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #62 = ADD32mrmrr
- { 63, 3, 1, 0, "ADD32ri", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #63 = ADD32ri
- { 64, 3, 1, 0, "ADD32ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #64 = ADD32ri8
- { 65, 7, 1, 0, "ADD32rm", 0|(1<<TID::MayLoad), 0|6|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #65 = ADD32rm
- { 66, 3, 1, 0, "ADD32rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #66 = ADD32rr
- { 67, 1, 0, 0, "ADD64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #67 = ADD64i32
- { 68, 6, 0, 0, "ADD64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #68 = ADD64mi32
- { 69, 6, 0, 0, "ADD64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #69 = ADD64mi8
- { 70, 6, 0, 0, "ADD64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #70 = ADD64mr
- { 71, 3, 1, 0, "ADD64mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #71 = ADD64mrmrr
- { 72, 3, 1, 0, "ADD64ri32", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #72 = ADD64ri32
- { 73, 3, 1, 0, "ADD64ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #73 = ADD64ri8
- { 74, 7, 1, 0, "ADD64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #74 = ADD64rm
- { 75, 3, 1, 0, "ADD64rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<12)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #75 = ADD64rr
- { 76, 1, 0, 0, "ADD8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(4<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #76 = ADD8i8
- { 77, 6, 0, 0, "ADD8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #77 = ADD8mi
- { 78, 6, 0, 0, "ADD8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4, NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #78 = ADD8mr
- { 79, 3, 1, 0, "ADD8mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(2<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #79 = ADD8mrmrr
- { 80, 3, 1, 0, "ADD8ri", 0, 0|16|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #80 = ADD8ri
- { 81, 7, 1, 0, "ADD8rm", 0|(1<<TID::MayLoad), 0|6|(2<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #81 = ADD8rm
- { 82, 3, 1, 0, "ADD8rr", 0|(1<<TID::Commutable), 0|3, NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #82 = ADD8rr
- { 83, 7, 1, 0, "ADDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #83 = ADDPDrm
- { 84, 3, 1, 0, "ADDPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #84 = ADDPDrr
- { 85, 7, 1, 0, "ADDPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #85 = ADDPSrm
- { 86, 3, 1, 0, "ADDPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #86 = ADDPSrr
- { 87, 7, 1, 0, "ADDSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #87 = ADDSDrm
- { 88, 7, 1, 0, "ADDSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #88 = ADDSDrm_Int
- { 89, 3, 1, 0, "ADDSDrr", 0|(1<<TID::Commutable), 0|5|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #89 = ADDSDrr
- { 90, 3, 1, 0, "ADDSDrr_Int", 0, 0|5|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #90 = ADDSDrr_Int
- { 91, 7, 1, 0, "ADDSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #91 = ADDSSrm
- { 92, 7, 1, 0, "ADDSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #92 = ADDSSrm_Int
- { 93, 3, 1, 0, "ADDSSrr", 0|(1<<TID::Commutable), 0|5|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #93 = ADDSSrr
- { 94, 3, 1, 0, "ADDSSrr_Int", 0, 0|5|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #94 = ADDSSrr_Int
- { 95, 7, 1, 0, "ADDSUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(208<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #95 = ADDSUBPDrm
- { 96, 3, 1, 0, "ADDSUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(208<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #96 = ADDSUBPDrr
- { 97, 7, 1, 0, "ADDSUBPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(208<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #97 = ADDSUBPSrm
- { 98, 3, 1, 0, "ADDSUBPSrr", 0, 0|5|(11<<8)|(208<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #98 = ADDSUBPSrr
- { 99, 5, 0, 0, "ADD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #99 = ADD_F32m
- { 100, 5, 0, 0, "ADD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #100 = ADD_F64m
- { 101, 5, 0, 0, "ADD_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #101 = ADD_FI16m
- { 102, 5, 0, 0, "ADD_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #102 = ADD_FI32m
- { 103, 1, 0, 0, "ADD_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #103 = ADD_FPrST0
- { 104, 1, 0, 0, "ADD_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #104 = ADD_FST0r
- { 105, 3, 1, 0, "ADD_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #105 = ADD_Fp32
- { 106, 7, 1, 0, "ADD_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #106 = ADD_Fp32m
- { 107, 3, 1, 0, "ADD_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #107 = ADD_Fp64
- { 108, 7, 1, 0, "ADD_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #108 = ADD_Fp64m
- { 109, 7, 1, 0, "ADD_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #109 = ADD_Fp64m32
- { 110, 3, 1, 0, "ADD_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #110 = ADD_Fp80
- { 111, 7, 1, 0, "ADD_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #111 = ADD_Fp80m32
- { 112, 7, 1, 0, "ADD_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #112 = ADD_Fp80m64
- { 113, 7, 1, 0, "ADD_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #113 = ADD_FpI16m32
- { 114, 7, 1, 0, "ADD_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #114 = ADD_FpI16m64
- { 115, 7, 1, 0, "ADD_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #115 = ADD_FpI16m80
- { 116, 7, 1, 0, "ADD_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #116 = ADD_FpI32m32
- { 117, 7, 1, 0, "ADD_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #117 = ADD_FpI32m64
- { 118, 7, 1, 0, "ADD_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #118 = ADD_FpI32m80
- { 119, 1, 0, 0, "ADD_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #119 = ADD_FrST0
- { 120, 1, 0, 0, "ADJCALLSTACKDOWN32", 0, 0, ImplicitList2, ImplicitList3, Barriers1, OperandInfo5 }, // Inst #120 = ADJCALLSTACKDOWN32
- { 121, 1, 0, 0, "ADJCALLSTACKDOWN64", 0, 0, ImplicitList4, ImplicitList5, Barriers1, OperandInfo5 }, // Inst #121 = ADJCALLSTACKDOWN64
- { 122, 2, 0, 0, "ADJCALLSTACKUP32", 0, 0, ImplicitList2, ImplicitList3, Barriers1, OperandInfo38 }, // Inst #122 = ADJCALLSTACKUP32
- { 123, 2, 0, 0, "ADJCALLSTACKUP64", 0, 0, ImplicitList4, ImplicitList5, Barriers1, OperandInfo38 }, // Inst #123 = ADJCALLSTACKUP64
- { 124, 1, 0, 0, "AND16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #124 = AND16i16
- { 125, 6, 0, 0, "AND16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #125 = AND16mi
- { 126, 6, 0, 0, "AND16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #126 = AND16mi8
- { 127, 6, 0, 0, "AND16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #127 = AND16mr
- { 128, 3, 1, 0, "AND16ri", 0, 0|20|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #128 = AND16ri
- { 129, 3, 1, 0, "AND16ri8", 0, 0|20|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #129 = AND16ri8
- { 130, 7, 1, 0, "AND16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #130 = AND16rm
- { 131, 3, 1, 0, "AND16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #131 = AND16rr
- { 132, 3, 1, 0, "AND16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #132 = AND16rr_REV
- { 133, 1, 0, 0, "AND32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #133 = AND32i32
- { 134, 6, 0, 0, "AND32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #134 = AND32mi
- { 135, 6, 0, 0, "AND32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #135 = AND32mi8
- { 136, 6, 0, 0, "AND32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #136 = AND32mr
- { 137, 3, 1, 0, "AND32ri", 0, 0|20|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #137 = AND32ri
- { 138, 3, 1, 0, "AND32ri8", 0, 0|20|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #138 = AND32ri8
- { 139, 7, 1, 0, "AND32rm", 0|(1<<TID::MayLoad), 0|6|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #139 = AND32rm
- { 140, 3, 1, 0, "AND32rr", 0|(1<<TID::Commutable), 0|3|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #140 = AND32rr
- { 141, 3, 1, 0, "AND32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #141 = AND32rr_REV
- { 142, 1, 0, 0, "AND64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #142 = AND64i32
- { 143, 6, 0, 0, "AND64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #143 = AND64mi32
- { 144, 6, 0, 0, "AND64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #144 = AND64mi8
- { 145, 6, 0, 0, "AND64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #145 = AND64mr
- { 146, 3, 1, 0, "AND64ri32", 0, 0|20|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #146 = AND64ri32
- { 147, 3, 1, 0, "AND64ri8", 0, 0|20|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #147 = AND64ri8
- { 148, 7, 1, 0, "AND64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #148 = AND64rm
- { 149, 3, 1, 0, "AND64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #149 = AND64rr
- { 150, 3, 1, 0, "AND64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #150 = AND64rr_REV
- { 151, 1, 0, 0, "AND8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(36<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #151 = AND8i8
- { 152, 6, 0, 0, "AND8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #152 = AND8mi
- { 153, 6, 0, 0, "AND8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(32<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #153 = AND8mr
- { 154, 3, 1, 0, "AND8ri", 0, 0|20|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #154 = AND8ri
- { 155, 7, 1, 0, "AND8rm", 0|(1<<TID::MayLoad), 0|6|(34<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #155 = AND8rm
- { 156, 3, 1, 0, "AND8rr", 0|(1<<TID::Commutable), 0|3|(32<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #156 = AND8rr
- { 157, 3, 1, 0, "AND8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(34<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #157 = AND8rr_REV
- { 158, 7, 1, 0, "ANDNPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #158 = ANDNPDrm
- { 159, 3, 1, 0, "ANDNPDrr", 0, 0|5|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #159 = ANDNPDrr
- { 160, 7, 1, 0, "ANDNPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #160 = ANDNPSrm
- { 161, 3, 1, 0, "ANDNPSrr", 0, 0|5|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #161 = ANDNPSrr
- { 162, 7, 1, 0, "ANDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #162 = ANDPDrm
- { 163, 3, 1, 0, "ANDPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #163 = ANDPDrr
- { 164, 7, 1, 0, "ANDPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #164 = ANDPSrm
- { 165, 3, 1, 0, "ANDPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #165 = ANDPSrr
- { 166, 9, 2, 0, "ATOMADD6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #166 = ATOMADD6432
- { 167, 7, 1, 0, "ATOMAND16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #167 = ATOMAND16
- { 168, 7, 1, 0, "ATOMAND32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #168 = ATOMAND32
- { 169, 7, 1, 0, "ATOMAND64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #169 = ATOMAND64
- { 170, 9, 2, 0, "ATOMAND6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #170 = ATOMAND6432
- { 171, 7, 1, 0, "ATOMAND8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo43 }, // Inst #171 = ATOMAND8
- { 172, 7, 1, 0, "ATOMMAX16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #172 = ATOMMAX16
- { 173, 7, 1, 0, "ATOMMAX32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #173 = ATOMMAX32
- { 174, 7, 1, 0, "ATOMMAX64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #174 = ATOMMAX64
- { 175, 7, 1, 0, "ATOMMIN16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #175 = ATOMMIN16
- { 176, 7, 1, 0, "ATOMMIN32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #176 = ATOMMIN32
- { 177, 7, 1, 0, "ATOMMIN64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #177 = ATOMMIN64
- { 178, 7, 1, 0, "ATOMNAND16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #178 = ATOMNAND16
- { 179, 7, 1, 0, "ATOMNAND32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #179 = ATOMNAND32
- { 180, 7, 1, 0, "ATOMNAND64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #180 = ATOMNAND64
- { 181, 9, 2, 0, "ATOMNAND6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #181 = ATOMNAND6432
- { 182, 7, 1, 0, "ATOMNAND8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo43 }, // Inst #182 = ATOMNAND8
- { 183, 7, 1, 0, "ATOMOR16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #183 = ATOMOR16
- { 184, 7, 1, 0, "ATOMOR32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #184 = ATOMOR32
- { 185, 7, 1, 0, "ATOMOR64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #185 = ATOMOR64
- { 186, 9, 2, 0, "ATOMOR6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #186 = ATOMOR6432
- { 187, 7, 1, 0, "ATOMOR8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo43 }, // Inst #187 = ATOMOR8
- { 188, 9, 2, 0, "ATOMSUB6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #188 = ATOMSUB6432
- { 189, 9, 2, 0, "ATOMSWAP6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #189 = ATOMSWAP6432
- { 190, 7, 1, 0, "ATOMUMAX16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #190 = ATOMUMAX16
- { 191, 7, 1, 0, "ATOMUMAX32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #191 = ATOMUMAX32
- { 192, 7, 1, 0, "ATOMUMAX64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #192 = ATOMUMAX64
- { 193, 7, 1, 0, "ATOMUMIN16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #193 = ATOMUMIN16
- { 194, 7, 1, 0, "ATOMUMIN32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #194 = ATOMUMIN32
- { 195, 7, 1, 0, "ATOMUMIN64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #195 = ATOMUMIN64
- { 196, 7, 1, 0, "ATOMXOR16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #196 = ATOMXOR16
- { 197, 7, 1, 0, "ATOMXOR32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #197 = ATOMXOR32
- { 198, 7, 1, 0, "ATOMXOR64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #198 = ATOMXOR64
- { 199, 9, 2, 0, "ATOMXOR6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #199 = ATOMXOR6432
- { 200, 7, 1, 0, "ATOMXOR8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo43 }, // Inst #200 = ATOMXOR8
- { 201, 8, 1, 0, "BLENDPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(13<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #201 = BLENDPDrmi
- { 202, 4, 1, 0, "BLENDPDrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(13<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #202 = BLENDPDrri
- { 203, 8, 1, 0, "BLENDPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(12<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #203 = BLENDPSrmi
- { 204, 4, 1, 0, "BLENDPSrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(12<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #204 = BLENDPSrri
- { 205, 7, 1, 0, "BLENDVPDrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(21<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #205 = BLENDVPDrm0
- { 206, 3, 1, 0, "BLENDVPDrr0", 0, 0|5|(1<<6)|(13<<8)|(21<<24), ImplicitList8, NULL, NULL, OperandInfo25 }, // Inst #206 = BLENDVPDrr0
- { 207, 7, 1, 0, "BLENDVPSrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(20<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #207 = BLENDVPSrm0
- { 208, 3, 1, 0, "BLENDVPSrr0", 0, 0|5|(1<<6)|(13<<8)|(20<<24), ImplicitList8, NULL, NULL, OperandInfo25 }, // Inst #208 = BLENDVPSrr0
- { 209, 6, 1, 0, "BSF16rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #209 = BSF16rm
- { 210, 2, 1, 0, "BSF16rr", 0, 0|5|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #210 = BSF16rr
- { 211, 6, 1, 0, "BSF32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #211 = BSF32rm
- { 212, 2, 1, 0, "BSF32rr", 0, 0|5|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #212 = BSF32rr
- { 213, 6, 1, 0, "BSF64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #213 = BSF64rm
- { 214, 2, 1, 0, "BSF64rr", 0, 0|5|(1<<8)|(1<<12)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #214 = BSF64rr
- { 215, 6, 1, 0, "BSR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #215 = BSR16rm
- { 216, 2, 1, 0, "BSR16rr", 0, 0|5|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #216 = BSR16rr
- { 217, 6, 1, 0, "BSR32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #217 = BSR32rm
- { 218, 2, 1, 0, "BSR32rr", 0, 0|5|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #218 = BSR32rr
- { 219, 6, 1, 0, "BSR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #219 = BSR64rm
- { 220, 2, 1, 0, "BSR64rr", 0, 0|5|(1<<8)|(1<<12)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #220 = BSR64rr
- { 221, 2, 1, 0, "BSWAP32r", 0, 0|2|(1<<8)|(200<<24), NULL, NULL, NULL, OperandInfo52 }, // Inst #221 = BSWAP32r
- { 222, 2, 1, 0, "BSWAP64r", 0, 0|2|(1<<8)|(1<<12)|(200<<24), NULL, NULL, NULL, OperandInfo53 }, // Inst #222 = BSWAP64r
- { 223, 6, 0, 0, "BT16mi8", 0|(1<<TID::MayLoad), 0|28|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #223 = BT16mi8
- { 224, 6, 0, 0, "BT16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #224 = BT16mr
- { 225, 2, 0, 0, "BT16ri8", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #225 = BT16ri8
- { 226, 2, 0, 0, "BT16rr", 0, 0|3|(1<<6)|(1<<8)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #226 = BT16rr
- { 227, 6, 0, 0, "BT32mi8", 0|(1<<TID::MayLoad), 0|28|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #227 = BT32mi8
- { 228, 6, 0, 0, "BT32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #228 = BT32mr
- { 229, 2, 0, 0, "BT32ri8", 0, 0|20|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #229 = BT32ri8
- { 230, 2, 0, 0, "BT32rr", 0, 0|3|(1<<8)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #230 = BT32rr
- { 231, 6, 0, 0, "BT64mi8", 0|(1<<TID::MayLoad), 0|28|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #231 = BT64mi8
- { 232, 6, 0, 0, "BT64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #232 = BT64mr
- { 233, 2, 0, 0, "BT64ri8", 0, 0|20|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #233 = BT64ri8
- { 234, 2, 0, 0, "BT64rr", 0, 0|3|(1<<8)|(1<<12)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #234 = BT64rr
- { 235, 6, 0, 0, "BTC16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #235 = BTC16mi8
- { 236, 6, 0, 0, "BTC16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #236 = BTC16mr
- { 237, 2, 0, 0, "BTC16ri8", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #237 = BTC16ri8
- { 238, 2, 0, 0, "BTC16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #238 = BTC16rr
- { 239, 6, 0, 0, "BTC32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #239 = BTC32mi8
- { 240, 6, 0, 0, "BTC32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #240 = BTC32mr
- { 241, 2, 0, 0, "BTC32ri8", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #241 = BTC32ri8
- { 242, 2, 0, 0, "BTC32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #242 = BTC32rr
- { 243, 6, 0, 0, "BTC64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #243 = BTC64mi8
- { 244, 6, 0, 0, "BTC64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #244 = BTC64mr
- { 245, 2, 0, 0, "BTC64ri8", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #245 = BTC64ri8
- { 246, 2, 0, 0, "BTC64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #246 = BTC64rr
- { 247, 6, 0, 0, "BTR16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #247 = BTR16mi8
- { 248, 6, 0, 0, "BTR16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #248 = BTR16mr
- { 249, 2, 0, 0, "BTR16ri8", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #249 = BTR16ri8
- { 250, 2, 0, 0, "BTR16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #250 = BTR16rr
- { 251, 6, 0, 0, "BTR32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #251 = BTR32mi8
- { 252, 6, 0, 0, "BTR32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #252 = BTR32mr
- { 253, 2, 0, 0, "BTR32ri8", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #253 = BTR32ri8
- { 254, 2, 0, 0, "BTR32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #254 = BTR32rr
- { 255, 6, 0, 0, "BTR64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #255 = BTR64mi8
- { 256, 6, 0, 0, "BTR64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #256 = BTR64mr
- { 257, 2, 0, 0, "BTR64ri8", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #257 = BTR64ri8
- { 258, 2, 0, 0, "BTR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #258 = BTR64rr
- { 259, 6, 0, 0, "BTS16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #259 = BTS16mi8
- { 260, 6, 0, 0, "BTS16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #260 = BTS16mr
- { 261, 2, 0, 0, "BTS16ri8", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #261 = BTS16ri8
- { 262, 2, 0, 0, "BTS16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #262 = BTS16rr
- { 263, 6, 0, 0, "BTS32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #263 = BTS32mi8
- { 264, 6, 0, 0, "BTS32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #264 = BTS32mr
- { 265, 2, 0, 0, "BTS32ri8", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #265 = BTS32ri8
- { 266, 2, 0, 0, "BTS32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #266 = BTS32rr
- { 267, 6, 0, 0, "BTS64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #267 = BTS64mi8
- { 268, 6, 0, 0, "BTS64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #268 = BTS64mr
- { 269, 2, 0, 0, "BTS64ri8", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #269 = BTS64ri8
- { 270, 2, 0, 0, "BTS64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #270 = BTS64rr
- { 271, 5, 0, 0, "CALL32m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo30 }, // Inst #271 = CALL32m
- { 272, 1, 0, 0, "CALL32r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo57 }, // Inst #272 = CALL32r
- { 273, 5, 0, 0, "CALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo30 }, // Inst #273 = CALL64m
- { 274, 1, 0, 0, "CALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(232<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo5 }, // Inst #274 = CALL64pcrel32
- { 275, 1, 0, 0, "CALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo58 }, // Inst #275 = CALL64r
- { 276, 1, 0, 0, "CALLpcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(232<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo5 }, // Inst #276 = CALLpcrel32
- { 277, 0, 0, 0, "CBW", 0, 0|1|(1<<6)|(152<<24), ImplicitList11, ImplicitList12, NULL, 0 }, // Inst #277 = CBW
- { 278, 0, 0, 0, "CDQ", 0, 0|1|(153<<24), ImplicitList13, ImplicitList14, Barriers5, 0 }, // Inst #278 = CDQ
- { 279, 0, 0, 0, "CDQE", 0, 0|1|(1<<12)|(152<<24), ImplicitList13, ImplicitList15, NULL, 0 }, // Inst #279 = CDQE
- { 280, 0, 0, 0, "CHS_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(224<<24), NULL, NULL, NULL, 0 }, // Inst #280 = CHS_F
- { 281, 2, 1, 0, "CHS_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #281 = CHS_Fp32
- { 282, 2, 1, 0, "CHS_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #282 = CHS_Fp64
- { 283, 2, 1, 0, "CHS_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #283 = CHS_Fp80
- { 284, 0, 0, 0, "CLC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(248<<24), NULL, NULL, NULL, 0 }, // Inst #284 = CLC
- { 285, 0, 0, 0, "CLD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(252<<24), NULL, NULL, NULL, 0 }, // Inst #285 = CLD
- { 286, 5, 0, 0, "CLFLUSH", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #286 = CLFLUSH
- { 287, 0, 0, 0, "CLI", 0|(1<<TID::UnmodeledSideEffects), 0|1|(250<<24), NULL, NULL, NULL, 0 }, // Inst #287 = CLI
- { 288, 0, 0, 0, "CLTS", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(6<<24), NULL, NULL, NULL, 0 }, // Inst #288 = CLTS
- { 289, 0, 0, 0, "CMC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(245<<24), NULL, NULL, NULL, 0 }, // Inst #289 = CMC
- { 290, 7, 1, 0, "CMOVA16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #290 = CMOVA16rm
- { 291, 3, 1, 0, "CMOVA16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #291 = CMOVA16rr
- { 292, 7, 1, 0, "CMOVA32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #292 = CMOVA32rm
- { 293, 3, 1, 0, "CMOVA32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #293 = CMOVA32rr
- { 294, 7, 1, 0, "CMOVA64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #294 = CMOVA64rm
- { 295, 3, 1, 0, "CMOVA64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #295 = CMOVA64rr
- { 296, 7, 1, 0, "CMOVAE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #296 = CMOVAE16rm
- { 297, 3, 1, 0, "CMOVAE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #297 = CMOVAE16rr
- { 298, 7, 1, 0, "CMOVAE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #298 = CMOVAE32rm
- { 299, 3, 1, 0, "CMOVAE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #299 = CMOVAE32rr
- { 300, 7, 1, 0, "CMOVAE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #300 = CMOVAE64rm
- { 301, 3, 1, 0, "CMOVAE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #301 = CMOVAE64rr
- { 302, 7, 1, 0, "CMOVB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #302 = CMOVB16rm
- { 303, 3, 1, 0, "CMOVB16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #303 = CMOVB16rr
- { 304, 7, 1, 0, "CMOVB32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #304 = CMOVB32rm
- { 305, 3, 1, 0, "CMOVB32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #305 = CMOVB32rr
- { 306, 7, 1, 0, "CMOVB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #306 = CMOVB64rm
- { 307, 3, 1, 0, "CMOVB64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #307 = CMOVB64rr
- { 308, 7, 1, 0, "CMOVBE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #308 = CMOVBE16rm
- { 309, 3, 1, 0, "CMOVBE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #309 = CMOVBE16rr
- { 310, 7, 1, 0, "CMOVBE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #310 = CMOVBE32rm
- { 311, 3, 1, 0, "CMOVBE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #311 = CMOVBE32rr
- { 312, 7, 1, 0, "CMOVBE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #312 = CMOVBE64rm
- { 313, 3, 1, 0, "CMOVBE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #313 = CMOVBE64rr
- { 314, 1, 1, 0, "CMOVBE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #314 = CMOVBE_F
- { 315, 3, 1, 0, "CMOVBE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #315 = CMOVBE_Fp32
- { 316, 3, 1, 0, "CMOVBE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #316 = CMOVBE_Fp64
- { 317, 3, 1, 0, "CMOVBE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #317 = CMOVBE_Fp80
- { 318, 1, 1, 0, "CMOVB_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #318 = CMOVB_F
- { 319, 3, 1, 0, "CMOVB_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #319 = CMOVB_Fp32
- { 320, 3, 1, 0, "CMOVB_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #320 = CMOVB_Fp64
- { 321, 3, 1, 0, "CMOVB_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #321 = CMOVB_Fp80
- { 322, 7, 1, 0, "CMOVE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #322 = CMOVE16rm
- { 323, 3, 1, 0, "CMOVE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #323 = CMOVE16rr
- { 324, 7, 1, 0, "CMOVE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #324 = CMOVE32rm
- { 325, 3, 1, 0, "CMOVE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #325 = CMOVE32rr
- { 326, 7, 1, 0, "CMOVE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #326 = CMOVE64rm
- { 327, 3, 1, 0, "CMOVE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #327 = CMOVE64rr
- { 328, 1, 1, 0, "CMOVE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #328 = CMOVE_F
- { 329, 3, 1, 0, "CMOVE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #329 = CMOVE_Fp32
- { 330, 3, 1, 0, "CMOVE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #330 = CMOVE_Fp64
- { 331, 3, 1, 0, "CMOVE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #331 = CMOVE_Fp80
- { 332, 7, 1, 0, "CMOVG16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #332 = CMOVG16rm
- { 333, 3, 1, 0, "CMOVG16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #333 = CMOVG16rr
- { 334, 7, 1, 0, "CMOVG32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #334 = CMOVG32rm
- { 335, 3, 1, 0, "CMOVG32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #335 = CMOVG32rr
- { 336, 7, 1, 0, "CMOVG64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #336 = CMOVG64rm
- { 337, 3, 1, 0, "CMOVG64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #337 = CMOVG64rr
- { 338, 7, 1, 0, "CMOVGE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #338 = CMOVGE16rm
- { 339, 3, 1, 0, "CMOVGE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #339 = CMOVGE16rr
- { 340, 7, 1, 0, "CMOVGE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #340 = CMOVGE32rm
- { 341, 3, 1, 0, "CMOVGE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #341 = CMOVGE32rr
- { 342, 7, 1, 0, "CMOVGE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #342 = CMOVGE64rm
- { 343, 3, 1, 0, "CMOVGE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #343 = CMOVGE64rr
- { 344, 7, 1, 0, "CMOVL16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #344 = CMOVL16rm
- { 345, 3, 1, 0, "CMOVL16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #345 = CMOVL16rr
- { 346, 7, 1, 0, "CMOVL32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #346 = CMOVL32rm
- { 347, 3, 1, 0, "CMOVL32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #347 = CMOVL32rr
- { 348, 7, 1, 0, "CMOVL64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #348 = CMOVL64rm
- { 349, 3, 1, 0, "CMOVL64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #349 = CMOVL64rr
- { 350, 7, 1, 0, "CMOVLE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #350 = CMOVLE16rm
- { 351, 3, 1, 0, "CMOVLE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #351 = CMOVLE16rr
- { 352, 7, 1, 0, "CMOVLE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #352 = CMOVLE32rm
- { 353, 3, 1, 0, "CMOVLE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #353 = CMOVLE32rr
- { 354, 7, 1, 0, "CMOVLE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #354 = CMOVLE64rm
- { 355, 3, 1, 0, "CMOVLE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #355 = CMOVLE64rr
- { 356, 1, 1, 0, "CMOVNBE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #356 = CMOVNBE_F
- { 357, 3, 1, 0, "CMOVNBE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #357 = CMOVNBE_Fp32
- { 358, 3, 1, 0, "CMOVNBE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #358 = CMOVNBE_Fp64
- { 359, 3, 1, 0, "CMOVNBE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #359 = CMOVNBE_Fp80
- { 360, 1, 1, 0, "CMOVNB_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #360 = CMOVNB_F
- { 361, 3, 1, 0, "CMOVNB_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #361 = CMOVNB_Fp32
- { 362, 3, 1, 0, "CMOVNB_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #362 = CMOVNB_Fp64
- { 363, 3, 1, 0, "CMOVNB_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #363 = CMOVNB_Fp80
- { 364, 7, 1, 0, "CMOVNE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #364 = CMOVNE16rm
- { 365, 3, 1, 0, "CMOVNE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #365 = CMOVNE16rr
- { 366, 7, 1, 0, "CMOVNE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #366 = CMOVNE32rm
- { 367, 3, 1, 0, "CMOVNE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #367 = CMOVNE32rr
- { 368, 7, 1, 0, "CMOVNE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #368 = CMOVNE64rm
- { 369, 3, 1, 0, "CMOVNE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #369 = CMOVNE64rr
- { 370, 1, 1, 0, "CMOVNE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #370 = CMOVNE_F
- { 371, 3, 1, 0, "CMOVNE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #371 = CMOVNE_Fp32
- { 372, 3, 1, 0, "CMOVNE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #372 = CMOVNE_Fp64
- { 373, 3, 1, 0, "CMOVNE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #373 = CMOVNE_Fp80
- { 374, 7, 1, 0, "CMOVNO16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #374 = CMOVNO16rm
- { 375, 3, 1, 0, "CMOVNO16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #375 = CMOVNO16rr
- { 376, 7, 1, 0, "CMOVNO32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #376 = CMOVNO32rm
- { 377, 3, 1, 0, "CMOVNO32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #377 = CMOVNO32rr
- { 378, 7, 1, 0, "CMOVNO64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #378 = CMOVNO64rm
- { 379, 3, 1, 0, "CMOVNO64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #379 = CMOVNO64rr
- { 380, 7, 1, 0, "CMOVNP16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #380 = CMOVNP16rm
- { 381, 3, 1, 0, "CMOVNP16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #381 = CMOVNP16rr
- { 382, 7, 1, 0, "CMOVNP32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #382 = CMOVNP32rm
- { 383, 3, 1, 0, "CMOVNP32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #383 = CMOVNP32rr
- { 384, 7, 1, 0, "CMOVNP64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #384 = CMOVNP64rm
- { 385, 3, 1, 0, "CMOVNP64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #385 = CMOVNP64rr
- { 386, 1, 1, 0, "CMOVNP_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #386 = CMOVNP_F
- { 387, 3, 1, 0, "CMOVNP_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #387 = CMOVNP_Fp32
- { 388, 3, 1, 0, "CMOVNP_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #388 = CMOVNP_Fp64
- { 389, 3, 1, 0, "CMOVNP_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #389 = CMOVNP_Fp80
- { 390, 7, 1, 0, "CMOVNS16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #390 = CMOVNS16rm
- { 391, 3, 1, 0, "CMOVNS16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #391 = CMOVNS16rr
- { 392, 7, 1, 0, "CMOVNS32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #392 = CMOVNS32rm
- { 393, 3, 1, 0, "CMOVNS32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #393 = CMOVNS32rr
- { 394, 7, 1, 0, "CMOVNS64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #394 = CMOVNS64rm
- { 395, 3, 1, 0, "CMOVNS64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #395 = CMOVNS64rr
- { 396, 7, 1, 0, "CMOVO16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #396 = CMOVO16rm
- { 397, 3, 1, 0, "CMOVO16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #397 = CMOVO16rr
- { 398, 7, 1, 0, "CMOVO32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #398 = CMOVO32rm
- { 399, 3, 1, 0, "CMOVO32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #399 = CMOVO32rr
- { 400, 7, 1, 0, "CMOVO64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #400 = CMOVO64rm
- { 401, 3, 1, 0, "CMOVO64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #401 = CMOVO64rr
- { 402, 7, 1, 0, "CMOVP16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #402 = CMOVP16rm
- { 403, 3, 1, 0, "CMOVP16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #403 = CMOVP16rr
- { 404, 7, 1, 0, "CMOVP32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #404 = CMOVP32rm
- { 405, 3, 1, 0, "CMOVP32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #405 = CMOVP32rr
- { 406, 7, 1, 0, "CMOVP64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #406 = CMOVP64rm
- { 407, 3, 1, 0, "CMOVP64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #407 = CMOVP64rr
- { 408, 1, 1, 0, "CMOVP_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #408 = CMOVP_F
- { 409, 3, 1, 0, "CMOVP_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #409 = CMOVP_Fp32
- { 410, 3, 1, 0, "CMOVP_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #410 = CMOVP_Fp64
- { 411, 3, 1, 0, "CMOVP_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #411 = CMOVP_Fp80
- { 412, 7, 1, 0, "CMOVS16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #412 = CMOVS16rm
- { 413, 3, 1, 0, "CMOVS16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #413 = CMOVS16rr
- { 414, 7, 1, 0, "CMOVS32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #414 = CMOVS32rm
- { 415, 3, 1, 0, "CMOVS32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #415 = CMOVS32rr
- { 416, 7, 1, 0, "CMOVS64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #416 = CMOVS64rm
- { 417, 3, 1, 0, "CMOVS64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #417 = CMOVS64rr
- { 418, 4, 1, 0, "CMOV_FR32", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo62 }, // Inst #418 = CMOV_FR32
- { 419, 4, 1, 0, "CMOV_FR64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo63 }, // Inst #419 = CMOV_FR64
- { 420, 4, 1, 0, "CMOV_GR8", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, ImplicitList1, Barriers1, OperandInfo64 }, // Inst #420 = CMOV_GR8
- { 421, 4, 1, 0, "CMOV_V1I64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo65 }, // Inst #421 = CMOV_V1I64
- { 422, 4, 1, 0, "CMOV_V2F64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo66 }, // Inst #422 = CMOV_V2F64
- { 423, 4, 1, 0, "CMOV_V2I64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo66 }, // Inst #423 = CMOV_V2I64
- { 424, 4, 1, 0, "CMOV_V4F32", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo66 }, // Inst #424 = CMOV_V4F32
- { 425, 1, 0, 0, "CMP16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #425 = CMP16i16
- { 426, 6, 0, 0, "CMP16mi", 0|(1<<TID::MayLoad), 0|31|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #426 = CMP16mi
- { 427, 6, 0, 0, "CMP16mi8", 0|(1<<TID::MayLoad), 0|31|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #427 = CMP16mi8
- { 428, 6, 0, 0, "CMP16mr", 0|(1<<TID::MayLoad), 0|4|(1<<6)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #428 = CMP16mr
- { 429, 2, 0, 0, "CMP16mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #429 = CMP16mrmrr
- { 430, 2, 0, 0, "CMP16ri", 0, 0|23|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #430 = CMP16ri
- { 431, 2, 0, 0, "CMP16ri8", 0, 0|23|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #431 = CMP16ri8
- { 432, 6, 0, 0, "CMP16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #432 = CMP16rm
- { 433, 2, 0, 0, "CMP16rr", 0, 0|3|(1<<6)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #433 = CMP16rr
- { 434, 1, 0, 0, "CMP32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #434 = CMP32i32
- { 435, 6, 0, 0, "CMP32mi", 0|(1<<TID::MayLoad), 0|31|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #435 = CMP32mi
- { 436, 6, 0, 0, "CMP32mi8", 0|(1<<TID::MayLoad), 0|31|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #436 = CMP32mi8
- { 437, 6, 0, 0, "CMP32mr", 0|(1<<TID::MayLoad), 0|4|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #437 = CMP32mr
- { 438, 2, 0, 0, "CMP32mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #438 = CMP32mrmrr
- { 439, 2, 0, 0, "CMP32ri", 0, 0|23|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #439 = CMP32ri
- { 440, 2, 0, 0, "CMP32ri8", 0, 0|23|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #440 = CMP32ri8
- { 441, 6, 0, 0, "CMP32rm", 0|(1<<TID::MayLoad), 0|6|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #441 = CMP32rm
- { 442, 2, 0, 0, "CMP32rr", 0, 0|3|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #442 = CMP32rr
- { 443, 1, 0, 0, "CMP64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #443 = CMP64i32
- { 444, 6, 0, 0, "CMP64mi32", 0|(1<<TID::MayLoad), 0|31|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #444 = CMP64mi32
- { 445, 6, 0, 0, "CMP64mi8", 0|(1<<TID::MayLoad), 0|31|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #445 = CMP64mi8
- { 446, 6, 0, 0, "CMP64mr", 0|(1<<TID::MayLoad), 0|4|(1<<12)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #446 = CMP64mr
- { 447, 2, 0, 0, "CMP64mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #447 = CMP64mrmrr
- { 448, 2, 0, 0, "CMP64ri32", 0, 0|23|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #448 = CMP64ri32
- { 449, 2, 0, 0, "CMP64ri8", 0, 0|23|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #449 = CMP64ri8
- { 450, 6, 0, 0, "CMP64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #450 = CMP64rm
- { 451, 2, 0, 0, "CMP64rr", 0, 0|3|(1<<12)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #451 = CMP64rr
- { 452, 1, 0, 0, "CMP8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(60<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #452 = CMP8i8
- { 453, 6, 0, 0, "CMP8mi", 0|(1<<TID::MayLoad), 0|31|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #453 = CMP8mi
- { 454, 6, 0, 0, "CMP8mr", 0|(1<<TID::MayLoad), 0|4|(56<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #454 = CMP8mr
- { 455, 2, 0, 0, "CMP8mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(58<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #455 = CMP8mrmrr
- { 456, 2, 0, 0, "CMP8ri", 0, 0|23|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo68 }, // Inst #456 = CMP8ri
- { 457, 6, 0, 0, "CMP8rm", 0|(1<<TID::MayLoad), 0|6|(58<<24), NULL, ImplicitList1, Barriers1, OperandInfo69 }, // Inst #457 = CMP8rm
- { 458, 2, 0, 0, "CMP8rr", 0, 0|3|(56<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #458 = CMP8rr
- { 459, 8, 1, 0, "CMPPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #459 = CMPPDrmi
- { 460, 4, 1, 0, "CMPPDrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #460 = CMPPDrri
- { 461, 8, 1, 0, "CMPPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #461 = CMPPSrmi
- { 462, 4, 1, 0, "CMPPSrri", 0, 0|5|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #462 = CMPPSrri
- { 463, 0, 0, 0, "CMPS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(167<<24), NULL, NULL, NULL, 0 }, // Inst #463 = CMPS16
- { 464, 0, 0, 0, "CMPS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(167<<24), NULL, NULL, NULL, 0 }, // Inst #464 = CMPS32
- { 465, 0, 0, 0, "CMPS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(167<<24), NULL, NULL, NULL, 0 }, // Inst #465 = CMPS64
- { 466, 0, 0, 0, "CMPS8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(166<<24), NULL, NULL, NULL, 0 }, // Inst #466 = CMPS8
- { 467, 8, 1, 0, "CMPSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo70 }, // Inst #467 = CMPSDrm
- { 468, 4, 1, 0, "CMPSDrr", 0, 0|5|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo71 }, // Inst #468 = CMPSDrr
- { 469, 8, 1, 0, "CMPSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo72 }, // Inst #469 = CMPSSrm
- { 470, 4, 1, 0, "CMPSSrr", 0, 0|5|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #470 = CMPSSrr
- { 471, 5, 0, 0, "CMPXCHG16B", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(1<<12)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #471 = CMPXCHG16B
- { 472, 6, 0, 0, "CMPXCHG16rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(177<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #472 = CMPXCHG16rm
- { 473, 2, 1, 0, "CMPXCHG16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(177<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #473 = CMPXCHG16rr
- { 474, 6, 0, 0, "CMPXCHG32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(177<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #474 = CMPXCHG32rm
- { 475, 2, 1, 0, "CMPXCHG32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(177<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #475 = CMPXCHG32rr
- { 476, 6, 0, 0, "CMPXCHG64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(177<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #476 = CMPXCHG64rm
- { 477, 2, 1, 0, "CMPXCHG64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(177<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #477 = CMPXCHG64rr
- { 478, 5, 0, 0, "CMPXCHG8B", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #478 = CMPXCHG8B
- { 479, 6, 0, 0, "CMPXCHG8rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(176<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #479 = CMPXCHG8rm
- { 480, 2, 1, 0, "CMPXCHG8rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(176<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #480 = CMPXCHG8rr
- { 481, 6, 0, 0, "COMISDrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(47<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #481 = COMISDrm
- { 482, 2, 0, 0, "COMISDrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(47<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #482 = COMISDrr
- { 483, 6, 0, 0, "COMISSrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #483 = COMISSrm
- { 484, 2, 0, 0, "COMISSrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #484 = COMISSrr
- { 485, 1, 0, 0, "COMP_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #485 = COMP_FST0r
- { 486, 1, 0, 0, "COM_FIPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(10<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #486 = COM_FIPr
- { 487, 1, 0, 0, "COM_FIr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #487 = COM_FIr
- { 488, 1, 0, 0, "COM_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #488 = COM_FST0r
- { 489, 0, 0, 0, "COS_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(255<<24), NULL, NULL, NULL, 0 }, // Inst #489 = COS_F
- { 490, 2, 1, 0, "COS_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #490 = COS_Fp32
- { 491, 2, 1, 0, "COS_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #491 = COS_Fp64
- { 492, 2, 1, 0, "COS_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #492 = COS_Fp80
- { 493, 0, 0, 0, "CPUID", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(162<<24), NULL, NULL, NULL, 0 }, // Inst #493 = CPUID
- { 494, 0, 0, 0, "CQO", 0, 0|1|(1<<12)|(153<<24), ImplicitList15, ImplicitList16, NULL, 0 }, // Inst #494 = CQO
- { 495, 7, 1, 0, "CRC32m16", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #495 = CRC32m16
- { 496, 7, 1, 0, "CRC32m32", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #496 = CRC32m32
- { 497, 7, 1, 0, "CRC32m8", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(240<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #497 = CRC32m8
- { 498, 3, 1, 0, "CRC32r16", 0, 0|5|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo77 }, // Inst #498 = CRC32r16
- { 499, 3, 1, 0, "CRC32r32", 0, 0|5|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo14 }, // Inst #499 = CRC32r32
- { 500, 3, 1, 0, "CRC32r8", 0, 0|5|(1<<6)|(15<<8)|(240<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #500 = CRC32r8
- { 501, 7, 1, 0, "CRC64m64", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(1<<12)|(240<<24), NULL, NULL, NULL, OperandInfo17 }, // Inst #501 = CRC64m64
- { 502, 3, 1, 0, "CRC64r64", 0, 0|5|(1<<6)|(15<<8)|(1<<12)|(240<<24), NULL, NULL, NULL, OperandInfo18 }, // Inst #502 = CRC64r64
- { 503, 6, 1, 0, "CVTDQ2PDrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #503 = CVTDQ2PDrm
- { 504, 2, 1, 0, "CVTDQ2PDrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #504 = CVTDQ2PDrr
- { 505, 6, 1, 0, "CVTDQ2PSrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #505 = CVTDQ2PSrm
- { 506, 2, 1, 0, "CVTDQ2PSrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #506 = CVTDQ2PSrr
- { 507, 6, 1, 0, "CVTPD2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #507 = CVTPD2DQrm
- { 508, 2, 1, 0, "CVTPD2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #508 = CVTPD2DQrr
- { 509, 6, 1, 0, "CVTPD2PSrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #509 = CVTPD2PSrm
- { 510, 2, 1, 0, "CVTPD2PSrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #510 = CVTPD2PSrr
- { 511, 6, 1, 0, "CVTPS2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #511 = CVTPS2DQrm
- { 512, 2, 1, 0, "CVTPS2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #512 = CVTPS2DQrr
- { 513, 6, 1, 0, "CVTPS2PDrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #513 = CVTPS2PDrm
- { 514, 2, 1, 0, "CVTPS2PDrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #514 = CVTPS2PDrr
- { 515, 6, 1, 0, "CVTSD2SI64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #515 = CVTSD2SI64rm
- { 516, 2, 1, 0, "CVTSD2SI64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #516 = CVTSD2SI64rr
- { 517, 6, 1, 0, "CVTSD2SSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #517 = CVTSD2SSrm
- { 518, 2, 1, 0, "CVTSD2SSrr", 0, 0|5|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo81 }, // Inst #518 = CVTSD2SSrr
- { 519, 6, 1, 0, "CVTSI2SD64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #519 = CVTSI2SD64rm
- { 520, 2, 1, 0, "CVTSI2SD64rr", 0, 0|5|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo83 }, // Inst #520 = CVTSI2SD64rr
- { 521, 6, 1, 0, "CVTSI2SDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #521 = CVTSI2SDrm
- { 522, 2, 1, 0, "CVTSI2SDrr", 0, 0|5|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo84 }, // Inst #522 = CVTSI2SDrr
- { 523, 6, 1, 0, "CVTSI2SS64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #523 = CVTSI2SS64rm
- { 524, 2, 1, 0, "CVTSI2SS64rr", 0, 0|5|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo85 }, // Inst #524 = CVTSI2SS64rr
- { 525, 6, 1, 0, "CVTSI2SSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #525 = CVTSI2SSrm
- { 526, 2, 1, 0, "CVTSI2SSrr", 0, 0|5|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo86 }, // Inst #526 = CVTSI2SSrr
- { 527, 6, 1, 0, "CVTSS2SDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #527 = CVTSS2SDrm
- { 528, 2, 1, 0, "CVTSS2SDrr", 0, 0|5|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo87 }, // Inst #528 = CVTSS2SDrr
- { 529, 6, 1, 0, "CVTSS2SI64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #529 = CVTSS2SI64rm
- { 530, 2, 1, 0, "CVTSS2SI64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo88 }, // Inst #530 = CVTSS2SI64rr
- { 531, 6, 1, 0, "CVTSS2SIrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #531 = CVTSS2SIrm
- { 532, 2, 1, 0, "CVTSS2SIrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #532 = CVTSS2SIrr
- { 533, 6, 1, 0, "CVTTPS2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #533 = CVTTPS2DQrm
- { 534, 2, 1, 0, "CVTTPS2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #534 = CVTTPS2DQrr
- { 535, 6, 1, 0, "CVTTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #535 = CVTTSD2SI64rm
- { 536, 2, 1, 0, "CVTTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #536 = CVTTSD2SI64rr
- { 537, 6, 1, 0, "CVTTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #537 = CVTTSD2SIrm
- { 538, 2, 1, 0, "CVTTSD2SIrr", 0, 0|5|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo90 }, // Inst #538 = CVTTSD2SIrr
- { 539, 6, 1, 0, "CVTTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #539 = CVTTSS2SI64rm
- { 540, 2, 1, 0, "CVTTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo88 }, // Inst #540 = CVTTSS2SI64rr
- { 541, 6, 1, 0, "CVTTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #541 = CVTTSS2SIrm
- { 542, 2, 1, 0, "CVTTSS2SIrr", 0, 0|5|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #542 = CVTTSS2SIrr
- { 543, 0, 0, 0, "CWD", 0, 0|1|(1<<6)|(153<<24), ImplicitList12, ImplicitList17, NULL, 0 }, // Inst #543 = CWD
- { 544, 0, 0, 0, "CWDE", 0, 0|1|(152<<24), ImplicitList12, ImplicitList13, NULL, 0 }, // Inst #544 = CWDE
- { 545, 5, 0, 0, "DEC16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #545 = DEC16m
- { 546, 2, 1, 0, "DEC16r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(1<<6)|(72<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #546 = DEC16r
- { 547, 5, 0, 0, "DEC32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #547 = DEC32m
- { 548, 2, 1, 0, "DEC32r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(72<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #548 = DEC32r
- { 549, 5, 0, 0, "DEC64_16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #549 = DEC64_16m
- { 550, 2, 1, 0, "DEC64_16r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #550 = DEC64_16r
- { 551, 5, 0, 0, "DEC64_32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #551 = DEC64_32m
- { 552, 2, 1, 0, "DEC64_32r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #552 = DEC64_32r
- { 553, 5, 0, 0, "DEC64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #553 = DEC64m
- { 554, 2, 1, 0, "DEC64r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #554 = DEC64r
- { 555, 5, 0, 0, "DEC8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #555 = DEC8m
- { 556, 2, 1, 0, "DEC8r", 0, 0|17|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #556 = DEC8r
- { 557, 5, 0, 0, "DIV16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(247<<24), ImplicitList17, ImplicitList18, Barriers1, OperandInfo30 }, // Inst #557 = DIV16m
- { 558, 1, 0, 0, "DIV16r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<6)|(247<<24), ImplicitList17, ImplicitList18, Barriers1, OperandInfo93 }, // Inst #558 = DIV16r
- { 559, 5, 0, 0, "DIV32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(247<<24), ImplicitList14, ImplicitList19, Barriers6, OperandInfo30 }, // Inst #559 = DIV32m
- { 560, 1, 0, 0, "DIV32r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(247<<24), ImplicitList14, ImplicitList19, Barriers6, OperandInfo57 }, // Inst #560 = DIV32r
- { 561, 5, 0, 0, "DIV64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(1<<12)|(247<<24), ImplicitList16, ImplicitList20, Barriers1, OperandInfo30 }, // Inst #561 = DIV64m
- { 562, 1, 0, 0, "DIV64r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<12)|(247<<24), ImplicitList16, ImplicitList20, Barriers1, OperandInfo58 }, // Inst #562 = DIV64r
- { 563, 5, 0, 0, "DIV8m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(246<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #563 = DIV8m
- { 564, 1, 0, 0, "DIV8r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(246<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo94 }, // Inst #564 = DIV8r
- { 565, 7, 1, 0, "DIVPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #565 = DIVPDrm
- { 566, 3, 1, 0, "DIVPDrr", 0, 0|5|(1<<6)|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #566 = DIVPDrr
- { 567, 7, 1, 0, "DIVPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #567 = DIVPSrm
- { 568, 3, 1, 0, "DIVPSrr", 0, 0|5|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #568 = DIVPSrr
- { 569, 5, 0, 0, "DIVR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #569 = DIVR_F32m
- { 570, 5, 0, 0, "DIVR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #570 = DIVR_F64m
- { 571, 5, 0, 0, "DIVR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #571 = DIVR_FI16m
- { 572, 5, 0, 0, "DIVR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #572 = DIVR_FI32m
- { 573, 1, 0, 0, "DIVR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #573 = DIVR_FPrST0
- { 574, 1, 0, 0, "DIVR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(248<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #574 = DIVR_FST0r
- { 575, 7, 1, 0, "DIVR_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #575 = DIVR_Fp32m
- { 576, 7, 1, 0, "DIVR_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #576 = DIVR_Fp64m
- { 577, 7, 1, 0, "DIVR_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #577 = DIVR_Fp64m32
- { 578, 7, 1, 0, "DIVR_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #578 = DIVR_Fp80m32
- { 579, 7, 1, 0, "DIVR_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #579 = DIVR_Fp80m64
- { 580, 7, 1, 0, "DIVR_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #580 = DIVR_FpI16m32
- { 581, 7, 1, 0, "DIVR_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #581 = DIVR_FpI16m64
- { 582, 7, 1, 0, "DIVR_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #582 = DIVR_FpI16m80
- { 583, 7, 1, 0, "DIVR_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #583 = DIVR_FpI32m32
- { 584, 7, 1, 0, "DIVR_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #584 = DIVR_FpI32m64
- { 585, 7, 1, 0, "DIVR_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #585 = DIVR_FpI32m80
- { 586, 1, 0, 0, "DIVR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #586 = DIVR_FrST0
- { 587, 7, 1, 0, "DIVSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #587 = DIVSDrm
- { 588, 7, 1, 0, "DIVSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #588 = DIVSDrm_Int
- { 589, 3, 1, 0, "DIVSDrr", 0, 0|5|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #589 = DIVSDrr
- { 590, 3, 1, 0, "DIVSDrr_Int", 0, 0|5|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #590 = DIVSDrr_Int
- { 591, 7, 1, 0, "DIVSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #591 = DIVSSrm
- { 592, 7, 1, 0, "DIVSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #592 = DIVSSrm_Int
- { 593, 3, 1, 0, "DIVSSrr", 0, 0|5|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #593 = DIVSSrr
- { 594, 3, 1, 0, "DIVSSrr_Int", 0, 0|5|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #594 = DIVSSrr_Int
- { 595, 5, 0, 0, "DIV_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #595 = DIV_F32m
- { 596, 5, 0, 0, "DIV_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #596 = DIV_F64m
- { 597, 5, 0, 0, "DIV_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #597 = DIV_FI16m
- { 598, 5, 0, 0, "DIV_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #598 = DIV_FI32m
- { 599, 1, 0, 0, "DIV_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(248<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #599 = DIV_FPrST0
- { 600, 1, 0, 0, "DIV_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #600 = DIV_FST0r
- { 601, 3, 1, 0, "DIV_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #601 = DIV_Fp32
- { 602, 7, 1, 0, "DIV_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #602 = DIV_Fp32m
- { 603, 3, 1, 0, "DIV_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #603 = DIV_Fp64
- { 604, 7, 1, 0, "DIV_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #604 = DIV_Fp64m
- { 605, 7, 1, 0, "DIV_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #605 = DIV_Fp64m32
- { 606, 3, 1, 0, "DIV_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #606 = DIV_Fp80
- { 607, 7, 1, 0, "DIV_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #607 = DIV_Fp80m32
- { 608, 7, 1, 0, "DIV_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #608 = DIV_Fp80m64
- { 609, 7, 1, 0, "DIV_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #609 = DIV_FpI16m32
- { 610, 7, 1, 0, "DIV_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #610 = DIV_FpI16m64
- { 611, 7, 1, 0, "DIV_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #611 = DIV_FpI16m80
- { 612, 7, 1, 0, "DIV_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #612 = DIV_FpI32m32
- { 613, 7, 1, 0, "DIV_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #613 = DIV_FpI32m64
- { 614, 7, 1, 0, "DIV_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #614 = DIV_FpI32m80
- { 615, 1, 0, 0, "DIV_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(248<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #615 = DIV_FrST0
- { 616, 8, 1, 0, "DPPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(65<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #616 = DPPDrmi
- { 617, 4, 1, 0, "DPPDrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(65<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #617 = DPPDrri
- { 618, 8, 1, 0, "DPPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(64<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #618 = DPPSrmi
- { 619, 4, 1, 0, "DPPSrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(64<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #619 = DPPSrri
- { 620, 1, 0, 0, "EH_RETURN", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(195<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #620 = EH_RETURN
- { 621, 1, 0, 0, "EH_RETURN64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(195<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #621 = EH_RETURN64
- { 622, 2, 0, 0, "ENTER", 0|(1<<TID::UnmodeledSideEffects), 0|1|(200<<24), NULL, NULL, NULL, OperandInfo38 }, // Inst #622 = ENTER
- { 623, 7, 0, 0, "EXTRACTPSmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<13)|(23<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #623 = EXTRACTPSmr
- { 624, 3, 1, 0, "EXTRACTPSrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(23<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #624 = EXTRACTPSrr
- { 625, 0, 0, 0, "F2XM1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(240<<24), NULL, NULL, NULL, 0 }, // Inst #625 = F2XM1
- { 626, 2, 0, 0, "FARCALL16i", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(154<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo38 }, // Inst #626 = FARCALL16i
- { 627, 5, 0, 0, "FARCALL16m", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo30 }, // Inst #627 = FARCALL16m
- { 628, 2, 0, 0, "FARCALL32i", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|1|(154<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo38 }, // Inst #628 = FARCALL32i
- { 629, 5, 0, 0, "FARCALL32m", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo30 }, // Inst #629 = FARCALL32m
- { 630, 5, 0, 0, "FARCALL64", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo30 }, // Inst #630 = FARCALL64
- { 631, 2, 0, 0, "FARJMP16i", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(234<<24), NULL, NULL, NULL, OperandInfo38 }, // Inst #631 = FARJMP16i
- { 632, 5, 0, 0, "FARJMP16m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #632 = FARJMP16m
- { 633, 2, 0, 0, "FARJMP32i", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(234<<24), NULL, NULL, NULL, OperandInfo38 }, // Inst #633 = FARJMP32i
- { 634, 5, 0, 0, "FARJMP32m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #634 = FARJMP32m
- { 635, 5, 0, 0, "FARJMP64", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #635 = FARJMP64
- { 636, 5, 0, 0, "FBLDm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #636 = FBLDm
- { 637, 5, 1, 0, "FBSTPm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #637 = FBSTPm
- { 638, 5, 0, 0, "FCOM32m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #638 = FCOM32m
- { 639, 5, 0, 0, "FCOM64m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #639 = FCOM64m
- { 640, 5, 0, 0, "FCOMP32m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #640 = FCOMP32m
- { 641, 5, 0, 0, "FCOMP64m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #641 = FCOMP64m
- { 642, 0, 0, 0, "FCOMPP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(9<<8)|(217<<24), NULL, NULL, NULL, 0 }, // Inst #642 = FCOMPP
- { 643, 0, 0, 0, "FDECSTP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(246<<24), NULL, NULL, NULL, 0 }, // Inst #643 = FDECSTP
- { 644, 1, 0, 0, "FFREE", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #644 = FFREE
- { 645, 5, 0, 0, "FICOM16m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #645 = FICOM16m
- { 646, 5, 0, 0, "FICOM32m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #646 = FICOM32m
- { 647, 5, 0, 0, "FICOMP16m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #647 = FICOMP16m
- { 648, 5, 0, 0, "FICOMP32m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #648 = FICOMP32m
- { 649, 0, 0, 0, "FINCSTP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(247<<24), NULL, NULL, NULL, 0 }, // Inst #649 = FINCSTP
- { 650, 5, 1, 0, "FISTTP32m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #650 = FISTTP32m
- { 651, 5, 0, 0, "FLDCW16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #651 = FLDCW16m
- { 652, 5, 0, 0, "FLDENVm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #652 = FLDENVm
- { 653, 0, 0, 0, "FLDL2E", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(234<<24), NULL, NULL, NULL, 0 }, // Inst #653 = FLDL2E
- { 654, 0, 0, 0, "FLDL2T", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(233<<24), NULL, NULL, NULL, 0 }, // Inst #654 = FLDL2T
- { 655, 0, 0, 0, "FLDLG2", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(236<<24), NULL, NULL, NULL, 0 }, // Inst #655 = FLDLG2
- { 656, 0, 0, 0, "FLDLN2", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(237<<24), NULL, NULL, NULL, 0 }, // Inst #656 = FLDLN2
- { 657, 0, 0, 0, "FLDPI", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(235<<24), NULL, NULL, NULL, 0 }, // Inst #657 = FLDPI
- { 658, 0, 0, 0, "FNCLEX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(6<<8)|(226<<24), NULL, NULL, NULL, 0 }, // Inst #658 = FNCLEX
- { 659, 0, 0, 0, "FNINIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(6<<8)|(227<<24), NULL, NULL, NULL, 0 }, // Inst #659 = FNINIT
- { 660, 0, 0, 0, "FNOP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(208<<24), NULL, NULL, NULL, 0 }, // Inst #660 = FNOP
- { 661, 5, 0, 0, "FNSTCW16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #661 = FNSTCW16m
- { 662, 0, 0, 0, "FNSTSW8r", 0|(1<<TID::UnmodeledSideEffects), 0|1|(10<<8)|(224<<24), NULL, ImplicitList12, NULL, 0 }, // Inst #662 = FNSTSW8r
- { 663, 5, 1, 0, "FNSTSWm", 0|(1<<TID::UnmodeledSideEffects), 0|31|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #663 = FNSTSWm
- { 664, 6, 0, 0, "FP32_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #664 = FP32_TO_INT16_IN_MEM
- { 665, 6, 0, 0, "FP32_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #665 = FP32_TO_INT32_IN_MEM
- { 666, 6, 0, 0, "FP32_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #666 = FP32_TO_INT64_IN_MEM
- { 667, 6, 0, 0, "FP64_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #667 = FP64_TO_INT16_IN_MEM
- { 668, 6, 0, 0, "FP64_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #668 = FP64_TO_INT32_IN_MEM
- { 669, 6, 0, 0, "FP64_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #669 = FP64_TO_INT64_IN_MEM
- { 670, 6, 0, 0, "FP80_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo99 }, // Inst #670 = FP80_TO_INT16_IN_MEM
- { 671, 6, 0, 0, "FP80_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo99 }, // Inst #671 = FP80_TO_INT32_IN_MEM
- { 672, 6, 0, 0, "FP80_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo99 }, // Inst #672 = FP80_TO_INT64_IN_MEM
- { 673, 0, 0, 0, "FPATAN", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(243<<24), NULL, NULL, NULL, 0 }, // Inst #673 = FPATAN
- { 674, 0, 0, 0, "FPREM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(248<<24), NULL, NULL, NULL, 0 }, // Inst #674 = FPREM
- { 675, 0, 0, 0, "FPREM1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(245<<24), NULL, NULL, NULL, 0 }, // Inst #675 = FPREM1
- { 676, 0, 0, 0, "FPTAN", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(242<<24), NULL, NULL, NULL, 0 }, // Inst #676 = FPTAN
- { 677, 0, 0, 0, "FP_REG_KILL", 0|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0, NULL, ImplicitList22, Barriers7, 0 }, // Inst #677 = FP_REG_KILL
- { 678, 0, 0, 0, "FRNDINT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(252<<24), NULL, NULL, NULL, 0 }, // Inst #678 = FRNDINT
- { 679, 5, 1, 0, "FRSTORm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #679 = FRSTORm
- { 680, 5, 1, 0, "FSAVEm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #680 = FSAVEm
- { 681, 0, 0, 0, "FSCALE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(253<<24), NULL, NULL, NULL, 0 }, // Inst #681 = FSCALE
- { 682, 0, 0, 0, "FSINCOS", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(251<<24), NULL, NULL, NULL, 0 }, // Inst #682 = FSINCOS
- { 683, 5, 1, 0, "FSTENVm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #683 = FSTENVm
- { 684, 6, 1, 0, "FS_MOV32rm", 0|(1<<TID::MayLoad), 0|6|(1<<20)|(139<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #684 = FS_MOV32rm
- { 685, 0, 0, 0, "FXAM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(229<<24), NULL, NULL, NULL, 0 }, // Inst #685 = FXAM
- { 686, 5, 0, 0, "FXRSTOR", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #686 = FXRSTOR
- { 687, 5, 1, 0, "FXSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #687 = FXSAVE
- { 688, 0, 0, 0, "FXTRACT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(244<<24), NULL, NULL, NULL, 0 }, // Inst #688 = FXTRACT
- { 689, 0, 0, 0, "FYL2X", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(241<<24), NULL, NULL, NULL, 0 }, // Inst #689 = FYL2X
- { 690, 0, 0, 0, "FYL2XP1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(249<<24), NULL, NULL, NULL, 0 }, // Inst #690 = FYL2XP1
- { 691, 1, 1, 0, "FpGET_ST0_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #691 = FpGET_ST0_32
- { 692, 1, 1, 0, "FpGET_ST0_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #692 = FpGET_ST0_64
- { 693, 1, 1, 0, "FpGET_ST0_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #693 = FpGET_ST0_80
- { 694, 1, 1, 0, "FpGET_ST1_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #694 = FpGET_ST1_32
- { 695, 1, 1, 0, "FpGET_ST1_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #695 = FpGET_ST1_64
- { 696, 1, 1, 0, "FpGET_ST1_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #696 = FpGET_ST1_80
- { 697, 1, 0, 0, "FpSET_ST0_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList23, NULL, OperandInfo100 }, // Inst #697 = FpSET_ST0_32
- { 698, 1, 0, 0, "FpSET_ST0_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList23, NULL, OperandInfo101 }, // Inst #698 = FpSET_ST0_64
- { 699, 1, 0, 0, "FpSET_ST0_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList23, NULL, OperandInfo102 }, // Inst #699 = FpSET_ST0_80
- { 700, 1, 0, 0, "FpSET_ST1_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo100 }, // Inst #700 = FpSET_ST1_32
- { 701, 1, 0, 0, "FpSET_ST1_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo101 }, // Inst #701 = FpSET_ST1_64
- { 702, 1, 0, 0, "FpSET_ST1_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo102 }, // Inst #702 = FpSET_ST1_80
- { 703, 7, 1, 0, "FsANDNPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #703 = FsANDNPDrm
- { 704, 3, 1, 0, "FsANDNPDrr", 0, 0|5|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #704 = FsANDNPDrr
- { 705, 7, 1, 0, "FsANDNPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #705 = FsANDNPSrm
- { 706, 3, 1, 0, "FsANDNPSrr", 0, 0|5|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #706 = FsANDNPSrr
- { 707, 7, 1, 0, "FsANDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #707 = FsANDPDrm
- { 708, 3, 1, 0, "FsANDPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #708 = FsANDPDrr
- { 709, 7, 1, 0, "FsANDPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #709 = FsANDPSrm
- { 710, 3, 1, 0, "FsANDPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #710 = FsANDPSrr
- { 711, 1, 1, 0, "FsFLD0SD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo103 }, // Inst #711 = FsFLD0SD
- { 712, 1, 1, 0, "FsFLD0SS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo104 }, // Inst #712 = FsFLD0SS
- { 713, 6, 1, 0, "FsMOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #713 = FsMOVAPDrm
- { 714, 2, 1, 0, "FsMOVAPDrr", 0, 0|5|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #714 = FsMOVAPDrr
- { 715, 6, 1, 0, "FsMOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #715 = FsMOVAPSrm
- { 716, 2, 1, 0, "FsMOVAPSrr", 0, 0|5|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #716 = FsMOVAPSrr
- { 717, 7, 1, 0, "FsORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #717 = FsORPDrm
- { 718, 3, 1, 0, "FsORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #718 = FsORPDrr
- { 719, 7, 1, 0, "FsORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #719 = FsORPSrm
- { 720, 3, 1, 0, "FsORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #720 = FsORPSrr
- { 721, 7, 1, 0, "FsXORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #721 = FsXORPDrm
- { 722, 3, 1, 0, "FsXORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #722 = FsXORPDrr
- { 723, 7, 1, 0, "FsXORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #723 = FsXORPSrm
- { 724, 3, 1, 0, "FsXORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #724 = FsXORPSrr
- { 725, 6, 1, 0, "GS_MOV32rm", 0|(1<<TID::MayLoad), 0|6|(2<<20)|(139<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #725 = GS_MOV32rm
- { 726, 7, 1, 0, "HADDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(124<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #726 = HADDPDrm
- { 727, 3, 1, 0, "HADDPDrr", 0, 0|5|(1<<6)|(1<<8)|(124<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #727 = HADDPDrr
- { 728, 7, 1, 0, "HADDPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(124<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #728 = HADDPSrm
- { 729, 3, 1, 0, "HADDPSrr", 0, 0|5|(11<<8)|(124<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #729 = HADDPSrr
- { 730, 0, 0, 0, "HLT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(244<<24), NULL, NULL, NULL, 0 }, // Inst #730 = HLT
- { 731, 7, 1, 0, "HSUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(125<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #731 = HSUBPDrm
- { 732, 3, 1, 0, "HSUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(125<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #732 = HSUBPDrr
- { 733, 7, 1, 0, "HSUBPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(125<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #733 = HSUBPSrm
- { 734, 3, 1, 0, "HSUBPSrr", 0, 0|5|(11<<8)|(125<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #734 = HSUBPSrr
- { 735, 5, 0, 0, "IDIV16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<6)|(247<<24), ImplicitList17, ImplicitList18, Barriers1, OperandInfo30 }, // Inst #735 = IDIV16m
- { 736, 1, 0, 0, "IDIV16r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<6)|(247<<24), ImplicitList17, ImplicitList18, Barriers1, OperandInfo93 }, // Inst #736 = IDIV16r
- { 737, 5, 0, 0, "IDIV32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(247<<24), ImplicitList14, ImplicitList19, Barriers6, OperandInfo30 }, // Inst #737 = IDIV32m
- { 738, 1, 0, 0, "IDIV32r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(247<<24), ImplicitList14, ImplicitList19, Barriers6, OperandInfo57 }, // Inst #738 = IDIV32r
- { 739, 5, 0, 0, "IDIV64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<12)|(247<<24), ImplicitList16, ImplicitList20, Barriers1, OperandInfo30 }, // Inst #739 = IDIV64m
- { 740, 1, 0, 0, "IDIV64r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<12)|(247<<24), ImplicitList16, ImplicitList20, Barriers1, OperandInfo58 }, // Inst #740 = IDIV64r
- { 741, 5, 0, 0, "IDIV8m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(246<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #741 = IDIV8m
- { 742, 1, 0, 0, "IDIV8r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(246<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo94 }, // Inst #742 = IDIV8r
- { 743, 5, 0, 0, "ILD_F16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #743 = ILD_F16m
- { 744, 5, 0, 0, "ILD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #744 = ILD_F32m
- { 745, 5, 0, 0, "ILD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #745 = ILD_F64m
- { 746, 6, 1, 0, "ILD_Fp16m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #746 = ILD_Fp16m32
- { 747, 6, 1, 0, "ILD_Fp16m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #747 = ILD_Fp16m64
- { 748, 6, 1, 0, "ILD_Fp16m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #748 = ILD_Fp16m80
- { 749, 6, 1, 0, "ILD_Fp32m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #749 = ILD_Fp32m32
- { 750, 6, 1, 0, "ILD_Fp32m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #750 = ILD_Fp32m64
- { 751, 6, 1, 0, "ILD_Fp32m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #751 = ILD_Fp32m80
- { 752, 6, 1, 0, "ILD_Fp64m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #752 = ILD_Fp64m32
- { 753, 6, 1, 0, "ILD_Fp64m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #753 = ILD_Fp64m64
- { 754, 6, 1, 0, "ILD_Fp64m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #754 = ILD_Fp64m80
- { 755, 5, 0, 0, "IMUL16m", 0|(1<<TID::MayLoad), 0|29|(1<<6)|(247<<24), ImplicitList12, ImplicitList18, Barriers1, OperandInfo30 }, // Inst #755 = IMUL16m
- { 756, 1, 0, 0, "IMUL16r", 0, 0|21|(1<<6)|(247<<24), ImplicitList12, ImplicitList18, Barriers1, OperandInfo93 }, // Inst #756 = IMUL16r
- { 757, 7, 1, 0, "IMUL16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #757 = IMUL16rm
- { 758, 7, 1, 0, "IMUL16rmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(2<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo110 }, // Inst #758 = IMUL16rmi
- { 759, 7, 1, 0, "IMUL16rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo110 }, // Inst #759 = IMUL16rmi8
- { 760, 3, 1, 0, "IMUL16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #760 = IMUL16rr
- { 761, 3, 1, 0, "IMUL16rri", 0, 0|5|(1<<6)|(2<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo111 }, // Inst #761 = IMUL16rri
- { 762, 3, 1, 0, "IMUL16rri8", 0, 0|5|(1<<6)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo111 }, // Inst #762 = IMUL16rri8
- { 763, 5, 0, 0, "IMUL32m", 0|(1<<TID::MayLoad), 0|29|(247<<24), ImplicitList13, ImplicitList19, Barriers6, OperandInfo30 }, // Inst #763 = IMUL32m
- { 764, 1, 0, 0, "IMUL32r", 0, 0|21|(247<<24), ImplicitList13, ImplicitList19, Barriers6, OperandInfo57 }, // Inst #764 = IMUL32r
- { 765, 7, 1, 0, "IMUL32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #765 = IMUL32rm
- { 766, 7, 1, 0, "IMUL32rmi", 0|(1<<TID::MayLoad), 0|6|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo112 }, // Inst #766 = IMUL32rmi
- { 767, 7, 1, 0, "IMUL32rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo112 }, // Inst #767 = IMUL32rmi8
- { 768, 3, 1, 0, "IMUL32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #768 = IMUL32rr
- { 769, 3, 1, 0, "IMUL32rri", 0, 0|5|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo113 }, // Inst #769 = IMUL32rri
- { 770, 3, 1, 0, "IMUL32rri8", 0, 0|5|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo113 }, // Inst #770 = IMUL32rri8
- { 771, 5, 0, 0, "IMUL64m", 0|(1<<TID::MayLoad), 0|29|(1<<12)|(247<<24), ImplicitList15, ImplicitList20, Barriers1, OperandInfo30 }, // Inst #771 = IMUL64m
- { 772, 1, 0, 0, "IMUL64r", 0, 0|21|(1<<12)|(247<<24), ImplicitList15, ImplicitList20, Barriers1, OperandInfo58 }, // Inst #772 = IMUL64r
- { 773, 7, 1, 0, "IMUL64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #773 = IMUL64rm
- { 774, 7, 1, 0, "IMUL64rmi32", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo114 }, // Inst #774 = IMUL64rmi32
- { 775, 7, 1, 0, "IMUL64rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo114 }, // Inst #775 = IMUL64rmi8
- { 776, 3, 1, 0, "IMUL64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #776 = IMUL64rr
- { 777, 3, 1, 0, "IMUL64rri32", 0, 0|5|(1<<12)|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo115 }, // Inst #777 = IMUL64rri32
- { 778, 3, 1, 0, "IMUL64rri8", 0, 0|5|(1<<12)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo115 }, // Inst #778 = IMUL64rri8
- { 779, 5, 0, 0, "IMUL8m", 0|(1<<TID::MayLoad), 0|29|(246<<24), ImplicitList11, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #779 = IMUL8m
- { 780, 1, 0, 0, "IMUL8r", 0, 0|21|(246<<24), ImplicitList11, ImplicitList21, Barriers1, OperandInfo94 }, // Inst #780 = IMUL8r
- { 781, 0, 0, 0, "IN16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(109<<24), NULL, NULL, NULL, 0 }, // Inst #781 = IN16
- { 782, 1, 0, 0, "IN16ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<13)|(229<<24), NULL, ImplicitList12, NULL, OperandInfo5 }, // Inst #782 = IN16ri
- { 783, 0, 0, 0, "IN16rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(237<<24), ImplicitList25, ImplicitList12, NULL, 0 }, // Inst #783 = IN16rr
- { 784, 0, 0, 0, "IN32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(109<<24), NULL, NULL, NULL, 0 }, // Inst #784 = IN32
- { 785, 1, 0, 0, "IN32ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(229<<24), NULL, ImplicitList13, NULL, OperandInfo5 }, // Inst #785 = IN32ri
- { 786, 0, 0, 0, "IN32rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(237<<24), ImplicitList25, ImplicitList13, NULL, 0 }, // Inst #786 = IN32rr
- { 787, 0, 0, 0, "IN8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(108<<24), NULL, NULL, NULL, 0 }, // Inst #787 = IN8
- { 788, 1, 0, 0, "IN8ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(228<<24), NULL, ImplicitList11, NULL, OperandInfo5 }, // Inst #788 = IN8ri
- { 789, 0, 0, 0, "IN8rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(236<<24), ImplicitList25, ImplicitList11, NULL, 0 }, // Inst #789 = IN8rr
- { 790, 5, 0, 0, "INC16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #790 = INC16m
- { 791, 2, 1, 0, "INC16r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(1<<6)|(64<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #791 = INC16r
- { 792, 5, 0, 0, "INC32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #792 = INC32m
- { 793, 2, 1, 0, "INC32r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(64<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #793 = INC32r
- { 794, 5, 0, 0, "INC64_16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #794 = INC64_16m
- { 795, 2, 1, 0, "INC64_16r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #795 = INC64_16r
- { 796, 5, 0, 0, "INC64_32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #796 = INC64_32m
- { 797, 2, 1, 0, "INC64_32r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #797 = INC64_32r
- { 798, 5, 0, 0, "INC64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #798 = INC64m
- { 799, 2, 1, 0, "INC64r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #799 = INC64r
- { 800, 5, 0, 0, "INC8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #800 = INC8m
- { 801, 2, 1, 0, "INC8r", 0, 0|16|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #801 = INC8r
- { 802, 8, 1, 0, "INSERTPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(33<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #802 = INSERTPSrm
- { 803, 4, 1, 0, "INSERTPSrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(33<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #803 = INSERTPSrr
- { 804, 1, 0, 0, "INT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(205<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #804 = INT
- { 805, 0, 0, 0, "INT3", 0|(1<<TID::UnmodeledSideEffects), 0|1|(204<<24), NULL, NULL, NULL, 0 }, // Inst #805 = INT3
- { 806, 0, 0, 0, "INVD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(8<<24), NULL, NULL, NULL, 0 }, // Inst #806 = INVD
- { 807, 0, 0, 0, "INVEPT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(56<<24), NULL, NULL, NULL, 0 }, // Inst #807 = INVEPT
- { 808, 0, 0, 0, "INVLPG", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #808 = INVLPG
- { 809, 0, 0, 0, "INVVPID", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(56<<24), NULL, NULL, NULL, 0 }, // Inst #809 = INVVPID
- { 810, 0, 0, 0, "IRET16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(207<<24), NULL, NULL, NULL, 0 }, // Inst #810 = IRET16
- { 811, 0, 0, 0, "IRET32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(207<<24), NULL, NULL, NULL, 0 }, // Inst #811 = IRET32
- { 812, 0, 0, 0, "IRET64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(207<<24), NULL, NULL, NULL, 0 }, // Inst #812 = IRET64
- { 813, 5, 0, 0, "ISTT_FP16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #813 = ISTT_FP16m
- { 814, 5, 0, 0, "ISTT_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #814 = ISTT_FP32m
- { 815, 5, 0, 0, "ISTT_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #815 = ISTT_FP64m
- { 816, 6, 0, 0, "ISTT_Fp16m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #816 = ISTT_Fp16m32
- { 817, 6, 0, 0, "ISTT_Fp16m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #817 = ISTT_Fp16m64
- { 818, 6, 0, 0, "ISTT_Fp16m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #818 = ISTT_Fp16m80
- { 819, 6, 0, 0, "ISTT_Fp32m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #819 = ISTT_Fp32m32
- { 820, 6, 0, 0, "ISTT_Fp32m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #820 = ISTT_Fp32m64
- { 821, 6, 0, 0, "ISTT_Fp32m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #821 = ISTT_Fp32m80
- { 822, 6, 0, 0, "ISTT_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #822 = ISTT_Fp64m32
- { 823, 6, 0, 0, "ISTT_Fp64m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #823 = ISTT_Fp64m64
- { 824, 6, 0, 0, "ISTT_Fp64m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #824 = ISTT_Fp64m80
- { 825, 5, 0, 0, "IST_F16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #825 = IST_F16m
- { 826, 5, 0, 0, "IST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #826 = IST_F32m
- { 827, 5, 0, 0, "IST_FP16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #827 = IST_FP16m
- { 828, 5, 0, 0, "IST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #828 = IST_FP32m
- { 829, 5, 0, 0, "IST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #829 = IST_FP64m
- { 830, 6, 0, 0, "IST_Fp16m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #830 = IST_Fp16m32
- { 831, 6, 0, 0, "IST_Fp16m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #831 = IST_Fp16m64
- { 832, 6, 0, 0, "IST_Fp16m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #832 = IST_Fp16m80
- { 833, 6, 0, 0, "IST_Fp32m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #833 = IST_Fp32m32
- { 834, 6, 0, 0, "IST_Fp32m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #834 = IST_Fp32m64
- { 835, 6, 0, 0, "IST_Fp32m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #835 = IST_Fp32m80
- { 836, 6, 0, 0, "IST_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #836 = IST_Fp64m32
- { 837, 6, 0, 0, "IST_Fp64m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #837 = IST_Fp64m64
- { 838, 6, 0, 0, "IST_Fp64m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #838 = IST_Fp64m80
- { 839, 8, 1, 0, "Int_CMPSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #839 = Int_CMPSDrm
- { 840, 4, 1, 0, "Int_CMPSDrr", 0, 0|5|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #840 = Int_CMPSDrr
- { 841, 8, 1, 0, "Int_CMPSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #841 = Int_CMPSSrm
- { 842, 4, 1, 0, "Int_CMPSSrr", 0, 0|5|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #842 = Int_CMPSSrr
- { 843, 6, 0, 0, "Int_COMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #843 = Int_COMISDrm
- { 844, 2, 0, 0, "Int_COMISDrr", 0, 0|5|(1<<6)|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #844 = Int_COMISDrr
- { 845, 6, 0, 0, "Int_COMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #845 = Int_COMISSrm
- { 846, 2, 0, 0, "Int_COMISSrr", 0, 0|5|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #846 = Int_COMISSrr
- { 847, 6, 1, 0, "Int_CVTDQ2PDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #847 = Int_CVTDQ2PDrm
- { 848, 2, 1, 0, "Int_CVTDQ2PDrr", 0, 0|5|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #848 = Int_CVTDQ2PDrr
- { 849, 6, 1, 0, "Int_CVTDQ2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #849 = Int_CVTDQ2PSrm
- { 850, 2, 1, 0, "Int_CVTDQ2PSrr", 0, 0|5|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #850 = Int_CVTDQ2PSrr
- { 851, 6, 1, 0, "Int_CVTPD2DQrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #851 = Int_CVTPD2DQrm
- { 852, 2, 1, 0, "Int_CVTPD2DQrr", 0, 0|5|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #852 = Int_CVTPD2DQrr
- { 853, 6, 1, 0, "Int_CVTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #853 = Int_CVTPD2PIrm
- { 854, 2, 1, 0, "Int_CVTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #854 = Int_CVTPD2PIrr
- { 855, 6, 1, 0, "Int_CVTPD2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #855 = Int_CVTPD2PSrm
- { 856, 2, 1, 0, "Int_CVTPD2PSrr", 0, 0|5|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #856 = Int_CVTPD2PSrr
- { 857, 6, 1, 0, "Int_CVTPI2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #857 = Int_CVTPI2PDrm
- { 858, 2, 1, 0, "Int_CVTPI2PDrr", 0, 0|5|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #858 = Int_CVTPI2PDrr
- { 859, 7, 1, 0, "Int_CVTPI2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #859 = Int_CVTPI2PSrm
- { 860, 3, 1, 0, "Int_CVTPI2PSrr", 0, 0|5|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo120 }, // Inst #860 = Int_CVTPI2PSrr
- { 861, 6, 1, 0, "Int_CVTPS2DQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #861 = Int_CVTPS2DQrm
- { 862, 2, 1, 0, "Int_CVTPS2DQrr", 0, 0|5|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #862 = Int_CVTPS2DQrr
- { 863, 6, 1, 0, "Int_CVTPS2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #863 = Int_CVTPS2PDrm
- { 864, 2, 1, 0, "Int_CVTPS2PDrr", 0, 0|5|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #864 = Int_CVTPS2PDrr
- { 865, 6, 1, 0, "Int_CVTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #865 = Int_CVTPS2PIrm
- { 866, 2, 1, 0, "Int_CVTPS2PIrr", 0, 0|5|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #866 = Int_CVTPS2PIrr
- { 867, 6, 1, 0, "Int_CVTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #867 = Int_CVTSD2SI64rm
- { 868, 2, 1, 0, "Int_CVTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #868 = Int_CVTSD2SI64rr
- { 869, 6, 1, 0, "Int_CVTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(45<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #869 = Int_CVTSD2SIrm
- { 870, 2, 1, 0, "Int_CVTSD2SIrr", 0, 0|5|(11<<8)|(45<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #870 = Int_CVTSD2SIrr
- { 871, 7, 1, 0, "Int_CVTSD2SSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #871 = Int_CVTSD2SSrm
- { 872, 3, 1, 0, "Int_CVTSD2SSrr", 0, 0|5|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #872 = Int_CVTSD2SSrr
- { 873, 7, 1, 0, "Int_CVTSI2SD64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #873 = Int_CVTSI2SD64rm
- { 874, 3, 1, 0, "Int_CVTSI2SD64rr", 0, 0|5|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo123 }, // Inst #874 = Int_CVTSI2SD64rr
- { 875, 7, 1, 0, "Int_CVTSI2SDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #875 = Int_CVTSI2SDrm
- { 876, 3, 1, 0, "Int_CVTSI2SDrr", 0, 0|5|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo124 }, // Inst #876 = Int_CVTSI2SDrr
- { 877, 7, 1, 0, "Int_CVTSI2SS64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #877 = Int_CVTSI2SS64rm
- { 878, 3, 1, 0, "Int_CVTSI2SS64rr", 0, 0|5|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo123 }, // Inst #878 = Int_CVTSI2SS64rr
- { 879, 7, 1, 0, "Int_CVTSI2SSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #879 = Int_CVTSI2SSrm
- { 880, 3, 1, 0, "Int_CVTSI2SSrr", 0, 0|5|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo124 }, // Inst #880 = Int_CVTSI2SSrr
- { 881, 7, 1, 0, "Int_CVTSS2SDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #881 = Int_CVTSS2SDrm
- { 882, 3, 1, 0, "Int_CVTSS2SDrr", 0, 0|5|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #882 = Int_CVTSS2SDrr
- { 883, 6, 1, 0, "Int_CVTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #883 = Int_CVTSS2SI64rm
- { 884, 2, 1, 0, "Int_CVTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #884 = Int_CVTSS2SI64rr
- { 885, 6, 1, 0, "Int_CVTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #885 = Int_CVTSS2SIrm
- { 886, 2, 1, 0, "Int_CVTSS2SIrr", 0, 0|5|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #886 = Int_CVTSS2SIrr
- { 887, 6, 1, 0, "Int_CVTTPD2DQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #887 = Int_CVTTPD2DQrm
- { 888, 2, 1, 0, "Int_CVTTPD2DQrr", 0, 0|5|(1<<6)|(1<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #888 = Int_CVTTPD2DQrr
- { 889, 6, 1, 0, "Int_CVTTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #889 = Int_CVTTPD2PIrm
- { 890, 2, 1, 0, "Int_CVTTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #890 = Int_CVTTPD2PIrr
- { 891, 6, 1, 0, "Int_CVTTPS2DQrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #891 = Int_CVTTPS2DQrm
- { 892, 2, 1, 0, "Int_CVTTPS2DQrr", 0, 0|5|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #892 = Int_CVTTPS2DQrr
- { 893, 6, 1, 0, "Int_CVTTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #893 = Int_CVTTPS2PIrm
- { 894, 2, 1, 0, "Int_CVTTPS2PIrr", 0, 0|5|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #894 = Int_CVTTPS2PIrr
- { 895, 6, 1, 0, "Int_CVTTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #895 = Int_CVTTSD2SI64rm
- { 896, 2, 1, 0, "Int_CVTTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #896 = Int_CVTTSD2SI64rr
- { 897, 6, 1, 0, "Int_CVTTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #897 = Int_CVTTSD2SIrm
- { 898, 2, 1, 0, "Int_CVTTSD2SIrr", 0, 0|5|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #898 = Int_CVTTSD2SIrr
- { 899, 6, 1, 0, "Int_CVTTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #899 = Int_CVTTSS2SI64rm
- { 900, 2, 1, 0, "Int_CVTTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #900 = Int_CVTTSS2SI64rr
- { 901, 6, 1, 0, "Int_CVTTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #901 = Int_CVTTSS2SIrm
- { 902, 2, 1, 0, "Int_CVTTSS2SIrr", 0, 0|5|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #902 = Int_CVTTSS2SIrr
- { 903, 6, 0, 0, "Int_UCOMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #903 = Int_UCOMISDrm
- { 904, 2, 0, 0, "Int_UCOMISDrr", 0, 0|5|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #904 = Int_UCOMISDrr
- { 905, 6, 0, 0, "Int_UCOMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #905 = Int_UCOMISSrm
- { 906, 2, 0, 0, "Int_UCOMISSrr", 0, 0|5|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #906 = Int_UCOMISSrr
- { 907, 1, 0, 0, "JA", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(135<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #907 = JA
- { 908, 1, 0, 0, "JA8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(119<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #908 = JA8
- { 909, 1, 0, 0, "JAE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(131<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #909 = JAE
- { 910, 1, 0, 0, "JAE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(115<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #910 = JAE8
- { 911, 1, 0, 0, "JB", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(130<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #911 = JB
- { 912, 1, 0, 0, "JB8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(114<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #912 = JB8
- { 913, 1, 0, 0, "JBE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(134<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #913 = JBE
- { 914, 1, 0, 0, "JBE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(118<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #914 = JBE8
- { 915, 1, 0, 0, "JCXZ8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(227<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #915 = JCXZ8
- { 916, 1, 0, 0, "JE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(132<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #916 = JE
- { 917, 1, 0, 0, "JE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(116<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #917 = JE8
- { 918, 1, 0, 0, "JG", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(143<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #918 = JG
- { 919, 1, 0, 0, "JG8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(127<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #919 = JG8
- { 920, 1, 0, 0, "JGE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(141<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #920 = JGE
- { 921, 1, 0, 0, "JGE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(125<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #921 = JGE8
- { 922, 1, 0, 0, "JL", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(140<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #922 = JL
- { 923, 1, 0, 0, "JL8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(124<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #923 = JL8
- { 924, 1, 0, 0, "JLE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(142<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #924 = JLE
- { 925, 1, 0, 0, "JLE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(126<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #925 = JLE8
- { 926, 1, 0, 0, "JMP", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #926 = JMP
- { 927, 5, 0, 0, "JMP32m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #927 = JMP32m
- { 928, 1, 0, 0, "JMP32r", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #928 = JMP32r
- { 929, 5, 0, 0, "JMP64m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #929 = JMP64m
- { 930, 1, 0, 0, "JMP64pcrel32", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #930 = JMP64pcrel32
- { 931, 1, 0, 0, "JMP64r", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #931 = JMP64r
- { 932, 1, 0, 0, "JMP8", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(235<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #932 = JMP8
- { 933, 1, 0, 0, "JNE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(133<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #933 = JNE
- { 934, 1, 0, 0, "JNE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(117<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #934 = JNE8
- { 935, 1, 0, 0, "JNO", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(129<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #935 = JNO
- { 936, 1, 0, 0, "JNO8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(113<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #936 = JNO8
- { 937, 1, 0, 0, "JNP", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(139<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #937 = JNP
- { 938, 1, 0, 0, "JNP8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(123<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #938 = JNP8
- { 939, 1, 0, 0, "JNS", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(137<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #939 = JNS
- { 940, 1, 0, 0, "JNS8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(121<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #940 = JNS8
- { 941, 1, 0, 0, "JO", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(128<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #941 = JO
- { 942, 1, 0, 0, "JO8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(112<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #942 = JO8
- { 943, 1, 0, 0, "JP", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(138<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #943 = JP
- { 944, 1, 0, 0, "JP8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(122<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #944 = JP8
- { 945, 1, 0, 0, "JS", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(136<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #945 = JS
- { 946, 1, 0, 0, "JS8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(120<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #946 = JS8
- { 947, 0, 0, 0, "LAHF", 0, 0|1|(159<<24), ImplicitList1, ImplicitList26, NULL, 0 }, // Inst #947 = LAHF
- { 948, 6, 1, 0, "LAR16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #948 = LAR16rm
- { 949, 2, 1, 0, "LAR16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #949 = LAR16rr
- { 950, 6, 1, 0, "LAR32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #950 = LAR32rm
- { 951, 2, 1, 0, "LAR32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #951 = LAR32rr
- { 952, 6, 1, 0, "LAR64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(2<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #952 = LAR64rm
- { 953, 2, 1, 0, "LAR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(2<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #953 = LAR64rr
- { 954, 6, 0, 0, "LCMPXCHG16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<19)|(177<<24), ImplicitList12, ImplicitList27, Barriers1, OperandInfo7 }, // Inst #954 = LCMPXCHG16
- { 955, 6, 0, 0, "LCMPXCHG32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<19)|(177<<24), ImplicitList13, ImplicitList28, Barriers1, OperandInfo11 }, // Inst #955 = LCMPXCHG32
- { 956, 6, 0, 0, "LCMPXCHG64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<19)|(177<<24), ImplicitList15, ImplicitList29, Barriers1, OperandInfo15 }, // Inst #956 = LCMPXCHG64
- { 957, 6, 0, 0, "LCMPXCHG8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<19)|(176<<24), ImplicitList11, ImplicitList30, Barriers1, OperandInfo20 }, // Inst #957 = LCMPXCHG8
- { 958, 5, 0, 0, "LCMPXCHG8B", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<8)|(1<<19)|(199<<24), ImplicitList6, ImplicitList19, Barriers6, OperandInfo30 }, // Inst #958 = LCMPXCHG8B
- { 959, 6, 1, 0, "LDDQUrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(240<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #959 = LDDQUrm
- { 960, 5, 0, 0, "LDMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #960 = LDMXCSR
- { 961, 6, 1, 0, "LDS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(197<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #961 = LDS16rm
- { 962, 6, 1, 0, "LDS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(197<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #962 = LDS32rm
- { 963, 0, 0, 0, "LD_F0", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(238<<24), NULL, NULL, NULL, 0 }, // Inst #963 = LD_F0
- { 964, 0, 0, 0, "LD_F1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(232<<24), NULL, NULL, NULL, 0 }, // Inst #964 = LD_F1
- { 965, 5, 0, 0, "LD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #965 = LD_F32m
- { 966, 5, 0, 0, "LD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #966 = LD_F64m
- { 967, 5, 0, 0, "LD_F80m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #967 = LD_F80m
- { 968, 1, 1, 0, "LD_Fp032", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #968 = LD_Fp032
- { 969, 1, 1, 0, "LD_Fp064", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #969 = LD_Fp064
- { 970, 1, 1, 0, "LD_Fp080", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #970 = LD_Fp080
- { 971, 1, 1, 0, "LD_Fp132", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #971 = LD_Fp132
- { 972, 1, 1, 0, "LD_Fp164", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #972 = LD_Fp164
- { 973, 1, 1, 0, "LD_Fp180", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #973 = LD_Fp180
- { 974, 6, 1, 0, "LD_Fp32m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #974 = LD_Fp32m
- { 975, 6, 1, 0, "LD_Fp32m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #975 = LD_Fp32m64
- { 976, 6, 1, 0, "LD_Fp32m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #976 = LD_Fp32m80
- { 977, 6, 1, 0, "LD_Fp64m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #977 = LD_Fp64m
- { 978, 6, 1, 0, "LD_Fp64m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #978 = LD_Fp64m80
- { 979, 6, 1, 0, "LD_Fp80m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #979 = LD_Fp80m
- { 980, 1, 0, 0, "LD_Frr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(4<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #980 = LD_Frr
- { 981, 5, 1, 0, "LEA16r", 0, 0|6|(1<<6)|(141<<24), NULL, NULL, NULL, OperandInfo126 }, // Inst #981 = LEA16r
- { 982, 5, 1, 0, "LEA32r", 0|(1<<TID::Rematerializable), 0|6|(141<<24), NULL, NULL, NULL, OperandInfo127 }, // Inst #982 = LEA32r
- { 983, 5, 1, 0, "LEA64_32r", 0, 0|6|(141<<24), NULL, NULL, NULL, OperandInfo127 }, // Inst #983 = LEA64_32r
- { 984, 5, 1, 0, "LEA64r", 0|(1<<TID::Rematerializable), 0|6|(1<<12)|(141<<24), NULL, NULL, NULL, OperandInfo128 }, // Inst #984 = LEA64r
- { 985, 0, 0, 0, "LEAVE", 0|(1<<TID::MayLoad), 0|1|(201<<24), ImplicitList31, ImplicitList31, NULL, 0 }, // Inst #985 = LEAVE
- { 986, 0, 0, 0, "LEAVE64", 0|(1<<TID::MayLoad), 0|1|(201<<24), ImplicitList32, ImplicitList32, NULL, 0 }, // Inst #986 = LEAVE64
- { 987, 6, 1, 0, "LES16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(196<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #987 = LES16rm
- { 988, 6, 1, 0, "LES32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(196<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #988 = LES32rm
- { 989, 0, 0, 0, "LFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #989 = LFENCE
- { 990, 6, 1, 0, "LFS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(180<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #990 = LFS16rm
- { 991, 6, 1, 0, "LFS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(180<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #991 = LFS32rm
- { 992, 6, 1, 0, "LFS64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(180<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #992 = LFS64rm
- { 993, 5, 0, 0, "LGDTm", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #993 = LGDTm
- { 994, 6, 1, 0, "LGS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(181<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #994 = LGS16rm
- { 995, 6, 1, 0, "LGS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(181<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #995 = LGS32rm
- { 996, 6, 1, 0, "LGS64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(181<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #996 = LGS64rm
- { 997, 5, 0, 0, "LIDTm", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #997 = LIDTm
- { 998, 5, 0, 0, "LLDT16m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #998 = LLDT16m
- { 999, 1, 0, 0, "LLDT16r", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #999 = LLDT16r
- { 1000, 5, 0, 0, "LMSW16m", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1000 = LMSW16m
- { 1001, 1, 0, 0, "LMSW16r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #1001 = LMSW16r
- { 1002, 6, 0, 0, "LOCK_ADD16mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(2<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1002 = LOCK_ADD16mi
- { 1003, 6, 0, 0, "LOCK_ADD16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<6)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1003 = LOCK_ADD16mi8
- { 1004, 6, 0, 0, "LOCK_ADD16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<19)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1004 = LOCK_ADD16mr
- { 1005, 6, 0, 0, "LOCK_ADD32mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1005 = LOCK_ADD32mi
- { 1006, 6, 0, 0, "LOCK_ADD32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1006 = LOCK_ADD32mi8
- { 1007, 6, 0, 0, "LOCK_ADD32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1007 = LOCK_ADD32mr
- { 1008, 6, 0, 0, "LOCK_ADD64mi32", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1008 = LOCK_ADD64mi32
- { 1009, 6, 0, 0, "LOCK_ADD64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1009 = LOCK_ADD64mi8
- { 1010, 6, 0, 0, "LOCK_ADD64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(1<<19)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1010 = LOCK_ADD64mr
- { 1011, 6, 0, 0, "LOCK_ADD8mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<13)|(1<<19)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1011 = LOCK_ADD8mi
- { 1012, 6, 0, 0, "LOCK_ADD8mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1012 = LOCK_ADD8mr
- { 1013, 5, 0, 0, "LOCK_DEC16m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<6)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1013 = LOCK_DEC16m
- { 1014, 5, 0, 0, "LOCK_DEC32m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1014 = LOCK_DEC32m
- { 1015, 5, 0, 0, "LOCK_DEC64m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<12)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1015 = LOCK_DEC64m
- { 1016, 5, 0, 0, "LOCK_DEC8m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<19)|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1016 = LOCK_DEC8m
- { 1017, 5, 0, 0, "LOCK_INC16m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<6)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1017 = LOCK_INC16m
- { 1018, 5, 0, 0, "LOCK_INC32m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1018 = LOCK_INC32m
- { 1019, 5, 0, 0, "LOCK_INC64m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1019 = LOCK_INC64m
- { 1020, 5, 0, 0, "LOCK_INC8m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<19)|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1020 = LOCK_INC8m
- { 1021, 6, 0, 0, "LOCK_SUB16mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(2<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1021 = LOCK_SUB16mi
- { 1022, 6, 0, 0, "LOCK_SUB16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1022 = LOCK_SUB16mi8
- { 1023, 6, 0, 0, "LOCK_SUB16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1023 = LOCK_SUB16mr
- { 1024, 6, 0, 0, "LOCK_SUB32mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1024 = LOCK_SUB32mi
- { 1025, 6, 0, 0, "LOCK_SUB32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1025 = LOCK_SUB32mi8
- { 1026, 6, 0, 0, "LOCK_SUB32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1026 = LOCK_SUB32mr
- { 1027, 6, 0, 0, "LOCK_SUB64mi32", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1027 = LOCK_SUB64mi32
- { 1028, 6, 0, 0, "LOCK_SUB64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1028 = LOCK_SUB64mi8
- { 1029, 6, 0, 0, "LOCK_SUB64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1029 = LOCK_SUB64mr
- { 1030, 6, 0, 0, "LOCK_SUB8mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<13)|(1<<19)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1030 = LOCK_SUB8mi
- { 1031, 6, 0, 0, "LOCK_SUB8mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1031 = LOCK_SUB8mr
- { 1032, 0, 0, 0, "LODSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(172<<24), NULL, NULL, NULL, 0 }, // Inst #1032 = LODSB
- { 1033, 0, 0, 0, "LODSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(173<<24), NULL, NULL, NULL, 0 }, // Inst #1033 = LODSD
- { 1034, 0, 0, 0, "LODSQ", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(173<<24), NULL, NULL, NULL, 0 }, // Inst #1034 = LODSQ
- { 1035, 0, 0, 0, "LODSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(173<<24), NULL, NULL, NULL, 0 }, // Inst #1035 = LODSW
- { 1036, 1, 1, 0, "LOOP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(226<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1036 = LOOP
- { 1037, 1, 1, 0, "LOOPE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(225<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1037 = LOOPE
- { 1038, 1, 1, 0, "LOOPNE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(224<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1038 = LOOPNE
- { 1039, 0, 0, 0, "LRET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(7<<16)|(203<<24), NULL, NULL, NULL, 0 }, // Inst #1039 = LRET
- { 1040, 1, 0, 0, "LRETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(7<<16)|(202<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1040 = LRETI
- { 1041, 6, 1, 0, "LSL16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1041 = LSL16rm
- { 1042, 2, 1, 0, "LSL16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1042 = LSL16rr
- { 1043, 6, 1, 0, "LSL32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1043 = LSL32rm
- { 1044, 2, 1, 0, "LSL32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1044 = LSL32rr
- { 1045, 6, 1, 0, "LSL64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(3<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1045 = LSL64rm
- { 1046, 2, 1, 0, "LSL64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(3<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1046 = LSL64rr
- { 1047, 6, 1, 0, "LSS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(178<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1047 = LSS16rm
- { 1048, 6, 1, 0, "LSS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(178<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1048 = LSS32rm
- { 1049, 6, 1, 0, "LSS64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(178<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1049 = LSS64rm
- { 1050, 5, 0, 0, "LTRm", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #1050 = LTRm
- { 1051, 1, 0, 0, "LTRr", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #1051 = LTRr
- { 1052, 7, 1, 0, "LXADD16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<6)|(1<<8)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1052 = LXADD16
- { 1053, 7, 1, 0, "LXADD32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #1053 = LXADD32
- { 1054, 7, 1, 0, "LXADD64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<12)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #1054 = LXADD64
- { 1055, 7, 1, 0, "LXADD8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<19)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1055 = LXADD8
- { 1056, 2, 0, 0, "MASKMOVDQU", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(247<<24), ImplicitList33, NULL, NULL, OperandInfo75 }, // Inst #1056 = MASKMOVDQU
- { 1057, 2, 0, 0, "MASKMOVDQU64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(247<<24), ImplicitList34, NULL, NULL, OperandInfo75 }, // Inst #1057 = MASKMOVDQU64
- { 1058, 7, 1, 0, "MAXPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1058 = MAXPDrm
- { 1059, 7, 1, 0, "MAXPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1059 = MAXPDrm_Int
- { 1060, 3, 1, 0, "MAXPDrr", 0, 0|5|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1060 = MAXPDrr
- { 1061, 3, 1, 0, "MAXPDrr_Int", 0, 0|5|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1061 = MAXPDrr_Int
- { 1062, 7, 1, 0, "MAXPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1062 = MAXPSrm
- { 1063, 7, 1, 0, "MAXPSrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1063 = MAXPSrm_Int
- { 1064, 3, 1, 0, "MAXPSrr", 0, 0|5|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1064 = MAXPSrr
- { 1065, 3, 1, 0, "MAXPSrr_Int", 0, 0|5|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1065 = MAXPSrr_Int
- { 1066, 7, 1, 0, "MAXSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1066 = MAXSDrm
- { 1067, 7, 1, 0, "MAXSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1067 = MAXSDrm_Int
- { 1068, 3, 1, 0, "MAXSDrr", 0, 0|5|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1068 = MAXSDrr
- { 1069, 3, 1, 0, "MAXSDrr_Int", 0, 0|5|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1069 = MAXSDrr_Int
- { 1070, 7, 1, 0, "MAXSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1070 = MAXSSrm
- { 1071, 7, 1, 0, "MAXSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1071 = MAXSSrm_Int
- { 1072, 3, 1, 0, "MAXSSrr", 0, 0|5|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1072 = MAXSSrr
- { 1073, 3, 1, 0, "MAXSSrr_Int", 0, 0|5|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1073 = MAXSSrr_Int
- { 1074, 0, 0, 0, "MFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|22|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #1074 = MFENCE
- { 1075, 7, 1, 0, "MINPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1075 = MINPDrm
- { 1076, 7, 1, 0, "MINPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1076 = MINPDrm_Int
- { 1077, 3, 1, 0, "MINPDrr", 0, 0|5|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1077 = MINPDrr
- { 1078, 3, 1, 0, "MINPDrr_Int", 0, 0|5|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1078 = MINPDrr_Int
- { 1079, 7, 1, 0, "MINPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1079 = MINPSrm
- { 1080, 7, 1, 0, "MINPSrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1080 = MINPSrm_Int
- { 1081, 3, 1, 0, "MINPSrr", 0, 0|5|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1081 = MINPSrr
- { 1082, 3, 1, 0, "MINPSrr_Int", 0, 0|5|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1082 = MINPSrr_Int
- { 1083, 7, 1, 0, "MINSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1083 = MINSDrm
- { 1084, 7, 1, 0, "MINSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1084 = MINSDrm_Int
- { 1085, 3, 1, 0, "MINSDrr", 0, 0|5|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1085 = MINSDrr
- { 1086, 3, 1, 0, "MINSDrr_Int", 0, 0|5|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1086 = MINSDrr_Int
- { 1087, 7, 1, 0, "MINSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1087 = MINSSrm
- { 1088, 7, 1, 0, "MINSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1088 = MINSSrm_Int
- { 1089, 3, 1, 0, "MINSSrr", 0, 0|5|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1089 = MINSSrr
- { 1090, 3, 1, 0, "MINSSrr_Int", 0, 0|5|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1090 = MINSSrr_Int
- { 1091, 6, 1, 0, "MMX_CVTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1091 = MMX_CVTPD2PIrm
- { 1092, 2, 1, 0, "MMX_CVTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1092 = MMX_CVTPD2PIrr
- { 1093, 6, 1, 0, "MMX_CVTPI2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1093 = MMX_CVTPI2PDrm
- { 1094, 2, 1, 0, "MMX_CVTPI2PDrr", 0, 0|5|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1094 = MMX_CVTPI2PDrr
- { 1095, 6, 1, 0, "MMX_CVTPI2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1095 = MMX_CVTPI2PSrm
- { 1096, 2, 1, 0, "MMX_CVTPI2PSrr", 0, 0|5|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1096 = MMX_CVTPI2PSrr
- { 1097, 6, 1, 0, "MMX_CVTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1097 = MMX_CVTPS2PIrm
- { 1098, 2, 1, 0, "MMX_CVTPS2PIrr", 0, 0|5|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1098 = MMX_CVTPS2PIrr
- { 1099, 6, 1, 0, "MMX_CVTTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1099 = MMX_CVTTPD2PIrm
- { 1100, 2, 1, 0, "MMX_CVTTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1100 = MMX_CVTTPD2PIrr
- { 1101, 6, 1, 0, "MMX_CVTTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1101 = MMX_CVTTPS2PIrm
- { 1102, 2, 1, 0, "MMX_CVTTPS2PIrr", 0, 0|5|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1102 = MMX_CVTTPS2PIrr
- { 1103, 0, 0, 0, "MMX_EMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(119<<24), NULL, NULL, NULL, 0 }, // Inst #1103 = MMX_EMMS
- { 1104, 0, 0, 0, "MMX_FEMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(14<<24), NULL, NULL, NULL, 0 }, // Inst #1104 = MMX_FEMMS
- { 1105, 2, 0, 0, "MMX_MASKMOVQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(247<<24), ImplicitList33, NULL, NULL, OperandInfo129 }, // Inst #1105 = MMX_MASKMOVQ
- { 1106, 2, 0, 0, "MMX_MASKMOVQ64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(247<<24), ImplicitList34, NULL, NULL, OperandInfo129 }, // Inst #1106 = MMX_MASKMOVQ64
- { 1107, 2, 1, 0, "MMX_MOVD64from64rr", 0, 0|3|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo130 }, // Inst #1107 = MMX_MOVD64from64rr
- { 1108, 2, 0, 0, "MMX_MOVD64grr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo131 }, // Inst #1108 = MMX_MOVD64grr
- { 1109, 6, 0, 0, "MMX_MOVD64mr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1109 = MMX_MOVD64mr
- { 1110, 6, 1, 0, "MMX_MOVD64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1110 = MMX_MOVD64rm
- { 1111, 2, 1, 0, "MMX_MOVD64rr", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo133 }, // Inst #1111 = MMX_MOVD64rr
- { 1112, 2, 1, 0, "MMX_MOVD64rrv164", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1112 = MMX_MOVD64rrv164
- { 1113, 2, 1, 0, "MMX_MOVD64to64rr", 0, 0|5|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1113 = MMX_MOVD64to64rr
- { 1114, 2, 1, 0, "MMX_MOVDQ2Qrr", 0, 0|5|(11<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1114 = MMX_MOVDQ2Qrr
- { 1115, 6, 0, 0, "MMX_MOVNTQmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1115 = MMX_MOVNTQmr
- { 1116, 2, 1, 0, "MMX_MOVQ2DQrr", 0, 0|5|(12<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1116 = MMX_MOVQ2DQrr
- { 1117, 2, 1, 0, "MMX_MOVQ2FR64rr", 0, 0|5|(12<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1117 = MMX_MOVQ2FR64rr
- { 1118, 6, 0, 0, "MMX_MOVQ64gmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1118 = MMX_MOVQ64gmr
- { 1119, 6, 0, 0, "MMX_MOVQ64mr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(127<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1119 = MMX_MOVQ64mr
- { 1120, 6, 1, 0, "MMX_MOVQ64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1120 = MMX_MOVQ64rm
- { 1121, 2, 1, 0, "MMX_MOVQ64rr", 0, 0|5|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1121 = MMX_MOVQ64rr
- { 1122, 6, 1, 0, "MMX_MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1122 = MMX_MOVZDI2PDIrm
- { 1123, 2, 1, 0, "MMX_MOVZDI2PDIrr", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo133 }, // Inst #1123 = MMX_MOVZDI2PDIrr
- { 1124, 7, 1, 0, "MMX_PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1124 = MMX_PACKSSDWrm
- { 1125, 3, 1, 0, "MMX_PACKSSDWrr", 0, 0|5|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1125 = MMX_PACKSSDWrr
- { 1126, 7, 1, 0, "MMX_PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1126 = MMX_PACKSSWBrm
- { 1127, 3, 1, 0, "MMX_PACKSSWBrr", 0, 0|5|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1127 = MMX_PACKSSWBrr
- { 1128, 7, 1, 0, "MMX_PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1128 = MMX_PACKUSWBrm
- { 1129, 3, 1, 0, "MMX_PACKUSWBrr", 0, 0|5|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1129 = MMX_PACKUSWBrr
- { 1130, 7, 1, 0, "MMX_PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1130 = MMX_PADDBrm
- { 1131, 3, 1, 0, "MMX_PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1131 = MMX_PADDBrr
- { 1132, 7, 1, 0, "MMX_PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1132 = MMX_PADDDrm
- { 1133, 3, 1, 0, "MMX_PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1133 = MMX_PADDDrr
- { 1134, 7, 1, 0, "MMX_PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1134 = MMX_PADDQrm
- { 1135, 3, 1, 0, "MMX_PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1135 = MMX_PADDQrr
- { 1136, 7, 1, 0, "MMX_PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1136 = MMX_PADDSBrm
- { 1137, 3, 1, 0, "MMX_PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1137 = MMX_PADDSBrr
- { 1138, 7, 1, 0, "MMX_PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1138 = MMX_PADDSWrm
- { 1139, 3, 1, 0, "MMX_PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1139 = MMX_PADDSWrr
- { 1140, 7, 1, 0, "MMX_PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1140 = MMX_PADDUSBrm
- { 1141, 3, 1, 0, "MMX_PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1141 = MMX_PADDUSBrr
- { 1142, 7, 1, 0, "MMX_PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1142 = MMX_PADDUSWrm
- { 1143, 3, 1, 0, "MMX_PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1143 = MMX_PADDUSWrr
- { 1144, 7, 1, 0, "MMX_PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1144 = MMX_PADDWrm
- { 1145, 3, 1, 0, "MMX_PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1145 = MMX_PADDWrr
- { 1146, 7, 1, 0, "MMX_PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1146 = MMX_PANDNrm
- { 1147, 3, 1, 0, "MMX_PANDNrr", 0, 0|5|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1147 = MMX_PANDNrr
- { 1148, 7, 1, 0, "MMX_PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1148 = MMX_PANDrm
- { 1149, 3, 1, 0, "MMX_PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1149 = MMX_PANDrr
- { 1150, 7, 1, 0, "MMX_PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1150 = MMX_PAVGBrm
- { 1151, 3, 1, 0, "MMX_PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1151 = MMX_PAVGBrr
- { 1152, 7, 1, 0, "MMX_PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1152 = MMX_PAVGWrm
- { 1153, 3, 1, 0, "MMX_PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1153 = MMX_PAVGWrr
- { 1154, 7, 1, 0, "MMX_PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1154 = MMX_PCMPEQBrm
- { 1155, 3, 1, 0, "MMX_PCMPEQBrr", 0, 0|5|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1155 = MMX_PCMPEQBrr
- { 1156, 7, 1, 0, "MMX_PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1156 = MMX_PCMPEQDrm
- { 1157, 3, 1, 0, "MMX_PCMPEQDrr", 0, 0|5|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1157 = MMX_PCMPEQDrr
- { 1158, 7, 1, 0, "MMX_PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1158 = MMX_PCMPEQWrm
- { 1159, 3, 1, 0, "MMX_PCMPEQWrr", 0, 0|5|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1159 = MMX_PCMPEQWrr
- { 1160, 7, 1, 0, "MMX_PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1160 = MMX_PCMPGTBrm
- { 1161, 3, 1, 0, "MMX_PCMPGTBrr", 0, 0|5|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1161 = MMX_PCMPGTBrr
- { 1162, 7, 1, 0, "MMX_PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1162 = MMX_PCMPGTDrm
- { 1163, 3, 1, 0, "MMX_PCMPGTDrr", 0, 0|5|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1163 = MMX_PCMPGTDrr
- { 1164, 7, 1, 0, "MMX_PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1164 = MMX_PCMPGTWrm
- { 1165, 3, 1, 0, "MMX_PCMPGTWrr", 0, 0|5|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1165 = MMX_PCMPGTWrr
- { 1166, 3, 1, 0, "MMX_PEXTRWri", 0, 0|5|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo138 }, // Inst #1166 = MMX_PEXTRWri
- { 1167, 8, 1, 0, "MMX_PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo139 }, // Inst #1167 = MMX_PINSRWrmi
- { 1168, 4, 1, 0, "MMX_PINSRWrri", 0, 0|5|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo140 }, // Inst #1168 = MMX_PINSRWrri
- { 1169, 7, 1, 0, "MMX_PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1169 = MMX_PMADDWDrm
- { 1170, 3, 1, 0, "MMX_PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1170 = MMX_PMADDWDrr
- { 1171, 7, 1, 0, "MMX_PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1171 = MMX_PMAXSWrm
- { 1172, 3, 1, 0, "MMX_PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1172 = MMX_PMAXSWrr
- { 1173, 7, 1, 0, "MMX_PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1173 = MMX_PMAXUBrm
- { 1174, 3, 1, 0, "MMX_PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1174 = MMX_PMAXUBrr
- { 1175, 7, 1, 0, "MMX_PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1175 = MMX_PMINSWrm
- { 1176, 3, 1, 0, "MMX_PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1176 = MMX_PMINSWrr
- { 1177, 7, 1, 0, "MMX_PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1177 = MMX_PMINUBrm
- { 1178, 3, 1, 0, "MMX_PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1178 = MMX_PMINUBrr
- { 1179, 2, 1, 0, "MMX_PMOVMSKBrr", 0, 0|5|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo131 }, // Inst #1179 = MMX_PMOVMSKBrr
- { 1180, 7, 1, 0, "MMX_PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1180 = MMX_PMULHUWrm
- { 1181, 3, 1, 0, "MMX_PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1181 = MMX_PMULHUWrr
- { 1182, 7, 1, 0, "MMX_PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1182 = MMX_PMULHWrm
- { 1183, 3, 1, 0, "MMX_PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1183 = MMX_PMULHWrr
- { 1184, 7, 1, 0, "MMX_PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1184 = MMX_PMULLWrm
- { 1185, 3, 1, 0, "MMX_PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1185 = MMX_PMULLWrr
- { 1186, 7, 1, 0, "MMX_PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1186 = MMX_PMULUDQrm
- { 1187, 3, 1, 0, "MMX_PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1187 = MMX_PMULUDQrr
- { 1188, 7, 1, 0, "MMX_PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1188 = MMX_PORrm
- { 1189, 3, 1, 0, "MMX_PORrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1189 = MMX_PORrr
- { 1190, 7, 1, 0, "MMX_PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1190 = MMX_PSADBWrm
- { 1191, 3, 1, 0, "MMX_PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1191 = MMX_PSADBWrr
- { 1192, 7, 1, 0, "MMX_PSHUFWmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo141 }, // Inst #1192 = MMX_PSHUFWmi
- { 1193, 3, 1, 0, "MMX_PSHUFWri", 0, 0|5|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1193 = MMX_PSHUFWri
- { 1194, 3, 1, 0, "MMX_PSLLDri", 0, 0|22|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1194 = MMX_PSLLDri
- { 1195, 7, 1, 0, "MMX_PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1195 = MMX_PSLLDrm
- { 1196, 3, 1, 0, "MMX_PSLLDrr", 0, 0|5|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1196 = MMX_PSLLDrr
- { 1197, 3, 1, 0, "MMX_PSLLQri", 0, 0|22|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1197 = MMX_PSLLQri
- { 1198, 7, 1, 0, "MMX_PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1198 = MMX_PSLLQrm
- { 1199, 3, 1, 0, "MMX_PSLLQrr", 0, 0|5|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1199 = MMX_PSLLQrr
- { 1200, 3, 1, 0, "MMX_PSLLWri", 0, 0|22|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1200 = MMX_PSLLWri
- { 1201, 7, 1, 0, "MMX_PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1201 = MMX_PSLLWrm
- { 1202, 3, 1, 0, "MMX_PSLLWrr", 0, 0|5|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1202 = MMX_PSLLWrr
- { 1203, 3, 1, 0, "MMX_PSRADri", 0, 0|20|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1203 = MMX_PSRADri
- { 1204, 7, 1, 0, "MMX_PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1204 = MMX_PSRADrm
- { 1205, 3, 1, 0, "MMX_PSRADrr", 0, 0|5|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1205 = MMX_PSRADrr
- { 1206, 3, 1, 0, "MMX_PSRAWri", 0, 0|20|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1206 = MMX_PSRAWri
- { 1207, 7, 1, 0, "MMX_PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1207 = MMX_PSRAWrm
- { 1208, 3, 1, 0, "MMX_PSRAWrr", 0, 0|5|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1208 = MMX_PSRAWrr
- { 1209, 3, 1, 0, "MMX_PSRLDri", 0, 0|18|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1209 = MMX_PSRLDri
- { 1210, 7, 1, 0, "MMX_PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1210 = MMX_PSRLDrm
- { 1211, 3, 1, 0, "MMX_PSRLDrr", 0, 0|5|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1211 = MMX_PSRLDrr
- { 1212, 3, 1, 0, "MMX_PSRLQri", 0, 0|18|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1212 = MMX_PSRLQri
- { 1213, 7, 1, 0, "MMX_PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1213 = MMX_PSRLQrm
- { 1214, 3, 1, 0, "MMX_PSRLQrr", 0, 0|5|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1214 = MMX_PSRLQrr
- { 1215, 3, 1, 0, "MMX_PSRLWri", 0, 0|18|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1215 = MMX_PSRLWri
- { 1216, 7, 1, 0, "MMX_PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1216 = MMX_PSRLWrm
- { 1217, 3, 1, 0, "MMX_PSRLWrr", 0, 0|5|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1217 = MMX_PSRLWrr
- { 1218, 7, 1, 0, "MMX_PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1218 = MMX_PSUBBrm
- { 1219, 3, 1, 0, "MMX_PSUBBrr", 0, 0|5|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1219 = MMX_PSUBBrr
- { 1220, 7, 1, 0, "MMX_PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1220 = MMX_PSUBDrm
- { 1221, 3, 1, 0, "MMX_PSUBDrr", 0, 0|5|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1221 = MMX_PSUBDrr
- { 1222, 7, 1, 0, "MMX_PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1222 = MMX_PSUBQrm
- { 1223, 3, 1, 0, "MMX_PSUBQrr", 0, 0|5|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1223 = MMX_PSUBQrr
- { 1224, 7, 1, 0, "MMX_PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1224 = MMX_PSUBSBrm
- { 1225, 3, 1, 0, "MMX_PSUBSBrr", 0, 0|5|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1225 = MMX_PSUBSBrr
- { 1226, 7, 1, 0, "MMX_PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1226 = MMX_PSUBSWrm
- { 1227, 3, 1, 0, "MMX_PSUBSWrr", 0, 0|5|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1227 = MMX_PSUBSWrr
- { 1228, 7, 1, 0, "MMX_PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1228 = MMX_PSUBUSBrm
- { 1229, 3, 1, 0, "MMX_PSUBUSBrr", 0, 0|5|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1229 = MMX_PSUBUSBrr
- { 1230, 7, 1, 0, "MMX_PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1230 = MMX_PSUBUSWrm
- { 1231, 3, 1, 0, "MMX_PSUBUSWrr", 0, 0|5|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1231 = MMX_PSUBUSWrr
- { 1232, 7, 1, 0, "MMX_PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1232 = MMX_PSUBWrm
- { 1233, 3, 1, 0, "MMX_PSUBWrr", 0, 0|5|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1233 = MMX_PSUBWrr
- { 1234, 7, 1, 0, "MMX_PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1234 = MMX_PUNPCKHBWrm
- { 1235, 3, 1, 0, "MMX_PUNPCKHBWrr", 0, 0|5|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1235 = MMX_PUNPCKHBWrr
- { 1236, 7, 1, 0, "MMX_PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1236 = MMX_PUNPCKHDQrm
- { 1237, 3, 1, 0, "MMX_PUNPCKHDQrr", 0, 0|5|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1237 = MMX_PUNPCKHDQrr
- { 1238, 7, 1, 0, "MMX_PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1238 = MMX_PUNPCKHWDrm
- { 1239, 3, 1, 0, "MMX_PUNPCKHWDrr", 0, 0|5|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1239 = MMX_PUNPCKHWDrr
- { 1240, 7, 1, 0, "MMX_PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1240 = MMX_PUNPCKLBWrm
- { 1241, 3, 1, 0, "MMX_PUNPCKLBWrr", 0, 0|5|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1241 = MMX_PUNPCKLBWrr
- { 1242, 7, 1, 0, "MMX_PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1242 = MMX_PUNPCKLDQrm
- { 1243, 3, 1, 0, "MMX_PUNPCKLDQrr", 0, 0|5|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1243 = MMX_PUNPCKLDQrr
- { 1244, 7, 1, 0, "MMX_PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1244 = MMX_PUNPCKLWDrm
- { 1245, 3, 1, 0, "MMX_PUNPCKLWDrr", 0, 0|5|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1245 = MMX_PUNPCKLWDrr
- { 1246, 7, 1, 0, "MMX_PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1246 = MMX_PXORrm
- { 1247, 3, 1, 0, "MMX_PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1247 = MMX_PXORrr
- { 1248, 1, 1, 0, "MMX_V_SET0", 0|(1<<TID::Rematerializable), 0|32|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo144 }, // Inst #1248 = MMX_V_SET0
- { 1249, 1, 1, 0, "MMX_V_SETALLONES", 0|(1<<TID::Rematerializable), 0|32|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo144 }, // Inst #1249 = MMX_V_SETALLONES
- { 1250, 0, 0, 0, "MONITOR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1250 = MONITOR
- { 1251, 1, 1, 0, "MOV16ao16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1251 = MOV16ao16
- { 1252, 6, 0, 0, "MOV16mi", 0|(1<<TID::MayStore), 0|24|(1<<6)|(2<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1252 = MOV16mi
- { 1253, 6, 0, 0, "MOV16mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(137<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #1253 = MOV16mr
- { 1254, 6, 1, 0, "MOV16ms", 0|(1<<TID::UnmodeledSideEffects), 0|4|(140<<24), NULL, NULL, NULL, OperandInfo145 }, // Inst #1254 = MOV16ms
- { 1255, 1, 0, 0, "MOV16o16a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1255 = MOV16o16a
- { 1256, 2, 1, 0, "MOV16ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<6)|(2<<13)|(184<<24), NULL, NULL, NULL, OperandInfo54 }, // Inst #1256 = MOV16ri
- { 1257, 6, 1, 0, "MOV16rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(139<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1257 = MOV16rm
- { 1258, 2, 1, 0, "MOV16rr", 0, 0|3|(1<<6)|(137<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1258 = MOV16rr
- { 1259, 2, 1, 0, "MOV16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(139<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1259 = MOV16rr_REV
- { 1260, 2, 1, 0, "MOV16rs", 0|(1<<TID::UnmodeledSideEffects), 0|3|(140<<24), NULL, NULL, NULL, OperandInfo146 }, // Inst #1260 = MOV16rs
- { 1261, 6, 1, 0, "MOV16sm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(142<<24), NULL, NULL, NULL, OperandInfo147 }, // Inst #1261 = MOV16sm
- { 1262, 2, 1, 0, "MOV16sr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(142<<24), NULL, NULL, NULL, OperandInfo148 }, // Inst #1262 = MOV16sr
- { 1263, 1, 1, 0, "MOV32ao32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1263 = MOV32ao32
- { 1264, 2, 1, 0, "MOV32cr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(34<<24), NULL, NULL, NULL, OperandInfo149 }, // Inst #1264 = MOV32cr
- { 1265, 2, 1, 0, "MOV32dr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(35<<24), NULL, NULL, NULL, OperandInfo150 }, // Inst #1265 = MOV32dr
- { 1266, 6, 0, 0, "MOV32mi", 0|(1<<TID::MayStore), 0|24|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1266 = MOV32mi
- { 1267, 6, 0, 0, "MOV32mr", 0|(1<<TID::MayStore), 0|4|(137<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1267 = MOV32mr
- { 1268, 1, 0, 0, "MOV32o32a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1268 = MOV32o32a
- { 1269, 1, 1, 0, "MOV32r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo57 }, // Inst #1269 = MOV32r0
- { 1270, 2, 1, 0, "MOV32rc", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(32<<24), NULL, NULL, NULL, OperandInfo151 }, // Inst #1270 = MOV32rc
- { 1271, 2, 1, 0, "MOV32rd", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(33<<24), NULL, NULL, NULL, OperandInfo152 }, // Inst #1271 = MOV32rd
- { 1272, 2, 1, 0, "MOV32ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(3<<13)|(184<<24), NULL, NULL, NULL, OperandInfo55 }, // Inst #1272 = MOV32ri
- { 1273, 6, 1, 0, "MOV32rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1273 = MOV32rm
- { 1274, 2, 1, 0, "MOV32rr", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1274 = MOV32rr
- { 1275, 2, 1, 0, "MOV32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(139<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1275 = MOV32rr_REV
- { 1276, 6, 1, 0, "MOV64FSrm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(1<<20)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1276 = MOV64FSrm
- { 1277, 6, 1, 0, "MOV64GSrm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(2<<20)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1277 = MOV64GSrm
- { 1278, 1, 1, 0, "MOV64ao64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1278 = MOV64ao64
- { 1279, 1, 1, 0, "MOV64ao8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(1<<13)|(162<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1279 = MOV64ao8
- { 1280, 2, 1, 0, "MOV64cr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(34<<24), NULL, NULL, NULL, OperandInfo153 }, // Inst #1280 = MOV64cr
- { 1281, 2, 1, 0, "MOV64dr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(35<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1281 = MOV64dr
- { 1282, 6, 0, 0, "MOV64mi32", 0|(1<<TID::MayStore), 0|24|(1<<12)|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1282 = MOV64mi32
- { 1283, 6, 0, 0, "MOV64mr", 0|(1<<TID::MayStore), 0|4|(1<<12)|(137<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #1283 = MOV64mr
- { 1284, 6, 1, 0, "MOV64ms", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(140<<24), NULL, NULL, NULL, OperandInfo145 }, // Inst #1284 = MOV64ms
- { 1285, 1, 0, 0, "MOV64o64a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1285 = MOV64o64a
- { 1286, 1, 0, 0, "MOV64o8a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(1<<13)|(160<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1286 = MOV64o8a
- { 1287, 2, 1, 0, "MOV64rc", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(32<<24), NULL, NULL, NULL, OperandInfo155 }, // Inst #1287 = MOV64rc
- { 1288, 2, 1, 0, "MOV64rd", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(33<<24), NULL, NULL, NULL, OperandInfo156 }, // Inst #1288 = MOV64rd
- { 1289, 2, 1, 0, "MOV64ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<12)|(4<<13)|(184<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1289 = MOV64ri
- { 1290, 2, 1, 0, "MOV64ri32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|16|(1<<12)|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1290 = MOV64ri32
- { 1291, 2, 1, 0, "MOV64ri64i32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(3<<13)|(184<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1291 = MOV64ri64i32
- { 1292, 6, 1, 0, "MOV64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<12)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1292 = MOV64rm
- { 1293, 2, 1, 0, "MOV64rr", 0, 0|3|(1<<12)|(137<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1293 = MOV64rr
- { 1294, 2, 1, 0, "MOV64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(139<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1294 = MOV64rr_REV
- { 1295, 2, 1, 0, "MOV64rs", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<12)|(140<<24), NULL, NULL, NULL, OperandInfo157 }, // Inst #1295 = MOV64rs
- { 1296, 6, 1, 0, "MOV64sm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<12)|(142<<24), NULL, NULL, NULL, OperandInfo147 }, // Inst #1296 = MOV64sm
- { 1297, 2, 1, 0, "MOV64sr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(142<<24), NULL, NULL, NULL, OperandInfo158 }, // Inst #1297 = MOV64sr
- { 1298, 2, 1, 0, "MOV64toPQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo159 }, // Inst #1298 = MOV64toPQIrr
- { 1299, 6, 1, 0, "MOV64toSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #1299 = MOV64toSDrm
- { 1300, 2, 1, 0, "MOV64toSDrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo83 }, // Inst #1300 = MOV64toSDrr
- { 1301, 1, 1, 0, "MOV8ao8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(162<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1301 = MOV8ao8
- { 1302, 6, 0, 0, "MOV8mi", 0|(1<<TID::MayStore), 0|24|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1302 = MOV8mi
- { 1303, 6, 0, 0, "MOV8mr", 0|(1<<TID::MayStore), 0|4|(136<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #1303 = MOV8mr
- { 1304, 6, 0, 0, "MOV8mr_NOREX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(136<<24), NULL, NULL, NULL, OperandInfo160 }, // Inst #1304 = MOV8mr_NOREX
- { 1305, 1, 0, 0, "MOV8o8a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(160<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1305 = MOV8o8a
- { 1306, 1, 1, 0, "MOV8r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo94 }, // Inst #1306 = MOV8r0
- { 1307, 2, 1, 0, "MOV8ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<13)|(176<<24), NULL, NULL, NULL, OperandInfo68 }, // Inst #1307 = MOV8ri
- { 1308, 6, 1, 0, "MOV8rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(138<<24), NULL, NULL, NULL, OperandInfo69 }, // Inst #1308 = MOV8rm
- { 1309, 6, 1, 0, "MOV8rm_NOREX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|6|(138<<24), NULL, NULL, NULL, OperandInfo161 }, // Inst #1309 = MOV8rm_NOREX
- { 1310, 2, 1, 0, "MOV8rr", 0, 0|3|(136<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #1310 = MOV8rr
- { 1311, 2, 1, 0, "MOV8rr_NOREX", 0, 0|3|(136<<24), NULL, NULL, NULL, OperandInfo162 }, // Inst #1311 = MOV8rr_NOREX
- { 1312, 2, 1, 0, "MOV8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(138<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #1312 = MOV8rr_REV
- { 1313, 6, 0, 0, "MOVAPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(41<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1313 = MOVAPDmr
- { 1314, 6, 1, 0, "MOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1314 = MOVAPDrm
- { 1315, 2, 1, 0, "MOVAPDrr", 0, 0|5|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1315 = MOVAPDrr
- { 1316, 6, 0, 0, "MOVAPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(41<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1316 = MOVAPSmr
- { 1317, 6, 1, 0, "MOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1317 = MOVAPSrm
- { 1318, 2, 1, 0, "MOVAPSrr", 0, 0|5|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1318 = MOVAPSrr
- { 1319, 6, 1, 0, "MOVDDUPrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1319 = MOVDDUPrm
- { 1320, 2, 1, 0, "MOVDDUPrr", 0, 0|5|(11<<8)|(18<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1320 = MOVDDUPrr
- { 1321, 6, 1, 0, "MOVDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1321 = MOVDI2PDIrm
- { 1322, 2, 1, 0, "MOVDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1322 = MOVDI2PDIrr
- { 1323, 6, 1, 0, "MOVDI2SSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1323 = MOVDI2SSrm
- { 1324, 2, 1, 0, "MOVDI2SSrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo86 }, // Inst #1324 = MOVDI2SSrr
- { 1325, 6, 0, 0, "MOVDQAmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1325 = MOVDQAmr
- { 1326, 6, 1, 0, "MOVDQArm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1326 = MOVDQArm
- { 1327, 2, 1, 0, "MOVDQArr", 0, 0|5|(1<<6)|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1327 = MOVDQArr
- { 1328, 6, 0, 0, "MOVDQUmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(12<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1328 = MOVDQUmr
- { 1329, 6, 0, 0, "MOVDQUmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(12<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1329 = MOVDQUmr_Int
- { 1330, 6, 1, 0, "MOVDQUrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1330 = MOVDQUrm
- { 1331, 6, 1, 0, "MOVDQUrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(12<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1331 = MOVDQUrm_Int
- { 1332, 3, 1, 0, "MOVHLPSrr", 0, 0|5|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1332 = MOVHLPSrr
- { 1333, 6, 0, 0, "MOVHPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(23<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1333 = MOVHPDmr
- { 1334, 7, 1, 0, "MOVHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1334 = MOVHPDrm
- { 1335, 6, 0, 0, "MOVHPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(23<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1335 = MOVHPSmr
- { 1336, 7, 1, 0, "MOVHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1336 = MOVHPSrm
- { 1337, 3, 1, 0, "MOVLHPSrr", 0, 0|5|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1337 = MOVLHPSrr
- { 1338, 6, 0, 0, "MOVLPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1338 = MOVLPDmr
- { 1339, 7, 1, 0, "MOVLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1339 = MOVLPDrm
- { 1340, 3, 1, 0, "MOVLPDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1340 = MOVLPDrr
- { 1341, 6, 0, 0, "MOVLPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1341 = MOVLPSmr
- { 1342, 7, 1, 0, "MOVLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1342 = MOVLPSrm
- { 1343, 3, 1, 0, "MOVLPSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1343 = MOVLPSrr
- { 1344, 6, 0, 0, "MOVLQ128mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1344 = MOVLQ128mr
- { 1345, 3, 1, 0, "MOVLSD2PDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo165 }, // Inst #1345 = MOVLSD2PDrr
- { 1346, 3, 1, 0, "MOVLSS2PSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo166 }, // Inst #1346 = MOVLSS2PSrr
- { 1347, 2, 1, 0, "MOVMSKPDrr", 0, 0|5|(1<<6)|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1347 = MOVMSKPDrr
- { 1348, 2, 1, 0, "MOVMSKPSrr", 0, 0|5|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1348 = MOVMSKPSrr
- { 1349, 6, 1, 0, "MOVNTDQArm", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1349 = MOVNTDQArm
- { 1350, 6, 0, 0, "MOVNTDQmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1350 = MOVNTDQmr
- { 1351, 6, 0, 0, "MOVNTImr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(195<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1351 = MOVNTImr
- { 1352, 6, 0, 0, "MOVNTPDmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1352 = MOVNTPDmr
- { 1353, 6, 0, 0, "MOVNTPSmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1353 = MOVNTPSmr
- { 1354, 2, 1, 0, "MOVPC32r", 0|(1<<TID::NotDuplicable), 0|(3<<13)|(232<<24), ImplicitList2, NULL, NULL, OperandInfo55 }, // Inst #1354 = MOVPC32r
- { 1355, 6, 0, 0, "MOVPD2SDmr", 0|(1<<TID::MayStore), 0|4|(11<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1355 = MOVPD2SDmr
- { 1356, 2, 1, 0, "MOVPD2SDrr", 0|(1<<TID::CheapAsAMove), 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo167 }, // Inst #1356 = MOVPD2SDrr
- { 1357, 6, 0, 0, "MOVPDI2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1357 = MOVPDI2DImr
- { 1358, 2, 1, 0, "MOVPDI2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1358 = MOVPDI2DIrr
- { 1359, 6, 0, 0, "MOVPQI2QImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1359 = MOVPQI2QImr
- { 1360, 2, 1, 0, "MOVPQIto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #1360 = MOVPQIto64rr
- { 1361, 6, 0, 0, "MOVPS2SSmr", 0|(1<<TID::MayStore), 0|4|(12<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1361 = MOVPS2SSmr
- { 1362, 2, 1, 0, "MOVPS2SSrr", 0|(1<<TID::CheapAsAMove), 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo168 }, // Inst #1362 = MOVPS2SSrr
- { 1363, 6, 1, 0, "MOVQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1363 = MOVQI2PQIrm
- { 1364, 2, 1, 0, "MOVQxrxr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1364 = MOVQxrxr
- { 1365, 6, 1, 0, "MOVSD2PDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1365 = MOVSD2PDrm
- { 1366, 2, 1, 0, "MOVSD2PDrr", 0|(1<<TID::CheapAsAMove), 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1366 = MOVSD2PDrr
- { 1367, 6, 0, 0, "MOVSDmr", 0|(1<<TID::MayStore), 0|4|(11<<8)|(17<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1367 = MOVSDmr
- { 1368, 6, 1, 0, "MOVSDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #1368 = MOVSDrm
- { 1369, 2, 1, 0, "MOVSDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #1369 = MOVSDrr
- { 1370, 6, 0, 0, "MOVSDto64mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1370 = MOVSDto64mr
- { 1371, 2, 1, 0, "MOVSDto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #1371 = MOVSDto64rr
- { 1372, 6, 1, 0, "MOVSHDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1372 = MOVSHDUPrm
- { 1373, 2, 1, 0, "MOVSHDUPrr", 0, 0|5|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1373 = MOVSHDUPrr
- { 1374, 6, 1, 0, "MOVSLDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1374 = MOVSLDUPrm
- { 1375, 2, 1, 0, "MOVSLDUPrr", 0, 0|5|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1375 = MOVSLDUPrr
- { 1376, 6, 0, 0, "MOVSS2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo171 }, // Inst #1376 = MOVSS2DImr
- { 1377, 2, 1, 0, "MOVSS2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #1377 = MOVSS2DIrr
- { 1378, 6, 1, 0, "MOVSS2PSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1378 = MOVSS2PSrm
- { 1379, 2, 1, 0, "MOVSS2PSrr", 0|(1<<TID::CheapAsAMove), 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo172 }, // Inst #1379 = MOVSS2PSrr
- { 1380, 6, 0, 0, "MOVSSmr", 0|(1<<TID::MayStore), 0|4|(12<<8)|(17<<24), NULL, NULL, NULL, OperandInfo171 }, // Inst #1380 = MOVSSmr
- { 1381, 6, 1, 0, "MOVSSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1381 = MOVSSrm
- { 1382, 2, 1, 0, "MOVSSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #1382 = MOVSSrr
- { 1383, 6, 1, 0, "MOVSX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1383 = MOVSX16rm8
- { 1384, 6, 1, 0, "MOVSX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1384 = MOVSX16rm8W
- { 1385, 2, 1, 0, "MOVSX16rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1385 = MOVSX16rr8
- { 1386, 2, 1, 0, "MOVSX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1386 = MOVSX16rr8W
- { 1387, 6, 1, 0, "MOVSX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1387 = MOVSX32rm16
- { 1388, 6, 1, 0, "MOVSX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1388 = MOVSX32rm8
- { 1389, 2, 1, 0, "MOVSX32rr16", 0, 0|5|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo174 }, // Inst #1389 = MOVSX32rr16
- { 1390, 2, 1, 0, "MOVSX32rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo175 }, // Inst #1390 = MOVSX32rr8
- { 1391, 6, 1, 0, "MOVSX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1391 = MOVSX64rm16
- { 1392, 6, 1, 0, "MOVSX64rm32", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1392 = MOVSX64rm32
- { 1393, 6, 1, 0, "MOVSX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1393 = MOVSX64rm8
- { 1394, 2, 1, 0, "MOVSX64rr16", 0, 0|5|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo176 }, // Inst #1394 = MOVSX64rr16
- { 1395, 2, 1, 0, "MOVSX64rr32", 0, 0|5|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #1395 = MOVSX64rr32
- { 1396, 2, 1, 0, "MOVSX64rr8", 0, 0|5|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo177 }, // Inst #1396 = MOVSX64rr8
- { 1397, 6, 0, 0, "MOVUPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1397 = MOVUPDmr
- { 1398, 6, 0, 0, "MOVUPDmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1398 = MOVUPDmr_Int
- { 1399, 6, 1, 0, "MOVUPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1399 = MOVUPDrm
- { 1400, 6, 1, 0, "MOVUPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1400 = MOVUPDrm_Int
- { 1401, 2, 1, 0, "MOVUPDrr", 0, 0|5|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1401 = MOVUPDrr
- { 1402, 6, 0, 0, "MOVUPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1402 = MOVUPSmr
- { 1403, 6, 0, 0, "MOVUPSmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1403 = MOVUPSmr_Int
- { 1404, 6, 1, 0, "MOVUPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1404 = MOVUPSrm
- { 1405, 6, 1, 0, "MOVUPSrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1405 = MOVUPSrm_Int
- { 1406, 2, 1, 0, "MOVUPSrr", 0, 0|5|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1406 = MOVUPSrr
- { 1407, 6, 1, 0, "MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1407 = MOVZDI2PDIrm
- { 1408, 2, 1, 0, "MOVZDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1408 = MOVZDI2PDIrr
- { 1409, 6, 1, 0, "MOVZPQILo2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1409 = MOVZPQILo2PQIrm
- { 1410, 2, 1, 0, "MOVZPQILo2PQIrr", 0, 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1410 = MOVZPQILo2PQIrr
- { 1411, 6, 1, 0, "MOVZQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1411 = MOVZQI2PQIrm
- { 1412, 2, 1, 0, "MOVZQI2PQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo159 }, // Inst #1412 = MOVZQI2PQIrr
- { 1413, 6, 1, 0, "MOVZSD2PDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1413 = MOVZSD2PDrm
- { 1414, 6, 1, 0, "MOVZSS2PSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1414 = MOVZSS2PSrm
- { 1415, 6, 1, 0, "MOVZX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1415 = MOVZX16rm8
- { 1416, 6, 1, 0, "MOVZX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1416 = MOVZX16rm8W
- { 1417, 2, 1, 0, "MOVZX16rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1417 = MOVZX16rr8
- { 1418, 2, 1, 0, "MOVZX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1418 = MOVZX16rr8W
- { 1419, 6, 1, 0, "MOVZX32_NOREXrm8", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo178 }, // Inst #1419 = MOVZX32_NOREXrm8
- { 1420, 2, 1, 0, "MOVZX32_NOREXrr8", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo179 }, // Inst #1420 = MOVZX32_NOREXrr8
- { 1421, 6, 1, 0, "MOVZX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1421 = MOVZX32rm16
- { 1422, 6, 1, 0, "MOVZX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1422 = MOVZX32rm8
- { 1423, 2, 1, 0, "MOVZX32rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo174 }, // Inst #1423 = MOVZX32rr16
- { 1424, 2, 1, 0, "MOVZX32rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo175 }, // Inst #1424 = MOVZX32rr8
- { 1425, 6, 1, 0, "MOVZX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1425 = MOVZX64rm16
- { 1426, 6, 1, 0, "MOVZX64rm16_Q", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(183<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1426 = MOVZX64rm16_Q
- { 1427, 6, 1, 0, "MOVZX64rm32", 0|(1<<TID::MayLoad), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1427 = MOVZX64rm32
- { 1428, 6, 1, 0, "MOVZX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1428 = MOVZX64rm8
- { 1429, 6, 1, 0, "MOVZX64rm8_Q", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(182<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1429 = MOVZX64rm8_Q
- { 1430, 2, 1, 0, "MOVZX64rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo176 }, // Inst #1430 = MOVZX64rr16
- { 1431, 2, 1, 0, "MOVZX64rr16_Q", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(183<<24), NULL, NULL, NULL, OperandInfo176 }, // Inst #1431 = MOVZX64rr16_Q
- { 1432, 2, 1, 0, "MOVZX64rr32", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #1432 = MOVZX64rr32
- { 1433, 2, 1, 0, "MOVZX64rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo177 }, // Inst #1433 = MOVZX64rr8
- { 1434, 2, 1, 0, "MOVZX64rr8_Q", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(182<<24), NULL, NULL, NULL, OperandInfo177 }, // Inst #1434 = MOVZX64rr8_Q
- { 1435, 2, 1, 0, "MOV_Fp3232", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #1435 = MOV_Fp3232
- { 1436, 2, 1, 0, "MOV_Fp3264", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo180 }, // Inst #1436 = MOV_Fp3264
- { 1437, 2, 1, 0, "MOV_Fp3280", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo181 }, // Inst #1437 = MOV_Fp3280
- { 1438, 2, 1, 0, "MOV_Fp6432", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo182 }, // Inst #1438 = MOV_Fp6432
- { 1439, 2, 1, 0, "MOV_Fp6464", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #1439 = MOV_Fp6464
- { 1440, 2, 1, 0, "MOV_Fp6480", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo183 }, // Inst #1440 = MOV_Fp6480
- { 1441, 2, 1, 0, "MOV_Fp8032", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo184 }, // Inst #1441 = MOV_Fp8032
- { 1442, 2, 1, 0, "MOV_Fp8064", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo185 }, // Inst #1442 = MOV_Fp8064
- { 1443, 2, 1, 0, "MOV_Fp8080", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #1443 = MOV_Fp8080
- { 1444, 8, 1, 0, "MPSADBWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1444 = MPSADBWrmi
- { 1445, 4, 1, 0, "MPSADBWrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1445 = MPSADBWrri
- { 1446, 5, 0, 0, "MUL16m", 0|(1<<TID::MayLoad), 0|28|(1<<6)|(247<<24), ImplicitList12, ImplicitList18, Barriers1, OperandInfo30 }, // Inst #1446 = MUL16m
- { 1447, 1, 0, 0, "MUL16r", 0, 0|20|(1<<6)|(247<<24), ImplicitList12, ImplicitList18, Barriers1, OperandInfo93 }, // Inst #1447 = MUL16r
- { 1448, 5, 0, 0, "MUL32m", 0|(1<<TID::MayLoad), 0|28|(247<<24), ImplicitList13, ImplicitList19, Barriers6, OperandInfo30 }, // Inst #1448 = MUL32m
- { 1449, 1, 0, 0, "MUL32r", 0, 0|20|(247<<24), ImplicitList13, ImplicitList19, Barriers6, OperandInfo57 }, // Inst #1449 = MUL32r
- { 1450, 5, 0, 0, "MUL64m", 0|(1<<TID::MayLoad), 0|28|(1<<12)|(247<<24), ImplicitList15, ImplicitList20, Barriers1, OperandInfo30 }, // Inst #1450 = MUL64m
- { 1451, 1, 0, 0, "MUL64r", 0, 0|20|(1<<12)|(247<<24), ImplicitList15, ImplicitList20, Barriers1, OperandInfo58 }, // Inst #1451 = MUL64r
- { 1452, 5, 0, 0, "MUL8m", 0|(1<<TID::MayLoad), 0|28|(246<<24), ImplicitList11, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #1452 = MUL8m
- { 1453, 1, 0, 0, "MUL8r", 0, 0|20|(246<<24), ImplicitList11, ImplicitList21, Barriers1, OperandInfo94 }, // Inst #1453 = MUL8r
- { 1454, 7, 1, 0, "MULPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1454 = MULPDrm
- { 1455, 3, 1, 0, "MULPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1455 = MULPDrr
- { 1456, 7, 1, 0, "MULPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1456 = MULPSrm
- { 1457, 3, 1, 0, "MULPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1457 = MULPSrr
- { 1458, 7, 1, 0, "MULSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1458 = MULSDrm
- { 1459, 7, 1, 0, "MULSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1459 = MULSDrm_Int
- { 1460, 3, 1, 0, "MULSDrr", 0|(1<<TID::Commutable), 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1460 = MULSDrr
- { 1461, 3, 1, 0, "MULSDrr_Int", 0, 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1461 = MULSDrr_Int
- { 1462, 7, 1, 0, "MULSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1462 = MULSSrm
- { 1463, 7, 1, 0, "MULSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1463 = MULSSrm_Int
- { 1464, 3, 1, 0, "MULSSrr", 0|(1<<TID::Commutable), 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1464 = MULSSrr
- { 1465, 3, 1, 0, "MULSSrr_Int", 0, 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1465 = MULSSrr_Int
- { 1466, 5, 0, 0, "MUL_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1466 = MUL_F32m
- { 1467, 5, 0, 0, "MUL_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1467 = MUL_F64m
- { 1468, 5, 0, 0, "MUL_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1468 = MUL_FI16m
- { 1469, 5, 0, 0, "MUL_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1469 = MUL_FI32m
- { 1470, 1, 0, 0, "MUL_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1470 = MUL_FPrST0
- { 1471, 1, 0, 0, "MUL_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1471 = MUL_FST0r
- { 1472, 3, 1, 0, "MUL_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #1472 = MUL_Fp32
- { 1473, 7, 1, 0, "MUL_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1473 = MUL_Fp32m
- { 1474, 3, 1, 0, "MUL_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #1474 = MUL_Fp64
- { 1475, 7, 1, 0, "MUL_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1475 = MUL_Fp64m
- { 1476, 7, 1, 0, "MUL_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1476 = MUL_Fp64m32
- { 1477, 3, 1, 0, "MUL_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #1477 = MUL_Fp80
- { 1478, 7, 1, 0, "MUL_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1478 = MUL_Fp80m32
- { 1479, 7, 1, 0, "MUL_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1479 = MUL_Fp80m64
- { 1480, 7, 1, 0, "MUL_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1480 = MUL_FpI16m32
- { 1481, 7, 1, 0, "MUL_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1481 = MUL_FpI16m64
- { 1482, 7, 1, 0, "MUL_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1482 = MUL_FpI16m80
- { 1483, 7, 1, 0, "MUL_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1483 = MUL_FpI32m32
- { 1484, 7, 1, 0, "MUL_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1484 = MUL_FpI32m64
- { 1485, 7, 1, 0, "MUL_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1485 = MUL_FpI32m80
- { 1486, 1, 0, 0, "MUL_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1486 = MUL_FrST0
- { 1487, 0, 0, 0, "MWAIT", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1487 = MWAIT
- { 1488, 5, 0, 0, "NEG16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1488 = NEG16m
- { 1489, 2, 1, 0, "NEG16r", 0, 0|19|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1489 = NEG16r
- { 1490, 5, 0, 0, "NEG32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1490 = NEG32m
- { 1491, 2, 1, 0, "NEG32r", 0, 0|19|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1491 = NEG32r
- { 1492, 5, 0, 0, "NEG64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1492 = NEG64m
- { 1493, 2, 1, 0, "NEG64r", 0, 0|19|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1493 = NEG64r
- { 1494, 5, 0, 0, "NEG8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1494 = NEG8m
- { 1495, 2, 1, 0, "NEG8r", 0, 0|19|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1495 = NEG8r
- { 1496, 0, 0, 0, "NOOP", 0, 0|1|(144<<24), NULL, NULL, NULL, 0 }, // Inst #1496 = NOOP
- { 1497, 5, 0, 0, "NOOPL", 0, 0|24|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1497 = NOOPL
- { 1498, 5, 0, 0, "NOOPW", 0, 0|24|(1<<6)|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1498 = NOOPW
- { 1499, 5, 0, 0, "NOT16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1499 = NOT16m
- { 1500, 2, 1, 0, "NOT16r", 0, 0|18|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo91 }, // Inst #1500 = NOT16r
- { 1501, 5, 0, 0, "NOT32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1501 = NOT32m
- { 1502, 2, 1, 0, "NOT32r", 0, 0|18|(247<<24), NULL, NULL, NULL, OperandInfo52 }, // Inst #1502 = NOT32r
- { 1503, 5, 0, 0, "NOT64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1503 = NOT64m
- { 1504, 2, 1, 0, "NOT64r", 0, 0|18|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo53 }, // Inst #1504 = NOT64r
- { 1505, 5, 0, 0, "NOT8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(246<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1505 = NOT8m
- { 1506, 2, 1, 0, "NOT8r", 0, 0|18|(246<<24), NULL, NULL, NULL, OperandInfo92 }, // Inst #1506 = NOT8r
- { 1507, 1, 0, 0, "OR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1507 = OR16i16
- { 1508, 6, 0, 0, "OR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1508 = OR16mi
- { 1509, 6, 0, 0, "OR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1509 = OR16mi8
- { 1510, 6, 0, 0, "OR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1510 = OR16mr
- { 1511, 3, 1, 0, "OR16ri", 0, 0|17|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1511 = OR16ri
- { 1512, 3, 1, 0, "OR16ri8", 0, 0|17|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1512 = OR16ri8
- { 1513, 7, 1, 0, "OR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1513 = OR16rm
- { 1514, 3, 1, 0, "OR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1514 = OR16rr
- { 1515, 3, 1, 0, "OR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1515 = OR16rr_REV
- { 1516, 1, 0, 0, "OR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1516 = OR32i32
- { 1517, 6, 0, 0, "OR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1517 = OR32mi
- { 1518, 6, 0, 0, "OR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1518 = OR32mi8
- { 1519, 6, 0, 0, "OR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1519 = OR32mr
- { 1520, 3, 1, 0, "OR32ri", 0, 0|17|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1520 = OR32ri
- { 1521, 3, 1, 0, "OR32ri8", 0, 0|17|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1521 = OR32ri8
- { 1522, 7, 1, 0, "OR32rm", 0|(1<<TID::MayLoad), 0|6|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #1522 = OR32rm
- { 1523, 3, 1, 0, "OR32rr", 0|(1<<TID::Commutable), 0|3|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1523 = OR32rr
- { 1524, 3, 1, 0, "OR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1524 = OR32rr_REV
- { 1525, 1, 0, 0, "OR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1525 = OR64i32
- { 1526, 6, 0, 0, "OR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1526 = OR64mi32
- { 1527, 6, 0, 0, "OR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1527 = OR64mi8
- { 1528, 6, 0, 0, "OR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1528 = OR64mr
- { 1529, 3, 1, 0, "OR64ri32", 0, 0|17|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1529 = OR64ri32
- { 1530, 3, 1, 0, "OR64ri8", 0, 0|17|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1530 = OR64ri8
- { 1531, 7, 1, 0, "OR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #1531 = OR64rm
- { 1532, 3, 1, 0, "OR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1532 = OR64rr
- { 1533, 3, 1, 0, "OR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1533 = OR64rr_REV
- { 1534, 1, 0, 0, "OR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(12<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1534 = OR8i8
- { 1535, 6, 0, 0, "OR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1535 = OR8mi
- { 1536, 6, 0, 0, "OR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1536 = OR8mr
- { 1537, 3, 1, 0, "OR8ri", 0, 0|17|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1537 = OR8ri
- { 1538, 7, 1, 0, "OR8rm", 0|(1<<TID::MayLoad), 0|6|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1538 = OR8rm
- { 1539, 3, 1, 0, "OR8rr", 0|(1<<TID::Commutable), 0|3|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1539 = OR8rr
- { 1540, 3, 1, 0, "OR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1540 = OR8rr_REV
- { 1541, 7, 1, 0, "ORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1541 = ORPDrm
- { 1542, 3, 1, 0, "ORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1542 = ORPDrr
- { 1543, 7, 1, 0, "ORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1543 = ORPSrm
- { 1544, 3, 1, 0, "ORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1544 = ORPSrr
- { 1545, 1, 0, 0, "OUT16ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<13)|(231<<24), ImplicitList12, NULL, NULL, OperandInfo5 }, // Inst #1545 = OUT16ir
- { 1546, 0, 0, 0, "OUT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(239<<24), ImplicitList35, NULL, NULL, 0 }, // Inst #1546 = OUT16rr
- { 1547, 1, 0, 0, "OUT32ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(231<<24), ImplicitList13, NULL, NULL, OperandInfo5 }, // Inst #1547 = OUT32ir
- { 1548, 0, 0, 0, "OUT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(239<<24), ImplicitList36, NULL, NULL, 0 }, // Inst #1548 = OUT32rr
- { 1549, 1, 0, 0, "OUT8ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(230<<24), ImplicitList11, NULL, NULL, OperandInfo5 }, // Inst #1549 = OUT8ir
- { 1550, 0, 0, 0, "OUT8rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(238<<24), ImplicitList37, NULL, NULL, 0 }, // Inst #1550 = OUT8rr
- { 1551, 0, 0, 0, "OUTSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(110<<24), NULL, NULL, NULL, 0 }, // Inst #1551 = OUTSB
- { 1552, 0, 0, 0, "OUTSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(111<<24), NULL, NULL, NULL, 0 }, // Inst #1552 = OUTSD
- { 1553, 0, 0, 0, "OUTSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(111<<24), NULL, NULL, NULL, 0 }, // Inst #1553 = OUTSW
- { 1554, 6, 1, 0, "PABSBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1554 = PABSBrm128
- { 1555, 6, 1, 0, "PABSBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1555 = PABSBrm64
- { 1556, 2, 1, 0, "PABSBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1556 = PABSBrr128
- { 1557, 2, 1, 0, "PABSBrr64", 0, 0|5|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1557 = PABSBrr64
- { 1558, 6, 1, 0, "PABSDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1558 = PABSDrm128
- { 1559, 6, 1, 0, "PABSDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1559 = PABSDrm64
- { 1560, 2, 1, 0, "PABSDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1560 = PABSDrr128
- { 1561, 2, 1, 0, "PABSDrr64", 0, 0|5|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1561 = PABSDrr64
- { 1562, 6, 1, 0, "PABSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1562 = PABSWrm128
- { 1563, 6, 1, 0, "PABSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1563 = PABSWrm64
- { 1564, 2, 1, 0, "PABSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1564 = PABSWrr128
- { 1565, 2, 1, 0, "PABSWrr64", 0, 0|5|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1565 = PABSWrr64
- { 1566, 7, 1, 0, "PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1566 = PACKSSDWrm
- { 1567, 3, 1, 0, "PACKSSDWrr", 0, 0|5|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1567 = PACKSSDWrr
- { 1568, 7, 1, 0, "PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1568 = PACKSSWBrm
- { 1569, 3, 1, 0, "PACKSSWBrr", 0, 0|5|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1569 = PACKSSWBrr
- { 1570, 7, 1, 0, "PACKUSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1570 = PACKUSDWrm
- { 1571, 3, 1, 0, "PACKUSDWrr", 0, 0|5|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1571 = PACKUSDWrr
- { 1572, 7, 1, 0, "PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1572 = PACKUSWBrm
- { 1573, 3, 1, 0, "PACKUSWBrr", 0, 0|5|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1573 = PACKUSWBrr
- { 1574, 7, 1, 0, "PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1574 = PADDBrm
- { 1575, 3, 1, 0, "PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1575 = PADDBrr
- { 1576, 7, 1, 0, "PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1576 = PADDDrm
- { 1577, 3, 1, 0, "PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1577 = PADDDrr
- { 1578, 7, 1, 0, "PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1578 = PADDQrm
- { 1579, 3, 1, 0, "PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1579 = PADDQrr
- { 1580, 7, 1, 0, "PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1580 = PADDSBrm
- { 1581, 3, 1, 0, "PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1581 = PADDSBrr
- { 1582, 7, 1, 0, "PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1582 = PADDSWrm
- { 1583, 3, 1, 0, "PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1583 = PADDSWrr
- { 1584, 7, 1, 0, "PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1584 = PADDUSBrm
- { 1585, 3, 1, 0, "PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1585 = PADDUSBrr
- { 1586, 7, 1, 0, "PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1586 = PADDUSWrm
- { 1587, 3, 1, 0, "PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1587 = PADDUSWrr
- { 1588, 7, 1, 0, "PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1588 = PADDWrm
- { 1589, 3, 1, 0, "PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1589 = PADDWrr
- { 1590, 8, 1, 0, "PALIGNR128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1590 = PALIGNR128rm
- { 1591, 4, 1, 0, "PALIGNR128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1591 = PALIGNR128rr
- { 1592, 8, 1, 0, "PALIGNR64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo139 }, // Inst #1592 = PALIGNR64rm
- { 1593, 4, 1, 0, "PALIGNR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo186 }, // Inst #1593 = PALIGNR64rr
- { 1594, 7, 1, 0, "PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1594 = PANDNrm
- { 1595, 3, 1, 0, "PANDNrr", 0, 0|5|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1595 = PANDNrr
- { 1596, 7, 1, 0, "PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1596 = PANDrm
- { 1597, 3, 1, 0, "PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1597 = PANDrr
- { 1598, 7, 1, 0, "PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1598 = PAVGBrm
- { 1599, 3, 1, 0, "PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1599 = PAVGBrr
- { 1600, 7, 1, 0, "PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1600 = PAVGWrm
- { 1601, 3, 1, 0, "PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1601 = PAVGWrr
- { 1602, 7, 1, 0, "PBLENDVBrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #1602 = PBLENDVBrm0
- { 1603, 3, 1, 0, "PBLENDVBrr0", 0, 0|5|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo25 }, // Inst #1603 = PBLENDVBrr0
- { 1604, 8, 1, 0, "PBLENDWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1604 = PBLENDWrmi
- { 1605, 4, 1, 0, "PBLENDWrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1605 = PBLENDWrri
- { 1606, 7, 1, 0, "PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1606 = PCMPEQBrm
- { 1607, 3, 1, 0, "PCMPEQBrr", 0, 0|5|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1607 = PCMPEQBrr
- { 1608, 7, 1, 0, "PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1608 = PCMPEQDrm
- { 1609, 3, 1, 0, "PCMPEQDrr", 0, 0|5|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1609 = PCMPEQDrr
- { 1610, 7, 1, 0, "PCMPEQQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1610 = PCMPEQQrm
- { 1611, 3, 1, 0, "PCMPEQQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1611 = PCMPEQQrr
- { 1612, 7, 1, 0, "PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1612 = PCMPEQWrm
- { 1613, 3, 1, 0, "PCMPEQWrr", 0, 0|5|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1613 = PCMPEQWrr
- { 1614, 7, 0, 0, "PCMPESTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1614 = PCMPESTRIArm
- { 1615, 3, 0, 0, "PCMPESTRIArr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1615 = PCMPESTRIArr
- { 1616, 7, 0, 0, "PCMPESTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1616 = PCMPESTRICrm
- { 1617, 3, 0, 0, "PCMPESTRICrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1617 = PCMPESTRICrr
- { 1618, 7, 0, 0, "PCMPESTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1618 = PCMPESTRIOrm
- { 1619, 3, 0, 0, "PCMPESTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1619 = PCMPESTRIOrr
- { 1620, 7, 0, 0, "PCMPESTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1620 = PCMPESTRISrm
- { 1621, 3, 0, 0, "PCMPESTRISrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1621 = PCMPESTRISrr
- { 1622, 7, 0, 0, "PCMPESTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1622 = PCMPESTRIZrm
- { 1623, 3, 0, 0, "PCMPESTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1623 = PCMPESTRIZrr
- { 1624, 7, 0, 0, "PCMPESTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1624 = PCMPESTRIrm
- { 1625, 3, 0, 0, "PCMPESTRIrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1625 = PCMPESTRIrr
- { 1626, 8, 1, 0, "PCMPESTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo189 }, // Inst #1626 = PCMPESTRM128MEM
- { 1627, 4, 1, 0, "PCMPESTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #1627 = PCMPESTRM128REG
- { 1628, 7, 0, 0, "PCMPESTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1628 = PCMPESTRM128rm
- { 1629, 3, 0, 0, "PCMPESTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1629 = PCMPESTRM128rr
- { 1630, 7, 1, 0, "PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1630 = PCMPGTBrm
- { 1631, 3, 1, 0, "PCMPGTBrr", 0, 0|5|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1631 = PCMPGTBrr
- { 1632, 7, 1, 0, "PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1632 = PCMPGTDrm
- { 1633, 3, 1, 0, "PCMPGTDrr", 0, 0|5|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1633 = PCMPGTDrr
- { 1634, 7, 1, 0, "PCMPGTQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1634 = PCMPGTQrm
- { 1635, 3, 1, 0, "PCMPGTQrr", 0, 0|5|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1635 = PCMPGTQrr
- { 1636, 7, 1, 0, "PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1636 = PCMPGTWrm
- { 1637, 3, 1, 0, "PCMPGTWrr", 0, 0|5|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1637 = PCMPGTWrr
- { 1638, 7, 0, 0, "PCMPISTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1638 = PCMPISTRIArm
- { 1639, 3, 0, 0, "PCMPISTRIArr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1639 = PCMPISTRIArr
- { 1640, 7, 0, 0, "PCMPISTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1640 = PCMPISTRICrm
- { 1641, 3, 0, 0, "PCMPISTRICrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1641 = PCMPISTRICrr
- { 1642, 7, 0, 0, "PCMPISTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1642 = PCMPISTRIOrm
- { 1643, 3, 0, 0, "PCMPISTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1643 = PCMPISTRIOrr
- { 1644, 7, 0, 0, "PCMPISTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1644 = PCMPISTRISrm
- { 1645, 3, 0, 0, "PCMPISTRISrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1645 = PCMPISTRISrr
- { 1646, 7, 0, 0, "PCMPISTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1646 = PCMPISTRIZrm
- { 1647, 3, 0, 0, "PCMPISTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1647 = PCMPISTRIZrr
- { 1648, 7, 0, 0, "PCMPISTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo187 }, // Inst #1648 = PCMPISTRIrm
- { 1649, 3, 0, 0, "PCMPISTRIrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList38, Barriers1, OperandInfo188 }, // Inst #1649 = PCMPISTRIrr
- { 1650, 8, 1, 0, "PCMPISTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo189 }, // Inst #1650 = PCMPISTRM128MEM
- { 1651, 4, 1, 0, "PCMPISTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #1651 = PCMPISTRM128REG
- { 1652, 7, 0, 0, "PCMPISTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1652 = PCMPISTRM128rm
- { 1653, 3, 0, 0, "PCMPISTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1653 = PCMPISTRM128rr
- { 1654, 7, 0, 0, "PEXTRBmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1654 = PEXTRBmr
- { 1655, 3, 1, 0, "PEXTRBrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1655 = PEXTRBrr
- { 1656, 7, 0, 0, "PEXTRDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1656 = PEXTRDmr
- { 1657, 3, 1, 0, "PEXTRDrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1657 = PEXTRDrr
- { 1658, 7, 0, 0, "PEXTRQmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1658 = PEXTRQmr
- { 1659, 3, 1, 0, "PEXTRQrr", 0, 0|3|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo190 }, // Inst #1659 = PEXTRQrr
- { 1660, 7, 0, 0, "PEXTRWmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(21<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1660 = PEXTRWmr
- { 1661, 3, 1, 0, "PEXTRWri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1661 = PEXTRWri
- { 1662, 7, 1, 0, "PHADDDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1662 = PHADDDrm128
- { 1663, 7, 1, 0, "PHADDDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1663 = PHADDDrm64
- { 1664, 3, 1, 0, "PHADDDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1664 = PHADDDrr128
- { 1665, 3, 1, 0, "PHADDDrr64", 0, 0|5|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1665 = PHADDDrr64
- { 1666, 7, 1, 0, "PHADDSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1666 = PHADDSWrm128
- { 1667, 7, 1, 0, "PHADDSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1667 = PHADDSWrm64
- { 1668, 3, 1, 0, "PHADDSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1668 = PHADDSWrr128
- { 1669, 3, 1, 0, "PHADDSWrr64", 0, 0|5|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1669 = PHADDSWrr64
- { 1670, 7, 1, 0, "PHADDWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1670 = PHADDWrm128
- { 1671, 7, 1, 0, "PHADDWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1671 = PHADDWrm64
- { 1672, 3, 1, 0, "PHADDWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1672 = PHADDWrr128
- { 1673, 3, 1, 0, "PHADDWrr64", 0, 0|5|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1673 = PHADDWrr64
- { 1674, 6, 1, 0, "PHMINPOSUWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1674 = PHMINPOSUWrm128
- { 1675, 2, 1, 0, "PHMINPOSUWrr128", 0, 0|5|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1675 = PHMINPOSUWrr128
- { 1676, 7, 1, 0, "PHSUBDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1676 = PHSUBDrm128
- { 1677, 7, 1, 0, "PHSUBDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1677 = PHSUBDrm64
- { 1678, 3, 1, 0, "PHSUBDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1678 = PHSUBDrr128
- { 1679, 3, 1, 0, "PHSUBDrr64", 0, 0|5|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1679 = PHSUBDrr64
- { 1680, 7, 1, 0, "PHSUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1680 = PHSUBSWrm128
- { 1681, 7, 1, 0, "PHSUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1681 = PHSUBSWrm64
- { 1682, 3, 1, 0, "PHSUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1682 = PHSUBSWrr128
- { 1683, 3, 1, 0, "PHSUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1683 = PHSUBSWrr64
- { 1684, 7, 1, 0, "PHSUBWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1684 = PHSUBWrm128
- { 1685, 7, 1, 0, "PHSUBWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1685 = PHSUBWrm64
- { 1686, 3, 1, 0, "PHSUBWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1686 = PHSUBWrr128
- { 1687, 3, 1, 0, "PHSUBWrr64", 0, 0|5|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1687 = PHSUBWrr64
- { 1688, 8, 1, 0, "PINSRBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1688 = PINSRBrm
- { 1689, 4, 1, 0, "PINSRBrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo191 }, // Inst #1689 = PINSRBrr
- { 1690, 8, 1, 0, "PINSRDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1690 = PINSRDrm
- { 1691, 4, 1, 0, "PINSRDrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo191 }, // Inst #1691 = PINSRDrr
- { 1692, 8, 1, 0, "PINSRQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1692 = PINSRQrm
- { 1693, 4, 1, 0, "PINSRQrr", 0, 0|5|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo192 }, // Inst #1693 = PINSRQrr
- { 1694, 8, 1, 0, "PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1694 = PINSRWrmi
- { 1695, 4, 1, 0, "PINSRWrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo191 }, // Inst #1695 = PINSRWrri
- { 1696, 7, 1, 0, "PMADDUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1696 = PMADDUBSWrm128
- { 1697, 7, 1, 0, "PMADDUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1697 = PMADDUBSWrm64
- { 1698, 3, 1, 0, "PMADDUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1698 = PMADDUBSWrr128
- { 1699, 3, 1, 0, "PMADDUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1699 = PMADDUBSWrr64
- { 1700, 7, 1, 0, "PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1700 = PMADDWDrm
- { 1701, 3, 1, 0, "PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1701 = PMADDWDrr
- { 1702, 7, 1, 0, "PMAXSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1702 = PMAXSBrm
- { 1703, 3, 1, 0, "PMAXSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1703 = PMAXSBrr
- { 1704, 7, 1, 0, "PMAXSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1704 = PMAXSDrm
- { 1705, 3, 1, 0, "PMAXSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1705 = PMAXSDrr
- { 1706, 7, 1, 0, "PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1706 = PMAXSWrm
- { 1707, 3, 1, 0, "PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1707 = PMAXSWrr
- { 1708, 7, 1, 0, "PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1708 = PMAXUBrm
- { 1709, 3, 1, 0, "PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1709 = PMAXUBrr
- { 1710, 7, 1, 0, "PMAXUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1710 = PMAXUDrm
- { 1711, 3, 1, 0, "PMAXUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1711 = PMAXUDrr
- { 1712, 7, 1, 0, "PMAXUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1712 = PMAXUWrm
- { 1713, 3, 1, 0, "PMAXUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1713 = PMAXUWrr
- { 1714, 7, 1, 0, "PMINSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1714 = PMINSBrm
- { 1715, 3, 1, 0, "PMINSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1715 = PMINSBrr
- { 1716, 7, 1, 0, "PMINSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1716 = PMINSDrm
- { 1717, 3, 1, 0, "PMINSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1717 = PMINSDrr
- { 1718, 7, 1, 0, "PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1718 = PMINSWrm
- { 1719, 3, 1, 0, "PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1719 = PMINSWrr
- { 1720, 7, 1, 0, "PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1720 = PMINUBrm
- { 1721, 3, 1, 0, "PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1721 = PMINUBrr
- { 1722, 7, 1, 0, "PMINUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1722 = PMINUDrm
- { 1723, 3, 1, 0, "PMINUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1723 = PMINUDrr
- { 1724, 7, 1, 0, "PMINUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1724 = PMINUWrm
- { 1725, 3, 1, 0, "PMINUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1725 = PMINUWrr
- { 1726, 2, 1, 0, "PMOVMSKBrr", 0, 0|5|(1<<6)|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1726 = PMOVMSKBrr
- { 1727, 6, 1, 0, "PMOVSXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1727 = PMOVSXBDrm
- { 1728, 2, 1, 0, "PMOVSXBDrr", 0, 0|5|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1728 = PMOVSXBDrr
- { 1729, 6, 1, 0, "PMOVSXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1729 = PMOVSXBQrm
- { 1730, 2, 1, 0, "PMOVSXBQrr", 0, 0|5|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1730 = PMOVSXBQrr
- { 1731, 6, 1, 0, "PMOVSXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1731 = PMOVSXBWrm
- { 1732, 2, 1, 0, "PMOVSXBWrr", 0, 0|5|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1732 = PMOVSXBWrr
- { 1733, 6, 1, 0, "PMOVSXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1733 = PMOVSXDQrm
- { 1734, 2, 1, 0, "PMOVSXDQrr", 0, 0|5|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1734 = PMOVSXDQrr
- { 1735, 6, 1, 0, "PMOVSXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1735 = PMOVSXWDrm
- { 1736, 2, 1, 0, "PMOVSXWDrr", 0, 0|5|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1736 = PMOVSXWDrr
- { 1737, 6, 1, 0, "PMOVSXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1737 = PMOVSXWQrm
- { 1738, 2, 1, 0, "PMOVSXWQrr", 0, 0|5|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1738 = PMOVSXWQrr
- { 1739, 6, 1, 0, "PMOVZXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1739 = PMOVZXBDrm
- { 1740, 2, 1, 0, "PMOVZXBDrr", 0, 0|5|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1740 = PMOVZXBDrr
- { 1741, 6, 1, 0, "PMOVZXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1741 = PMOVZXBQrm
- { 1742, 2, 1, 0, "PMOVZXBQrr", 0, 0|5|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1742 = PMOVZXBQrr
- { 1743, 6, 1, 0, "PMOVZXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1743 = PMOVZXBWrm
- { 1744, 2, 1, 0, "PMOVZXBWrr", 0, 0|5|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1744 = PMOVZXBWrr
- { 1745, 6, 1, 0, "PMOVZXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1745 = PMOVZXDQrm
- { 1746, 2, 1, 0, "PMOVZXDQrr", 0, 0|5|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1746 = PMOVZXDQrr
- { 1747, 6, 1, 0, "PMOVZXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1747 = PMOVZXWDrm
- { 1748, 2, 1, 0, "PMOVZXWDrr", 0, 0|5|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1748 = PMOVZXWDrr
- { 1749, 6, 1, 0, "PMOVZXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1749 = PMOVZXWQrm
- { 1750, 2, 1, 0, "PMOVZXWQrr", 0, 0|5|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1750 = PMOVZXWQrr
- { 1751, 7, 1, 0, "PMULDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1751 = PMULDQrm
- { 1752, 3, 1, 0, "PMULDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1752 = PMULDQrr
- { 1753, 7, 1, 0, "PMULHRSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1753 = PMULHRSWrm128
- { 1754, 7, 1, 0, "PMULHRSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1754 = PMULHRSWrm64
- { 1755, 3, 1, 0, "PMULHRSWrr128", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1755 = PMULHRSWrr128
- { 1756, 3, 1, 0, "PMULHRSWrr64", 0|(1<<TID::Commutable), 0|5|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1756 = PMULHRSWrr64
- { 1757, 7, 1, 0, "PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1757 = PMULHUWrm
- { 1758, 3, 1, 0, "PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1758 = PMULHUWrr
- { 1759, 7, 1, 0, "PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1759 = PMULHWrm
- { 1760, 3, 1, 0, "PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1760 = PMULHWrr
- { 1761, 7, 1, 0, "PMULLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1761 = PMULLDrm
- { 1762, 7, 1, 0, "PMULLDrm_int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1762 = PMULLDrm_int
- { 1763, 3, 1, 0, "PMULLDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1763 = PMULLDrr
- { 1764, 3, 1, 0, "PMULLDrr_int", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1764 = PMULLDrr_int
- { 1765, 7, 1, 0, "PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1765 = PMULLWrm
- { 1766, 3, 1, 0, "PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1766 = PMULLWrr
- { 1767, 7, 1, 0, "PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1767 = PMULUDQrm
- { 1768, 3, 1, 0, "PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1768 = PMULUDQrr
- { 1769, 1, 1, 0, "POP16r", 0|(1<<TID::MayLoad), 0|2|(1<<6)|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1769 = POP16r
- { 1770, 5, 1, 0, "POP16rmm", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1770 = POP16rmm
- { 1771, 1, 1, 0, "POP16rmr", 0|(1<<TID::MayLoad), 0|16|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1771 = POP16rmr
- { 1772, 1, 1, 0, "POP32r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1772 = POP32r
- { 1773, 5, 1, 0, "POP32rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1773 = POP32rmm
- { 1774, 1, 1, 0, "POP32rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1774 = POP32rmr
- { 1775, 1, 1, 0, "POP64r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1775 = POP64r
- { 1776, 5, 1, 0, "POP64rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo30 }, // Inst #1776 = POP64rmm
- { 1777, 1, 1, 0, "POP64rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1777 = POP64rmr
- { 1778, 6, 1, 0, "POPCNT16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1778 = POPCNT16rm
- { 1779, 2, 1, 0, "POPCNT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1779 = POPCNT16rr
- { 1780, 6, 1, 0, "POPCNT32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1780 = POPCNT32rm
- { 1781, 2, 1, 0, "POPCNT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1781 = POPCNT32rr
- { 1782, 6, 1, 0, "POPCNT64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(1<<12)|(184<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1782 = POPCNT64rm
- { 1783, 2, 1, 0, "POPCNT64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(1<<12)|(184<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1783 = POPCNT64rr
- { 1784, 0, 0, 0, "POPF", 0|(1<<TID::MayLoad), 0|1|(1<<6)|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1784 = POPF
- { 1785, 0, 0, 0, "POPFD", 0|(1<<TID::MayLoad), 0|1|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1785 = POPFD
- { 1786, 0, 0, 0, "POPFQ", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(157<<24), ImplicitList4, ImplicitList5, Barriers1, 0 }, // Inst #1786 = POPFQ
- { 1787, 0, 0, 0, "POPFS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1787 = POPFS16
- { 1788, 0, 0, 0, "POPFS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1788 = POPFS32
- { 1789, 0, 0, 0, "POPFS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1789 = POPFS64
- { 1790, 0, 0, 0, "POPGS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1790 = POPGS16
- { 1791, 0, 0, 0, "POPGS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1791 = POPGS32
- { 1792, 0, 0, 0, "POPGS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1792 = POPGS64
- { 1793, 7, 1, 0, "PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1793 = PORrm
- { 1794, 3, 1, 0, "PORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1794 = PORrr
- { 1795, 5, 0, 0, "PREFETCHNTA", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1795 = PREFETCHNTA
- { 1796, 5, 0, 0, "PREFETCHT0", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1796 = PREFETCHT0
- { 1797, 5, 0, 0, "PREFETCHT1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1797 = PREFETCHT1
- { 1798, 5, 0, 0, "PREFETCHT2", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1798 = PREFETCHT2
- { 1799, 7, 1, 0, "PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1799 = PSADBWrm
- { 1800, 3, 1, 0, "PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1800 = PSADBWrr
- { 1801, 7, 1, 0, "PSHUFBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo24 }, // Inst #1801 = PSHUFBrm128
- { 1802, 7, 1, 0, "PSHUFBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo136 }, // Inst #1802 = PSHUFBrm64
- { 1803, 3, 1, 0, "PSHUFBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo25 }, // Inst #1803 = PSHUFBrr128
- { 1804, 3, 1, 0, "PSHUFBrr64", 0, 0|5|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo137 }, // Inst #1804 = PSHUFBrr64
- { 1805, 7, 1, 0, "PSHUFDmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1805 = PSHUFDmi
- { 1806, 3, 1, 0, "PSHUFDri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1806 = PSHUFDri
- { 1807, 7, 1, 0, "PSHUFHWmi", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1807 = PSHUFHWmi
- { 1808, 3, 1, 0, "PSHUFHWri", 0, 0|5|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1808 = PSHUFHWri
- { 1809, 7, 1, 0, "PSHUFLWmi", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1809 = PSHUFLWmi
- { 1810, 3, 1, 0, "PSHUFLWri", 0, 0|5|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1810 = PSHUFLWri
- { 1811, 7, 1, 0, "PSIGNBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1811 = PSIGNBrm128
- { 1812, 7, 1, 0, "PSIGNBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1812 = PSIGNBrm64
- { 1813, 3, 1, 0, "PSIGNBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1813 = PSIGNBrr128
- { 1814, 3, 1, 0, "PSIGNBrr64", 0, 0|5|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1814 = PSIGNBrr64
- { 1815, 7, 1, 0, "PSIGNDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1815 = PSIGNDrm128
- { 1816, 7, 1, 0, "PSIGNDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1816 = PSIGNDrm64
- { 1817, 3, 1, 0, "PSIGNDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1817 = PSIGNDrr128
- { 1818, 3, 1, 0, "PSIGNDrr64", 0, 0|5|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1818 = PSIGNDrr64
- { 1819, 7, 1, 0, "PSIGNWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1819 = PSIGNWrm128
- { 1820, 7, 1, 0, "PSIGNWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1820 = PSIGNWrm64
- { 1821, 3, 1, 0, "PSIGNWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1821 = PSIGNWrr128
- { 1822, 3, 1, 0, "PSIGNWrr64", 0, 0|5|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1822 = PSIGNWrr64
- { 1823, 3, 1, 0, "PSLLDQri", 0, 0|23|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1823 = PSLLDQri
- { 1824, 3, 1, 0, "PSLLDri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1824 = PSLLDri
- { 1825, 7, 1, 0, "PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1825 = PSLLDrm
- { 1826, 3, 1, 0, "PSLLDrr", 0, 0|5|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1826 = PSLLDrr
- { 1827, 3, 1, 0, "PSLLQri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1827 = PSLLQri
- { 1828, 7, 1, 0, "PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1828 = PSLLQrm
- { 1829, 3, 1, 0, "PSLLQrr", 0, 0|5|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1829 = PSLLQrr
- { 1830, 3, 1, 0, "PSLLWri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1830 = PSLLWri
- { 1831, 7, 1, 0, "PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1831 = PSLLWrm
- { 1832, 3, 1, 0, "PSLLWrr", 0, 0|5|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1832 = PSLLWrr
- { 1833, 3, 1, 0, "PSRADri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1833 = PSRADri
- { 1834, 7, 1, 0, "PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1834 = PSRADrm
- { 1835, 3, 1, 0, "PSRADrr", 0, 0|5|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1835 = PSRADrr
- { 1836, 3, 1, 0, "PSRAWri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1836 = PSRAWri
- { 1837, 7, 1, 0, "PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1837 = PSRAWrm
- { 1838, 3, 1, 0, "PSRAWrr", 0, 0|5|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1838 = PSRAWrr
- { 1839, 3, 1, 0, "PSRLDQri", 0, 0|19|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1839 = PSRLDQri
- { 1840, 3, 1, 0, "PSRLDri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1840 = PSRLDri
- { 1841, 7, 1, 0, "PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1841 = PSRLDrm
- { 1842, 3, 1, 0, "PSRLDrr", 0, 0|5|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1842 = PSRLDrr
- { 1843, 3, 1, 0, "PSRLQri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1843 = PSRLQri
- { 1844, 7, 1, 0, "PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1844 = PSRLQrm
- { 1845, 3, 1, 0, "PSRLQrr", 0, 0|5|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1845 = PSRLQrr
- { 1846, 3, 1, 0, "PSRLWri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1846 = PSRLWri
- { 1847, 7, 1, 0, "PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1847 = PSRLWrm
- { 1848, 3, 1, 0, "PSRLWrr", 0, 0|5|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1848 = PSRLWrr
- { 1849, 7, 1, 0, "PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1849 = PSUBBrm
- { 1850, 3, 1, 0, "PSUBBrr", 0, 0|5|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1850 = PSUBBrr
- { 1851, 7, 1, 0, "PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1851 = PSUBDrm
- { 1852, 3, 1, 0, "PSUBDrr", 0, 0|5|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1852 = PSUBDrr
- { 1853, 7, 1, 0, "PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1853 = PSUBQrm
- { 1854, 3, 1, 0, "PSUBQrr", 0, 0|5|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1854 = PSUBQrr
- { 1855, 7, 1, 0, "PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1855 = PSUBSBrm
- { 1856, 3, 1, 0, "PSUBSBrr", 0, 0|5|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1856 = PSUBSBrr
- { 1857, 7, 1, 0, "PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1857 = PSUBSWrm
- { 1858, 3, 1, 0, "PSUBSWrr", 0, 0|5|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1858 = PSUBSWrr
- { 1859, 7, 1, 0, "PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1859 = PSUBUSBrm
- { 1860, 3, 1, 0, "PSUBUSBrr", 0, 0|5|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1860 = PSUBUSBrr
- { 1861, 7, 1, 0, "PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1861 = PSUBUSWrm
- { 1862, 3, 1, 0, "PSUBUSWrr", 0, 0|5|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1862 = PSUBUSWrr
- { 1863, 7, 1, 0, "PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1863 = PSUBWrm
- { 1864, 3, 1, 0, "PSUBWrr", 0, 0|5|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1864 = PSUBWrr
- { 1865, 6, 0, 0, "PTESTrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #1865 = PTESTrm
- { 1866, 2, 0, 0, "PTESTrr", 0, 0|5|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #1866 = PTESTrr
- { 1867, 7, 1, 0, "PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1867 = PUNPCKHBWrm
- { 1868, 3, 1, 0, "PUNPCKHBWrr", 0, 0|5|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1868 = PUNPCKHBWrr
- { 1869, 7, 1, 0, "PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1869 = PUNPCKHDQrm
- { 1870, 3, 1, 0, "PUNPCKHDQrr", 0, 0|5|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1870 = PUNPCKHDQrr
- { 1871, 7, 1, 0, "PUNPCKHQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1871 = PUNPCKHQDQrm
- { 1872, 3, 1, 0, "PUNPCKHQDQrr", 0, 0|5|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1872 = PUNPCKHQDQrr
- { 1873, 7, 1, 0, "PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1873 = PUNPCKHWDrm
- { 1874, 3, 1, 0, "PUNPCKHWDrr", 0, 0|5|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1874 = PUNPCKHWDrr
- { 1875, 7, 1, 0, "PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1875 = PUNPCKLBWrm
- { 1876, 3, 1, 0, "PUNPCKLBWrr", 0, 0|5|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1876 = PUNPCKLBWrr
- { 1877, 7, 1, 0, "PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1877 = PUNPCKLDQrm
- { 1878, 3, 1, 0, "PUNPCKLDQrr", 0, 0|5|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1878 = PUNPCKLDQrr
- { 1879, 7, 1, 0, "PUNPCKLQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1879 = PUNPCKLQDQrm
- { 1880, 3, 1, 0, "PUNPCKLQDQrr", 0, 0|5|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1880 = PUNPCKLQDQrr
- { 1881, 7, 1, 0, "PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1881 = PUNPCKLWDrm
- { 1882, 3, 1, 0, "PUNPCKLWDrr", 0, 0|5|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1882 = PUNPCKLWDrr
- { 1883, 1, 0, 0, "PUSH16r", 0|(1<<TID::MayStore), 0|2|(1<<6)|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1883 = PUSH16r
- { 1884, 5, 0, 0, "PUSH16rmm", 0|(1<<TID::MayStore), 0|30|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1884 = PUSH16rmm
- { 1885, 1, 0, 0, "PUSH16rmr", 0|(1<<TID::MayStore), 0|22|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1885 = PUSH16rmr
- { 1886, 1, 0, 0, "PUSH32i16", 0|(1<<TID::MayStore), 0|1|(2<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1886 = PUSH32i16
- { 1887, 1, 0, 0, "PUSH32i32", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1887 = PUSH32i32
- { 1888, 1, 0, 0, "PUSH32i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1888 = PUSH32i8
- { 1889, 1, 0, 0, "PUSH32r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1889 = PUSH32r
- { 1890, 5, 0, 0, "PUSH32rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1890 = PUSH32rmm
- { 1891, 1, 0, 0, "PUSH32rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1891 = PUSH32rmr
- { 1892, 1, 0, 0, "PUSH64i16", 0|(1<<TID::MayStore), 0|1|(2<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1892 = PUSH64i16
- { 1893, 1, 0, 0, "PUSH64i32", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1893 = PUSH64i32
- { 1894, 1, 0, 0, "PUSH64i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1894 = PUSH64i8
- { 1895, 1, 0, 0, "PUSH64r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1895 = PUSH64r
- { 1896, 5, 0, 0, "PUSH64rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo30 }, // Inst #1896 = PUSH64rmm
- { 1897, 1, 0, 0, "PUSH64rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1897 = PUSH64rmr
- { 1898, 0, 0, 0, "PUSHF", 0|(1<<TID::MayStore), 0|1|(1<<6)|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1898 = PUSHF
- { 1899, 0, 0, 0, "PUSHFD", 0|(1<<TID::MayStore), 0|1|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1899 = PUSHFD
- { 1900, 0, 0, 0, "PUSHFQ64", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(156<<24), ImplicitList5, ImplicitList4, NULL, 0 }, // Inst #1900 = PUSHFQ64
- { 1901, 0, 0, 0, "PUSHFS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1901 = PUSHFS16
- { 1902, 0, 0, 0, "PUSHFS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1902 = PUSHFS32
- { 1903, 0, 0, 0, "PUSHFS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1903 = PUSHFS64
- { 1904, 0, 0, 0, "PUSHGS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1904 = PUSHGS16
- { 1905, 0, 0, 0, "PUSHGS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1905 = PUSHGS32
- { 1906, 0, 0, 0, "PUSHGS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1906 = PUSHGS64
- { 1907, 7, 1, 0, "PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1907 = PXORrm
- { 1908, 3, 1, 0, "PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1908 = PXORrr
- { 1909, 10, 1, 0, "RCL16m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1909 = RCL16m1
- { 1910, 10, 1, 0, "RCL16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1910 = RCL16mCL
- { 1911, 11, 1, 0, "RCL16mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1911 = RCL16mi
- { 1912, 2, 1, 0, "RCL16r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1912 = RCL16r1
- { 1913, 2, 1, 0, "RCL16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1913 = RCL16rCL
- { 1914, 3, 1, 0, "RCL16ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1914 = RCL16ri
- { 1915, 10, 1, 0, "RCL32m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1915 = RCL32m1
- { 1916, 10, 1, 0, "RCL32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1916 = RCL32mCL
- { 1917, 11, 1, 0, "RCL32mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1917 = RCL32mi
- { 1918, 2, 1, 0, "RCL32r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1918 = RCL32r1
- { 1919, 2, 1, 0, "RCL32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1919 = RCL32rCL
- { 1920, 3, 1, 0, "RCL32ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1920 = RCL32ri
- { 1921, 10, 1, 0, "RCL64m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1921 = RCL64m1
- { 1922, 10, 1, 0, "RCL64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1922 = RCL64mCL
- { 1923, 11, 1, 0, "RCL64mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1923 = RCL64mi
- { 1924, 2, 1, 0, "RCL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1924 = RCL64r1
- { 1925, 2, 1, 0, "RCL64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1925 = RCL64rCL
- { 1926, 3, 1, 0, "RCL64ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1926 = RCL64ri
- { 1927, 10, 1, 0, "RCL8m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1927 = RCL8m1
- { 1928, 10, 1, 0, "RCL8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1928 = RCL8mCL
- { 1929, 11, 1, 0, "RCL8mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1929 = RCL8mi
- { 1930, 2, 1, 0, "RCL8r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1930 = RCL8r1
- { 1931, 2, 1, 0, "RCL8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1931 = RCL8rCL
- { 1932, 3, 1, 0, "RCL8ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1932 = RCL8ri
- { 1933, 6, 1, 0, "RCPPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1933 = RCPPSm
- { 1934, 6, 1, 0, "RCPPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1934 = RCPPSm_Int
- { 1935, 2, 1, 0, "RCPPSr", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1935 = RCPPSr
- { 1936, 2, 1, 0, "RCPPSr_Int", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1936 = RCPPSr_Int
- { 1937, 6, 1, 0, "RCPSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1937 = RCPSSm
- { 1938, 6, 1, 0, "RCPSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1938 = RCPSSm_Int
- { 1939, 2, 1, 0, "RCPSSr", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #1939 = RCPSSr
- { 1940, 2, 1, 0, "RCPSSr_Int", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1940 = RCPSSr_Int
- { 1941, 10, 1, 0, "RCR16m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1941 = RCR16m1
- { 1942, 10, 1, 0, "RCR16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1942 = RCR16mCL
- { 1943, 11, 1, 0, "RCR16mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1943 = RCR16mi
- { 1944, 2, 1, 0, "RCR16r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1944 = RCR16r1
- { 1945, 2, 1, 0, "RCR16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1945 = RCR16rCL
- { 1946, 3, 1, 0, "RCR16ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1946 = RCR16ri
- { 1947, 10, 1, 0, "RCR32m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1947 = RCR32m1
- { 1948, 10, 1, 0, "RCR32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1948 = RCR32mCL
- { 1949, 11, 1, 0, "RCR32mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1949 = RCR32mi
- { 1950, 2, 1, 0, "RCR32r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1950 = RCR32r1
- { 1951, 2, 1, 0, "RCR32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1951 = RCR32rCL
- { 1952, 3, 1, 0, "RCR32ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1952 = RCR32ri
- { 1953, 10, 1, 0, "RCR64m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1953 = RCR64m1
- { 1954, 10, 1, 0, "RCR64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1954 = RCR64mCL
- { 1955, 11, 1, 0, "RCR64mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1955 = RCR64mi
- { 1956, 2, 1, 0, "RCR64r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1956 = RCR64r1
- { 1957, 2, 1, 0, "RCR64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1957 = RCR64rCL
- { 1958, 3, 1, 0, "RCR64ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1958 = RCR64ri
- { 1959, 10, 1, 0, "RCR8m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1959 = RCR8m1
- { 1960, 10, 1, 0, "RCR8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1960 = RCR8mCL
- { 1961, 11, 1, 0, "RCR8mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1961 = RCR8mi
- { 1962, 2, 1, 0, "RCR8r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1962 = RCR8r1
- { 1963, 2, 1, 0, "RCR8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1963 = RCR8rCL
- { 1964, 3, 1, 0, "RCR8ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1964 = RCR8ri
- { 1965, 0, 0, 0, "RDMSR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(50<<24), NULL, NULL, NULL, 0 }, // Inst #1965 = RDMSR
- { 1966, 0, 0, 0, "RDPMC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(51<<24), NULL, NULL, NULL, 0 }, // Inst #1966 = RDPMC
- { 1967, 0, 0, 0, "RDTSC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(49<<24), NULL, ImplicitList16, NULL, 0 }, // Inst #1967 = RDTSC
- { 1968, 0, 0, 0, "REP_MOVSB", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(164<<24), ImplicitList41, ImplicitList41, NULL, 0 }, // Inst #1968 = REP_MOVSB
- { 1969, 0, 0, 0, "REP_MOVSD", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(165<<24), ImplicitList41, ImplicitList41, NULL, 0 }, // Inst #1969 = REP_MOVSD
- { 1970, 0, 0, 0, "REP_MOVSQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(165<<24), ImplicitList42, ImplicitList42, NULL, 0 }, // Inst #1970 = REP_MOVSQ
- { 1971, 0, 0, 0, "REP_MOVSW", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(165<<24), ImplicitList41, ImplicitList41, NULL, 0 }, // Inst #1971 = REP_MOVSW
- { 1972, 0, 0, 0, "REP_STOSB", 0|(1<<TID::MayStore), 0|1|(2<<8)|(170<<24), ImplicitList43, ImplicitList44, NULL, 0 }, // Inst #1972 = REP_STOSB
- { 1973, 0, 0, 0, "REP_STOSD", 0|(1<<TID::MayStore), 0|1|(2<<8)|(171<<24), ImplicitList45, ImplicitList44, NULL, 0 }, // Inst #1973 = REP_STOSD
- { 1974, 0, 0, 0, "REP_STOSQ", 0|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(171<<24), ImplicitList46, ImplicitList47, NULL, 0 }, // Inst #1974 = REP_STOSQ
- { 1975, 0, 0, 0, "REP_STOSW", 0|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(171<<24), ImplicitList48, ImplicitList44, NULL, 0 }, // Inst #1975 = REP_STOSW
- { 1976, 0, 0, 0, "RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(7<<16)|(195<<24), NULL, NULL, NULL, 0 }, // Inst #1976 = RET
- { 1977, 1, 0, 0, "RETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(2<<13)|(7<<16)|(194<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1977 = RETI
- { 1978, 5, 0, 0, "ROL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1978 = ROL16m1
- { 1979, 5, 0, 0, "ROL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1979 = ROL16mCL
- { 1980, 6, 0, 0, "ROL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1980 = ROL16mi
- { 1981, 2, 1, 0, "ROL16r1", 0, 0|16|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1981 = ROL16r1
- { 1982, 2, 1, 0, "ROL16rCL", 0, 0|16|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1982 = ROL16rCL
- { 1983, 3, 1, 0, "ROL16ri", 0, 0|16|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1983 = ROL16ri
- { 1984, 5, 0, 0, "ROL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1984 = ROL32m1
- { 1985, 5, 0, 0, "ROL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1985 = ROL32mCL
- { 1986, 6, 0, 0, "ROL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1986 = ROL32mi
- { 1987, 2, 1, 0, "ROL32r1", 0, 0|16|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1987 = ROL32r1
- { 1988, 2, 1, 0, "ROL32rCL", 0, 0|16|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1988 = ROL32rCL
- { 1989, 3, 1, 0, "ROL32ri", 0, 0|16|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1989 = ROL32ri
- { 1990, 5, 0, 0, "ROL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1990 = ROL64m1
- { 1991, 5, 0, 0, "ROL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1991 = ROL64mCL
- { 1992, 6, 0, 0, "ROL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1992 = ROL64mi
- { 1993, 2, 1, 0, "ROL64r1", 0, 0|16|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1993 = ROL64r1
- { 1994, 2, 1, 0, "ROL64rCL", 0, 0|16|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1994 = ROL64rCL
- { 1995, 3, 1, 0, "ROL64ri", 0, 0|16|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1995 = ROL64ri
- { 1996, 5, 0, 0, "ROL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1996 = ROL8m1
- { 1997, 5, 0, 0, "ROL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1997 = ROL8mCL
- { 1998, 6, 0, 0, "ROL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1998 = ROL8mi
- { 1999, 2, 1, 0, "ROL8r1", 0, 0|16|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1999 = ROL8r1
- { 2000, 2, 1, 0, "ROL8rCL", 0, 0|16|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2000 = ROL8rCL
- { 2001, 3, 1, 0, "ROL8ri", 0, 0|16|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2001 = ROL8ri
- { 2002, 5, 0, 0, "ROR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2002 = ROR16m1
- { 2003, 5, 0, 0, "ROR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2003 = ROR16mCL
- { 2004, 6, 0, 0, "ROR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2004 = ROR16mi
- { 2005, 2, 1, 0, "ROR16r1", 0, 0|17|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2005 = ROR16r1
- { 2006, 2, 1, 0, "ROR16rCL", 0, 0|17|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2006 = ROR16rCL
- { 2007, 3, 1, 0, "ROR16ri", 0, 0|17|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2007 = ROR16ri
- { 2008, 5, 0, 0, "ROR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2008 = ROR32m1
- { 2009, 5, 0, 0, "ROR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2009 = ROR32mCL
- { 2010, 6, 0, 0, "ROR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2010 = ROR32mi
- { 2011, 2, 1, 0, "ROR32r1", 0, 0|17|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2011 = ROR32r1
- { 2012, 2, 1, 0, "ROR32rCL", 0, 0|17|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2012 = ROR32rCL
- { 2013, 3, 1, 0, "ROR32ri", 0, 0|17|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2013 = ROR32ri
- { 2014, 5, 0, 0, "ROR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2014 = ROR64m1
- { 2015, 5, 0, 0, "ROR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2015 = ROR64mCL
- { 2016, 6, 0, 0, "ROR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2016 = ROR64mi
- { 2017, 2, 1, 0, "ROR64r1", 0, 0|17|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2017 = ROR64r1
- { 2018, 2, 1, 0, "ROR64rCL", 0, 0|17|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2018 = ROR64rCL
- { 2019, 3, 1, 0, "ROR64ri", 0, 0|17|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2019 = ROR64ri
- { 2020, 5, 0, 0, "ROR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2020 = ROR8m1
- { 2021, 5, 0, 0, "ROR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2021 = ROR8mCL
- { 2022, 6, 0, 0, "ROR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2022 = ROR8mi
- { 2023, 2, 1, 0, "ROR8r1", 0, 0|17|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2023 = ROR8r1
- { 2024, 2, 1, 0, "ROR8rCL", 0, 0|17|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2024 = ROR8rCL
- { 2025, 3, 1, 0, "ROR8ri", 0, 0|17|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2025 = ROR8ri
- { 2026, 7, 1, 0, "ROUNDPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #2026 = ROUNDPDm_Int
- { 2027, 3, 1, 0, "ROUNDPDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #2027 = ROUNDPDr_Int
- { 2028, 7, 1, 0, "ROUNDPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #2028 = ROUNDPSm_Int
- { 2029, 3, 1, 0, "ROUNDPSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #2029 = ROUNDPSr_Int
- { 2030, 8, 1, 0, "ROUNDSDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2030 = ROUNDSDm_Int
- { 2031, 4, 1, 0, "ROUNDSDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2031 = ROUNDSDr_Int
- { 2032, 8, 1, 0, "ROUNDSSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2032 = ROUNDSSm_Int
- { 2033, 4, 1, 0, "ROUNDSSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2033 = ROUNDSSr_Int
- { 2034, 0, 0, 0, "RSM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(170<<24), NULL, NULL, NULL, 0 }, // Inst #2034 = RSM
- { 2035, 6, 1, 0, "RSQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2035 = RSQRTPSm
- { 2036, 6, 1, 0, "RSQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2036 = RSQRTPSm_Int
- { 2037, 2, 1, 0, "RSQRTPSr", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2037 = RSQRTPSr
- { 2038, 2, 1, 0, "RSQRTPSr_Int", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2038 = RSQRTPSr_Int
- { 2039, 6, 1, 0, "RSQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2039 = RSQRTSSm
- { 2040, 6, 1, 0, "RSQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2040 = RSQRTSSm_Int
- { 2041, 2, 1, 0, "RSQRTSSr", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #2041 = RSQRTSSr
- { 2042, 2, 1, 0, "RSQRTSSr_Int", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2042 = RSQRTSSr_Int
- { 2043, 0, 0, 0, "SAHF", 0, 0|1|(158<<24), ImplicitList26, ImplicitList1, Barriers1, 0 }, // Inst #2043 = SAHF
- { 2044, 5, 0, 0, "SAR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2044 = SAR16m1
- { 2045, 5, 0, 0, "SAR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2045 = SAR16mCL
- { 2046, 6, 0, 0, "SAR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2046 = SAR16mi
- { 2047, 2, 1, 0, "SAR16r1", 0, 0|23|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2047 = SAR16r1
- { 2048, 2, 1, 0, "SAR16rCL", 0, 0|23|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2048 = SAR16rCL
- { 2049, 3, 1, 0, "SAR16ri", 0, 0|23|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2049 = SAR16ri
- { 2050, 5, 0, 0, "SAR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2050 = SAR32m1
- { 2051, 5, 0, 0, "SAR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2051 = SAR32mCL
- { 2052, 6, 0, 0, "SAR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2052 = SAR32mi
- { 2053, 2, 1, 0, "SAR32r1", 0, 0|23|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2053 = SAR32r1
- { 2054, 2, 1, 0, "SAR32rCL", 0, 0|23|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2054 = SAR32rCL
- { 2055, 3, 1, 0, "SAR32ri", 0, 0|23|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2055 = SAR32ri
- { 2056, 5, 0, 0, "SAR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2056 = SAR64m1
- { 2057, 5, 0, 0, "SAR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2057 = SAR64mCL
- { 2058, 6, 0, 0, "SAR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2058 = SAR64mi
- { 2059, 2, 1, 0, "SAR64r1", 0, 0|23|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2059 = SAR64r1
- { 2060, 2, 1, 0, "SAR64rCL", 0, 0|23|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2060 = SAR64rCL
- { 2061, 3, 1, 0, "SAR64ri", 0, 0|23|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2061 = SAR64ri
- { 2062, 5, 0, 0, "SAR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2062 = SAR8m1
- { 2063, 5, 0, 0, "SAR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2063 = SAR8mCL
- { 2064, 6, 0, 0, "SAR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2064 = SAR8mi
- { 2065, 2, 1, 0, "SAR8r1", 0, 0|23|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2065 = SAR8r1
- { 2066, 2, 1, 0, "SAR8rCL", 0, 0|23|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2066 = SAR8rCL
- { 2067, 3, 1, 0, "SAR8ri", 0, 0|23|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2067 = SAR8ri
- { 2068, 1, 0, 0, "SBB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2068 = SBB16i16
- { 2069, 6, 0, 0, "SBB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(2<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2069 = SBB16mi
- { 2070, 6, 0, 0, "SBB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2070 = SBB16mi8
- { 2071, 6, 0, 0, "SBB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2071 = SBB16mr
- { 2072, 3, 1, 0, "SBB16ri", 0, 0|19|(1<<6)|(2<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2072 = SBB16ri
- { 2073, 3, 1, 0, "SBB16ri8", 0, 0|19|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2073 = SBB16ri8
- { 2074, 7, 1, 0, "SBB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2074 = SBB16rm
- { 2075, 3, 1, 0, "SBB16rr", 0, 0|3|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2075 = SBB16rr
- { 2076, 3, 1, 0, "SBB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2076 = SBB16rr_REV
- { 2077, 1, 0, 0, "SBB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2077 = SBB32i32
- { 2078, 6, 0, 0, "SBB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2078 = SBB32mi
- { 2079, 6, 0, 0, "SBB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2079 = SBB32mi8
- { 2080, 6, 0, 0, "SBB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2080 = SBB32mr
- { 2081, 3, 1, 0, "SBB32ri", 0, 0|19|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2081 = SBB32ri
- { 2082, 3, 1, 0, "SBB32ri8", 0, 0|19|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2082 = SBB32ri8
- { 2083, 7, 1, 0, "SBB32rm", 0|(1<<TID::MayLoad), 0|6|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2083 = SBB32rm
- { 2084, 3, 1, 0, "SBB32rr", 0, 0|3|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2084 = SBB32rr
- { 2085, 3, 1, 0, "SBB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2085 = SBB32rr_REV
- { 2086, 1, 0, 0, "SBB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2086 = SBB64i32
- { 2087, 6, 0, 0, "SBB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2087 = SBB64mi32
- { 2088, 6, 0, 0, "SBB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2088 = SBB64mi8
- { 2089, 6, 0, 0, "SBB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2089 = SBB64mr
- { 2090, 3, 1, 0, "SBB64ri32", 0, 0|19|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2090 = SBB64ri32
- { 2091, 3, 1, 0, "SBB64ri8", 0, 0|19|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2091 = SBB64ri8
- { 2092, 7, 1, 0, "SBB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2092 = SBB64rm
- { 2093, 3, 1, 0, "SBB64rr", 0, 0|3|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2093 = SBB64rr
- { 2094, 3, 1, 0, "SBB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2094 = SBB64rr_REV
- { 2095, 1, 0, 0, "SBB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(28<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2095 = SBB8i8
- { 2096, 6, 0, 0, "SBB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(3<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2096 = SBB8mi
- { 2097, 6, 0, 0, "SBB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2097 = SBB8mr
- { 2098, 3, 1, 0, "SBB8ri", 0, 0|19|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2098 = SBB8ri
- { 2099, 7, 1, 0, "SBB8rm", 0|(1<<TID::MayLoad), 0|6|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2099 = SBB8rm
- { 2100, 3, 1, 0, "SBB8rr", 0, 0|3|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2100 = SBB8rr
- { 2101, 3, 1, 0, "SBB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2101 = SBB8rr_REV
- { 2102, 0, 0, 0, "SCAS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2102 = SCAS16
- { 2103, 0, 0, 0, "SCAS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2103 = SCAS32
- { 2104, 0, 0, 0, "SCAS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2104 = SCAS64
- { 2105, 0, 0, 0, "SCAS8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(174<<24), NULL, NULL, NULL, 0 }, // Inst #2105 = SCAS8
- { 2106, 5, 0, 0, "SETAEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2106 = SETAEm
- { 2107, 1, 1, 0, "SETAEr", 0, 0|16|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2107 = SETAEr
- { 2108, 5, 0, 0, "SETAm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2108 = SETAm
- { 2109, 1, 1, 0, "SETAr", 0, 0|16|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2109 = SETAr
- { 2110, 5, 0, 0, "SETBEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2110 = SETBEm
- { 2111, 1, 1, 0, "SETBEr", 0, 0|16|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2111 = SETBEr
- { 2112, 1, 1, 0, "SETB_C16r", 0, 0|32|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo93 }, // Inst #2112 = SETB_C16r
- { 2113, 1, 1, 0, "SETB_C32r", 0, 0|32|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo57 }, // Inst #2113 = SETB_C32r
- { 2114, 1, 1, 0, "SETB_C64r", 0, 0|32|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo58 }, // Inst #2114 = SETB_C64r
- { 2115, 1, 1, 0, "SETB_C8r", 0, 0|32|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo94 }, // Inst #2115 = SETB_C8r
- { 2116, 5, 0, 0, "SETBm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2116 = SETBm
- { 2117, 1, 1, 0, "SETBr", 0, 0|16|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2117 = SETBr
- { 2118, 5, 0, 0, "SETEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2118 = SETEm
- { 2119, 1, 1, 0, "SETEr", 0, 0|16|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2119 = SETEr
- { 2120, 5, 0, 0, "SETGEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2120 = SETGEm
- { 2121, 1, 1, 0, "SETGEr", 0, 0|16|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2121 = SETGEr
- { 2122, 5, 0, 0, "SETGm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2122 = SETGm
- { 2123, 1, 1, 0, "SETGr", 0, 0|16|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2123 = SETGr
- { 2124, 5, 0, 0, "SETLEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2124 = SETLEm
- { 2125, 1, 1, 0, "SETLEr", 0, 0|16|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2125 = SETLEr
- { 2126, 5, 0, 0, "SETLm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2126 = SETLm
- { 2127, 1, 1, 0, "SETLr", 0, 0|16|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2127 = SETLr
- { 2128, 5, 0, 0, "SETNEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2128 = SETNEm
- { 2129, 1, 1, 0, "SETNEr", 0, 0|16|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2129 = SETNEr
- { 2130, 5, 0, 0, "SETNOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2130 = SETNOm
- { 2131, 1, 1, 0, "SETNOr", 0, 0|16|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2131 = SETNOr
- { 2132, 5, 0, 0, "SETNPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2132 = SETNPm
- { 2133, 1, 1, 0, "SETNPr", 0, 0|16|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2133 = SETNPr
- { 2134, 5, 0, 0, "SETNSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2134 = SETNSm
- { 2135, 1, 1, 0, "SETNSr", 0, 0|16|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2135 = SETNSr
- { 2136, 5, 0, 0, "SETOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2136 = SETOm
- { 2137, 1, 1, 0, "SETOr", 0, 0|16|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2137 = SETOr
- { 2138, 5, 0, 0, "SETPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2138 = SETPm
- { 2139, 1, 1, 0, "SETPr", 0, 0|16|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2139 = SETPr
- { 2140, 5, 0, 0, "SETSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2140 = SETSm
- { 2141, 1, 1, 0, "SETSr", 0, 0|16|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2141 = SETSr
- { 2142, 0, 0, 0, "SFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|23|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #2142 = SFENCE
- { 2143, 5, 1, 0, "SGDTm", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2143 = SGDTm
- { 2144, 5, 0, 0, "SHL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2144 = SHL16m1
- { 2145, 5, 0, 0, "SHL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2145 = SHL16mCL
- { 2146, 6, 0, 0, "SHL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2146 = SHL16mi
- { 2147, 2, 1, 0, "SHL16r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2147 = SHL16r1
- { 2148, 2, 1, 0, "SHL16rCL", 0, 0|20|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2148 = SHL16rCL
- { 2149, 3, 1, 0, "SHL16ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2149 = SHL16ri
- { 2150, 5, 0, 0, "SHL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2150 = SHL32m1
- { 2151, 5, 0, 0, "SHL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2151 = SHL32mCL
- { 2152, 6, 0, 0, "SHL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2152 = SHL32mi
- { 2153, 2, 1, 0, "SHL32r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2153 = SHL32r1
- { 2154, 2, 1, 0, "SHL32rCL", 0, 0|20|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2154 = SHL32rCL
- { 2155, 3, 1, 0, "SHL32ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2155 = SHL32ri
- { 2156, 5, 0, 0, "SHL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2156 = SHL64m1
- { 2157, 5, 0, 0, "SHL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2157 = SHL64mCL
- { 2158, 6, 0, 0, "SHL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2158 = SHL64mi
- { 2159, 2, 1, 0, "SHL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2159 = SHL64r1
- { 2160, 2, 1, 0, "SHL64rCL", 0, 0|20|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2160 = SHL64rCL
- { 2161, 3, 1, 0, "SHL64ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2161 = SHL64ri
- { 2162, 5, 0, 0, "SHL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2162 = SHL8m1
- { 2163, 5, 0, 0, "SHL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2163 = SHL8mCL
- { 2164, 6, 0, 0, "SHL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2164 = SHL8mi
- { 2165, 2, 1, 0, "SHL8r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2165 = SHL8r1
- { 2166, 2, 1, 0, "SHL8rCL", 0, 0|20|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2166 = SHL8rCL
- { 2167, 3, 1, 0, "SHL8ri", 0, 0|20|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2167 = SHL8ri
- { 2168, 6, 0, 0, "SHLD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2168 = SHLD16mrCL
- { 2169, 7, 0, 0, "SHLD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo196 }, // Inst #2169 = SHLD16mri8
- { 2170, 3, 1, 0, "SHLD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2170 = SHLD16rrCL
- { 2171, 4, 1, 0, "SHLD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo197 }, // Inst #2171 = SHLD16rri8
- { 2172, 6, 0, 0, "SHLD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2172 = SHLD32mrCL
- { 2173, 7, 0, 0, "SHLD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo198 }, // Inst #2173 = SHLD32mri8
- { 2174, 3, 1, 0, "SHLD32rrCL", 0, 0|3|(1<<8)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2174 = SHLD32rrCL
- { 2175, 4, 1, 0, "SHLD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo199 }, // Inst #2175 = SHLD32rri8
- { 2176, 6, 0, 0, "SHLD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2176 = SHLD64mrCL
- { 2177, 7, 0, 0, "SHLD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo200 }, // Inst #2177 = SHLD64mri8
- { 2178, 3, 1, 0, "SHLD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(165<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2178 = SHLD64rrCL
- { 2179, 4, 1, 0, "SHLD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo201 }, // Inst #2179 = SHLD64rri8
- { 2180, 5, 0, 0, "SHR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2180 = SHR16m1
- { 2181, 5, 0, 0, "SHR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2181 = SHR16mCL
- { 2182, 6, 0, 0, "SHR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2182 = SHR16mi
- { 2183, 2, 1, 0, "SHR16r1", 0, 0|21|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2183 = SHR16r1
- { 2184, 2, 1, 0, "SHR16rCL", 0, 0|21|(1<<6)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2184 = SHR16rCL
- { 2185, 3, 1, 0, "SHR16ri", 0, 0|21|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2185 = SHR16ri
- { 2186, 5, 0, 0, "SHR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2186 = SHR32m1
- { 2187, 5, 0, 0, "SHR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2187 = SHR32mCL
- { 2188, 6, 0, 0, "SHR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2188 = SHR32mi
- { 2189, 2, 1, 0, "SHR32r1", 0, 0|21|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2189 = SHR32r1
- { 2190, 2, 1, 0, "SHR32rCL", 0, 0|21|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2190 = SHR32rCL
- { 2191, 3, 1, 0, "SHR32ri", 0, 0|21|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2191 = SHR32ri
- { 2192, 5, 0, 0, "SHR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2192 = SHR64m1
- { 2193, 5, 0, 0, "SHR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2193 = SHR64mCL
- { 2194, 6, 0, 0, "SHR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2194 = SHR64mi
- { 2195, 2, 1, 0, "SHR64r1", 0, 0|21|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2195 = SHR64r1
- { 2196, 2, 1, 0, "SHR64rCL", 0, 0|21|(1<<12)|(211<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2196 = SHR64rCL
- { 2197, 3, 1, 0, "SHR64ri", 0, 0|21|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2197 = SHR64ri
- { 2198, 5, 0, 0, "SHR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2198 = SHR8m1
- { 2199, 5, 0, 0, "SHR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2199 = SHR8mCL
- { 2200, 6, 0, 0, "SHR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2200 = SHR8mi
- { 2201, 2, 1, 0, "SHR8r1", 0, 0|21|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2201 = SHR8r1
- { 2202, 2, 1, 0, "SHR8rCL", 0, 0|21|(210<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2202 = SHR8rCL
- { 2203, 3, 1, 0, "SHR8ri", 0, 0|21|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2203 = SHR8ri
- { 2204, 6, 0, 0, "SHRD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2204 = SHRD16mrCL
- { 2205, 7, 0, 0, "SHRD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo196 }, // Inst #2205 = SHRD16mri8
- { 2206, 3, 1, 0, "SHRD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2206 = SHRD16rrCL
- { 2207, 4, 1, 0, "SHRD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo197 }, // Inst #2207 = SHRD16rri8
- { 2208, 6, 0, 0, "SHRD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2208 = SHRD32mrCL
- { 2209, 7, 0, 0, "SHRD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo198 }, // Inst #2209 = SHRD32mri8
- { 2210, 3, 1, 0, "SHRD32rrCL", 0, 0|3|(1<<8)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2210 = SHRD32rrCL
- { 2211, 4, 1, 0, "SHRD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo199 }, // Inst #2211 = SHRD32rri8
- { 2212, 6, 0, 0, "SHRD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2212 = SHRD64mrCL
- { 2213, 7, 0, 0, "SHRD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo200 }, // Inst #2213 = SHRD64mri8
- { 2214, 3, 1, 0, "SHRD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(173<<24), ImplicitList40, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2214 = SHRD64rrCL
- { 2215, 4, 1, 0, "SHRD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo201 }, // Inst #2215 = SHRD64rri8
- { 2216, 8, 1, 0, "SHUFPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2216 = SHUFPDrmi
- { 2217, 4, 1, 0, "SHUFPDrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2217 = SHUFPDrri
- { 2218, 8, 1, 0, "SHUFPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2218 = SHUFPSrmi
- { 2219, 4, 1, 0, "SHUFPSrri", 0|(1<<TID::ConvertibleTo3Addr), 0|5|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2219 = SHUFPSrri
- { 2220, 5, 1, 0, "SIDTm", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2220 = SIDTm
- { 2221, 0, 0, 0, "SIN_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(254<<24), NULL, NULL, NULL, 0 }, // Inst #2221 = SIN_F
- { 2222, 2, 1, 0, "SIN_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2222 = SIN_Fp32
- { 2223, 2, 1, 0, "SIN_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2223 = SIN_Fp64
- { 2224, 2, 1, 0, "SIN_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2224 = SIN_Fp80
- { 2225, 5, 1, 0, "SLDT16m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2225 = SLDT16m
- { 2226, 1, 1, 0, "SLDT16r", 0|(1<<TID::UnmodeledSideEffects), 0|16|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2226 = SLDT16r
- { 2227, 5, 1, 0, "SLDT64m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(1<<12), NULL, NULL, NULL, OperandInfo30 }, // Inst #2227 = SLDT64m
- { 2228, 1, 1, 0, "SLDT64r", 0|(1<<TID::UnmodeledSideEffects), 0|16|(1<<8)|(1<<12), NULL, NULL, NULL, OperandInfo58 }, // Inst #2228 = SLDT64r
- { 2229, 5, 1, 0, "SMSW16m", 0|(1<<TID::UnmodeledSideEffects), 0|28|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2229 = SMSW16m
- { 2230, 1, 1, 0, "SMSW16r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #2230 = SMSW16r
- { 2231, 1, 1, 0, "SMSW32r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2231 = SMSW32r
- { 2232, 1, 1, 0, "SMSW64r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8)|(1<<12)|(1<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2232 = SMSW64r
- { 2233, 6, 1, 0, "SQRTPDm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2233 = SQRTPDm
- { 2234, 6, 1, 0, "SQRTPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2234 = SQRTPDm_Int
- { 2235, 2, 1, 0, "SQRTPDr", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2235 = SQRTPDr
- { 2236, 2, 1, 0, "SQRTPDr_Int", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2236 = SQRTPDr_Int
- { 2237, 6, 1, 0, "SQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2237 = SQRTPSm
- { 2238, 6, 1, 0, "SQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2238 = SQRTPSm_Int
- { 2239, 2, 1, 0, "SQRTPSr", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2239 = SQRTPSr
- { 2240, 2, 1, 0, "SQRTPSr_Int", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2240 = SQRTPSr_Int
- { 2241, 6, 1, 0, "SQRTSDm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #2241 = SQRTSDm
- { 2242, 6, 1, 0, "SQRTSDm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2242 = SQRTSDm_Int
- { 2243, 2, 1, 0, "SQRTSDr", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #2243 = SQRTSDr
- { 2244, 2, 1, 0, "SQRTSDr_Int", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2244 = SQRTSDr_Int
- { 2245, 6, 1, 0, "SQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2245 = SQRTSSm
- { 2246, 6, 1, 0, "SQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2246 = SQRTSSm_Int
- { 2247, 2, 1, 0, "SQRTSSr", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #2247 = SQRTSSr
- { 2248, 2, 1, 0, "SQRTSSr_Int", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2248 = SQRTSSr_Int
- { 2249, 0, 0, 0, "SQRT_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(250<<24), NULL, NULL, NULL, 0 }, // Inst #2249 = SQRT_F
- { 2250, 2, 1, 0, "SQRT_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2250 = SQRT_Fp32
- { 2251, 2, 1, 0, "SQRT_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2251 = SQRT_Fp64
- { 2252, 2, 1, 0, "SQRT_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2252 = SQRT_Fp80
- { 2253, 0, 0, 0, "STC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(249<<24), NULL, NULL, NULL, 0 }, // Inst #2253 = STC
- { 2254, 0, 0, 0, "STD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(253<<24), NULL, NULL, NULL, 0 }, // Inst #2254 = STD
- { 2255, 0, 0, 0, "STI", 0|(1<<TID::UnmodeledSideEffects), 0|1|(251<<24), NULL, NULL, NULL, 0 }, // Inst #2255 = STI
- { 2256, 5, 0, 0, "STMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2256 = STMXCSR
- { 2257, 5, 1, 0, "STRm", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2257 = STRm
- { 2258, 1, 1, 0, "STRr", 0|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2258 = STRr
- { 2259, 5, 0, 0, "ST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2259 = ST_F32m
- { 2260, 5, 0, 0, "ST_F64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2260 = ST_F64m
- { 2261, 5, 0, 0, "ST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2261 = ST_FP32m
- { 2262, 5, 0, 0, "ST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2262 = ST_FP64m
- { 2263, 5, 0, 0, "ST_FP80m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2263 = ST_FP80m
- { 2264, 1, 0, 0, "ST_FPrr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2264 = ST_FPrr
- { 2265, 6, 0, 0, "ST_Fp32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2265 = ST_Fp32m
- { 2266, 6, 0, 0, "ST_Fp64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2266 = ST_Fp64m
- { 2267, 6, 0, 0, "ST_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2267 = ST_Fp64m32
- { 2268, 6, 0, 0, "ST_Fp80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2268 = ST_Fp80m32
- { 2269, 6, 0, 0, "ST_Fp80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2269 = ST_Fp80m64
- { 2270, 6, 0, 0, "ST_FpP32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2270 = ST_FpP32m
- { 2271, 6, 0, 0, "ST_FpP64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2271 = ST_FpP64m
- { 2272, 6, 0, 0, "ST_FpP64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2272 = ST_FpP64m32
- { 2273, 6, 0, 0, "ST_FpP80m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2273 = ST_FpP80m
- { 2274, 6, 0, 0, "ST_FpP80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2274 = ST_FpP80m32
- { 2275, 6, 0, 0, "ST_FpP80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2275 = ST_FpP80m64
- { 2276, 1, 0, 0, "ST_Frr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2276 = ST_Frr
- { 2277, 1, 0, 0, "SUB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2277 = SUB16i16
- { 2278, 6, 0, 0, "SUB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2278 = SUB16mi
- { 2279, 6, 0, 0, "SUB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2279 = SUB16mi8
- { 2280, 6, 0, 0, "SUB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2280 = SUB16mr
- { 2281, 3, 1, 0, "SUB16ri", 0, 0|21|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2281 = SUB16ri
- { 2282, 3, 1, 0, "SUB16ri8", 0, 0|21|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2282 = SUB16ri8
- { 2283, 7, 1, 0, "SUB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2283 = SUB16rm
- { 2284, 3, 1, 0, "SUB16rr", 0, 0|3|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2284 = SUB16rr
- { 2285, 3, 1, 0, "SUB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2285 = SUB16rr_REV
- { 2286, 1, 0, 0, "SUB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2286 = SUB32i32
- { 2287, 6, 0, 0, "SUB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2287 = SUB32mi
- { 2288, 6, 0, 0, "SUB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2288 = SUB32mi8
- { 2289, 6, 0, 0, "SUB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2289 = SUB32mr
- { 2290, 3, 1, 0, "SUB32ri", 0, 0|21|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2290 = SUB32ri
- { 2291, 3, 1, 0, "SUB32ri8", 0, 0|21|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2291 = SUB32ri8
- { 2292, 7, 1, 0, "SUB32rm", 0|(1<<TID::MayLoad), 0|6|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2292 = SUB32rm
- { 2293, 3, 1, 0, "SUB32rr", 0, 0|3|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2293 = SUB32rr
- { 2294, 3, 1, 0, "SUB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2294 = SUB32rr_REV
- { 2295, 1, 0, 0, "SUB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2295 = SUB64i32
- { 2296, 6, 0, 0, "SUB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2296 = SUB64mi32
- { 2297, 6, 0, 0, "SUB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2297 = SUB64mi8
- { 2298, 6, 0, 0, "SUB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2298 = SUB64mr
- { 2299, 3, 1, 0, "SUB64ri32", 0, 0|21|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2299 = SUB64ri32
- { 2300, 3, 1, 0, "SUB64ri8", 0, 0|21|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2300 = SUB64ri8
- { 2301, 7, 1, 0, "SUB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2301 = SUB64rm
- { 2302, 3, 1, 0, "SUB64rr", 0, 0|3|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2302 = SUB64rr
- { 2303, 3, 1, 0, "SUB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2303 = SUB64rr_REV
- { 2304, 1, 0, 0, "SUB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(44<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2304 = SUB8i8
- { 2305, 6, 0, 0, "SUB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2305 = SUB8mi
- { 2306, 6, 0, 0, "SUB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2306 = SUB8mr
- { 2307, 3, 1, 0, "SUB8ri", 0, 0|21|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2307 = SUB8ri
- { 2308, 7, 1, 0, "SUB8rm", 0|(1<<TID::MayLoad), 0|6|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2308 = SUB8rm
- { 2309, 3, 1, 0, "SUB8rr", 0, 0|3|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2309 = SUB8rr
- { 2310, 3, 1, 0, "SUB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2310 = SUB8rr_REV
- { 2311, 7, 1, 0, "SUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2311 = SUBPDrm
- { 2312, 3, 1, 0, "SUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2312 = SUBPDrr
- { 2313, 7, 1, 0, "SUBPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2313 = SUBPSrm
- { 2314, 3, 1, 0, "SUBPSrr", 0, 0|5|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2314 = SUBPSrr
- { 2315, 5, 0, 0, "SUBR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2315 = SUBR_F32m
- { 2316, 5, 0, 0, "SUBR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2316 = SUBR_F64m
- { 2317, 5, 0, 0, "SUBR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2317 = SUBR_FI16m
- { 2318, 5, 0, 0, "SUBR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2318 = SUBR_FI32m
- { 2319, 1, 0, 0, "SUBR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2319 = SUBR_FPrST0
- { 2320, 1, 0, 0, "SUBR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2320 = SUBR_FST0r
- { 2321, 7, 1, 0, "SUBR_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2321 = SUBR_Fp32m
- { 2322, 7, 1, 0, "SUBR_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2322 = SUBR_Fp64m
- { 2323, 7, 1, 0, "SUBR_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2323 = SUBR_Fp64m32
- { 2324, 7, 1, 0, "SUBR_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2324 = SUBR_Fp80m32
- { 2325, 7, 1, 0, "SUBR_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2325 = SUBR_Fp80m64
- { 2326, 7, 1, 0, "SUBR_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2326 = SUBR_FpI16m32
- { 2327, 7, 1, 0, "SUBR_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2327 = SUBR_FpI16m64
- { 2328, 7, 1, 0, "SUBR_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2328 = SUBR_FpI16m80
- { 2329, 7, 1, 0, "SUBR_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2329 = SUBR_FpI32m32
- { 2330, 7, 1, 0, "SUBR_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2330 = SUBR_FpI32m64
- { 2331, 7, 1, 0, "SUBR_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2331 = SUBR_FpI32m80
- { 2332, 1, 0, 0, "SUBR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2332 = SUBR_FrST0
- { 2333, 7, 1, 0, "SUBSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #2333 = SUBSDrm
- { 2334, 7, 1, 0, "SUBSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2334 = SUBSDrm_Int
- { 2335, 3, 1, 0, "SUBSDrr", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #2335 = SUBSDrr
- { 2336, 3, 1, 0, "SUBSDrr_Int", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2336 = SUBSDrr_Int
- { 2337, 7, 1, 0, "SUBSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #2337 = SUBSSrm
- { 2338, 7, 1, 0, "SUBSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2338 = SUBSSrm_Int
- { 2339, 3, 1, 0, "SUBSSrr", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2339 = SUBSSrr
- { 2340, 3, 1, 0, "SUBSSrr_Int", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2340 = SUBSSrr_Int
- { 2341, 5, 0, 0, "SUB_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2341 = SUB_F32m
- { 2342, 5, 0, 0, "SUB_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2342 = SUB_F64m
- { 2343, 5, 0, 0, "SUB_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2343 = SUB_FI16m
- { 2344, 5, 0, 0, "SUB_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2344 = SUB_FI32m
- { 2345, 1, 0, 0, "SUB_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2345 = SUB_FPrST0
- { 2346, 1, 0, 0, "SUB_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2346 = SUB_FST0r
- { 2347, 3, 1, 0, "SUB_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2347 = SUB_Fp32
- { 2348, 7, 1, 0, "SUB_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2348 = SUB_Fp32m
- { 2349, 3, 1, 0, "SUB_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2349 = SUB_Fp64
- { 2350, 7, 1, 0, "SUB_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2350 = SUB_Fp64m
- { 2351, 7, 1, 0, "SUB_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2351 = SUB_Fp64m32
- { 2352, 3, 1, 0, "SUB_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2352 = SUB_Fp80
- { 2353, 7, 1, 0, "SUB_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2353 = SUB_Fp80m32
- { 2354, 7, 1, 0, "SUB_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2354 = SUB_Fp80m64
- { 2355, 7, 1, 0, "SUB_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2355 = SUB_FpI16m32
- { 2356, 7, 1, 0, "SUB_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2356 = SUB_FpI16m64
- { 2357, 7, 1, 0, "SUB_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2357 = SUB_FpI16m80
- { 2358, 7, 1, 0, "SUB_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2358 = SUB_FpI32m32
- { 2359, 7, 1, 0, "SUB_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2359 = SUB_FpI32m64
- { 2360, 7, 1, 0, "SUB_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2360 = SUB_FpI32m80
- { 2361, 1, 0, 0, "SUB_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2361 = SUB_FrST0
- { 2362, 0, 0, 0, "SWPGS", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2362 = SWPGS
- { 2363, 0, 0, 0, "SYSCALL", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(5<<24), NULL, NULL, NULL, 0 }, // Inst #2363 = SYSCALL
- { 2364, 0, 0, 0, "SYSENTER", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(52<<24), NULL, NULL, NULL, 0 }, // Inst #2364 = SYSENTER
- { 2365, 0, 0, 0, "SYSEXIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2365 = SYSEXIT
- { 2366, 0, 0, 0, "SYSEXIT64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<12)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2366 = SYSEXIT64
- { 2367, 0, 0, 0, "SYSRET", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(7<<24), NULL, NULL, NULL, 0 }, // Inst #2367 = SYSRET
- { 2368, 1, 0, 0, "TAILJMPd", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #2368 = TAILJMPd
- { 2369, 5, 0, 0, "TAILJMPm", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2369 = TAILJMPm
- { 2370, 1, 0, 0, "TAILJMPr", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2370 = TAILJMPr
- { 2371, 1, 0, 0, "TAILJMPr64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2371 = TAILJMPr64
- { 2372, 2, 0, 0, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #2372 = TCRETURNdi
- { 2373, 2, 0, 0, "TCRETURNdi64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #2373 = TCRETURNdi64
- { 2374, 2, 0, 0, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo55 }, // Inst #2374 = TCRETURNri
- { 2375, 2, 0, 0, "TCRETURNri64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo56 }, // Inst #2375 = TCRETURNri64
- { 2376, 1, 0, 0, "TEST16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2376 = TEST16i16
- { 2377, 6, 0, 0, "TEST16mi", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(2<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2377 = TEST16mi
- { 2378, 2, 0, 0, "TEST16ri", 0, 0|16|(1<<6)|(2<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #2378 = TEST16ri
- { 2379, 6, 0, 0, "TEST16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #2379 = TEST16rm
- { 2380, 2, 0, 0, "TEST16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #2380 = TEST16rr
- { 2381, 1, 0, 0, "TEST32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2381 = TEST32i32
- { 2382, 6, 0, 0, "TEST32mi", 0|(1<<TID::MayLoad), 0|24|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2382 = TEST32mi
- { 2383, 2, 0, 0, "TEST32ri", 0, 0|16|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #2383 = TEST32ri
- { 2384, 6, 0, 0, "TEST32rm", 0|(1<<TID::MayLoad), 0|6|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #2384 = TEST32rm
- { 2385, 2, 0, 0, "TEST32rr", 0|(1<<TID::Commutable), 0|3|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #2385 = TEST32rr
- { 2386, 1, 0, 0, "TEST64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2386 = TEST64i32
- { 2387, 6, 0, 0, "TEST64mi32", 0|(1<<TID::MayLoad), 0|24|(1<<12)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2387 = TEST64mi32
- { 2388, 2, 0, 0, "TEST64ri32", 0, 0|16|(1<<12)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #2388 = TEST64ri32
- { 2389, 6, 0, 0, "TEST64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #2389 = TEST64rm
- { 2390, 2, 0, 0, "TEST64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #2390 = TEST64rr
- { 2391, 1, 0, 0, "TEST8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(168<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2391 = TEST8i8
- { 2392, 6, 0, 0, "TEST8mi", 0|(1<<TID::MayLoad), 0|24|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2392 = TEST8mi
- { 2393, 2, 0, 0, "TEST8ri", 0, 0|16|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo68 }, // Inst #2393 = TEST8ri
- { 2394, 6, 0, 0, "TEST8rm", 0|(1<<TID::MayLoad), 0|6|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo69 }, // Inst #2394 = TEST8rm
- { 2395, 2, 0, 0, "TEST8rr", 0|(1<<TID::Commutable), 0|3|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #2395 = TEST8rr
- { 2396, 4, 0, 0, "TLS_addr32", 0, 0, ImplicitList2, ImplicitList9, Barriers3, OperandInfo203 }, // Inst #2396 = TLS_addr32
- { 2397, 4, 0, 0, "TLS_addr64", 0, 0, ImplicitList4, ImplicitList10, Barriers4, OperandInfo204 }, // Inst #2397 = TLS_addr64
- { 2398, 0, 0, 0, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(11<<24), NULL, NULL, NULL, 0 }, // Inst #2398 = TRAP
- { 2399, 0, 0, 0, "TST_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(228<<24), NULL, NULL, NULL, 0 }, // Inst #2399 = TST_F
- { 2400, 1, 0, 0, "TST_Fp32", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #2400 = TST_Fp32
- { 2401, 1, 0, 0, "TST_Fp64", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #2401 = TST_Fp64
- { 2402, 1, 0, 0, "TST_Fp80", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #2402 = TST_Fp80
- { 2403, 6, 0, 0, "UCOMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo82 }, // Inst #2403 = UCOMISDrm
- { 2404, 2, 0, 0, "UCOMISDrr", 0, 0|5|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo105 }, // Inst #2404 = UCOMISDrr
- { 2405, 6, 0, 0, "UCOMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo80 }, // Inst #2405 = UCOMISSrm
- { 2406, 2, 0, 0, "UCOMISSrr", 0, 0|5|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo106 }, // Inst #2406 = UCOMISSrr
- { 2407, 1, 0, 0, "UCOM_FIPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(10<<8)|(232<<24), ImplicitList23, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2407 = UCOM_FIPr
- { 2408, 1, 0, 0, "UCOM_FIr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(232<<24), ImplicitList23, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2408 = UCOM_FIr
- { 2409, 0, 0, 0, "UCOM_FPPr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(5<<8)|(233<<24), ImplicitList23, ImplicitList1, Barriers1, 0 }, // Inst #2409 = UCOM_FPPr
- { 2410, 1, 0, 0, "UCOM_FPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(232<<24), ImplicitList23, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2410 = UCOM_FPr
- { 2411, 2, 0, 0, "UCOM_FpIr32", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2411 = UCOM_FpIr32
- { 2412, 2, 0, 0, "UCOM_FpIr64", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2412 = UCOM_FpIr64
- { 2413, 2, 0, 0, "UCOM_FpIr80", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2413 = UCOM_FpIr80
- { 2414, 2, 0, 0, "UCOM_Fpr32", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2414 = UCOM_Fpr32
- { 2415, 2, 0, 0, "UCOM_Fpr64", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2415 = UCOM_Fpr64
- { 2416, 2, 0, 0, "UCOM_Fpr80", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2416 = UCOM_Fpr80
- { 2417, 1, 0, 0, "UCOM_Fr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(224<<24), ImplicitList23, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2417 = UCOM_Fr
- { 2418, 7, 1, 0, "UNPCKHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2418 = UNPCKHPDrm
- { 2419, 3, 1, 0, "UNPCKHPDrr", 0, 0|5|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2419 = UNPCKHPDrr
- { 2420, 7, 1, 0, "UNPCKHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2420 = UNPCKHPSrm
- { 2421, 3, 1, 0, "UNPCKHPSrr", 0, 0|5|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2421 = UNPCKHPSrr
- { 2422, 7, 1, 0, "UNPCKLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2422 = UNPCKLPDrm
- { 2423, 3, 1, 0, "UNPCKLPDrr", 0, 0|5|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2423 = UNPCKLPDrr
- { 2424, 7, 1, 0, "UNPCKLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2424 = UNPCKLPSrm
- { 2425, 3, 1, 0, "UNPCKLPSrr", 0, 0|5|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2425 = UNPCKLPSrr
- { 2426, 3, 0, 0, "VASTART_SAVE_XMM_REGS", 0|(1<<TID::UsesCustomInserter)|(1<<TID::Variadic), 0, NULL, NULL, NULL, OperandInfo205 }, // Inst #2426 = VASTART_SAVE_XMM_REGS
- { 2427, 5, 0, 0, "VERRm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2427 = VERRm
- { 2428, 1, 0, 0, "VERRr", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2428 = VERRr
- { 2429, 5, 0, 0, "VERWm", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2429 = VERWm
- { 2430, 1, 0, 0, "VERWr", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2430 = VERWr
- { 2431, 0, 0, 0, "VMCALL", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2431 = VMCALL
- { 2432, 5, 0, 0, "VMCLEARm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2432 = VMCLEARm
- { 2433, 0, 0, 0, "VMLAUNCH", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2433 = VMLAUNCH
- { 2434, 5, 0, 0, "VMPTRLDm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2434 = VMPTRLDm
- { 2435, 5, 1, 0, "VMPTRSTm", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2435 = VMPTRSTm
- { 2436, 6, 1, 0, "VMREAD32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #2436 = VMREAD32rm
- { 2437, 2, 1, 0, "VMREAD32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2437 = VMREAD32rr
- { 2438, 6, 1, 0, "VMREAD64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #2438 = VMREAD64rm
- { 2439, 2, 1, 0, "VMREAD64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2439 = VMREAD64rr
- { 2440, 0, 0, 0, "VMRESUME", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2440 = VMRESUME
- { 2441, 6, 1, 0, "VMWRITE32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #2441 = VMWRITE32rm
- { 2442, 2, 1, 0, "VMWRITE32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2442 = VMWRITE32rr
- { 2443, 6, 1, 0, "VMWRITE64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #2443 = VMWRITE64rm
- { 2444, 2, 1, 0, "VMWRITE64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2444 = VMWRITE64rr
- { 2445, 0, 0, 0, "VMXOFF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2445 = VMXOFF
- { 2446, 5, 0, 0, "VMXON", 0|(1<<TID::UnmodeledSideEffects), 0|30|(11<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2446 = VMXON
- { 2447, 1, 1, 0, "V_SET0", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo206 }, // Inst #2447 = V_SET0
- { 2448, 1, 1, 0, "V_SETALLONES", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo206 }, // Inst #2448 = V_SETALLONES
- { 2449, 0, 0, 0, "WAIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(155<<24), NULL, NULL, NULL, 0 }, // Inst #2449 = WAIT
- { 2450, 0, 0, 0, "WBINVD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(9<<24), NULL, NULL, NULL, 0 }, // Inst #2450 = WBINVD
- { 2451, 5, 0, 0, "WINCALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList4, ImplicitList49, Barriers8, OperandInfo30 }, // Inst #2451 = WINCALL64m
- { 2452, 1, 0, 0, "WINCALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(232<<24), ImplicitList4, ImplicitList49, Barriers8, OperandInfo5 }, // Inst #2452 = WINCALL64pcrel32
- { 2453, 1, 0, 0, "WINCALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList4, ImplicitList49, Barriers8, OperandInfo58 }, // Inst #2453 = WINCALL64r
- { 2454, 0, 0, 0, "WRMSR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(48<<24), NULL, NULL, NULL, 0 }, // Inst #2454 = WRMSR
- { 2455, 6, 0, 0, "XADD16rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #2455 = XADD16rm
- { 2456, 2, 1, 0, "XADD16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #2456 = XADD16rr
- { 2457, 6, 0, 0, "XADD32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #2457 = XADD32rm
- { 2458, 2, 1, 0, "XADD32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2458 = XADD32rr
- { 2459, 6, 0, 0, "XADD64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(193<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #2459 = XADD64rm
- { 2460, 2, 1, 0, "XADD64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(193<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2460 = XADD64rr
- { 2461, 6, 0, 0, "XADD8rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(192<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #2461 = XADD8rm
- { 2462, 2, 1, 0, "XADD8rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(192<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #2462 = XADD8rr
- { 2463, 1, 0, 0, "XCHG16ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(1<<6)|(144<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #2463 = XCHG16ar
- { 2464, 7, 1, 0, "XCHG16rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo9 }, // Inst #2464 = XCHG16rm
- { 2465, 3, 1, 0, "XCHG16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo10 }, // Inst #2465 = XCHG16rr
- { 2466, 1, 0, 0, "XCHG32ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(144<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2466 = XCHG32ar
- { 2467, 7, 1, 0, "XCHG32rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(135<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #2467 = XCHG32rm
- { 2468, 3, 1, 0, "XCHG32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(135<<24), NULL, NULL, NULL, OperandInfo14 }, // Inst #2468 = XCHG32rr
- { 2469, 1, 0, 0, "XCHG64ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(1<<12)|(144<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2469 = XCHG64ar
- { 2470, 7, 1, 0, "XCHG64rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo17 }, // Inst #2470 = XCHG64rm
- { 2471, 3, 1, 0, "XCHG64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo18 }, // Inst #2471 = XCHG64rr
- { 2472, 7, 1, 0, "XCHG8rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(134<<24), NULL, NULL, NULL, OperandInfo22 }, // Inst #2472 = XCHG8rm
- { 2473, 3, 1, 0, "XCHG8rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(134<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2473 = XCHG8rr
- { 2474, 1, 0, 0, "XCH_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(4<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2474 = XCH_F
- { 2475, 0, 0, 0, "XLAT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(215<<24), NULL, NULL, NULL, 0 }, // Inst #2475 = XLAT
- { 2476, 1, 0, 0, "XOR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2476 = XOR16i16
- { 2477, 6, 0, 0, "XOR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2477 = XOR16mi
- { 2478, 6, 0, 0, "XOR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2478 = XOR16mi8
- { 2479, 6, 0, 0, "XOR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2479 = XOR16mr
- { 2480, 3, 1, 0, "XOR16ri", 0, 0|22|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2480 = XOR16ri
- { 2481, 3, 1, 0, "XOR16ri8", 0, 0|22|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2481 = XOR16ri8
- { 2482, 7, 1, 0, "XOR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2482 = XOR16rm
- { 2483, 3, 1, 0, "XOR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2483 = XOR16rr
- { 2484, 3, 1, 0, "XOR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2484 = XOR16rr_REV
- { 2485, 1, 0, 0, "XOR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2485 = XOR32i32
- { 2486, 6, 0, 0, "XOR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2486 = XOR32mi
- { 2487, 6, 0, 0, "XOR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2487 = XOR32mi8
- { 2488, 6, 0, 0, "XOR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2488 = XOR32mr
- { 2489, 3, 1, 0, "XOR32ri", 0, 0|22|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2489 = XOR32ri
- { 2490, 3, 1, 0, "XOR32ri8", 0, 0|22|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2490 = XOR32ri8
- { 2491, 7, 1, 0, "XOR32rm", 0|(1<<TID::MayLoad), 0|6|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2491 = XOR32rm
- { 2492, 3, 1, 0, "XOR32rr", 0|(1<<TID::Commutable), 0|3|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2492 = XOR32rr
- { 2493, 3, 1, 0, "XOR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2493 = XOR32rr_REV
- { 2494, 1, 0, 0, "XOR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2494 = XOR64i32
- { 2495, 6, 0, 0, "XOR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2495 = XOR64mi32
- { 2496, 6, 0, 0, "XOR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2496 = XOR64mi8
- { 2497, 6, 0, 0, "XOR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2497 = XOR64mr
- { 2498, 3, 1, 0, "XOR64ri32", 0, 0|22|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2498 = XOR64ri32
- { 2499, 3, 1, 0, "XOR64ri8", 0, 0|22|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2499 = XOR64ri8
- { 2500, 7, 1, 0, "XOR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2500 = XOR64rm
- { 2501, 3, 1, 0, "XOR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2501 = XOR64rr
- { 2502, 3, 1, 0, "XOR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2502 = XOR64rr_REV
- { 2503, 1, 0, 0, "XOR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(52<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2503 = XOR8i8
- { 2504, 6, 0, 0, "XOR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2504 = XOR8mi
- { 2505, 6, 0, 0, "XOR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2505 = XOR8mr
- { 2506, 3, 1, 0, "XOR8ri", 0, 0|22|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2506 = XOR8ri
- { 2507, 7, 1, 0, "XOR8rm", 0|(1<<TID::MayLoad), 0|6|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2507 = XOR8rm
- { 2508, 3, 1, 0, "XOR8rr", 0|(1<<TID::Commutable), 0|3|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2508 = XOR8rr
- { 2509, 3, 1, 0, "XOR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2509 = XOR8rr_REV
- { 2510, 7, 1, 0, "XORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2510 = XORPDrm
- { 2511, 3, 1, 0, "XORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2511 = XORPDrr
- { 2512, 7, 1, 0, "XORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2512 = XORPSrm
- { 2513, 3, 1, 0, "XORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2513 = XORPSrr
+ { 11, 0, 0, 0, "DEBUG_VALUE", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, 0 }, // Inst #11 = DEBUG_VALUE
+ { 12, 0, 0, 0, "ABS_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(225<<24), NULL, NULL, NULL, 0 }, // Inst #12 = ABS_F
+ { 13, 2, 1, 0, "ABS_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #13 = ABS_Fp32
+ { 14, 2, 1, 0, "ABS_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #14 = ABS_Fp64
+ { 15, 2, 1, 0, "ABS_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #15 = ABS_Fp80
+ { 16, 1, 0, 0, "ADC16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #16 = ADC16i16
+ { 17, 6, 0, 0, "ADC16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(2<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #17 = ADC16mi
+ { 18, 6, 0, 0, "ADC16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #18 = ADC16mi8
+ { 19, 6, 0, 0, "ADC16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #19 = ADC16mr
+ { 20, 3, 1, 0, "ADC16ri", 0, 0|18|(1<<6)|(2<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #20 = ADC16ri
+ { 21, 3, 1, 0, "ADC16ri8", 0, 0|18|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #21 = ADC16ri8
+ { 22, 7, 1, 0, "ADC16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #22 = ADC16rm
+ { 23, 3, 1, 0, "ADC16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #23 = ADC16rr
+ { 24, 3, 1, 0, "ADC16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #24 = ADC16rr_REV
+ { 25, 1, 0, 0, "ADC32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #25 = ADC32i32
+ { 26, 6, 0, 0, "ADC32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #26 = ADC32mi
+ { 27, 6, 0, 0, "ADC32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #27 = ADC32mi8
+ { 28, 6, 0, 0, "ADC32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #28 = ADC32mr
+ { 29, 3, 1, 0, "ADC32ri", 0, 0|18|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #29 = ADC32ri
+ { 30, 3, 1, 0, "ADC32ri8", 0, 0|18|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #30 = ADC32ri8
+ { 31, 7, 1, 0, "ADC32rm", 0|(1<<TID::MayLoad), 0|6|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #31 = ADC32rm
+ { 32, 3, 1, 0, "ADC32rr", 0|(1<<TID::Commutable), 0|3|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #32 = ADC32rr
+ { 33, 3, 1, 0, "ADC32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #33 = ADC32rr_REV
+ { 34, 1, 0, 0, "ADC64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(21<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #34 = ADC64i32
+ { 35, 6, 0, 0, "ADC64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #35 = ADC64mi32
+ { 36, 6, 0, 0, "ADC64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #36 = ADC64mi8
+ { 37, 6, 0, 0, "ADC64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #37 = ADC64mr
+ { 38, 3, 1, 0, "ADC64ri32", 0, 0|18|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #38 = ADC64ri32
+ { 39, 3, 1, 0, "ADC64ri8", 0, 0|18|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #39 = ADC64ri8
+ { 40, 7, 1, 0, "ADC64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #40 = ADC64rm
+ { 41, 3, 1, 0, "ADC64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(17<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #41 = ADC64rr
+ { 42, 3, 1, 0, "ADC64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(19<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo19 }, // Inst #42 = ADC64rr_REV
+ { 43, 1, 0, 0, "ADC8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(20<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #43 = ADC8i8
+ { 44, 6, 0, 0, "ADC8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #44 = ADC8mi
+ { 45, 6, 0, 0, "ADC8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(16<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #45 = ADC8mr
+ { 46, 3, 1, 0, "ADC8ri", 0, 0|18|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #46 = ADC8ri
+ { 47, 7, 1, 0, "ADC8rm", 0|(1<<TID::MayLoad), 0|6|(18<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #47 = ADC8rm
+ { 48, 3, 1, 0, "ADC8rr", 0|(1<<TID::Commutable), 0|3|(16<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #48 = ADC8rr
+ { 49, 3, 1, 0, "ADC8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(18<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #49 = ADC8rr_REV
+ { 50, 1, 0, 0, "ADD16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #50 = ADD16i16
+ { 51, 6, 0, 0, "ADD16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #51 = ADD16mi
+ { 52, 6, 0, 0, "ADD16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #52 = ADD16mi8
+ { 53, 6, 0, 0, "ADD16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #53 = ADD16mr
+ { 54, 3, 1, 0, "ADD16mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #54 = ADD16mrmrr
+ { 55, 3, 1, 0, "ADD16ri", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #55 = ADD16ri
+ { 56, 3, 1, 0, "ADD16ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #56 = ADD16ri8
+ { 57, 7, 1, 0, "ADD16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #57 = ADD16rm
+ { 58, 3, 1, 0, "ADD16rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<6)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #58 = ADD16rr
+ { 59, 1, 0, 0, "ADD32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #59 = ADD32i32
+ { 60, 6, 0, 0, "ADD32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #60 = ADD32mi
+ { 61, 6, 0, 0, "ADD32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #61 = ADD32mi8
+ { 62, 6, 0, 0, "ADD32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #62 = ADD32mr
+ { 63, 3, 1, 0, "ADD32mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #63 = ADD32mrmrr
+ { 64, 3, 1, 0, "ADD32ri", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #64 = ADD32ri
+ { 65, 3, 1, 0, "ADD32ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #65 = ADD32ri8
+ { 66, 7, 1, 0, "ADD32rm", 0|(1<<TID::MayLoad), 0|6|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #66 = ADD32rm
+ { 67, 3, 1, 0, "ADD32rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #67 = ADD32rr
+ { 68, 1, 0, 0, "ADD64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(5<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #68 = ADD64i32
+ { 69, 6, 0, 0, "ADD64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #69 = ADD64mi32
+ { 70, 6, 0, 0, "ADD64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #70 = ADD64mi8
+ { 71, 6, 0, 0, "ADD64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #71 = ADD64mr
+ { 72, 3, 1, 0, "ADD64mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #72 = ADD64mrmrr
+ { 73, 3, 1, 0, "ADD64ri32", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #73 = ADD64ri32
+ { 74, 3, 1, 0, "ADD64ri8", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #74 = ADD64ri8
+ { 75, 7, 1, 0, "ADD64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #75 = ADD64rm
+ { 76, 3, 1, 0, "ADD64rr", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::Commutable), 0|3|(1<<12)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #76 = ADD64rr
+ { 77, 1, 0, 0, "ADD8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(4<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #77 = ADD8i8
+ { 78, 6, 0, 0, "ADD8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #78 = ADD8mi
+ { 79, 6, 0, 0, "ADD8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4, NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #79 = ADD8mr
+ { 80, 3, 1, 0, "ADD8mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(2<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #80 = ADD8mrmrr
+ { 81, 3, 1, 0, "ADD8ri", 0, 0|16|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #81 = ADD8ri
+ { 82, 7, 1, 0, "ADD8rm", 0|(1<<TID::MayLoad), 0|6|(2<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #82 = ADD8rm
+ { 83, 3, 1, 0, "ADD8rr", 0|(1<<TID::Commutable), 0|3, NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #83 = ADD8rr
+ { 84, 7, 1, 0, "ADDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #84 = ADDPDrm
+ { 85, 3, 1, 0, "ADDPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #85 = ADDPDrr
+ { 86, 7, 1, 0, "ADDPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #86 = ADDPSrm
+ { 87, 3, 1, 0, "ADDPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(88<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #87 = ADDPSrr
+ { 88, 7, 1, 0, "ADDSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #88 = ADDSDrm
+ { 89, 7, 1, 0, "ADDSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #89 = ADDSDrm_Int
+ { 90, 3, 1, 0, "ADDSDrr", 0|(1<<TID::Commutable), 0|5|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #90 = ADDSDrr
+ { 91, 3, 1, 0, "ADDSDrr_Int", 0, 0|5|(11<<8)|(88<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #91 = ADDSDrr_Int
+ { 92, 7, 1, 0, "ADDSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #92 = ADDSSrm
+ { 93, 7, 1, 0, "ADDSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #93 = ADDSSrm_Int
+ { 94, 3, 1, 0, "ADDSSrr", 0|(1<<TID::Commutable), 0|5|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #94 = ADDSSrr
+ { 95, 3, 1, 0, "ADDSSrr_Int", 0, 0|5|(12<<8)|(88<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #95 = ADDSSrr_Int
+ { 96, 7, 1, 0, "ADDSUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(208<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #96 = ADDSUBPDrm
+ { 97, 3, 1, 0, "ADDSUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(208<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #97 = ADDSUBPDrr
+ { 98, 7, 1, 0, "ADDSUBPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(208<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #98 = ADDSUBPSrm
+ { 99, 3, 1, 0, "ADDSUBPSrr", 0, 0|5|(11<<8)|(208<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #99 = ADDSUBPSrr
+ { 100, 5, 0, 0, "ADD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #100 = ADD_F32m
+ { 101, 5, 0, 0, "ADD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #101 = ADD_F64m
+ { 102, 5, 0, 0, "ADD_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #102 = ADD_FI16m
+ { 103, 5, 0, 0, "ADD_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #103 = ADD_FI32m
+ { 104, 1, 0, 0, "ADD_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #104 = ADD_FPrST0
+ { 105, 1, 0, 0, "ADD_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #105 = ADD_FST0r
+ { 106, 3, 1, 0, "ADD_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #106 = ADD_Fp32
+ { 107, 7, 1, 0, "ADD_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #107 = ADD_Fp32m
+ { 108, 3, 1, 0, "ADD_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #108 = ADD_Fp64
+ { 109, 7, 1, 0, "ADD_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #109 = ADD_Fp64m
+ { 110, 7, 1, 0, "ADD_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #110 = ADD_Fp64m32
+ { 111, 3, 1, 0, "ADD_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #111 = ADD_Fp80
+ { 112, 7, 1, 0, "ADD_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #112 = ADD_Fp80m32
+ { 113, 7, 1, 0, "ADD_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #113 = ADD_Fp80m64
+ { 114, 7, 1, 0, "ADD_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #114 = ADD_FpI16m32
+ { 115, 7, 1, 0, "ADD_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #115 = ADD_FpI16m64
+ { 116, 7, 1, 0, "ADD_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #116 = ADD_FpI16m80
+ { 117, 7, 1, 0, "ADD_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #117 = ADD_FpI32m32
+ { 118, 7, 1, 0, "ADD_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #118 = ADD_FpI32m64
+ { 119, 7, 1, 0, "ADD_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #119 = ADD_FpI32m80
+ { 120, 1, 0, 0, "ADD_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #120 = ADD_FrST0
+ { 121, 1, 0, 0, "ADJCALLSTACKDOWN32", 0, 0, ImplicitList2, ImplicitList3, Barriers1, OperandInfo5 }, // Inst #121 = ADJCALLSTACKDOWN32
+ { 122, 1, 0, 0, "ADJCALLSTACKDOWN64", 0, 0, ImplicitList4, ImplicitList5, Barriers1, OperandInfo5 }, // Inst #122 = ADJCALLSTACKDOWN64
+ { 123, 2, 0, 0, "ADJCALLSTACKUP32", 0, 0, ImplicitList2, ImplicitList3, Barriers1, OperandInfo38 }, // Inst #123 = ADJCALLSTACKUP32
+ { 124, 2, 0, 0, "ADJCALLSTACKUP64", 0, 0, ImplicitList4, ImplicitList5, Barriers1, OperandInfo38 }, // Inst #124 = ADJCALLSTACKUP64
+ { 125, 1, 0, 0, "AND16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #125 = AND16i16
+ { 126, 6, 0, 0, "AND16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #126 = AND16mi
+ { 127, 6, 0, 0, "AND16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #127 = AND16mi8
+ { 128, 6, 0, 0, "AND16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #128 = AND16mr
+ { 129, 3, 1, 0, "AND16ri", 0, 0|20|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #129 = AND16ri
+ { 130, 3, 1, 0, "AND16ri8", 0, 0|20|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #130 = AND16ri8
+ { 131, 7, 1, 0, "AND16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #131 = AND16rm
+ { 132, 3, 1, 0, "AND16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #132 = AND16rr
+ { 133, 3, 1, 0, "AND16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #133 = AND16rr_REV
+ { 134, 1, 0, 0, "AND32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #134 = AND32i32
+ { 135, 6, 0, 0, "AND32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #135 = AND32mi
+ { 136, 6, 0, 0, "AND32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #136 = AND32mi8
+ { 137, 6, 0, 0, "AND32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #137 = AND32mr
+ { 138, 3, 1, 0, "AND32ri", 0, 0|20|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #138 = AND32ri
+ { 139, 3, 1, 0, "AND32ri8", 0, 0|20|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #139 = AND32ri8
+ { 140, 7, 1, 0, "AND32rm", 0|(1<<TID::MayLoad), 0|6|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #140 = AND32rm
+ { 141, 3, 1, 0, "AND32rr", 0|(1<<TID::Commutable), 0|3|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #141 = AND32rr
+ { 142, 3, 1, 0, "AND32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #142 = AND32rr_REV
+ { 143, 1, 0, 0, "AND64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(37<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #143 = AND64i32
+ { 144, 6, 0, 0, "AND64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #144 = AND64mi32
+ { 145, 6, 0, 0, "AND64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #145 = AND64mi8
+ { 146, 6, 0, 0, "AND64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #146 = AND64mr
+ { 147, 3, 1, 0, "AND64ri32", 0, 0|20|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #147 = AND64ri32
+ { 148, 3, 1, 0, "AND64ri8", 0, 0|20|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #148 = AND64ri8
+ { 149, 7, 1, 0, "AND64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #149 = AND64rm
+ { 150, 3, 1, 0, "AND64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(33<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #150 = AND64rr
+ { 151, 3, 1, 0, "AND64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(35<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #151 = AND64rr_REV
+ { 152, 1, 0, 0, "AND8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(36<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #152 = AND8i8
+ { 153, 6, 0, 0, "AND8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #153 = AND8mi
+ { 154, 6, 0, 0, "AND8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(32<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #154 = AND8mr
+ { 155, 3, 1, 0, "AND8ri", 0, 0|20|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #155 = AND8ri
+ { 156, 7, 1, 0, "AND8rm", 0|(1<<TID::MayLoad), 0|6|(34<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #156 = AND8rm
+ { 157, 3, 1, 0, "AND8rr", 0|(1<<TID::Commutable), 0|3|(32<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #157 = AND8rr
+ { 158, 3, 1, 0, "AND8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(34<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #158 = AND8rr_REV
+ { 159, 7, 1, 0, "ANDNPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #159 = ANDNPDrm
+ { 160, 3, 1, 0, "ANDNPDrr", 0, 0|5|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #160 = ANDNPDrr
+ { 161, 7, 1, 0, "ANDNPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #161 = ANDNPSrm
+ { 162, 3, 1, 0, "ANDNPSrr", 0, 0|5|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #162 = ANDNPSrr
+ { 163, 7, 1, 0, "ANDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #163 = ANDPDrm
+ { 164, 3, 1, 0, "ANDPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #164 = ANDPDrr
+ { 165, 7, 1, 0, "ANDPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #165 = ANDPSrm
+ { 166, 3, 1, 0, "ANDPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #166 = ANDPSrr
+ { 167, 9, 2, 0, "ATOMADD6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #167 = ATOMADD6432
+ { 168, 7, 1, 0, "ATOMAND16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #168 = ATOMAND16
+ { 169, 7, 1, 0, "ATOMAND32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #169 = ATOMAND32
+ { 170, 7, 1, 0, "ATOMAND64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #170 = ATOMAND64
+ { 171, 9, 2, 0, "ATOMAND6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #171 = ATOMAND6432
+ { 172, 7, 1, 0, "ATOMAND8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo43 }, // Inst #172 = ATOMAND8
+ { 173, 7, 1, 0, "ATOMMAX16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #173 = ATOMMAX16
+ { 174, 7, 1, 0, "ATOMMAX32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #174 = ATOMMAX32
+ { 175, 7, 1, 0, "ATOMMAX64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #175 = ATOMMAX64
+ { 176, 7, 1, 0, "ATOMMIN16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #176 = ATOMMIN16
+ { 177, 7, 1, 0, "ATOMMIN32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #177 = ATOMMIN32
+ { 178, 7, 1, 0, "ATOMMIN64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #178 = ATOMMIN64
+ { 179, 7, 1, 0, "ATOMNAND16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #179 = ATOMNAND16
+ { 180, 7, 1, 0, "ATOMNAND32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #180 = ATOMNAND32
+ { 181, 7, 1, 0, "ATOMNAND64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #181 = ATOMNAND64
+ { 182, 9, 2, 0, "ATOMNAND6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #182 = ATOMNAND6432
+ { 183, 7, 1, 0, "ATOMNAND8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo43 }, // Inst #183 = ATOMNAND8
+ { 184, 7, 1, 0, "ATOMOR16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #184 = ATOMOR16
+ { 185, 7, 1, 0, "ATOMOR32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #185 = ATOMOR32
+ { 186, 7, 1, 0, "ATOMOR64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #186 = ATOMOR64
+ { 187, 9, 2, 0, "ATOMOR6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #187 = ATOMOR6432
+ { 188, 7, 1, 0, "ATOMOR8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo43 }, // Inst #188 = ATOMOR8
+ { 189, 9, 2, 0, "ATOMSUB6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #189 = ATOMSUB6432
+ { 190, 9, 2, 0, "ATOMSWAP6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #190 = ATOMSWAP6432
+ { 191, 7, 1, 0, "ATOMUMAX16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #191 = ATOMUMAX16
+ { 192, 7, 1, 0, "ATOMUMAX32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #192 = ATOMUMAX32
+ { 193, 7, 1, 0, "ATOMUMAX64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #193 = ATOMUMAX64
+ { 194, 7, 1, 0, "ATOMUMIN16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #194 = ATOMUMIN16
+ { 195, 7, 1, 0, "ATOMUMIN32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #195 = ATOMUMIN32
+ { 196, 7, 1, 0, "ATOMUMIN64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #196 = ATOMUMIN64
+ { 197, 7, 1, 0, "ATOMXOR16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo40 }, // Inst #197 = ATOMXOR16
+ { 198, 7, 1, 0, "ATOMXOR32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo41 }, // Inst #198 = ATOMXOR32
+ { 199, 7, 1, 0, "ATOMXOR64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo42 }, // Inst #199 = ATOMXOR64
+ { 200, 9, 2, 0, "ATOMXOR6432", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList6, ImplicitList7, Barriers2, OperandInfo39 }, // Inst #200 = ATOMXOR6432
+ { 201, 7, 1, 0, "ATOMXOR8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, ImplicitList1, Barriers1, OperandInfo43 }, // Inst #201 = ATOMXOR8
+ { 202, 8, 1, 0, "BLENDPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(13<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #202 = BLENDPDrmi
+ { 203, 4, 1, 0, "BLENDPDrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(13<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #203 = BLENDPDrri
+ { 204, 8, 1, 0, "BLENDPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(12<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #204 = BLENDPSrmi
+ { 205, 4, 1, 0, "BLENDPSrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(12<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #205 = BLENDPSrri
+ { 206, 7, 1, 0, "BLENDVPDrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(21<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #206 = BLENDVPDrm0
+ { 207, 3, 1, 0, "BLENDVPDrr0", 0, 0|5|(1<<6)|(13<<8)|(21<<24), ImplicitList8, NULL, NULL, OperandInfo25 }, // Inst #207 = BLENDVPDrr0
+ { 208, 7, 1, 0, "BLENDVPSrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(20<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #208 = BLENDVPSrm0
+ { 209, 3, 1, 0, "BLENDVPSrr0", 0, 0|5|(1<<6)|(13<<8)|(20<<24), ImplicitList8, NULL, NULL, OperandInfo25 }, // Inst #209 = BLENDVPSrr0
+ { 210, 6, 1, 0, "BSF16rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #210 = BSF16rm
+ { 211, 2, 1, 0, "BSF16rr", 0, 0|5|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #211 = BSF16rr
+ { 212, 6, 1, 0, "BSF32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #212 = BSF32rm
+ { 213, 2, 1, 0, "BSF32rr", 0, 0|5|(1<<8)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #213 = BSF32rr
+ { 214, 6, 1, 0, "BSF64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #214 = BSF64rm
+ { 215, 2, 1, 0, "BSF64rr", 0, 0|5|(1<<8)|(1<<12)|(188<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #215 = BSF64rr
+ { 216, 6, 1, 0, "BSR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #216 = BSR16rm
+ { 217, 2, 1, 0, "BSR16rr", 0, 0|5|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #217 = BSR16rr
+ { 218, 6, 1, 0, "BSR32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #218 = BSR32rm
+ { 219, 2, 1, 0, "BSR32rr", 0, 0|5|(1<<8)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #219 = BSR32rr
+ { 220, 6, 1, 0, "BSR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #220 = BSR64rm
+ { 221, 2, 1, 0, "BSR64rr", 0, 0|5|(1<<8)|(1<<12)|(189<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #221 = BSR64rr
+ { 222, 2, 1, 0, "BSWAP32r", 0, 0|2|(1<<8)|(200<<24), NULL, NULL, NULL, OperandInfo52 }, // Inst #222 = BSWAP32r
+ { 223, 2, 1, 0, "BSWAP64r", 0, 0|2|(1<<8)|(1<<12)|(200<<24), NULL, NULL, NULL, OperandInfo53 }, // Inst #223 = BSWAP64r
+ { 224, 6, 0, 0, "BT16mi8", 0|(1<<TID::MayLoad), 0|28|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #224 = BT16mi8
+ { 225, 6, 0, 0, "BT16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #225 = BT16mr
+ { 226, 2, 0, 0, "BT16ri8", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #226 = BT16ri8
+ { 227, 2, 0, 0, "BT16rr", 0, 0|3|(1<<6)|(1<<8)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #227 = BT16rr
+ { 228, 6, 0, 0, "BT32mi8", 0|(1<<TID::MayLoad), 0|28|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #228 = BT32mi8
+ { 229, 6, 0, 0, "BT32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #229 = BT32mr
+ { 230, 2, 0, 0, "BT32ri8", 0, 0|20|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #230 = BT32ri8
+ { 231, 2, 0, 0, "BT32rr", 0, 0|3|(1<<8)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #231 = BT32rr
+ { 232, 6, 0, 0, "BT64mi8", 0|(1<<TID::MayLoad), 0|28|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #232 = BT64mi8
+ { 233, 6, 0, 0, "BT64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #233 = BT64mr
+ { 234, 2, 0, 0, "BT64ri8", 0, 0|20|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #234 = BT64ri8
+ { 235, 2, 0, 0, "BT64rr", 0, 0|3|(1<<8)|(1<<12)|(163<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #235 = BT64rr
+ { 236, 6, 0, 0, "BTC16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #236 = BTC16mi8
+ { 237, 6, 0, 0, "BTC16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #237 = BTC16mr
+ { 238, 2, 0, 0, "BTC16ri8", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #238 = BTC16ri8
+ { 239, 2, 0, 0, "BTC16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #239 = BTC16rr
+ { 240, 6, 0, 0, "BTC32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #240 = BTC32mi8
+ { 241, 6, 0, 0, "BTC32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #241 = BTC32mr
+ { 242, 2, 0, 0, "BTC32ri8", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #242 = BTC32ri8
+ { 243, 2, 0, 0, "BTC32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #243 = BTC32rr
+ { 244, 6, 0, 0, "BTC64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #244 = BTC64mi8
+ { 245, 6, 0, 0, "BTC64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #245 = BTC64mr
+ { 246, 2, 0, 0, "BTC64ri8", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #246 = BTC64ri8
+ { 247, 2, 0, 0, "BTC64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(187<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #247 = BTC64rr
+ { 248, 6, 0, 0, "BTR16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #248 = BTR16mi8
+ { 249, 6, 0, 0, "BTR16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #249 = BTR16mr
+ { 250, 2, 0, 0, "BTR16ri8", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #250 = BTR16ri8
+ { 251, 2, 0, 0, "BTR16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #251 = BTR16rr
+ { 252, 6, 0, 0, "BTR32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #252 = BTR32mi8
+ { 253, 6, 0, 0, "BTR32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #253 = BTR32mr
+ { 254, 2, 0, 0, "BTR32ri8", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #254 = BTR32ri8
+ { 255, 2, 0, 0, "BTR32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #255 = BTR32rr
+ { 256, 6, 0, 0, "BTR64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #256 = BTR64mi8
+ { 257, 6, 0, 0, "BTR64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #257 = BTR64mr
+ { 258, 2, 0, 0, "BTR64ri8", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #258 = BTR64ri8
+ { 259, 2, 0, 0, "BTR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(179<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #259 = BTR64rr
+ { 260, 6, 0, 0, "BTS16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #260 = BTS16mi8
+ { 261, 6, 0, 0, "BTS16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #261 = BTS16mr
+ { 262, 2, 0, 0, "BTS16ri8", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<6)|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #262 = BTS16ri8
+ { 263, 2, 0, 0, "BTS16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #263 = BTS16rr
+ { 264, 6, 0, 0, "BTS32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #264 = BTS32mi8
+ { 265, 6, 0, 0, "BTS32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #265 = BTS32mr
+ { 266, 2, 0, 0, "BTS32ri8", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #266 = BTS32ri8
+ { 267, 2, 0, 0, "BTS32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #267 = BTS32rr
+ { 268, 6, 0, 0, "BTS64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #268 = BTS64mi8
+ { 269, 6, 0, 0, "BTS64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #269 = BTS64mr
+ { 270, 2, 0, 0, "BTS64ri8", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8)|(1<<12)|(1<<13)|(186<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #270 = BTS64ri8
+ { 271, 2, 0, 0, "BTS64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(171<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #271 = BTS64rr
+ { 272, 5, 0, 0, "CALL32m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo30 }, // Inst #272 = CALL32m
+ { 273, 1, 0, 0, "CALL32r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo57 }, // Inst #273 = CALL32r
+ { 274, 5, 0, 0, "CALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo30 }, // Inst #274 = CALL64m
+ { 275, 1, 0, 0, "CALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(232<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo5 }, // Inst #275 = CALL64pcrel32
+ { 276, 1, 0, 0, "CALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo58 }, // Inst #276 = CALL64r
+ { 277, 1, 0, 0, "CALLpcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(232<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo5 }, // Inst #277 = CALLpcrel32
+ { 278, 0, 0, 0, "CBW", 0, 0|1|(1<<6)|(152<<24), ImplicitList11, ImplicitList12, NULL, 0 }, // Inst #278 = CBW
+ { 279, 0, 0, 0, "CDQ", 0, 0|1|(153<<24), ImplicitList13, ImplicitList14, Barriers5, 0 }, // Inst #279 = CDQ
+ { 280, 0, 0, 0, "CDQE", 0, 0|1|(1<<12)|(152<<24), ImplicitList13, ImplicitList15, NULL, 0 }, // Inst #280 = CDQE
+ { 281, 0, 0, 0, "CHS_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(224<<24), NULL, NULL, NULL, 0 }, // Inst #281 = CHS_F
+ { 282, 2, 1, 0, "CHS_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #282 = CHS_Fp32
+ { 283, 2, 1, 0, "CHS_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #283 = CHS_Fp64
+ { 284, 2, 1, 0, "CHS_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #284 = CHS_Fp80
+ { 285, 0, 0, 0, "CLC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(248<<24), NULL, NULL, NULL, 0 }, // Inst #285 = CLC
+ { 286, 0, 0, 0, "CLD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(252<<24), NULL, NULL, NULL, 0 }, // Inst #286 = CLD
+ { 287, 5, 0, 0, "CLFLUSH", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #287 = CLFLUSH
+ { 288, 0, 0, 0, "CLI", 0|(1<<TID::UnmodeledSideEffects), 0|1|(250<<24), NULL, NULL, NULL, 0 }, // Inst #288 = CLI
+ { 289, 0, 0, 0, "CLTS", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(6<<24), NULL, NULL, NULL, 0 }, // Inst #289 = CLTS
+ { 290, 0, 0, 0, "CMC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(245<<24), NULL, NULL, NULL, 0 }, // Inst #290 = CMC
+ { 291, 7, 1, 0, "CMOVA16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #291 = CMOVA16rm
+ { 292, 3, 1, 0, "CMOVA16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #292 = CMOVA16rr
+ { 293, 7, 1, 0, "CMOVA32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #293 = CMOVA32rm
+ { 294, 3, 1, 0, "CMOVA32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #294 = CMOVA32rr
+ { 295, 7, 1, 0, "CMOVA64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #295 = CMOVA64rm
+ { 296, 3, 1, 0, "CMOVA64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(71<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #296 = CMOVA64rr
+ { 297, 7, 1, 0, "CMOVAE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #297 = CMOVAE16rm
+ { 298, 3, 1, 0, "CMOVAE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #298 = CMOVAE16rr
+ { 299, 7, 1, 0, "CMOVAE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #299 = CMOVAE32rm
+ { 300, 3, 1, 0, "CMOVAE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #300 = CMOVAE32rr
+ { 301, 7, 1, 0, "CMOVAE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #301 = CMOVAE64rm
+ { 302, 3, 1, 0, "CMOVAE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(67<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #302 = CMOVAE64rr
+ { 303, 7, 1, 0, "CMOVB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #303 = CMOVB16rm
+ { 304, 3, 1, 0, "CMOVB16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #304 = CMOVB16rr
+ { 305, 7, 1, 0, "CMOVB32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #305 = CMOVB32rm
+ { 306, 3, 1, 0, "CMOVB32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #306 = CMOVB32rr
+ { 307, 7, 1, 0, "CMOVB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #307 = CMOVB64rm
+ { 308, 3, 1, 0, "CMOVB64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(66<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #308 = CMOVB64rr
+ { 309, 7, 1, 0, "CMOVBE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #309 = CMOVBE16rm
+ { 310, 3, 1, 0, "CMOVBE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #310 = CMOVBE16rr
+ { 311, 7, 1, 0, "CMOVBE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #311 = CMOVBE32rm
+ { 312, 3, 1, 0, "CMOVBE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #312 = CMOVBE32rr
+ { 313, 7, 1, 0, "CMOVBE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #313 = CMOVBE64rm
+ { 314, 3, 1, 0, "CMOVBE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(70<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #314 = CMOVBE64rr
+ { 315, 1, 1, 0, "CMOVBE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #315 = CMOVBE_F
+ { 316, 3, 1, 0, "CMOVBE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #316 = CMOVBE_Fp32
+ { 317, 3, 1, 0, "CMOVBE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #317 = CMOVBE_Fp64
+ { 318, 3, 1, 0, "CMOVBE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #318 = CMOVBE_Fp80
+ { 319, 1, 1, 0, "CMOVB_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #319 = CMOVB_F
+ { 320, 3, 1, 0, "CMOVB_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #320 = CMOVB_Fp32
+ { 321, 3, 1, 0, "CMOVB_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #321 = CMOVB_Fp64
+ { 322, 3, 1, 0, "CMOVB_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #322 = CMOVB_Fp80
+ { 323, 7, 1, 0, "CMOVE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #323 = CMOVE16rm
+ { 324, 3, 1, 0, "CMOVE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #324 = CMOVE16rr
+ { 325, 7, 1, 0, "CMOVE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #325 = CMOVE32rm
+ { 326, 3, 1, 0, "CMOVE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #326 = CMOVE32rr
+ { 327, 7, 1, 0, "CMOVE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #327 = CMOVE64rm
+ { 328, 3, 1, 0, "CMOVE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(68<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #328 = CMOVE64rr
+ { 329, 1, 1, 0, "CMOVE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #329 = CMOVE_F
+ { 330, 3, 1, 0, "CMOVE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #330 = CMOVE_Fp32
+ { 331, 3, 1, 0, "CMOVE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #331 = CMOVE_Fp64
+ { 332, 3, 1, 0, "CMOVE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #332 = CMOVE_Fp80
+ { 333, 7, 1, 0, "CMOVG16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #333 = CMOVG16rm
+ { 334, 3, 1, 0, "CMOVG16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #334 = CMOVG16rr
+ { 335, 7, 1, 0, "CMOVG32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #335 = CMOVG32rm
+ { 336, 3, 1, 0, "CMOVG32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #336 = CMOVG32rr
+ { 337, 7, 1, 0, "CMOVG64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #337 = CMOVG64rm
+ { 338, 3, 1, 0, "CMOVG64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(79<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #338 = CMOVG64rr
+ { 339, 7, 1, 0, "CMOVGE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #339 = CMOVGE16rm
+ { 340, 3, 1, 0, "CMOVGE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #340 = CMOVGE16rr
+ { 341, 7, 1, 0, "CMOVGE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #341 = CMOVGE32rm
+ { 342, 3, 1, 0, "CMOVGE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #342 = CMOVGE32rr
+ { 343, 7, 1, 0, "CMOVGE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #343 = CMOVGE64rm
+ { 344, 3, 1, 0, "CMOVGE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(77<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #344 = CMOVGE64rr
+ { 345, 7, 1, 0, "CMOVL16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #345 = CMOVL16rm
+ { 346, 3, 1, 0, "CMOVL16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #346 = CMOVL16rr
+ { 347, 7, 1, 0, "CMOVL32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #347 = CMOVL32rm
+ { 348, 3, 1, 0, "CMOVL32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #348 = CMOVL32rr
+ { 349, 7, 1, 0, "CMOVL64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #349 = CMOVL64rm
+ { 350, 3, 1, 0, "CMOVL64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(76<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #350 = CMOVL64rr
+ { 351, 7, 1, 0, "CMOVLE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #351 = CMOVLE16rm
+ { 352, 3, 1, 0, "CMOVLE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #352 = CMOVLE16rr
+ { 353, 7, 1, 0, "CMOVLE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #353 = CMOVLE32rm
+ { 354, 3, 1, 0, "CMOVLE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #354 = CMOVLE32rr
+ { 355, 7, 1, 0, "CMOVLE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #355 = CMOVLE64rm
+ { 356, 3, 1, 0, "CMOVLE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(78<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #356 = CMOVLE64rr
+ { 357, 1, 1, 0, "CMOVNBE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #357 = CMOVNBE_F
+ { 358, 3, 1, 0, "CMOVNBE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #358 = CMOVNBE_Fp32
+ { 359, 3, 1, 0, "CMOVNBE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #359 = CMOVNBE_Fp64
+ { 360, 3, 1, 0, "CMOVNBE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #360 = CMOVNBE_Fp80
+ { 361, 1, 1, 0, "CMOVNB_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #361 = CMOVNB_F
+ { 362, 3, 1, 0, "CMOVNB_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #362 = CMOVNB_Fp32
+ { 363, 3, 1, 0, "CMOVNB_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #363 = CMOVNB_Fp64
+ { 364, 3, 1, 0, "CMOVNB_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #364 = CMOVNB_Fp80
+ { 365, 7, 1, 0, "CMOVNE16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #365 = CMOVNE16rm
+ { 366, 3, 1, 0, "CMOVNE16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #366 = CMOVNE16rr
+ { 367, 7, 1, 0, "CMOVNE32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #367 = CMOVNE32rm
+ { 368, 3, 1, 0, "CMOVNE32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #368 = CMOVNE32rr
+ { 369, 7, 1, 0, "CMOVNE64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #369 = CMOVNE64rm
+ { 370, 3, 1, 0, "CMOVNE64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(69<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #370 = CMOVNE64rr
+ { 371, 1, 1, 0, "CMOVNE_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #371 = CMOVNE_F
+ { 372, 3, 1, 0, "CMOVNE_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #372 = CMOVNE_Fp32
+ { 373, 3, 1, 0, "CMOVNE_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #373 = CMOVNE_Fp64
+ { 374, 3, 1, 0, "CMOVNE_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #374 = CMOVNE_Fp80
+ { 375, 7, 1, 0, "CMOVNO16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #375 = CMOVNO16rm
+ { 376, 3, 1, 0, "CMOVNO16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #376 = CMOVNO16rr
+ { 377, 7, 1, 0, "CMOVNO32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #377 = CMOVNO32rm
+ { 378, 3, 1, 0, "CMOVNO32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #378 = CMOVNO32rr
+ { 379, 7, 1, 0, "CMOVNO64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #379 = CMOVNO64rm
+ { 380, 3, 1, 0, "CMOVNO64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(65<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #380 = CMOVNO64rr
+ { 381, 7, 1, 0, "CMOVNP16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #381 = CMOVNP16rm
+ { 382, 3, 1, 0, "CMOVNP16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #382 = CMOVNP16rr
+ { 383, 7, 1, 0, "CMOVNP32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #383 = CMOVNP32rm
+ { 384, 3, 1, 0, "CMOVNP32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #384 = CMOVNP32rr
+ { 385, 7, 1, 0, "CMOVNP64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #385 = CMOVNP64rm
+ { 386, 3, 1, 0, "CMOVNP64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(75<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #386 = CMOVNP64rr
+ { 387, 1, 1, 0, "CMOVNP_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #387 = CMOVNP_F
+ { 388, 3, 1, 0, "CMOVNP_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #388 = CMOVNP_Fp32
+ { 389, 3, 1, 0, "CMOVNP_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #389 = CMOVNP_Fp64
+ { 390, 3, 1, 0, "CMOVNP_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #390 = CMOVNP_Fp80
+ { 391, 7, 1, 0, "CMOVNS16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #391 = CMOVNS16rm
+ { 392, 3, 1, 0, "CMOVNS16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #392 = CMOVNS16rr
+ { 393, 7, 1, 0, "CMOVNS32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #393 = CMOVNS32rm
+ { 394, 3, 1, 0, "CMOVNS32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #394 = CMOVNS32rr
+ { 395, 7, 1, 0, "CMOVNS64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #395 = CMOVNS64rm
+ { 396, 3, 1, 0, "CMOVNS64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(73<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #396 = CMOVNS64rr
+ { 397, 7, 1, 0, "CMOVO16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #397 = CMOVO16rm
+ { 398, 3, 1, 0, "CMOVO16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #398 = CMOVO16rr
+ { 399, 7, 1, 0, "CMOVO32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #399 = CMOVO32rm
+ { 400, 3, 1, 0, "CMOVO32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #400 = CMOVO32rr
+ { 401, 7, 1, 0, "CMOVO64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #401 = CMOVO64rm
+ { 402, 3, 1, 0, "CMOVO64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(64<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #402 = CMOVO64rr
+ { 403, 7, 1, 0, "CMOVP16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #403 = CMOVP16rm
+ { 404, 3, 1, 0, "CMOVP16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #404 = CMOVP16rr
+ { 405, 7, 1, 0, "CMOVP32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #405 = CMOVP32rm
+ { 406, 3, 1, 0, "CMOVP32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #406 = CMOVP32rr
+ { 407, 7, 1, 0, "CMOVP64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #407 = CMOVP64rm
+ { 408, 3, 1, 0, "CMOVP64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(74<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #408 = CMOVP64rr
+ { 409, 1, 1, 0, "CMOVP_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(5<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #409 = CMOVP_F
+ { 410, 3, 1, 0, "CMOVP_Fp32", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo59 }, // Inst #410 = CMOVP_Fp32
+ { 411, 3, 1, 0, "CMOVP_Fp64", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo60 }, // Inst #411 = CMOVP_Fp64
+ { 412, 3, 1, 0, "CMOVP_Fp80", 0, 0|(6<<16), ImplicitList1, NULL, NULL, OperandInfo61 }, // Inst #412 = CMOVP_Fp80
+ { 413, 7, 1, 0, "CMOVS16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo9 }, // Inst #413 = CMOVS16rm
+ { 414, 3, 1, 0, "CMOVS16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo10 }, // Inst #414 = CMOVS16rr
+ { 415, 7, 1, 0, "CMOVS32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo13 }, // Inst #415 = CMOVS32rm
+ { 416, 3, 1, 0, "CMOVS32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo14 }, // Inst #416 = CMOVS32rr
+ { 417, 7, 1, 0, "CMOVS64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo17 }, // Inst #417 = CMOVS64rm
+ { 418, 3, 1, 0, "CMOVS64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(72<<24), ImplicitList1, NULL, NULL, OperandInfo18 }, // Inst #418 = CMOVS64rr
+ { 419, 4, 1, 0, "CMOV_FR32", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo62 }, // Inst #419 = CMOV_FR32
+ { 420, 4, 1, 0, "CMOV_FR64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo63 }, // Inst #420 = CMOV_FR64
+ { 421, 4, 1, 0, "CMOV_GR8", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, ImplicitList1, Barriers1, OperandInfo64 }, // Inst #421 = CMOV_GR8
+ { 422, 4, 1, 0, "CMOV_V1I64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo65 }, // Inst #422 = CMOV_V1I64
+ { 423, 4, 1, 0, "CMOV_V2F64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo66 }, // Inst #423 = CMOV_V2F64
+ { 424, 4, 1, 0, "CMOV_V2I64", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo66 }, // Inst #424 = CMOV_V2I64
+ { 425, 4, 1, 0, "CMOV_V4F32", 0|(1<<TID::UsesCustomInserter), 0, ImplicitList1, NULL, NULL, OperandInfo66 }, // Inst #425 = CMOV_V4F32
+ { 426, 1, 0, 0, "CMP16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #426 = CMP16i16
+ { 427, 6, 0, 0, "CMP16mi", 0|(1<<TID::MayLoad), 0|31|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #427 = CMP16mi
+ { 428, 6, 0, 0, "CMP16mi8", 0|(1<<TID::MayLoad), 0|31|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #428 = CMP16mi8
+ { 429, 6, 0, 0, "CMP16mr", 0|(1<<TID::MayLoad), 0|4|(1<<6)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #429 = CMP16mr
+ { 430, 2, 0, 0, "CMP16mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #430 = CMP16mrmrr
+ { 431, 2, 0, 0, "CMP16ri", 0, 0|23|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #431 = CMP16ri
+ { 432, 2, 0, 0, "CMP16ri8", 0, 0|23|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #432 = CMP16ri8
+ { 433, 6, 0, 0, "CMP16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #433 = CMP16rm
+ { 434, 2, 0, 0, "CMP16rr", 0, 0|3|(1<<6)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #434 = CMP16rr
+ { 435, 1, 0, 0, "CMP32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #435 = CMP32i32
+ { 436, 6, 0, 0, "CMP32mi", 0|(1<<TID::MayLoad), 0|31|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #436 = CMP32mi
+ { 437, 6, 0, 0, "CMP32mi8", 0|(1<<TID::MayLoad), 0|31|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #437 = CMP32mi8
+ { 438, 6, 0, 0, "CMP32mr", 0|(1<<TID::MayLoad), 0|4|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #438 = CMP32mr
+ { 439, 2, 0, 0, "CMP32mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #439 = CMP32mrmrr
+ { 440, 2, 0, 0, "CMP32ri", 0, 0|23|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #440 = CMP32ri
+ { 441, 2, 0, 0, "CMP32ri8", 0, 0|23|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #441 = CMP32ri8
+ { 442, 6, 0, 0, "CMP32rm", 0|(1<<TID::MayLoad), 0|6|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #442 = CMP32rm
+ { 443, 2, 0, 0, "CMP32rr", 0, 0|3|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #443 = CMP32rr
+ { 444, 1, 0, 0, "CMP64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(61<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #444 = CMP64i32
+ { 445, 6, 0, 0, "CMP64mi32", 0|(1<<TID::MayLoad), 0|31|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #445 = CMP64mi32
+ { 446, 6, 0, 0, "CMP64mi8", 0|(1<<TID::MayLoad), 0|31|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #446 = CMP64mi8
+ { 447, 6, 0, 0, "CMP64mr", 0|(1<<TID::MayLoad), 0|4|(1<<12)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #447 = CMP64mr
+ { 448, 2, 0, 0, "CMP64mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #448 = CMP64mrmrr
+ { 449, 2, 0, 0, "CMP64ri32", 0, 0|23|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #449 = CMP64ri32
+ { 450, 2, 0, 0, "CMP64ri8", 0, 0|23|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #450 = CMP64ri8
+ { 451, 6, 0, 0, "CMP64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(59<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #451 = CMP64rm
+ { 452, 2, 0, 0, "CMP64rr", 0, 0|3|(1<<12)|(57<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #452 = CMP64rr
+ { 453, 1, 0, 0, "CMP8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(60<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #453 = CMP8i8
+ { 454, 6, 0, 0, "CMP8mi", 0|(1<<TID::MayLoad), 0|31|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #454 = CMP8mi
+ { 455, 6, 0, 0, "CMP8mr", 0|(1<<TID::MayLoad), 0|4|(56<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #455 = CMP8mr
+ { 456, 2, 0, 0, "CMP8mrmrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(58<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #456 = CMP8mrmrr
+ { 457, 2, 0, 0, "CMP8ri", 0, 0|23|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo68 }, // Inst #457 = CMP8ri
+ { 458, 6, 0, 0, "CMP8rm", 0|(1<<TID::MayLoad), 0|6|(58<<24), NULL, ImplicitList1, Barriers1, OperandInfo69 }, // Inst #458 = CMP8rm
+ { 459, 2, 0, 0, "CMP8rr", 0, 0|3|(56<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #459 = CMP8rr
+ { 460, 8, 1, 0, "CMPPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #460 = CMPPDrmi
+ { 461, 4, 1, 0, "CMPPDrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #461 = CMPPDrri
+ { 462, 8, 1, 0, "CMPPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #462 = CMPPSrmi
+ { 463, 4, 1, 0, "CMPPSrri", 0, 0|5|(1<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #463 = CMPPSrri
+ { 464, 0, 0, 0, "CMPS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(167<<24), NULL, NULL, NULL, 0 }, // Inst #464 = CMPS16
+ { 465, 0, 0, 0, "CMPS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(167<<24), NULL, NULL, NULL, 0 }, // Inst #465 = CMPS32
+ { 466, 0, 0, 0, "CMPS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(167<<24), NULL, NULL, NULL, 0 }, // Inst #466 = CMPS64
+ { 467, 0, 0, 0, "CMPS8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(166<<24), NULL, NULL, NULL, 0 }, // Inst #467 = CMPS8
+ { 468, 8, 1, 0, "CMPSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo70 }, // Inst #468 = CMPSDrm
+ { 469, 4, 1, 0, "CMPSDrr", 0, 0|5|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo71 }, // Inst #469 = CMPSDrr
+ { 470, 8, 1, 0, "CMPSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo72 }, // Inst #470 = CMPSSrm
+ { 471, 4, 1, 0, "CMPSSrr", 0, 0|5|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo73 }, // Inst #471 = CMPSSrr
+ { 472, 5, 0, 0, "CMPXCHG16B", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(1<<12)|(199<<24), ImplicitList16, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #472 = CMPXCHG16B
+ { 473, 6, 0, 0, "CMPXCHG16rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(177<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #473 = CMPXCHG16rm
+ { 474, 2, 1, 0, "CMPXCHG16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(177<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #474 = CMPXCHG16rr
+ { 475, 6, 0, 0, "CMPXCHG32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(177<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #475 = CMPXCHG32rm
+ { 476, 2, 1, 0, "CMPXCHG32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(177<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #476 = CMPXCHG32rr
+ { 477, 6, 0, 0, "CMPXCHG64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(177<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #477 = CMPXCHG64rm
+ { 478, 2, 1, 0, "CMPXCHG64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(177<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #478 = CMPXCHG64rr
+ { 479, 5, 0, 0, "CMPXCHG8B", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(199<<24), ImplicitList6, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #479 = CMPXCHG8B
+ { 480, 6, 0, 0, "CMPXCHG8rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(176<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #480 = CMPXCHG8rm
+ { 481, 2, 1, 0, "CMPXCHG8rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(176<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #481 = CMPXCHG8rr
+ { 482, 6, 0, 0, "COMISDrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(47<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #482 = COMISDrm
+ { 483, 2, 0, 0, "COMISDrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(47<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #483 = COMISDrr
+ { 484, 6, 0, 0, "COMISSrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #484 = COMISSrm
+ { 485, 2, 0, 0, "COMISSrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #485 = COMISSrr
+ { 486, 1, 0, 0, "COMP_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #486 = COMP_FST0r
+ { 487, 1, 0, 0, "COM_FIPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(10<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #487 = COM_FIPr
+ { 488, 1, 0, 0, "COM_FIr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #488 = COM_FIr
+ { 489, 1, 0, 0, "COM_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #489 = COM_FST0r
+ { 490, 0, 0, 0, "COS_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(255<<24), NULL, NULL, NULL, 0 }, // Inst #490 = COS_F
+ { 491, 2, 1, 0, "COS_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #491 = COS_Fp32
+ { 492, 2, 1, 0, "COS_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #492 = COS_Fp64
+ { 493, 2, 1, 0, "COS_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #493 = COS_Fp80
+ { 494, 0, 0, 0, "CPUID", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(162<<24), NULL, NULL, NULL, 0 }, // Inst #494 = CPUID
+ { 495, 0, 0, 0, "CQO", 0, 0|1|(1<<12)|(153<<24), ImplicitList15, ImplicitList19, NULL, 0 }, // Inst #495 = CQO
+ { 496, 7, 1, 0, "CRC32m16", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #496 = CRC32m16
+ { 497, 7, 1, 0, "CRC32m32", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #497 = CRC32m32
+ { 498, 7, 1, 0, "CRC32m8", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(240<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #498 = CRC32m8
+ { 499, 3, 1, 0, "CRC32r16", 0, 0|5|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo77 }, // Inst #499 = CRC32r16
+ { 500, 3, 1, 0, "CRC32r32", 0, 0|5|(1<<6)|(15<<8)|(241<<24), NULL, NULL, NULL, OperandInfo14 }, // Inst #500 = CRC32r32
+ { 501, 3, 1, 0, "CRC32r8", 0, 0|5|(1<<6)|(15<<8)|(240<<24), NULL, NULL, NULL, OperandInfo78 }, // Inst #501 = CRC32r8
+ { 502, 7, 1, 0, "CRC64m64", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(15<<8)|(1<<12)|(240<<24), NULL, NULL, NULL, OperandInfo17 }, // Inst #502 = CRC64m64
+ { 503, 3, 1, 0, "CRC64r64", 0, 0|5|(1<<6)|(15<<8)|(1<<12)|(240<<24), NULL, NULL, NULL, OperandInfo18 }, // Inst #503 = CRC64r64
+ { 504, 6, 1, 0, "CVTDQ2PDrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #504 = CVTDQ2PDrm
+ { 505, 2, 1, 0, "CVTDQ2PDrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #505 = CVTDQ2PDrr
+ { 506, 6, 1, 0, "CVTDQ2PSrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #506 = CVTDQ2PSrm
+ { 507, 2, 1, 0, "CVTDQ2PSrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #507 = CVTDQ2PSrr
+ { 508, 6, 1, 0, "CVTPD2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #508 = CVTPD2DQrm
+ { 509, 2, 1, 0, "CVTPD2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #509 = CVTPD2DQrr
+ { 510, 6, 1, 0, "CVTPD2PSrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #510 = CVTPD2PSrm
+ { 511, 2, 1, 0, "CVTPD2PSrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #511 = CVTPD2PSrr
+ { 512, 6, 1, 0, "CVTPS2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #512 = CVTPS2DQrm
+ { 513, 2, 1, 0, "CVTPS2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #513 = CVTPS2DQrr
+ { 514, 6, 1, 0, "CVTPS2PDrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #514 = CVTPS2PDrm
+ { 515, 2, 1, 0, "CVTPS2PDrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #515 = CVTPS2PDrr
+ { 516, 6, 1, 0, "CVTSD2SI64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #516 = CVTSD2SI64rm
+ { 517, 2, 1, 0, "CVTSD2SI64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #517 = CVTSD2SI64rr
+ { 518, 6, 1, 0, "CVTSD2SSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #518 = CVTSD2SSrm
+ { 519, 2, 1, 0, "CVTSD2SSrr", 0, 0|5|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo81 }, // Inst #519 = CVTSD2SSrr
+ { 520, 6, 1, 0, "CVTSI2SD64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #520 = CVTSI2SD64rm
+ { 521, 2, 1, 0, "CVTSI2SD64rr", 0, 0|5|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo83 }, // Inst #521 = CVTSI2SD64rr
+ { 522, 6, 1, 0, "CVTSI2SDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #522 = CVTSI2SDrm
+ { 523, 2, 1, 0, "CVTSI2SDrr", 0, 0|5|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo84 }, // Inst #523 = CVTSI2SDrr
+ { 524, 6, 1, 0, "CVTSI2SS64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #524 = CVTSI2SS64rm
+ { 525, 2, 1, 0, "CVTSI2SS64rr", 0, 0|5|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo85 }, // Inst #525 = CVTSI2SS64rr
+ { 526, 6, 1, 0, "CVTSI2SSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #526 = CVTSI2SSrm
+ { 527, 2, 1, 0, "CVTSI2SSrr", 0, 0|5|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo86 }, // Inst #527 = CVTSI2SSrr
+ { 528, 6, 1, 0, "CVTSS2SDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #528 = CVTSS2SDrm
+ { 529, 2, 1, 0, "CVTSS2SDrr", 0, 0|5|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo87 }, // Inst #529 = CVTSS2SDrr
+ { 530, 6, 1, 0, "CVTSS2SI64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #530 = CVTSS2SI64rm
+ { 531, 2, 1, 0, "CVTSS2SI64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo88 }, // Inst #531 = CVTSS2SI64rr
+ { 532, 6, 1, 0, "CVTSS2SIrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #532 = CVTSS2SIrm
+ { 533, 2, 1, 0, "CVTSS2SIrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #533 = CVTSS2SIrr
+ { 534, 6, 1, 0, "CVTTPS2DQrm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #534 = CVTTPS2DQrm
+ { 535, 2, 1, 0, "CVTTPS2DQrr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #535 = CVTTPS2DQrr
+ { 536, 6, 1, 0, "CVTTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #536 = CVTTSD2SI64rm
+ { 537, 2, 1, 0, "CVTTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #537 = CVTTSD2SI64rr
+ { 538, 6, 1, 0, "CVTTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #538 = CVTTSD2SIrm
+ { 539, 2, 1, 0, "CVTTSD2SIrr", 0, 0|5|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo90 }, // Inst #539 = CVTTSD2SIrr
+ { 540, 6, 1, 0, "CVTTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #540 = CVTTSS2SI64rm
+ { 541, 2, 1, 0, "CVTTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo88 }, // Inst #541 = CVTTSS2SI64rr
+ { 542, 6, 1, 0, "CVTTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #542 = CVTTSS2SIrm
+ { 543, 2, 1, 0, "CVTTSS2SIrr", 0, 0|5|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #543 = CVTTSS2SIrr
+ { 544, 0, 0, 0, "CWD", 0, 0|1|(1<<6)|(153<<24), ImplicitList12, ImplicitList20, NULL, 0 }, // Inst #544 = CWD
+ { 545, 0, 0, 0, "CWDE", 0, 0|1|(152<<24), ImplicitList12, ImplicitList13, NULL, 0 }, // Inst #545 = CWDE
+ { 546, 5, 0, 0, "DEC16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #546 = DEC16m
+ { 547, 2, 1, 0, "DEC16r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(1<<6)|(72<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #547 = DEC16r
+ { 548, 5, 0, 0, "DEC32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #548 = DEC32m
+ { 549, 2, 1, 0, "DEC32r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(72<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #549 = DEC32r
+ { 550, 5, 0, 0, "DEC64_16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #550 = DEC64_16m
+ { 551, 2, 1, 0, "DEC64_16r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #551 = DEC64_16r
+ { 552, 5, 0, 0, "DEC64_32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #552 = DEC64_32m
+ { 553, 2, 1, 0, "DEC64_32r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #553 = DEC64_32r
+ { 554, 5, 0, 0, "DEC64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #554 = DEC64m
+ { 555, 2, 1, 0, "DEC64r", 0|(1<<TID::ConvertibleTo3Addr), 0|17|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #555 = DEC64r
+ { 556, 5, 0, 0, "DEC8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #556 = DEC8m
+ { 557, 2, 1, 0, "DEC8r", 0, 0|17|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #557 = DEC8r
+ { 558, 5, 0, 0, "DIV16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(247<<24), ImplicitList20, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #558 = DIV16m
+ { 559, 1, 0, 0, "DIV16r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<6)|(247<<24), ImplicitList20, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #559 = DIV16r
+ { 560, 5, 0, 0, "DIV32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(247<<24), ImplicitList14, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #560 = DIV32m
+ { 561, 1, 0, 0, "DIV32r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(247<<24), ImplicitList14, ImplicitList18, Barriers6, OperandInfo57 }, // Inst #561 = DIV32r
+ { 562, 5, 0, 0, "DIV64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(1<<12)|(247<<24), ImplicitList19, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #562 = DIV64m
+ { 563, 1, 0, 0, "DIV64r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<12)|(247<<24), ImplicitList19, ImplicitList17, Barriers1, OperandInfo58 }, // Inst #563 = DIV64r
+ { 564, 5, 0, 0, "DIV8m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(246<<24), ImplicitList12, ImplicitList22, Barriers1, OperandInfo30 }, // Inst #564 = DIV8m
+ { 565, 1, 0, 0, "DIV8r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(246<<24), ImplicitList12, ImplicitList22, Barriers1, OperandInfo94 }, // Inst #565 = DIV8r
+ { 566, 7, 1, 0, "DIVPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #566 = DIVPDrm
+ { 567, 3, 1, 0, "DIVPDrr", 0, 0|5|(1<<6)|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #567 = DIVPDrr
+ { 568, 7, 1, 0, "DIVPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #568 = DIVPSrm
+ { 569, 3, 1, 0, "DIVPSrr", 0, 0|5|(1<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #569 = DIVPSrr
+ { 570, 5, 0, 0, "DIVR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #570 = DIVR_F32m
+ { 571, 5, 0, 0, "DIVR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #571 = DIVR_F64m
+ { 572, 5, 0, 0, "DIVR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #572 = DIVR_FI16m
+ { 573, 5, 0, 0, "DIVR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #573 = DIVR_FI32m
+ { 574, 1, 0, 0, "DIVR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #574 = DIVR_FPrST0
+ { 575, 1, 0, 0, "DIVR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(248<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #575 = DIVR_FST0r
+ { 576, 7, 1, 0, "DIVR_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #576 = DIVR_Fp32m
+ { 577, 7, 1, 0, "DIVR_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #577 = DIVR_Fp64m
+ { 578, 7, 1, 0, "DIVR_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #578 = DIVR_Fp64m32
+ { 579, 7, 1, 0, "DIVR_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #579 = DIVR_Fp80m32
+ { 580, 7, 1, 0, "DIVR_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #580 = DIVR_Fp80m64
+ { 581, 7, 1, 0, "DIVR_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #581 = DIVR_FpI16m32
+ { 582, 7, 1, 0, "DIVR_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #582 = DIVR_FpI16m64
+ { 583, 7, 1, 0, "DIVR_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #583 = DIVR_FpI16m80
+ { 584, 7, 1, 0, "DIVR_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #584 = DIVR_FpI32m32
+ { 585, 7, 1, 0, "DIVR_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #585 = DIVR_FpI32m64
+ { 586, 7, 1, 0, "DIVR_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #586 = DIVR_FpI32m80
+ { 587, 1, 0, 0, "DIVR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #587 = DIVR_FrST0
+ { 588, 7, 1, 0, "DIVSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #588 = DIVSDrm
+ { 589, 7, 1, 0, "DIVSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #589 = DIVSDrm_Int
+ { 590, 3, 1, 0, "DIVSDrr", 0, 0|5|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #590 = DIVSDrr
+ { 591, 3, 1, 0, "DIVSDrr_Int", 0, 0|5|(11<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #591 = DIVSDrr_Int
+ { 592, 7, 1, 0, "DIVSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #592 = DIVSSrm
+ { 593, 7, 1, 0, "DIVSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #593 = DIVSSrm_Int
+ { 594, 3, 1, 0, "DIVSSrr", 0, 0|5|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #594 = DIVSSrr
+ { 595, 3, 1, 0, "DIVSSrr_Int", 0, 0|5|(12<<8)|(94<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #595 = DIVSSrr_Int
+ { 596, 5, 0, 0, "DIV_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #596 = DIV_F32m
+ { 597, 5, 0, 0, "DIV_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #597 = DIV_F64m
+ { 598, 5, 0, 0, "DIV_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #598 = DIV_FI16m
+ { 599, 5, 0, 0, "DIV_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|30|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #599 = DIV_FI32m
+ { 600, 1, 0, 0, "DIV_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(248<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #600 = DIV_FPrST0
+ { 601, 1, 0, 0, "DIV_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(240<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #601 = DIV_FST0r
+ { 602, 3, 1, 0, "DIV_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #602 = DIV_Fp32
+ { 603, 7, 1, 0, "DIV_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #603 = DIV_Fp32m
+ { 604, 3, 1, 0, "DIV_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #604 = DIV_Fp64
+ { 605, 7, 1, 0, "DIV_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #605 = DIV_Fp64m
+ { 606, 7, 1, 0, "DIV_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #606 = DIV_Fp64m32
+ { 607, 3, 1, 0, "DIV_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #607 = DIV_Fp80
+ { 608, 7, 1, 0, "DIV_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #608 = DIV_Fp80m32
+ { 609, 7, 1, 0, "DIV_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #609 = DIV_Fp80m64
+ { 610, 7, 1, 0, "DIV_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #610 = DIV_FpI16m32
+ { 611, 7, 1, 0, "DIV_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #611 = DIV_FpI16m64
+ { 612, 7, 1, 0, "DIV_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #612 = DIV_FpI16m80
+ { 613, 7, 1, 0, "DIV_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #613 = DIV_FpI32m32
+ { 614, 7, 1, 0, "DIV_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #614 = DIV_FpI32m64
+ { 615, 7, 1, 0, "DIV_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #615 = DIV_FpI32m80
+ { 616, 1, 0, 0, "DIV_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(248<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #616 = DIV_FrST0
+ { 617, 8, 1, 0, "DPPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(65<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #617 = DPPDrmi
+ { 618, 4, 1, 0, "DPPDrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(65<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #618 = DPPDrri
+ { 619, 8, 1, 0, "DPPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(64<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #619 = DPPSrmi
+ { 620, 4, 1, 0, "DPPSrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(64<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #620 = DPPSrri
+ { 621, 1, 0, 0, "EH_RETURN", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(195<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #621 = EH_RETURN
+ { 622, 1, 0, 0, "EH_RETURN64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(195<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #622 = EH_RETURN64
+ { 623, 2, 0, 0, "ENTER", 0|(1<<TID::UnmodeledSideEffects), 0|1|(200<<24), NULL, NULL, NULL, OperandInfo38 }, // Inst #623 = ENTER
+ { 624, 7, 0, 0, "EXTRACTPSmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<13)|(23<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #624 = EXTRACTPSmr
+ { 625, 3, 1, 0, "EXTRACTPSrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(23<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #625 = EXTRACTPSrr
+ { 626, 0, 0, 0, "F2XM1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(240<<24), NULL, NULL, NULL, 0 }, // Inst #626 = F2XM1
+ { 627, 2, 0, 0, "FARCALL16i", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(154<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo38 }, // Inst #627 = FARCALL16i
+ { 628, 5, 0, 0, "FARCALL16m", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo30 }, // Inst #628 = FARCALL16m
+ { 629, 2, 0, 0, "FARCALL32i", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|1|(154<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo38 }, // Inst #629 = FARCALL32i
+ { 630, 5, 0, 0, "FARCALL32m", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(255<<24), ImplicitList2, ImplicitList9, Barriers3, OperandInfo30 }, // Inst #630 = FARCALL32m
+ { 631, 5, 0, 0, "FARCALL64", 0|(1<<TID::Call)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(255<<24), ImplicitList4, ImplicitList10, Barriers4, OperandInfo30 }, // Inst #631 = FARCALL64
+ { 632, 2, 0, 0, "FARJMP16i", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(234<<24), NULL, NULL, NULL, OperandInfo38 }, // Inst #632 = FARJMP16i
+ { 633, 5, 0, 0, "FARJMP16m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #633 = FARJMP16m
+ { 634, 2, 0, 0, "FARJMP32i", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(234<<24), NULL, NULL, NULL, OperandInfo38 }, // Inst #634 = FARJMP32i
+ { 635, 5, 0, 0, "FARJMP32m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #635 = FARJMP32m
+ { 636, 5, 0, 0, "FARJMP64", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #636 = FARJMP64
+ { 637, 5, 0, 0, "FBLDm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #637 = FBLDm
+ { 638, 5, 1, 0, "FBSTPm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #638 = FBSTPm
+ { 639, 5, 0, 0, "FCOM32m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #639 = FCOM32m
+ { 640, 5, 0, 0, "FCOM64m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #640 = FCOM64m
+ { 641, 5, 0, 0, "FCOMP32m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #641 = FCOMP32m
+ { 642, 5, 0, 0, "FCOMP64m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #642 = FCOMP64m
+ { 643, 0, 0, 0, "FCOMPP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(9<<8)|(217<<24), NULL, NULL, NULL, 0 }, // Inst #643 = FCOMPP
+ { 644, 0, 0, 0, "FDECSTP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(246<<24), NULL, NULL, NULL, 0 }, // Inst #644 = FDECSTP
+ { 645, 1, 0, 0, "FFREE", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #645 = FFREE
+ { 646, 5, 0, 0, "FICOM16m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #646 = FICOM16m
+ { 647, 5, 0, 0, "FICOM32m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #647 = FICOM32m
+ { 648, 5, 0, 0, "FICOMP16m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #648 = FICOMP16m
+ { 649, 5, 0, 0, "FICOMP32m", 0|(1<<TID::UnmodeledSideEffects), 0|27|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #649 = FICOMP32m
+ { 650, 0, 0, 0, "FINCSTP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(247<<24), NULL, NULL, NULL, 0 }, // Inst #650 = FINCSTP
+ { 651, 5, 1, 0, "FISTTP32m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #651 = FISTTP32m
+ { 652, 5, 0, 0, "FLDCW16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #652 = FLDCW16m
+ { 653, 5, 0, 0, "FLDENVm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #653 = FLDENVm
+ { 654, 0, 0, 0, "FLDL2E", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(234<<24), NULL, NULL, NULL, 0 }, // Inst #654 = FLDL2E
+ { 655, 0, 0, 0, "FLDL2T", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(233<<24), NULL, NULL, NULL, 0 }, // Inst #655 = FLDL2T
+ { 656, 0, 0, 0, "FLDLG2", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(236<<24), NULL, NULL, NULL, 0 }, // Inst #656 = FLDLG2
+ { 657, 0, 0, 0, "FLDLN2", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(237<<24), NULL, NULL, NULL, 0 }, // Inst #657 = FLDLN2
+ { 658, 0, 0, 0, "FLDPI", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(235<<24), NULL, NULL, NULL, 0 }, // Inst #658 = FLDPI
+ { 659, 0, 0, 0, "FNCLEX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(6<<8)|(226<<24), NULL, NULL, NULL, 0 }, // Inst #659 = FNCLEX
+ { 660, 0, 0, 0, "FNINIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(6<<8)|(227<<24), NULL, NULL, NULL, 0 }, // Inst #660 = FNINIT
+ { 661, 0, 0, 0, "FNOP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(208<<24), NULL, NULL, NULL, 0 }, // Inst #661 = FNOP
+ { 662, 5, 0, 0, "FNSTCW16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #662 = FNSTCW16m
+ { 663, 0, 0, 0, "FNSTSW8r", 0|(1<<TID::UnmodeledSideEffects), 0|1|(10<<8)|(224<<24), NULL, ImplicitList12, NULL, 0 }, // Inst #663 = FNSTSW8r
+ { 664, 5, 1, 0, "FNSTSWm", 0|(1<<TID::UnmodeledSideEffects), 0|31|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #664 = FNSTSWm
+ { 665, 6, 0, 0, "FP32_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #665 = FP32_TO_INT16_IN_MEM
+ { 666, 6, 0, 0, "FP32_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #666 = FP32_TO_INT32_IN_MEM
+ { 667, 6, 0, 0, "FP32_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo97 }, // Inst #667 = FP32_TO_INT64_IN_MEM
+ { 668, 6, 0, 0, "FP64_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #668 = FP64_TO_INT16_IN_MEM
+ { 669, 6, 0, 0, "FP64_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #669 = FP64_TO_INT32_IN_MEM
+ { 670, 6, 0, 0, "FP64_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo98 }, // Inst #670 = FP64_TO_INT64_IN_MEM
+ { 671, 6, 0, 0, "FP80_TO_INT16_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo99 }, // Inst #671 = FP80_TO_INT16_IN_MEM
+ { 672, 6, 0, 0, "FP80_TO_INT32_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo99 }, // Inst #672 = FP80_TO_INT32_IN_MEM
+ { 673, 6, 0, 0, "FP80_TO_INT64_IN_MEM", 0|(1<<TID::MayStore)|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, OperandInfo99 }, // Inst #673 = FP80_TO_INT64_IN_MEM
+ { 674, 0, 0, 0, "FPATAN", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(243<<24), NULL, NULL, NULL, 0 }, // Inst #674 = FPATAN
+ { 675, 0, 0, 0, "FPREM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(248<<24), NULL, NULL, NULL, 0 }, // Inst #675 = FPREM
+ { 676, 0, 0, 0, "FPREM1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(245<<24), NULL, NULL, NULL, 0 }, // Inst #676 = FPREM1
+ { 677, 0, 0, 0, "FPTAN", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(242<<24), NULL, NULL, NULL, 0 }, // Inst #677 = FPTAN
+ { 678, 0, 0, 0, "FP_REG_KILL", 0|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0, NULL, ImplicitList23, Barriers7, 0 }, // Inst #678 = FP_REG_KILL
+ { 679, 0, 0, 0, "FRNDINT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(252<<24), NULL, NULL, NULL, 0 }, // Inst #679 = FRNDINT
+ { 680, 5, 1, 0, "FRSTORm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #680 = FRSTORm
+ { 681, 5, 1, 0, "FSAVEm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #681 = FSAVEm
+ { 682, 0, 0, 0, "FSCALE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(253<<24), NULL, NULL, NULL, 0 }, // Inst #682 = FSCALE
+ { 683, 0, 0, 0, "FSINCOS", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(251<<24), NULL, NULL, NULL, 0 }, // Inst #683 = FSINCOS
+ { 684, 5, 1, 0, "FSTENVm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #684 = FSTENVm
+ { 685, 6, 1, 0, "FS_MOV32rm", 0|(1<<TID::MayLoad), 0|6|(1<<20)|(139<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #685 = FS_MOV32rm
+ { 686, 0, 0, 0, "FXAM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(229<<24), NULL, NULL, NULL, 0 }, // Inst #686 = FXAM
+ { 687, 5, 0, 0, "FXRSTOR", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #687 = FXRSTOR
+ { 688, 5, 1, 0, "FXSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #688 = FXSAVE
+ { 689, 0, 0, 0, "FXTRACT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(244<<24), NULL, NULL, NULL, 0 }, // Inst #689 = FXTRACT
+ { 690, 0, 0, 0, "FYL2X", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(241<<24), NULL, NULL, NULL, 0 }, // Inst #690 = FYL2X
+ { 691, 0, 0, 0, "FYL2XP1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(249<<24), NULL, NULL, NULL, 0 }, // Inst #691 = FYL2XP1
+ { 692, 1, 1, 0, "FpGET_ST0_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #692 = FpGET_ST0_32
+ { 693, 1, 1, 0, "FpGET_ST0_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #693 = FpGET_ST0_64
+ { 694, 1, 1, 0, "FpGET_ST0_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #694 = FpGET_ST0_80
+ { 695, 1, 1, 0, "FpGET_ST1_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #695 = FpGET_ST1_32
+ { 696, 1, 1, 0, "FpGET_ST1_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #696 = FpGET_ST1_64
+ { 697, 1, 1, 0, "FpGET_ST1_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #697 = FpGET_ST1_80
+ { 698, 1, 0, 0, "FpSET_ST0_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo100 }, // Inst #698 = FpSET_ST0_32
+ { 699, 1, 0, 0, "FpSET_ST0_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo101 }, // Inst #699 = FpSET_ST0_64
+ { 700, 1, 0, 0, "FpSET_ST0_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList24, NULL, OperandInfo102 }, // Inst #700 = FpSET_ST0_80
+ { 701, 1, 0, 0, "FpSET_ST1_32", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList25, NULL, OperandInfo100 }, // Inst #701 = FpSET_ST1_32
+ { 702, 1, 0, 0, "FpSET_ST1_64", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList25, NULL, OperandInfo101 }, // Inst #702 = FpSET_ST1_64
+ { 703, 1, 0, 0, "FpSET_ST1_80", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<16), NULL, ImplicitList25, NULL, OperandInfo102 }, // Inst #703 = FpSET_ST1_80
+ { 704, 7, 1, 0, "FsANDNPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #704 = FsANDNPDrm
+ { 705, 3, 1, 0, "FsANDNPDrr", 0, 0|5|(1<<6)|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #705 = FsANDNPDrr
+ { 706, 7, 1, 0, "FsANDNPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #706 = FsANDNPSrm
+ { 707, 3, 1, 0, "FsANDNPSrr", 0, 0|5|(1<<8)|(85<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #707 = FsANDNPSrr
+ { 708, 7, 1, 0, "FsANDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #708 = FsANDPDrm
+ { 709, 3, 1, 0, "FsANDPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #709 = FsANDPDrr
+ { 710, 7, 1, 0, "FsANDPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #710 = FsANDPSrm
+ { 711, 3, 1, 0, "FsANDPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(84<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #711 = FsANDPSrr
+ { 712, 1, 1, 0, "FsFLD0SD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo103 }, // Inst #712 = FsFLD0SD
+ { 713, 1, 1, 0, "FsFLD0SS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo104 }, // Inst #713 = FsFLD0SS
+ { 714, 6, 1, 0, "FsMOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #714 = FsMOVAPDrm
+ { 715, 2, 1, 0, "FsMOVAPDrr", 0, 0|5|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #715 = FsMOVAPDrr
+ { 716, 6, 1, 0, "FsMOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #716 = FsMOVAPSrm
+ { 717, 2, 1, 0, "FsMOVAPSrr", 0, 0|5|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #717 = FsMOVAPSrr
+ { 718, 7, 1, 0, "FsORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #718 = FsORPDrm
+ { 719, 3, 1, 0, "FsORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #719 = FsORPDrr
+ { 720, 7, 1, 0, "FsORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #720 = FsORPSrm
+ { 721, 3, 1, 0, "FsORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #721 = FsORPSrr
+ { 722, 7, 1, 0, "FsXORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #722 = FsXORPDrm
+ { 723, 3, 1, 0, "FsXORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #723 = FsXORPDrr
+ { 724, 7, 1, 0, "FsXORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #724 = FsXORPSrm
+ { 725, 3, 1, 0, "FsXORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #725 = FsXORPSrr
+ { 726, 6, 1, 0, "GS_MOV32rm", 0|(1<<TID::MayLoad), 0|6|(2<<20)|(139<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #726 = GS_MOV32rm
+ { 727, 7, 1, 0, "HADDPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(124<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #727 = HADDPDrm
+ { 728, 3, 1, 0, "HADDPDrr", 0, 0|5|(1<<6)|(1<<8)|(124<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #728 = HADDPDrr
+ { 729, 7, 1, 0, "HADDPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(124<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #729 = HADDPSrm
+ { 730, 3, 1, 0, "HADDPSrr", 0, 0|5|(11<<8)|(124<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #730 = HADDPSrr
+ { 731, 0, 0, 0, "HLT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(244<<24), NULL, NULL, NULL, 0 }, // Inst #731 = HLT
+ { 732, 7, 1, 0, "HSUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(125<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #732 = HSUBPDrm
+ { 733, 3, 1, 0, "HSUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(125<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #733 = HSUBPDrr
+ { 734, 7, 1, 0, "HSUBPSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(125<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #734 = HSUBPSrm
+ { 735, 3, 1, 0, "HSUBPSrr", 0, 0|5|(11<<8)|(125<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #735 = HSUBPSrr
+ { 736, 5, 0, 0, "IDIV16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<6)|(247<<24), ImplicitList20, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #736 = IDIV16m
+ { 737, 1, 0, 0, "IDIV16r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<6)|(247<<24), ImplicitList20, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #737 = IDIV16r
+ { 738, 5, 0, 0, "IDIV32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(247<<24), ImplicitList14, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #738 = IDIV32m
+ { 739, 1, 0, 0, "IDIV32r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(247<<24), ImplicitList14, ImplicitList18, Barriers6, OperandInfo57 }, // Inst #739 = IDIV32r
+ { 740, 5, 0, 0, "IDIV64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(1<<12)|(247<<24), ImplicitList19, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #740 = IDIV64m
+ { 741, 1, 0, 0, "IDIV64r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(1<<12)|(247<<24), ImplicitList19, ImplicitList17, Barriers1, OperandInfo58 }, // Inst #741 = IDIV64r
+ { 742, 5, 0, 0, "IDIV8m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|31|(246<<24), ImplicitList12, ImplicitList22, Barriers1, OperandInfo30 }, // Inst #742 = IDIV8m
+ { 743, 1, 0, 0, "IDIV8r", 0|(1<<TID::UnmodeledSideEffects), 0|23|(246<<24), ImplicitList12, ImplicitList22, Barriers1, OperandInfo94 }, // Inst #743 = IDIV8r
+ { 744, 5, 0, 0, "ILD_F16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #744 = ILD_F16m
+ { 745, 5, 0, 0, "ILD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #745 = ILD_F32m
+ { 746, 5, 0, 0, "ILD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #746 = ILD_F64m
+ { 747, 6, 1, 0, "ILD_Fp16m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #747 = ILD_Fp16m32
+ { 748, 6, 1, 0, "ILD_Fp16m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #748 = ILD_Fp16m64
+ { 749, 6, 1, 0, "ILD_Fp16m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #749 = ILD_Fp16m80
+ { 750, 6, 1, 0, "ILD_Fp32m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #750 = ILD_Fp32m32
+ { 751, 6, 1, 0, "ILD_Fp32m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #751 = ILD_Fp32m64
+ { 752, 6, 1, 0, "ILD_Fp32m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #752 = ILD_Fp32m80
+ { 753, 6, 1, 0, "ILD_Fp64m32", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #753 = ILD_Fp64m32
+ { 754, 6, 1, 0, "ILD_Fp64m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #754 = ILD_Fp64m64
+ { 755, 6, 1, 0, "ILD_Fp64m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #755 = ILD_Fp64m80
+ { 756, 5, 0, 0, "IMUL16m", 0|(1<<TID::MayLoad), 0|29|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #756 = IMUL16m
+ { 757, 1, 0, 0, "IMUL16r", 0, 0|21|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #757 = IMUL16r
+ { 758, 7, 1, 0, "IMUL16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #758 = IMUL16rm
+ { 759, 7, 1, 0, "IMUL16rmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(2<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo110 }, // Inst #759 = IMUL16rmi
+ { 760, 7, 1, 0, "IMUL16rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo110 }, // Inst #760 = IMUL16rmi8
+ { 761, 3, 1, 0, "IMUL16rr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #761 = IMUL16rr
+ { 762, 3, 1, 0, "IMUL16rri", 0, 0|5|(1<<6)|(2<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo111 }, // Inst #762 = IMUL16rri
+ { 763, 3, 1, 0, "IMUL16rri8", 0, 0|5|(1<<6)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo111 }, // Inst #763 = IMUL16rri8
+ { 764, 5, 0, 0, "IMUL32m", 0|(1<<TID::MayLoad), 0|29|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #764 = IMUL32m
+ { 765, 1, 0, 0, "IMUL32r", 0, 0|21|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo57 }, // Inst #765 = IMUL32r
+ { 766, 7, 1, 0, "IMUL32rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #766 = IMUL32rm
+ { 767, 7, 1, 0, "IMUL32rmi", 0|(1<<TID::MayLoad), 0|6|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo112 }, // Inst #767 = IMUL32rmi
+ { 768, 7, 1, 0, "IMUL32rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo112 }, // Inst #768 = IMUL32rmi8
+ { 769, 3, 1, 0, "IMUL32rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #769 = IMUL32rr
+ { 770, 3, 1, 0, "IMUL32rri", 0, 0|5|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo113 }, // Inst #770 = IMUL32rri
+ { 771, 3, 1, 0, "IMUL32rri8", 0, 0|5|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo113 }, // Inst #771 = IMUL32rri8
+ { 772, 5, 0, 0, "IMUL64m", 0|(1<<TID::MayLoad), 0|29|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #772 = IMUL64m
+ { 773, 1, 0, 0, "IMUL64r", 0, 0|21|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo58 }, // Inst #773 = IMUL64r
+ { 774, 7, 1, 0, "IMUL64rm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #774 = IMUL64rm
+ { 775, 7, 1, 0, "IMUL64rmi32", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo114 }, // Inst #775 = IMUL64rmi32
+ { 776, 7, 1, 0, "IMUL64rmi8", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo114 }, // Inst #776 = IMUL64rmi8
+ { 777, 3, 1, 0, "IMUL64rr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(1<<12)|(175<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #777 = IMUL64rr
+ { 778, 3, 1, 0, "IMUL64rri32", 0, 0|5|(1<<12)|(3<<13)|(105<<24), NULL, ImplicitList1, Barriers1, OperandInfo115 }, // Inst #778 = IMUL64rri32
+ { 779, 3, 1, 0, "IMUL64rri8", 0, 0|5|(1<<12)|(1<<13)|(107<<24), NULL, ImplicitList1, Barriers1, OperandInfo115 }, // Inst #779 = IMUL64rri8
+ { 780, 5, 0, 0, "IMUL8m", 0|(1<<TID::MayLoad), 0|29|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo30 }, // Inst #780 = IMUL8m
+ { 781, 1, 0, 0, "IMUL8r", 0, 0|21|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo94 }, // Inst #781 = IMUL8r
+ { 782, 0, 0, 0, "IN16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(109<<24), NULL, NULL, NULL, 0 }, // Inst #782 = IN16
+ { 783, 1, 0, 0, "IN16ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<13)|(229<<24), NULL, ImplicitList12, NULL, OperandInfo5 }, // Inst #783 = IN16ri
+ { 784, 0, 0, 0, "IN16rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(237<<24), ImplicitList26, ImplicitList12, NULL, 0 }, // Inst #784 = IN16rr
+ { 785, 0, 0, 0, "IN32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(109<<24), NULL, NULL, NULL, 0 }, // Inst #785 = IN32
+ { 786, 1, 0, 0, "IN32ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(229<<24), NULL, ImplicitList13, NULL, OperandInfo5 }, // Inst #786 = IN32ri
+ { 787, 0, 0, 0, "IN32rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(237<<24), ImplicitList26, ImplicitList13, NULL, 0 }, // Inst #787 = IN32rr
+ { 788, 0, 0, 0, "IN8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(108<<24), NULL, NULL, NULL, 0 }, // Inst #788 = IN8
+ { 789, 1, 0, 0, "IN8ri", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(228<<24), NULL, ImplicitList11, NULL, OperandInfo5 }, // Inst #789 = IN8ri
+ { 790, 0, 0, 0, "IN8rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(236<<24), ImplicitList26, ImplicitList11, NULL, 0 }, // Inst #790 = IN8rr
+ { 791, 5, 0, 0, "INC16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #791 = INC16m
+ { 792, 2, 1, 0, "INC16r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(1<<6)|(64<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #792 = INC16r
+ { 793, 5, 0, 0, "INC32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #793 = INC32m
+ { 794, 2, 1, 0, "INC32r", 0|(1<<TID::ConvertibleTo3Addr), 0|2|(64<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #794 = INC32r
+ { 795, 5, 0, 0, "INC64_16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #795 = INC64_16m
+ { 796, 2, 1, 0, "INC64_16r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<6)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #796 = INC64_16r
+ { 797, 5, 0, 0, "INC64_32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #797 = INC64_32m
+ { 798, 2, 1, 0, "INC64_32r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #798 = INC64_32r
+ { 799, 5, 0, 0, "INC64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #799 = INC64m
+ { 800, 2, 1, 0, "INC64r", 0|(1<<TID::ConvertibleTo3Addr), 0|16|(1<<12)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #800 = INC64r
+ { 801, 5, 0, 0, "INC8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #801 = INC8m
+ { 802, 2, 1, 0, "INC8r", 0, 0|16|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #802 = INC8r
+ { 803, 8, 1, 0, "INSERTPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(33<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #803 = INSERTPSrm
+ { 804, 4, 1, 0, "INSERTPSrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(33<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #804 = INSERTPSrr
+ { 805, 1, 0, 0, "INT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(205<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #805 = INT
+ { 806, 0, 0, 0, "INT3", 0|(1<<TID::UnmodeledSideEffects), 0|1|(204<<24), NULL, NULL, NULL, 0 }, // Inst #806 = INT3
+ { 807, 0, 0, 0, "INVD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(8<<24), NULL, NULL, NULL, 0 }, // Inst #807 = INVD
+ { 808, 0, 0, 0, "INVEPT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(56<<24), NULL, NULL, NULL, 0 }, // Inst #808 = INVEPT
+ { 809, 0, 0, 0, "INVLPG", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #809 = INVLPG
+ { 810, 0, 0, 0, "INVVPID", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(56<<24), NULL, NULL, NULL, 0 }, // Inst #810 = INVVPID
+ { 811, 0, 0, 0, "IRET16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(207<<24), NULL, NULL, NULL, 0 }, // Inst #811 = IRET16
+ { 812, 0, 0, 0, "IRET32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(207<<24), NULL, NULL, NULL, 0 }, // Inst #812 = IRET32
+ { 813, 0, 0, 0, "IRET64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(207<<24), NULL, NULL, NULL, 0 }, // Inst #813 = IRET64
+ { 814, 5, 0, 0, "ISTT_FP16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #814 = ISTT_FP16m
+ { 815, 5, 0, 0, "ISTT_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #815 = ISTT_FP32m
+ { 816, 5, 0, 0, "ISTT_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|25|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #816 = ISTT_FP64m
+ { 817, 6, 0, 0, "ISTT_Fp16m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #817 = ISTT_Fp16m32
+ { 818, 6, 0, 0, "ISTT_Fp16m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #818 = ISTT_Fp16m64
+ { 819, 6, 0, 0, "ISTT_Fp16m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #819 = ISTT_Fp16m80
+ { 820, 6, 0, 0, "ISTT_Fp32m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #820 = ISTT_Fp32m32
+ { 821, 6, 0, 0, "ISTT_Fp32m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #821 = ISTT_Fp32m64
+ { 822, 6, 0, 0, "ISTT_Fp32m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #822 = ISTT_Fp32m80
+ { 823, 6, 0, 0, "ISTT_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #823 = ISTT_Fp64m32
+ { 824, 6, 0, 0, "ISTT_Fp64m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #824 = ISTT_Fp64m64
+ { 825, 6, 0, 0, "ISTT_Fp64m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #825 = ISTT_Fp64m80
+ { 826, 5, 0, 0, "IST_F16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #826 = IST_F16m
+ { 827, 5, 0, 0, "IST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #827 = IST_F32m
+ { 828, 5, 0, 0, "IST_FP16m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #828 = IST_FP16m
+ { 829, 5, 0, 0, "IST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #829 = IST_FP32m
+ { 830, 5, 0, 0, "IST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(223<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #830 = IST_FP64m
+ { 831, 6, 0, 0, "IST_Fp16m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #831 = IST_Fp16m32
+ { 832, 6, 0, 0, "IST_Fp16m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #832 = IST_Fp16m64
+ { 833, 6, 0, 0, "IST_Fp16m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #833 = IST_Fp16m80
+ { 834, 6, 0, 0, "IST_Fp32m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #834 = IST_Fp32m32
+ { 835, 6, 0, 0, "IST_Fp32m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #835 = IST_Fp32m64
+ { 836, 6, 0, 0, "IST_Fp32m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #836 = IST_Fp32m80
+ { 837, 6, 0, 0, "IST_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #837 = IST_Fp64m32
+ { 838, 6, 0, 0, "IST_Fp64m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #838 = IST_Fp64m64
+ { 839, 6, 0, 0, "IST_Fp64m80", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #839 = IST_Fp64m80
+ { 840, 8, 1, 0, "Int_CMPSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #840 = Int_CMPSDrm
+ { 841, 4, 1, 0, "Int_CMPSDrr", 0, 0|5|(11<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #841 = Int_CMPSDrr
+ { 842, 8, 1, 0, "Int_CMPSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #842 = Int_CMPSSrm
+ { 843, 4, 1, 0, "Int_CMPSSrr", 0, 0|5|(12<<8)|(1<<13)|(194<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #843 = Int_CMPSSrr
+ { 844, 6, 0, 0, "Int_COMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #844 = Int_COMISDrm
+ { 845, 2, 0, 0, "Int_COMISDrr", 0, 0|5|(1<<6)|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #845 = Int_COMISDrr
+ { 846, 6, 0, 0, "Int_COMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #846 = Int_COMISSrm
+ { 847, 2, 0, 0, "Int_COMISSrr", 0, 0|5|(1<<8)|(47<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #847 = Int_COMISSrr
+ { 848, 6, 1, 0, "Int_CVTDQ2PDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #848 = Int_CVTDQ2PDrm
+ { 849, 2, 1, 0, "Int_CVTDQ2PDrr", 0, 0|5|(12<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #849 = Int_CVTDQ2PDrr
+ { 850, 6, 1, 0, "Int_CVTDQ2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #850 = Int_CVTDQ2PSrm
+ { 851, 2, 1, 0, "Int_CVTDQ2PSrr", 0, 0|5|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #851 = Int_CVTDQ2PSrr
+ { 852, 6, 1, 0, "Int_CVTPD2DQrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #852 = Int_CVTPD2DQrm
+ { 853, 2, 1, 0, "Int_CVTPD2DQrr", 0, 0|5|(11<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #853 = Int_CVTPD2DQrr
+ { 854, 6, 1, 0, "Int_CVTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #854 = Int_CVTPD2PIrm
+ { 855, 2, 1, 0, "Int_CVTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #855 = Int_CVTPD2PIrr
+ { 856, 6, 1, 0, "Int_CVTPD2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #856 = Int_CVTPD2PSrm
+ { 857, 2, 1, 0, "Int_CVTPD2PSrr", 0, 0|5|(1<<6)|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #857 = Int_CVTPD2PSrr
+ { 858, 6, 1, 0, "Int_CVTPI2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #858 = Int_CVTPI2PDrm
+ { 859, 2, 1, 0, "Int_CVTPI2PDrr", 0, 0|5|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #859 = Int_CVTPI2PDrr
+ { 860, 7, 1, 0, "Int_CVTPI2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #860 = Int_CVTPI2PSrm
+ { 861, 3, 1, 0, "Int_CVTPI2PSrr", 0, 0|5|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo120 }, // Inst #861 = Int_CVTPI2PSrr
+ { 862, 6, 1, 0, "Int_CVTPS2DQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #862 = Int_CVTPS2DQrm
+ { 863, 2, 1, 0, "Int_CVTPS2DQrr", 0, 0|5|(1<<6)|(1<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #863 = Int_CVTPS2DQrr
+ { 864, 6, 1, 0, "Int_CVTPS2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #864 = Int_CVTPS2PDrm
+ { 865, 2, 1, 0, "Int_CVTPS2PDrr", 0, 0|5|(1<<8)|(90<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #865 = Int_CVTPS2PDrr
+ { 866, 6, 1, 0, "Int_CVTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #866 = Int_CVTPS2PIrm
+ { 867, 2, 1, 0, "Int_CVTPS2PIrr", 0, 0|5|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #867 = Int_CVTPS2PIrr
+ { 868, 6, 1, 0, "Int_CVTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #868 = Int_CVTSD2SI64rm
+ { 869, 2, 1, 0, "Int_CVTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #869 = Int_CVTSD2SI64rr
+ { 870, 6, 1, 0, "Int_CVTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(45<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #870 = Int_CVTSD2SIrm
+ { 871, 2, 1, 0, "Int_CVTSD2SIrr", 0, 0|5|(11<<8)|(45<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #871 = Int_CVTSD2SIrr
+ { 872, 7, 1, 0, "Int_CVTSD2SSrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #872 = Int_CVTSD2SSrm
+ { 873, 3, 1, 0, "Int_CVTSD2SSrr", 0, 0|5|(11<<8)|(90<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #873 = Int_CVTSD2SSrr
+ { 874, 7, 1, 0, "Int_CVTSI2SD64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #874 = Int_CVTSI2SD64rm
+ { 875, 3, 1, 0, "Int_CVTSI2SD64rr", 0, 0|5|(11<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo123 }, // Inst #875 = Int_CVTSI2SD64rr
+ { 876, 7, 1, 0, "Int_CVTSI2SDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #876 = Int_CVTSI2SDrm
+ { 877, 3, 1, 0, "Int_CVTSI2SDrr", 0, 0|5|(11<<8)|(42<<24), NULL, NULL, NULL, OperandInfo124 }, // Inst #877 = Int_CVTSI2SDrr
+ { 878, 7, 1, 0, "Int_CVTSI2SS64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #878 = Int_CVTSI2SS64rm
+ { 879, 3, 1, 0, "Int_CVTSI2SS64rr", 0, 0|5|(12<<8)|(1<<12)|(42<<24), NULL, NULL, NULL, OperandInfo123 }, // Inst #879 = Int_CVTSI2SS64rr
+ { 880, 7, 1, 0, "Int_CVTSI2SSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #880 = Int_CVTSI2SSrm
+ { 881, 3, 1, 0, "Int_CVTSI2SSrr", 0, 0|5|(12<<8)|(42<<24), NULL, NULL, NULL, OperandInfo124 }, // Inst #881 = Int_CVTSI2SSrr
+ { 882, 7, 1, 0, "Int_CVTSS2SDrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #882 = Int_CVTSS2SDrm
+ { 883, 3, 1, 0, "Int_CVTSS2SDrr", 0, 0|5|(12<<8)|(90<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #883 = Int_CVTSS2SDrr
+ { 884, 6, 1, 0, "Int_CVTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #884 = Int_CVTSS2SI64rm
+ { 885, 2, 1, 0, "Int_CVTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(45<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #885 = Int_CVTSS2SI64rr
+ { 886, 6, 1, 0, "Int_CVTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #886 = Int_CVTSS2SIrm
+ { 887, 2, 1, 0, "Int_CVTSS2SIrr", 0, 0|5|(12<<8)|(45<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #887 = Int_CVTSS2SIrr
+ { 888, 6, 1, 0, "Int_CVTTPD2DQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(230<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #888 = Int_CVTTPD2DQrm
+ { 889, 2, 1, 0, "Int_CVTTPD2DQrr", 0, 0|5|(1<<6)|(1<<8)|(230<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #889 = Int_CVTTPD2DQrr
+ { 890, 6, 1, 0, "Int_CVTTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #890 = Int_CVTTPD2PIrm
+ { 891, 2, 1, 0, "Int_CVTTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #891 = Int_CVTTPD2PIrr
+ { 892, 6, 1, 0, "Int_CVTTPS2DQrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #892 = Int_CVTTPS2DQrm
+ { 893, 2, 1, 0, "Int_CVTTPS2DQrr", 0, 0|5|(12<<8)|(91<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #893 = Int_CVTTPS2DQrr
+ { 894, 6, 1, 0, "Int_CVTTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #894 = Int_CVTTPS2PIrm
+ { 895, 2, 1, 0, "Int_CVTTPS2PIrr", 0, 0|5|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #895 = Int_CVTTPS2PIrr
+ { 896, 6, 1, 0, "Int_CVTTSD2SI64rm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #896 = Int_CVTTSD2SI64rm
+ { 897, 2, 1, 0, "Int_CVTTSD2SI64rr", 0, 0|5|(11<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #897 = Int_CVTTSD2SI64rr
+ { 898, 6, 1, 0, "Int_CVTTSD2SIrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #898 = Int_CVTTSD2SIrm
+ { 899, 2, 1, 0, "Int_CVTTSD2SIrr", 0, 0|5|(11<<8)|(44<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #899 = Int_CVTTSD2SIrr
+ { 900, 6, 1, 0, "Int_CVTTSS2SI64rm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #900 = Int_CVTTSS2SI64rm
+ { 901, 2, 1, 0, "Int_CVTTSS2SI64rr", 0, 0|5|(12<<8)|(1<<12)|(44<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #901 = Int_CVTTSS2SI64rr
+ { 902, 6, 1, 0, "Int_CVTTSS2SIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #902 = Int_CVTTSS2SIrm
+ { 903, 2, 1, 0, "Int_CVTTSS2SIrr", 0, 0|5|(12<<8)|(44<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #903 = Int_CVTTSS2SIrr
+ { 904, 6, 0, 0, "Int_UCOMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #904 = Int_UCOMISDrm
+ { 905, 2, 0, 0, "Int_UCOMISDrr", 0, 0|5|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #905 = Int_UCOMISDrr
+ { 906, 6, 0, 0, "Int_UCOMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #906 = Int_UCOMISSrm
+ { 907, 2, 0, 0, "Int_UCOMISSrr", 0, 0|5|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #907 = Int_UCOMISSrr
+ { 908, 1, 0, 0, "JA", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(135<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #908 = JA
+ { 909, 1, 0, 0, "JA8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(119<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #909 = JA8
+ { 910, 1, 0, 0, "JAE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(131<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #910 = JAE
+ { 911, 1, 0, 0, "JAE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(115<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #911 = JAE8
+ { 912, 1, 0, 0, "JB", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(130<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #912 = JB
+ { 913, 1, 0, 0, "JB8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(114<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #913 = JB8
+ { 914, 1, 0, 0, "JBE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(134<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #914 = JBE
+ { 915, 1, 0, 0, "JBE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(118<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #915 = JBE8
+ { 916, 1, 0, 0, "JCXZ8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(227<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #916 = JCXZ8
+ { 917, 1, 0, 0, "JE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(132<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #917 = JE
+ { 918, 1, 0, 0, "JE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(116<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #918 = JE8
+ { 919, 1, 0, 0, "JG", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(143<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #919 = JG
+ { 920, 1, 0, 0, "JG8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(127<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #920 = JG8
+ { 921, 1, 0, 0, "JGE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(141<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #921 = JGE
+ { 922, 1, 0, 0, "JGE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(125<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #922 = JGE8
+ { 923, 1, 0, 0, "JL", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(140<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #923 = JL
+ { 924, 1, 0, 0, "JL8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(124<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #924 = JL8
+ { 925, 1, 0, 0, "JLE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(142<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #925 = JLE
+ { 926, 1, 0, 0, "JLE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(126<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #926 = JLE8
+ { 927, 1, 0, 0, "JMP", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|1|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #927 = JMP
+ { 928, 5, 0, 0, "JMP32m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #928 = JMP32m
+ { 929, 1, 0, 0, "JMP32r", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #929 = JMP32r
+ { 930, 5, 0, 0, "JMP64m", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #930 = JMP64m
+ { 931, 1, 0, 0, "JMP64pcrel32", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #931 = JMP64pcrel32
+ { 932, 1, 0, 0, "JMP64r", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #932 = JMP64r
+ { 933, 1, 0, 0, "JMP8", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(235<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #933 = JMP8
+ { 934, 1, 0, 0, "JNE", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(133<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #934 = JNE
+ { 935, 1, 0, 0, "JNE8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(117<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #935 = JNE8
+ { 936, 1, 0, 0, "JNO", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(129<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #936 = JNO
+ { 937, 1, 0, 0, "JNO8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(113<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #937 = JNO8
+ { 938, 1, 0, 0, "JNP", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(139<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #938 = JNP
+ { 939, 1, 0, 0, "JNP8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(123<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #939 = JNP8
+ { 940, 1, 0, 0, "JNS", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(137<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #940 = JNS
+ { 941, 1, 0, 0, "JNS8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(121<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #941 = JNS8
+ { 942, 1, 0, 0, "JO", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(128<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #942 = JO
+ { 943, 1, 0, 0, "JO8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(112<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #943 = JO8
+ { 944, 1, 0, 0, "JP", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(138<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #944 = JP
+ { 945, 1, 0, 0, "JP8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(122<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #945 = JP8
+ { 946, 1, 0, 0, "JS", 0|(1<<TID::Branch)|(1<<TID::Terminator), 0|1|(1<<8)|(136<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #946 = JS
+ { 947, 1, 0, 0, "JS8", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(120<<24), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #947 = JS8
+ { 948, 0, 0, 0, "LAHF", 0, 0|1|(159<<24), ImplicitList1, ImplicitList27, NULL, 0 }, // Inst #948 = LAHF
+ { 949, 6, 1, 0, "LAR16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #949 = LAR16rm
+ { 950, 2, 1, 0, "LAR16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #950 = LAR16rr
+ { 951, 6, 1, 0, "LAR32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #951 = LAR32rm
+ { 952, 2, 1, 0, "LAR32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(2<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #952 = LAR32rr
+ { 953, 6, 1, 0, "LAR64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(2<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #953 = LAR64rm
+ { 954, 2, 1, 0, "LAR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(2<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #954 = LAR64rr
+ { 955, 6, 0, 0, "LCMPXCHG16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<19)|(177<<24), ImplicitList12, ImplicitList28, Barriers1, OperandInfo7 }, // Inst #955 = LCMPXCHG16
+ { 956, 6, 0, 0, "LCMPXCHG32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<19)|(177<<24), ImplicitList13, ImplicitList29, Barriers1, OperandInfo11 }, // Inst #956 = LCMPXCHG32
+ { 957, 6, 0, 0, "LCMPXCHG64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<19)|(177<<24), ImplicitList15, ImplicitList30, Barriers1, OperandInfo15 }, // Inst #957 = LCMPXCHG64
+ { 958, 6, 0, 0, "LCMPXCHG8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<19)|(176<<24), ImplicitList11, ImplicitList31, Barriers1, OperandInfo20 }, // Inst #958 = LCMPXCHG8
+ { 959, 5, 0, 0, "LCMPXCHG8B", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<8)|(1<<19)|(199<<24), ImplicitList6, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #959 = LCMPXCHG8B
+ { 960, 6, 1, 0, "LDDQUrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(240<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #960 = LDDQUrm
+ { 961, 5, 0, 0, "LDMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #961 = LDMXCSR
+ { 962, 6, 1, 0, "LDS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(197<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #962 = LDS16rm
+ { 963, 6, 1, 0, "LDS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(197<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #963 = LDS32rm
+ { 964, 0, 0, 0, "LD_F0", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(238<<24), NULL, NULL, NULL, 0 }, // Inst #964 = LD_F0
+ { 965, 0, 0, 0, "LD_F1", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(232<<24), NULL, NULL, NULL, 0 }, // Inst #965 = LD_F1
+ { 966, 5, 0, 0, "LD_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #966 = LD_F32m
+ { 967, 5, 0, 0, "LD_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|24|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #967 = LD_F64m
+ { 968, 5, 0, 0, "LD_F80m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #968 = LD_F80m
+ { 969, 1, 1, 0, "LD_Fp032", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #969 = LD_Fp032
+ { 970, 1, 1, 0, "LD_Fp064", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #970 = LD_Fp064
+ { 971, 1, 1, 0, "LD_Fp080", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #971 = LD_Fp080
+ { 972, 1, 1, 0, "LD_Fp132", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #972 = LD_Fp132
+ { 973, 1, 1, 0, "LD_Fp164", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #973 = LD_Fp164
+ { 974, 1, 1, 0, "LD_Fp180", 0|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #974 = LD_Fp180
+ { 975, 6, 1, 0, "LD_Fp32m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo107 }, // Inst #975 = LD_Fp32m
+ { 976, 6, 1, 0, "LD_Fp32m64", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #976 = LD_Fp32m64
+ { 977, 6, 1, 0, "LD_Fp32m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #977 = LD_Fp32m80
+ { 978, 6, 1, 0, "LD_Fp64m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<16), NULL, NULL, NULL, OperandInfo108 }, // Inst #978 = LD_Fp64m
+ { 979, 6, 1, 0, "LD_Fp64m80", 0|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #979 = LD_Fp64m80
+ { 980, 6, 1, 0, "LD_Fp80m", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<16), NULL, NULL, NULL, OperandInfo109 }, // Inst #980 = LD_Fp80m
+ { 981, 1, 0, 0, "LD_Frr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(4<<8)|(192<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #981 = LD_Frr
+ { 982, 5, 1, 0, "LEA16r", 0, 0|6|(1<<6)|(141<<24), NULL, NULL, NULL, OperandInfo126 }, // Inst #982 = LEA16r
+ { 983, 5, 1, 0, "LEA32r", 0|(1<<TID::Rematerializable), 0|6|(141<<24), NULL, NULL, NULL, OperandInfo127 }, // Inst #983 = LEA32r
+ { 984, 5, 1, 0, "LEA64_32r", 0, 0|6|(141<<24), NULL, NULL, NULL, OperandInfo127 }, // Inst #984 = LEA64_32r
+ { 985, 5, 1, 0, "LEA64r", 0|(1<<TID::Rematerializable), 0|6|(1<<12)|(141<<24), NULL, NULL, NULL, OperandInfo128 }, // Inst #985 = LEA64r
+ { 986, 0, 0, 0, "LEAVE", 0|(1<<TID::MayLoad), 0|1|(201<<24), ImplicitList32, ImplicitList32, NULL, 0 }, // Inst #986 = LEAVE
+ { 987, 0, 0, 0, "LEAVE64", 0|(1<<TID::MayLoad), 0|1|(201<<24), ImplicitList33, ImplicitList33, NULL, 0 }, // Inst #987 = LEAVE64
+ { 988, 6, 1, 0, "LES16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(196<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #988 = LES16rm
+ { 989, 6, 1, 0, "LES32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(196<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #989 = LES32rm
+ { 990, 0, 0, 0, "LFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #990 = LFENCE
+ { 991, 6, 1, 0, "LFS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(180<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #991 = LFS16rm
+ { 992, 6, 1, 0, "LFS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(180<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #992 = LFS32rm
+ { 993, 6, 1, 0, "LFS64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(180<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #993 = LFS64rm
+ { 994, 5, 0, 0, "LGDTm", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #994 = LGDTm
+ { 995, 6, 1, 0, "LGS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(181<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #995 = LGS16rm
+ { 996, 6, 1, 0, "LGS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(181<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #996 = LGS32rm
+ { 997, 6, 1, 0, "LGS64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(181<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #997 = LGS64rm
+ { 998, 5, 0, 0, "LIDTm", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #998 = LIDTm
+ { 999, 5, 0, 0, "LLDT16m", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #999 = LLDT16m
+ { 1000, 1, 0, 0, "LLDT16r", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #1000 = LLDT16r
+ { 1001, 5, 0, 0, "LMSW16m", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1001 = LMSW16m
+ { 1002, 1, 0, 0, "LMSW16r", 0|(1<<TID::UnmodeledSideEffects), 0|22|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #1002 = LMSW16r
+ { 1003, 6, 0, 0, "LOCK_ADD16mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(2<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1003 = LOCK_ADD16mi
+ { 1004, 6, 0, 0, "LOCK_ADD16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<6)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1004 = LOCK_ADD16mi8
+ { 1005, 6, 0, 0, "LOCK_ADD16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<19)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1005 = LOCK_ADD16mr
+ { 1006, 6, 0, 0, "LOCK_ADD32mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1006 = LOCK_ADD32mi
+ { 1007, 6, 0, 0, "LOCK_ADD32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1007 = LOCK_ADD32mi8
+ { 1008, 6, 0, 0, "LOCK_ADD32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(1<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1008 = LOCK_ADD32mr
+ { 1009, 6, 0, 0, "LOCK_ADD64mi32", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1009 = LOCK_ADD64mi32
+ { 1010, 6, 0, 0, "LOCK_ADD64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1010 = LOCK_ADD64mi8
+ { 1011, 6, 0, 0, "LOCK_ADD64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(1<<19)|(3<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1011 = LOCK_ADD64mr
+ { 1012, 6, 0, 0, "LOCK_ADD8mi", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<13)|(1<<19)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1012 = LOCK_ADD8mi
+ { 1013, 6, 0, 0, "LOCK_ADD8mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1013 = LOCK_ADD8mr
+ { 1014, 5, 0, 0, "LOCK_DEC16m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<6)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1014 = LOCK_DEC16m
+ { 1015, 5, 0, 0, "LOCK_DEC32m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1015 = LOCK_DEC32m
+ { 1016, 5, 0, 0, "LOCK_DEC64m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<12)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1016 = LOCK_DEC64m
+ { 1017, 5, 0, 0, "LOCK_DEC8m", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<19)|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1017 = LOCK_DEC8m
+ { 1018, 5, 0, 0, "LOCK_INC16m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<6)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1018 = LOCK_INC16m
+ { 1019, 5, 0, 0, "LOCK_INC32m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1019 = LOCK_INC32m
+ { 1020, 5, 0, 0, "LOCK_INC64m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<12)|(1<<19)|(255<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1020 = LOCK_INC64m
+ { 1021, 5, 0, 0, "LOCK_INC8m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<19)|(254<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1021 = LOCK_INC8m
+ { 1022, 6, 0, 0, "LOCK_SUB16mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(2<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1022 = LOCK_SUB16mi
+ { 1023, 6, 0, 0, "LOCK_SUB16mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<6)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1023 = LOCK_SUB16mi8
+ { 1024, 6, 0, 0, "LOCK_SUB16mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1024 = LOCK_SUB16mr
+ { 1025, 6, 0, 0, "LOCK_SUB32mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1025 = LOCK_SUB32mi
+ { 1026, 6, 0, 0, "LOCK_SUB32mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1026 = LOCK_SUB32mi8
+ { 1027, 6, 0, 0, "LOCK_SUB32mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1027 = LOCK_SUB32mr
+ { 1028, 6, 0, 0, "LOCK_SUB64mi32", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(3<<13)|(1<<19)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1028 = LOCK_SUB64mi32
+ { 1029, 6, 0, 0, "LOCK_SUB64mi8", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<12)|(1<<13)|(1<<19)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1029 = LOCK_SUB64mi8
+ { 1030, 6, 0, 0, "LOCK_SUB64mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(1<<19)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1030 = LOCK_SUB64mr
+ { 1031, 6, 0, 0, "LOCK_SUB8mi", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<13)|(1<<19)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1031 = LOCK_SUB8mi
+ { 1032, 6, 0, 0, "LOCK_SUB8mr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<19)|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1032 = LOCK_SUB8mr
+ { 1033, 0, 0, 0, "LODSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(172<<24), NULL, NULL, NULL, 0 }, // Inst #1033 = LODSB
+ { 1034, 0, 0, 0, "LODSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(173<<24), NULL, NULL, NULL, 0 }, // Inst #1034 = LODSD
+ { 1035, 0, 0, 0, "LODSQ", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(173<<24), NULL, NULL, NULL, 0 }, // Inst #1035 = LODSQ
+ { 1036, 0, 0, 0, "LODSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(173<<24), NULL, NULL, NULL, 0 }, // Inst #1036 = LODSW
+ { 1037, 1, 1, 0, "LOOP", 0|(1<<TID::UnmodeledSideEffects), 0|1|(226<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1037 = LOOP
+ { 1038, 1, 1, 0, "LOOPE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(225<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1038 = LOOPE
+ { 1039, 1, 1, 0, "LOOPNE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(224<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1039 = LOOPNE
+ { 1040, 0, 0, 0, "LRET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(7<<16)|(203<<24), NULL, NULL, NULL, 0 }, // Inst #1040 = LRET
+ { 1041, 1, 0, 0, "LRETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(2<<13)|(7<<16)|(202<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1041 = LRETI
+ { 1042, 6, 1, 0, "LSL16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1042 = LSL16rm
+ { 1043, 2, 1, 0, "LSL16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1043 = LSL16rr
+ { 1044, 6, 1, 0, "LSL32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1044 = LSL32rm
+ { 1045, 2, 1, 0, "LSL32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(3<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1045 = LSL32rr
+ { 1046, 6, 1, 0, "LSL64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(3<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1046 = LSL64rm
+ { 1047, 2, 1, 0, "LSL64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(3<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1047 = LSL64rr
+ { 1048, 6, 1, 0, "LSS16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(178<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1048 = LSS16rm
+ { 1049, 6, 1, 0, "LSS32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(178<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1049 = LSS32rm
+ { 1050, 6, 1, 0, "LSS64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(178<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1050 = LSS64rm
+ { 1051, 5, 0, 0, "LTRm", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #1051 = LTRm
+ { 1052, 1, 0, 0, "LTRr", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #1052 = LTRr
+ { 1053, 7, 1, 0, "LXADD16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<6)|(1<<8)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1053 = LXADD16
+ { 1054, 7, 1, 0, "LXADD32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #1054 = LXADD32
+ { 1055, 7, 1, 0, "LXADD64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<12)|(1<<19)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #1055 = LXADD64
+ { 1056, 7, 1, 0, "LXADD8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<8)|(1<<19)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1056 = LXADD8
+ { 1057, 2, 0, 0, "MASKMOVDQU", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(247<<24), ImplicitList34, NULL, NULL, OperandInfo75 }, // Inst #1057 = MASKMOVDQU
+ { 1058, 2, 0, 0, "MASKMOVDQU64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(247<<24), ImplicitList35, NULL, NULL, OperandInfo75 }, // Inst #1058 = MASKMOVDQU64
+ { 1059, 7, 1, 0, "MAXPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1059 = MAXPDrm
+ { 1060, 7, 1, 0, "MAXPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1060 = MAXPDrm_Int
+ { 1061, 3, 1, 0, "MAXPDrr", 0, 0|5|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1061 = MAXPDrr
+ { 1062, 3, 1, 0, "MAXPDrr_Int", 0, 0|5|(1<<6)|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1062 = MAXPDrr_Int
+ { 1063, 7, 1, 0, "MAXPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1063 = MAXPSrm
+ { 1064, 7, 1, 0, "MAXPSrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1064 = MAXPSrm_Int
+ { 1065, 3, 1, 0, "MAXPSrr", 0, 0|5|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1065 = MAXPSrr
+ { 1066, 3, 1, 0, "MAXPSrr_Int", 0, 0|5|(1<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1066 = MAXPSrr_Int
+ { 1067, 7, 1, 0, "MAXSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1067 = MAXSDrm
+ { 1068, 7, 1, 0, "MAXSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1068 = MAXSDrm_Int
+ { 1069, 3, 1, 0, "MAXSDrr", 0, 0|5|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1069 = MAXSDrr
+ { 1070, 3, 1, 0, "MAXSDrr_Int", 0, 0|5|(11<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1070 = MAXSDrr_Int
+ { 1071, 7, 1, 0, "MAXSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1071 = MAXSSrm
+ { 1072, 7, 1, 0, "MAXSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1072 = MAXSSrm_Int
+ { 1073, 3, 1, 0, "MAXSSrr", 0, 0|5|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1073 = MAXSSrr
+ { 1074, 3, 1, 0, "MAXSSrr_Int", 0, 0|5|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1074 = MAXSSrr_Int
+ { 1075, 0, 0, 0, "MFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|22|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #1075 = MFENCE
+ { 1076, 7, 1, 0, "MINPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1076 = MINPDrm
+ { 1077, 7, 1, 0, "MINPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1077 = MINPDrm_Int
+ { 1078, 3, 1, 0, "MINPDrr", 0, 0|5|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1078 = MINPDrr
+ { 1079, 3, 1, 0, "MINPDrr_Int", 0, 0|5|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1079 = MINPDrr_Int
+ { 1080, 7, 1, 0, "MINPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1080 = MINPSrm
+ { 1081, 7, 1, 0, "MINPSrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1081 = MINPSrm_Int
+ { 1082, 3, 1, 0, "MINPSrr", 0, 0|5|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1082 = MINPSrr
+ { 1083, 3, 1, 0, "MINPSrr_Int", 0, 0|5|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1083 = MINPSrr_Int
+ { 1084, 7, 1, 0, "MINSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1084 = MINSDrm
+ { 1085, 7, 1, 0, "MINSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1085 = MINSDrm_Int
+ { 1086, 3, 1, 0, "MINSDrr", 0, 0|5|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1086 = MINSDrr
+ { 1087, 3, 1, 0, "MINSDrr_Int", 0, 0|5|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1087 = MINSDrr_Int
+ { 1088, 7, 1, 0, "MINSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1088 = MINSSrm
+ { 1089, 7, 1, 0, "MINSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1089 = MINSSrm_Int
+ { 1090, 3, 1, 0, "MINSSrr", 0, 0|5|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1090 = MINSSrr
+ { 1091, 3, 1, 0, "MINSSrr_Int", 0, 0|5|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1091 = MINSSrr_Int
+ { 1092, 6, 1, 0, "MMX_CVTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1092 = MMX_CVTPD2PIrm
+ { 1093, 2, 1, 0, "MMX_CVTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1093 = MMX_CVTPD2PIrr
+ { 1094, 6, 1, 0, "MMX_CVTPI2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1094 = MMX_CVTPI2PDrm
+ { 1095, 2, 1, 0, "MMX_CVTPI2PDrr", 0, 0|5|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1095 = MMX_CVTPI2PDrr
+ { 1096, 6, 1, 0, "MMX_CVTPI2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1096 = MMX_CVTPI2PSrm
+ { 1097, 2, 1, 0, "MMX_CVTPI2PSrr", 0, 0|5|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1097 = MMX_CVTPI2PSrr
+ { 1098, 6, 1, 0, "MMX_CVTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1098 = MMX_CVTPS2PIrm
+ { 1099, 2, 1, 0, "MMX_CVTPS2PIrr", 0, 0|5|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1099 = MMX_CVTPS2PIrr
+ { 1100, 6, 1, 0, "MMX_CVTTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1100 = MMX_CVTTPD2PIrm
+ { 1101, 2, 1, 0, "MMX_CVTTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1101 = MMX_CVTTPD2PIrr
+ { 1102, 6, 1, 0, "MMX_CVTTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1102 = MMX_CVTTPS2PIrm
+ { 1103, 2, 1, 0, "MMX_CVTTPS2PIrr", 0, 0|5|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1103 = MMX_CVTTPS2PIrr
+ { 1104, 0, 0, 0, "MMX_EMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(119<<24), NULL, NULL, NULL, 0 }, // Inst #1104 = MMX_EMMS
+ { 1105, 0, 0, 0, "MMX_FEMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(14<<24), NULL, NULL, NULL, 0 }, // Inst #1105 = MMX_FEMMS
+ { 1106, 2, 0, 0, "MMX_MASKMOVQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(247<<24), ImplicitList34, NULL, NULL, OperandInfo129 }, // Inst #1106 = MMX_MASKMOVQ
+ { 1107, 2, 0, 0, "MMX_MASKMOVQ64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(247<<24), ImplicitList35, NULL, NULL, OperandInfo129 }, // Inst #1107 = MMX_MASKMOVQ64
+ { 1108, 2, 1, 0, "MMX_MOVD64from64rr", 0, 0|3|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo130 }, // Inst #1108 = MMX_MOVD64from64rr
+ { 1109, 2, 0, 0, "MMX_MOVD64grr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo131 }, // Inst #1109 = MMX_MOVD64grr
+ { 1110, 6, 0, 0, "MMX_MOVD64mr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1110 = MMX_MOVD64mr
+ { 1111, 6, 1, 0, "MMX_MOVD64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1111 = MMX_MOVD64rm
+ { 1112, 2, 1, 0, "MMX_MOVD64rr", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo133 }, // Inst #1112 = MMX_MOVD64rr
+ { 1113, 2, 1, 0, "MMX_MOVD64rrv164", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1113 = MMX_MOVD64rrv164
+ { 1114, 2, 1, 0, "MMX_MOVD64to64rr", 0, 0|5|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1114 = MMX_MOVD64to64rr
+ { 1115, 2, 1, 0, "MMX_MOVDQ2Qrr", 0, 0|5|(11<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1115 = MMX_MOVDQ2Qrr
+ { 1116, 6, 0, 0, "MMX_MOVNTQmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1116 = MMX_MOVNTQmr
+ { 1117, 2, 1, 0, "MMX_MOVQ2DQrr", 0, 0|5|(12<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1117 = MMX_MOVQ2DQrr
+ { 1118, 2, 1, 0, "MMX_MOVQ2FR64rr", 0, 0|5|(12<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1118 = MMX_MOVQ2FR64rr
+ { 1119, 6, 0, 0, "MMX_MOVQ64gmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1119 = MMX_MOVQ64gmr
+ { 1120, 6, 0, 0, "MMX_MOVQ64mr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(127<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1120 = MMX_MOVQ64mr
+ { 1121, 6, 1, 0, "MMX_MOVQ64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1121 = MMX_MOVQ64rm
+ { 1122, 2, 1, 0, "MMX_MOVQ64rr", 0, 0|5|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1122 = MMX_MOVQ64rr
+ { 1123, 6, 1, 0, "MMX_MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1123 = MMX_MOVZDI2PDIrm
+ { 1124, 2, 1, 0, "MMX_MOVZDI2PDIrr", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo133 }, // Inst #1124 = MMX_MOVZDI2PDIrr
+ { 1125, 7, 1, 0, "MMX_PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1125 = MMX_PACKSSDWrm
+ { 1126, 3, 1, 0, "MMX_PACKSSDWrr", 0, 0|5|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1126 = MMX_PACKSSDWrr
+ { 1127, 7, 1, 0, "MMX_PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1127 = MMX_PACKSSWBrm
+ { 1128, 3, 1, 0, "MMX_PACKSSWBrr", 0, 0|5|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1128 = MMX_PACKSSWBrr
+ { 1129, 7, 1, 0, "MMX_PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1129 = MMX_PACKUSWBrm
+ { 1130, 3, 1, 0, "MMX_PACKUSWBrr", 0, 0|5|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1130 = MMX_PACKUSWBrr
+ { 1131, 7, 1, 0, "MMX_PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1131 = MMX_PADDBrm
+ { 1132, 3, 1, 0, "MMX_PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1132 = MMX_PADDBrr
+ { 1133, 7, 1, 0, "MMX_PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1133 = MMX_PADDDrm
+ { 1134, 3, 1, 0, "MMX_PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1134 = MMX_PADDDrr
+ { 1135, 7, 1, 0, "MMX_PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1135 = MMX_PADDQrm
+ { 1136, 3, 1, 0, "MMX_PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1136 = MMX_PADDQrr
+ { 1137, 7, 1, 0, "MMX_PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1137 = MMX_PADDSBrm
+ { 1138, 3, 1, 0, "MMX_PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1138 = MMX_PADDSBrr
+ { 1139, 7, 1, 0, "MMX_PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1139 = MMX_PADDSWrm
+ { 1140, 3, 1, 0, "MMX_PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1140 = MMX_PADDSWrr
+ { 1141, 7, 1, 0, "MMX_PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1141 = MMX_PADDUSBrm
+ { 1142, 3, 1, 0, "MMX_PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1142 = MMX_PADDUSBrr
+ { 1143, 7, 1, 0, "MMX_PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1143 = MMX_PADDUSWrm
+ { 1144, 3, 1, 0, "MMX_PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1144 = MMX_PADDUSWrr
+ { 1145, 7, 1, 0, "MMX_PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1145 = MMX_PADDWrm
+ { 1146, 3, 1, 0, "MMX_PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1146 = MMX_PADDWrr
+ { 1147, 7, 1, 0, "MMX_PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1147 = MMX_PANDNrm
+ { 1148, 3, 1, 0, "MMX_PANDNrr", 0, 0|5|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1148 = MMX_PANDNrr
+ { 1149, 7, 1, 0, "MMX_PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1149 = MMX_PANDrm
+ { 1150, 3, 1, 0, "MMX_PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1150 = MMX_PANDrr
+ { 1151, 7, 1, 0, "MMX_PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1151 = MMX_PAVGBrm
+ { 1152, 3, 1, 0, "MMX_PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1152 = MMX_PAVGBrr
+ { 1153, 7, 1, 0, "MMX_PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1153 = MMX_PAVGWrm
+ { 1154, 3, 1, 0, "MMX_PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1154 = MMX_PAVGWrr
+ { 1155, 7, 1, 0, "MMX_PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1155 = MMX_PCMPEQBrm
+ { 1156, 3, 1, 0, "MMX_PCMPEQBrr", 0, 0|5|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1156 = MMX_PCMPEQBrr
+ { 1157, 7, 1, 0, "MMX_PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1157 = MMX_PCMPEQDrm
+ { 1158, 3, 1, 0, "MMX_PCMPEQDrr", 0, 0|5|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1158 = MMX_PCMPEQDrr
+ { 1159, 7, 1, 0, "MMX_PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1159 = MMX_PCMPEQWrm
+ { 1160, 3, 1, 0, "MMX_PCMPEQWrr", 0, 0|5|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1160 = MMX_PCMPEQWrr
+ { 1161, 7, 1, 0, "MMX_PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1161 = MMX_PCMPGTBrm
+ { 1162, 3, 1, 0, "MMX_PCMPGTBrr", 0, 0|5|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1162 = MMX_PCMPGTBrr
+ { 1163, 7, 1, 0, "MMX_PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1163 = MMX_PCMPGTDrm
+ { 1164, 3, 1, 0, "MMX_PCMPGTDrr", 0, 0|5|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1164 = MMX_PCMPGTDrr
+ { 1165, 7, 1, 0, "MMX_PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1165 = MMX_PCMPGTWrm
+ { 1166, 3, 1, 0, "MMX_PCMPGTWrr", 0, 0|5|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1166 = MMX_PCMPGTWrr
+ { 1167, 3, 1, 0, "MMX_PEXTRWri", 0, 0|5|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo138 }, // Inst #1167 = MMX_PEXTRWri
+ { 1168, 8, 1, 0, "MMX_PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo139 }, // Inst #1168 = MMX_PINSRWrmi
+ { 1169, 4, 1, 0, "MMX_PINSRWrri", 0, 0|5|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo140 }, // Inst #1169 = MMX_PINSRWrri
+ { 1170, 7, 1, 0, "MMX_PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1170 = MMX_PMADDWDrm
+ { 1171, 3, 1, 0, "MMX_PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1171 = MMX_PMADDWDrr
+ { 1172, 7, 1, 0, "MMX_PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1172 = MMX_PMAXSWrm
+ { 1173, 3, 1, 0, "MMX_PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1173 = MMX_PMAXSWrr
+ { 1174, 7, 1, 0, "MMX_PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1174 = MMX_PMAXUBrm
+ { 1175, 3, 1, 0, "MMX_PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1175 = MMX_PMAXUBrr
+ { 1176, 7, 1, 0, "MMX_PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1176 = MMX_PMINSWrm
+ { 1177, 3, 1, 0, "MMX_PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1177 = MMX_PMINSWrr
+ { 1178, 7, 1, 0, "MMX_PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1178 = MMX_PMINUBrm
+ { 1179, 3, 1, 0, "MMX_PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1179 = MMX_PMINUBrr
+ { 1180, 2, 1, 0, "MMX_PMOVMSKBrr", 0, 0|5|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo131 }, // Inst #1180 = MMX_PMOVMSKBrr
+ { 1181, 7, 1, 0, "MMX_PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1181 = MMX_PMULHUWrm
+ { 1182, 3, 1, 0, "MMX_PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1182 = MMX_PMULHUWrr
+ { 1183, 7, 1, 0, "MMX_PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1183 = MMX_PMULHWrm
+ { 1184, 3, 1, 0, "MMX_PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1184 = MMX_PMULHWrr
+ { 1185, 7, 1, 0, "MMX_PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1185 = MMX_PMULLWrm
+ { 1186, 3, 1, 0, "MMX_PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1186 = MMX_PMULLWrr
+ { 1187, 7, 1, 0, "MMX_PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1187 = MMX_PMULUDQrm
+ { 1188, 3, 1, 0, "MMX_PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1188 = MMX_PMULUDQrr
+ { 1189, 7, 1, 0, "MMX_PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1189 = MMX_PORrm
+ { 1190, 3, 1, 0, "MMX_PORrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1190 = MMX_PORrr
+ { 1191, 7, 1, 0, "MMX_PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1191 = MMX_PSADBWrm
+ { 1192, 3, 1, 0, "MMX_PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1192 = MMX_PSADBWrr
+ { 1193, 7, 1, 0, "MMX_PSHUFWmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo141 }, // Inst #1193 = MMX_PSHUFWmi
+ { 1194, 3, 1, 0, "MMX_PSHUFWri", 0, 0|5|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1194 = MMX_PSHUFWri
+ { 1195, 3, 1, 0, "MMX_PSLLDri", 0, 0|22|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1195 = MMX_PSLLDri
+ { 1196, 7, 1, 0, "MMX_PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1196 = MMX_PSLLDrm
+ { 1197, 3, 1, 0, "MMX_PSLLDrr", 0, 0|5|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1197 = MMX_PSLLDrr
+ { 1198, 3, 1, 0, "MMX_PSLLQri", 0, 0|22|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1198 = MMX_PSLLQri
+ { 1199, 7, 1, 0, "MMX_PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1199 = MMX_PSLLQrm
+ { 1200, 3, 1, 0, "MMX_PSLLQrr", 0, 0|5|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1200 = MMX_PSLLQrr
+ { 1201, 3, 1, 0, "MMX_PSLLWri", 0, 0|22|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1201 = MMX_PSLLWri
+ { 1202, 7, 1, 0, "MMX_PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1202 = MMX_PSLLWrm
+ { 1203, 3, 1, 0, "MMX_PSLLWrr", 0, 0|5|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1203 = MMX_PSLLWrr
+ { 1204, 3, 1, 0, "MMX_PSRADri", 0, 0|20|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1204 = MMX_PSRADri
+ { 1205, 7, 1, 0, "MMX_PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1205 = MMX_PSRADrm
+ { 1206, 3, 1, 0, "MMX_PSRADrr", 0, 0|5|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1206 = MMX_PSRADrr
+ { 1207, 3, 1, 0, "MMX_PSRAWri", 0, 0|20|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1207 = MMX_PSRAWri
+ { 1208, 7, 1, 0, "MMX_PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1208 = MMX_PSRAWrm
+ { 1209, 3, 1, 0, "MMX_PSRAWrr", 0, 0|5|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1209 = MMX_PSRAWrr
+ { 1210, 3, 1, 0, "MMX_PSRLDri", 0, 0|18|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1210 = MMX_PSRLDri
+ { 1211, 7, 1, 0, "MMX_PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1211 = MMX_PSRLDrm
+ { 1212, 3, 1, 0, "MMX_PSRLDrr", 0, 0|5|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1212 = MMX_PSRLDrr
+ { 1213, 3, 1, 0, "MMX_PSRLQri", 0, 0|18|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1213 = MMX_PSRLQri
+ { 1214, 7, 1, 0, "MMX_PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1214 = MMX_PSRLQrm
+ { 1215, 3, 1, 0, "MMX_PSRLQrr", 0, 0|5|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1215 = MMX_PSRLQrr
+ { 1216, 3, 1, 0, "MMX_PSRLWri", 0, 0|18|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1216 = MMX_PSRLWri
+ { 1217, 7, 1, 0, "MMX_PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1217 = MMX_PSRLWrm
+ { 1218, 3, 1, 0, "MMX_PSRLWrr", 0, 0|5|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1218 = MMX_PSRLWrr
+ { 1219, 7, 1, 0, "MMX_PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1219 = MMX_PSUBBrm
+ { 1220, 3, 1, 0, "MMX_PSUBBrr", 0, 0|5|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1220 = MMX_PSUBBrr
+ { 1221, 7, 1, 0, "MMX_PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1221 = MMX_PSUBDrm
+ { 1222, 3, 1, 0, "MMX_PSUBDrr", 0, 0|5|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1222 = MMX_PSUBDrr
+ { 1223, 7, 1, 0, "MMX_PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1223 = MMX_PSUBQrm
+ { 1224, 3, 1, 0, "MMX_PSUBQrr", 0, 0|5|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1224 = MMX_PSUBQrr
+ { 1225, 7, 1, 0, "MMX_PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1225 = MMX_PSUBSBrm
+ { 1226, 3, 1, 0, "MMX_PSUBSBrr", 0, 0|5|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1226 = MMX_PSUBSBrr
+ { 1227, 7, 1, 0, "MMX_PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1227 = MMX_PSUBSWrm
+ { 1228, 3, 1, 0, "MMX_PSUBSWrr", 0, 0|5|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1228 = MMX_PSUBSWrr
+ { 1229, 7, 1, 0, "MMX_PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1229 = MMX_PSUBUSBrm
+ { 1230, 3, 1, 0, "MMX_PSUBUSBrr", 0, 0|5|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1230 = MMX_PSUBUSBrr
+ { 1231, 7, 1, 0, "MMX_PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1231 = MMX_PSUBUSWrm
+ { 1232, 3, 1, 0, "MMX_PSUBUSWrr", 0, 0|5|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1232 = MMX_PSUBUSWrr
+ { 1233, 7, 1, 0, "MMX_PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1233 = MMX_PSUBWrm
+ { 1234, 3, 1, 0, "MMX_PSUBWrr", 0, 0|5|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1234 = MMX_PSUBWrr
+ { 1235, 7, 1, 0, "MMX_PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1235 = MMX_PUNPCKHBWrm
+ { 1236, 3, 1, 0, "MMX_PUNPCKHBWrr", 0, 0|5|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1236 = MMX_PUNPCKHBWrr
+ { 1237, 7, 1, 0, "MMX_PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1237 = MMX_PUNPCKHDQrm
+ { 1238, 3, 1, 0, "MMX_PUNPCKHDQrr", 0, 0|5|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1238 = MMX_PUNPCKHDQrr
+ { 1239, 7, 1, 0, "MMX_PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1239 = MMX_PUNPCKHWDrm
+ { 1240, 3, 1, 0, "MMX_PUNPCKHWDrr", 0, 0|5|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1240 = MMX_PUNPCKHWDrr
+ { 1241, 7, 1, 0, "MMX_PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1241 = MMX_PUNPCKLBWrm
+ { 1242, 3, 1, 0, "MMX_PUNPCKLBWrr", 0, 0|5|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1242 = MMX_PUNPCKLBWrr
+ { 1243, 7, 1, 0, "MMX_PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1243 = MMX_PUNPCKLDQrm
+ { 1244, 3, 1, 0, "MMX_PUNPCKLDQrr", 0, 0|5|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1244 = MMX_PUNPCKLDQrr
+ { 1245, 7, 1, 0, "MMX_PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1245 = MMX_PUNPCKLWDrm
+ { 1246, 3, 1, 0, "MMX_PUNPCKLWDrr", 0, 0|5|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1246 = MMX_PUNPCKLWDrr
+ { 1247, 7, 1, 0, "MMX_PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1247 = MMX_PXORrm
+ { 1248, 3, 1, 0, "MMX_PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1248 = MMX_PXORrr
+ { 1249, 1, 1, 0, "MMX_V_SET0", 0|(1<<TID::Rematerializable), 0|32|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo144 }, // Inst #1249 = MMX_V_SET0
+ { 1250, 1, 1, 0, "MMX_V_SETALLONES", 0|(1<<TID::Rematerializable), 0|32|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo144 }, // Inst #1250 = MMX_V_SETALLONES
+ { 1251, 0, 0, 0, "MONITOR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1251 = MONITOR
+ { 1252, 1, 1, 0, "MOV16ao16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1252 = MOV16ao16
+ { 1253, 6, 0, 0, "MOV16mi", 0|(1<<TID::MayStore), 0|24|(1<<6)|(2<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1253 = MOV16mi
+ { 1254, 6, 0, 0, "MOV16mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(137<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #1254 = MOV16mr
+ { 1255, 6, 1, 0, "MOV16ms", 0|(1<<TID::UnmodeledSideEffects), 0|4|(140<<24), NULL, NULL, NULL, OperandInfo145 }, // Inst #1255 = MOV16ms
+ { 1256, 1, 0, 0, "MOV16o16a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1256 = MOV16o16a
+ { 1257, 1, 1, 0, "MOV16r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo93 }, // Inst #1257 = MOV16r0
+ { 1258, 2, 1, 0, "MOV16ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<6)|(2<<13)|(184<<24), NULL, NULL, NULL, OperandInfo54 }, // Inst #1258 = MOV16ri
+ { 1259, 6, 1, 0, "MOV16rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(139<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1259 = MOV16rm
+ { 1260, 2, 1, 0, "MOV16rr", 0, 0|3|(1<<6)|(137<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1260 = MOV16rr
+ { 1261, 2, 1, 0, "MOV16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(139<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1261 = MOV16rr_REV
+ { 1262, 2, 1, 0, "MOV16rs", 0|(1<<TID::UnmodeledSideEffects), 0|3|(140<<24), NULL, NULL, NULL, OperandInfo146 }, // Inst #1262 = MOV16rs
+ { 1263, 6, 1, 0, "MOV16sm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(142<<24), NULL, NULL, NULL, OperandInfo147 }, // Inst #1263 = MOV16sm
+ { 1264, 2, 1, 0, "MOV16sr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(142<<24), NULL, NULL, NULL, OperandInfo148 }, // Inst #1264 = MOV16sr
+ { 1265, 1, 1, 0, "MOV32ao32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1265 = MOV32ao32
+ { 1266, 2, 1, 0, "MOV32cr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(34<<24), NULL, NULL, NULL, OperandInfo149 }, // Inst #1266 = MOV32cr
+ { 1267, 2, 1, 0, "MOV32dr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(35<<24), NULL, NULL, NULL, OperandInfo150 }, // Inst #1267 = MOV32dr
+ { 1268, 6, 0, 0, "MOV32mi", 0|(1<<TID::MayStore), 0|24|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1268 = MOV32mi
+ { 1269, 6, 0, 0, "MOV32mr", 0|(1<<TID::MayStore), 0|4|(137<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1269 = MOV32mr
+ { 1270, 1, 0, 0, "MOV32o32a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1270 = MOV32o32a
+ { 1271, 1, 1, 0, "MOV32r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo57 }, // Inst #1271 = MOV32r0
+ { 1272, 2, 1, 0, "MOV32rc", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(32<<24), NULL, NULL, NULL, OperandInfo151 }, // Inst #1272 = MOV32rc
+ { 1273, 2, 1, 0, "MOV32rd", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(33<<24), NULL, NULL, NULL, OperandInfo152 }, // Inst #1273 = MOV32rd
+ { 1274, 2, 1, 0, "MOV32ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(3<<13)|(184<<24), NULL, NULL, NULL, OperandInfo55 }, // Inst #1274 = MOV32ri
+ { 1275, 6, 1, 0, "MOV32rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1275 = MOV32rm
+ { 1276, 2, 1, 0, "MOV32rr", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1276 = MOV32rr
+ { 1277, 2, 1, 0, "MOV32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(139<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1277 = MOV32rr_REV
+ { 1278, 6, 1, 0, "MOV64FSrm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(1<<20)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1278 = MOV64FSrm
+ { 1279, 6, 1, 0, "MOV64GSrm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(2<<20)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1279 = MOV64GSrm
+ { 1280, 1, 1, 0, "MOV64ao64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1280 = MOV64ao64
+ { 1281, 1, 1, 0, "MOV64ao8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(1<<13)|(162<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1281 = MOV64ao8
+ { 1282, 2, 1, 0, "MOV64cr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(34<<24), NULL, NULL, NULL, OperandInfo153 }, // Inst #1282 = MOV64cr
+ { 1283, 2, 1, 0, "MOV64dr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(35<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1283 = MOV64dr
+ { 1284, 6, 0, 0, "MOV64mi32", 0|(1<<TID::MayStore), 0|24|(1<<12)|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1284 = MOV64mi32
+ { 1285, 6, 0, 0, "MOV64mr", 0|(1<<TID::MayStore), 0|4|(1<<12)|(137<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #1285 = MOV64mr
+ { 1286, 6, 1, 0, "MOV64ms", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(140<<24), NULL, NULL, NULL, OperandInfo145 }, // Inst #1286 = MOV64ms
+ { 1287, 1, 0, 0, "MOV64o64a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1287 = MOV64o64a
+ { 1288, 1, 0, 0, "MOV64o8a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(1<<13)|(160<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1288 = MOV64o8a
+ { 1289, 1, 1, 0, "MOV64r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo58 }, // Inst #1289 = MOV64r0
+ { 1290, 2, 1, 0, "MOV64rc", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(32<<24), NULL, NULL, NULL, OperandInfo155 }, // Inst #1290 = MOV64rc
+ { 1291, 2, 1, 0, "MOV64rd", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(33<<24), NULL, NULL, NULL, OperandInfo156 }, // Inst #1291 = MOV64rd
+ { 1292, 2, 1, 0, "MOV64ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<12)|(4<<13)|(184<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1292 = MOV64ri
+ { 1293, 2, 1, 0, "MOV64ri32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|16|(1<<12)|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1293 = MOV64ri32
+ { 1294, 2, 1, 0, "MOV64ri64i32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(3<<13)|(184<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1294 = MOV64ri64i32
+ { 1295, 6, 1, 0, "MOV64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<12)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1295 = MOV64rm
+ { 1296, 2, 1, 0, "MOV64rr", 0, 0|3|(1<<12)|(137<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1296 = MOV64rr
+ { 1297, 2, 1, 0, "MOV64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(139<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1297 = MOV64rr_REV
+ { 1298, 2, 1, 0, "MOV64rs", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<12)|(140<<24), NULL, NULL, NULL, OperandInfo157 }, // Inst #1298 = MOV64rs
+ { 1299, 6, 1, 0, "MOV64sm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<12)|(142<<24), NULL, NULL, NULL, OperandInfo147 }, // Inst #1299 = MOV64sm
+ { 1300, 2, 1, 0, "MOV64sr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(142<<24), NULL, NULL, NULL, OperandInfo158 }, // Inst #1300 = MOV64sr
+ { 1301, 2, 1, 0, "MOV64toPQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo159 }, // Inst #1301 = MOV64toPQIrr
+ { 1302, 6, 1, 0, "MOV64toSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #1302 = MOV64toSDrm
+ { 1303, 2, 1, 0, "MOV64toSDrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo83 }, // Inst #1303 = MOV64toSDrr
+ { 1304, 1, 1, 0, "MOV8ao8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(162<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1304 = MOV8ao8
+ { 1305, 6, 0, 0, "MOV8mi", 0|(1<<TID::MayStore), 0|24|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1305 = MOV8mi
+ { 1306, 6, 0, 0, "MOV8mr", 0|(1<<TID::MayStore), 0|4|(136<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #1306 = MOV8mr
+ { 1307, 6, 0, 0, "MOV8mr_NOREX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(136<<24), NULL, NULL, NULL, OperandInfo160 }, // Inst #1307 = MOV8mr_NOREX
+ { 1308, 1, 0, 0, "MOV8o8a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(160<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1308 = MOV8o8a
+ { 1309, 1, 1, 0, "MOV8r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo94 }, // Inst #1309 = MOV8r0
+ { 1310, 2, 1, 0, "MOV8ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<13)|(176<<24), NULL, NULL, NULL, OperandInfo68 }, // Inst #1310 = MOV8ri
+ { 1311, 6, 1, 0, "MOV8rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(138<<24), NULL, NULL, NULL, OperandInfo69 }, // Inst #1311 = MOV8rm
+ { 1312, 6, 1, 0, "MOV8rm_NOREX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|6|(138<<24), NULL, NULL, NULL, OperandInfo161 }, // Inst #1312 = MOV8rm_NOREX
+ { 1313, 2, 1, 0, "MOV8rr", 0, 0|3|(136<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #1313 = MOV8rr
+ { 1314, 2, 1, 0, "MOV8rr_NOREX", 0, 0|3|(136<<24), NULL, NULL, NULL, OperandInfo162 }, // Inst #1314 = MOV8rr_NOREX
+ { 1315, 2, 1, 0, "MOV8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(138<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #1315 = MOV8rr_REV
+ { 1316, 6, 0, 0, "MOVAPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(41<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1316 = MOVAPDmr
+ { 1317, 6, 1, 0, "MOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1317 = MOVAPDrm
+ { 1318, 2, 1, 0, "MOVAPDrr", 0, 0|5|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1318 = MOVAPDrr
+ { 1319, 6, 0, 0, "MOVAPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(41<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1319 = MOVAPSmr
+ { 1320, 6, 1, 0, "MOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1320 = MOVAPSrm
+ { 1321, 2, 1, 0, "MOVAPSrr", 0, 0|5|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1321 = MOVAPSrr
+ { 1322, 6, 1, 0, "MOVDDUPrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1322 = MOVDDUPrm
+ { 1323, 2, 1, 0, "MOVDDUPrr", 0, 0|5|(11<<8)|(18<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1323 = MOVDDUPrr
+ { 1324, 6, 1, 0, "MOVDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1324 = MOVDI2PDIrm
+ { 1325, 2, 1, 0, "MOVDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1325 = MOVDI2PDIrr
+ { 1326, 6, 1, 0, "MOVDI2SSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1326 = MOVDI2SSrm
+ { 1327, 2, 1, 0, "MOVDI2SSrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo86 }, // Inst #1327 = MOVDI2SSrr
+ { 1328, 6, 0, 0, "MOVDQAmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1328 = MOVDQAmr
+ { 1329, 6, 1, 0, "MOVDQArm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1329 = MOVDQArm
+ { 1330, 2, 1, 0, "MOVDQArr", 0, 0|5|(1<<6)|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1330 = MOVDQArr
+ { 1331, 6, 0, 0, "MOVDQUmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(12<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1331 = MOVDQUmr
+ { 1332, 6, 0, 0, "MOVDQUmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(12<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1332 = MOVDQUmr_Int
+ { 1333, 6, 1, 0, "MOVDQUrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1333 = MOVDQUrm
+ { 1334, 6, 1, 0, "MOVDQUrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(12<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1334 = MOVDQUrm_Int
+ { 1335, 3, 1, 0, "MOVHLPSrr", 0, 0|5|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1335 = MOVHLPSrr
+ { 1336, 6, 0, 0, "MOVHPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(23<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1336 = MOVHPDmr
+ { 1337, 7, 1, 0, "MOVHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1337 = MOVHPDrm
+ { 1338, 6, 0, 0, "MOVHPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(23<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1338 = MOVHPSmr
+ { 1339, 7, 1, 0, "MOVHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1339 = MOVHPSrm
+ { 1340, 3, 1, 0, "MOVLHPSrr", 0, 0|5|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1340 = MOVLHPSrr
+ { 1341, 6, 0, 0, "MOVLPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1341 = MOVLPDmr
+ { 1342, 7, 1, 0, "MOVLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1342 = MOVLPDrm
+ { 1343, 3, 1, 0, "MOVLPDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1343 = MOVLPDrr
+ { 1344, 6, 0, 0, "MOVLPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1344 = MOVLPSmr
+ { 1345, 7, 1, 0, "MOVLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1345 = MOVLPSrm
+ { 1346, 3, 1, 0, "MOVLPSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1346 = MOVLPSrr
+ { 1347, 6, 0, 0, "MOVLQ128mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1347 = MOVLQ128mr
+ { 1348, 3, 1, 0, "MOVLSD2PDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo165 }, // Inst #1348 = MOVLSD2PDrr
+ { 1349, 3, 1, 0, "MOVLSS2PSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo166 }, // Inst #1349 = MOVLSS2PSrr
+ { 1350, 2, 1, 0, "MOVMSKPDrr", 0, 0|5|(1<<6)|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1350 = MOVMSKPDrr
+ { 1351, 2, 1, 0, "MOVMSKPSrr", 0, 0|5|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1351 = MOVMSKPSrr
+ { 1352, 6, 1, 0, "MOVNTDQArm", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1352 = MOVNTDQArm
+ { 1353, 6, 0, 0, "MOVNTDQmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1353 = MOVNTDQmr
+ { 1354, 6, 0, 0, "MOVNTImr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(195<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1354 = MOVNTImr
+ { 1355, 6, 0, 0, "MOVNTPDmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1355 = MOVNTPDmr
+ { 1356, 6, 0, 0, "MOVNTPSmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1356 = MOVNTPSmr
+ { 1357, 2, 1, 0, "MOVPC32r", 0|(1<<TID::NotDuplicable), 0|(3<<13)|(232<<24), ImplicitList2, NULL, NULL, OperandInfo55 }, // Inst #1357 = MOVPC32r
+ { 1358, 6, 0, 0, "MOVPD2SDmr", 0|(1<<TID::MayStore), 0|4|(11<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1358 = MOVPD2SDmr
+ { 1359, 2, 1, 0, "MOVPD2SDrr", 0|(1<<TID::CheapAsAMove), 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo167 }, // Inst #1359 = MOVPD2SDrr
+ { 1360, 6, 0, 0, "MOVPDI2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1360 = MOVPDI2DImr
+ { 1361, 2, 1, 0, "MOVPDI2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1361 = MOVPDI2DIrr
+ { 1362, 6, 0, 0, "MOVPQI2QImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1362 = MOVPQI2QImr
+ { 1363, 2, 1, 0, "MOVPQIto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #1363 = MOVPQIto64rr
+ { 1364, 6, 0, 0, "MOVPS2SSmr", 0|(1<<TID::MayStore), 0|4|(12<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1364 = MOVPS2SSmr
+ { 1365, 2, 1, 0, "MOVPS2SSrr", 0|(1<<TID::CheapAsAMove), 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo168 }, // Inst #1365 = MOVPS2SSrr
+ { 1366, 6, 1, 0, "MOVQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1366 = MOVQI2PQIrm
+ { 1367, 2, 1, 0, "MOVQxrxr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1367 = MOVQxrxr
+ { 1368, 6, 1, 0, "MOVSD2PDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1368 = MOVSD2PDrm
+ { 1369, 2, 1, 0, "MOVSD2PDrr", 0|(1<<TID::CheapAsAMove), 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1369 = MOVSD2PDrr
+ { 1370, 6, 0, 0, "MOVSDmr", 0|(1<<TID::MayStore), 0|4|(11<<8)|(17<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1370 = MOVSDmr
+ { 1371, 6, 1, 0, "MOVSDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #1371 = MOVSDrm
+ { 1372, 2, 1, 0, "MOVSDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #1372 = MOVSDrr
+ { 1373, 6, 0, 0, "MOVSDto64mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1373 = MOVSDto64mr
+ { 1374, 2, 1, 0, "MOVSDto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #1374 = MOVSDto64rr
+ { 1375, 6, 1, 0, "MOVSHDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1375 = MOVSHDUPrm
+ { 1376, 2, 1, 0, "MOVSHDUPrr", 0, 0|5|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1376 = MOVSHDUPrr
+ { 1377, 6, 1, 0, "MOVSLDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1377 = MOVSLDUPrm
+ { 1378, 2, 1, 0, "MOVSLDUPrr", 0, 0|5|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1378 = MOVSLDUPrr
+ { 1379, 6, 0, 0, "MOVSS2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo171 }, // Inst #1379 = MOVSS2DImr
+ { 1380, 2, 1, 0, "MOVSS2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #1380 = MOVSS2DIrr
+ { 1381, 6, 1, 0, "MOVSS2PSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1381 = MOVSS2PSrm
+ { 1382, 2, 1, 0, "MOVSS2PSrr", 0|(1<<TID::CheapAsAMove), 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo172 }, // Inst #1382 = MOVSS2PSrr
+ { 1383, 6, 0, 0, "MOVSSmr", 0|(1<<TID::MayStore), 0|4|(12<<8)|(17<<24), NULL, NULL, NULL, OperandInfo171 }, // Inst #1383 = MOVSSmr
+ { 1384, 6, 1, 0, "MOVSSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1384 = MOVSSrm
+ { 1385, 2, 1, 0, "MOVSSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #1385 = MOVSSrr
+ { 1386, 6, 1, 0, "MOVSX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1386 = MOVSX16rm8
+ { 1387, 6, 1, 0, "MOVSX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1387 = MOVSX16rm8W
+ { 1388, 2, 1, 0, "MOVSX16rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1388 = MOVSX16rr8
+ { 1389, 2, 1, 0, "MOVSX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1389 = MOVSX16rr8W
+ { 1390, 6, 1, 0, "MOVSX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1390 = MOVSX32rm16
+ { 1391, 6, 1, 0, "MOVSX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1391 = MOVSX32rm8
+ { 1392, 2, 1, 0, "MOVSX32rr16", 0, 0|5|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo174 }, // Inst #1392 = MOVSX32rr16
+ { 1393, 2, 1, 0, "MOVSX32rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo175 }, // Inst #1393 = MOVSX32rr8
+ { 1394, 6, 1, 0, "MOVSX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1394 = MOVSX64rm16
+ { 1395, 6, 1, 0, "MOVSX64rm32", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1395 = MOVSX64rm32
+ { 1396, 6, 1, 0, "MOVSX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1396 = MOVSX64rm8
+ { 1397, 2, 1, 0, "MOVSX64rr16", 0, 0|5|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo176 }, // Inst #1397 = MOVSX64rr16
+ { 1398, 2, 1, 0, "MOVSX64rr32", 0, 0|5|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #1398 = MOVSX64rr32
+ { 1399, 2, 1, 0, "MOVSX64rr8", 0, 0|5|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo177 }, // Inst #1399 = MOVSX64rr8
+ { 1400, 6, 0, 0, "MOVUPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1400 = MOVUPDmr
+ { 1401, 6, 0, 0, "MOVUPDmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1401 = MOVUPDmr_Int
+ { 1402, 6, 1, 0, "MOVUPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1402 = MOVUPDrm
+ { 1403, 6, 1, 0, "MOVUPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1403 = MOVUPDrm_Int
+ { 1404, 2, 1, 0, "MOVUPDrr", 0, 0|5|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1404 = MOVUPDrr
+ { 1405, 6, 0, 0, "MOVUPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1405 = MOVUPSmr
+ { 1406, 6, 0, 0, "MOVUPSmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1406 = MOVUPSmr_Int
+ { 1407, 6, 1, 0, "MOVUPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1407 = MOVUPSrm
+ { 1408, 6, 1, 0, "MOVUPSrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1408 = MOVUPSrm_Int
+ { 1409, 2, 1, 0, "MOVUPSrr", 0, 0|5|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1409 = MOVUPSrr
+ { 1410, 6, 1, 0, "MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1410 = MOVZDI2PDIrm
+ { 1411, 2, 1, 0, "MOVZDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1411 = MOVZDI2PDIrr
+ { 1412, 6, 1, 0, "MOVZPQILo2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1412 = MOVZPQILo2PQIrm
+ { 1413, 2, 1, 0, "MOVZPQILo2PQIrr", 0, 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1413 = MOVZPQILo2PQIrr
+ { 1414, 6, 1, 0, "MOVZQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1414 = MOVZQI2PQIrm
+ { 1415, 2, 1, 0, "MOVZQI2PQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo159 }, // Inst #1415 = MOVZQI2PQIrr
+ { 1416, 6, 1, 0, "MOVZSD2PDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1416 = MOVZSD2PDrm
+ { 1417, 6, 1, 0, "MOVZSS2PSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1417 = MOVZSS2PSrm
+ { 1418, 6, 1, 0, "MOVZX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1418 = MOVZX16rm8
+ { 1419, 6, 1, 0, "MOVZX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1419 = MOVZX16rm8W
+ { 1420, 2, 1, 0, "MOVZX16rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1420 = MOVZX16rr8
+ { 1421, 2, 1, 0, "MOVZX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1421 = MOVZX16rr8W
+ { 1422, 6, 1, 0, "MOVZX32_NOREXrm8", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo178 }, // Inst #1422 = MOVZX32_NOREXrm8
+ { 1423, 2, 1, 0, "MOVZX32_NOREXrr8", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo179 }, // Inst #1423 = MOVZX32_NOREXrr8
+ { 1424, 6, 1, 0, "MOVZX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1424 = MOVZX32rm16
+ { 1425, 6, 1, 0, "MOVZX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1425 = MOVZX32rm8
+ { 1426, 2, 1, 0, "MOVZX32rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo174 }, // Inst #1426 = MOVZX32rr16
+ { 1427, 2, 1, 0, "MOVZX32rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo175 }, // Inst #1427 = MOVZX32rr8
+ { 1428, 6, 1, 0, "MOVZX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1428 = MOVZX64rm16
+ { 1429, 6, 1, 0, "MOVZX64rm16_Q", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(183<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1429 = MOVZX64rm16_Q
+ { 1430, 6, 1, 0, "MOVZX64rm32", 0|(1<<TID::MayLoad), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1430 = MOVZX64rm32
+ { 1431, 6, 1, 0, "MOVZX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1431 = MOVZX64rm8
+ { 1432, 6, 1, 0, "MOVZX64rm8_Q", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(182<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1432 = MOVZX64rm8_Q
+ { 1433, 2, 1, 0, "MOVZX64rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo176 }, // Inst #1433 = MOVZX64rr16
+ { 1434, 2, 1, 0, "MOVZX64rr16_Q", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(183<<24), NULL, NULL, NULL, OperandInfo176 }, // Inst #1434 = MOVZX64rr16_Q
+ { 1435, 2, 1, 0, "MOVZX64rr32", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #1435 = MOVZX64rr32
+ { 1436, 2, 1, 0, "MOVZX64rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo177 }, // Inst #1436 = MOVZX64rr8
+ { 1437, 2, 1, 0, "MOVZX64rr8_Q", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(182<<24), NULL, NULL, NULL, OperandInfo177 }, // Inst #1437 = MOVZX64rr8_Q
+ { 1438, 2, 1, 0, "MOV_Fp3232", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #1438 = MOV_Fp3232
+ { 1439, 2, 1, 0, "MOV_Fp3264", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo180 }, // Inst #1439 = MOV_Fp3264
+ { 1440, 2, 1, 0, "MOV_Fp3280", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo181 }, // Inst #1440 = MOV_Fp3280
+ { 1441, 2, 1, 0, "MOV_Fp6432", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo182 }, // Inst #1441 = MOV_Fp6432
+ { 1442, 2, 1, 0, "MOV_Fp6464", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #1442 = MOV_Fp6464
+ { 1443, 2, 1, 0, "MOV_Fp6480", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo183 }, // Inst #1443 = MOV_Fp6480
+ { 1444, 2, 1, 0, "MOV_Fp8032", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo184 }, // Inst #1444 = MOV_Fp8032
+ { 1445, 2, 1, 0, "MOV_Fp8064", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo185 }, // Inst #1445 = MOV_Fp8064
+ { 1446, 2, 1, 0, "MOV_Fp8080", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #1446 = MOV_Fp8080
+ { 1447, 8, 1, 0, "MPSADBWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1447 = MPSADBWrmi
+ { 1448, 4, 1, 0, "MPSADBWrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1448 = MPSADBWrri
+ { 1449, 5, 0, 0, "MUL16m", 0|(1<<TID::MayLoad), 0|28|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #1449 = MUL16m
+ { 1450, 1, 0, 0, "MUL16r", 0, 0|20|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #1450 = MUL16r
+ { 1451, 5, 0, 0, "MUL32m", 0|(1<<TID::MayLoad), 0|28|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #1451 = MUL32m
+ { 1452, 1, 0, 0, "MUL32r", 0, 0|20|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo57 }, // Inst #1452 = MUL32r
+ { 1453, 5, 0, 0, "MUL64m", 0|(1<<TID::MayLoad), 0|28|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #1453 = MUL64m
+ { 1454, 1, 0, 0, "MUL64r", 0, 0|20|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo58 }, // Inst #1454 = MUL64r
+ { 1455, 5, 0, 0, "MUL8m", 0|(1<<TID::MayLoad), 0|28|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo30 }, // Inst #1455 = MUL8m
+ { 1456, 1, 0, 0, "MUL8r", 0, 0|20|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo94 }, // Inst #1456 = MUL8r
+ { 1457, 7, 1, 0, "MULPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1457 = MULPDrm
+ { 1458, 3, 1, 0, "MULPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1458 = MULPDrr
+ { 1459, 7, 1, 0, "MULPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1459 = MULPSrm
+ { 1460, 3, 1, 0, "MULPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1460 = MULPSrr
+ { 1461, 7, 1, 0, "MULSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1461 = MULSDrm
+ { 1462, 7, 1, 0, "MULSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1462 = MULSDrm_Int
+ { 1463, 3, 1, 0, "MULSDrr", 0|(1<<TID::Commutable), 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1463 = MULSDrr
+ { 1464, 3, 1, 0, "MULSDrr_Int", 0, 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1464 = MULSDrr_Int
+ { 1465, 7, 1, 0, "MULSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1465 = MULSSrm
+ { 1466, 7, 1, 0, "MULSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1466 = MULSSrm_Int
+ { 1467, 3, 1, 0, "MULSSrr", 0|(1<<TID::Commutable), 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1467 = MULSSrr
+ { 1468, 3, 1, 0, "MULSSrr_Int", 0, 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1468 = MULSSrr_Int
+ { 1469, 5, 0, 0, "MUL_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1469 = MUL_F32m
+ { 1470, 5, 0, 0, "MUL_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1470 = MUL_F64m
+ { 1471, 5, 0, 0, "MUL_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1471 = MUL_FI16m
+ { 1472, 5, 0, 0, "MUL_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1472 = MUL_FI32m
+ { 1473, 1, 0, 0, "MUL_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1473 = MUL_FPrST0
+ { 1474, 1, 0, 0, "MUL_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1474 = MUL_FST0r
+ { 1475, 3, 1, 0, "MUL_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #1475 = MUL_Fp32
+ { 1476, 7, 1, 0, "MUL_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1476 = MUL_Fp32m
+ { 1477, 3, 1, 0, "MUL_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #1477 = MUL_Fp64
+ { 1478, 7, 1, 0, "MUL_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1478 = MUL_Fp64m
+ { 1479, 7, 1, 0, "MUL_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1479 = MUL_Fp64m32
+ { 1480, 3, 1, 0, "MUL_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #1480 = MUL_Fp80
+ { 1481, 7, 1, 0, "MUL_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1481 = MUL_Fp80m32
+ { 1482, 7, 1, 0, "MUL_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1482 = MUL_Fp80m64
+ { 1483, 7, 1, 0, "MUL_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1483 = MUL_FpI16m32
+ { 1484, 7, 1, 0, "MUL_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1484 = MUL_FpI16m64
+ { 1485, 7, 1, 0, "MUL_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1485 = MUL_FpI16m80
+ { 1486, 7, 1, 0, "MUL_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1486 = MUL_FpI32m32
+ { 1487, 7, 1, 0, "MUL_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1487 = MUL_FpI32m64
+ { 1488, 7, 1, 0, "MUL_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1488 = MUL_FpI32m80
+ { 1489, 1, 0, 0, "MUL_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1489 = MUL_FrST0
+ { 1490, 0, 0, 0, "MWAIT", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1490 = MWAIT
+ { 1491, 5, 0, 0, "NEG16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1491 = NEG16m
+ { 1492, 2, 1, 0, "NEG16r", 0, 0|19|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1492 = NEG16r
+ { 1493, 5, 0, 0, "NEG32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1493 = NEG32m
+ { 1494, 2, 1, 0, "NEG32r", 0, 0|19|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1494 = NEG32r
+ { 1495, 5, 0, 0, "NEG64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1495 = NEG64m
+ { 1496, 2, 1, 0, "NEG64r", 0, 0|19|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1496 = NEG64r
+ { 1497, 5, 0, 0, "NEG8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1497 = NEG8m
+ { 1498, 2, 1, 0, "NEG8r", 0, 0|19|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1498 = NEG8r
+ { 1499, 0, 0, 0, "NOOP", 0, 0|1|(144<<24), NULL, NULL, NULL, 0 }, // Inst #1499 = NOOP
+ { 1500, 5, 0, 0, "NOOPL", 0, 0|24|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1500 = NOOPL
+ { 1501, 5, 0, 0, "NOOPW", 0, 0|24|(1<<6)|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1501 = NOOPW
+ { 1502, 5, 0, 0, "NOT16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1502 = NOT16m
+ { 1503, 2, 1, 0, "NOT16r", 0, 0|18|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo91 }, // Inst #1503 = NOT16r
+ { 1504, 5, 0, 0, "NOT32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1504 = NOT32m
+ { 1505, 2, 1, 0, "NOT32r", 0, 0|18|(247<<24), NULL, NULL, NULL, OperandInfo52 }, // Inst #1505 = NOT32r
+ { 1506, 5, 0, 0, "NOT64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1506 = NOT64m
+ { 1507, 2, 1, 0, "NOT64r", 0, 0|18|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo53 }, // Inst #1507 = NOT64r
+ { 1508, 5, 0, 0, "NOT8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(246<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1508 = NOT8m
+ { 1509, 2, 1, 0, "NOT8r", 0, 0|18|(246<<24), NULL, NULL, NULL, OperandInfo92 }, // Inst #1509 = NOT8r
+ { 1510, 1, 0, 0, "OR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1510 = OR16i16
+ { 1511, 6, 0, 0, "OR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1511 = OR16mi
+ { 1512, 6, 0, 0, "OR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1512 = OR16mi8
+ { 1513, 6, 0, 0, "OR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1513 = OR16mr
+ { 1514, 3, 1, 0, "OR16ri", 0, 0|17|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1514 = OR16ri
+ { 1515, 3, 1, 0, "OR16ri8", 0, 0|17|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1515 = OR16ri8
+ { 1516, 7, 1, 0, "OR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1516 = OR16rm
+ { 1517, 3, 1, 0, "OR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1517 = OR16rr
+ { 1518, 3, 1, 0, "OR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1518 = OR16rr_REV
+ { 1519, 1, 0, 0, "OR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1519 = OR32i32
+ { 1520, 6, 0, 0, "OR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1520 = OR32mi
+ { 1521, 6, 0, 0, "OR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1521 = OR32mi8
+ { 1522, 6, 0, 0, "OR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1522 = OR32mr
+ { 1523, 3, 1, 0, "OR32ri", 0, 0|17|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1523 = OR32ri
+ { 1524, 3, 1, 0, "OR32ri8", 0, 0|17|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1524 = OR32ri8
+ { 1525, 7, 1, 0, "OR32rm", 0|(1<<TID::MayLoad), 0|6|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #1525 = OR32rm
+ { 1526, 3, 1, 0, "OR32rr", 0|(1<<TID::Commutable), 0|3|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1526 = OR32rr
+ { 1527, 3, 1, 0, "OR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1527 = OR32rr_REV
+ { 1528, 1, 0, 0, "OR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1528 = OR64i32
+ { 1529, 6, 0, 0, "OR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1529 = OR64mi32
+ { 1530, 6, 0, 0, "OR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1530 = OR64mi8
+ { 1531, 6, 0, 0, "OR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1531 = OR64mr
+ { 1532, 3, 1, 0, "OR64ri32", 0, 0|17|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1532 = OR64ri32
+ { 1533, 3, 1, 0, "OR64ri8", 0, 0|17|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1533 = OR64ri8
+ { 1534, 7, 1, 0, "OR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #1534 = OR64rm
+ { 1535, 3, 1, 0, "OR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1535 = OR64rr
+ { 1536, 3, 1, 0, "OR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1536 = OR64rr_REV
+ { 1537, 1, 0, 0, "OR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(12<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1537 = OR8i8
+ { 1538, 6, 0, 0, "OR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1538 = OR8mi
+ { 1539, 6, 0, 0, "OR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1539 = OR8mr
+ { 1540, 3, 1, 0, "OR8ri", 0, 0|17|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1540 = OR8ri
+ { 1541, 7, 1, 0, "OR8rm", 0|(1<<TID::MayLoad), 0|6|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1541 = OR8rm
+ { 1542, 3, 1, 0, "OR8rr", 0|(1<<TID::Commutable), 0|3|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1542 = OR8rr
+ { 1543, 3, 1, 0, "OR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1543 = OR8rr_REV
+ { 1544, 7, 1, 0, "ORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1544 = ORPDrm
+ { 1545, 3, 1, 0, "ORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1545 = ORPDrr
+ { 1546, 7, 1, 0, "ORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1546 = ORPSrm
+ { 1547, 3, 1, 0, "ORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1547 = ORPSrr
+ { 1548, 1, 0, 0, "OUT16ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<13)|(231<<24), ImplicitList12, NULL, NULL, OperandInfo5 }, // Inst #1548 = OUT16ir
+ { 1549, 0, 0, 0, "OUT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(239<<24), ImplicitList36, NULL, NULL, 0 }, // Inst #1549 = OUT16rr
+ { 1550, 1, 0, 0, "OUT32ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(231<<24), ImplicitList13, NULL, NULL, OperandInfo5 }, // Inst #1550 = OUT32ir
+ { 1551, 0, 0, 0, "OUT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(239<<24), ImplicitList37, NULL, NULL, 0 }, // Inst #1551 = OUT32rr
+ { 1552, 1, 0, 0, "OUT8ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(230<<24), ImplicitList11, NULL, NULL, OperandInfo5 }, // Inst #1552 = OUT8ir
+ { 1553, 0, 0, 0, "OUT8rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(238<<24), ImplicitList38, NULL, NULL, 0 }, // Inst #1553 = OUT8rr
+ { 1554, 0, 0, 0, "OUTSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(110<<24), NULL, NULL, NULL, 0 }, // Inst #1554 = OUTSB
+ { 1555, 0, 0, 0, "OUTSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(111<<24), NULL, NULL, NULL, 0 }, // Inst #1555 = OUTSD
+ { 1556, 0, 0, 0, "OUTSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(111<<24), NULL, NULL, NULL, 0 }, // Inst #1556 = OUTSW
+ { 1557, 6, 1, 0, "PABSBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1557 = PABSBrm128
+ { 1558, 6, 1, 0, "PABSBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1558 = PABSBrm64
+ { 1559, 2, 1, 0, "PABSBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1559 = PABSBrr128
+ { 1560, 2, 1, 0, "PABSBrr64", 0, 0|5|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1560 = PABSBrr64
+ { 1561, 6, 1, 0, "PABSDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1561 = PABSDrm128
+ { 1562, 6, 1, 0, "PABSDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1562 = PABSDrm64
+ { 1563, 2, 1, 0, "PABSDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1563 = PABSDrr128
+ { 1564, 2, 1, 0, "PABSDrr64", 0, 0|5|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1564 = PABSDrr64
+ { 1565, 6, 1, 0, "PABSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1565 = PABSWrm128
+ { 1566, 6, 1, 0, "PABSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1566 = PABSWrm64
+ { 1567, 2, 1, 0, "PABSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1567 = PABSWrr128
+ { 1568, 2, 1, 0, "PABSWrr64", 0, 0|5|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1568 = PABSWrr64
+ { 1569, 7, 1, 0, "PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1569 = PACKSSDWrm
+ { 1570, 3, 1, 0, "PACKSSDWrr", 0, 0|5|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1570 = PACKSSDWrr
+ { 1571, 7, 1, 0, "PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1571 = PACKSSWBrm
+ { 1572, 3, 1, 0, "PACKSSWBrr", 0, 0|5|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1572 = PACKSSWBrr
+ { 1573, 7, 1, 0, "PACKUSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1573 = PACKUSDWrm
+ { 1574, 3, 1, 0, "PACKUSDWrr", 0, 0|5|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1574 = PACKUSDWrr
+ { 1575, 7, 1, 0, "PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1575 = PACKUSWBrm
+ { 1576, 3, 1, 0, "PACKUSWBrr", 0, 0|5|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1576 = PACKUSWBrr
+ { 1577, 7, 1, 0, "PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1577 = PADDBrm
+ { 1578, 3, 1, 0, "PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1578 = PADDBrr
+ { 1579, 7, 1, 0, "PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1579 = PADDDrm
+ { 1580, 3, 1, 0, "PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1580 = PADDDrr
+ { 1581, 7, 1, 0, "PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1581 = PADDQrm
+ { 1582, 3, 1, 0, "PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1582 = PADDQrr
+ { 1583, 7, 1, 0, "PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1583 = PADDSBrm
+ { 1584, 3, 1, 0, "PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1584 = PADDSBrr
+ { 1585, 7, 1, 0, "PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1585 = PADDSWrm
+ { 1586, 3, 1, 0, "PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1586 = PADDSWrr
+ { 1587, 7, 1, 0, "PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1587 = PADDUSBrm
+ { 1588, 3, 1, 0, "PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1588 = PADDUSBrr
+ { 1589, 7, 1, 0, "PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1589 = PADDUSWrm
+ { 1590, 3, 1, 0, "PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1590 = PADDUSWrr
+ { 1591, 7, 1, 0, "PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1591 = PADDWrm
+ { 1592, 3, 1, 0, "PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1592 = PADDWrr
+ { 1593, 8, 1, 0, "PALIGNR128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1593 = PALIGNR128rm
+ { 1594, 4, 1, 0, "PALIGNR128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1594 = PALIGNR128rr
+ { 1595, 8, 1, 0, "PALIGNR64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo139 }, // Inst #1595 = PALIGNR64rm
+ { 1596, 4, 1, 0, "PALIGNR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo186 }, // Inst #1596 = PALIGNR64rr
+ { 1597, 7, 1, 0, "PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1597 = PANDNrm
+ { 1598, 3, 1, 0, "PANDNrr", 0, 0|5|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1598 = PANDNrr
+ { 1599, 7, 1, 0, "PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1599 = PANDrm
+ { 1600, 3, 1, 0, "PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1600 = PANDrr
+ { 1601, 7, 1, 0, "PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1601 = PAVGBrm
+ { 1602, 3, 1, 0, "PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1602 = PAVGBrr
+ { 1603, 7, 1, 0, "PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1603 = PAVGWrm
+ { 1604, 3, 1, 0, "PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1604 = PAVGWrr
+ { 1605, 7, 1, 0, "PBLENDVBrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #1605 = PBLENDVBrm0
+ { 1606, 3, 1, 0, "PBLENDVBrr0", 0, 0|5|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo25 }, // Inst #1606 = PBLENDVBrr0
+ { 1607, 8, 1, 0, "PBLENDWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1607 = PBLENDWrmi
+ { 1608, 4, 1, 0, "PBLENDWrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1608 = PBLENDWrri
+ { 1609, 7, 1, 0, "PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1609 = PCMPEQBrm
+ { 1610, 3, 1, 0, "PCMPEQBrr", 0, 0|5|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1610 = PCMPEQBrr
+ { 1611, 7, 1, 0, "PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1611 = PCMPEQDrm
+ { 1612, 3, 1, 0, "PCMPEQDrr", 0, 0|5|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1612 = PCMPEQDrr
+ { 1613, 7, 1, 0, "PCMPEQQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1613 = PCMPEQQrm
+ { 1614, 3, 1, 0, "PCMPEQQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1614 = PCMPEQQrr
+ { 1615, 7, 1, 0, "PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1615 = PCMPEQWrm
+ { 1616, 3, 1, 0, "PCMPEQWrr", 0, 0|5|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1616 = PCMPEQWrr
+ { 1617, 7, 0, 0, "PCMPESTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1617 = PCMPESTRIArm
+ { 1618, 3, 0, 0, "PCMPESTRIArr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1618 = PCMPESTRIArr
+ { 1619, 7, 0, 0, "PCMPESTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1619 = PCMPESTRICrm
+ { 1620, 3, 0, 0, "PCMPESTRICrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1620 = PCMPESTRICrr
+ { 1621, 7, 0, 0, "PCMPESTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1621 = PCMPESTRIOrm
+ { 1622, 3, 0, 0, "PCMPESTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1622 = PCMPESTRIOrr
+ { 1623, 7, 0, 0, "PCMPESTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1623 = PCMPESTRISrm
+ { 1624, 3, 0, 0, "PCMPESTRISrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1624 = PCMPESTRISrr
+ { 1625, 7, 0, 0, "PCMPESTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1625 = PCMPESTRIZrm
+ { 1626, 3, 0, 0, "PCMPESTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1626 = PCMPESTRIZrr
+ { 1627, 7, 0, 0, "PCMPESTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1627 = PCMPESTRIrm
+ { 1628, 3, 0, 0, "PCMPESTRIrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1628 = PCMPESTRIrr
+ { 1629, 8, 1, 0, "PCMPESTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo189 }, // Inst #1629 = PCMPESTRM128MEM
+ { 1630, 4, 1, 0, "PCMPESTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #1630 = PCMPESTRM128REG
+ { 1631, 7, 0, 0, "PCMPESTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList40, Barriers1, OperandInfo187 }, // Inst #1631 = PCMPESTRM128rm
+ { 1632, 3, 0, 0, "PCMPESTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList40, Barriers1, OperandInfo188 }, // Inst #1632 = PCMPESTRM128rr
+ { 1633, 7, 1, 0, "PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1633 = PCMPGTBrm
+ { 1634, 3, 1, 0, "PCMPGTBrr", 0, 0|5|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1634 = PCMPGTBrr
+ { 1635, 7, 1, 0, "PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1635 = PCMPGTDrm
+ { 1636, 3, 1, 0, "PCMPGTDrr", 0, 0|5|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1636 = PCMPGTDrr
+ { 1637, 7, 1, 0, "PCMPGTQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1637 = PCMPGTQrm
+ { 1638, 3, 1, 0, "PCMPGTQrr", 0, 0|5|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1638 = PCMPGTQrr
+ { 1639, 7, 1, 0, "PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1639 = PCMPGTWrm
+ { 1640, 3, 1, 0, "PCMPGTWrr", 0, 0|5|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1640 = PCMPGTWrr
+ { 1641, 7, 0, 0, "PCMPISTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1641 = PCMPISTRIArm
+ { 1642, 3, 0, 0, "PCMPISTRIArr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1642 = PCMPISTRIArr
+ { 1643, 7, 0, 0, "PCMPISTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1643 = PCMPISTRICrm
+ { 1644, 3, 0, 0, "PCMPISTRICrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1644 = PCMPISTRICrr
+ { 1645, 7, 0, 0, "PCMPISTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1645 = PCMPISTRIOrm
+ { 1646, 3, 0, 0, "PCMPISTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1646 = PCMPISTRIOrr
+ { 1647, 7, 0, 0, "PCMPISTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1647 = PCMPISTRISrm
+ { 1648, 3, 0, 0, "PCMPISTRISrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1648 = PCMPISTRISrr
+ { 1649, 7, 0, 0, "PCMPISTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1649 = PCMPISTRIZrm
+ { 1650, 3, 0, 0, "PCMPISTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1650 = PCMPISTRIZrr
+ { 1651, 7, 0, 0, "PCMPISTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo187 }, // Inst #1651 = PCMPISTRIrm
+ { 1652, 3, 0, 0, "PCMPISTRIrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList39, Barriers1, OperandInfo188 }, // Inst #1652 = PCMPISTRIrr
+ { 1653, 8, 1, 0, "PCMPISTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo189 }, // Inst #1653 = PCMPISTRM128MEM
+ { 1654, 4, 1, 0, "PCMPISTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #1654 = PCMPISTRM128REG
+ { 1655, 7, 0, 0, "PCMPISTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList40, Barriers1, OperandInfo187 }, // Inst #1655 = PCMPISTRM128rm
+ { 1656, 3, 0, 0, "PCMPISTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList40, Barriers1, OperandInfo188 }, // Inst #1656 = PCMPISTRM128rr
+ { 1657, 7, 0, 0, "PEXTRBmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1657 = PEXTRBmr
+ { 1658, 3, 1, 0, "PEXTRBrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1658 = PEXTRBrr
+ { 1659, 7, 0, 0, "PEXTRDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1659 = PEXTRDmr
+ { 1660, 3, 1, 0, "PEXTRDrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1660 = PEXTRDrr
+ { 1661, 7, 0, 0, "PEXTRQmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1661 = PEXTRQmr
+ { 1662, 3, 1, 0, "PEXTRQrr", 0, 0|3|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo190 }, // Inst #1662 = PEXTRQrr
+ { 1663, 7, 0, 0, "PEXTRWmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(21<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1663 = PEXTRWmr
+ { 1664, 3, 1, 0, "PEXTRWri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1664 = PEXTRWri
+ { 1665, 7, 1, 0, "PHADDDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1665 = PHADDDrm128
+ { 1666, 7, 1, 0, "PHADDDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1666 = PHADDDrm64
+ { 1667, 3, 1, 0, "PHADDDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1667 = PHADDDrr128
+ { 1668, 3, 1, 0, "PHADDDrr64", 0, 0|5|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1668 = PHADDDrr64
+ { 1669, 7, 1, 0, "PHADDSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1669 = PHADDSWrm128
+ { 1670, 7, 1, 0, "PHADDSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1670 = PHADDSWrm64
+ { 1671, 3, 1, 0, "PHADDSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1671 = PHADDSWrr128
+ { 1672, 3, 1, 0, "PHADDSWrr64", 0, 0|5|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1672 = PHADDSWrr64
+ { 1673, 7, 1, 0, "PHADDWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1673 = PHADDWrm128
+ { 1674, 7, 1, 0, "PHADDWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1674 = PHADDWrm64
+ { 1675, 3, 1, 0, "PHADDWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1675 = PHADDWrr128
+ { 1676, 3, 1, 0, "PHADDWrr64", 0, 0|5|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1676 = PHADDWrr64
+ { 1677, 6, 1, 0, "PHMINPOSUWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1677 = PHMINPOSUWrm128
+ { 1678, 2, 1, 0, "PHMINPOSUWrr128", 0, 0|5|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1678 = PHMINPOSUWrr128
+ { 1679, 7, 1, 0, "PHSUBDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1679 = PHSUBDrm128
+ { 1680, 7, 1, 0, "PHSUBDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1680 = PHSUBDrm64
+ { 1681, 3, 1, 0, "PHSUBDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1681 = PHSUBDrr128
+ { 1682, 3, 1, 0, "PHSUBDrr64", 0, 0|5|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1682 = PHSUBDrr64
+ { 1683, 7, 1, 0, "PHSUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1683 = PHSUBSWrm128
+ { 1684, 7, 1, 0, "PHSUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1684 = PHSUBSWrm64
+ { 1685, 3, 1, 0, "PHSUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1685 = PHSUBSWrr128
+ { 1686, 3, 1, 0, "PHSUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1686 = PHSUBSWrr64
+ { 1687, 7, 1, 0, "PHSUBWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1687 = PHSUBWrm128
+ { 1688, 7, 1, 0, "PHSUBWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1688 = PHSUBWrm64
+ { 1689, 3, 1, 0, "PHSUBWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1689 = PHSUBWrr128
+ { 1690, 3, 1, 0, "PHSUBWrr64", 0, 0|5|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1690 = PHSUBWrr64
+ { 1691, 8, 1, 0, "PINSRBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1691 = PINSRBrm
+ { 1692, 4, 1, 0, "PINSRBrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo191 }, // Inst #1692 = PINSRBrr
+ { 1693, 8, 1, 0, "PINSRDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1693 = PINSRDrm
+ { 1694, 4, 1, 0, "PINSRDrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo191 }, // Inst #1694 = PINSRDrr
+ { 1695, 8, 1, 0, "PINSRQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1695 = PINSRQrm
+ { 1696, 4, 1, 0, "PINSRQrr", 0, 0|5|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo192 }, // Inst #1696 = PINSRQrr
+ { 1697, 8, 1, 0, "PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1697 = PINSRWrmi
+ { 1698, 4, 1, 0, "PINSRWrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo191 }, // Inst #1698 = PINSRWrri
+ { 1699, 7, 1, 0, "PMADDUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1699 = PMADDUBSWrm128
+ { 1700, 7, 1, 0, "PMADDUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1700 = PMADDUBSWrm64
+ { 1701, 3, 1, 0, "PMADDUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1701 = PMADDUBSWrr128
+ { 1702, 3, 1, 0, "PMADDUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1702 = PMADDUBSWrr64
+ { 1703, 7, 1, 0, "PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1703 = PMADDWDrm
+ { 1704, 3, 1, 0, "PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1704 = PMADDWDrr
+ { 1705, 7, 1, 0, "PMAXSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1705 = PMAXSBrm
+ { 1706, 3, 1, 0, "PMAXSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1706 = PMAXSBrr
+ { 1707, 7, 1, 0, "PMAXSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1707 = PMAXSDrm
+ { 1708, 3, 1, 0, "PMAXSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1708 = PMAXSDrr
+ { 1709, 7, 1, 0, "PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1709 = PMAXSWrm
+ { 1710, 3, 1, 0, "PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1710 = PMAXSWrr
+ { 1711, 7, 1, 0, "PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1711 = PMAXUBrm
+ { 1712, 3, 1, 0, "PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1712 = PMAXUBrr
+ { 1713, 7, 1, 0, "PMAXUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1713 = PMAXUDrm
+ { 1714, 3, 1, 0, "PMAXUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1714 = PMAXUDrr
+ { 1715, 7, 1, 0, "PMAXUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1715 = PMAXUWrm
+ { 1716, 3, 1, 0, "PMAXUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1716 = PMAXUWrr
+ { 1717, 7, 1, 0, "PMINSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1717 = PMINSBrm
+ { 1718, 3, 1, 0, "PMINSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1718 = PMINSBrr
+ { 1719, 7, 1, 0, "PMINSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1719 = PMINSDrm
+ { 1720, 3, 1, 0, "PMINSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1720 = PMINSDrr
+ { 1721, 7, 1, 0, "PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1721 = PMINSWrm
+ { 1722, 3, 1, 0, "PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1722 = PMINSWrr
+ { 1723, 7, 1, 0, "PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1723 = PMINUBrm
+ { 1724, 3, 1, 0, "PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1724 = PMINUBrr
+ { 1725, 7, 1, 0, "PMINUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1725 = PMINUDrm
+ { 1726, 3, 1, 0, "PMINUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1726 = PMINUDrr
+ { 1727, 7, 1, 0, "PMINUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1727 = PMINUWrm
+ { 1728, 3, 1, 0, "PMINUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1728 = PMINUWrr
+ { 1729, 2, 1, 0, "PMOVMSKBrr", 0, 0|5|(1<<6)|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1729 = PMOVMSKBrr
+ { 1730, 6, 1, 0, "PMOVSXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1730 = PMOVSXBDrm
+ { 1731, 2, 1, 0, "PMOVSXBDrr", 0, 0|5|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1731 = PMOVSXBDrr
+ { 1732, 6, 1, 0, "PMOVSXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1732 = PMOVSXBQrm
+ { 1733, 2, 1, 0, "PMOVSXBQrr", 0, 0|5|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1733 = PMOVSXBQrr
+ { 1734, 6, 1, 0, "PMOVSXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1734 = PMOVSXBWrm
+ { 1735, 2, 1, 0, "PMOVSXBWrr", 0, 0|5|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1735 = PMOVSXBWrr
+ { 1736, 6, 1, 0, "PMOVSXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1736 = PMOVSXDQrm
+ { 1737, 2, 1, 0, "PMOVSXDQrr", 0, 0|5|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1737 = PMOVSXDQrr
+ { 1738, 6, 1, 0, "PMOVSXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1738 = PMOVSXWDrm
+ { 1739, 2, 1, 0, "PMOVSXWDrr", 0, 0|5|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1739 = PMOVSXWDrr
+ { 1740, 6, 1, 0, "PMOVSXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1740 = PMOVSXWQrm
+ { 1741, 2, 1, 0, "PMOVSXWQrr", 0, 0|5|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1741 = PMOVSXWQrr
+ { 1742, 6, 1, 0, "PMOVZXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1742 = PMOVZXBDrm
+ { 1743, 2, 1, 0, "PMOVZXBDrr", 0, 0|5|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1743 = PMOVZXBDrr
+ { 1744, 6, 1, 0, "PMOVZXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1744 = PMOVZXBQrm
+ { 1745, 2, 1, 0, "PMOVZXBQrr", 0, 0|5|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1745 = PMOVZXBQrr
+ { 1746, 6, 1, 0, "PMOVZXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1746 = PMOVZXBWrm
+ { 1747, 2, 1, 0, "PMOVZXBWrr", 0, 0|5|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1747 = PMOVZXBWrr
+ { 1748, 6, 1, 0, "PMOVZXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1748 = PMOVZXDQrm
+ { 1749, 2, 1, 0, "PMOVZXDQrr", 0, 0|5|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1749 = PMOVZXDQrr
+ { 1750, 6, 1, 0, "PMOVZXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1750 = PMOVZXWDrm
+ { 1751, 2, 1, 0, "PMOVZXWDrr", 0, 0|5|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1751 = PMOVZXWDrr
+ { 1752, 6, 1, 0, "PMOVZXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1752 = PMOVZXWQrm
+ { 1753, 2, 1, 0, "PMOVZXWQrr", 0, 0|5|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1753 = PMOVZXWQrr
+ { 1754, 7, 1, 0, "PMULDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1754 = PMULDQrm
+ { 1755, 3, 1, 0, "PMULDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1755 = PMULDQrr
+ { 1756, 7, 1, 0, "PMULHRSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1756 = PMULHRSWrm128
+ { 1757, 7, 1, 0, "PMULHRSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1757 = PMULHRSWrm64
+ { 1758, 3, 1, 0, "PMULHRSWrr128", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1758 = PMULHRSWrr128
+ { 1759, 3, 1, 0, "PMULHRSWrr64", 0|(1<<TID::Commutable), 0|5|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1759 = PMULHRSWrr64
+ { 1760, 7, 1, 0, "PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1760 = PMULHUWrm
+ { 1761, 3, 1, 0, "PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1761 = PMULHUWrr
+ { 1762, 7, 1, 0, "PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1762 = PMULHWrm
+ { 1763, 3, 1, 0, "PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1763 = PMULHWrr
+ { 1764, 7, 1, 0, "PMULLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1764 = PMULLDrm
+ { 1765, 7, 1, 0, "PMULLDrm_int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1765 = PMULLDrm_int
+ { 1766, 3, 1, 0, "PMULLDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1766 = PMULLDrr
+ { 1767, 3, 1, 0, "PMULLDrr_int", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1767 = PMULLDrr_int
+ { 1768, 7, 1, 0, "PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1768 = PMULLWrm
+ { 1769, 3, 1, 0, "PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1769 = PMULLWrr
+ { 1770, 7, 1, 0, "PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1770 = PMULUDQrm
+ { 1771, 3, 1, 0, "PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1771 = PMULUDQrr
+ { 1772, 1, 1, 0, "POP16r", 0|(1<<TID::MayLoad), 0|2|(1<<6)|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1772 = POP16r
+ { 1773, 5, 1, 0, "POP16rmm", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1773 = POP16rmm
+ { 1774, 1, 1, 0, "POP16rmr", 0|(1<<TID::MayLoad), 0|16|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1774 = POP16rmr
+ { 1775, 1, 1, 0, "POP32r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1775 = POP32r
+ { 1776, 5, 1, 0, "POP32rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1776 = POP32rmm
+ { 1777, 1, 1, 0, "POP32rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1777 = POP32rmr
+ { 1778, 1, 1, 0, "POP64r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1778 = POP64r
+ { 1779, 5, 1, 0, "POP64rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo30 }, // Inst #1779 = POP64rmm
+ { 1780, 1, 1, 0, "POP64rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1780 = POP64rmr
+ { 1781, 6, 1, 0, "POPCNT16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1781 = POPCNT16rm
+ { 1782, 2, 1, 0, "POPCNT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1782 = POPCNT16rr
+ { 1783, 6, 1, 0, "POPCNT32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1783 = POPCNT32rm
+ { 1784, 2, 1, 0, "POPCNT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1784 = POPCNT32rr
+ { 1785, 6, 1, 0, "POPCNT64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(1<<12)|(184<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1785 = POPCNT64rm
+ { 1786, 2, 1, 0, "POPCNT64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(1<<12)|(184<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1786 = POPCNT64rr
+ { 1787, 0, 0, 0, "POPF", 0|(1<<TID::MayLoad), 0|1|(1<<6)|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1787 = POPF
+ { 1788, 0, 0, 0, "POPFD", 0|(1<<TID::MayLoad), 0|1|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1788 = POPFD
+ { 1789, 0, 0, 0, "POPFQ", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(157<<24), ImplicitList4, ImplicitList5, Barriers1, 0 }, // Inst #1789 = POPFQ
+ { 1790, 0, 0, 0, "POPFS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1790 = POPFS16
+ { 1791, 0, 0, 0, "POPFS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1791 = POPFS32
+ { 1792, 0, 0, 0, "POPFS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1792 = POPFS64
+ { 1793, 0, 0, 0, "POPGS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1793 = POPGS16
+ { 1794, 0, 0, 0, "POPGS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1794 = POPGS32
+ { 1795, 0, 0, 0, "POPGS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1795 = POPGS64
+ { 1796, 7, 1, 0, "PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1796 = PORrm
+ { 1797, 3, 1, 0, "PORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1797 = PORrr
+ { 1798, 5, 0, 0, "PREFETCHNTA", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1798 = PREFETCHNTA
+ { 1799, 5, 0, 0, "PREFETCHT0", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1799 = PREFETCHT0
+ { 1800, 5, 0, 0, "PREFETCHT1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1800 = PREFETCHT1
+ { 1801, 5, 0, 0, "PREFETCHT2", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1801 = PREFETCHT2
+ { 1802, 7, 1, 0, "PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1802 = PSADBWrm
+ { 1803, 3, 1, 0, "PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1803 = PSADBWrr
+ { 1804, 7, 1, 0, "PSHUFBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo24 }, // Inst #1804 = PSHUFBrm128
+ { 1805, 7, 1, 0, "PSHUFBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo136 }, // Inst #1805 = PSHUFBrm64
+ { 1806, 3, 1, 0, "PSHUFBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo25 }, // Inst #1806 = PSHUFBrr128
+ { 1807, 3, 1, 0, "PSHUFBrr64", 0, 0|5|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo137 }, // Inst #1807 = PSHUFBrr64
+ { 1808, 7, 1, 0, "PSHUFDmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1808 = PSHUFDmi
+ { 1809, 3, 1, 0, "PSHUFDri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1809 = PSHUFDri
+ { 1810, 7, 1, 0, "PSHUFHWmi", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1810 = PSHUFHWmi
+ { 1811, 3, 1, 0, "PSHUFHWri", 0, 0|5|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1811 = PSHUFHWri
+ { 1812, 7, 1, 0, "PSHUFLWmi", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1812 = PSHUFLWmi
+ { 1813, 3, 1, 0, "PSHUFLWri", 0, 0|5|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1813 = PSHUFLWri
+ { 1814, 7, 1, 0, "PSIGNBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1814 = PSIGNBrm128
+ { 1815, 7, 1, 0, "PSIGNBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1815 = PSIGNBrm64
+ { 1816, 3, 1, 0, "PSIGNBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1816 = PSIGNBrr128
+ { 1817, 3, 1, 0, "PSIGNBrr64", 0, 0|5|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1817 = PSIGNBrr64
+ { 1818, 7, 1, 0, "PSIGNDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1818 = PSIGNDrm128
+ { 1819, 7, 1, 0, "PSIGNDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1819 = PSIGNDrm64
+ { 1820, 3, 1, 0, "PSIGNDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1820 = PSIGNDrr128
+ { 1821, 3, 1, 0, "PSIGNDrr64", 0, 0|5|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1821 = PSIGNDrr64
+ { 1822, 7, 1, 0, "PSIGNWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1822 = PSIGNWrm128
+ { 1823, 7, 1, 0, "PSIGNWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1823 = PSIGNWrm64
+ { 1824, 3, 1, 0, "PSIGNWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1824 = PSIGNWrr128
+ { 1825, 3, 1, 0, "PSIGNWrr64", 0, 0|5|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1825 = PSIGNWrr64
+ { 1826, 3, 1, 0, "PSLLDQri", 0, 0|23|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1826 = PSLLDQri
+ { 1827, 3, 1, 0, "PSLLDri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1827 = PSLLDri
+ { 1828, 7, 1, 0, "PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1828 = PSLLDrm
+ { 1829, 3, 1, 0, "PSLLDrr", 0, 0|5|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1829 = PSLLDrr
+ { 1830, 3, 1, 0, "PSLLQri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1830 = PSLLQri
+ { 1831, 7, 1, 0, "PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1831 = PSLLQrm
+ { 1832, 3, 1, 0, "PSLLQrr", 0, 0|5|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1832 = PSLLQrr
+ { 1833, 3, 1, 0, "PSLLWri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1833 = PSLLWri
+ { 1834, 7, 1, 0, "PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1834 = PSLLWrm
+ { 1835, 3, 1, 0, "PSLLWrr", 0, 0|5|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1835 = PSLLWrr
+ { 1836, 3, 1, 0, "PSRADri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1836 = PSRADri
+ { 1837, 7, 1, 0, "PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1837 = PSRADrm
+ { 1838, 3, 1, 0, "PSRADrr", 0, 0|5|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1838 = PSRADrr
+ { 1839, 3, 1, 0, "PSRAWri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1839 = PSRAWri
+ { 1840, 7, 1, 0, "PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1840 = PSRAWrm
+ { 1841, 3, 1, 0, "PSRAWrr", 0, 0|5|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1841 = PSRAWrr
+ { 1842, 3, 1, 0, "PSRLDQri", 0, 0|19|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1842 = PSRLDQri
+ { 1843, 3, 1, 0, "PSRLDri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1843 = PSRLDri
+ { 1844, 7, 1, 0, "PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1844 = PSRLDrm
+ { 1845, 3, 1, 0, "PSRLDrr", 0, 0|5|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1845 = PSRLDrr
+ { 1846, 3, 1, 0, "PSRLQri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1846 = PSRLQri
+ { 1847, 7, 1, 0, "PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1847 = PSRLQrm
+ { 1848, 3, 1, 0, "PSRLQrr", 0, 0|5|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1848 = PSRLQrr
+ { 1849, 3, 1, 0, "PSRLWri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo193 }, // Inst #1849 = PSRLWri
+ { 1850, 7, 1, 0, "PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1850 = PSRLWrm
+ { 1851, 3, 1, 0, "PSRLWrr", 0, 0|5|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1851 = PSRLWrr
+ { 1852, 7, 1, 0, "PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1852 = PSUBBrm
+ { 1853, 3, 1, 0, "PSUBBrr", 0, 0|5|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1853 = PSUBBrr
+ { 1854, 7, 1, 0, "PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1854 = PSUBDrm
+ { 1855, 3, 1, 0, "PSUBDrr", 0, 0|5|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1855 = PSUBDrr
+ { 1856, 7, 1, 0, "PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1856 = PSUBQrm
+ { 1857, 3, 1, 0, "PSUBQrr", 0, 0|5|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1857 = PSUBQrr
+ { 1858, 7, 1, 0, "PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1858 = PSUBSBrm
+ { 1859, 3, 1, 0, "PSUBSBrr", 0, 0|5|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1859 = PSUBSBrr
+ { 1860, 7, 1, 0, "PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1860 = PSUBSWrm
+ { 1861, 3, 1, 0, "PSUBSWrr", 0, 0|5|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1861 = PSUBSWrr
+ { 1862, 7, 1, 0, "PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1862 = PSUBUSBrm
+ { 1863, 3, 1, 0, "PSUBUSBrr", 0, 0|5|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1863 = PSUBUSBrr
+ { 1864, 7, 1, 0, "PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1864 = PSUBUSWrm
+ { 1865, 3, 1, 0, "PSUBUSWrr", 0, 0|5|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1865 = PSUBUSWrr
+ { 1866, 7, 1, 0, "PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1866 = PSUBWrm
+ { 1867, 3, 1, 0, "PSUBWrr", 0, 0|5|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1867 = PSUBWrr
+ { 1868, 6, 0, 0, "PTESTrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #1868 = PTESTrm
+ { 1869, 2, 0, 0, "PTESTrr", 0, 0|5|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #1869 = PTESTrr
+ { 1870, 7, 1, 0, "PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1870 = PUNPCKHBWrm
+ { 1871, 3, 1, 0, "PUNPCKHBWrr", 0, 0|5|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1871 = PUNPCKHBWrr
+ { 1872, 7, 1, 0, "PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1872 = PUNPCKHDQrm
+ { 1873, 3, 1, 0, "PUNPCKHDQrr", 0, 0|5|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1873 = PUNPCKHDQrr
+ { 1874, 7, 1, 0, "PUNPCKHQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1874 = PUNPCKHQDQrm
+ { 1875, 3, 1, 0, "PUNPCKHQDQrr", 0, 0|5|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1875 = PUNPCKHQDQrr
+ { 1876, 7, 1, 0, "PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1876 = PUNPCKHWDrm
+ { 1877, 3, 1, 0, "PUNPCKHWDrr", 0, 0|5|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1877 = PUNPCKHWDrr
+ { 1878, 7, 1, 0, "PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1878 = PUNPCKLBWrm
+ { 1879, 3, 1, 0, "PUNPCKLBWrr", 0, 0|5|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1879 = PUNPCKLBWrr
+ { 1880, 7, 1, 0, "PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1880 = PUNPCKLDQrm
+ { 1881, 3, 1, 0, "PUNPCKLDQrr", 0, 0|5|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1881 = PUNPCKLDQrr
+ { 1882, 7, 1, 0, "PUNPCKLQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1882 = PUNPCKLQDQrm
+ { 1883, 3, 1, 0, "PUNPCKLQDQrr", 0, 0|5|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1883 = PUNPCKLQDQrr
+ { 1884, 7, 1, 0, "PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1884 = PUNPCKLWDrm
+ { 1885, 3, 1, 0, "PUNPCKLWDrr", 0, 0|5|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1885 = PUNPCKLWDrr
+ { 1886, 1, 0, 0, "PUSH16r", 0|(1<<TID::MayStore), 0|2|(1<<6)|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1886 = PUSH16r
+ { 1887, 5, 0, 0, "PUSH16rmm", 0|(1<<TID::MayStore), 0|30|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1887 = PUSH16rmm
+ { 1888, 1, 0, 0, "PUSH16rmr", 0|(1<<TID::MayStore), 0|22|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1888 = PUSH16rmr
+ { 1889, 1, 0, 0, "PUSH32i16", 0|(1<<TID::MayStore), 0|1|(2<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1889 = PUSH32i16
+ { 1890, 1, 0, 0, "PUSH32i32", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1890 = PUSH32i32
+ { 1891, 1, 0, 0, "PUSH32i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1891 = PUSH32i8
+ { 1892, 1, 0, 0, "PUSH32r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1892 = PUSH32r
+ { 1893, 5, 0, 0, "PUSH32rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1893 = PUSH32rmm
+ { 1894, 1, 0, 0, "PUSH32rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1894 = PUSH32rmr
+ { 1895, 1, 0, 0, "PUSH64i16", 0|(1<<TID::MayStore), 0|1|(2<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1895 = PUSH64i16
+ { 1896, 1, 0, 0, "PUSH64i32", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1896 = PUSH64i32
+ { 1897, 1, 0, 0, "PUSH64i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1897 = PUSH64i8
+ { 1898, 1, 0, 0, "PUSH64r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1898 = PUSH64r
+ { 1899, 5, 0, 0, "PUSH64rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo30 }, // Inst #1899 = PUSH64rmm
+ { 1900, 1, 0, 0, "PUSH64rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1900 = PUSH64rmr
+ { 1901, 0, 0, 0, "PUSHF", 0|(1<<TID::MayStore), 0|1|(1<<6)|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1901 = PUSHF
+ { 1902, 0, 0, 0, "PUSHFD", 0|(1<<TID::MayStore), 0|1|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1902 = PUSHFD
+ { 1903, 0, 0, 0, "PUSHFQ64", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(156<<24), ImplicitList5, ImplicitList4, NULL, 0 }, // Inst #1903 = PUSHFQ64
+ { 1904, 0, 0, 0, "PUSHFS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1904 = PUSHFS16
+ { 1905, 0, 0, 0, "PUSHFS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1905 = PUSHFS32
+ { 1906, 0, 0, 0, "PUSHFS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1906 = PUSHFS64
+ { 1907, 0, 0, 0, "PUSHGS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1907 = PUSHGS16
+ { 1908, 0, 0, 0, "PUSHGS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1908 = PUSHGS32
+ { 1909, 0, 0, 0, "PUSHGS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1909 = PUSHGS64
+ { 1910, 7, 1, 0, "PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1910 = PXORrm
+ { 1911, 3, 1, 0, "PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1911 = PXORrr
+ { 1912, 10, 1, 0, "RCL16m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1912 = RCL16m1
+ { 1913, 10, 1, 0, "RCL16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1913 = RCL16mCL
+ { 1914, 11, 1, 0, "RCL16mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1914 = RCL16mi
+ { 1915, 2, 1, 0, "RCL16r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1915 = RCL16r1
+ { 1916, 2, 1, 0, "RCL16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1916 = RCL16rCL
+ { 1917, 3, 1, 0, "RCL16ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1917 = RCL16ri
+ { 1918, 10, 1, 0, "RCL32m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1918 = RCL32m1
+ { 1919, 10, 1, 0, "RCL32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1919 = RCL32mCL
+ { 1920, 11, 1, 0, "RCL32mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1920 = RCL32mi
+ { 1921, 2, 1, 0, "RCL32r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1921 = RCL32r1
+ { 1922, 2, 1, 0, "RCL32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1922 = RCL32rCL
+ { 1923, 3, 1, 0, "RCL32ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1923 = RCL32ri
+ { 1924, 10, 1, 0, "RCL64m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1924 = RCL64m1
+ { 1925, 10, 1, 0, "RCL64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1925 = RCL64mCL
+ { 1926, 11, 1, 0, "RCL64mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1926 = RCL64mi
+ { 1927, 2, 1, 0, "RCL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1927 = RCL64r1
+ { 1928, 2, 1, 0, "RCL64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1928 = RCL64rCL
+ { 1929, 3, 1, 0, "RCL64ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1929 = RCL64ri
+ { 1930, 10, 1, 0, "RCL8m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1930 = RCL8m1
+ { 1931, 10, 1, 0, "RCL8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1931 = RCL8mCL
+ { 1932, 11, 1, 0, "RCL8mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1932 = RCL8mi
+ { 1933, 2, 1, 0, "RCL8r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1933 = RCL8r1
+ { 1934, 2, 1, 0, "RCL8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1934 = RCL8rCL
+ { 1935, 3, 1, 0, "RCL8ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1935 = RCL8ri
+ { 1936, 6, 1, 0, "RCPPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1936 = RCPPSm
+ { 1937, 6, 1, 0, "RCPPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1937 = RCPPSm_Int
+ { 1938, 2, 1, 0, "RCPPSr", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1938 = RCPPSr
+ { 1939, 2, 1, 0, "RCPPSr_Int", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1939 = RCPPSr_Int
+ { 1940, 6, 1, 0, "RCPSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1940 = RCPSSm
+ { 1941, 6, 1, 0, "RCPSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1941 = RCPSSm_Int
+ { 1942, 2, 1, 0, "RCPSSr", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #1942 = RCPSSr
+ { 1943, 2, 1, 0, "RCPSSr_Int", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1943 = RCPSSr_Int
+ { 1944, 10, 1, 0, "RCR16m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1944 = RCR16m1
+ { 1945, 10, 1, 0, "RCR16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1945 = RCR16mCL
+ { 1946, 11, 1, 0, "RCR16mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1946 = RCR16mi
+ { 1947, 2, 1, 0, "RCR16r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1947 = RCR16r1
+ { 1948, 2, 1, 0, "RCR16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1948 = RCR16rCL
+ { 1949, 3, 1, 0, "RCR16ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1949 = RCR16ri
+ { 1950, 10, 1, 0, "RCR32m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1950 = RCR32m1
+ { 1951, 10, 1, 0, "RCR32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1951 = RCR32mCL
+ { 1952, 11, 1, 0, "RCR32mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1952 = RCR32mi
+ { 1953, 2, 1, 0, "RCR32r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1953 = RCR32r1
+ { 1954, 2, 1, 0, "RCR32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1954 = RCR32rCL
+ { 1955, 3, 1, 0, "RCR32ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1955 = RCR32ri
+ { 1956, 10, 1, 0, "RCR64m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1956 = RCR64m1
+ { 1957, 10, 1, 0, "RCR64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1957 = RCR64mCL
+ { 1958, 11, 1, 0, "RCR64mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1958 = RCR64mi
+ { 1959, 2, 1, 0, "RCR64r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1959 = RCR64r1
+ { 1960, 2, 1, 0, "RCR64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1960 = RCR64rCL
+ { 1961, 3, 1, 0, "RCR64ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1961 = RCR64ri
+ { 1962, 10, 1, 0, "RCR8m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1962 = RCR8m1
+ { 1963, 10, 1, 0, "RCR8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #1963 = RCR8mCL
+ { 1964, 11, 1, 0, "RCR8mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #1964 = RCR8mi
+ { 1965, 2, 1, 0, "RCR8r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1965 = RCR8r1
+ { 1966, 2, 1, 0, "RCR8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1966 = RCR8rCL
+ { 1967, 3, 1, 0, "RCR8ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1967 = RCR8ri
+ { 1968, 0, 0, 0, "RDMSR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(50<<24), NULL, NULL, NULL, 0 }, // Inst #1968 = RDMSR
+ { 1969, 0, 0, 0, "RDPMC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(51<<24), NULL, NULL, NULL, 0 }, // Inst #1969 = RDPMC
+ { 1970, 0, 0, 0, "RDTSC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(49<<24), NULL, ImplicitList19, NULL, 0 }, // Inst #1970 = RDTSC
+ { 1971, 0, 0, 0, "REP_MOVSB", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(164<<24), ImplicitList42, ImplicitList42, NULL, 0 }, // Inst #1971 = REP_MOVSB
+ { 1972, 0, 0, 0, "REP_MOVSD", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(165<<24), ImplicitList42, ImplicitList42, NULL, 0 }, // Inst #1972 = REP_MOVSD
+ { 1973, 0, 0, 0, "REP_MOVSQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(165<<24), ImplicitList43, ImplicitList43, NULL, 0 }, // Inst #1973 = REP_MOVSQ
+ { 1974, 0, 0, 0, "REP_MOVSW", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(165<<24), ImplicitList42, ImplicitList42, NULL, 0 }, // Inst #1974 = REP_MOVSW
+ { 1975, 0, 0, 0, "REP_STOSB", 0|(1<<TID::MayStore), 0|1|(2<<8)|(170<<24), ImplicitList44, ImplicitList45, NULL, 0 }, // Inst #1975 = REP_STOSB
+ { 1976, 0, 0, 0, "REP_STOSD", 0|(1<<TID::MayStore), 0|1|(2<<8)|(171<<24), ImplicitList46, ImplicitList45, NULL, 0 }, // Inst #1976 = REP_STOSD
+ { 1977, 0, 0, 0, "REP_STOSQ", 0|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(171<<24), ImplicitList47, ImplicitList48, NULL, 0 }, // Inst #1977 = REP_STOSQ
+ { 1978, 0, 0, 0, "REP_STOSW", 0|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(171<<24), ImplicitList49, ImplicitList45, NULL, 0 }, // Inst #1978 = REP_STOSW
+ { 1979, 0, 0, 0, "RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(7<<16)|(195<<24), NULL, NULL, NULL, 0 }, // Inst #1979 = RET
+ { 1980, 1, 0, 0, "RETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(2<<13)|(7<<16)|(194<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1980 = RETI
+ { 1981, 5, 0, 0, "ROL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1981 = ROL16m1
+ { 1982, 5, 0, 0, "ROL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1982 = ROL16mCL
+ { 1983, 6, 0, 0, "ROL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1983 = ROL16mi
+ { 1984, 2, 1, 0, "ROL16r1", 0, 0|16|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1984 = ROL16r1
+ { 1985, 2, 1, 0, "ROL16rCL", 0, 0|16|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1985 = ROL16rCL
+ { 1986, 3, 1, 0, "ROL16ri", 0, 0|16|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1986 = ROL16ri
+ { 1987, 5, 0, 0, "ROL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1987 = ROL32m1
+ { 1988, 5, 0, 0, "ROL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1988 = ROL32mCL
+ { 1989, 6, 0, 0, "ROL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1989 = ROL32mi
+ { 1990, 2, 1, 0, "ROL32r1", 0, 0|16|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1990 = ROL32r1
+ { 1991, 2, 1, 0, "ROL32rCL", 0, 0|16|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1991 = ROL32rCL
+ { 1992, 3, 1, 0, "ROL32ri", 0, 0|16|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1992 = ROL32ri
+ { 1993, 5, 0, 0, "ROL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1993 = ROL64m1
+ { 1994, 5, 0, 0, "ROL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1994 = ROL64mCL
+ { 1995, 6, 0, 0, "ROL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1995 = ROL64mi
+ { 1996, 2, 1, 0, "ROL64r1", 0, 0|16|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1996 = ROL64r1
+ { 1997, 2, 1, 0, "ROL64rCL", 0, 0|16|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1997 = ROL64rCL
+ { 1998, 3, 1, 0, "ROL64ri", 0, 0|16|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1998 = ROL64ri
+ { 1999, 5, 0, 0, "ROL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1999 = ROL8m1
+ { 2000, 5, 0, 0, "ROL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2000 = ROL8mCL
+ { 2001, 6, 0, 0, "ROL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2001 = ROL8mi
+ { 2002, 2, 1, 0, "ROL8r1", 0, 0|16|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2002 = ROL8r1
+ { 2003, 2, 1, 0, "ROL8rCL", 0, 0|16|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2003 = ROL8rCL
+ { 2004, 3, 1, 0, "ROL8ri", 0, 0|16|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2004 = ROL8ri
+ { 2005, 5, 0, 0, "ROR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2005 = ROR16m1
+ { 2006, 5, 0, 0, "ROR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2006 = ROR16mCL
+ { 2007, 6, 0, 0, "ROR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2007 = ROR16mi
+ { 2008, 2, 1, 0, "ROR16r1", 0, 0|17|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2008 = ROR16r1
+ { 2009, 2, 1, 0, "ROR16rCL", 0, 0|17|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2009 = ROR16rCL
+ { 2010, 3, 1, 0, "ROR16ri", 0, 0|17|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2010 = ROR16ri
+ { 2011, 5, 0, 0, "ROR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2011 = ROR32m1
+ { 2012, 5, 0, 0, "ROR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2012 = ROR32mCL
+ { 2013, 6, 0, 0, "ROR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2013 = ROR32mi
+ { 2014, 2, 1, 0, "ROR32r1", 0, 0|17|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2014 = ROR32r1
+ { 2015, 2, 1, 0, "ROR32rCL", 0, 0|17|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2015 = ROR32rCL
+ { 2016, 3, 1, 0, "ROR32ri", 0, 0|17|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2016 = ROR32ri
+ { 2017, 5, 0, 0, "ROR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2017 = ROR64m1
+ { 2018, 5, 0, 0, "ROR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2018 = ROR64mCL
+ { 2019, 6, 0, 0, "ROR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2019 = ROR64mi
+ { 2020, 2, 1, 0, "ROR64r1", 0, 0|17|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2020 = ROR64r1
+ { 2021, 2, 1, 0, "ROR64rCL", 0, 0|17|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2021 = ROR64rCL
+ { 2022, 3, 1, 0, "ROR64ri", 0, 0|17|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2022 = ROR64ri
+ { 2023, 5, 0, 0, "ROR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2023 = ROR8m1
+ { 2024, 5, 0, 0, "ROR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2024 = ROR8mCL
+ { 2025, 6, 0, 0, "ROR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2025 = ROR8mi
+ { 2026, 2, 1, 0, "ROR8r1", 0, 0|17|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2026 = ROR8r1
+ { 2027, 2, 1, 0, "ROR8rCL", 0, 0|17|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2027 = ROR8rCL
+ { 2028, 3, 1, 0, "ROR8ri", 0, 0|17|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2028 = ROR8ri
+ { 2029, 7, 1, 0, "ROUNDPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #2029 = ROUNDPDm_Int
+ { 2030, 3, 1, 0, "ROUNDPDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #2030 = ROUNDPDr_Int
+ { 2031, 7, 1, 0, "ROUNDPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #2031 = ROUNDPSm_Int
+ { 2032, 3, 1, 0, "ROUNDPSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #2032 = ROUNDPSr_Int
+ { 2033, 8, 1, 0, "ROUNDSDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2033 = ROUNDSDm_Int
+ { 2034, 4, 1, 0, "ROUNDSDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2034 = ROUNDSDr_Int
+ { 2035, 8, 1, 0, "ROUNDSSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2035 = ROUNDSSm_Int
+ { 2036, 4, 1, 0, "ROUNDSSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2036 = ROUNDSSr_Int
+ { 2037, 0, 0, 0, "RSM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(170<<24), NULL, NULL, NULL, 0 }, // Inst #2037 = RSM
+ { 2038, 6, 1, 0, "RSQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2038 = RSQRTPSm
+ { 2039, 6, 1, 0, "RSQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2039 = RSQRTPSm_Int
+ { 2040, 2, 1, 0, "RSQRTPSr", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2040 = RSQRTPSr
+ { 2041, 2, 1, 0, "RSQRTPSr_Int", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2041 = RSQRTPSr_Int
+ { 2042, 6, 1, 0, "RSQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2042 = RSQRTSSm
+ { 2043, 6, 1, 0, "RSQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2043 = RSQRTSSm_Int
+ { 2044, 2, 1, 0, "RSQRTSSr", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #2044 = RSQRTSSr
+ { 2045, 2, 1, 0, "RSQRTSSr_Int", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2045 = RSQRTSSr_Int
+ { 2046, 0, 0, 0, "SAHF", 0, 0|1|(158<<24), ImplicitList27, ImplicitList1, Barriers1, 0 }, // Inst #2046 = SAHF
+ { 2047, 5, 0, 0, "SAR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2047 = SAR16m1
+ { 2048, 5, 0, 0, "SAR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2048 = SAR16mCL
+ { 2049, 6, 0, 0, "SAR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2049 = SAR16mi
+ { 2050, 2, 1, 0, "SAR16r1", 0, 0|23|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2050 = SAR16r1
+ { 2051, 2, 1, 0, "SAR16rCL", 0, 0|23|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2051 = SAR16rCL
+ { 2052, 3, 1, 0, "SAR16ri", 0, 0|23|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2052 = SAR16ri
+ { 2053, 5, 0, 0, "SAR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2053 = SAR32m1
+ { 2054, 5, 0, 0, "SAR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2054 = SAR32mCL
+ { 2055, 6, 0, 0, "SAR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2055 = SAR32mi
+ { 2056, 2, 1, 0, "SAR32r1", 0, 0|23|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2056 = SAR32r1
+ { 2057, 2, 1, 0, "SAR32rCL", 0, 0|23|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2057 = SAR32rCL
+ { 2058, 3, 1, 0, "SAR32ri", 0, 0|23|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2058 = SAR32ri
+ { 2059, 5, 0, 0, "SAR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2059 = SAR64m1
+ { 2060, 5, 0, 0, "SAR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2060 = SAR64mCL
+ { 2061, 6, 0, 0, "SAR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2061 = SAR64mi
+ { 2062, 2, 1, 0, "SAR64r1", 0, 0|23|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2062 = SAR64r1
+ { 2063, 2, 1, 0, "SAR64rCL", 0, 0|23|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2063 = SAR64rCL
+ { 2064, 3, 1, 0, "SAR64ri", 0, 0|23|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2064 = SAR64ri
+ { 2065, 5, 0, 0, "SAR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2065 = SAR8m1
+ { 2066, 5, 0, 0, "SAR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2066 = SAR8mCL
+ { 2067, 6, 0, 0, "SAR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2067 = SAR8mi
+ { 2068, 2, 1, 0, "SAR8r1", 0, 0|23|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2068 = SAR8r1
+ { 2069, 2, 1, 0, "SAR8rCL", 0, 0|23|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2069 = SAR8rCL
+ { 2070, 3, 1, 0, "SAR8ri", 0, 0|23|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2070 = SAR8ri
+ { 2071, 1, 0, 0, "SBB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2071 = SBB16i16
+ { 2072, 6, 0, 0, "SBB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(2<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2072 = SBB16mi
+ { 2073, 6, 0, 0, "SBB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2073 = SBB16mi8
+ { 2074, 6, 0, 0, "SBB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2074 = SBB16mr
+ { 2075, 3, 1, 0, "SBB16ri", 0, 0|19|(1<<6)|(2<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2075 = SBB16ri
+ { 2076, 3, 1, 0, "SBB16ri8", 0, 0|19|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2076 = SBB16ri8
+ { 2077, 7, 1, 0, "SBB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2077 = SBB16rm
+ { 2078, 3, 1, 0, "SBB16rr", 0, 0|3|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2078 = SBB16rr
+ { 2079, 3, 1, 0, "SBB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2079 = SBB16rr_REV
+ { 2080, 1, 0, 0, "SBB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2080 = SBB32i32
+ { 2081, 6, 0, 0, "SBB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2081 = SBB32mi
+ { 2082, 6, 0, 0, "SBB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2082 = SBB32mi8
+ { 2083, 6, 0, 0, "SBB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2083 = SBB32mr
+ { 2084, 3, 1, 0, "SBB32ri", 0, 0|19|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2084 = SBB32ri
+ { 2085, 3, 1, 0, "SBB32ri8", 0, 0|19|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2085 = SBB32ri8
+ { 2086, 7, 1, 0, "SBB32rm", 0|(1<<TID::MayLoad), 0|6|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2086 = SBB32rm
+ { 2087, 3, 1, 0, "SBB32rr", 0, 0|3|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2087 = SBB32rr
+ { 2088, 3, 1, 0, "SBB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2088 = SBB32rr_REV
+ { 2089, 1, 0, 0, "SBB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2089 = SBB64i32
+ { 2090, 6, 0, 0, "SBB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2090 = SBB64mi32
+ { 2091, 6, 0, 0, "SBB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2091 = SBB64mi8
+ { 2092, 6, 0, 0, "SBB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2092 = SBB64mr
+ { 2093, 3, 1, 0, "SBB64ri32", 0, 0|19|(1<<12)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2093 = SBB64ri32
+ { 2094, 3, 1, 0, "SBB64ri8", 0, 0|19|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2094 = SBB64ri8
+ { 2095, 7, 1, 0, "SBB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2095 = SBB64rm
+ { 2096, 3, 1, 0, "SBB64rr", 0, 0|3|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2096 = SBB64rr
+ { 2097, 3, 1, 0, "SBB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2097 = SBB64rr_REV
+ { 2098, 1, 0, 0, "SBB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(28<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2098 = SBB8i8
+ { 2099, 6, 0, 0, "SBB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(3<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2099 = SBB8mi
+ { 2100, 6, 0, 0, "SBB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2100 = SBB8mr
+ { 2101, 3, 1, 0, "SBB8ri", 0, 0|19|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2101 = SBB8ri
+ { 2102, 7, 1, 0, "SBB8rm", 0|(1<<TID::MayLoad), 0|6|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2102 = SBB8rm
+ { 2103, 3, 1, 0, "SBB8rr", 0, 0|3|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2103 = SBB8rr
+ { 2104, 3, 1, 0, "SBB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2104 = SBB8rr_REV
+ { 2105, 0, 0, 0, "SCAS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2105 = SCAS16
+ { 2106, 0, 0, 0, "SCAS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2106 = SCAS32
+ { 2107, 0, 0, 0, "SCAS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2107 = SCAS64
+ { 2108, 0, 0, 0, "SCAS8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(174<<24), NULL, NULL, NULL, 0 }, // Inst #2108 = SCAS8
+ { 2109, 5, 0, 0, "SETAEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2109 = SETAEm
+ { 2110, 1, 1, 0, "SETAEr", 0, 0|16|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2110 = SETAEr
+ { 2111, 5, 0, 0, "SETAm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2111 = SETAm
+ { 2112, 1, 1, 0, "SETAr", 0, 0|16|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2112 = SETAr
+ { 2113, 5, 0, 0, "SETBEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2113 = SETBEm
+ { 2114, 1, 1, 0, "SETBEr", 0, 0|16|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2114 = SETBEr
+ { 2115, 1, 1, 0, "SETB_C16r", 0, 0|32|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo93 }, // Inst #2115 = SETB_C16r
+ { 2116, 1, 1, 0, "SETB_C32r", 0, 0|32|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo57 }, // Inst #2116 = SETB_C32r
+ { 2117, 1, 1, 0, "SETB_C64r", 0, 0|32|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo58 }, // Inst #2117 = SETB_C64r
+ { 2118, 1, 1, 0, "SETB_C8r", 0, 0|32|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo94 }, // Inst #2118 = SETB_C8r
+ { 2119, 5, 0, 0, "SETBm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2119 = SETBm
+ { 2120, 1, 1, 0, "SETBr", 0, 0|16|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2120 = SETBr
+ { 2121, 5, 0, 0, "SETEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2121 = SETEm
+ { 2122, 1, 1, 0, "SETEr", 0, 0|16|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2122 = SETEr
+ { 2123, 5, 0, 0, "SETGEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2123 = SETGEm
+ { 2124, 1, 1, 0, "SETGEr", 0, 0|16|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2124 = SETGEr
+ { 2125, 5, 0, 0, "SETGm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2125 = SETGm
+ { 2126, 1, 1, 0, "SETGr", 0, 0|16|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2126 = SETGr
+ { 2127, 5, 0, 0, "SETLEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2127 = SETLEm
+ { 2128, 1, 1, 0, "SETLEr", 0, 0|16|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2128 = SETLEr
+ { 2129, 5, 0, 0, "SETLm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2129 = SETLm
+ { 2130, 1, 1, 0, "SETLr", 0, 0|16|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2130 = SETLr
+ { 2131, 5, 0, 0, "SETNEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2131 = SETNEm
+ { 2132, 1, 1, 0, "SETNEr", 0, 0|16|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2132 = SETNEr
+ { 2133, 5, 0, 0, "SETNOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2133 = SETNOm
+ { 2134, 1, 1, 0, "SETNOr", 0, 0|16|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2134 = SETNOr
+ { 2135, 5, 0, 0, "SETNPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2135 = SETNPm
+ { 2136, 1, 1, 0, "SETNPr", 0, 0|16|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2136 = SETNPr
+ { 2137, 5, 0, 0, "SETNSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2137 = SETNSm
+ { 2138, 1, 1, 0, "SETNSr", 0, 0|16|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2138 = SETNSr
+ { 2139, 5, 0, 0, "SETOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2139 = SETOm
+ { 2140, 1, 1, 0, "SETOr", 0, 0|16|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2140 = SETOr
+ { 2141, 5, 0, 0, "SETPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2141 = SETPm
+ { 2142, 1, 1, 0, "SETPr", 0, 0|16|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2142 = SETPr
+ { 2143, 5, 0, 0, "SETSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2143 = SETSm
+ { 2144, 1, 1, 0, "SETSr", 0, 0|16|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2144 = SETSr
+ { 2145, 0, 0, 0, "SFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|23|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #2145 = SFENCE
+ { 2146, 5, 1, 0, "SGDTm", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2146 = SGDTm
+ { 2147, 5, 0, 0, "SHL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2147 = SHL16m1
+ { 2148, 5, 0, 0, "SHL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2148 = SHL16mCL
+ { 2149, 6, 0, 0, "SHL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2149 = SHL16mi
+ { 2150, 2, 1, 0, "SHL16r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2150 = SHL16r1
+ { 2151, 2, 1, 0, "SHL16rCL", 0, 0|20|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2151 = SHL16rCL
+ { 2152, 3, 1, 0, "SHL16ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2152 = SHL16ri
+ { 2153, 5, 0, 0, "SHL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2153 = SHL32m1
+ { 2154, 5, 0, 0, "SHL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2154 = SHL32mCL
+ { 2155, 6, 0, 0, "SHL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2155 = SHL32mi
+ { 2156, 2, 1, 0, "SHL32r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2156 = SHL32r1
+ { 2157, 2, 1, 0, "SHL32rCL", 0, 0|20|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2157 = SHL32rCL
+ { 2158, 3, 1, 0, "SHL32ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2158 = SHL32ri
+ { 2159, 5, 0, 0, "SHL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2159 = SHL64m1
+ { 2160, 5, 0, 0, "SHL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2160 = SHL64mCL
+ { 2161, 6, 0, 0, "SHL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2161 = SHL64mi
+ { 2162, 2, 1, 0, "SHL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2162 = SHL64r1
+ { 2163, 2, 1, 0, "SHL64rCL", 0, 0|20|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2163 = SHL64rCL
+ { 2164, 3, 1, 0, "SHL64ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2164 = SHL64ri
+ { 2165, 5, 0, 0, "SHL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2165 = SHL8m1
+ { 2166, 5, 0, 0, "SHL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2166 = SHL8mCL
+ { 2167, 6, 0, 0, "SHL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2167 = SHL8mi
+ { 2168, 2, 1, 0, "SHL8r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2168 = SHL8r1
+ { 2169, 2, 1, 0, "SHL8rCL", 0, 0|20|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2169 = SHL8rCL
+ { 2170, 3, 1, 0, "SHL8ri", 0, 0|20|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2170 = SHL8ri
+ { 2171, 6, 0, 0, "SHLD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(165<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2171 = SHLD16mrCL
+ { 2172, 7, 0, 0, "SHLD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo196 }, // Inst #2172 = SHLD16mri8
+ { 2173, 3, 1, 0, "SHLD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(165<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2173 = SHLD16rrCL
+ { 2174, 4, 1, 0, "SHLD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo197 }, // Inst #2174 = SHLD16rri8
+ { 2175, 6, 0, 0, "SHLD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(165<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2175 = SHLD32mrCL
+ { 2176, 7, 0, 0, "SHLD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo198 }, // Inst #2176 = SHLD32mri8
+ { 2177, 3, 1, 0, "SHLD32rrCL", 0, 0|3|(1<<8)|(165<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2177 = SHLD32rrCL
+ { 2178, 4, 1, 0, "SHLD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo199 }, // Inst #2178 = SHLD32rri8
+ { 2179, 6, 0, 0, "SHLD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(165<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2179 = SHLD64mrCL
+ { 2180, 7, 0, 0, "SHLD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo200 }, // Inst #2180 = SHLD64mri8
+ { 2181, 3, 1, 0, "SHLD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(165<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2181 = SHLD64rrCL
+ { 2182, 4, 1, 0, "SHLD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo201 }, // Inst #2182 = SHLD64rri8
+ { 2183, 5, 0, 0, "SHR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2183 = SHR16m1
+ { 2184, 5, 0, 0, "SHR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2184 = SHR16mCL
+ { 2185, 6, 0, 0, "SHR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2185 = SHR16mi
+ { 2186, 2, 1, 0, "SHR16r1", 0, 0|21|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2186 = SHR16r1
+ { 2187, 2, 1, 0, "SHR16rCL", 0, 0|21|(1<<6)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2187 = SHR16rCL
+ { 2188, 3, 1, 0, "SHR16ri", 0, 0|21|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2188 = SHR16ri
+ { 2189, 5, 0, 0, "SHR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2189 = SHR32m1
+ { 2190, 5, 0, 0, "SHR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2190 = SHR32mCL
+ { 2191, 6, 0, 0, "SHR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2191 = SHR32mi
+ { 2192, 2, 1, 0, "SHR32r1", 0, 0|21|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2192 = SHR32r1
+ { 2193, 2, 1, 0, "SHR32rCL", 0, 0|21|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2193 = SHR32rCL
+ { 2194, 3, 1, 0, "SHR32ri", 0, 0|21|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2194 = SHR32ri
+ { 2195, 5, 0, 0, "SHR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2195 = SHR64m1
+ { 2196, 5, 0, 0, "SHR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2196 = SHR64mCL
+ { 2197, 6, 0, 0, "SHR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2197 = SHR64mi
+ { 2198, 2, 1, 0, "SHR64r1", 0, 0|21|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2198 = SHR64r1
+ { 2199, 2, 1, 0, "SHR64rCL", 0, 0|21|(1<<12)|(211<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2199 = SHR64rCL
+ { 2200, 3, 1, 0, "SHR64ri", 0, 0|21|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2200 = SHR64ri
+ { 2201, 5, 0, 0, "SHR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2201 = SHR8m1
+ { 2202, 5, 0, 0, "SHR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2202 = SHR8mCL
+ { 2203, 6, 0, 0, "SHR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2203 = SHR8mi
+ { 2204, 2, 1, 0, "SHR8r1", 0, 0|21|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2204 = SHR8r1
+ { 2205, 2, 1, 0, "SHR8rCL", 0, 0|21|(210<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2205 = SHR8rCL
+ { 2206, 3, 1, 0, "SHR8ri", 0, 0|21|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2206 = SHR8ri
+ { 2207, 6, 0, 0, "SHRD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(173<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2207 = SHRD16mrCL
+ { 2208, 7, 0, 0, "SHRD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo196 }, // Inst #2208 = SHRD16mri8
+ { 2209, 3, 1, 0, "SHRD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(173<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2209 = SHRD16rrCL
+ { 2210, 4, 1, 0, "SHRD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo197 }, // Inst #2210 = SHRD16rri8
+ { 2211, 6, 0, 0, "SHRD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(173<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2211 = SHRD32mrCL
+ { 2212, 7, 0, 0, "SHRD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo198 }, // Inst #2212 = SHRD32mri8
+ { 2213, 3, 1, 0, "SHRD32rrCL", 0, 0|3|(1<<8)|(173<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2213 = SHRD32rrCL
+ { 2214, 4, 1, 0, "SHRD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo199 }, // Inst #2214 = SHRD32rri8
+ { 2215, 6, 0, 0, "SHRD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(173<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2215 = SHRD64mrCL
+ { 2216, 7, 0, 0, "SHRD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo200 }, // Inst #2216 = SHRD64mri8
+ { 2217, 3, 1, 0, "SHRD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(173<<24), ImplicitList41, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2217 = SHRD64rrCL
+ { 2218, 4, 1, 0, "SHRD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo201 }, // Inst #2218 = SHRD64rri8
+ { 2219, 8, 1, 0, "SHUFPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2219 = SHUFPDrmi
+ { 2220, 4, 1, 0, "SHUFPDrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2220 = SHUFPDrri
+ { 2221, 8, 1, 0, "SHUFPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2221 = SHUFPSrmi
+ { 2222, 4, 1, 0, "SHUFPSrri", 0|(1<<TID::ConvertibleTo3Addr), 0|5|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2222 = SHUFPSrri
+ { 2223, 5, 1, 0, "SIDTm", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2223 = SIDTm
+ { 2224, 0, 0, 0, "SIN_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(254<<24), NULL, NULL, NULL, 0 }, // Inst #2224 = SIN_F
+ { 2225, 2, 1, 0, "SIN_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2225 = SIN_Fp32
+ { 2226, 2, 1, 0, "SIN_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2226 = SIN_Fp64
+ { 2227, 2, 1, 0, "SIN_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2227 = SIN_Fp80
+ { 2228, 5, 1, 0, "SLDT16m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2228 = SLDT16m
+ { 2229, 1, 1, 0, "SLDT16r", 0|(1<<TID::UnmodeledSideEffects), 0|16|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2229 = SLDT16r
+ { 2230, 5, 1, 0, "SLDT64m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(1<<12), NULL, NULL, NULL, OperandInfo30 }, // Inst #2230 = SLDT64m
+ { 2231, 1, 1, 0, "SLDT64r", 0|(1<<TID::UnmodeledSideEffects), 0|16|(1<<8)|(1<<12), NULL, NULL, NULL, OperandInfo58 }, // Inst #2231 = SLDT64r
+ { 2232, 5, 1, 0, "SMSW16m", 0|(1<<TID::UnmodeledSideEffects), 0|28|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2232 = SMSW16m
+ { 2233, 1, 1, 0, "SMSW16r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #2233 = SMSW16r
+ { 2234, 1, 1, 0, "SMSW32r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2234 = SMSW32r
+ { 2235, 1, 1, 0, "SMSW64r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8)|(1<<12)|(1<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2235 = SMSW64r
+ { 2236, 6, 1, 0, "SQRTPDm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2236 = SQRTPDm
+ { 2237, 6, 1, 0, "SQRTPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2237 = SQRTPDm_Int
+ { 2238, 2, 1, 0, "SQRTPDr", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2238 = SQRTPDr
+ { 2239, 2, 1, 0, "SQRTPDr_Int", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2239 = SQRTPDr_Int
+ { 2240, 6, 1, 0, "SQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2240 = SQRTPSm
+ { 2241, 6, 1, 0, "SQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2241 = SQRTPSm_Int
+ { 2242, 2, 1, 0, "SQRTPSr", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2242 = SQRTPSr
+ { 2243, 2, 1, 0, "SQRTPSr_Int", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2243 = SQRTPSr_Int
+ { 2244, 6, 1, 0, "SQRTSDm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #2244 = SQRTSDm
+ { 2245, 6, 1, 0, "SQRTSDm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2245 = SQRTSDm_Int
+ { 2246, 2, 1, 0, "SQRTSDr", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #2246 = SQRTSDr
+ { 2247, 2, 1, 0, "SQRTSDr_Int", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2247 = SQRTSDr_Int
+ { 2248, 6, 1, 0, "SQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2248 = SQRTSSm
+ { 2249, 6, 1, 0, "SQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2249 = SQRTSSm_Int
+ { 2250, 2, 1, 0, "SQRTSSr", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #2250 = SQRTSSr
+ { 2251, 2, 1, 0, "SQRTSSr_Int", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2251 = SQRTSSr_Int
+ { 2252, 0, 0, 0, "SQRT_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(250<<24), NULL, NULL, NULL, 0 }, // Inst #2252 = SQRT_F
+ { 2253, 2, 1, 0, "SQRT_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2253 = SQRT_Fp32
+ { 2254, 2, 1, 0, "SQRT_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2254 = SQRT_Fp64
+ { 2255, 2, 1, 0, "SQRT_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2255 = SQRT_Fp80
+ { 2256, 0, 0, 0, "STC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(249<<24), NULL, NULL, NULL, 0 }, // Inst #2256 = STC
+ { 2257, 0, 0, 0, "STD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(253<<24), NULL, NULL, NULL, 0 }, // Inst #2257 = STD
+ { 2258, 0, 0, 0, "STI", 0|(1<<TID::UnmodeledSideEffects), 0|1|(251<<24), NULL, NULL, NULL, 0 }, // Inst #2258 = STI
+ { 2259, 5, 0, 0, "STMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2259 = STMXCSR
+ { 2260, 5, 1, 0, "STRm", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2260 = STRm
+ { 2261, 1, 1, 0, "STRr", 0|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2261 = STRr
+ { 2262, 5, 0, 0, "ST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2262 = ST_F32m
+ { 2263, 5, 0, 0, "ST_F64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2263 = ST_F64m
+ { 2264, 5, 0, 0, "ST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2264 = ST_FP32m
+ { 2265, 5, 0, 0, "ST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2265 = ST_FP64m
+ { 2266, 5, 0, 0, "ST_FP80m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2266 = ST_FP80m
+ { 2267, 1, 0, 0, "ST_FPrr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2267 = ST_FPrr
+ { 2268, 6, 0, 0, "ST_Fp32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2268 = ST_Fp32m
+ { 2269, 6, 0, 0, "ST_Fp64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2269 = ST_Fp64m
+ { 2270, 6, 0, 0, "ST_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2270 = ST_Fp64m32
+ { 2271, 6, 0, 0, "ST_Fp80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2271 = ST_Fp80m32
+ { 2272, 6, 0, 0, "ST_Fp80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2272 = ST_Fp80m64
+ { 2273, 6, 0, 0, "ST_FpP32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2273 = ST_FpP32m
+ { 2274, 6, 0, 0, "ST_FpP64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2274 = ST_FpP64m
+ { 2275, 6, 0, 0, "ST_FpP64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2275 = ST_FpP64m32
+ { 2276, 6, 0, 0, "ST_FpP80m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2276 = ST_FpP80m
+ { 2277, 6, 0, 0, "ST_FpP80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2277 = ST_FpP80m32
+ { 2278, 6, 0, 0, "ST_FpP80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2278 = ST_FpP80m64
+ { 2279, 1, 0, 0, "ST_Frr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2279 = ST_Frr
+ { 2280, 1, 0, 0, "SUB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2280 = SUB16i16
+ { 2281, 6, 0, 0, "SUB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2281 = SUB16mi
+ { 2282, 6, 0, 0, "SUB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2282 = SUB16mi8
+ { 2283, 6, 0, 0, "SUB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2283 = SUB16mr
+ { 2284, 3, 1, 0, "SUB16ri", 0, 0|21|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2284 = SUB16ri
+ { 2285, 3, 1, 0, "SUB16ri8", 0, 0|21|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2285 = SUB16ri8
+ { 2286, 7, 1, 0, "SUB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2286 = SUB16rm
+ { 2287, 3, 1, 0, "SUB16rr", 0, 0|3|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2287 = SUB16rr
+ { 2288, 3, 1, 0, "SUB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2288 = SUB16rr_REV
+ { 2289, 1, 0, 0, "SUB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2289 = SUB32i32
+ { 2290, 6, 0, 0, "SUB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2290 = SUB32mi
+ { 2291, 6, 0, 0, "SUB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2291 = SUB32mi8
+ { 2292, 6, 0, 0, "SUB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2292 = SUB32mr
+ { 2293, 3, 1, 0, "SUB32ri", 0, 0|21|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2293 = SUB32ri
+ { 2294, 3, 1, 0, "SUB32ri8", 0, 0|21|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2294 = SUB32ri8
+ { 2295, 7, 1, 0, "SUB32rm", 0|(1<<TID::MayLoad), 0|6|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2295 = SUB32rm
+ { 2296, 3, 1, 0, "SUB32rr", 0, 0|3|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2296 = SUB32rr
+ { 2297, 3, 1, 0, "SUB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2297 = SUB32rr_REV
+ { 2298, 1, 0, 0, "SUB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2298 = SUB64i32
+ { 2299, 6, 0, 0, "SUB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2299 = SUB64mi32
+ { 2300, 6, 0, 0, "SUB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2300 = SUB64mi8
+ { 2301, 6, 0, 0, "SUB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2301 = SUB64mr
+ { 2302, 3, 1, 0, "SUB64ri32", 0, 0|21|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2302 = SUB64ri32
+ { 2303, 3, 1, 0, "SUB64ri8", 0, 0|21|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2303 = SUB64ri8
+ { 2304, 7, 1, 0, "SUB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2304 = SUB64rm
+ { 2305, 3, 1, 0, "SUB64rr", 0, 0|3|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2305 = SUB64rr
+ { 2306, 3, 1, 0, "SUB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2306 = SUB64rr_REV
+ { 2307, 1, 0, 0, "SUB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(44<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2307 = SUB8i8
+ { 2308, 6, 0, 0, "SUB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2308 = SUB8mi
+ { 2309, 6, 0, 0, "SUB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2309 = SUB8mr
+ { 2310, 3, 1, 0, "SUB8ri", 0, 0|21|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2310 = SUB8ri
+ { 2311, 7, 1, 0, "SUB8rm", 0|(1<<TID::MayLoad), 0|6|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2311 = SUB8rm
+ { 2312, 3, 1, 0, "SUB8rr", 0, 0|3|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2312 = SUB8rr
+ { 2313, 3, 1, 0, "SUB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2313 = SUB8rr_REV
+ { 2314, 7, 1, 0, "SUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2314 = SUBPDrm
+ { 2315, 3, 1, 0, "SUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2315 = SUBPDrr
+ { 2316, 7, 1, 0, "SUBPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2316 = SUBPSrm
+ { 2317, 3, 1, 0, "SUBPSrr", 0, 0|5|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2317 = SUBPSrr
+ { 2318, 5, 0, 0, "SUBR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2318 = SUBR_F32m
+ { 2319, 5, 0, 0, "SUBR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2319 = SUBR_F64m
+ { 2320, 5, 0, 0, "SUBR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2320 = SUBR_FI16m
+ { 2321, 5, 0, 0, "SUBR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2321 = SUBR_FI32m
+ { 2322, 1, 0, 0, "SUBR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2322 = SUBR_FPrST0
+ { 2323, 1, 0, 0, "SUBR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2323 = SUBR_FST0r
+ { 2324, 7, 1, 0, "SUBR_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2324 = SUBR_Fp32m
+ { 2325, 7, 1, 0, "SUBR_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2325 = SUBR_Fp64m
+ { 2326, 7, 1, 0, "SUBR_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2326 = SUBR_Fp64m32
+ { 2327, 7, 1, 0, "SUBR_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2327 = SUBR_Fp80m32
+ { 2328, 7, 1, 0, "SUBR_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2328 = SUBR_Fp80m64
+ { 2329, 7, 1, 0, "SUBR_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2329 = SUBR_FpI16m32
+ { 2330, 7, 1, 0, "SUBR_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2330 = SUBR_FpI16m64
+ { 2331, 7, 1, 0, "SUBR_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2331 = SUBR_FpI16m80
+ { 2332, 7, 1, 0, "SUBR_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2332 = SUBR_FpI32m32
+ { 2333, 7, 1, 0, "SUBR_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2333 = SUBR_FpI32m64
+ { 2334, 7, 1, 0, "SUBR_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2334 = SUBR_FpI32m80
+ { 2335, 1, 0, 0, "SUBR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2335 = SUBR_FrST0
+ { 2336, 7, 1, 0, "SUBSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #2336 = SUBSDrm
+ { 2337, 7, 1, 0, "SUBSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2337 = SUBSDrm_Int
+ { 2338, 3, 1, 0, "SUBSDrr", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #2338 = SUBSDrr
+ { 2339, 3, 1, 0, "SUBSDrr_Int", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2339 = SUBSDrr_Int
+ { 2340, 7, 1, 0, "SUBSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #2340 = SUBSSrm
+ { 2341, 7, 1, 0, "SUBSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2341 = SUBSSrm_Int
+ { 2342, 3, 1, 0, "SUBSSrr", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2342 = SUBSSrr
+ { 2343, 3, 1, 0, "SUBSSrr_Int", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2343 = SUBSSrr_Int
+ { 2344, 5, 0, 0, "SUB_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2344 = SUB_F32m
+ { 2345, 5, 0, 0, "SUB_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2345 = SUB_F64m
+ { 2346, 5, 0, 0, "SUB_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2346 = SUB_FI16m
+ { 2347, 5, 0, 0, "SUB_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2347 = SUB_FI32m
+ { 2348, 1, 0, 0, "SUB_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2348 = SUB_FPrST0
+ { 2349, 1, 0, 0, "SUB_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2349 = SUB_FST0r
+ { 2350, 3, 1, 0, "SUB_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2350 = SUB_Fp32
+ { 2351, 7, 1, 0, "SUB_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2351 = SUB_Fp32m
+ { 2352, 3, 1, 0, "SUB_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2352 = SUB_Fp64
+ { 2353, 7, 1, 0, "SUB_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2353 = SUB_Fp64m
+ { 2354, 7, 1, 0, "SUB_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2354 = SUB_Fp64m32
+ { 2355, 3, 1, 0, "SUB_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2355 = SUB_Fp80
+ { 2356, 7, 1, 0, "SUB_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2356 = SUB_Fp80m32
+ { 2357, 7, 1, 0, "SUB_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2357 = SUB_Fp80m64
+ { 2358, 7, 1, 0, "SUB_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2358 = SUB_FpI16m32
+ { 2359, 7, 1, 0, "SUB_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2359 = SUB_FpI16m64
+ { 2360, 7, 1, 0, "SUB_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2360 = SUB_FpI16m80
+ { 2361, 7, 1, 0, "SUB_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2361 = SUB_FpI32m32
+ { 2362, 7, 1, 0, "SUB_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2362 = SUB_FpI32m64
+ { 2363, 7, 1, 0, "SUB_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2363 = SUB_FpI32m80
+ { 2364, 1, 0, 0, "SUB_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2364 = SUB_FrST0
+ { 2365, 0, 0, 0, "SWPGS", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2365 = SWPGS
+ { 2366, 0, 0, 0, "SYSCALL", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(5<<24), NULL, NULL, NULL, 0 }, // Inst #2366 = SYSCALL
+ { 2367, 0, 0, 0, "SYSENTER", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(52<<24), NULL, NULL, NULL, 0 }, // Inst #2367 = SYSENTER
+ { 2368, 0, 0, 0, "SYSEXIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2368 = SYSEXIT
+ { 2369, 0, 0, 0, "SYSEXIT64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<12)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2369 = SYSEXIT64
+ { 2370, 0, 0, 0, "SYSRET", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(7<<24), NULL, NULL, NULL, 0 }, // Inst #2370 = SYSRET
+ { 2371, 1, 0, 0, "TAILJMPd", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|1|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #2371 = TAILJMPd
+ { 2372, 5, 0, 0, "TAILJMPm", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2372 = TAILJMPm
+ { 2373, 1, 0, 0, "TAILJMPr", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2373 = TAILJMPr
+ { 2374, 1, 0, 0, "TAILJMPr64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2374 = TAILJMPr64
+ { 2375, 2, 0, 0, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #2375 = TCRETURNdi
+ { 2376, 2, 0, 0, "TCRETURNdi64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #2376 = TCRETURNdi64
+ { 2377, 2, 0, 0, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo55 }, // Inst #2377 = TCRETURNri
+ { 2378, 2, 0, 0, "TCRETURNri64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo56 }, // Inst #2378 = TCRETURNri64
+ { 2379, 1, 0, 0, "TEST16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2379 = TEST16i16
+ { 2380, 6, 0, 0, "TEST16mi", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(2<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2380 = TEST16mi
+ { 2381, 2, 0, 0, "TEST16ri", 0, 0|16|(1<<6)|(2<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #2381 = TEST16ri
+ { 2382, 6, 0, 0, "TEST16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #2382 = TEST16rm
+ { 2383, 2, 0, 0, "TEST16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #2383 = TEST16rr
+ { 2384, 1, 0, 0, "TEST32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2384 = TEST32i32
+ { 2385, 6, 0, 0, "TEST32mi", 0|(1<<TID::MayLoad), 0|24|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2385 = TEST32mi
+ { 2386, 2, 0, 0, "TEST32ri", 0, 0|16|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #2386 = TEST32ri
+ { 2387, 6, 0, 0, "TEST32rm", 0|(1<<TID::MayLoad), 0|6|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #2387 = TEST32rm
+ { 2388, 2, 0, 0, "TEST32rr", 0|(1<<TID::Commutable), 0|3|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #2388 = TEST32rr
+ { 2389, 1, 0, 0, "TEST64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2389 = TEST64i32
+ { 2390, 6, 0, 0, "TEST64mi32", 0|(1<<TID::MayLoad), 0|24|(1<<12)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2390 = TEST64mi32
+ { 2391, 2, 0, 0, "TEST64ri32", 0, 0|16|(1<<12)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #2391 = TEST64ri32
+ { 2392, 6, 0, 0, "TEST64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #2392 = TEST64rm
+ { 2393, 2, 0, 0, "TEST64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #2393 = TEST64rr
+ { 2394, 1, 0, 0, "TEST8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(168<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2394 = TEST8i8
+ { 2395, 6, 0, 0, "TEST8mi", 0|(1<<TID::MayLoad), 0|24|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2395 = TEST8mi
+ { 2396, 2, 0, 0, "TEST8ri", 0, 0|16|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo68 }, // Inst #2396 = TEST8ri
+ { 2397, 6, 0, 0, "TEST8rm", 0|(1<<TID::MayLoad), 0|6|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo69 }, // Inst #2397 = TEST8rm
+ { 2398, 2, 0, 0, "TEST8rr", 0|(1<<TID::Commutable), 0|3|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #2398 = TEST8rr
+ { 2399, 4, 0, 0, "TLS_addr32", 0, 0, ImplicitList2, ImplicitList9, Barriers3, OperandInfo203 }, // Inst #2399 = TLS_addr32
+ { 2400, 4, 0, 0, "TLS_addr64", 0, 0, ImplicitList4, ImplicitList10, Barriers4, OperandInfo204 }, // Inst #2400 = TLS_addr64
+ { 2401, 0, 0, 0, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(11<<24), NULL, NULL, NULL, 0 }, // Inst #2401 = TRAP
+ { 2402, 0, 0, 0, "TST_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(228<<24), NULL, NULL, NULL, 0 }, // Inst #2402 = TST_F
+ { 2403, 1, 0, 0, "TST_Fp32", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #2403 = TST_Fp32
+ { 2404, 1, 0, 0, "TST_Fp64", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #2404 = TST_Fp64
+ { 2405, 1, 0, 0, "TST_Fp80", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #2405 = TST_Fp80
+ { 2406, 6, 0, 0, "UCOMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo82 }, // Inst #2406 = UCOMISDrm
+ { 2407, 2, 0, 0, "UCOMISDrr", 0, 0|5|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo105 }, // Inst #2407 = UCOMISDrr
+ { 2408, 6, 0, 0, "UCOMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo80 }, // Inst #2408 = UCOMISSrm
+ { 2409, 2, 0, 0, "UCOMISSrr", 0, 0|5|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo106 }, // Inst #2409 = UCOMISSrr
+ { 2410, 1, 0, 0, "UCOM_FIPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(10<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2410 = UCOM_FIPr
+ { 2411, 1, 0, 0, "UCOM_FIr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2411 = UCOM_FIr
+ { 2412, 0, 0, 0, "UCOM_FPPr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(5<<8)|(233<<24), ImplicitList24, ImplicitList1, Barriers1, 0 }, // Inst #2412 = UCOM_FPPr
+ { 2413, 1, 0, 0, "UCOM_FPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2413 = UCOM_FPr
+ { 2414, 2, 0, 0, "UCOM_FpIr32", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2414 = UCOM_FpIr32
+ { 2415, 2, 0, 0, "UCOM_FpIr64", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2415 = UCOM_FpIr64
+ { 2416, 2, 0, 0, "UCOM_FpIr80", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2416 = UCOM_FpIr80
+ { 2417, 2, 0, 0, "UCOM_Fpr32", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2417 = UCOM_Fpr32
+ { 2418, 2, 0, 0, "UCOM_Fpr64", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2418 = UCOM_Fpr64
+ { 2419, 2, 0, 0, "UCOM_Fpr80", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2419 = UCOM_Fpr80
+ { 2420, 1, 0, 0, "UCOM_Fr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(224<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2420 = UCOM_Fr
+ { 2421, 7, 1, 0, "UNPCKHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2421 = UNPCKHPDrm
+ { 2422, 3, 1, 0, "UNPCKHPDrr", 0, 0|5|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2422 = UNPCKHPDrr
+ { 2423, 7, 1, 0, "UNPCKHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2423 = UNPCKHPSrm
+ { 2424, 3, 1, 0, "UNPCKHPSrr", 0, 0|5|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2424 = UNPCKHPSrr
+ { 2425, 7, 1, 0, "UNPCKLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2425 = UNPCKLPDrm
+ { 2426, 3, 1, 0, "UNPCKLPDrr", 0, 0|5|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2426 = UNPCKLPDrr
+ { 2427, 7, 1, 0, "UNPCKLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2427 = UNPCKLPSrm
+ { 2428, 3, 1, 0, "UNPCKLPSrr", 0, 0|5|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2428 = UNPCKLPSrr
+ { 2429, 3, 0, 0, "VASTART_SAVE_XMM_REGS", 0|(1<<TID::UsesCustomInserter)|(1<<TID::Variadic), 0, NULL, NULL, NULL, OperandInfo205 }, // Inst #2429 = VASTART_SAVE_XMM_REGS
+ { 2430, 5, 0, 0, "VERRm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2430 = VERRm
+ { 2431, 1, 0, 0, "VERRr", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2431 = VERRr
+ { 2432, 5, 0, 0, "VERWm", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2432 = VERWm
+ { 2433, 1, 0, 0, "VERWr", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2433 = VERWr
+ { 2434, 0, 0, 0, "VMCALL", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2434 = VMCALL
+ { 2435, 5, 0, 0, "VMCLEARm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2435 = VMCLEARm
+ { 2436, 0, 0, 0, "VMLAUNCH", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2436 = VMLAUNCH
+ { 2437, 5, 0, 0, "VMPTRLDm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2437 = VMPTRLDm
+ { 2438, 5, 1, 0, "VMPTRSTm", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2438 = VMPTRSTm
+ { 2439, 6, 1, 0, "VMREAD32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #2439 = VMREAD32rm
+ { 2440, 2, 1, 0, "VMREAD32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2440 = VMREAD32rr
+ { 2441, 6, 1, 0, "VMREAD64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #2441 = VMREAD64rm
+ { 2442, 2, 1, 0, "VMREAD64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2442 = VMREAD64rr
+ { 2443, 0, 0, 0, "VMRESUME", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2443 = VMRESUME
+ { 2444, 6, 1, 0, "VMWRITE32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #2444 = VMWRITE32rm
+ { 2445, 2, 1, 0, "VMWRITE32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2445 = VMWRITE32rr
+ { 2446, 6, 1, 0, "VMWRITE64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #2446 = VMWRITE64rm
+ { 2447, 2, 1, 0, "VMWRITE64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2447 = VMWRITE64rr
+ { 2448, 0, 0, 0, "VMXOFF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2448 = VMXOFF
+ { 2449, 5, 0, 0, "VMXON", 0|(1<<TID::UnmodeledSideEffects), 0|30|(11<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2449 = VMXON
+ { 2450, 1, 1, 0, "V_SET0", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo206 }, // Inst #2450 = V_SET0
+ { 2451, 1, 1, 0, "V_SETALLONES", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo206 }, // Inst #2451 = V_SETALLONES
+ { 2452, 0, 0, 0, "WAIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(155<<24), NULL, NULL, NULL, 0 }, // Inst #2452 = WAIT
+ { 2453, 0, 0, 0, "WBINVD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(9<<24), NULL, NULL, NULL, 0 }, // Inst #2453 = WBINVD
+ { 2454, 5, 0, 0, "WINCALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList4, ImplicitList50, Barriers8, OperandInfo30 }, // Inst #2454 = WINCALL64m
+ { 2455, 1, 0, 0, "WINCALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(232<<24), ImplicitList4, ImplicitList50, Barriers8, OperandInfo5 }, // Inst #2455 = WINCALL64pcrel32
+ { 2456, 1, 0, 0, "WINCALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList4, ImplicitList50, Barriers8, OperandInfo58 }, // Inst #2456 = WINCALL64r
+ { 2457, 0, 0, 0, "WRMSR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(48<<24), NULL, NULL, NULL, 0 }, // Inst #2457 = WRMSR
+ { 2458, 6, 0, 0, "XADD16rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #2458 = XADD16rm
+ { 2459, 2, 1, 0, "XADD16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #2459 = XADD16rr
+ { 2460, 6, 0, 0, "XADD32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #2460 = XADD32rm
+ { 2461, 2, 1, 0, "XADD32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2461 = XADD32rr
+ { 2462, 6, 0, 0, "XADD64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(193<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #2462 = XADD64rm
+ { 2463, 2, 1, 0, "XADD64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(193<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2463 = XADD64rr
+ { 2464, 6, 0, 0, "XADD8rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(192<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #2464 = XADD8rm
+ { 2465, 2, 1, 0, "XADD8rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(192<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #2465 = XADD8rr
+ { 2466, 1, 0, 0, "XCHG16ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(1<<6)|(144<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #2466 = XCHG16ar
+ { 2467, 7, 1, 0, "XCHG16rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo9 }, // Inst #2467 = XCHG16rm
+ { 2468, 3, 1, 0, "XCHG16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo10 }, // Inst #2468 = XCHG16rr
+ { 2469, 1, 0, 0, "XCHG32ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(144<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2469 = XCHG32ar
+ { 2470, 7, 1, 0, "XCHG32rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(135<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #2470 = XCHG32rm
+ { 2471, 3, 1, 0, "XCHG32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(135<<24), NULL, NULL, NULL, OperandInfo14 }, // Inst #2471 = XCHG32rr
+ { 2472, 1, 0, 0, "XCHG64ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(1<<12)|(144<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2472 = XCHG64ar
+ { 2473, 7, 1, 0, "XCHG64rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo17 }, // Inst #2473 = XCHG64rm
+ { 2474, 3, 1, 0, "XCHG64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo18 }, // Inst #2474 = XCHG64rr
+ { 2475, 7, 1, 0, "XCHG8rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(134<<24), NULL, NULL, NULL, OperandInfo22 }, // Inst #2475 = XCHG8rm
+ { 2476, 3, 1, 0, "XCHG8rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(134<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2476 = XCHG8rr
+ { 2477, 1, 0, 0, "XCH_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(4<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2477 = XCH_F
+ { 2478, 0, 0, 0, "XLAT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(215<<24), NULL, NULL, NULL, 0 }, // Inst #2478 = XLAT
+ { 2479, 1, 0, 0, "XOR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(2<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2479 = XOR16i16
+ { 2480, 6, 0, 0, "XOR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2480 = XOR16mi
+ { 2481, 6, 0, 0, "XOR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2481 = XOR16mi8
+ { 2482, 6, 0, 0, "XOR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2482 = XOR16mr
+ { 2483, 3, 1, 0, "XOR16ri", 0, 0|22|(1<<6)|(2<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2483 = XOR16ri
+ { 2484, 3, 1, 0, "XOR16ri8", 0, 0|22|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2484 = XOR16ri8
+ { 2485, 7, 1, 0, "XOR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2485 = XOR16rm
+ { 2486, 3, 1, 0, "XOR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2486 = XOR16rr
+ { 2487, 3, 1, 0, "XOR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2487 = XOR16rr_REV
+ { 2488, 1, 0, 0, "XOR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(3<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2488 = XOR32i32
+ { 2489, 6, 0, 0, "XOR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2489 = XOR32mi
+ { 2490, 6, 0, 0, "XOR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2490 = XOR32mi8
+ { 2491, 6, 0, 0, "XOR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2491 = XOR32mr
+ { 2492, 3, 1, 0, "XOR32ri", 0, 0|22|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2492 = XOR32ri
+ { 2493, 3, 1, 0, "XOR32ri8", 0, 0|22|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2493 = XOR32ri8
+ { 2494, 7, 1, 0, "XOR32rm", 0|(1<<TID::MayLoad), 0|6|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2494 = XOR32rm
+ { 2495, 3, 1, 0, "XOR32rr", 0|(1<<TID::Commutable), 0|3|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2495 = XOR32rr
+ { 2496, 3, 1, 0, "XOR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2496 = XOR32rr_REV
+ { 2497, 1, 0, 0, "XOR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(3<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2497 = XOR64i32
+ { 2498, 6, 0, 0, "XOR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2498 = XOR64mi32
+ { 2499, 6, 0, 0, "XOR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2499 = XOR64mi8
+ { 2500, 6, 0, 0, "XOR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2500 = XOR64mr
+ { 2501, 3, 1, 0, "XOR64ri32", 0, 0|22|(1<<12)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2501 = XOR64ri32
+ { 2502, 3, 1, 0, "XOR64ri8", 0, 0|22|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2502 = XOR64ri8
+ { 2503, 7, 1, 0, "XOR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2503 = XOR64rm
+ { 2504, 3, 1, 0, "XOR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2504 = XOR64rr
+ { 2505, 3, 1, 0, "XOR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2505 = XOR64rr_REV
+ { 2506, 1, 0, 0, "XOR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(52<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2506 = XOR8i8
+ { 2507, 6, 0, 0, "XOR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2507 = XOR8mi
+ { 2508, 6, 0, 0, "XOR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2508 = XOR8mr
+ { 2509, 3, 1, 0, "XOR8ri", 0, 0|22|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2509 = XOR8ri
+ { 2510, 7, 1, 0, "XOR8rm", 0|(1<<TID::MayLoad), 0|6|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2510 = XOR8rm
+ { 2511, 3, 1, 0, "XOR8rr", 0|(1<<TID::Commutable), 0|3|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2511 = XOR8rr
+ { 2512, 3, 1, 0, "XOR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2512 = XOR8rr_REV
+ { 2513, 7, 1, 0, "XORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2513 = XORPDrm
+ { 2514, 3, 1, 0, "XORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2514 = XORPDrr
+ { 2515, 7, 1, 0, "XORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2515 = XORPSrm
+ { 2516, 3, 1, 0, "XORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2516 = XORPSrr
};
} // End llvm namespace
diff --git a/libclamav/c++/X86GenInstrNames.inc b/libclamav/c++/X86GenInstrNames.inc
index e107252..42f4ac9 100644
--- a/libclamav/c++/X86GenInstrNames.inc
+++ b/libclamav/c++/X86GenInstrNames.inc
@@ -21,2510 +21,2513 @@ namespace X86 {
IMPLICIT_DEF = 8,
SUBREG_TO_REG = 9,
COPY_TO_REGCLASS = 10,
- ABS_F = 11,
- ABS_Fp32 = 12,
- ABS_Fp64 = 13,
- ABS_Fp80 = 14,
- ADC16i16 = 15,
- ADC16mi = 16,
- ADC16mi8 = 17,
- ADC16mr = 18,
- ADC16ri = 19,
- ADC16ri8 = 20,
- ADC16rm = 21,
- ADC16rr = 22,
- ADC16rr_REV = 23,
- ADC32i32 = 24,
- ADC32mi = 25,
- ADC32mi8 = 26,
- ADC32mr = 27,
- ADC32ri = 28,
- ADC32ri8 = 29,
- ADC32rm = 30,
- ADC32rr = 31,
- ADC32rr_REV = 32,
- ADC64i32 = 33,
- ADC64mi32 = 34,
- ADC64mi8 = 35,
- ADC64mr = 36,
- ADC64ri32 = 37,
- ADC64ri8 = 38,
- ADC64rm = 39,
- ADC64rr = 40,
- ADC64rr_REV = 41,
- ADC8i8 = 42,
- ADC8mi = 43,
- ADC8mr = 44,
- ADC8ri = 45,
- ADC8rm = 46,
- ADC8rr = 47,
- ADC8rr_REV = 48,
- ADD16i16 = 49,
- ADD16mi = 50,
- ADD16mi8 = 51,
- ADD16mr = 52,
- ADD16mrmrr = 53,
- ADD16ri = 54,
- ADD16ri8 = 55,
- ADD16rm = 56,
- ADD16rr = 57,
- ADD32i32 = 58,
- ADD32mi = 59,
- ADD32mi8 = 60,
- ADD32mr = 61,
- ADD32mrmrr = 62,
- ADD32ri = 63,
- ADD32ri8 = 64,
- ADD32rm = 65,
- ADD32rr = 66,
- ADD64i32 = 67,
- ADD64mi32 = 68,
- ADD64mi8 = 69,
- ADD64mr = 70,
- ADD64mrmrr = 71,
- ADD64ri32 = 72,
- ADD64ri8 = 73,
- ADD64rm = 74,
- ADD64rr = 75,
- ADD8i8 = 76,
- ADD8mi = 77,
- ADD8mr = 78,
- ADD8mrmrr = 79,
- ADD8ri = 80,
- ADD8rm = 81,
- ADD8rr = 82,
- ADDPDrm = 83,
- ADDPDrr = 84,
- ADDPSrm = 85,
- ADDPSrr = 86,
- ADDSDrm = 87,
- ADDSDrm_Int = 88,
- ADDSDrr = 89,
- ADDSDrr_Int = 90,
- ADDSSrm = 91,
- ADDSSrm_Int = 92,
- ADDSSrr = 93,
- ADDSSrr_Int = 94,
- ADDSUBPDrm = 95,
- ADDSUBPDrr = 96,
- ADDSUBPSrm = 97,
- ADDSUBPSrr = 98,
- ADD_F32m = 99,
- ADD_F64m = 100,
- ADD_FI16m = 101,
- ADD_FI32m = 102,
- ADD_FPrST0 = 103,
- ADD_FST0r = 104,
- ADD_Fp32 = 105,
- ADD_Fp32m = 106,
- ADD_Fp64 = 107,
- ADD_Fp64m = 108,
- ADD_Fp64m32 = 109,
- ADD_Fp80 = 110,
- ADD_Fp80m32 = 111,
- ADD_Fp80m64 = 112,
- ADD_FpI16m32 = 113,
- ADD_FpI16m64 = 114,
- ADD_FpI16m80 = 115,
- ADD_FpI32m32 = 116,
- ADD_FpI32m64 = 117,
- ADD_FpI32m80 = 118,
- ADD_FrST0 = 119,
- ADJCALLSTACKDOWN32 = 120,
- ADJCALLSTACKDOWN64 = 121,
- ADJCALLSTACKUP32 = 122,
- ADJCALLSTACKUP64 = 123,
- AND16i16 = 124,
- AND16mi = 125,
- AND16mi8 = 126,
- AND16mr = 127,
- AND16ri = 128,
- AND16ri8 = 129,
- AND16rm = 130,
- AND16rr = 131,
- AND16rr_REV = 132,
- AND32i32 = 133,
- AND32mi = 134,
- AND32mi8 = 135,
- AND32mr = 136,
- AND32ri = 137,
- AND32ri8 = 138,
- AND32rm = 139,
- AND32rr = 140,
- AND32rr_REV = 141,
- AND64i32 = 142,
- AND64mi32 = 143,
- AND64mi8 = 144,
- AND64mr = 145,
- AND64ri32 = 146,
- AND64ri8 = 147,
- AND64rm = 148,
- AND64rr = 149,
- AND64rr_REV = 150,
- AND8i8 = 151,
- AND8mi = 152,
- AND8mr = 153,
- AND8ri = 154,
- AND8rm = 155,
- AND8rr = 156,
- AND8rr_REV = 157,
- ANDNPDrm = 158,
- ANDNPDrr = 159,
- ANDNPSrm = 160,
- ANDNPSrr = 161,
- ANDPDrm = 162,
- ANDPDrr = 163,
- ANDPSrm = 164,
- ANDPSrr = 165,
- ATOMADD6432 = 166,
- ATOMAND16 = 167,
- ATOMAND32 = 168,
- ATOMAND64 = 169,
- ATOMAND6432 = 170,
- ATOMAND8 = 171,
- ATOMMAX16 = 172,
- ATOMMAX32 = 173,
- ATOMMAX64 = 174,
- ATOMMIN16 = 175,
- ATOMMIN32 = 176,
- ATOMMIN64 = 177,
- ATOMNAND16 = 178,
- ATOMNAND32 = 179,
- ATOMNAND64 = 180,
- ATOMNAND6432 = 181,
- ATOMNAND8 = 182,
- ATOMOR16 = 183,
- ATOMOR32 = 184,
- ATOMOR64 = 185,
- ATOMOR6432 = 186,
- ATOMOR8 = 187,
- ATOMSUB6432 = 188,
- ATOMSWAP6432 = 189,
- ATOMUMAX16 = 190,
- ATOMUMAX32 = 191,
- ATOMUMAX64 = 192,
- ATOMUMIN16 = 193,
- ATOMUMIN32 = 194,
- ATOMUMIN64 = 195,
- ATOMXOR16 = 196,
- ATOMXOR32 = 197,
- ATOMXOR64 = 198,
- ATOMXOR6432 = 199,
- ATOMXOR8 = 200,
- BLENDPDrmi = 201,
- BLENDPDrri = 202,
- BLENDPSrmi = 203,
- BLENDPSrri = 204,
- BLENDVPDrm0 = 205,
- BLENDVPDrr0 = 206,
- BLENDVPSrm0 = 207,
- BLENDVPSrr0 = 208,
- BSF16rm = 209,
- BSF16rr = 210,
- BSF32rm = 211,
- BSF32rr = 212,
- BSF64rm = 213,
- BSF64rr = 214,
- BSR16rm = 215,
- BSR16rr = 216,
- BSR32rm = 217,
- BSR32rr = 218,
- BSR64rm = 219,
- BSR64rr = 220,
- BSWAP32r = 221,
- BSWAP64r = 222,
- BT16mi8 = 223,
- BT16mr = 224,
- BT16ri8 = 225,
- BT16rr = 226,
- BT32mi8 = 227,
- BT32mr = 228,
- BT32ri8 = 229,
- BT32rr = 230,
- BT64mi8 = 231,
- BT64mr = 232,
- BT64ri8 = 233,
- BT64rr = 234,
- BTC16mi8 = 235,
- BTC16mr = 236,
- BTC16ri8 = 237,
- BTC16rr = 238,
- BTC32mi8 = 239,
- BTC32mr = 240,
- BTC32ri8 = 241,
- BTC32rr = 242,
- BTC64mi8 = 243,
- BTC64mr = 244,
- BTC64ri8 = 245,
- BTC64rr = 246,
- BTR16mi8 = 247,
- BTR16mr = 248,
- BTR16ri8 = 249,
- BTR16rr = 250,
- BTR32mi8 = 251,
- BTR32mr = 252,
- BTR32ri8 = 253,
- BTR32rr = 254,
- BTR64mi8 = 255,
- BTR64mr = 256,
- BTR64ri8 = 257,
- BTR64rr = 258,
- BTS16mi8 = 259,
- BTS16mr = 260,
- BTS16ri8 = 261,
- BTS16rr = 262,
- BTS32mi8 = 263,
- BTS32mr = 264,
- BTS32ri8 = 265,
- BTS32rr = 266,
- BTS64mi8 = 267,
- BTS64mr = 268,
- BTS64ri8 = 269,
- BTS64rr = 270,
- CALL32m = 271,
- CALL32r = 272,
- CALL64m = 273,
- CALL64pcrel32 = 274,
- CALL64r = 275,
- CALLpcrel32 = 276,
- CBW = 277,
- CDQ = 278,
- CDQE = 279,
- CHS_F = 280,
- CHS_Fp32 = 281,
- CHS_Fp64 = 282,
- CHS_Fp80 = 283,
- CLC = 284,
- CLD = 285,
- CLFLUSH = 286,
- CLI = 287,
- CLTS = 288,
- CMC = 289,
- CMOVA16rm = 290,
- CMOVA16rr = 291,
- CMOVA32rm = 292,
- CMOVA32rr = 293,
- CMOVA64rm = 294,
- CMOVA64rr = 295,
- CMOVAE16rm = 296,
- CMOVAE16rr = 297,
- CMOVAE32rm = 298,
- CMOVAE32rr = 299,
- CMOVAE64rm = 300,
- CMOVAE64rr = 301,
- CMOVB16rm = 302,
- CMOVB16rr = 303,
- CMOVB32rm = 304,
- CMOVB32rr = 305,
- CMOVB64rm = 306,
- CMOVB64rr = 307,
- CMOVBE16rm = 308,
- CMOVBE16rr = 309,
- CMOVBE32rm = 310,
- CMOVBE32rr = 311,
- CMOVBE64rm = 312,
- CMOVBE64rr = 313,
- CMOVBE_F = 314,
- CMOVBE_Fp32 = 315,
- CMOVBE_Fp64 = 316,
- CMOVBE_Fp80 = 317,
- CMOVB_F = 318,
- CMOVB_Fp32 = 319,
- CMOVB_Fp64 = 320,
- CMOVB_Fp80 = 321,
- CMOVE16rm = 322,
- CMOVE16rr = 323,
- CMOVE32rm = 324,
- CMOVE32rr = 325,
- CMOVE64rm = 326,
- CMOVE64rr = 327,
- CMOVE_F = 328,
- CMOVE_Fp32 = 329,
- CMOVE_Fp64 = 330,
- CMOVE_Fp80 = 331,
- CMOVG16rm = 332,
- CMOVG16rr = 333,
- CMOVG32rm = 334,
- CMOVG32rr = 335,
- CMOVG64rm = 336,
- CMOVG64rr = 337,
- CMOVGE16rm = 338,
- CMOVGE16rr = 339,
- CMOVGE32rm = 340,
- CMOVGE32rr = 341,
- CMOVGE64rm = 342,
- CMOVGE64rr = 343,
- CMOVL16rm = 344,
- CMOVL16rr = 345,
- CMOVL32rm = 346,
- CMOVL32rr = 347,
- CMOVL64rm = 348,
- CMOVL64rr = 349,
- CMOVLE16rm = 350,
- CMOVLE16rr = 351,
- CMOVLE32rm = 352,
- CMOVLE32rr = 353,
- CMOVLE64rm = 354,
- CMOVLE64rr = 355,
- CMOVNBE_F = 356,
- CMOVNBE_Fp32 = 357,
- CMOVNBE_Fp64 = 358,
- CMOVNBE_Fp80 = 359,
- CMOVNB_F = 360,
- CMOVNB_Fp32 = 361,
- CMOVNB_Fp64 = 362,
- CMOVNB_Fp80 = 363,
- CMOVNE16rm = 364,
- CMOVNE16rr = 365,
- CMOVNE32rm = 366,
- CMOVNE32rr = 367,
- CMOVNE64rm = 368,
- CMOVNE64rr = 369,
- CMOVNE_F = 370,
- CMOVNE_Fp32 = 371,
- CMOVNE_Fp64 = 372,
- CMOVNE_Fp80 = 373,
- CMOVNO16rm = 374,
- CMOVNO16rr = 375,
- CMOVNO32rm = 376,
- CMOVNO32rr = 377,
- CMOVNO64rm = 378,
- CMOVNO64rr = 379,
- CMOVNP16rm = 380,
- CMOVNP16rr = 381,
- CMOVNP32rm = 382,
- CMOVNP32rr = 383,
- CMOVNP64rm = 384,
- CMOVNP64rr = 385,
- CMOVNP_F = 386,
- CMOVNP_Fp32 = 387,
- CMOVNP_Fp64 = 388,
- CMOVNP_Fp80 = 389,
- CMOVNS16rm = 390,
- CMOVNS16rr = 391,
- CMOVNS32rm = 392,
- CMOVNS32rr = 393,
- CMOVNS64rm = 394,
- CMOVNS64rr = 395,
- CMOVO16rm = 396,
- CMOVO16rr = 397,
- CMOVO32rm = 398,
- CMOVO32rr = 399,
- CMOVO64rm = 400,
- CMOVO64rr = 401,
- CMOVP16rm = 402,
- CMOVP16rr = 403,
- CMOVP32rm = 404,
- CMOVP32rr = 405,
- CMOVP64rm = 406,
- CMOVP64rr = 407,
- CMOVP_F = 408,
- CMOVP_Fp32 = 409,
- CMOVP_Fp64 = 410,
- CMOVP_Fp80 = 411,
- CMOVS16rm = 412,
- CMOVS16rr = 413,
- CMOVS32rm = 414,
- CMOVS32rr = 415,
- CMOVS64rm = 416,
- CMOVS64rr = 417,
- CMOV_FR32 = 418,
- CMOV_FR64 = 419,
- CMOV_GR8 = 420,
- CMOV_V1I64 = 421,
- CMOV_V2F64 = 422,
- CMOV_V2I64 = 423,
- CMOV_V4F32 = 424,
- CMP16i16 = 425,
- CMP16mi = 426,
- CMP16mi8 = 427,
- CMP16mr = 428,
- CMP16mrmrr = 429,
- CMP16ri = 430,
- CMP16ri8 = 431,
- CMP16rm = 432,
- CMP16rr = 433,
- CMP32i32 = 434,
- CMP32mi = 435,
- CMP32mi8 = 436,
- CMP32mr = 437,
- CMP32mrmrr = 438,
- CMP32ri = 439,
- CMP32ri8 = 440,
- CMP32rm = 441,
- CMP32rr = 442,
- CMP64i32 = 443,
- CMP64mi32 = 444,
- CMP64mi8 = 445,
- CMP64mr = 446,
- CMP64mrmrr = 447,
- CMP64ri32 = 448,
- CMP64ri8 = 449,
- CMP64rm = 450,
- CMP64rr = 451,
- CMP8i8 = 452,
- CMP8mi = 453,
- CMP8mr = 454,
- CMP8mrmrr = 455,
- CMP8ri = 456,
- CMP8rm = 457,
- CMP8rr = 458,
- CMPPDrmi = 459,
- CMPPDrri = 460,
- CMPPSrmi = 461,
- CMPPSrri = 462,
- CMPS16 = 463,
- CMPS32 = 464,
- CMPS64 = 465,
- CMPS8 = 466,
- CMPSDrm = 467,
- CMPSDrr = 468,
- CMPSSrm = 469,
- CMPSSrr = 470,
- CMPXCHG16B = 471,
- CMPXCHG16rm = 472,
- CMPXCHG16rr = 473,
- CMPXCHG32rm = 474,
- CMPXCHG32rr = 475,
- CMPXCHG64rm = 476,
- CMPXCHG64rr = 477,
- CMPXCHG8B = 478,
- CMPXCHG8rm = 479,
- CMPXCHG8rr = 480,
- COMISDrm = 481,
- COMISDrr = 482,
- COMISSrm = 483,
- COMISSrr = 484,
- COMP_FST0r = 485,
- COM_FIPr = 486,
- COM_FIr = 487,
- COM_FST0r = 488,
- COS_F = 489,
- COS_Fp32 = 490,
- COS_Fp64 = 491,
- COS_Fp80 = 492,
- CPUID = 493,
- CQO = 494,
- CRC32m16 = 495,
- CRC32m32 = 496,
- CRC32m8 = 497,
- CRC32r16 = 498,
- CRC32r32 = 499,
- CRC32r8 = 500,
- CRC64m64 = 501,
- CRC64r64 = 502,
- CVTDQ2PDrm = 503,
- CVTDQ2PDrr = 504,
- CVTDQ2PSrm = 505,
- CVTDQ2PSrr = 506,
- CVTPD2DQrm = 507,
- CVTPD2DQrr = 508,
- CVTPD2PSrm = 509,
- CVTPD2PSrr = 510,
- CVTPS2DQrm = 511,
- CVTPS2DQrr = 512,
- CVTPS2PDrm = 513,
- CVTPS2PDrr = 514,
- CVTSD2SI64rm = 515,
- CVTSD2SI64rr = 516,
- CVTSD2SSrm = 517,
- CVTSD2SSrr = 518,
- CVTSI2SD64rm = 519,
- CVTSI2SD64rr = 520,
- CVTSI2SDrm = 521,
- CVTSI2SDrr = 522,
- CVTSI2SS64rm = 523,
- CVTSI2SS64rr = 524,
- CVTSI2SSrm = 525,
- CVTSI2SSrr = 526,
- CVTSS2SDrm = 527,
- CVTSS2SDrr = 528,
- CVTSS2SI64rm = 529,
- CVTSS2SI64rr = 530,
- CVTSS2SIrm = 531,
- CVTSS2SIrr = 532,
- CVTTPS2DQrm = 533,
- CVTTPS2DQrr = 534,
- CVTTSD2SI64rm = 535,
- CVTTSD2SI64rr = 536,
- CVTTSD2SIrm = 537,
- CVTTSD2SIrr = 538,
- CVTTSS2SI64rm = 539,
- CVTTSS2SI64rr = 540,
- CVTTSS2SIrm = 541,
- CVTTSS2SIrr = 542,
- CWD = 543,
- CWDE = 544,
- DEC16m = 545,
- DEC16r = 546,
- DEC32m = 547,
- DEC32r = 548,
- DEC64_16m = 549,
- DEC64_16r = 550,
- DEC64_32m = 551,
- DEC64_32r = 552,
- DEC64m = 553,
- DEC64r = 554,
- DEC8m = 555,
- DEC8r = 556,
- DIV16m = 557,
- DIV16r = 558,
- DIV32m = 559,
- DIV32r = 560,
- DIV64m = 561,
- DIV64r = 562,
- DIV8m = 563,
- DIV8r = 564,
- DIVPDrm = 565,
- DIVPDrr = 566,
- DIVPSrm = 567,
- DIVPSrr = 568,
- DIVR_F32m = 569,
- DIVR_F64m = 570,
- DIVR_FI16m = 571,
- DIVR_FI32m = 572,
- DIVR_FPrST0 = 573,
- DIVR_FST0r = 574,
- DIVR_Fp32m = 575,
- DIVR_Fp64m = 576,
- DIVR_Fp64m32 = 577,
- DIVR_Fp80m32 = 578,
- DIVR_Fp80m64 = 579,
- DIVR_FpI16m32 = 580,
- DIVR_FpI16m64 = 581,
- DIVR_FpI16m80 = 582,
- DIVR_FpI32m32 = 583,
- DIVR_FpI32m64 = 584,
- DIVR_FpI32m80 = 585,
- DIVR_FrST0 = 586,
- DIVSDrm = 587,
- DIVSDrm_Int = 588,
- DIVSDrr = 589,
- DIVSDrr_Int = 590,
- DIVSSrm = 591,
- DIVSSrm_Int = 592,
- DIVSSrr = 593,
- DIVSSrr_Int = 594,
- DIV_F32m = 595,
- DIV_F64m = 596,
- DIV_FI16m = 597,
- DIV_FI32m = 598,
- DIV_FPrST0 = 599,
- DIV_FST0r = 600,
- DIV_Fp32 = 601,
- DIV_Fp32m = 602,
- DIV_Fp64 = 603,
- DIV_Fp64m = 604,
- DIV_Fp64m32 = 605,
- DIV_Fp80 = 606,
- DIV_Fp80m32 = 607,
- DIV_Fp80m64 = 608,
- DIV_FpI16m32 = 609,
- DIV_FpI16m64 = 610,
- DIV_FpI16m80 = 611,
- DIV_FpI32m32 = 612,
- DIV_FpI32m64 = 613,
- DIV_FpI32m80 = 614,
- DIV_FrST0 = 615,
- DPPDrmi = 616,
- DPPDrri = 617,
- DPPSrmi = 618,
- DPPSrri = 619,
- EH_RETURN = 620,
- EH_RETURN64 = 621,
- ENTER = 622,
- EXTRACTPSmr = 623,
- EXTRACTPSrr = 624,
- F2XM1 = 625,
- FARCALL16i = 626,
- FARCALL16m = 627,
- FARCALL32i = 628,
- FARCALL32m = 629,
- FARCALL64 = 630,
- FARJMP16i = 631,
- FARJMP16m = 632,
- FARJMP32i = 633,
- FARJMP32m = 634,
- FARJMP64 = 635,
- FBLDm = 636,
- FBSTPm = 637,
- FCOM32m = 638,
- FCOM64m = 639,
- FCOMP32m = 640,
- FCOMP64m = 641,
- FCOMPP = 642,
- FDECSTP = 643,
- FFREE = 644,
- FICOM16m = 645,
- FICOM32m = 646,
- FICOMP16m = 647,
- FICOMP32m = 648,
- FINCSTP = 649,
- FISTTP32m = 650,
- FLDCW16m = 651,
- FLDENVm = 652,
- FLDL2E = 653,
- FLDL2T = 654,
- FLDLG2 = 655,
- FLDLN2 = 656,
- FLDPI = 657,
- FNCLEX = 658,
- FNINIT = 659,
- FNOP = 660,
- FNSTCW16m = 661,
- FNSTSW8r = 662,
- FNSTSWm = 663,
- FP32_TO_INT16_IN_MEM = 664,
- FP32_TO_INT32_IN_MEM = 665,
- FP32_TO_INT64_IN_MEM = 666,
- FP64_TO_INT16_IN_MEM = 667,
- FP64_TO_INT32_IN_MEM = 668,
- FP64_TO_INT64_IN_MEM = 669,
- FP80_TO_INT16_IN_MEM = 670,
- FP80_TO_INT32_IN_MEM = 671,
- FP80_TO_INT64_IN_MEM = 672,
- FPATAN = 673,
- FPREM = 674,
- FPREM1 = 675,
- FPTAN = 676,
- FP_REG_KILL = 677,
- FRNDINT = 678,
- FRSTORm = 679,
- FSAVEm = 680,
- FSCALE = 681,
- FSINCOS = 682,
- FSTENVm = 683,
- FS_MOV32rm = 684,
- FXAM = 685,
- FXRSTOR = 686,
- FXSAVE = 687,
- FXTRACT = 688,
- FYL2X = 689,
- FYL2XP1 = 690,
- FpGET_ST0_32 = 691,
- FpGET_ST0_64 = 692,
- FpGET_ST0_80 = 693,
- FpGET_ST1_32 = 694,
- FpGET_ST1_64 = 695,
- FpGET_ST1_80 = 696,
- FpSET_ST0_32 = 697,
- FpSET_ST0_64 = 698,
- FpSET_ST0_80 = 699,
- FpSET_ST1_32 = 700,
- FpSET_ST1_64 = 701,
- FpSET_ST1_80 = 702,
- FsANDNPDrm = 703,
- FsANDNPDrr = 704,
- FsANDNPSrm = 705,
- FsANDNPSrr = 706,
- FsANDPDrm = 707,
- FsANDPDrr = 708,
- FsANDPSrm = 709,
- FsANDPSrr = 710,
- FsFLD0SD = 711,
- FsFLD0SS = 712,
- FsMOVAPDrm = 713,
- FsMOVAPDrr = 714,
- FsMOVAPSrm = 715,
- FsMOVAPSrr = 716,
- FsORPDrm = 717,
- FsORPDrr = 718,
- FsORPSrm = 719,
- FsORPSrr = 720,
- FsXORPDrm = 721,
- FsXORPDrr = 722,
- FsXORPSrm = 723,
- FsXORPSrr = 724,
- GS_MOV32rm = 725,
- HADDPDrm = 726,
- HADDPDrr = 727,
- HADDPSrm = 728,
- HADDPSrr = 729,
- HLT = 730,
- HSUBPDrm = 731,
- HSUBPDrr = 732,
- HSUBPSrm = 733,
- HSUBPSrr = 734,
- IDIV16m = 735,
- IDIV16r = 736,
- IDIV32m = 737,
- IDIV32r = 738,
- IDIV64m = 739,
- IDIV64r = 740,
- IDIV8m = 741,
- IDIV8r = 742,
- ILD_F16m = 743,
- ILD_F32m = 744,
- ILD_F64m = 745,
- ILD_Fp16m32 = 746,
- ILD_Fp16m64 = 747,
- ILD_Fp16m80 = 748,
- ILD_Fp32m32 = 749,
- ILD_Fp32m64 = 750,
- ILD_Fp32m80 = 751,
- ILD_Fp64m32 = 752,
- ILD_Fp64m64 = 753,
- ILD_Fp64m80 = 754,
- IMUL16m = 755,
- IMUL16r = 756,
- IMUL16rm = 757,
- IMUL16rmi = 758,
- IMUL16rmi8 = 759,
- IMUL16rr = 760,
- IMUL16rri = 761,
- IMUL16rri8 = 762,
- IMUL32m = 763,
- IMUL32r = 764,
- IMUL32rm = 765,
- IMUL32rmi = 766,
- IMUL32rmi8 = 767,
- IMUL32rr = 768,
- IMUL32rri = 769,
- IMUL32rri8 = 770,
- IMUL64m = 771,
- IMUL64r = 772,
- IMUL64rm = 773,
- IMUL64rmi32 = 774,
- IMUL64rmi8 = 775,
- IMUL64rr = 776,
- IMUL64rri32 = 777,
- IMUL64rri8 = 778,
- IMUL8m = 779,
- IMUL8r = 780,
- IN16 = 781,
- IN16ri = 782,
- IN16rr = 783,
- IN32 = 784,
- IN32ri = 785,
- IN32rr = 786,
- IN8 = 787,
- IN8ri = 788,
- IN8rr = 789,
- INC16m = 790,
- INC16r = 791,
- INC32m = 792,
- INC32r = 793,
- INC64_16m = 794,
- INC64_16r = 795,
- INC64_32m = 796,
- INC64_32r = 797,
- INC64m = 798,
- INC64r = 799,
- INC8m = 800,
- INC8r = 801,
- INSERTPSrm = 802,
- INSERTPSrr = 803,
- INT = 804,
- INT3 = 805,
- INVD = 806,
- INVEPT = 807,
- INVLPG = 808,
- INVVPID = 809,
- IRET16 = 810,
- IRET32 = 811,
- IRET64 = 812,
- ISTT_FP16m = 813,
- ISTT_FP32m = 814,
- ISTT_FP64m = 815,
- ISTT_Fp16m32 = 816,
- ISTT_Fp16m64 = 817,
- ISTT_Fp16m80 = 818,
- ISTT_Fp32m32 = 819,
- ISTT_Fp32m64 = 820,
- ISTT_Fp32m80 = 821,
- ISTT_Fp64m32 = 822,
- ISTT_Fp64m64 = 823,
- ISTT_Fp64m80 = 824,
- IST_F16m = 825,
- IST_F32m = 826,
- IST_FP16m = 827,
- IST_FP32m = 828,
- IST_FP64m = 829,
- IST_Fp16m32 = 830,
- IST_Fp16m64 = 831,
- IST_Fp16m80 = 832,
- IST_Fp32m32 = 833,
- IST_Fp32m64 = 834,
- IST_Fp32m80 = 835,
- IST_Fp64m32 = 836,
- IST_Fp64m64 = 837,
- IST_Fp64m80 = 838,
- Int_CMPSDrm = 839,
- Int_CMPSDrr = 840,
- Int_CMPSSrm = 841,
- Int_CMPSSrr = 842,
- Int_COMISDrm = 843,
- Int_COMISDrr = 844,
- Int_COMISSrm = 845,
- Int_COMISSrr = 846,
- Int_CVTDQ2PDrm = 847,
- Int_CVTDQ2PDrr = 848,
- Int_CVTDQ2PSrm = 849,
- Int_CVTDQ2PSrr = 850,
- Int_CVTPD2DQrm = 851,
- Int_CVTPD2DQrr = 852,
- Int_CVTPD2PIrm = 853,
- Int_CVTPD2PIrr = 854,
- Int_CVTPD2PSrm = 855,
- Int_CVTPD2PSrr = 856,
- Int_CVTPI2PDrm = 857,
- Int_CVTPI2PDrr = 858,
- Int_CVTPI2PSrm = 859,
- Int_CVTPI2PSrr = 860,
- Int_CVTPS2DQrm = 861,
- Int_CVTPS2DQrr = 862,
- Int_CVTPS2PDrm = 863,
- Int_CVTPS2PDrr = 864,
- Int_CVTPS2PIrm = 865,
- Int_CVTPS2PIrr = 866,
- Int_CVTSD2SI64rm = 867,
- Int_CVTSD2SI64rr = 868,
- Int_CVTSD2SIrm = 869,
- Int_CVTSD2SIrr = 870,
- Int_CVTSD2SSrm = 871,
- Int_CVTSD2SSrr = 872,
- Int_CVTSI2SD64rm = 873,
- Int_CVTSI2SD64rr = 874,
- Int_CVTSI2SDrm = 875,
- Int_CVTSI2SDrr = 876,
- Int_CVTSI2SS64rm = 877,
- Int_CVTSI2SS64rr = 878,
- Int_CVTSI2SSrm = 879,
- Int_CVTSI2SSrr = 880,
- Int_CVTSS2SDrm = 881,
- Int_CVTSS2SDrr = 882,
- Int_CVTSS2SI64rm = 883,
- Int_CVTSS2SI64rr = 884,
- Int_CVTSS2SIrm = 885,
- Int_CVTSS2SIrr = 886,
- Int_CVTTPD2DQrm = 887,
- Int_CVTTPD2DQrr = 888,
- Int_CVTTPD2PIrm = 889,
- Int_CVTTPD2PIrr = 890,
- Int_CVTTPS2DQrm = 891,
- Int_CVTTPS2DQrr = 892,
- Int_CVTTPS2PIrm = 893,
- Int_CVTTPS2PIrr = 894,
- Int_CVTTSD2SI64rm = 895,
- Int_CVTTSD2SI64rr = 896,
- Int_CVTTSD2SIrm = 897,
- Int_CVTTSD2SIrr = 898,
- Int_CVTTSS2SI64rm = 899,
- Int_CVTTSS2SI64rr = 900,
- Int_CVTTSS2SIrm = 901,
- Int_CVTTSS2SIrr = 902,
- Int_UCOMISDrm = 903,
- Int_UCOMISDrr = 904,
- Int_UCOMISSrm = 905,
- Int_UCOMISSrr = 906,
- JA = 907,
- JA8 = 908,
- JAE = 909,
- JAE8 = 910,
- JB = 911,
- JB8 = 912,
- JBE = 913,
- JBE8 = 914,
- JCXZ8 = 915,
- JE = 916,
- JE8 = 917,
- JG = 918,
- JG8 = 919,
- JGE = 920,
- JGE8 = 921,
- JL = 922,
- JL8 = 923,
- JLE = 924,
- JLE8 = 925,
- JMP = 926,
- JMP32m = 927,
- JMP32r = 928,
- JMP64m = 929,
- JMP64pcrel32 = 930,
- JMP64r = 931,
- JMP8 = 932,
- JNE = 933,
- JNE8 = 934,
- JNO = 935,
- JNO8 = 936,
- JNP = 937,
- JNP8 = 938,
- JNS = 939,
- JNS8 = 940,
- JO = 941,
- JO8 = 942,
- JP = 943,
- JP8 = 944,
- JS = 945,
- JS8 = 946,
- LAHF = 947,
- LAR16rm = 948,
- LAR16rr = 949,
- LAR32rm = 950,
- LAR32rr = 951,
- LAR64rm = 952,
- LAR64rr = 953,
- LCMPXCHG16 = 954,
- LCMPXCHG32 = 955,
- LCMPXCHG64 = 956,
- LCMPXCHG8 = 957,
- LCMPXCHG8B = 958,
- LDDQUrm = 959,
- LDMXCSR = 960,
- LDS16rm = 961,
- LDS32rm = 962,
- LD_F0 = 963,
- LD_F1 = 964,
- LD_F32m = 965,
- LD_F64m = 966,
- LD_F80m = 967,
- LD_Fp032 = 968,
- LD_Fp064 = 969,
- LD_Fp080 = 970,
- LD_Fp132 = 971,
- LD_Fp164 = 972,
- LD_Fp180 = 973,
- LD_Fp32m = 974,
- LD_Fp32m64 = 975,
- LD_Fp32m80 = 976,
- LD_Fp64m = 977,
- LD_Fp64m80 = 978,
- LD_Fp80m = 979,
- LD_Frr = 980,
- LEA16r = 981,
- LEA32r = 982,
- LEA64_32r = 983,
- LEA64r = 984,
- LEAVE = 985,
- LEAVE64 = 986,
- LES16rm = 987,
- LES32rm = 988,
- LFENCE = 989,
- LFS16rm = 990,
- LFS32rm = 991,
- LFS64rm = 992,
- LGDTm = 993,
- LGS16rm = 994,
- LGS32rm = 995,
- LGS64rm = 996,
- LIDTm = 997,
- LLDT16m = 998,
- LLDT16r = 999,
- LMSW16m = 1000,
- LMSW16r = 1001,
- LOCK_ADD16mi = 1002,
- LOCK_ADD16mi8 = 1003,
- LOCK_ADD16mr = 1004,
- LOCK_ADD32mi = 1005,
- LOCK_ADD32mi8 = 1006,
- LOCK_ADD32mr = 1007,
- LOCK_ADD64mi32 = 1008,
- LOCK_ADD64mi8 = 1009,
- LOCK_ADD64mr = 1010,
- LOCK_ADD8mi = 1011,
- LOCK_ADD8mr = 1012,
- LOCK_DEC16m = 1013,
- LOCK_DEC32m = 1014,
- LOCK_DEC64m = 1015,
- LOCK_DEC8m = 1016,
- LOCK_INC16m = 1017,
- LOCK_INC32m = 1018,
- LOCK_INC64m = 1019,
- LOCK_INC8m = 1020,
- LOCK_SUB16mi = 1021,
- LOCK_SUB16mi8 = 1022,
- LOCK_SUB16mr = 1023,
- LOCK_SUB32mi = 1024,
- LOCK_SUB32mi8 = 1025,
- LOCK_SUB32mr = 1026,
- LOCK_SUB64mi32 = 1027,
- LOCK_SUB64mi8 = 1028,
- LOCK_SUB64mr = 1029,
- LOCK_SUB8mi = 1030,
- LOCK_SUB8mr = 1031,
- LODSB = 1032,
- LODSD = 1033,
- LODSQ = 1034,
- LODSW = 1035,
- LOOP = 1036,
- LOOPE = 1037,
- LOOPNE = 1038,
- LRET = 1039,
- LRETI = 1040,
- LSL16rm = 1041,
- LSL16rr = 1042,
- LSL32rm = 1043,
- LSL32rr = 1044,
- LSL64rm = 1045,
- LSL64rr = 1046,
- LSS16rm = 1047,
- LSS32rm = 1048,
- LSS64rm = 1049,
- LTRm = 1050,
- LTRr = 1051,
- LXADD16 = 1052,
- LXADD32 = 1053,
- LXADD64 = 1054,
- LXADD8 = 1055,
- MASKMOVDQU = 1056,
- MASKMOVDQU64 = 1057,
- MAXPDrm = 1058,
- MAXPDrm_Int = 1059,
- MAXPDrr = 1060,
- MAXPDrr_Int = 1061,
- MAXPSrm = 1062,
- MAXPSrm_Int = 1063,
- MAXPSrr = 1064,
- MAXPSrr_Int = 1065,
- MAXSDrm = 1066,
- MAXSDrm_Int = 1067,
- MAXSDrr = 1068,
- MAXSDrr_Int = 1069,
- MAXSSrm = 1070,
- MAXSSrm_Int = 1071,
- MAXSSrr = 1072,
- MAXSSrr_Int = 1073,
- MFENCE = 1074,
- MINPDrm = 1075,
- MINPDrm_Int = 1076,
- MINPDrr = 1077,
- MINPDrr_Int = 1078,
- MINPSrm = 1079,
- MINPSrm_Int = 1080,
- MINPSrr = 1081,
- MINPSrr_Int = 1082,
- MINSDrm = 1083,
- MINSDrm_Int = 1084,
- MINSDrr = 1085,
- MINSDrr_Int = 1086,
- MINSSrm = 1087,
- MINSSrm_Int = 1088,
- MINSSrr = 1089,
- MINSSrr_Int = 1090,
- MMX_CVTPD2PIrm = 1091,
- MMX_CVTPD2PIrr = 1092,
- MMX_CVTPI2PDrm = 1093,
- MMX_CVTPI2PDrr = 1094,
- MMX_CVTPI2PSrm = 1095,
- MMX_CVTPI2PSrr = 1096,
- MMX_CVTPS2PIrm = 1097,
- MMX_CVTPS2PIrr = 1098,
- MMX_CVTTPD2PIrm = 1099,
- MMX_CVTTPD2PIrr = 1100,
- MMX_CVTTPS2PIrm = 1101,
- MMX_CVTTPS2PIrr = 1102,
- MMX_EMMS = 1103,
- MMX_FEMMS = 1104,
- MMX_MASKMOVQ = 1105,
- MMX_MASKMOVQ64 = 1106,
- MMX_MOVD64from64rr = 1107,
- MMX_MOVD64grr = 1108,
- MMX_MOVD64mr = 1109,
- MMX_MOVD64rm = 1110,
- MMX_MOVD64rr = 1111,
- MMX_MOVD64rrv164 = 1112,
- MMX_MOVD64to64rr = 1113,
- MMX_MOVDQ2Qrr = 1114,
- MMX_MOVNTQmr = 1115,
- MMX_MOVQ2DQrr = 1116,
- MMX_MOVQ2FR64rr = 1117,
- MMX_MOVQ64gmr = 1118,
- MMX_MOVQ64mr = 1119,
- MMX_MOVQ64rm = 1120,
- MMX_MOVQ64rr = 1121,
- MMX_MOVZDI2PDIrm = 1122,
- MMX_MOVZDI2PDIrr = 1123,
- MMX_PACKSSDWrm = 1124,
- MMX_PACKSSDWrr = 1125,
- MMX_PACKSSWBrm = 1126,
- MMX_PACKSSWBrr = 1127,
- MMX_PACKUSWBrm = 1128,
- MMX_PACKUSWBrr = 1129,
- MMX_PADDBrm = 1130,
- MMX_PADDBrr = 1131,
- MMX_PADDDrm = 1132,
- MMX_PADDDrr = 1133,
- MMX_PADDQrm = 1134,
- MMX_PADDQrr = 1135,
- MMX_PADDSBrm = 1136,
- MMX_PADDSBrr = 1137,
- MMX_PADDSWrm = 1138,
- MMX_PADDSWrr = 1139,
- MMX_PADDUSBrm = 1140,
- MMX_PADDUSBrr = 1141,
- MMX_PADDUSWrm = 1142,
- MMX_PADDUSWrr = 1143,
- MMX_PADDWrm = 1144,
- MMX_PADDWrr = 1145,
- MMX_PANDNrm = 1146,
- MMX_PANDNrr = 1147,
- MMX_PANDrm = 1148,
- MMX_PANDrr = 1149,
- MMX_PAVGBrm = 1150,
- MMX_PAVGBrr = 1151,
- MMX_PAVGWrm = 1152,
- MMX_PAVGWrr = 1153,
- MMX_PCMPEQBrm = 1154,
- MMX_PCMPEQBrr = 1155,
- MMX_PCMPEQDrm = 1156,
- MMX_PCMPEQDrr = 1157,
- MMX_PCMPEQWrm = 1158,
- MMX_PCMPEQWrr = 1159,
- MMX_PCMPGTBrm = 1160,
- MMX_PCMPGTBrr = 1161,
- MMX_PCMPGTDrm = 1162,
- MMX_PCMPGTDrr = 1163,
- MMX_PCMPGTWrm = 1164,
- MMX_PCMPGTWrr = 1165,
- MMX_PEXTRWri = 1166,
- MMX_PINSRWrmi = 1167,
- MMX_PINSRWrri = 1168,
- MMX_PMADDWDrm = 1169,
- MMX_PMADDWDrr = 1170,
- MMX_PMAXSWrm = 1171,
- MMX_PMAXSWrr = 1172,
- MMX_PMAXUBrm = 1173,
- MMX_PMAXUBrr = 1174,
- MMX_PMINSWrm = 1175,
- MMX_PMINSWrr = 1176,
- MMX_PMINUBrm = 1177,
- MMX_PMINUBrr = 1178,
- MMX_PMOVMSKBrr = 1179,
- MMX_PMULHUWrm = 1180,
- MMX_PMULHUWrr = 1181,
- MMX_PMULHWrm = 1182,
- MMX_PMULHWrr = 1183,
- MMX_PMULLWrm = 1184,
- MMX_PMULLWrr = 1185,
- MMX_PMULUDQrm = 1186,
- MMX_PMULUDQrr = 1187,
- MMX_PORrm = 1188,
- MMX_PORrr = 1189,
- MMX_PSADBWrm = 1190,
- MMX_PSADBWrr = 1191,
- MMX_PSHUFWmi = 1192,
- MMX_PSHUFWri = 1193,
- MMX_PSLLDri = 1194,
- MMX_PSLLDrm = 1195,
- MMX_PSLLDrr = 1196,
- MMX_PSLLQri = 1197,
- MMX_PSLLQrm = 1198,
- MMX_PSLLQrr = 1199,
- MMX_PSLLWri = 1200,
- MMX_PSLLWrm = 1201,
- MMX_PSLLWrr = 1202,
- MMX_PSRADri = 1203,
- MMX_PSRADrm = 1204,
- MMX_PSRADrr = 1205,
- MMX_PSRAWri = 1206,
- MMX_PSRAWrm = 1207,
- MMX_PSRAWrr = 1208,
- MMX_PSRLDri = 1209,
- MMX_PSRLDrm = 1210,
- MMX_PSRLDrr = 1211,
- MMX_PSRLQri = 1212,
- MMX_PSRLQrm = 1213,
- MMX_PSRLQrr = 1214,
- MMX_PSRLWri = 1215,
- MMX_PSRLWrm = 1216,
- MMX_PSRLWrr = 1217,
- MMX_PSUBBrm = 1218,
- MMX_PSUBBrr = 1219,
- MMX_PSUBDrm = 1220,
- MMX_PSUBDrr = 1221,
- MMX_PSUBQrm = 1222,
- MMX_PSUBQrr = 1223,
- MMX_PSUBSBrm = 1224,
- MMX_PSUBSBrr = 1225,
- MMX_PSUBSWrm = 1226,
- MMX_PSUBSWrr = 1227,
- MMX_PSUBUSBrm = 1228,
- MMX_PSUBUSBrr = 1229,
- MMX_PSUBUSWrm = 1230,
- MMX_PSUBUSWrr = 1231,
- MMX_PSUBWrm = 1232,
- MMX_PSUBWrr = 1233,
- MMX_PUNPCKHBWrm = 1234,
- MMX_PUNPCKHBWrr = 1235,
- MMX_PUNPCKHDQrm = 1236,
- MMX_PUNPCKHDQrr = 1237,
- MMX_PUNPCKHWDrm = 1238,
- MMX_PUNPCKHWDrr = 1239,
- MMX_PUNPCKLBWrm = 1240,
- MMX_PUNPCKLBWrr = 1241,
- MMX_PUNPCKLDQrm = 1242,
- MMX_PUNPCKLDQrr = 1243,
- MMX_PUNPCKLWDrm = 1244,
- MMX_PUNPCKLWDrr = 1245,
- MMX_PXORrm = 1246,
- MMX_PXORrr = 1247,
- MMX_V_SET0 = 1248,
- MMX_V_SETALLONES = 1249,
- MONITOR = 1250,
- MOV16ao16 = 1251,
- MOV16mi = 1252,
- MOV16mr = 1253,
- MOV16ms = 1254,
- MOV16o16a = 1255,
- MOV16ri = 1256,
- MOV16rm = 1257,
- MOV16rr = 1258,
- MOV16rr_REV = 1259,
- MOV16rs = 1260,
- MOV16sm = 1261,
- MOV16sr = 1262,
- MOV32ao32 = 1263,
- MOV32cr = 1264,
- MOV32dr = 1265,
- MOV32mi = 1266,
- MOV32mr = 1267,
- MOV32o32a = 1268,
- MOV32r0 = 1269,
- MOV32rc = 1270,
- MOV32rd = 1271,
- MOV32ri = 1272,
- MOV32rm = 1273,
- MOV32rr = 1274,
- MOV32rr_REV = 1275,
- MOV64FSrm = 1276,
- MOV64GSrm = 1277,
- MOV64ao64 = 1278,
- MOV64ao8 = 1279,
- MOV64cr = 1280,
- MOV64dr = 1281,
- MOV64mi32 = 1282,
- MOV64mr = 1283,
- MOV64ms = 1284,
- MOV64o64a = 1285,
- MOV64o8a = 1286,
- MOV64rc = 1287,
- MOV64rd = 1288,
- MOV64ri = 1289,
- MOV64ri32 = 1290,
- MOV64ri64i32 = 1291,
- MOV64rm = 1292,
- MOV64rr = 1293,
- MOV64rr_REV = 1294,
- MOV64rs = 1295,
- MOV64sm = 1296,
- MOV64sr = 1297,
- MOV64toPQIrr = 1298,
- MOV64toSDrm = 1299,
- MOV64toSDrr = 1300,
- MOV8ao8 = 1301,
- MOV8mi = 1302,
- MOV8mr = 1303,
- MOV8mr_NOREX = 1304,
- MOV8o8a = 1305,
- MOV8r0 = 1306,
- MOV8ri = 1307,
- MOV8rm = 1308,
- MOV8rm_NOREX = 1309,
- MOV8rr = 1310,
- MOV8rr_NOREX = 1311,
- MOV8rr_REV = 1312,
- MOVAPDmr = 1313,
- MOVAPDrm = 1314,
- MOVAPDrr = 1315,
- MOVAPSmr = 1316,
- MOVAPSrm = 1317,
- MOVAPSrr = 1318,
- MOVDDUPrm = 1319,
- MOVDDUPrr = 1320,
- MOVDI2PDIrm = 1321,
- MOVDI2PDIrr = 1322,
- MOVDI2SSrm = 1323,
- MOVDI2SSrr = 1324,
- MOVDQAmr = 1325,
- MOVDQArm = 1326,
- MOVDQArr = 1327,
- MOVDQUmr = 1328,
- MOVDQUmr_Int = 1329,
- MOVDQUrm = 1330,
- MOVDQUrm_Int = 1331,
- MOVHLPSrr = 1332,
- MOVHPDmr = 1333,
- MOVHPDrm = 1334,
- MOVHPSmr = 1335,
- MOVHPSrm = 1336,
- MOVLHPSrr = 1337,
- MOVLPDmr = 1338,
- MOVLPDrm = 1339,
- MOVLPDrr = 1340,
- MOVLPSmr = 1341,
- MOVLPSrm = 1342,
- MOVLPSrr = 1343,
- MOVLQ128mr = 1344,
- MOVLSD2PDrr = 1345,
- MOVLSS2PSrr = 1346,
- MOVMSKPDrr = 1347,
- MOVMSKPSrr = 1348,
- MOVNTDQArm = 1349,
- MOVNTDQmr = 1350,
- MOVNTImr = 1351,
- MOVNTPDmr = 1352,
- MOVNTPSmr = 1353,
- MOVPC32r = 1354,
- MOVPD2SDmr = 1355,
- MOVPD2SDrr = 1356,
- MOVPDI2DImr = 1357,
- MOVPDI2DIrr = 1358,
- MOVPQI2QImr = 1359,
- MOVPQIto64rr = 1360,
- MOVPS2SSmr = 1361,
- MOVPS2SSrr = 1362,
- MOVQI2PQIrm = 1363,
- MOVQxrxr = 1364,
- MOVSD2PDrm = 1365,
- MOVSD2PDrr = 1366,
- MOVSDmr = 1367,
- MOVSDrm = 1368,
- MOVSDrr = 1369,
- MOVSDto64mr = 1370,
- MOVSDto64rr = 1371,
- MOVSHDUPrm = 1372,
- MOVSHDUPrr = 1373,
- MOVSLDUPrm = 1374,
- MOVSLDUPrr = 1375,
- MOVSS2DImr = 1376,
- MOVSS2DIrr = 1377,
- MOVSS2PSrm = 1378,
- MOVSS2PSrr = 1379,
- MOVSSmr = 1380,
- MOVSSrm = 1381,
- MOVSSrr = 1382,
- MOVSX16rm8 = 1383,
- MOVSX16rm8W = 1384,
- MOVSX16rr8 = 1385,
- MOVSX16rr8W = 1386,
- MOVSX32rm16 = 1387,
- MOVSX32rm8 = 1388,
- MOVSX32rr16 = 1389,
- MOVSX32rr8 = 1390,
- MOVSX64rm16 = 1391,
- MOVSX64rm32 = 1392,
- MOVSX64rm8 = 1393,
- MOVSX64rr16 = 1394,
- MOVSX64rr32 = 1395,
- MOVSX64rr8 = 1396,
- MOVUPDmr = 1397,
- MOVUPDmr_Int = 1398,
- MOVUPDrm = 1399,
- MOVUPDrm_Int = 1400,
- MOVUPDrr = 1401,
- MOVUPSmr = 1402,
- MOVUPSmr_Int = 1403,
- MOVUPSrm = 1404,
- MOVUPSrm_Int = 1405,
- MOVUPSrr = 1406,
- MOVZDI2PDIrm = 1407,
- MOVZDI2PDIrr = 1408,
- MOVZPQILo2PQIrm = 1409,
- MOVZPQILo2PQIrr = 1410,
- MOVZQI2PQIrm = 1411,
- MOVZQI2PQIrr = 1412,
- MOVZSD2PDrm = 1413,
- MOVZSS2PSrm = 1414,
- MOVZX16rm8 = 1415,
- MOVZX16rm8W = 1416,
- MOVZX16rr8 = 1417,
- MOVZX16rr8W = 1418,
- MOVZX32_NOREXrm8 = 1419,
- MOVZX32_NOREXrr8 = 1420,
- MOVZX32rm16 = 1421,
- MOVZX32rm8 = 1422,
- MOVZX32rr16 = 1423,
- MOVZX32rr8 = 1424,
- MOVZX64rm16 = 1425,
- MOVZX64rm16_Q = 1426,
- MOVZX64rm32 = 1427,
- MOVZX64rm8 = 1428,
- MOVZX64rm8_Q = 1429,
- MOVZX64rr16 = 1430,
- MOVZX64rr16_Q = 1431,
- MOVZX64rr32 = 1432,
- MOVZX64rr8 = 1433,
- MOVZX64rr8_Q = 1434,
- MOV_Fp3232 = 1435,
- MOV_Fp3264 = 1436,
- MOV_Fp3280 = 1437,
- MOV_Fp6432 = 1438,
- MOV_Fp6464 = 1439,
- MOV_Fp6480 = 1440,
- MOV_Fp8032 = 1441,
- MOV_Fp8064 = 1442,
- MOV_Fp8080 = 1443,
- MPSADBWrmi = 1444,
- MPSADBWrri = 1445,
- MUL16m = 1446,
- MUL16r = 1447,
- MUL32m = 1448,
- MUL32r = 1449,
- MUL64m = 1450,
- MUL64r = 1451,
- MUL8m = 1452,
- MUL8r = 1453,
- MULPDrm = 1454,
- MULPDrr = 1455,
- MULPSrm = 1456,
- MULPSrr = 1457,
- MULSDrm = 1458,
- MULSDrm_Int = 1459,
- MULSDrr = 1460,
- MULSDrr_Int = 1461,
- MULSSrm = 1462,
- MULSSrm_Int = 1463,
- MULSSrr = 1464,
- MULSSrr_Int = 1465,
- MUL_F32m = 1466,
- MUL_F64m = 1467,
- MUL_FI16m = 1468,
- MUL_FI32m = 1469,
- MUL_FPrST0 = 1470,
- MUL_FST0r = 1471,
- MUL_Fp32 = 1472,
- MUL_Fp32m = 1473,
- MUL_Fp64 = 1474,
- MUL_Fp64m = 1475,
- MUL_Fp64m32 = 1476,
- MUL_Fp80 = 1477,
- MUL_Fp80m32 = 1478,
- MUL_Fp80m64 = 1479,
- MUL_FpI16m32 = 1480,
- MUL_FpI16m64 = 1481,
- MUL_FpI16m80 = 1482,
- MUL_FpI32m32 = 1483,
- MUL_FpI32m64 = 1484,
- MUL_FpI32m80 = 1485,
- MUL_FrST0 = 1486,
- MWAIT = 1487,
- NEG16m = 1488,
- NEG16r = 1489,
- NEG32m = 1490,
- NEG32r = 1491,
- NEG64m = 1492,
- NEG64r = 1493,
- NEG8m = 1494,
- NEG8r = 1495,
- NOOP = 1496,
- NOOPL = 1497,
- NOOPW = 1498,
- NOT16m = 1499,
- NOT16r = 1500,
- NOT32m = 1501,
- NOT32r = 1502,
- NOT64m = 1503,
- NOT64r = 1504,
- NOT8m = 1505,
- NOT8r = 1506,
- OR16i16 = 1507,
- OR16mi = 1508,
- OR16mi8 = 1509,
- OR16mr = 1510,
- OR16ri = 1511,
- OR16ri8 = 1512,
- OR16rm = 1513,
- OR16rr = 1514,
- OR16rr_REV = 1515,
- OR32i32 = 1516,
- OR32mi = 1517,
- OR32mi8 = 1518,
- OR32mr = 1519,
- OR32ri = 1520,
- OR32ri8 = 1521,
- OR32rm = 1522,
- OR32rr = 1523,
- OR32rr_REV = 1524,
- OR64i32 = 1525,
- OR64mi32 = 1526,
- OR64mi8 = 1527,
- OR64mr = 1528,
- OR64ri32 = 1529,
- OR64ri8 = 1530,
- OR64rm = 1531,
- OR64rr = 1532,
- OR64rr_REV = 1533,
- OR8i8 = 1534,
- OR8mi = 1535,
- OR8mr = 1536,
- OR8ri = 1537,
- OR8rm = 1538,
- OR8rr = 1539,
- OR8rr_REV = 1540,
- ORPDrm = 1541,
- ORPDrr = 1542,
- ORPSrm = 1543,
- ORPSrr = 1544,
- OUT16ir = 1545,
- OUT16rr = 1546,
- OUT32ir = 1547,
- OUT32rr = 1548,
- OUT8ir = 1549,
- OUT8rr = 1550,
- OUTSB = 1551,
- OUTSD = 1552,
- OUTSW = 1553,
- PABSBrm128 = 1554,
- PABSBrm64 = 1555,
- PABSBrr128 = 1556,
- PABSBrr64 = 1557,
- PABSDrm128 = 1558,
- PABSDrm64 = 1559,
- PABSDrr128 = 1560,
- PABSDrr64 = 1561,
- PABSWrm128 = 1562,
- PABSWrm64 = 1563,
- PABSWrr128 = 1564,
- PABSWrr64 = 1565,
- PACKSSDWrm = 1566,
- PACKSSDWrr = 1567,
- PACKSSWBrm = 1568,
- PACKSSWBrr = 1569,
- PACKUSDWrm = 1570,
- PACKUSDWrr = 1571,
- PACKUSWBrm = 1572,
- PACKUSWBrr = 1573,
- PADDBrm = 1574,
- PADDBrr = 1575,
- PADDDrm = 1576,
- PADDDrr = 1577,
- PADDQrm = 1578,
- PADDQrr = 1579,
- PADDSBrm = 1580,
- PADDSBrr = 1581,
- PADDSWrm = 1582,
- PADDSWrr = 1583,
- PADDUSBrm = 1584,
- PADDUSBrr = 1585,
- PADDUSWrm = 1586,
- PADDUSWrr = 1587,
- PADDWrm = 1588,
- PADDWrr = 1589,
- PALIGNR128rm = 1590,
- PALIGNR128rr = 1591,
- PALIGNR64rm = 1592,
- PALIGNR64rr = 1593,
- PANDNrm = 1594,
- PANDNrr = 1595,
- PANDrm = 1596,
- PANDrr = 1597,
- PAVGBrm = 1598,
- PAVGBrr = 1599,
- PAVGWrm = 1600,
- PAVGWrr = 1601,
- PBLENDVBrm0 = 1602,
- PBLENDVBrr0 = 1603,
- PBLENDWrmi = 1604,
- PBLENDWrri = 1605,
- PCMPEQBrm = 1606,
- PCMPEQBrr = 1607,
- PCMPEQDrm = 1608,
- PCMPEQDrr = 1609,
- PCMPEQQrm = 1610,
- PCMPEQQrr = 1611,
- PCMPEQWrm = 1612,
- PCMPEQWrr = 1613,
- PCMPESTRIArm = 1614,
- PCMPESTRIArr = 1615,
- PCMPESTRICrm = 1616,
- PCMPESTRICrr = 1617,
- PCMPESTRIOrm = 1618,
- PCMPESTRIOrr = 1619,
- PCMPESTRISrm = 1620,
- PCMPESTRISrr = 1621,
- PCMPESTRIZrm = 1622,
- PCMPESTRIZrr = 1623,
- PCMPESTRIrm = 1624,
- PCMPESTRIrr = 1625,
- PCMPESTRM128MEM = 1626,
- PCMPESTRM128REG = 1627,
- PCMPESTRM128rm = 1628,
- PCMPESTRM128rr = 1629,
- PCMPGTBrm = 1630,
- PCMPGTBrr = 1631,
- PCMPGTDrm = 1632,
- PCMPGTDrr = 1633,
- PCMPGTQrm = 1634,
- PCMPGTQrr = 1635,
- PCMPGTWrm = 1636,
- PCMPGTWrr = 1637,
- PCMPISTRIArm = 1638,
- PCMPISTRIArr = 1639,
- PCMPISTRICrm = 1640,
- PCMPISTRICrr = 1641,
- PCMPISTRIOrm = 1642,
- PCMPISTRIOrr = 1643,
- PCMPISTRISrm = 1644,
- PCMPISTRISrr = 1645,
- PCMPISTRIZrm = 1646,
- PCMPISTRIZrr = 1647,
- PCMPISTRIrm = 1648,
- PCMPISTRIrr = 1649,
- PCMPISTRM128MEM = 1650,
- PCMPISTRM128REG = 1651,
- PCMPISTRM128rm = 1652,
- PCMPISTRM128rr = 1653,
- PEXTRBmr = 1654,
- PEXTRBrr = 1655,
- PEXTRDmr = 1656,
- PEXTRDrr = 1657,
- PEXTRQmr = 1658,
- PEXTRQrr = 1659,
- PEXTRWmr = 1660,
- PEXTRWri = 1661,
- PHADDDrm128 = 1662,
- PHADDDrm64 = 1663,
- PHADDDrr128 = 1664,
- PHADDDrr64 = 1665,
- PHADDSWrm128 = 1666,
- PHADDSWrm64 = 1667,
- PHADDSWrr128 = 1668,
- PHADDSWrr64 = 1669,
- PHADDWrm128 = 1670,
- PHADDWrm64 = 1671,
- PHADDWrr128 = 1672,
- PHADDWrr64 = 1673,
- PHMINPOSUWrm128 = 1674,
- PHMINPOSUWrr128 = 1675,
- PHSUBDrm128 = 1676,
- PHSUBDrm64 = 1677,
- PHSUBDrr128 = 1678,
- PHSUBDrr64 = 1679,
- PHSUBSWrm128 = 1680,
- PHSUBSWrm64 = 1681,
- PHSUBSWrr128 = 1682,
- PHSUBSWrr64 = 1683,
- PHSUBWrm128 = 1684,
- PHSUBWrm64 = 1685,
- PHSUBWrr128 = 1686,
- PHSUBWrr64 = 1687,
- PINSRBrm = 1688,
- PINSRBrr = 1689,
- PINSRDrm = 1690,
- PINSRDrr = 1691,
- PINSRQrm = 1692,
- PINSRQrr = 1693,
- PINSRWrmi = 1694,
- PINSRWrri = 1695,
- PMADDUBSWrm128 = 1696,
- PMADDUBSWrm64 = 1697,
- PMADDUBSWrr128 = 1698,
- PMADDUBSWrr64 = 1699,
- PMADDWDrm = 1700,
- PMADDWDrr = 1701,
- PMAXSBrm = 1702,
- PMAXSBrr = 1703,
- PMAXSDrm = 1704,
- PMAXSDrr = 1705,
- PMAXSWrm = 1706,
- PMAXSWrr = 1707,
- PMAXUBrm = 1708,
- PMAXUBrr = 1709,
- PMAXUDrm = 1710,
- PMAXUDrr = 1711,
- PMAXUWrm = 1712,
- PMAXUWrr = 1713,
- PMINSBrm = 1714,
- PMINSBrr = 1715,
- PMINSDrm = 1716,
- PMINSDrr = 1717,
- PMINSWrm = 1718,
- PMINSWrr = 1719,
- PMINUBrm = 1720,
- PMINUBrr = 1721,
- PMINUDrm = 1722,
- PMINUDrr = 1723,
- PMINUWrm = 1724,
- PMINUWrr = 1725,
- PMOVMSKBrr = 1726,
- PMOVSXBDrm = 1727,
- PMOVSXBDrr = 1728,
- PMOVSXBQrm = 1729,
- PMOVSXBQrr = 1730,
- PMOVSXBWrm = 1731,
- PMOVSXBWrr = 1732,
- PMOVSXDQrm = 1733,
- PMOVSXDQrr = 1734,
- PMOVSXWDrm = 1735,
- PMOVSXWDrr = 1736,
- PMOVSXWQrm = 1737,
- PMOVSXWQrr = 1738,
- PMOVZXBDrm = 1739,
- PMOVZXBDrr = 1740,
- PMOVZXBQrm = 1741,
- PMOVZXBQrr = 1742,
- PMOVZXBWrm = 1743,
- PMOVZXBWrr = 1744,
- PMOVZXDQrm = 1745,
- PMOVZXDQrr = 1746,
- PMOVZXWDrm = 1747,
- PMOVZXWDrr = 1748,
- PMOVZXWQrm = 1749,
- PMOVZXWQrr = 1750,
- PMULDQrm = 1751,
- PMULDQrr = 1752,
- PMULHRSWrm128 = 1753,
- PMULHRSWrm64 = 1754,
- PMULHRSWrr128 = 1755,
- PMULHRSWrr64 = 1756,
- PMULHUWrm = 1757,
- PMULHUWrr = 1758,
- PMULHWrm = 1759,
- PMULHWrr = 1760,
- PMULLDrm = 1761,
- PMULLDrm_int = 1762,
- PMULLDrr = 1763,
- PMULLDrr_int = 1764,
- PMULLWrm = 1765,
- PMULLWrr = 1766,
- PMULUDQrm = 1767,
- PMULUDQrr = 1768,
- POP16r = 1769,
- POP16rmm = 1770,
- POP16rmr = 1771,
- POP32r = 1772,
- POP32rmm = 1773,
- POP32rmr = 1774,
- POP64r = 1775,
- POP64rmm = 1776,
- POP64rmr = 1777,
- POPCNT16rm = 1778,
- POPCNT16rr = 1779,
- POPCNT32rm = 1780,
- POPCNT32rr = 1781,
- POPCNT64rm = 1782,
- POPCNT64rr = 1783,
- POPF = 1784,
- POPFD = 1785,
- POPFQ = 1786,
- POPFS16 = 1787,
- POPFS32 = 1788,
- POPFS64 = 1789,
- POPGS16 = 1790,
- POPGS32 = 1791,
- POPGS64 = 1792,
- PORrm = 1793,
- PORrr = 1794,
- PREFETCHNTA = 1795,
- PREFETCHT0 = 1796,
- PREFETCHT1 = 1797,
- PREFETCHT2 = 1798,
- PSADBWrm = 1799,
- PSADBWrr = 1800,
- PSHUFBrm128 = 1801,
- PSHUFBrm64 = 1802,
- PSHUFBrr128 = 1803,
- PSHUFBrr64 = 1804,
- PSHUFDmi = 1805,
- PSHUFDri = 1806,
- PSHUFHWmi = 1807,
- PSHUFHWri = 1808,
- PSHUFLWmi = 1809,
- PSHUFLWri = 1810,
- PSIGNBrm128 = 1811,
- PSIGNBrm64 = 1812,
- PSIGNBrr128 = 1813,
- PSIGNBrr64 = 1814,
- PSIGNDrm128 = 1815,
- PSIGNDrm64 = 1816,
- PSIGNDrr128 = 1817,
- PSIGNDrr64 = 1818,
- PSIGNWrm128 = 1819,
- PSIGNWrm64 = 1820,
- PSIGNWrr128 = 1821,
- PSIGNWrr64 = 1822,
- PSLLDQri = 1823,
- PSLLDri = 1824,
- PSLLDrm = 1825,
- PSLLDrr = 1826,
- PSLLQri = 1827,
- PSLLQrm = 1828,
- PSLLQrr = 1829,
- PSLLWri = 1830,
- PSLLWrm = 1831,
- PSLLWrr = 1832,
- PSRADri = 1833,
- PSRADrm = 1834,
- PSRADrr = 1835,
- PSRAWri = 1836,
- PSRAWrm = 1837,
- PSRAWrr = 1838,
- PSRLDQri = 1839,
- PSRLDri = 1840,
- PSRLDrm = 1841,
- PSRLDrr = 1842,
- PSRLQri = 1843,
- PSRLQrm = 1844,
- PSRLQrr = 1845,
- PSRLWri = 1846,
- PSRLWrm = 1847,
- PSRLWrr = 1848,
- PSUBBrm = 1849,
- PSUBBrr = 1850,
- PSUBDrm = 1851,
- PSUBDrr = 1852,
- PSUBQrm = 1853,
- PSUBQrr = 1854,
- PSUBSBrm = 1855,
- PSUBSBrr = 1856,
- PSUBSWrm = 1857,
- PSUBSWrr = 1858,
- PSUBUSBrm = 1859,
- PSUBUSBrr = 1860,
- PSUBUSWrm = 1861,
- PSUBUSWrr = 1862,
- PSUBWrm = 1863,
- PSUBWrr = 1864,
- PTESTrm = 1865,
- PTESTrr = 1866,
- PUNPCKHBWrm = 1867,
- PUNPCKHBWrr = 1868,
- PUNPCKHDQrm = 1869,
- PUNPCKHDQrr = 1870,
- PUNPCKHQDQrm = 1871,
- PUNPCKHQDQrr = 1872,
- PUNPCKHWDrm = 1873,
- PUNPCKHWDrr = 1874,
- PUNPCKLBWrm = 1875,
- PUNPCKLBWrr = 1876,
- PUNPCKLDQrm = 1877,
- PUNPCKLDQrr = 1878,
- PUNPCKLQDQrm = 1879,
- PUNPCKLQDQrr = 1880,
- PUNPCKLWDrm = 1881,
- PUNPCKLWDrr = 1882,
- PUSH16r = 1883,
- PUSH16rmm = 1884,
- PUSH16rmr = 1885,
- PUSH32i16 = 1886,
- PUSH32i32 = 1887,
- PUSH32i8 = 1888,
- PUSH32r = 1889,
- PUSH32rmm = 1890,
- PUSH32rmr = 1891,
- PUSH64i16 = 1892,
- PUSH64i32 = 1893,
- PUSH64i8 = 1894,
- PUSH64r = 1895,
- PUSH64rmm = 1896,
- PUSH64rmr = 1897,
- PUSHF = 1898,
- PUSHFD = 1899,
- PUSHFQ64 = 1900,
- PUSHFS16 = 1901,
- PUSHFS32 = 1902,
- PUSHFS64 = 1903,
- PUSHGS16 = 1904,
- PUSHGS32 = 1905,
- PUSHGS64 = 1906,
- PXORrm = 1907,
- PXORrr = 1908,
- RCL16m1 = 1909,
- RCL16mCL = 1910,
- RCL16mi = 1911,
- RCL16r1 = 1912,
- RCL16rCL = 1913,
- RCL16ri = 1914,
- RCL32m1 = 1915,
- RCL32mCL = 1916,
- RCL32mi = 1917,
- RCL32r1 = 1918,
- RCL32rCL = 1919,
- RCL32ri = 1920,
- RCL64m1 = 1921,
- RCL64mCL = 1922,
- RCL64mi = 1923,
- RCL64r1 = 1924,
- RCL64rCL = 1925,
- RCL64ri = 1926,
- RCL8m1 = 1927,
- RCL8mCL = 1928,
- RCL8mi = 1929,
- RCL8r1 = 1930,
- RCL8rCL = 1931,
- RCL8ri = 1932,
- RCPPSm = 1933,
- RCPPSm_Int = 1934,
- RCPPSr = 1935,
- RCPPSr_Int = 1936,
- RCPSSm = 1937,
- RCPSSm_Int = 1938,
- RCPSSr = 1939,
- RCPSSr_Int = 1940,
- RCR16m1 = 1941,
- RCR16mCL = 1942,
- RCR16mi = 1943,
- RCR16r1 = 1944,
- RCR16rCL = 1945,
- RCR16ri = 1946,
- RCR32m1 = 1947,
- RCR32mCL = 1948,
- RCR32mi = 1949,
- RCR32r1 = 1950,
- RCR32rCL = 1951,
- RCR32ri = 1952,
- RCR64m1 = 1953,
- RCR64mCL = 1954,
- RCR64mi = 1955,
- RCR64r1 = 1956,
- RCR64rCL = 1957,
- RCR64ri = 1958,
- RCR8m1 = 1959,
- RCR8mCL = 1960,
- RCR8mi = 1961,
- RCR8r1 = 1962,
- RCR8rCL = 1963,
- RCR8ri = 1964,
- RDMSR = 1965,
- RDPMC = 1966,
- RDTSC = 1967,
- REP_MOVSB = 1968,
- REP_MOVSD = 1969,
- REP_MOVSQ = 1970,
- REP_MOVSW = 1971,
- REP_STOSB = 1972,
- REP_STOSD = 1973,
- REP_STOSQ = 1974,
- REP_STOSW = 1975,
- RET = 1976,
- RETI = 1977,
- ROL16m1 = 1978,
- ROL16mCL = 1979,
- ROL16mi = 1980,
- ROL16r1 = 1981,
- ROL16rCL = 1982,
- ROL16ri = 1983,
- ROL32m1 = 1984,
- ROL32mCL = 1985,
- ROL32mi = 1986,
- ROL32r1 = 1987,
- ROL32rCL = 1988,
- ROL32ri = 1989,
- ROL64m1 = 1990,
- ROL64mCL = 1991,
- ROL64mi = 1992,
- ROL64r1 = 1993,
- ROL64rCL = 1994,
- ROL64ri = 1995,
- ROL8m1 = 1996,
- ROL8mCL = 1997,
- ROL8mi = 1998,
- ROL8r1 = 1999,
- ROL8rCL = 2000,
- ROL8ri = 2001,
- ROR16m1 = 2002,
- ROR16mCL = 2003,
- ROR16mi = 2004,
- ROR16r1 = 2005,
- ROR16rCL = 2006,
- ROR16ri = 2007,
- ROR32m1 = 2008,
- ROR32mCL = 2009,
- ROR32mi = 2010,
- ROR32r1 = 2011,
- ROR32rCL = 2012,
- ROR32ri = 2013,
- ROR64m1 = 2014,
- ROR64mCL = 2015,
- ROR64mi = 2016,
- ROR64r1 = 2017,
- ROR64rCL = 2018,
- ROR64ri = 2019,
- ROR8m1 = 2020,
- ROR8mCL = 2021,
- ROR8mi = 2022,
- ROR8r1 = 2023,
- ROR8rCL = 2024,
- ROR8ri = 2025,
- ROUNDPDm_Int = 2026,
- ROUNDPDr_Int = 2027,
- ROUNDPSm_Int = 2028,
- ROUNDPSr_Int = 2029,
- ROUNDSDm_Int = 2030,
- ROUNDSDr_Int = 2031,
- ROUNDSSm_Int = 2032,
- ROUNDSSr_Int = 2033,
- RSM = 2034,
- RSQRTPSm = 2035,
- RSQRTPSm_Int = 2036,
- RSQRTPSr = 2037,
- RSQRTPSr_Int = 2038,
- RSQRTSSm = 2039,
- RSQRTSSm_Int = 2040,
- RSQRTSSr = 2041,
- RSQRTSSr_Int = 2042,
- SAHF = 2043,
- SAR16m1 = 2044,
- SAR16mCL = 2045,
- SAR16mi = 2046,
- SAR16r1 = 2047,
- SAR16rCL = 2048,
- SAR16ri = 2049,
- SAR32m1 = 2050,
- SAR32mCL = 2051,
- SAR32mi = 2052,
- SAR32r1 = 2053,
- SAR32rCL = 2054,
- SAR32ri = 2055,
- SAR64m1 = 2056,
- SAR64mCL = 2057,
- SAR64mi = 2058,
- SAR64r1 = 2059,
- SAR64rCL = 2060,
- SAR64ri = 2061,
- SAR8m1 = 2062,
- SAR8mCL = 2063,
- SAR8mi = 2064,
- SAR8r1 = 2065,
- SAR8rCL = 2066,
- SAR8ri = 2067,
- SBB16i16 = 2068,
- SBB16mi = 2069,
- SBB16mi8 = 2070,
- SBB16mr = 2071,
- SBB16ri = 2072,
- SBB16ri8 = 2073,
- SBB16rm = 2074,
- SBB16rr = 2075,
- SBB16rr_REV = 2076,
- SBB32i32 = 2077,
- SBB32mi = 2078,
- SBB32mi8 = 2079,
- SBB32mr = 2080,
- SBB32ri = 2081,
- SBB32ri8 = 2082,
- SBB32rm = 2083,
- SBB32rr = 2084,
- SBB32rr_REV = 2085,
- SBB64i32 = 2086,
- SBB64mi32 = 2087,
- SBB64mi8 = 2088,
- SBB64mr = 2089,
- SBB64ri32 = 2090,
- SBB64ri8 = 2091,
- SBB64rm = 2092,
- SBB64rr = 2093,
- SBB64rr_REV = 2094,
- SBB8i8 = 2095,
- SBB8mi = 2096,
- SBB8mr = 2097,
- SBB8ri = 2098,
- SBB8rm = 2099,
- SBB8rr = 2100,
- SBB8rr_REV = 2101,
- SCAS16 = 2102,
- SCAS32 = 2103,
- SCAS64 = 2104,
- SCAS8 = 2105,
- SETAEm = 2106,
- SETAEr = 2107,
- SETAm = 2108,
- SETAr = 2109,
- SETBEm = 2110,
- SETBEr = 2111,
- SETB_C16r = 2112,
- SETB_C32r = 2113,
- SETB_C64r = 2114,
- SETB_C8r = 2115,
- SETBm = 2116,
- SETBr = 2117,
- SETEm = 2118,
- SETEr = 2119,
- SETGEm = 2120,
- SETGEr = 2121,
- SETGm = 2122,
- SETGr = 2123,
- SETLEm = 2124,
- SETLEr = 2125,
- SETLm = 2126,
- SETLr = 2127,
- SETNEm = 2128,
- SETNEr = 2129,
- SETNOm = 2130,
- SETNOr = 2131,
- SETNPm = 2132,
- SETNPr = 2133,
- SETNSm = 2134,
- SETNSr = 2135,
- SETOm = 2136,
- SETOr = 2137,
- SETPm = 2138,
- SETPr = 2139,
- SETSm = 2140,
- SETSr = 2141,
- SFENCE = 2142,
- SGDTm = 2143,
- SHL16m1 = 2144,
- SHL16mCL = 2145,
- SHL16mi = 2146,
- SHL16r1 = 2147,
- SHL16rCL = 2148,
- SHL16ri = 2149,
- SHL32m1 = 2150,
- SHL32mCL = 2151,
- SHL32mi = 2152,
- SHL32r1 = 2153,
- SHL32rCL = 2154,
- SHL32ri = 2155,
- SHL64m1 = 2156,
- SHL64mCL = 2157,
- SHL64mi = 2158,
- SHL64r1 = 2159,
- SHL64rCL = 2160,
- SHL64ri = 2161,
- SHL8m1 = 2162,
- SHL8mCL = 2163,
- SHL8mi = 2164,
- SHL8r1 = 2165,
- SHL8rCL = 2166,
- SHL8ri = 2167,
- SHLD16mrCL = 2168,
- SHLD16mri8 = 2169,
- SHLD16rrCL = 2170,
- SHLD16rri8 = 2171,
- SHLD32mrCL = 2172,
- SHLD32mri8 = 2173,
- SHLD32rrCL = 2174,
- SHLD32rri8 = 2175,
- SHLD64mrCL = 2176,
- SHLD64mri8 = 2177,
- SHLD64rrCL = 2178,
- SHLD64rri8 = 2179,
- SHR16m1 = 2180,
- SHR16mCL = 2181,
- SHR16mi = 2182,
- SHR16r1 = 2183,
- SHR16rCL = 2184,
- SHR16ri = 2185,
- SHR32m1 = 2186,
- SHR32mCL = 2187,
- SHR32mi = 2188,
- SHR32r1 = 2189,
- SHR32rCL = 2190,
- SHR32ri = 2191,
- SHR64m1 = 2192,
- SHR64mCL = 2193,
- SHR64mi = 2194,
- SHR64r1 = 2195,
- SHR64rCL = 2196,
- SHR64ri = 2197,
- SHR8m1 = 2198,
- SHR8mCL = 2199,
- SHR8mi = 2200,
- SHR8r1 = 2201,
- SHR8rCL = 2202,
- SHR8ri = 2203,
- SHRD16mrCL = 2204,
- SHRD16mri8 = 2205,
- SHRD16rrCL = 2206,
- SHRD16rri8 = 2207,
- SHRD32mrCL = 2208,
- SHRD32mri8 = 2209,
- SHRD32rrCL = 2210,
- SHRD32rri8 = 2211,
- SHRD64mrCL = 2212,
- SHRD64mri8 = 2213,
- SHRD64rrCL = 2214,
- SHRD64rri8 = 2215,
- SHUFPDrmi = 2216,
- SHUFPDrri = 2217,
- SHUFPSrmi = 2218,
- SHUFPSrri = 2219,
- SIDTm = 2220,
- SIN_F = 2221,
- SIN_Fp32 = 2222,
- SIN_Fp64 = 2223,
- SIN_Fp80 = 2224,
- SLDT16m = 2225,
- SLDT16r = 2226,
- SLDT64m = 2227,
- SLDT64r = 2228,
- SMSW16m = 2229,
- SMSW16r = 2230,
- SMSW32r = 2231,
- SMSW64r = 2232,
- SQRTPDm = 2233,
- SQRTPDm_Int = 2234,
- SQRTPDr = 2235,
- SQRTPDr_Int = 2236,
- SQRTPSm = 2237,
- SQRTPSm_Int = 2238,
- SQRTPSr = 2239,
- SQRTPSr_Int = 2240,
- SQRTSDm = 2241,
- SQRTSDm_Int = 2242,
- SQRTSDr = 2243,
- SQRTSDr_Int = 2244,
- SQRTSSm = 2245,
- SQRTSSm_Int = 2246,
- SQRTSSr = 2247,
- SQRTSSr_Int = 2248,
- SQRT_F = 2249,
- SQRT_Fp32 = 2250,
- SQRT_Fp64 = 2251,
- SQRT_Fp80 = 2252,
- STC = 2253,
- STD = 2254,
- STI = 2255,
- STMXCSR = 2256,
- STRm = 2257,
- STRr = 2258,
- ST_F32m = 2259,
- ST_F64m = 2260,
- ST_FP32m = 2261,
- ST_FP64m = 2262,
- ST_FP80m = 2263,
- ST_FPrr = 2264,
- ST_Fp32m = 2265,
- ST_Fp64m = 2266,
- ST_Fp64m32 = 2267,
- ST_Fp80m32 = 2268,
- ST_Fp80m64 = 2269,
- ST_FpP32m = 2270,
- ST_FpP64m = 2271,
- ST_FpP64m32 = 2272,
- ST_FpP80m = 2273,
- ST_FpP80m32 = 2274,
- ST_FpP80m64 = 2275,
- ST_Frr = 2276,
- SUB16i16 = 2277,
- SUB16mi = 2278,
- SUB16mi8 = 2279,
- SUB16mr = 2280,
- SUB16ri = 2281,
- SUB16ri8 = 2282,
- SUB16rm = 2283,
- SUB16rr = 2284,
- SUB16rr_REV = 2285,
- SUB32i32 = 2286,
- SUB32mi = 2287,
- SUB32mi8 = 2288,
- SUB32mr = 2289,
- SUB32ri = 2290,
- SUB32ri8 = 2291,
- SUB32rm = 2292,
- SUB32rr = 2293,
- SUB32rr_REV = 2294,
- SUB64i32 = 2295,
- SUB64mi32 = 2296,
- SUB64mi8 = 2297,
- SUB64mr = 2298,
- SUB64ri32 = 2299,
- SUB64ri8 = 2300,
- SUB64rm = 2301,
- SUB64rr = 2302,
- SUB64rr_REV = 2303,
- SUB8i8 = 2304,
- SUB8mi = 2305,
- SUB8mr = 2306,
- SUB8ri = 2307,
- SUB8rm = 2308,
- SUB8rr = 2309,
- SUB8rr_REV = 2310,
- SUBPDrm = 2311,
- SUBPDrr = 2312,
- SUBPSrm = 2313,
- SUBPSrr = 2314,
- SUBR_F32m = 2315,
- SUBR_F64m = 2316,
- SUBR_FI16m = 2317,
- SUBR_FI32m = 2318,
- SUBR_FPrST0 = 2319,
- SUBR_FST0r = 2320,
- SUBR_Fp32m = 2321,
- SUBR_Fp64m = 2322,
- SUBR_Fp64m32 = 2323,
- SUBR_Fp80m32 = 2324,
- SUBR_Fp80m64 = 2325,
- SUBR_FpI16m32 = 2326,
- SUBR_FpI16m64 = 2327,
- SUBR_FpI16m80 = 2328,
- SUBR_FpI32m32 = 2329,
- SUBR_FpI32m64 = 2330,
- SUBR_FpI32m80 = 2331,
- SUBR_FrST0 = 2332,
- SUBSDrm = 2333,
- SUBSDrm_Int = 2334,
- SUBSDrr = 2335,
- SUBSDrr_Int = 2336,
- SUBSSrm = 2337,
- SUBSSrm_Int = 2338,
- SUBSSrr = 2339,
- SUBSSrr_Int = 2340,
- SUB_F32m = 2341,
- SUB_F64m = 2342,
- SUB_FI16m = 2343,
- SUB_FI32m = 2344,
- SUB_FPrST0 = 2345,
- SUB_FST0r = 2346,
- SUB_Fp32 = 2347,
- SUB_Fp32m = 2348,
- SUB_Fp64 = 2349,
- SUB_Fp64m = 2350,
- SUB_Fp64m32 = 2351,
- SUB_Fp80 = 2352,
- SUB_Fp80m32 = 2353,
- SUB_Fp80m64 = 2354,
- SUB_FpI16m32 = 2355,
- SUB_FpI16m64 = 2356,
- SUB_FpI16m80 = 2357,
- SUB_FpI32m32 = 2358,
- SUB_FpI32m64 = 2359,
- SUB_FpI32m80 = 2360,
- SUB_FrST0 = 2361,
- SWPGS = 2362,
- SYSCALL = 2363,
- SYSENTER = 2364,
- SYSEXIT = 2365,
- SYSEXIT64 = 2366,
- SYSRET = 2367,
- TAILJMPd = 2368,
- TAILJMPm = 2369,
- TAILJMPr = 2370,
- TAILJMPr64 = 2371,
- TCRETURNdi = 2372,
- TCRETURNdi64 = 2373,
- TCRETURNri = 2374,
- TCRETURNri64 = 2375,
- TEST16i16 = 2376,
- TEST16mi = 2377,
- TEST16ri = 2378,
- TEST16rm = 2379,
- TEST16rr = 2380,
- TEST32i32 = 2381,
- TEST32mi = 2382,
- TEST32ri = 2383,
- TEST32rm = 2384,
- TEST32rr = 2385,
- TEST64i32 = 2386,
- TEST64mi32 = 2387,
- TEST64ri32 = 2388,
- TEST64rm = 2389,
- TEST64rr = 2390,
- TEST8i8 = 2391,
- TEST8mi = 2392,
- TEST8ri = 2393,
- TEST8rm = 2394,
- TEST8rr = 2395,
- TLS_addr32 = 2396,
- TLS_addr64 = 2397,
- TRAP = 2398,
- TST_F = 2399,
- TST_Fp32 = 2400,
- TST_Fp64 = 2401,
- TST_Fp80 = 2402,
- UCOMISDrm = 2403,
- UCOMISDrr = 2404,
- UCOMISSrm = 2405,
- UCOMISSrr = 2406,
- UCOM_FIPr = 2407,
- UCOM_FIr = 2408,
- UCOM_FPPr = 2409,
- UCOM_FPr = 2410,
- UCOM_FpIr32 = 2411,
- UCOM_FpIr64 = 2412,
- UCOM_FpIr80 = 2413,
- UCOM_Fpr32 = 2414,
- UCOM_Fpr64 = 2415,
- UCOM_Fpr80 = 2416,
- UCOM_Fr = 2417,
- UNPCKHPDrm = 2418,
- UNPCKHPDrr = 2419,
- UNPCKHPSrm = 2420,
- UNPCKHPSrr = 2421,
- UNPCKLPDrm = 2422,
- UNPCKLPDrr = 2423,
- UNPCKLPSrm = 2424,
- UNPCKLPSrr = 2425,
- VASTART_SAVE_XMM_REGS = 2426,
- VERRm = 2427,
- VERRr = 2428,
- VERWm = 2429,
- VERWr = 2430,
- VMCALL = 2431,
- VMCLEARm = 2432,
- VMLAUNCH = 2433,
- VMPTRLDm = 2434,
- VMPTRSTm = 2435,
- VMREAD32rm = 2436,
- VMREAD32rr = 2437,
- VMREAD64rm = 2438,
- VMREAD64rr = 2439,
- VMRESUME = 2440,
- VMWRITE32rm = 2441,
- VMWRITE32rr = 2442,
- VMWRITE64rm = 2443,
- VMWRITE64rr = 2444,
- VMXOFF = 2445,
- VMXON = 2446,
- V_SET0 = 2447,
- V_SETALLONES = 2448,
- WAIT = 2449,
- WBINVD = 2450,
- WINCALL64m = 2451,
- WINCALL64pcrel32 = 2452,
- WINCALL64r = 2453,
- WRMSR = 2454,
- XADD16rm = 2455,
- XADD16rr = 2456,
- XADD32rm = 2457,
- XADD32rr = 2458,
- XADD64rm = 2459,
- XADD64rr = 2460,
- XADD8rm = 2461,
- XADD8rr = 2462,
- XCHG16ar = 2463,
- XCHG16rm = 2464,
- XCHG16rr = 2465,
- XCHG32ar = 2466,
- XCHG32rm = 2467,
- XCHG32rr = 2468,
- XCHG64ar = 2469,
- XCHG64rm = 2470,
- XCHG64rr = 2471,
- XCHG8rm = 2472,
- XCHG8rr = 2473,
- XCH_F = 2474,
- XLAT = 2475,
- XOR16i16 = 2476,
- XOR16mi = 2477,
- XOR16mi8 = 2478,
- XOR16mr = 2479,
- XOR16ri = 2480,
- XOR16ri8 = 2481,
- XOR16rm = 2482,
- XOR16rr = 2483,
- XOR16rr_REV = 2484,
- XOR32i32 = 2485,
- XOR32mi = 2486,
- XOR32mi8 = 2487,
- XOR32mr = 2488,
- XOR32ri = 2489,
- XOR32ri8 = 2490,
- XOR32rm = 2491,
- XOR32rr = 2492,
- XOR32rr_REV = 2493,
- XOR64i32 = 2494,
- XOR64mi32 = 2495,
- XOR64mi8 = 2496,
- XOR64mr = 2497,
- XOR64ri32 = 2498,
- XOR64ri8 = 2499,
- XOR64rm = 2500,
- XOR64rr = 2501,
- XOR64rr_REV = 2502,
- XOR8i8 = 2503,
- XOR8mi = 2504,
- XOR8mr = 2505,
- XOR8ri = 2506,
- XOR8rm = 2507,
- XOR8rr = 2508,
- XOR8rr_REV = 2509,
- XORPDrm = 2510,
- XORPDrr = 2511,
- XORPSrm = 2512,
- XORPSrr = 2513,
- INSTRUCTION_LIST_END = 2514
+ DEBUG_VALUE = 11,
+ ABS_F = 12,
+ ABS_Fp32 = 13,
+ ABS_Fp64 = 14,
+ ABS_Fp80 = 15,
+ ADC16i16 = 16,
+ ADC16mi = 17,
+ ADC16mi8 = 18,
+ ADC16mr = 19,
+ ADC16ri = 20,
+ ADC16ri8 = 21,
+ ADC16rm = 22,
+ ADC16rr = 23,
+ ADC16rr_REV = 24,
+ ADC32i32 = 25,
+ ADC32mi = 26,
+ ADC32mi8 = 27,
+ ADC32mr = 28,
+ ADC32ri = 29,
+ ADC32ri8 = 30,
+ ADC32rm = 31,
+ ADC32rr = 32,
+ ADC32rr_REV = 33,
+ ADC64i32 = 34,
+ ADC64mi32 = 35,
+ ADC64mi8 = 36,
+ ADC64mr = 37,
+ ADC64ri32 = 38,
+ ADC64ri8 = 39,
+ ADC64rm = 40,
+ ADC64rr = 41,
+ ADC64rr_REV = 42,
+ ADC8i8 = 43,
+ ADC8mi = 44,
+ ADC8mr = 45,
+ ADC8ri = 46,
+ ADC8rm = 47,
+ ADC8rr = 48,
+ ADC8rr_REV = 49,
+ ADD16i16 = 50,
+ ADD16mi = 51,
+ ADD16mi8 = 52,
+ ADD16mr = 53,
+ ADD16mrmrr = 54,
+ ADD16ri = 55,
+ ADD16ri8 = 56,
+ ADD16rm = 57,
+ ADD16rr = 58,
+ ADD32i32 = 59,
+ ADD32mi = 60,
+ ADD32mi8 = 61,
+ ADD32mr = 62,
+ ADD32mrmrr = 63,
+ ADD32ri = 64,
+ ADD32ri8 = 65,
+ ADD32rm = 66,
+ ADD32rr = 67,
+ ADD64i32 = 68,
+ ADD64mi32 = 69,
+ ADD64mi8 = 70,
+ ADD64mr = 71,
+ ADD64mrmrr = 72,
+ ADD64ri32 = 73,
+ ADD64ri8 = 74,
+ ADD64rm = 75,
+ ADD64rr = 76,
+ ADD8i8 = 77,
+ ADD8mi = 78,
+ ADD8mr = 79,
+ ADD8mrmrr = 80,
+ ADD8ri = 81,
+ ADD8rm = 82,
+ ADD8rr = 83,
+ ADDPDrm = 84,
+ ADDPDrr = 85,
+ ADDPSrm = 86,
+ ADDPSrr = 87,
+ ADDSDrm = 88,
+ ADDSDrm_Int = 89,
+ ADDSDrr = 90,
+ ADDSDrr_Int = 91,
+ ADDSSrm = 92,
+ ADDSSrm_Int = 93,
+ ADDSSrr = 94,
+ ADDSSrr_Int = 95,
+ ADDSUBPDrm = 96,
+ ADDSUBPDrr = 97,
+ ADDSUBPSrm = 98,
+ ADDSUBPSrr = 99,
+ ADD_F32m = 100,
+ ADD_F64m = 101,
+ ADD_FI16m = 102,
+ ADD_FI32m = 103,
+ ADD_FPrST0 = 104,
+ ADD_FST0r = 105,
+ ADD_Fp32 = 106,
+ ADD_Fp32m = 107,
+ ADD_Fp64 = 108,
+ ADD_Fp64m = 109,
+ ADD_Fp64m32 = 110,
+ ADD_Fp80 = 111,
+ ADD_Fp80m32 = 112,
+ ADD_Fp80m64 = 113,
+ ADD_FpI16m32 = 114,
+ ADD_FpI16m64 = 115,
+ ADD_FpI16m80 = 116,
+ ADD_FpI32m32 = 117,
+ ADD_FpI32m64 = 118,
+ ADD_FpI32m80 = 119,
+ ADD_FrST0 = 120,
+ ADJCALLSTACKDOWN32 = 121,
+ ADJCALLSTACKDOWN64 = 122,
+ ADJCALLSTACKUP32 = 123,
+ ADJCALLSTACKUP64 = 124,
+ AND16i16 = 125,
+ AND16mi = 126,
+ AND16mi8 = 127,
+ AND16mr = 128,
+ AND16ri = 129,
+ AND16ri8 = 130,
+ AND16rm = 131,
+ AND16rr = 132,
+ AND16rr_REV = 133,
+ AND32i32 = 134,
+ AND32mi = 135,
+ AND32mi8 = 136,
+ AND32mr = 137,
+ AND32ri = 138,
+ AND32ri8 = 139,
+ AND32rm = 140,
+ AND32rr = 141,
+ AND32rr_REV = 142,
+ AND64i32 = 143,
+ AND64mi32 = 144,
+ AND64mi8 = 145,
+ AND64mr = 146,
+ AND64ri32 = 147,
+ AND64ri8 = 148,
+ AND64rm = 149,
+ AND64rr = 150,
+ AND64rr_REV = 151,
+ AND8i8 = 152,
+ AND8mi = 153,
+ AND8mr = 154,
+ AND8ri = 155,
+ AND8rm = 156,
+ AND8rr = 157,
+ AND8rr_REV = 158,
+ ANDNPDrm = 159,
+ ANDNPDrr = 160,
+ ANDNPSrm = 161,
+ ANDNPSrr = 162,
+ ANDPDrm = 163,
+ ANDPDrr = 164,
+ ANDPSrm = 165,
+ ANDPSrr = 166,
+ ATOMADD6432 = 167,
+ ATOMAND16 = 168,
+ ATOMAND32 = 169,
+ ATOMAND64 = 170,
+ ATOMAND6432 = 171,
+ ATOMAND8 = 172,
+ ATOMMAX16 = 173,
+ ATOMMAX32 = 174,
+ ATOMMAX64 = 175,
+ ATOMMIN16 = 176,
+ ATOMMIN32 = 177,
+ ATOMMIN64 = 178,
+ ATOMNAND16 = 179,
+ ATOMNAND32 = 180,
+ ATOMNAND64 = 181,
+ ATOMNAND6432 = 182,
+ ATOMNAND8 = 183,
+ ATOMOR16 = 184,
+ ATOMOR32 = 185,
+ ATOMOR64 = 186,
+ ATOMOR6432 = 187,
+ ATOMOR8 = 188,
+ ATOMSUB6432 = 189,
+ ATOMSWAP6432 = 190,
+ ATOMUMAX16 = 191,
+ ATOMUMAX32 = 192,
+ ATOMUMAX64 = 193,
+ ATOMUMIN16 = 194,
+ ATOMUMIN32 = 195,
+ ATOMUMIN64 = 196,
+ ATOMXOR16 = 197,
+ ATOMXOR32 = 198,
+ ATOMXOR64 = 199,
+ ATOMXOR6432 = 200,
+ ATOMXOR8 = 201,
+ BLENDPDrmi = 202,
+ BLENDPDrri = 203,
+ BLENDPSrmi = 204,
+ BLENDPSrri = 205,
+ BLENDVPDrm0 = 206,
+ BLENDVPDrr0 = 207,
+ BLENDVPSrm0 = 208,
+ BLENDVPSrr0 = 209,
+ BSF16rm = 210,
+ BSF16rr = 211,
+ BSF32rm = 212,
+ BSF32rr = 213,
+ BSF64rm = 214,
+ BSF64rr = 215,
+ BSR16rm = 216,
+ BSR16rr = 217,
+ BSR32rm = 218,
+ BSR32rr = 219,
+ BSR64rm = 220,
+ BSR64rr = 221,
+ BSWAP32r = 222,
+ BSWAP64r = 223,
+ BT16mi8 = 224,
+ BT16mr = 225,
+ BT16ri8 = 226,
+ BT16rr = 227,
+ BT32mi8 = 228,
+ BT32mr = 229,
+ BT32ri8 = 230,
+ BT32rr = 231,
+ BT64mi8 = 232,
+ BT64mr = 233,
+ BT64ri8 = 234,
+ BT64rr = 235,
+ BTC16mi8 = 236,
+ BTC16mr = 237,
+ BTC16ri8 = 238,
+ BTC16rr = 239,
+ BTC32mi8 = 240,
+ BTC32mr = 241,
+ BTC32ri8 = 242,
+ BTC32rr = 243,
+ BTC64mi8 = 244,
+ BTC64mr = 245,
+ BTC64ri8 = 246,
+ BTC64rr = 247,
+ BTR16mi8 = 248,
+ BTR16mr = 249,
+ BTR16ri8 = 250,
+ BTR16rr = 251,
+ BTR32mi8 = 252,
+ BTR32mr = 253,
+ BTR32ri8 = 254,
+ BTR32rr = 255,
+ BTR64mi8 = 256,
+ BTR64mr = 257,
+ BTR64ri8 = 258,
+ BTR64rr = 259,
+ BTS16mi8 = 260,
+ BTS16mr = 261,
+ BTS16ri8 = 262,
+ BTS16rr = 263,
+ BTS32mi8 = 264,
+ BTS32mr = 265,
+ BTS32ri8 = 266,
+ BTS32rr = 267,
+ BTS64mi8 = 268,
+ BTS64mr = 269,
+ BTS64ri8 = 270,
+ BTS64rr = 271,
+ CALL32m = 272,
+ CALL32r = 273,
+ CALL64m = 274,
+ CALL64pcrel32 = 275,
+ CALL64r = 276,
+ CALLpcrel32 = 277,
+ CBW = 278,
+ CDQ = 279,
+ CDQE = 280,
+ CHS_F = 281,
+ CHS_Fp32 = 282,
+ CHS_Fp64 = 283,
+ CHS_Fp80 = 284,
+ CLC = 285,
+ CLD = 286,
+ CLFLUSH = 287,
+ CLI = 288,
+ CLTS = 289,
+ CMC = 290,
+ CMOVA16rm = 291,
+ CMOVA16rr = 292,
+ CMOVA32rm = 293,
+ CMOVA32rr = 294,
+ CMOVA64rm = 295,
+ CMOVA64rr = 296,
+ CMOVAE16rm = 297,
+ CMOVAE16rr = 298,
+ CMOVAE32rm = 299,
+ CMOVAE32rr = 300,
+ CMOVAE64rm = 301,
+ CMOVAE64rr = 302,
+ CMOVB16rm = 303,
+ CMOVB16rr = 304,
+ CMOVB32rm = 305,
+ CMOVB32rr = 306,
+ CMOVB64rm = 307,
+ CMOVB64rr = 308,
+ CMOVBE16rm = 309,
+ CMOVBE16rr = 310,
+ CMOVBE32rm = 311,
+ CMOVBE32rr = 312,
+ CMOVBE64rm = 313,
+ CMOVBE64rr = 314,
+ CMOVBE_F = 315,
+ CMOVBE_Fp32 = 316,
+ CMOVBE_Fp64 = 317,
+ CMOVBE_Fp80 = 318,
+ CMOVB_F = 319,
+ CMOVB_Fp32 = 320,
+ CMOVB_Fp64 = 321,
+ CMOVB_Fp80 = 322,
+ CMOVE16rm = 323,
+ CMOVE16rr = 324,
+ CMOVE32rm = 325,
+ CMOVE32rr = 326,
+ CMOVE64rm = 327,
+ CMOVE64rr = 328,
+ CMOVE_F = 329,
+ CMOVE_Fp32 = 330,
+ CMOVE_Fp64 = 331,
+ CMOVE_Fp80 = 332,
+ CMOVG16rm = 333,
+ CMOVG16rr = 334,
+ CMOVG32rm = 335,
+ CMOVG32rr = 336,
+ CMOVG64rm = 337,
+ CMOVG64rr = 338,
+ CMOVGE16rm = 339,
+ CMOVGE16rr = 340,
+ CMOVGE32rm = 341,
+ CMOVGE32rr = 342,
+ CMOVGE64rm = 343,
+ CMOVGE64rr = 344,
+ CMOVL16rm = 345,
+ CMOVL16rr = 346,
+ CMOVL32rm = 347,
+ CMOVL32rr = 348,
+ CMOVL64rm = 349,
+ CMOVL64rr = 350,
+ CMOVLE16rm = 351,
+ CMOVLE16rr = 352,
+ CMOVLE32rm = 353,
+ CMOVLE32rr = 354,
+ CMOVLE64rm = 355,
+ CMOVLE64rr = 356,
+ CMOVNBE_F = 357,
+ CMOVNBE_Fp32 = 358,
+ CMOVNBE_Fp64 = 359,
+ CMOVNBE_Fp80 = 360,
+ CMOVNB_F = 361,
+ CMOVNB_Fp32 = 362,
+ CMOVNB_Fp64 = 363,
+ CMOVNB_Fp80 = 364,
+ CMOVNE16rm = 365,
+ CMOVNE16rr = 366,
+ CMOVNE32rm = 367,
+ CMOVNE32rr = 368,
+ CMOVNE64rm = 369,
+ CMOVNE64rr = 370,
+ CMOVNE_F = 371,
+ CMOVNE_Fp32 = 372,
+ CMOVNE_Fp64 = 373,
+ CMOVNE_Fp80 = 374,
+ CMOVNO16rm = 375,
+ CMOVNO16rr = 376,
+ CMOVNO32rm = 377,
+ CMOVNO32rr = 378,
+ CMOVNO64rm = 379,
+ CMOVNO64rr = 380,
+ CMOVNP16rm = 381,
+ CMOVNP16rr = 382,
+ CMOVNP32rm = 383,
+ CMOVNP32rr = 384,
+ CMOVNP64rm = 385,
+ CMOVNP64rr = 386,
+ CMOVNP_F = 387,
+ CMOVNP_Fp32 = 388,
+ CMOVNP_Fp64 = 389,
+ CMOVNP_Fp80 = 390,
+ CMOVNS16rm = 391,
+ CMOVNS16rr = 392,
+ CMOVNS32rm = 393,
+ CMOVNS32rr = 394,
+ CMOVNS64rm = 395,
+ CMOVNS64rr = 396,
+ CMOVO16rm = 397,
+ CMOVO16rr = 398,
+ CMOVO32rm = 399,
+ CMOVO32rr = 400,
+ CMOVO64rm = 401,
+ CMOVO64rr = 402,
+ CMOVP16rm = 403,
+ CMOVP16rr = 404,
+ CMOVP32rm = 405,
+ CMOVP32rr = 406,
+ CMOVP64rm = 407,
+ CMOVP64rr = 408,
+ CMOVP_F = 409,
+ CMOVP_Fp32 = 410,
+ CMOVP_Fp64 = 411,
+ CMOVP_Fp80 = 412,
+ CMOVS16rm = 413,
+ CMOVS16rr = 414,
+ CMOVS32rm = 415,
+ CMOVS32rr = 416,
+ CMOVS64rm = 417,
+ CMOVS64rr = 418,
+ CMOV_FR32 = 419,
+ CMOV_FR64 = 420,
+ CMOV_GR8 = 421,
+ CMOV_V1I64 = 422,
+ CMOV_V2F64 = 423,
+ CMOV_V2I64 = 424,
+ CMOV_V4F32 = 425,
+ CMP16i16 = 426,
+ CMP16mi = 427,
+ CMP16mi8 = 428,
+ CMP16mr = 429,
+ CMP16mrmrr = 430,
+ CMP16ri = 431,
+ CMP16ri8 = 432,
+ CMP16rm = 433,
+ CMP16rr = 434,
+ CMP32i32 = 435,
+ CMP32mi = 436,
+ CMP32mi8 = 437,
+ CMP32mr = 438,
+ CMP32mrmrr = 439,
+ CMP32ri = 440,
+ CMP32ri8 = 441,
+ CMP32rm = 442,
+ CMP32rr = 443,
+ CMP64i32 = 444,
+ CMP64mi32 = 445,
+ CMP64mi8 = 446,
+ CMP64mr = 447,
+ CMP64mrmrr = 448,
+ CMP64ri32 = 449,
+ CMP64ri8 = 450,
+ CMP64rm = 451,
+ CMP64rr = 452,
+ CMP8i8 = 453,
+ CMP8mi = 454,
+ CMP8mr = 455,
+ CMP8mrmrr = 456,
+ CMP8ri = 457,
+ CMP8rm = 458,
+ CMP8rr = 459,
+ CMPPDrmi = 460,
+ CMPPDrri = 461,
+ CMPPSrmi = 462,
+ CMPPSrri = 463,
+ CMPS16 = 464,
+ CMPS32 = 465,
+ CMPS64 = 466,
+ CMPS8 = 467,
+ CMPSDrm = 468,
+ CMPSDrr = 469,
+ CMPSSrm = 470,
+ CMPSSrr = 471,
+ CMPXCHG16B = 472,
+ CMPXCHG16rm = 473,
+ CMPXCHG16rr = 474,
+ CMPXCHG32rm = 475,
+ CMPXCHG32rr = 476,
+ CMPXCHG64rm = 477,
+ CMPXCHG64rr = 478,
+ CMPXCHG8B = 479,
+ CMPXCHG8rm = 480,
+ CMPXCHG8rr = 481,
+ COMISDrm = 482,
+ COMISDrr = 483,
+ COMISSrm = 484,
+ COMISSrr = 485,
+ COMP_FST0r = 486,
+ COM_FIPr = 487,
+ COM_FIr = 488,
+ COM_FST0r = 489,
+ COS_F = 490,
+ COS_Fp32 = 491,
+ COS_Fp64 = 492,
+ COS_Fp80 = 493,
+ CPUID = 494,
+ CQO = 495,
+ CRC32m16 = 496,
+ CRC32m32 = 497,
+ CRC32m8 = 498,
+ CRC32r16 = 499,
+ CRC32r32 = 500,
+ CRC32r8 = 501,
+ CRC64m64 = 502,
+ CRC64r64 = 503,
+ CVTDQ2PDrm = 504,
+ CVTDQ2PDrr = 505,
+ CVTDQ2PSrm = 506,
+ CVTDQ2PSrr = 507,
+ CVTPD2DQrm = 508,
+ CVTPD2DQrr = 509,
+ CVTPD2PSrm = 510,
+ CVTPD2PSrr = 511,
+ CVTPS2DQrm = 512,
+ CVTPS2DQrr = 513,
+ CVTPS2PDrm = 514,
+ CVTPS2PDrr = 515,
+ CVTSD2SI64rm = 516,
+ CVTSD2SI64rr = 517,
+ CVTSD2SSrm = 518,
+ CVTSD2SSrr = 519,
+ CVTSI2SD64rm = 520,
+ CVTSI2SD64rr = 521,
+ CVTSI2SDrm = 522,
+ CVTSI2SDrr = 523,
+ CVTSI2SS64rm = 524,
+ CVTSI2SS64rr = 525,
+ CVTSI2SSrm = 526,
+ CVTSI2SSrr = 527,
+ CVTSS2SDrm = 528,
+ CVTSS2SDrr = 529,
+ CVTSS2SI64rm = 530,
+ CVTSS2SI64rr = 531,
+ CVTSS2SIrm = 532,
+ CVTSS2SIrr = 533,
+ CVTTPS2DQrm = 534,
+ CVTTPS2DQrr = 535,
+ CVTTSD2SI64rm = 536,
+ CVTTSD2SI64rr = 537,
+ CVTTSD2SIrm = 538,
+ CVTTSD2SIrr = 539,
+ CVTTSS2SI64rm = 540,
+ CVTTSS2SI64rr = 541,
+ CVTTSS2SIrm = 542,
+ CVTTSS2SIrr = 543,
+ CWD = 544,
+ CWDE = 545,
+ DEC16m = 546,
+ DEC16r = 547,
+ DEC32m = 548,
+ DEC32r = 549,
+ DEC64_16m = 550,
+ DEC64_16r = 551,
+ DEC64_32m = 552,
+ DEC64_32r = 553,
+ DEC64m = 554,
+ DEC64r = 555,
+ DEC8m = 556,
+ DEC8r = 557,
+ DIV16m = 558,
+ DIV16r = 559,
+ DIV32m = 560,
+ DIV32r = 561,
+ DIV64m = 562,
+ DIV64r = 563,
+ DIV8m = 564,
+ DIV8r = 565,
+ DIVPDrm = 566,
+ DIVPDrr = 567,
+ DIVPSrm = 568,
+ DIVPSrr = 569,
+ DIVR_F32m = 570,
+ DIVR_F64m = 571,
+ DIVR_FI16m = 572,
+ DIVR_FI32m = 573,
+ DIVR_FPrST0 = 574,
+ DIVR_FST0r = 575,
+ DIVR_Fp32m = 576,
+ DIVR_Fp64m = 577,
+ DIVR_Fp64m32 = 578,
+ DIVR_Fp80m32 = 579,
+ DIVR_Fp80m64 = 580,
+ DIVR_FpI16m32 = 581,
+ DIVR_FpI16m64 = 582,
+ DIVR_FpI16m80 = 583,
+ DIVR_FpI32m32 = 584,
+ DIVR_FpI32m64 = 585,
+ DIVR_FpI32m80 = 586,
+ DIVR_FrST0 = 587,
+ DIVSDrm = 588,
+ DIVSDrm_Int = 589,
+ DIVSDrr = 590,
+ DIVSDrr_Int = 591,
+ DIVSSrm = 592,
+ DIVSSrm_Int = 593,
+ DIVSSrr = 594,
+ DIVSSrr_Int = 595,
+ DIV_F32m = 596,
+ DIV_F64m = 597,
+ DIV_FI16m = 598,
+ DIV_FI32m = 599,
+ DIV_FPrST0 = 600,
+ DIV_FST0r = 601,
+ DIV_Fp32 = 602,
+ DIV_Fp32m = 603,
+ DIV_Fp64 = 604,
+ DIV_Fp64m = 605,
+ DIV_Fp64m32 = 606,
+ DIV_Fp80 = 607,
+ DIV_Fp80m32 = 608,
+ DIV_Fp80m64 = 609,
+ DIV_FpI16m32 = 610,
+ DIV_FpI16m64 = 611,
+ DIV_FpI16m80 = 612,
+ DIV_FpI32m32 = 613,
+ DIV_FpI32m64 = 614,
+ DIV_FpI32m80 = 615,
+ DIV_FrST0 = 616,
+ DPPDrmi = 617,
+ DPPDrri = 618,
+ DPPSrmi = 619,
+ DPPSrri = 620,
+ EH_RETURN = 621,
+ EH_RETURN64 = 622,
+ ENTER = 623,
+ EXTRACTPSmr = 624,
+ EXTRACTPSrr = 625,
+ F2XM1 = 626,
+ FARCALL16i = 627,
+ FARCALL16m = 628,
+ FARCALL32i = 629,
+ FARCALL32m = 630,
+ FARCALL64 = 631,
+ FARJMP16i = 632,
+ FARJMP16m = 633,
+ FARJMP32i = 634,
+ FARJMP32m = 635,
+ FARJMP64 = 636,
+ FBLDm = 637,
+ FBSTPm = 638,
+ FCOM32m = 639,
+ FCOM64m = 640,
+ FCOMP32m = 641,
+ FCOMP64m = 642,
+ FCOMPP = 643,
+ FDECSTP = 644,
+ FFREE = 645,
+ FICOM16m = 646,
+ FICOM32m = 647,
+ FICOMP16m = 648,
+ FICOMP32m = 649,
+ FINCSTP = 650,
+ FISTTP32m = 651,
+ FLDCW16m = 652,
+ FLDENVm = 653,
+ FLDL2E = 654,
+ FLDL2T = 655,
+ FLDLG2 = 656,
+ FLDLN2 = 657,
+ FLDPI = 658,
+ FNCLEX = 659,
+ FNINIT = 660,
+ FNOP = 661,
+ FNSTCW16m = 662,
+ FNSTSW8r = 663,
+ FNSTSWm = 664,
+ FP32_TO_INT16_IN_MEM = 665,
+ FP32_TO_INT32_IN_MEM = 666,
+ FP32_TO_INT64_IN_MEM = 667,
+ FP64_TO_INT16_IN_MEM = 668,
+ FP64_TO_INT32_IN_MEM = 669,
+ FP64_TO_INT64_IN_MEM = 670,
+ FP80_TO_INT16_IN_MEM = 671,
+ FP80_TO_INT32_IN_MEM = 672,
+ FP80_TO_INT64_IN_MEM = 673,
+ FPATAN = 674,
+ FPREM = 675,
+ FPREM1 = 676,
+ FPTAN = 677,
+ FP_REG_KILL = 678,
+ FRNDINT = 679,
+ FRSTORm = 680,
+ FSAVEm = 681,
+ FSCALE = 682,
+ FSINCOS = 683,
+ FSTENVm = 684,
+ FS_MOV32rm = 685,
+ FXAM = 686,
+ FXRSTOR = 687,
+ FXSAVE = 688,
+ FXTRACT = 689,
+ FYL2X = 690,
+ FYL2XP1 = 691,
+ FpGET_ST0_32 = 692,
+ FpGET_ST0_64 = 693,
+ FpGET_ST0_80 = 694,
+ FpGET_ST1_32 = 695,
+ FpGET_ST1_64 = 696,
+ FpGET_ST1_80 = 697,
+ FpSET_ST0_32 = 698,
+ FpSET_ST0_64 = 699,
+ FpSET_ST0_80 = 700,
+ FpSET_ST1_32 = 701,
+ FpSET_ST1_64 = 702,
+ FpSET_ST1_80 = 703,
+ FsANDNPDrm = 704,
+ FsANDNPDrr = 705,
+ FsANDNPSrm = 706,
+ FsANDNPSrr = 707,
+ FsANDPDrm = 708,
+ FsANDPDrr = 709,
+ FsANDPSrm = 710,
+ FsANDPSrr = 711,
+ FsFLD0SD = 712,
+ FsFLD0SS = 713,
+ FsMOVAPDrm = 714,
+ FsMOVAPDrr = 715,
+ FsMOVAPSrm = 716,
+ FsMOVAPSrr = 717,
+ FsORPDrm = 718,
+ FsORPDrr = 719,
+ FsORPSrm = 720,
+ FsORPSrr = 721,
+ FsXORPDrm = 722,
+ FsXORPDrr = 723,
+ FsXORPSrm = 724,
+ FsXORPSrr = 725,
+ GS_MOV32rm = 726,
+ HADDPDrm = 727,
+ HADDPDrr = 728,
+ HADDPSrm = 729,
+ HADDPSrr = 730,
+ HLT = 731,
+ HSUBPDrm = 732,
+ HSUBPDrr = 733,
+ HSUBPSrm = 734,
+ HSUBPSrr = 735,
+ IDIV16m = 736,
+ IDIV16r = 737,
+ IDIV32m = 738,
+ IDIV32r = 739,
+ IDIV64m = 740,
+ IDIV64r = 741,
+ IDIV8m = 742,
+ IDIV8r = 743,
+ ILD_F16m = 744,
+ ILD_F32m = 745,
+ ILD_F64m = 746,
+ ILD_Fp16m32 = 747,
+ ILD_Fp16m64 = 748,
+ ILD_Fp16m80 = 749,
+ ILD_Fp32m32 = 750,
+ ILD_Fp32m64 = 751,
+ ILD_Fp32m80 = 752,
+ ILD_Fp64m32 = 753,
+ ILD_Fp64m64 = 754,
+ ILD_Fp64m80 = 755,
+ IMUL16m = 756,
+ IMUL16r = 757,
+ IMUL16rm = 758,
+ IMUL16rmi = 759,
+ IMUL16rmi8 = 760,
+ IMUL16rr = 761,
+ IMUL16rri = 762,
+ IMUL16rri8 = 763,
+ IMUL32m = 764,
+ IMUL32r = 765,
+ IMUL32rm = 766,
+ IMUL32rmi = 767,
+ IMUL32rmi8 = 768,
+ IMUL32rr = 769,
+ IMUL32rri = 770,
+ IMUL32rri8 = 771,
+ IMUL64m = 772,
+ IMUL64r = 773,
+ IMUL64rm = 774,
+ IMUL64rmi32 = 775,
+ IMUL64rmi8 = 776,
+ IMUL64rr = 777,
+ IMUL64rri32 = 778,
+ IMUL64rri8 = 779,
+ IMUL8m = 780,
+ IMUL8r = 781,
+ IN16 = 782,
+ IN16ri = 783,
+ IN16rr = 784,
+ IN32 = 785,
+ IN32ri = 786,
+ IN32rr = 787,
+ IN8 = 788,
+ IN8ri = 789,
+ IN8rr = 790,
+ INC16m = 791,
+ INC16r = 792,
+ INC32m = 793,
+ INC32r = 794,
+ INC64_16m = 795,
+ INC64_16r = 796,
+ INC64_32m = 797,
+ INC64_32r = 798,
+ INC64m = 799,
+ INC64r = 800,
+ INC8m = 801,
+ INC8r = 802,
+ INSERTPSrm = 803,
+ INSERTPSrr = 804,
+ INT = 805,
+ INT3 = 806,
+ INVD = 807,
+ INVEPT = 808,
+ INVLPG = 809,
+ INVVPID = 810,
+ IRET16 = 811,
+ IRET32 = 812,
+ IRET64 = 813,
+ ISTT_FP16m = 814,
+ ISTT_FP32m = 815,
+ ISTT_FP64m = 816,
+ ISTT_Fp16m32 = 817,
+ ISTT_Fp16m64 = 818,
+ ISTT_Fp16m80 = 819,
+ ISTT_Fp32m32 = 820,
+ ISTT_Fp32m64 = 821,
+ ISTT_Fp32m80 = 822,
+ ISTT_Fp64m32 = 823,
+ ISTT_Fp64m64 = 824,
+ ISTT_Fp64m80 = 825,
+ IST_F16m = 826,
+ IST_F32m = 827,
+ IST_FP16m = 828,
+ IST_FP32m = 829,
+ IST_FP64m = 830,
+ IST_Fp16m32 = 831,
+ IST_Fp16m64 = 832,
+ IST_Fp16m80 = 833,
+ IST_Fp32m32 = 834,
+ IST_Fp32m64 = 835,
+ IST_Fp32m80 = 836,
+ IST_Fp64m32 = 837,
+ IST_Fp64m64 = 838,
+ IST_Fp64m80 = 839,
+ Int_CMPSDrm = 840,
+ Int_CMPSDrr = 841,
+ Int_CMPSSrm = 842,
+ Int_CMPSSrr = 843,
+ Int_COMISDrm = 844,
+ Int_COMISDrr = 845,
+ Int_COMISSrm = 846,
+ Int_COMISSrr = 847,
+ Int_CVTDQ2PDrm = 848,
+ Int_CVTDQ2PDrr = 849,
+ Int_CVTDQ2PSrm = 850,
+ Int_CVTDQ2PSrr = 851,
+ Int_CVTPD2DQrm = 852,
+ Int_CVTPD2DQrr = 853,
+ Int_CVTPD2PIrm = 854,
+ Int_CVTPD2PIrr = 855,
+ Int_CVTPD2PSrm = 856,
+ Int_CVTPD2PSrr = 857,
+ Int_CVTPI2PDrm = 858,
+ Int_CVTPI2PDrr = 859,
+ Int_CVTPI2PSrm = 860,
+ Int_CVTPI2PSrr = 861,
+ Int_CVTPS2DQrm = 862,
+ Int_CVTPS2DQrr = 863,
+ Int_CVTPS2PDrm = 864,
+ Int_CVTPS2PDrr = 865,
+ Int_CVTPS2PIrm = 866,
+ Int_CVTPS2PIrr = 867,
+ Int_CVTSD2SI64rm = 868,
+ Int_CVTSD2SI64rr = 869,
+ Int_CVTSD2SIrm = 870,
+ Int_CVTSD2SIrr = 871,
+ Int_CVTSD2SSrm = 872,
+ Int_CVTSD2SSrr = 873,
+ Int_CVTSI2SD64rm = 874,
+ Int_CVTSI2SD64rr = 875,
+ Int_CVTSI2SDrm = 876,
+ Int_CVTSI2SDrr = 877,
+ Int_CVTSI2SS64rm = 878,
+ Int_CVTSI2SS64rr = 879,
+ Int_CVTSI2SSrm = 880,
+ Int_CVTSI2SSrr = 881,
+ Int_CVTSS2SDrm = 882,
+ Int_CVTSS2SDrr = 883,
+ Int_CVTSS2SI64rm = 884,
+ Int_CVTSS2SI64rr = 885,
+ Int_CVTSS2SIrm = 886,
+ Int_CVTSS2SIrr = 887,
+ Int_CVTTPD2DQrm = 888,
+ Int_CVTTPD2DQrr = 889,
+ Int_CVTTPD2PIrm = 890,
+ Int_CVTTPD2PIrr = 891,
+ Int_CVTTPS2DQrm = 892,
+ Int_CVTTPS2DQrr = 893,
+ Int_CVTTPS2PIrm = 894,
+ Int_CVTTPS2PIrr = 895,
+ Int_CVTTSD2SI64rm = 896,
+ Int_CVTTSD2SI64rr = 897,
+ Int_CVTTSD2SIrm = 898,
+ Int_CVTTSD2SIrr = 899,
+ Int_CVTTSS2SI64rm = 900,
+ Int_CVTTSS2SI64rr = 901,
+ Int_CVTTSS2SIrm = 902,
+ Int_CVTTSS2SIrr = 903,
+ Int_UCOMISDrm = 904,
+ Int_UCOMISDrr = 905,
+ Int_UCOMISSrm = 906,
+ Int_UCOMISSrr = 907,
+ JA = 908,
+ JA8 = 909,
+ JAE = 910,
+ JAE8 = 911,
+ JB = 912,
+ JB8 = 913,
+ JBE = 914,
+ JBE8 = 915,
+ JCXZ8 = 916,
+ JE = 917,
+ JE8 = 918,
+ JG = 919,
+ JG8 = 920,
+ JGE = 921,
+ JGE8 = 922,
+ JL = 923,
+ JL8 = 924,
+ JLE = 925,
+ JLE8 = 926,
+ JMP = 927,
+ JMP32m = 928,
+ JMP32r = 929,
+ JMP64m = 930,
+ JMP64pcrel32 = 931,
+ JMP64r = 932,
+ JMP8 = 933,
+ JNE = 934,
+ JNE8 = 935,
+ JNO = 936,
+ JNO8 = 937,
+ JNP = 938,
+ JNP8 = 939,
+ JNS = 940,
+ JNS8 = 941,
+ JO = 942,
+ JO8 = 943,
+ JP = 944,
+ JP8 = 945,
+ JS = 946,
+ JS8 = 947,
+ LAHF = 948,
+ LAR16rm = 949,
+ LAR16rr = 950,
+ LAR32rm = 951,
+ LAR32rr = 952,
+ LAR64rm = 953,
+ LAR64rr = 954,
+ LCMPXCHG16 = 955,
+ LCMPXCHG32 = 956,
+ LCMPXCHG64 = 957,
+ LCMPXCHG8 = 958,
+ LCMPXCHG8B = 959,
+ LDDQUrm = 960,
+ LDMXCSR = 961,
+ LDS16rm = 962,
+ LDS32rm = 963,
+ LD_F0 = 964,
+ LD_F1 = 965,
+ LD_F32m = 966,
+ LD_F64m = 967,
+ LD_F80m = 968,
+ LD_Fp032 = 969,
+ LD_Fp064 = 970,
+ LD_Fp080 = 971,
+ LD_Fp132 = 972,
+ LD_Fp164 = 973,
+ LD_Fp180 = 974,
+ LD_Fp32m = 975,
+ LD_Fp32m64 = 976,
+ LD_Fp32m80 = 977,
+ LD_Fp64m = 978,
+ LD_Fp64m80 = 979,
+ LD_Fp80m = 980,
+ LD_Frr = 981,
+ LEA16r = 982,
+ LEA32r = 983,
+ LEA64_32r = 984,
+ LEA64r = 985,
+ LEAVE = 986,
+ LEAVE64 = 987,
+ LES16rm = 988,
+ LES32rm = 989,
+ LFENCE = 990,
+ LFS16rm = 991,
+ LFS32rm = 992,
+ LFS64rm = 993,
+ LGDTm = 994,
+ LGS16rm = 995,
+ LGS32rm = 996,
+ LGS64rm = 997,
+ LIDTm = 998,
+ LLDT16m = 999,
+ LLDT16r = 1000,
+ LMSW16m = 1001,
+ LMSW16r = 1002,
+ LOCK_ADD16mi = 1003,
+ LOCK_ADD16mi8 = 1004,
+ LOCK_ADD16mr = 1005,
+ LOCK_ADD32mi = 1006,
+ LOCK_ADD32mi8 = 1007,
+ LOCK_ADD32mr = 1008,
+ LOCK_ADD64mi32 = 1009,
+ LOCK_ADD64mi8 = 1010,
+ LOCK_ADD64mr = 1011,
+ LOCK_ADD8mi = 1012,
+ LOCK_ADD8mr = 1013,
+ LOCK_DEC16m = 1014,
+ LOCK_DEC32m = 1015,
+ LOCK_DEC64m = 1016,
+ LOCK_DEC8m = 1017,
+ LOCK_INC16m = 1018,
+ LOCK_INC32m = 1019,
+ LOCK_INC64m = 1020,
+ LOCK_INC8m = 1021,
+ LOCK_SUB16mi = 1022,
+ LOCK_SUB16mi8 = 1023,
+ LOCK_SUB16mr = 1024,
+ LOCK_SUB32mi = 1025,
+ LOCK_SUB32mi8 = 1026,
+ LOCK_SUB32mr = 1027,
+ LOCK_SUB64mi32 = 1028,
+ LOCK_SUB64mi8 = 1029,
+ LOCK_SUB64mr = 1030,
+ LOCK_SUB8mi = 1031,
+ LOCK_SUB8mr = 1032,
+ LODSB = 1033,
+ LODSD = 1034,
+ LODSQ = 1035,
+ LODSW = 1036,
+ LOOP = 1037,
+ LOOPE = 1038,
+ LOOPNE = 1039,
+ LRET = 1040,
+ LRETI = 1041,
+ LSL16rm = 1042,
+ LSL16rr = 1043,
+ LSL32rm = 1044,
+ LSL32rr = 1045,
+ LSL64rm = 1046,
+ LSL64rr = 1047,
+ LSS16rm = 1048,
+ LSS32rm = 1049,
+ LSS64rm = 1050,
+ LTRm = 1051,
+ LTRr = 1052,
+ LXADD16 = 1053,
+ LXADD32 = 1054,
+ LXADD64 = 1055,
+ LXADD8 = 1056,
+ MASKMOVDQU = 1057,
+ MASKMOVDQU64 = 1058,
+ MAXPDrm = 1059,
+ MAXPDrm_Int = 1060,
+ MAXPDrr = 1061,
+ MAXPDrr_Int = 1062,
+ MAXPSrm = 1063,
+ MAXPSrm_Int = 1064,
+ MAXPSrr = 1065,
+ MAXPSrr_Int = 1066,
+ MAXSDrm = 1067,
+ MAXSDrm_Int = 1068,
+ MAXSDrr = 1069,
+ MAXSDrr_Int = 1070,
+ MAXSSrm = 1071,
+ MAXSSrm_Int = 1072,
+ MAXSSrr = 1073,
+ MAXSSrr_Int = 1074,
+ MFENCE = 1075,
+ MINPDrm = 1076,
+ MINPDrm_Int = 1077,
+ MINPDrr = 1078,
+ MINPDrr_Int = 1079,
+ MINPSrm = 1080,
+ MINPSrm_Int = 1081,
+ MINPSrr = 1082,
+ MINPSrr_Int = 1083,
+ MINSDrm = 1084,
+ MINSDrm_Int = 1085,
+ MINSDrr = 1086,
+ MINSDrr_Int = 1087,
+ MINSSrm = 1088,
+ MINSSrm_Int = 1089,
+ MINSSrr = 1090,
+ MINSSrr_Int = 1091,
+ MMX_CVTPD2PIrm = 1092,
+ MMX_CVTPD2PIrr = 1093,
+ MMX_CVTPI2PDrm = 1094,
+ MMX_CVTPI2PDrr = 1095,
+ MMX_CVTPI2PSrm = 1096,
+ MMX_CVTPI2PSrr = 1097,
+ MMX_CVTPS2PIrm = 1098,
+ MMX_CVTPS2PIrr = 1099,
+ MMX_CVTTPD2PIrm = 1100,
+ MMX_CVTTPD2PIrr = 1101,
+ MMX_CVTTPS2PIrm = 1102,
+ MMX_CVTTPS2PIrr = 1103,
+ MMX_EMMS = 1104,
+ MMX_FEMMS = 1105,
+ MMX_MASKMOVQ = 1106,
+ MMX_MASKMOVQ64 = 1107,
+ MMX_MOVD64from64rr = 1108,
+ MMX_MOVD64grr = 1109,
+ MMX_MOVD64mr = 1110,
+ MMX_MOVD64rm = 1111,
+ MMX_MOVD64rr = 1112,
+ MMX_MOVD64rrv164 = 1113,
+ MMX_MOVD64to64rr = 1114,
+ MMX_MOVDQ2Qrr = 1115,
+ MMX_MOVNTQmr = 1116,
+ MMX_MOVQ2DQrr = 1117,
+ MMX_MOVQ2FR64rr = 1118,
+ MMX_MOVQ64gmr = 1119,
+ MMX_MOVQ64mr = 1120,
+ MMX_MOVQ64rm = 1121,
+ MMX_MOVQ64rr = 1122,
+ MMX_MOVZDI2PDIrm = 1123,
+ MMX_MOVZDI2PDIrr = 1124,
+ MMX_PACKSSDWrm = 1125,
+ MMX_PACKSSDWrr = 1126,
+ MMX_PACKSSWBrm = 1127,
+ MMX_PACKSSWBrr = 1128,
+ MMX_PACKUSWBrm = 1129,
+ MMX_PACKUSWBrr = 1130,
+ MMX_PADDBrm = 1131,
+ MMX_PADDBrr = 1132,
+ MMX_PADDDrm = 1133,
+ MMX_PADDDrr = 1134,
+ MMX_PADDQrm = 1135,
+ MMX_PADDQrr = 1136,
+ MMX_PADDSBrm = 1137,
+ MMX_PADDSBrr = 1138,
+ MMX_PADDSWrm = 1139,
+ MMX_PADDSWrr = 1140,
+ MMX_PADDUSBrm = 1141,
+ MMX_PADDUSBrr = 1142,
+ MMX_PADDUSWrm = 1143,
+ MMX_PADDUSWrr = 1144,
+ MMX_PADDWrm = 1145,
+ MMX_PADDWrr = 1146,
+ MMX_PANDNrm = 1147,
+ MMX_PANDNrr = 1148,
+ MMX_PANDrm = 1149,
+ MMX_PANDrr = 1150,
+ MMX_PAVGBrm = 1151,
+ MMX_PAVGBrr = 1152,
+ MMX_PAVGWrm = 1153,
+ MMX_PAVGWrr = 1154,
+ MMX_PCMPEQBrm = 1155,
+ MMX_PCMPEQBrr = 1156,
+ MMX_PCMPEQDrm = 1157,
+ MMX_PCMPEQDrr = 1158,
+ MMX_PCMPEQWrm = 1159,
+ MMX_PCMPEQWrr = 1160,
+ MMX_PCMPGTBrm = 1161,
+ MMX_PCMPGTBrr = 1162,
+ MMX_PCMPGTDrm = 1163,
+ MMX_PCMPGTDrr = 1164,
+ MMX_PCMPGTWrm = 1165,
+ MMX_PCMPGTWrr = 1166,
+ MMX_PEXTRWri = 1167,
+ MMX_PINSRWrmi = 1168,
+ MMX_PINSRWrri = 1169,
+ MMX_PMADDWDrm = 1170,
+ MMX_PMADDWDrr = 1171,
+ MMX_PMAXSWrm = 1172,
+ MMX_PMAXSWrr = 1173,
+ MMX_PMAXUBrm = 1174,
+ MMX_PMAXUBrr = 1175,
+ MMX_PMINSWrm = 1176,
+ MMX_PMINSWrr = 1177,
+ MMX_PMINUBrm = 1178,
+ MMX_PMINUBrr = 1179,
+ MMX_PMOVMSKBrr = 1180,
+ MMX_PMULHUWrm = 1181,
+ MMX_PMULHUWrr = 1182,
+ MMX_PMULHWrm = 1183,
+ MMX_PMULHWrr = 1184,
+ MMX_PMULLWrm = 1185,
+ MMX_PMULLWrr = 1186,
+ MMX_PMULUDQrm = 1187,
+ MMX_PMULUDQrr = 1188,
+ MMX_PORrm = 1189,
+ MMX_PORrr = 1190,
+ MMX_PSADBWrm = 1191,
+ MMX_PSADBWrr = 1192,
+ MMX_PSHUFWmi = 1193,
+ MMX_PSHUFWri = 1194,
+ MMX_PSLLDri = 1195,
+ MMX_PSLLDrm = 1196,
+ MMX_PSLLDrr = 1197,
+ MMX_PSLLQri = 1198,
+ MMX_PSLLQrm = 1199,
+ MMX_PSLLQrr = 1200,
+ MMX_PSLLWri = 1201,
+ MMX_PSLLWrm = 1202,
+ MMX_PSLLWrr = 1203,
+ MMX_PSRADri = 1204,
+ MMX_PSRADrm = 1205,
+ MMX_PSRADrr = 1206,
+ MMX_PSRAWri = 1207,
+ MMX_PSRAWrm = 1208,
+ MMX_PSRAWrr = 1209,
+ MMX_PSRLDri = 1210,
+ MMX_PSRLDrm = 1211,
+ MMX_PSRLDrr = 1212,
+ MMX_PSRLQri = 1213,
+ MMX_PSRLQrm = 1214,
+ MMX_PSRLQrr = 1215,
+ MMX_PSRLWri = 1216,
+ MMX_PSRLWrm = 1217,
+ MMX_PSRLWrr = 1218,
+ MMX_PSUBBrm = 1219,
+ MMX_PSUBBrr = 1220,
+ MMX_PSUBDrm = 1221,
+ MMX_PSUBDrr = 1222,
+ MMX_PSUBQrm = 1223,
+ MMX_PSUBQrr = 1224,
+ MMX_PSUBSBrm = 1225,
+ MMX_PSUBSBrr = 1226,
+ MMX_PSUBSWrm = 1227,
+ MMX_PSUBSWrr = 1228,
+ MMX_PSUBUSBrm = 1229,
+ MMX_PSUBUSBrr = 1230,
+ MMX_PSUBUSWrm = 1231,
+ MMX_PSUBUSWrr = 1232,
+ MMX_PSUBWrm = 1233,
+ MMX_PSUBWrr = 1234,
+ MMX_PUNPCKHBWrm = 1235,
+ MMX_PUNPCKHBWrr = 1236,
+ MMX_PUNPCKHDQrm = 1237,
+ MMX_PUNPCKHDQrr = 1238,
+ MMX_PUNPCKHWDrm = 1239,
+ MMX_PUNPCKHWDrr = 1240,
+ MMX_PUNPCKLBWrm = 1241,
+ MMX_PUNPCKLBWrr = 1242,
+ MMX_PUNPCKLDQrm = 1243,
+ MMX_PUNPCKLDQrr = 1244,
+ MMX_PUNPCKLWDrm = 1245,
+ MMX_PUNPCKLWDrr = 1246,
+ MMX_PXORrm = 1247,
+ MMX_PXORrr = 1248,
+ MMX_V_SET0 = 1249,
+ MMX_V_SETALLONES = 1250,
+ MONITOR = 1251,
+ MOV16ao16 = 1252,
+ MOV16mi = 1253,
+ MOV16mr = 1254,
+ MOV16ms = 1255,
+ MOV16o16a = 1256,
+ MOV16r0 = 1257,
+ MOV16ri = 1258,
+ MOV16rm = 1259,
+ MOV16rr = 1260,
+ MOV16rr_REV = 1261,
+ MOV16rs = 1262,
+ MOV16sm = 1263,
+ MOV16sr = 1264,
+ MOV32ao32 = 1265,
+ MOV32cr = 1266,
+ MOV32dr = 1267,
+ MOV32mi = 1268,
+ MOV32mr = 1269,
+ MOV32o32a = 1270,
+ MOV32r0 = 1271,
+ MOV32rc = 1272,
+ MOV32rd = 1273,
+ MOV32ri = 1274,
+ MOV32rm = 1275,
+ MOV32rr = 1276,
+ MOV32rr_REV = 1277,
+ MOV64FSrm = 1278,
+ MOV64GSrm = 1279,
+ MOV64ao64 = 1280,
+ MOV64ao8 = 1281,
+ MOV64cr = 1282,
+ MOV64dr = 1283,
+ MOV64mi32 = 1284,
+ MOV64mr = 1285,
+ MOV64ms = 1286,
+ MOV64o64a = 1287,
+ MOV64o8a = 1288,
+ MOV64r0 = 1289,
+ MOV64rc = 1290,
+ MOV64rd = 1291,
+ MOV64ri = 1292,
+ MOV64ri32 = 1293,
+ MOV64ri64i32 = 1294,
+ MOV64rm = 1295,
+ MOV64rr = 1296,
+ MOV64rr_REV = 1297,
+ MOV64rs = 1298,
+ MOV64sm = 1299,
+ MOV64sr = 1300,
+ MOV64toPQIrr = 1301,
+ MOV64toSDrm = 1302,
+ MOV64toSDrr = 1303,
+ MOV8ao8 = 1304,
+ MOV8mi = 1305,
+ MOV8mr = 1306,
+ MOV8mr_NOREX = 1307,
+ MOV8o8a = 1308,
+ MOV8r0 = 1309,
+ MOV8ri = 1310,
+ MOV8rm = 1311,
+ MOV8rm_NOREX = 1312,
+ MOV8rr = 1313,
+ MOV8rr_NOREX = 1314,
+ MOV8rr_REV = 1315,
+ MOVAPDmr = 1316,
+ MOVAPDrm = 1317,
+ MOVAPDrr = 1318,
+ MOVAPSmr = 1319,
+ MOVAPSrm = 1320,
+ MOVAPSrr = 1321,
+ MOVDDUPrm = 1322,
+ MOVDDUPrr = 1323,
+ MOVDI2PDIrm = 1324,
+ MOVDI2PDIrr = 1325,
+ MOVDI2SSrm = 1326,
+ MOVDI2SSrr = 1327,
+ MOVDQAmr = 1328,
+ MOVDQArm = 1329,
+ MOVDQArr = 1330,
+ MOVDQUmr = 1331,
+ MOVDQUmr_Int = 1332,
+ MOVDQUrm = 1333,
+ MOVDQUrm_Int = 1334,
+ MOVHLPSrr = 1335,
+ MOVHPDmr = 1336,
+ MOVHPDrm = 1337,
+ MOVHPSmr = 1338,
+ MOVHPSrm = 1339,
+ MOVLHPSrr = 1340,
+ MOVLPDmr = 1341,
+ MOVLPDrm = 1342,
+ MOVLPDrr = 1343,
+ MOVLPSmr = 1344,
+ MOVLPSrm = 1345,
+ MOVLPSrr = 1346,
+ MOVLQ128mr = 1347,
+ MOVLSD2PDrr = 1348,
+ MOVLSS2PSrr = 1349,
+ MOVMSKPDrr = 1350,
+ MOVMSKPSrr = 1351,
+ MOVNTDQArm = 1352,
+ MOVNTDQmr = 1353,
+ MOVNTImr = 1354,
+ MOVNTPDmr = 1355,
+ MOVNTPSmr = 1356,
+ MOVPC32r = 1357,
+ MOVPD2SDmr = 1358,
+ MOVPD2SDrr = 1359,
+ MOVPDI2DImr = 1360,
+ MOVPDI2DIrr = 1361,
+ MOVPQI2QImr = 1362,
+ MOVPQIto64rr = 1363,
+ MOVPS2SSmr = 1364,
+ MOVPS2SSrr = 1365,
+ MOVQI2PQIrm = 1366,
+ MOVQxrxr = 1367,
+ MOVSD2PDrm = 1368,
+ MOVSD2PDrr = 1369,
+ MOVSDmr = 1370,
+ MOVSDrm = 1371,
+ MOVSDrr = 1372,
+ MOVSDto64mr = 1373,
+ MOVSDto64rr = 1374,
+ MOVSHDUPrm = 1375,
+ MOVSHDUPrr = 1376,
+ MOVSLDUPrm = 1377,
+ MOVSLDUPrr = 1378,
+ MOVSS2DImr = 1379,
+ MOVSS2DIrr = 1380,
+ MOVSS2PSrm = 1381,
+ MOVSS2PSrr = 1382,
+ MOVSSmr = 1383,
+ MOVSSrm = 1384,
+ MOVSSrr = 1385,
+ MOVSX16rm8 = 1386,
+ MOVSX16rm8W = 1387,
+ MOVSX16rr8 = 1388,
+ MOVSX16rr8W = 1389,
+ MOVSX32rm16 = 1390,
+ MOVSX32rm8 = 1391,
+ MOVSX32rr16 = 1392,
+ MOVSX32rr8 = 1393,
+ MOVSX64rm16 = 1394,
+ MOVSX64rm32 = 1395,
+ MOVSX64rm8 = 1396,
+ MOVSX64rr16 = 1397,
+ MOVSX64rr32 = 1398,
+ MOVSX64rr8 = 1399,
+ MOVUPDmr = 1400,
+ MOVUPDmr_Int = 1401,
+ MOVUPDrm = 1402,
+ MOVUPDrm_Int = 1403,
+ MOVUPDrr = 1404,
+ MOVUPSmr = 1405,
+ MOVUPSmr_Int = 1406,
+ MOVUPSrm = 1407,
+ MOVUPSrm_Int = 1408,
+ MOVUPSrr = 1409,
+ MOVZDI2PDIrm = 1410,
+ MOVZDI2PDIrr = 1411,
+ MOVZPQILo2PQIrm = 1412,
+ MOVZPQILo2PQIrr = 1413,
+ MOVZQI2PQIrm = 1414,
+ MOVZQI2PQIrr = 1415,
+ MOVZSD2PDrm = 1416,
+ MOVZSS2PSrm = 1417,
+ MOVZX16rm8 = 1418,
+ MOVZX16rm8W = 1419,
+ MOVZX16rr8 = 1420,
+ MOVZX16rr8W = 1421,
+ MOVZX32_NOREXrm8 = 1422,
+ MOVZX32_NOREXrr8 = 1423,
+ MOVZX32rm16 = 1424,
+ MOVZX32rm8 = 1425,
+ MOVZX32rr16 = 1426,
+ MOVZX32rr8 = 1427,
+ MOVZX64rm16 = 1428,
+ MOVZX64rm16_Q = 1429,
+ MOVZX64rm32 = 1430,
+ MOVZX64rm8 = 1431,
+ MOVZX64rm8_Q = 1432,
+ MOVZX64rr16 = 1433,
+ MOVZX64rr16_Q = 1434,
+ MOVZX64rr32 = 1435,
+ MOVZX64rr8 = 1436,
+ MOVZX64rr8_Q = 1437,
+ MOV_Fp3232 = 1438,
+ MOV_Fp3264 = 1439,
+ MOV_Fp3280 = 1440,
+ MOV_Fp6432 = 1441,
+ MOV_Fp6464 = 1442,
+ MOV_Fp6480 = 1443,
+ MOV_Fp8032 = 1444,
+ MOV_Fp8064 = 1445,
+ MOV_Fp8080 = 1446,
+ MPSADBWrmi = 1447,
+ MPSADBWrri = 1448,
+ MUL16m = 1449,
+ MUL16r = 1450,
+ MUL32m = 1451,
+ MUL32r = 1452,
+ MUL64m = 1453,
+ MUL64r = 1454,
+ MUL8m = 1455,
+ MUL8r = 1456,
+ MULPDrm = 1457,
+ MULPDrr = 1458,
+ MULPSrm = 1459,
+ MULPSrr = 1460,
+ MULSDrm = 1461,
+ MULSDrm_Int = 1462,
+ MULSDrr = 1463,
+ MULSDrr_Int = 1464,
+ MULSSrm = 1465,
+ MULSSrm_Int = 1466,
+ MULSSrr = 1467,
+ MULSSrr_Int = 1468,
+ MUL_F32m = 1469,
+ MUL_F64m = 1470,
+ MUL_FI16m = 1471,
+ MUL_FI32m = 1472,
+ MUL_FPrST0 = 1473,
+ MUL_FST0r = 1474,
+ MUL_Fp32 = 1475,
+ MUL_Fp32m = 1476,
+ MUL_Fp64 = 1477,
+ MUL_Fp64m = 1478,
+ MUL_Fp64m32 = 1479,
+ MUL_Fp80 = 1480,
+ MUL_Fp80m32 = 1481,
+ MUL_Fp80m64 = 1482,
+ MUL_FpI16m32 = 1483,
+ MUL_FpI16m64 = 1484,
+ MUL_FpI16m80 = 1485,
+ MUL_FpI32m32 = 1486,
+ MUL_FpI32m64 = 1487,
+ MUL_FpI32m80 = 1488,
+ MUL_FrST0 = 1489,
+ MWAIT = 1490,
+ NEG16m = 1491,
+ NEG16r = 1492,
+ NEG32m = 1493,
+ NEG32r = 1494,
+ NEG64m = 1495,
+ NEG64r = 1496,
+ NEG8m = 1497,
+ NEG8r = 1498,
+ NOOP = 1499,
+ NOOPL = 1500,
+ NOOPW = 1501,
+ NOT16m = 1502,
+ NOT16r = 1503,
+ NOT32m = 1504,
+ NOT32r = 1505,
+ NOT64m = 1506,
+ NOT64r = 1507,
+ NOT8m = 1508,
+ NOT8r = 1509,
+ OR16i16 = 1510,
+ OR16mi = 1511,
+ OR16mi8 = 1512,
+ OR16mr = 1513,
+ OR16ri = 1514,
+ OR16ri8 = 1515,
+ OR16rm = 1516,
+ OR16rr = 1517,
+ OR16rr_REV = 1518,
+ OR32i32 = 1519,
+ OR32mi = 1520,
+ OR32mi8 = 1521,
+ OR32mr = 1522,
+ OR32ri = 1523,
+ OR32ri8 = 1524,
+ OR32rm = 1525,
+ OR32rr = 1526,
+ OR32rr_REV = 1527,
+ OR64i32 = 1528,
+ OR64mi32 = 1529,
+ OR64mi8 = 1530,
+ OR64mr = 1531,
+ OR64ri32 = 1532,
+ OR64ri8 = 1533,
+ OR64rm = 1534,
+ OR64rr = 1535,
+ OR64rr_REV = 1536,
+ OR8i8 = 1537,
+ OR8mi = 1538,
+ OR8mr = 1539,
+ OR8ri = 1540,
+ OR8rm = 1541,
+ OR8rr = 1542,
+ OR8rr_REV = 1543,
+ ORPDrm = 1544,
+ ORPDrr = 1545,
+ ORPSrm = 1546,
+ ORPSrr = 1547,
+ OUT16ir = 1548,
+ OUT16rr = 1549,
+ OUT32ir = 1550,
+ OUT32rr = 1551,
+ OUT8ir = 1552,
+ OUT8rr = 1553,
+ OUTSB = 1554,
+ OUTSD = 1555,
+ OUTSW = 1556,
+ PABSBrm128 = 1557,
+ PABSBrm64 = 1558,
+ PABSBrr128 = 1559,
+ PABSBrr64 = 1560,
+ PABSDrm128 = 1561,
+ PABSDrm64 = 1562,
+ PABSDrr128 = 1563,
+ PABSDrr64 = 1564,
+ PABSWrm128 = 1565,
+ PABSWrm64 = 1566,
+ PABSWrr128 = 1567,
+ PABSWrr64 = 1568,
+ PACKSSDWrm = 1569,
+ PACKSSDWrr = 1570,
+ PACKSSWBrm = 1571,
+ PACKSSWBrr = 1572,
+ PACKUSDWrm = 1573,
+ PACKUSDWrr = 1574,
+ PACKUSWBrm = 1575,
+ PACKUSWBrr = 1576,
+ PADDBrm = 1577,
+ PADDBrr = 1578,
+ PADDDrm = 1579,
+ PADDDrr = 1580,
+ PADDQrm = 1581,
+ PADDQrr = 1582,
+ PADDSBrm = 1583,
+ PADDSBrr = 1584,
+ PADDSWrm = 1585,
+ PADDSWrr = 1586,
+ PADDUSBrm = 1587,
+ PADDUSBrr = 1588,
+ PADDUSWrm = 1589,
+ PADDUSWrr = 1590,
+ PADDWrm = 1591,
+ PADDWrr = 1592,
+ PALIGNR128rm = 1593,
+ PALIGNR128rr = 1594,
+ PALIGNR64rm = 1595,
+ PALIGNR64rr = 1596,
+ PANDNrm = 1597,
+ PANDNrr = 1598,
+ PANDrm = 1599,
+ PANDrr = 1600,
+ PAVGBrm = 1601,
+ PAVGBrr = 1602,
+ PAVGWrm = 1603,
+ PAVGWrr = 1604,
+ PBLENDVBrm0 = 1605,
+ PBLENDVBrr0 = 1606,
+ PBLENDWrmi = 1607,
+ PBLENDWrri = 1608,
+ PCMPEQBrm = 1609,
+ PCMPEQBrr = 1610,
+ PCMPEQDrm = 1611,
+ PCMPEQDrr = 1612,
+ PCMPEQQrm = 1613,
+ PCMPEQQrr = 1614,
+ PCMPEQWrm = 1615,
+ PCMPEQWrr = 1616,
+ PCMPESTRIArm = 1617,
+ PCMPESTRIArr = 1618,
+ PCMPESTRICrm = 1619,
+ PCMPESTRICrr = 1620,
+ PCMPESTRIOrm = 1621,
+ PCMPESTRIOrr = 1622,
+ PCMPESTRISrm = 1623,
+ PCMPESTRISrr = 1624,
+ PCMPESTRIZrm = 1625,
+ PCMPESTRIZrr = 1626,
+ PCMPESTRIrm = 1627,
+ PCMPESTRIrr = 1628,
+ PCMPESTRM128MEM = 1629,
+ PCMPESTRM128REG = 1630,
+ PCMPESTRM128rm = 1631,
+ PCMPESTRM128rr = 1632,
+ PCMPGTBrm = 1633,
+ PCMPGTBrr = 1634,
+ PCMPGTDrm = 1635,
+ PCMPGTDrr = 1636,
+ PCMPGTQrm = 1637,
+ PCMPGTQrr = 1638,
+ PCMPGTWrm = 1639,
+ PCMPGTWrr = 1640,
+ PCMPISTRIArm = 1641,
+ PCMPISTRIArr = 1642,
+ PCMPISTRICrm = 1643,
+ PCMPISTRICrr = 1644,
+ PCMPISTRIOrm = 1645,
+ PCMPISTRIOrr = 1646,
+ PCMPISTRISrm = 1647,
+ PCMPISTRISrr = 1648,
+ PCMPISTRIZrm = 1649,
+ PCMPISTRIZrr = 1650,
+ PCMPISTRIrm = 1651,
+ PCMPISTRIrr = 1652,
+ PCMPISTRM128MEM = 1653,
+ PCMPISTRM128REG = 1654,
+ PCMPISTRM128rm = 1655,
+ PCMPISTRM128rr = 1656,
+ PEXTRBmr = 1657,
+ PEXTRBrr = 1658,
+ PEXTRDmr = 1659,
+ PEXTRDrr = 1660,
+ PEXTRQmr = 1661,
+ PEXTRQrr = 1662,
+ PEXTRWmr = 1663,
+ PEXTRWri = 1664,
+ PHADDDrm128 = 1665,
+ PHADDDrm64 = 1666,
+ PHADDDrr128 = 1667,
+ PHADDDrr64 = 1668,
+ PHADDSWrm128 = 1669,
+ PHADDSWrm64 = 1670,
+ PHADDSWrr128 = 1671,
+ PHADDSWrr64 = 1672,
+ PHADDWrm128 = 1673,
+ PHADDWrm64 = 1674,
+ PHADDWrr128 = 1675,
+ PHADDWrr64 = 1676,
+ PHMINPOSUWrm128 = 1677,
+ PHMINPOSUWrr128 = 1678,
+ PHSUBDrm128 = 1679,
+ PHSUBDrm64 = 1680,
+ PHSUBDrr128 = 1681,
+ PHSUBDrr64 = 1682,
+ PHSUBSWrm128 = 1683,
+ PHSUBSWrm64 = 1684,
+ PHSUBSWrr128 = 1685,
+ PHSUBSWrr64 = 1686,
+ PHSUBWrm128 = 1687,
+ PHSUBWrm64 = 1688,
+ PHSUBWrr128 = 1689,
+ PHSUBWrr64 = 1690,
+ PINSRBrm = 1691,
+ PINSRBrr = 1692,
+ PINSRDrm = 1693,
+ PINSRDrr = 1694,
+ PINSRQrm = 1695,
+ PINSRQrr = 1696,
+ PINSRWrmi = 1697,
+ PINSRWrri = 1698,
+ PMADDUBSWrm128 = 1699,
+ PMADDUBSWrm64 = 1700,
+ PMADDUBSWrr128 = 1701,
+ PMADDUBSWrr64 = 1702,
+ PMADDWDrm = 1703,
+ PMADDWDrr = 1704,
+ PMAXSBrm = 1705,
+ PMAXSBrr = 1706,
+ PMAXSDrm = 1707,
+ PMAXSDrr = 1708,
+ PMAXSWrm = 1709,
+ PMAXSWrr = 1710,
+ PMAXUBrm = 1711,
+ PMAXUBrr = 1712,
+ PMAXUDrm = 1713,
+ PMAXUDrr = 1714,
+ PMAXUWrm = 1715,
+ PMAXUWrr = 1716,
+ PMINSBrm = 1717,
+ PMINSBrr = 1718,
+ PMINSDrm = 1719,
+ PMINSDrr = 1720,
+ PMINSWrm = 1721,
+ PMINSWrr = 1722,
+ PMINUBrm = 1723,
+ PMINUBrr = 1724,
+ PMINUDrm = 1725,
+ PMINUDrr = 1726,
+ PMINUWrm = 1727,
+ PMINUWrr = 1728,
+ PMOVMSKBrr = 1729,
+ PMOVSXBDrm = 1730,
+ PMOVSXBDrr = 1731,
+ PMOVSXBQrm = 1732,
+ PMOVSXBQrr = 1733,
+ PMOVSXBWrm = 1734,
+ PMOVSXBWrr = 1735,
+ PMOVSXDQrm = 1736,
+ PMOVSXDQrr = 1737,
+ PMOVSXWDrm = 1738,
+ PMOVSXWDrr = 1739,
+ PMOVSXWQrm = 1740,
+ PMOVSXWQrr = 1741,
+ PMOVZXBDrm = 1742,
+ PMOVZXBDrr = 1743,
+ PMOVZXBQrm = 1744,
+ PMOVZXBQrr = 1745,
+ PMOVZXBWrm = 1746,
+ PMOVZXBWrr = 1747,
+ PMOVZXDQrm = 1748,
+ PMOVZXDQrr = 1749,
+ PMOVZXWDrm = 1750,
+ PMOVZXWDrr = 1751,
+ PMOVZXWQrm = 1752,
+ PMOVZXWQrr = 1753,
+ PMULDQrm = 1754,
+ PMULDQrr = 1755,
+ PMULHRSWrm128 = 1756,
+ PMULHRSWrm64 = 1757,
+ PMULHRSWrr128 = 1758,
+ PMULHRSWrr64 = 1759,
+ PMULHUWrm = 1760,
+ PMULHUWrr = 1761,
+ PMULHWrm = 1762,
+ PMULHWrr = 1763,
+ PMULLDrm = 1764,
+ PMULLDrm_int = 1765,
+ PMULLDrr = 1766,
+ PMULLDrr_int = 1767,
+ PMULLWrm = 1768,
+ PMULLWrr = 1769,
+ PMULUDQrm = 1770,
+ PMULUDQrr = 1771,
+ POP16r = 1772,
+ POP16rmm = 1773,
+ POP16rmr = 1774,
+ POP32r = 1775,
+ POP32rmm = 1776,
+ POP32rmr = 1777,
+ POP64r = 1778,
+ POP64rmm = 1779,
+ POP64rmr = 1780,
+ POPCNT16rm = 1781,
+ POPCNT16rr = 1782,
+ POPCNT32rm = 1783,
+ POPCNT32rr = 1784,
+ POPCNT64rm = 1785,
+ POPCNT64rr = 1786,
+ POPF = 1787,
+ POPFD = 1788,
+ POPFQ = 1789,
+ POPFS16 = 1790,
+ POPFS32 = 1791,
+ POPFS64 = 1792,
+ POPGS16 = 1793,
+ POPGS32 = 1794,
+ POPGS64 = 1795,
+ PORrm = 1796,
+ PORrr = 1797,
+ PREFETCHNTA = 1798,
+ PREFETCHT0 = 1799,
+ PREFETCHT1 = 1800,
+ PREFETCHT2 = 1801,
+ PSADBWrm = 1802,
+ PSADBWrr = 1803,
+ PSHUFBrm128 = 1804,
+ PSHUFBrm64 = 1805,
+ PSHUFBrr128 = 1806,
+ PSHUFBrr64 = 1807,
+ PSHUFDmi = 1808,
+ PSHUFDri = 1809,
+ PSHUFHWmi = 1810,
+ PSHUFHWri = 1811,
+ PSHUFLWmi = 1812,
+ PSHUFLWri = 1813,
+ PSIGNBrm128 = 1814,
+ PSIGNBrm64 = 1815,
+ PSIGNBrr128 = 1816,
+ PSIGNBrr64 = 1817,
+ PSIGNDrm128 = 1818,
+ PSIGNDrm64 = 1819,
+ PSIGNDrr128 = 1820,
+ PSIGNDrr64 = 1821,
+ PSIGNWrm128 = 1822,
+ PSIGNWrm64 = 1823,
+ PSIGNWrr128 = 1824,
+ PSIGNWrr64 = 1825,
+ PSLLDQri = 1826,
+ PSLLDri = 1827,
+ PSLLDrm = 1828,
+ PSLLDrr = 1829,
+ PSLLQri = 1830,
+ PSLLQrm = 1831,
+ PSLLQrr = 1832,
+ PSLLWri = 1833,
+ PSLLWrm = 1834,
+ PSLLWrr = 1835,
+ PSRADri = 1836,
+ PSRADrm = 1837,
+ PSRADrr = 1838,
+ PSRAWri = 1839,
+ PSRAWrm = 1840,
+ PSRAWrr = 1841,
+ PSRLDQri = 1842,
+ PSRLDri = 1843,
+ PSRLDrm = 1844,
+ PSRLDrr = 1845,
+ PSRLQri = 1846,
+ PSRLQrm = 1847,
+ PSRLQrr = 1848,
+ PSRLWri = 1849,
+ PSRLWrm = 1850,
+ PSRLWrr = 1851,
+ PSUBBrm = 1852,
+ PSUBBrr = 1853,
+ PSUBDrm = 1854,
+ PSUBDrr = 1855,
+ PSUBQrm = 1856,
+ PSUBQrr = 1857,
+ PSUBSBrm = 1858,
+ PSUBSBrr = 1859,
+ PSUBSWrm = 1860,
+ PSUBSWrr = 1861,
+ PSUBUSBrm = 1862,
+ PSUBUSBrr = 1863,
+ PSUBUSWrm = 1864,
+ PSUBUSWrr = 1865,
+ PSUBWrm = 1866,
+ PSUBWrr = 1867,
+ PTESTrm = 1868,
+ PTESTrr = 1869,
+ PUNPCKHBWrm = 1870,
+ PUNPCKHBWrr = 1871,
+ PUNPCKHDQrm = 1872,
+ PUNPCKHDQrr = 1873,
+ PUNPCKHQDQrm = 1874,
+ PUNPCKHQDQrr = 1875,
+ PUNPCKHWDrm = 1876,
+ PUNPCKHWDrr = 1877,
+ PUNPCKLBWrm = 1878,
+ PUNPCKLBWrr = 1879,
+ PUNPCKLDQrm = 1880,
+ PUNPCKLDQrr = 1881,
+ PUNPCKLQDQrm = 1882,
+ PUNPCKLQDQrr = 1883,
+ PUNPCKLWDrm = 1884,
+ PUNPCKLWDrr = 1885,
+ PUSH16r = 1886,
+ PUSH16rmm = 1887,
+ PUSH16rmr = 1888,
+ PUSH32i16 = 1889,
+ PUSH32i32 = 1890,
+ PUSH32i8 = 1891,
+ PUSH32r = 1892,
+ PUSH32rmm = 1893,
+ PUSH32rmr = 1894,
+ PUSH64i16 = 1895,
+ PUSH64i32 = 1896,
+ PUSH64i8 = 1897,
+ PUSH64r = 1898,
+ PUSH64rmm = 1899,
+ PUSH64rmr = 1900,
+ PUSHF = 1901,
+ PUSHFD = 1902,
+ PUSHFQ64 = 1903,
+ PUSHFS16 = 1904,
+ PUSHFS32 = 1905,
+ PUSHFS64 = 1906,
+ PUSHGS16 = 1907,
+ PUSHGS32 = 1908,
+ PUSHGS64 = 1909,
+ PXORrm = 1910,
+ PXORrr = 1911,
+ RCL16m1 = 1912,
+ RCL16mCL = 1913,
+ RCL16mi = 1914,
+ RCL16r1 = 1915,
+ RCL16rCL = 1916,
+ RCL16ri = 1917,
+ RCL32m1 = 1918,
+ RCL32mCL = 1919,
+ RCL32mi = 1920,
+ RCL32r1 = 1921,
+ RCL32rCL = 1922,
+ RCL32ri = 1923,
+ RCL64m1 = 1924,
+ RCL64mCL = 1925,
+ RCL64mi = 1926,
+ RCL64r1 = 1927,
+ RCL64rCL = 1928,
+ RCL64ri = 1929,
+ RCL8m1 = 1930,
+ RCL8mCL = 1931,
+ RCL8mi = 1932,
+ RCL8r1 = 1933,
+ RCL8rCL = 1934,
+ RCL8ri = 1935,
+ RCPPSm = 1936,
+ RCPPSm_Int = 1937,
+ RCPPSr = 1938,
+ RCPPSr_Int = 1939,
+ RCPSSm = 1940,
+ RCPSSm_Int = 1941,
+ RCPSSr = 1942,
+ RCPSSr_Int = 1943,
+ RCR16m1 = 1944,
+ RCR16mCL = 1945,
+ RCR16mi = 1946,
+ RCR16r1 = 1947,
+ RCR16rCL = 1948,
+ RCR16ri = 1949,
+ RCR32m1 = 1950,
+ RCR32mCL = 1951,
+ RCR32mi = 1952,
+ RCR32r1 = 1953,
+ RCR32rCL = 1954,
+ RCR32ri = 1955,
+ RCR64m1 = 1956,
+ RCR64mCL = 1957,
+ RCR64mi = 1958,
+ RCR64r1 = 1959,
+ RCR64rCL = 1960,
+ RCR64ri = 1961,
+ RCR8m1 = 1962,
+ RCR8mCL = 1963,
+ RCR8mi = 1964,
+ RCR8r1 = 1965,
+ RCR8rCL = 1966,
+ RCR8ri = 1967,
+ RDMSR = 1968,
+ RDPMC = 1969,
+ RDTSC = 1970,
+ REP_MOVSB = 1971,
+ REP_MOVSD = 1972,
+ REP_MOVSQ = 1973,
+ REP_MOVSW = 1974,
+ REP_STOSB = 1975,
+ REP_STOSD = 1976,
+ REP_STOSQ = 1977,
+ REP_STOSW = 1978,
+ RET = 1979,
+ RETI = 1980,
+ ROL16m1 = 1981,
+ ROL16mCL = 1982,
+ ROL16mi = 1983,
+ ROL16r1 = 1984,
+ ROL16rCL = 1985,
+ ROL16ri = 1986,
+ ROL32m1 = 1987,
+ ROL32mCL = 1988,
+ ROL32mi = 1989,
+ ROL32r1 = 1990,
+ ROL32rCL = 1991,
+ ROL32ri = 1992,
+ ROL64m1 = 1993,
+ ROL64mCL = 1994,
+ ROL64mi = 1995,
+ ROL64r1 = 1996,
+ ROL64rCL = 1997,
+ ROL64ri = 1998,
+ ROL8m1 = 1999,
+ ROL8mCL = 2000,
+ ROL8mi = 2001,
+ ROL8r1 = 2002,
+ ROL8rCL = 2003,
+ ROL8ri = 2004,
+ ROR16m1 = 2005,
+ ROR16mCL = 2006,
+ ROR16mi = 2007,
+ ROR16r1 = 2008,
+ ROR16rCL = 2009,
+ ROR16ri = 2010,
+ ROR32m1 = 2011,
+ ROR32mCL = 2012,
+ ROR32mi = 2013,
+ ROR32r1 = 2014,
+ ROR32rCL = 2015,
+ ROR32ri = 2016,
+ ROR64m1 = 2017,
+ ROR64mCL = 2018,
+ ROR64mi = 2019,
+ ROR64r1 = 2020,
+ ROR64rCL = 2021,
+ ROR64ri = 2022,
+ ROR8m1 = 2023,
+ ROR8mCL = 2024,
+ ROR8mi = 2025,
+ ROR8r1 = 2026,
+ ROR8rCL = 2027,
+ ROR8ri = 2028,
+ ROUNDPDm_Int = 2029,
+ ROUNDPDr_Int = 2030,
+ ROUNDPSm_Int = 2031,
+ ROUNDPSr_Int = 2032,
+ ROUNDSDm_Int = 2033,
+ ROUNDSDr_Int = 2034,
+ ROUNDSSm_Int = 2035,
+ ROUNDSSr_Int = 2036,
+ RSM = 2037,
+ RSQRTPSm = 2038,
+ RSQRTPSm_Int = 2039,
+ RSQRTPSr = 2040,
+ RSQRTPSr_Int = 2041,
+ RSQRTSSm = 2042,
+ RSQRTSSm_Int = 2043,
+ RSQRTSSr = 2044,
+ RSQRTSSr_Int = 2045,
+ SAHF = 2046,
+ SAR16m1 = 2047,
+ SAR16mCL = 2048,
+ SAR16mi = 2049,
+ SAR16r1 = 2050,
+ SAR16rCL = 2051,
+ SAR16ri = 2052,
+ SAR32m1 = 2053,
+ SAR32mCL = 2054,
+ SAR32mi = 2055,
+ SAR32r1 = 2056,
+ SAR32rCL = 2057,
+ SAR32ri = 2058,
+ SAR64m1 = 2059,
+ SAR64mCL = 2060,
+ SAR64mi = 2061,
+ SAR64r1 = 2062,
+ SAR64rCL = 2063,
+ SAR64ri = 2064,
+ SAR8m1 = 2065,
+ SAR8mCL = 2066,
+ SAR8mi = 2067,
+ SAR8r1 = 2068,
+ SAR8rCL = 2069,
+ SAR8ri = 2070,
+ SBB16i16 = 2071,
+ SBB16mi = 2072,
+ SBB16mi8 = 2073,
+ SBB16mr = 2074,
+ SBB16ri = 2075,
+ SBB16ri8 = 2076,
+ SBB16rm = 2077,
+ SBB16rr = 2078,
+ SBB16rr_REV = 2079,
+ SBB32i32 = 2080,
+ SBB32mi = 2081,
+ SBB32mi8 = 2082,
+ SBB32mr = 2083,
+ SBB32ri = 2084,
+ SBB32ri8 = 2085,
+ SBB32rm = 2086,
+ SBB32rr = 2087,
+ SBB32rr_REV = 2088,
+ SBB64i32 = 2089,
+ SBB64mi32 = 2090,
+ SBB64mi8 = 2091,
+ SBB64mr = 2092,
+ SBB64ri32 = 2093,
+ SBB64ri8 = 2094,
+ SBB64rm = 2095,
+ SBB64rr = 2096,
+ SBB64rr_REV = 2097,
+ SBB8i8 = 2098,
+ SBB8mi = 2099,
+ SBB8mr = 2100,
+ SBB8ri = 2101,
+ SBB8rm = 2102,
+ SBB8rr = 2103,
+ SBB8rr_REV = 2104,
+ SCAS16 = 2105,
+ SCAS32 = 2106,
+ SCAS64 = 2107,
+ SCAS8 = 2108,
+ SETAEm = 2109,
+ SETAEr = 2110,
+ SETAm = 2111,
+ SETAr = 2112,
+ SETBEm = 2113,
+ SETBEr = 2114,
+ SETB_C16r = 2115,
+ SETB_C32r = 2116,
+ SETB_C64r = 2117,
+ SETB_C8r = 2118,
+ SETBm = 2119,
+ SETBr = 2120,
+ SETEm = 2121,
+ SETEr = 2122,
+ SETGEm = 2123,
+ SETGEr = 2124,
+ SETGm = 2125,
+ SETGr = 2126,
+ SETLEm = 2127,
+ SETLEr = 2128,
+ SETLm = 2129,
+ SETLr = 2130,
+ SETNEm = 2131,
+ SETNEr = 2132,
+ SETNOm = 2133,
+ SETNOr = 2134,
+ SETNPm = 2135,
+ SETNPr = 2136,
+ SETNSm = 2137,
+ SETNSr = 2138,
+ SETOm = 2139,
+ SETOr = 2140,
+ SETPm = 2141,
+ SETPr = 2142,
+ SETSm = 2143,
+ SETSr = 2144,
+ SFENCE = 2145,
+ SGDTm = 2146,
+ SHL16m1 = 2147,
+ SHL16mCL = 2148,
+ SHL16mi = 2149,
+ SHL16r1 = 2150,
+ SHL16rCL = 2151,
+ SHL16ri = 2152,
+ SHL32m1 = 2153,
+ SHL32mCL = 2154,
+ SHL32mi = 2155,
+ SHL32r1 = 2156,
+ SHL32rCL = 2157,
+ SHL32ri = 2158,
+ SHL64m1 = 2159,
+ SHL64mCL = 2160,
+ SHL64mi = 2161,
+ SHL64r1 = 2162,
+ SHL64rCL = 2163,
+ SHL64ri = 2164,
+ SHL8m1 = 2165,
+ SHL8mCL = 2166,
+ SHL8mi = 2167,
+ SHL8r1 = 2168,
+ SHL8rCL = 2169,
+ SHL8ri = 2170,
+ SHLD16mrCL = 2171,
+ SHLD16mri8 = 2172,
+ SHLD16rrCL = 2173,
+ SHLD16rri8 = 2174,
+ SHLD32mrCL = 2175,
+ SHLD32mri8 = 2176,
+ SHLD32rrCL = 2177,
+ SHLD32rri8 = 2178,
+ SHLD64mrCL = 2179,
+ SHLD64mri8 = 2180,
+ SHLD64rrCL = 2181,
+ SHLD64rri8 = 2182,
+ SHR16m1 = 2183,
+ SHR16mCL = 2184,
+ SHR16mi = 2185,
+ SHR16r1 = 2186,
+ SHR16rCL = 2187,
+ SHR16ri = 2188,
+ SHR32m1 = 2189,
+ SHR32mCL = 2190,
+ SHR32mi = 2191,
+ SHR32r1 = 2192,
+ SHR32rCL = 2193,
+ SHR32ri = 2194,
+ SHR64m1 = 2195,
+ SHR64mCL = 2196,
+ SHR64mi = 2197,
+ SHR64r1 = 2198,
+ SHR64rCL = 2199,
+ SHR64ri = 2200,
+ SHR8m1 = 2201,
+ SHR8mCL = 2202,
+ SHR8mi = 2203,
+ SHR8r1 = 2204,
+ SHR8rCL = 2205,
+ SHR8ri = 2206,
+ SHRD16mrCL = 2207,
+ SHRD16mri8 = 2208,
+ SHRD16rrCL = 2209,
+ SHRD16rri8 = 2210,
+ SHRD32mrCL = 2211,
+ SHRD32mri8 = 2212,
+ SHRD32rrCL = 2213,
+ SHRD32rri8 = 2214,
+ SHRD64mrCL = 2215,
+ SHRD64mri8 = 2216,
+ SHRD64rrCL = 2217,
+ SHRD64rri8 = 2218,
+ SHUFPDrmi = 2219,
+ SHUFPDrri = 2220,
+ SHUFPSrmi = 2221,
+ SHUFPSrri = 2222,
+ SIDTm = 2223,
+ SIN_F = 2224,
+ SIN_Fp32 = 2225,
+ SIN_Fp64 = 2226,
+ SIN_Fp80 = 2227,
+ SLDT16m = 2228,
+ SLDT16r = 2229,
+ SLDT64m = 2230,
+ SLDT64r = 2231,
+ SMSW16m = 2232,
+ SMSW16r = 2233,
+ SMSW32r = 2234,
+ SMSW64r = 2235,
+ SQRTPDm = 2236,
+ SQRTPDm_Int = 2237,
+ SQRTPDr = 2238,
+ SQRTPDr_Int = 2239,
+ SQRTPSm = 2240,
+ SQRTPSm_Int = 2241,
+ SQRTPSr = 2242,
+ SQRTPSr_Int = 2243,
+ SQRTSDm = 2244,
+ SQRTSDm_Int = 2245,
+ SQRTSDr = 2246,
+ SQRTSDr_Int = 2247,
+ SQRTSSm = 2248,
+ SQRTSSm_Int = 2249,
+ SQRTSSr = 2250,
+ SQRTSSr_Int = 2251,
+ SQRT_F = 2252,
+ SQRT_Fp32 = 2253,
+ SQRT_Fp64 = 2254,
+ SQRT_Fp80 = 2255,
+ STC = 2256,
+ STD = 2257,
+ STI = 2258,
+ STMXCSR = 2259,
+ STRm = 2260,
+ STRr = 2261,
+ ST_F32m = 2262,
+ ST_F64m = 2263,
+ ST_FP32m = 2264,
+ ST_FP64m = 2265,
+ ST_FP80m = 2266,
+ ST_FPrr = 2267,
+ ST_Fp32m = 2268,
+ ST_Fp64m = 2269,
+ ST_Fp64m32 = 2270,
+ ST_Fp80m32 = 2271,
+ ST_Fp80m64 = 2272,
+ ST_FpP32m = 2273,
+ ST_FpP64m = 2274,
+ ST_FpP64m32 = 2275,
+ ST_FpP80m = 2276,
+ ST_FpP80m32 = 2277,
+ ST_FpP80m64 = 2278,
+ ST_Frr = 2279,
+ SUB16i16 = 2280,
+ SUB16mi = 2281,
+ SUB16mi8 = 2282,
+ SUB16mr = 2283,
+ SUB16ri = 2284,
+ SUB16ri8 = 2285,
+ SUB16rm = 2286,
+ SUB16rr = 2287,
+ SUB16rr_REV = 2288,
+ SUB32i32 = 2289,
+ SUB32mi = 2290,
+ SUB32mi8 = 2291,
+ SUB32mr = 2292,
+ SUB32ri = 2293,
+ SUB32ri8 = 2294,
+ SUB32rm = 2295,
+ SUB32rr = 2296,
+ SUB32rr_REV = 2297,
+ SUB64i32 = 2298,
+ SUB64mi32 = 2299,
+ SUB64mi8 = 2300,
+ SUB64mr = 2301,
+ SUB64ri32 = 2302,
+ SUB64ri8 = 2303,
+ SUB64rm = 2304,
+ SUB64rr = 2305,
+ SUB64rr_REV = 2306,
+ SUB8i8 = 2307,
+ SUB8mi = 2308,
+ SUB8mr = 2309,
+ SUB8ri = 2310,
+ SUB8rm = 2311,
+ SUB8rr = 2312,
+ SUB8rr_REV = 2313,
+ SUBPDrm = 2314,
+ SUBPDrr = 2315,
+ SUBPSrm = 2316,
+ SUBPSrr = 2317,
+ SUBR_F32m = 2318,
+ SUBR_F64m = 2319,
+ SUBR_FI16m = 2320,
+ SUBR_FI32m = 2321,
+ SUBR_FPrST0 = 2322,
+ SUBR_FST0r = 2323,
+ SUBR_Fp32m = 2324,
+ SUBR_Fp64m = 2325,
+ SUBR_Fp64m32 = 2326,
+ SUBR_Fp80m32 = 2327,
+ SUBR_Fp80m64 = 2328,
+ SUBR_FpI16m32 = 2329,
+ SUBR_FpI16m64 = 2330,
+ SUBR_FpI16m80 = 2331,
+ SUBR_FpI32m32 = 2332,
+ SUBR_FpI32m64 = 2333,
+ SUBR_FpI32m80 = 2334,
+ SUBR_FrST0 = 2335,
+ SUBSDrm = 2336,
+ SUBSDrm_Int = 2337,
+ SUBSDrr = 2338,
+ SUBSDrr_Int = 2339,
+ SUBSSrm = 2340,
+ SUBSSrm_Int = 2341,
+ SUBSSrr = 2342,
+ SUBSSrr_Int = 2343,
+ SUB_F32m = 2344,
+ SUB_F64m = 2345,
+ SUB_FI16m = 2346,
+ SUB_FI32m = 2347,
+ SUB_FPrST0 = 2348,
+ SUB_FST0r = 2349,
+ SUB_Fp32 = 2350,
+ SUB_Fp32m = 2351,
+ SUB_Fp64 = 2352,
+ SUB_Fp64m = 2353,
+ SUB_Fp64m32 = 2354,
+ SUB_Fp80 = 2355,
+ SUB_Fp80m32 = 2356,
+ SUB_Fp80m64 = 2357,
+ SUB_FpI16m32 = 2358,
+ SUB_FpI16m64 = 2359,
+ SUB_FpI16m80 = 2360,
+ SUB_FpI32m32 = 2361,
+ SUB_FpI32m64 = 2362,
+ SUB_FpI32m80 = 2363,
+ SUB_FrST0 = 2364,
+ SWPGS = 2365,
+ SYSCALL = 2366,
+ SYSENTER = 2367,
+ SYSEXIT = 2368,
+ SYSEXIT64 = 2369,
+ SYSRET = 2370,
+ TAILJMPd = 2371,
+ TAILJMPm = 2372,
+ TAILJMPr = 2373,
+ TAILJMPr64 = 2374,
+ TCRETURNdi = 2375,
+ TCRETURNdi64 = 2376,
+ TCRETURNri = 2377,
+ TCRETURNri64 = 2378,
+ TEST16i16 = 2379,
+ TEST16mi = 2380,
+ TEST16ri = 2381,
+ TEST16rm = 2382,
+ TEST16rr = 2383,
+ TEST32i32 = 2384,
+ TEST32mi = 2385,
+ TEST32ri = 2386,
+ TEST32rm = 2387,
+ TEST32rr = 2388,
+ TEST64i32 = 2389,
+ TEST64mi32 = 2390,
+ TEST64ri32 = 2391,
+ TEST64rm = 2392,
+ TEST64rr = 2393,
+ TEST8i8 = 2394,
+ TEST8mi = 2395,
+ TEST8ri = 2396,
+ TEST8rm = 2397,
+ TEST8rr = 2398,
+ TLS_addr32 = 2399,
+ TLS_addr64 = 2400,
+ TRAP = 2401,
+ TST_F = 2402,
+ TST_Fp32 = 2403,
+ TST_Fp64 = 2404,
+ TST_Fp80 = 2405,
+ UCOMISDrm = 2406,
+ UCOMISDrr = 2407,
+ UCOMISSrm = 2408,
+ UCOMISSrr = 2409,
+ UCOM_FIPr = 2410,
+ UCOM_FIr = 2411,
+ UCOM_FPPr = 2412,
+ UCOM_FPr = 2413,
+ UCOM_FpIr32 = 2414,
+ UCOM_FpIr64 = 2415,
+ UCOM_FpIr80 = 2416,
+ UCOM_Fpr32 = 2417,
+ UCOM_Fpr64 = 2418,
+ UCOM_Fpr80 = 2419,
+ UCOM_Fr = 2420,
+ UNPCKHPDrm = 2421,
+ UNPCKHPDrr = 2422,
+ UNPCKHPSrm = 2423,
+ UNPCKHPSrr = 2424,
+ UNPCKLPDrm = 2425,
+ UNPCKLPDrr = 2426,
+ UNPCKLPSrm = 2427,
+ UNPCKLPSrr = 2428,
+ VASTART_SAVE_XMM_REGS = 2429,
+ VERRm = 2430,
+ VERRr = 2431,
+ VERWm = 2432,
+ VERWr = 2433,
+ VMCALL = 2434,
+ VMCLEARm = 2435,
+ VMLAUNCH = 2436,
+ VMPTRLDm = 2437,
+ VMPTRSTm = 2438,
+ VMREAD32rm = 2439,
+ VMREAD32rr = 2440,
+ VMREAD64rm = 2441,
+ VMREAD64rr = 2442,
+ VMRESUME = 2443,
+ VMWRITE32rm = 2444,
+ VMWRITE32rr = 2445,
+ VMWRITE64rm = 2446,
+ VMWRITE64rr = 2447,
+ VMXOFF = 2448,
+ VMXON = 2449,
+ V_SET0 = 2450,
+ V_SETALLONES = 2451,
+ WAIT = 2452,
+ WBINVD = 2453,
+ WINCALL64m = 2454,
+ WINCALL64pcrel32 = 2455,
+ WINCALL64r = 2456,
+ WRMSR = 2457,
+ XADD16rm = 2458,
+ XADD16rr = 2459,
+ XADD32rm = 2460,
+ XADD32rr = 2461,
+ XADD64rm = 2462,
+ XADD64rr = 2463,
+ XADD8rm = 2464,
+ XADD8rr = 2465,
+ XCHG16ar = 2466,
+ XCHG16rm = 2467,
+ XCHG16rr = 2468,
+ XCHG32ar = 2469,
+ XCHG32rm = 2470,
+ XCHG32rr = 2471,
+ XCHG64ar = 2472,
+ XCHG64rm = 2473,
+ XCHG64rr = 2474,
+ XCHG8rm = 2475,
+ XCHG8rr = 2476,
+ XCH_F = 2477,
+ XLAT = 2478,
+ XOR16i16 = 2479,
+ XOR16mi = 2480,
+ XOR16mi8 = 2481,
+ XOR16mr = 2482,
+ XOR16ri = 2483,
+ XOR16ri8 = 2484,
+ XOR16rm = 2485,
+ XOR16rr = 2486,
+ XOR16rr_REV = 2487,
+ XOR32i32 = 2488,
+ XOR32mi = 2489,
+ XOR32mi8 = 2490,
+ XOR32mr = 2491,
+ XOR32ri = 2492,
+ XOR32ri8 = 2493,
+ XOR32rm = 2494,
+ XOR32rr = 2495,
+ XOR32rr_REV = 2496,
+ XOR64i32 = 2497,
+ XOR64mi32 = 2498,
+ XOR64mi8 = 2499,
+ XOR64mr = 2500,
+ XOR64ri32 = 2501,
+ XOR64ri8 = 2502,
+ XOR64rm = 2503,
+ XOR64rr = 2504,
+ XOR64rr_REV = 2505,
+ XOR8i8 = 2506,
+ XOR8mi = 2507,
+ XOR8mr = 2508,
+ XOR8ri = 2509,
+ XOR8rm = 2510,
+ XOR8rr = 2511,
+ XOR8rr_REV = 2512,
+ XORPDrm = 2513,
+ XORPDrr = 2514,
+ XORPSrm = 2515,
+ XORPSrr = 2516,
+ INSTRUCTION_LIST_END = 2517
};
}
} // End llvm namespace
diff --git a/libclamav/c++/X86GenSubtarget.inc b/libclamav/c++/X86GenSubtarget.inc
index 270465a..dbafd0c 100644
--- a/libclamav/c++/X86GenSubtarget.inc
+++ b/libclamav/c++/X86GenSubtarget.inc
@@ -30,7 +30,8 @@ enum {
FeatureSSE42 = 1 << 12,
FeatureSSE4A = 1 << 13,
FeatureSSSE3 = 1 << 14,
- FeatureSlowBTMem = 1 << 15
+ FeatureSlowBTMem = 1 << 15,
+ FeatureVectorUAMem = 1 << 16
};
// Sorted (by key) array of values for CPU features.
@@ -50,7 +51,8 @@ static const llvm::SubtargetFeatureKV FeatureKV[] = {
{ "sse41", "Enable SSE 4.1 instructions", FeatureSSE41, FeatureSSSE3 },
{ "sse42", "Enable SSE 4.2 instructions", FeatureSSE42, FeatureSSE41 },
{ "sse4a", "Support SSE 4a instructions", FeatureSSE4A, 0 },
- { "ssse3", "Enable SSSE3 instructions", FeatureSSSE3, FeatureSSE3 }
+ { "ssse3", "Enable SSSE3 instructions", FeatureSSSE3, FeatureSSE3 },
+ { "vector-unaligned-mem", "Allow unaligned memory operands on vector/SIMD instructions", FeatureVectorUAMem, 0 }
};
enum {
@@ -119,8 +121,8 @@ enum {
// subtarget options.
std::string llvm::X86Subtarget::ParseSubtargetFeatures(const std::string &FS,
const std::string &CPU) {
- DEBUG(errs() << "\nFeatures:" << FS);
- DEBUG(errs() << "\nCPU:" << CPU);
+ DEBUG(dbgs() << "\nFeatures:" << FS);
+ DEBUG(dbgs() << "\nCPU:" << CPU);
SubtargetFeatures Features(FS);
Features.setCPUIfNone(CPU);
uint32_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize,
@@ -141,5 +143,6 @@ std::string llvm::X86Subtarget::ParseSubtargetFeatures(const std::string &FS,
if ((Bits & FeatureSSE4A) != 0) HasSSE4A = true;
if ((Bits & FeatureSSSE3) != 0 && X86SSELevel < SSSE3) X86SSELevel = SSSE3;
if ((Bits & FeatureSlowBTMem) != 0) IsBTMemSlow = true;
+ if ((Bits & FeatureVectorUAMem) != 0) HasVectorUAMem = true;
return Features.getCPU();
}
diff --git a/libclamav/c++/llvm/include/llvm/Intrinsics.gen b/libclamav/c++/llvm/include/llvm/Intrinsics.gen
index cd1c589..a5dc144 100644
--- a/libclamav/c++/llvm/include/llvm/Intrinsics.gen
+++ b/libclamav/c++/llvm/include/llvm/Intrinsics.gen
@@ -160,10 +160,6 @@
ctpop, // llvm.ctpop
cttz, // llvm.cttz
dbg_declare, // llvm.dbg.declare
- dbg_func_start, // llvm.dbg.func.start
- dbg_region_end, // llvm.dbg.region.end
- dbg_region_start, // llvm.dbg.region.start
- dbg_stoppoint, // llvm.dbg.stoppoint
dbg_value, // llvm.dbg.value
eh_dwarf_cfa, // llvm.eh.dwarf.cfa
eh_exception, // llvm.eh.exception
@@ -924,10 +920,6 @@
"llvm.ctpop",
"llvm.cttz",
"llvm.dbg.declare",
- "llvm.dbg.func.start",
- "llvm.dbg.region.end",
- "llvm.dbg.region.start",
- "llvm.dbg.stoppoint",
"llvm.dbg.value",
"llvm.eh.dwarf.cfa",
"llvm.eh.exception",
@@ -1699,10 +1691,6 @@
false,
false,
false,
- false,
- false,
- false,
- false,
true,
true,
false,
@@ -2461,10 +2449,6 @@
break;
case 'd':
if (Len == 16 && !memcmp(Name, "llvm.dbg.declare", 16)) return Intrinsic::dbg_declare;
- if (Len == 19 && !memcmp(Name, "llvm.dbg.func.start", 19)) return Intrinsic::dbg_func_start;
- if (Len == 19 && !memcmp(Name, "llvm.dbg.region.end", 19)) return Intrinsic::dbg_region_end;
- if (Len == 21 && !memcmp(Name, "llvm.dbg.region.start", 21)) return Intrinsic::dbg_region_start;
- if (Len == 18 && !memcmp(Name, "llvm.dbg.stoppoint", 18)) return Intrinsic::dbg_stoppoint;
if (Len == 14 && !memcmp(Name, "llvm.dbg.value", 14)) return Intrinsic::dbg_value;
break;
case 'e':
@@ -4187,9 +4171,6 @@
case Intrinsic::invariant_end: // llvm.invariant.end
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::isVoid, MVT::iPTR, MVT::i64, MVT::iPTR);
break;
- case Intrinsic::dbg_declare: // llvm.dbg.declare
- VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::iPTR, MVT::Metadata);
- break;
case Intrinsic::memory_barrier: // llvm.memory.barrier
VerifyIntrinsicPrototype(ID, IF, 1, 5, MVT::isVoid, MVT::i1, MVT::i1, MVT::i1, MVT::i1, MVT::i1);
break;
@@ -4200,9 +4181,6 @@
case Intrinsic::x86_sse3_mwait: // llvm.x86.sse3.mwait
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::i32, MVT::i32);
break;
- case Intrinsic::dbg_stoppoint: // llvm.dbg.stoppoint
- VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::isVoid, MVT::i32, MVT::i32, MVT::Metadata);
- break;
case Intrinsic::eh_return_i32: // llvm.eh.return.i32
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::i32, MVT::iPTR);
break;
@@ -4211,14 +4189,12 @@
case Intrinsic::lifetime_start: // llvm.lifetime.start
VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::i64, MVT::iPTR);
break;
- case Intrinsic::dbg_func_start: // llvm.dbg.func.start
- case Intrinsic::dbg_region_end: // llvm.dbg.region.end
- case Intrinsic::dbg_region_start: // llvm.dbg.region.start
- VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::isVoid, MVT::Metadata);
- break;
case Intrinsic::dbg_value: // llvm.dbg.value
VerifyIntrinsicPrototype(ID, IF, 1, 3, MVT::isVoid, MVT::Metadata, MVT::i64, MVT::Metadata);
break;
+ case Intrinsic::dbg_declare: // llvm.dbg.declare
+ VerifyIntrinsicPrototype(ID, IF, 1, 2, MVT::isVoid, MVT::Metadata, MVT::Metadata);
+ break;
case Intrinsic::eh_sjlj_longjmp: // llvm.eh.sjlj.longjmp
case Intrinsic::ppc_dcba: // llvm.ppc.dcba
case Intrinsic::ppc_dcbf: // llvm.ppc.dcbf
@@ -5811,11 +5787,6 @@
ArgTys.push_back(IntegerType::get(Context, 64));
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
break;
- case Intrinsic::dbg_declare: // llvm.dbg.declare
- ResultTy = Type::getVoidTy(Context);
- ArgTys.push_back(PointerType::getUnqual(StructType::get(Context)));
- ArgTys.push_back(Type::getMetadataTy(Context));
- break;
case Intrinsic::memory_barrier: // llvm.memory.barrier
ResultTy = Type::getVoidTy(Context);
ArgTys.push_back(IntegerType::get(Context, 1));
@@ -5834,12 +5805,6 @@
ArgTys.push_back(IntegerType::get(Context, 32));
ArgTys.push_back(IntegerType::get(Context, 32));
break;
- case Intrinsic::dbg_stoppoint: // llvm.dbg.stoppoint
- ResultTy = Type::getVoidTy(Context);
- ArgTys.push_back(IntegerType::get(Context, 32));
- ArgTys.push_back(IntegerType::get(Context, 32));
- ArgTys.push_back(Type::getMetadataTy(Context));
- break;
case Intrinsic::eh_return_i32: // llvm.eh.return.i32
ResultTy = Type::getVoidTy(Context);
ArgTys.push_back(IntegerType::get(Context, 32));
@@ -5852,16 +5817,15 @@
ArgTys.push_back(IntegerType::get(Context, 64));
ArgTys.push_back(PointerType::getUnqual(IntegerType::get(Context, 8)));
break;
- case Intrinsic::dbg_func_start: // llvm.dbg.func.start
- case Intrinsic::dbg_region_end: // llvm.dbg.region.end
- case Intrinsic::dbg_region_start: // llvm.dbg.region.start
+ case Intrinsic::dbg_value: // llvm.dbg.value
ResultTy = Type::getVoidTy(Context);
ArgTys.push_back(Type::getMetadataTy(Context));
+ ArgTys.push_back(IntegerType::get(Context, 64));
+ ArgTys.push_back(Type::getMetadataTy(Context));
break;
- case Intrinsic::dbg_value: // llvm.dbg.value
+ case Intrinsic::dbg_declare: // llvm.dbg.declare
ResultTy = Type::getVoidTy(Context);
ArgTys.push_back(Type::getMetadataTy(Context));
- ArgTys.push_back(IntegerType::get(Context, 64));
ArgTys.push_back(Type::getMetadataTy(Context));
break;
case Intrinsic::eh_sjlj_longjmp: // llvm.eh.sjlj.longjmp
@@ -6182,10 +6146,6 @@ AttrListPtr Intrinsic::getAttributes(ID id) { // No intrinsic can throw excepti
case Intrinsic::ctpop:
case Intrinsic::cttz:
case Intrinsic::dbg_declare:
- case Intrinsic::dbg_func_start:
- case Intrinsic::dbg_region_end:
- case Intrinsic::dbg_region_start:
- case Intrinsic::dbg_stoppoint:
case Intrinsic::dbg_value:
case Intrinsic::eh_sjlj_longjmp:
case Intrinsic::eh_sjlj_lsda:
@@ -6826,7 +6786,7 @@ AttrListPtr Intrinsic::getAttributes(ID id) { // No intrinsic can throw excepti
// Determine intrinsic alias analysis mod/ref behavior.
#ifdef GET_INTRINSIC_MODREF_BEHAVIOR
-switch (id) {
+switch (iid) {
default:
return UnknownModRefBehavior;
case Intrinsic::alpha_umulh:
@@ -7113,14 +7073,6 @@ case Intrinsic::cttz:
return DoesNotAccessMemory;
case Intrinsic::dbg_declare:
return DoesNotAccessMemory;
-case Intrinsic::dbg_func_start:
- return DoesNotAccessMemory;
-case Intrinsic::dbg_region_end:
- return DoesNotAccessMemory;
-case Intrinsic::dbg_region_start:
- return DoesNotAccessMemory;
-case Intrinsic::dbg_stoppoint:
- return DoesNotAccessMemory;
case Intrinsic::dbg_value:
return DoesNotAccessMemory;
case Intrinsic::eh_exception:
diff --git a/libclamav/c++/strip-llvm.sh b/libclamav/c++/strip-llvm.sh
index f369128..92f0244 100755
--- a/libclamav/c++/strip-llvm.sh
+++ b/libclamav/c++/strip-llvm.sh
@@ -22,7 +22,8 @@ for i in llvm/bindings/ llvm/examples/ llvm/projects/ llvm/runtime/\
llvm/tools/llvm-bcanalyzer llvm/tools/llvm-db\
llvm/tools/llvm-extract llvm/tools/llvm-ld llvm/tools/llvm-link llvm/tools/llvm-mc\
llvm/tools/llvm-nm llvm/tools/llvm-prof llvm/tools/llvm-ranlib\
- llvm/tools/llvm-stub llvm/tools/lto llvm/tools/opt
+ llvm/tools/llvm-stub llvm/tools/lto llvm/tools/opt llvm/lib/MC/MCParser\
+ llvm/tools/llvm-dis/Makefile
do
git rm -rf $i;
done
--
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